Capstone / SX1276Lib_modtronix

SX1276 library for modtronix inair9. Edited for use with NRF51DK board.

Dependents:   InAir9_PingPong

Fork of SX1276Lib_modtronix by modtronix H

sx1276/sx1276.cpp@18:cdb08d710838, 2015-03-03 (annotated)

Committer:
modtronix
Date:
Tue Mar 03 23:28:08 2015 +0000
Revision:
18:cdb08d710838
Parent:
16:0927c093fd82
Child:
19:ef26bd64cb67
Added SX1276LibConfig.h for library configuration

Who changed what in which revision?

UserRevisionLine numberNew contents of line
GregCr 0:e6ceb13d2d05 1 /*
GregCr 0:e6ceb13d2d05 2 / _____) _ | |
GregCr 0:e6ceb13d2d05 3 ( (____ _____ ____ _| |_ _____ ____| |__
GregCr 0:e6ceb13d2d05 4 \____ \| ___ | (_ _) ___ |/ ___) _ \
GregCr 0:e6ceb13d2d05 5 _____) ) ____| | | || |_| ____( (___| | | |
GregCr 0:e6ceb13d2d05 6 (______/|_____)_|_|_| \__)_____)\____)_| |_|
GregCr 8:0fe3e0e8007b 7 ( C )2014 Semtech
GregCr 0:e6ceb13d2d05 8
GregCr 0:e6ceb13d2d05 9 Description: Actual implementation of a SX1276 radio, inherits Radio
GregCr 0:e6ceb13d2d05 10
GregCr 0:e6ceb13d2d05 11 License: Revised BSD License, see LICENSE.TXT file include in the project
GregCr 0:e6ceb13d2d05 12
GregCr 0:e6ceb13d2d05 13 Maintainers: Miguel Luis, Gregory Cristian and Nicolas Huguenin
GregCr 0:e6ceb13d2d05 14 */
GregCr 0:e6ceb13d2d05 15 #include "sx1276.h"
GregCr 0:e6ceb13d2d05 16
GregCr 0:e6ceb13d2d05 17 const FskBandwidth_t SX1276::FskBandwidths[] =
GregCr 0:e6ceb13d2d05 18 {
GregCr 0:e6ceb13d2d05 19 { 2600 , 0x17 },
GregCr 0:e6ceb13d2d05 20 { 3100 , 0x0F },
GregCr 0:e6ceb13d2d05 21 { 3900 , 0x07 },
GregCr 0:e6ceb13d2d05 22 { 5200 , 0x16 },
GregCr 0:e6ceb13d2d05 23 { 6300 , 0x0E },
GregCr 0:e6ceb13d2d05 24 { 7800 , 0x06 },
GregCr 0:e6ceb13d2d05 25 { 10400 , 0x15 },
GregCr 0:e6ceb13d2d05 26 { 12500 , 0x0D },
GregCr 0:e6ceb13d2d05 27 { 15600 , 0x05 },
GregCr 0:e6ceb13d2d05 28 { 20800 , 0x14 },
GregCr 0:e6ceb13d2d05 29 { 25000 , 0x0C },
GregCr 0:e6ceb13d2d05 30 { 31300 , 0x04 },
GregCr 0:e6ceb13d2d05 31 { 41700 , 0x13 },
GregCr 0:e6ceb13d2d05 32 { 50000 , 0x0B },
GregCr 0:e6ceb13d2d05 33 { 62500 , 0x03 },
GregCr 0:e6ceb13d2d05 34 { 83333 , 0x12 },
GregCr 0:e6ceb13d2d05 35 { 100000, 0x0A },
GregCr 0:e6ceb13d2d05 36 { 125000, 0x02 },
GregCr 0:e6ceb13d2d05 37 { 166700, 0x11 },
GregCr 0:e6ceb13d2d05 38 { 200000, 0x09 },
mluis 15:04374b1c33fa 39 { 250000, 0x01 },
mluis 15:04374b1c33fa 40 { 0, 0x00 }, // Invalid Badwidth
GregCr 0:e6ceb13d2d05 41 };
GregCr 0:e6ceb13d2d05 42
GregCr 0:e6ceb13d2d05 43
GregCr 7:2b555111463f 44 SX1276::SX1276( void ( *txDone )( ), void ( *txTimeout ) ( ), void ( *rxDone ) ( uint8_t *payload, uint16_t size, int16_t rssi, int8_t snr ),
mluis 13:618826a997e2 45 void ( *rxTimeout ) ( ), void ( *rxError ) ( ), void ( *fhssChangeChannel ) ( uint8_t channelIndex ), void ( *cadDone ) ( bool channelActivityDetected ),
mluis 13:618826a997e2 46 PinName mosi, PinName miso, PinName sclk, PinName nss, PinName reset,
GregCr 0:e6ceb13d2d05 47 PinName dio0, PinName dio1, PinName dio2, PinName dio3, PinName dio4, PinName dio5 )
mluis 13:618826a997e2 48 : Radio( txDone, txTimeout, rxDone, rxTimeout, rxError, fhssChangeChannel, cadDone ),
mluis 13:618826a997e2 49 spi( mosi, miso, sclk ),
mluis 13:618826a997e2 50 nss( nss ),
mluis 13:618826a997e2 51 reset( reset ),
mluis 13:618826a997e2 52 dio0( dio0 ), dio1( dio1 ), dio2( dio2 ), dio3( dio3 ), dio4( dio4 ), dio5( dio5 ),
mluis 13:618826a997e2 53 isRadioActive( false )
GregCr 0:e6ceb13d2d05 54 {
mluis 13:618826a997e2 55 wait_ms( 10 );
mluis 13:618826a997e2 56 this->rxTx = 0;
mluis 13:618826a997e2 57 this->rxBuffer = new uint8_t[RX_BUFFER_SIZE];
mluis 13:618826a997e2 58 previousOpMode = RF_OPMODE_STANDBY;
mluis 13:618826a997e2 59
mluis 13:618826a997e2 60 this->dioIrq = new DioIrqHandler[6];
GregCr 0:e6ceb13d2d05 61
mluis 13:618826a997e2 62 this->dioIrq[0] = &SX1276::OnDio0Irq;
mluis 13:618826a997e2 63 this->dioIrq[1] = &SX1276::OnDio1Irq;
mluis 13:618826a997e2 64 this->dioIrq[2] = &SX1276::OnDio2Irq;
modtronix 18:cdb08d710838 65 //For SHD3I with inAir9 in imod3, on FRDM-KL25Z board. It uses A4 on FRDM-KL25Z board, which does not have interrupt
modtronix 18:cdb08d710838 66 #if( defined ( TARGET_KL25Z ) && defined(SHIELD_SHD3I_INAIR9) )
modtronix 18:cdb08d710838 67 this->dioIrq[3] = NULL;
modtronix 18:cdb08d710838 68 #else
mluis 13:618826a997e2 69 this->dioIrq[3] = &SX1276::OnDio3Irq;
modtronix 18:cdb08d710838 70 #endif
mluis 13:618826a997e2 71 this->dioIrq[4] = &SX1276::OnDio4Irq;
mluis 13:618826a997e2 72 this->dioIrq[5] = NULL;
mluis 13:618826a997e2 73
mluis 13:618826a997e2 74 this->settings.State = IDLE;
GregCr 0:e6ceb13d2d05 75 }
GregCr 0:e6ceb13d2d05 76
GregCr 0:e6ceb13d2d05 77 SX1276::~SX1276( )
GregCr 0:e6ceb13d2d05 78 {
mluis 13:618826a997e2 79 delete this->rxBuffer;
mluis 13:618826a997e2 80 delete this->dioIrq;
GregCr 0:e6ceb13d2d05 81 }
GregCr 0:e6ceb13d2d05 82
GregCr 0:e6ceb13d2d05 83 void SX1276::RxChainCalibration( void )
GregCr 0:e6ceb13d2d05 84 {
GregCr 0:e6ceb13d2d05 85 uint8_t regPaConfigInitVal;
GregCr 0:e6ceb13d2d05 86 uint32_t initialFreq;
GregCr 0:e6ceb13d2d05 87
GregCr 0:e6ceb13d2d05 88 // Save context
GregCr 0:e6ceb13d2d05 89 regPaConfigInitVal = this->Read( REG_PACONFIG );
GregCr 0:e6ceb13d2d05 90 initialFreq = ( double )( ( ( uint32_t )this->Read( REG_FRFMSB ) << 16 ) |
GregCr 0:e6ceb13d2d05 91 ( ( uint32_t )this->Read( REG_FRFMID ) << 8 ) |
GregCr 0:e6ceb13d2d05 92 ( ( uint32_t )this->Read( REG_FRFLSB ) ) ) * ( double )FREQ_STEP;
GregCr 0:e6ceb13d2d05 93
GregCr 0:e6ceb13d2d05 94 // Cut the PA just in case, RFO output, power = -1 dBm
GregCr 0:e6ceb13d2d05 95 this->Write( REG_PACONFIG, 0x00 );
GregCr 0:e6ceb13d2d05 96
GregCr 0:e6ceb13d2d05 97 // Launch Rx chain calibration for LF band
GregCr 0:e6ceb13d2d05 98 Write ( REG_IMAGECAL, ( Read( REG_IMAGECAL ) & RF_IMAGECAL_IMAGECAL_MASK ) | RF_IMAGECAL_IMAGECAL_START );
GregCr 0:e6ceb13d2d05 99 while( ( Read( REG_IMAGECAL ) & RF_IMAGECAL_IMAGECAL_RUNNING ) == RF_IMAGECAL_IMAGECAL_RUNNING )
GregCr 0:e6ceb13d2d05 100 {
GregCr 0:e6ceb13d2d05 101 }
GregCr 0:e6ceb13d2d05 102
GregCr 0:e6ceb13d2d05 103 // Sets a Frequency in HF band
GregCr 0:e6ceb13d2d05 104 settings.Channel= 868000000 ;
GregCr 0:e6ceb13d2d05 105
GregCr 0:e6ceb13d2d05 106 // Launch Rx chain calibration for HF band
GregCr 0:e6ceb13d2d05 107 Write ( REG_IMAGECAL, ( Read( REG_IMAGECAL ) & RF_IMAGECAL_IMAGECAL_MASK ) | RF_IMAGECAL_IMAGECAL_START );
GregCr 0:e6ceb13d2d05 108 while( ( Read( REG_IMAGECAL ) & RF_IMAGECAL_IMAGECAL_RUNNING ) == RF_IMAGECAL_IMAGECAL_RUNNING )
GregCr 0:e6ceb13d2d05 109 {
GregCr 0:e6ceb13d2d05 110 }
GregCr 0:e6ceb13d2d05 111
GregCr 0:e6ceb13d2d05 112 // Restore context
GregCr 0:e6ceb13d2d05 113 this->Write( REG_PACONFIG, regPaConfigInitVal );
GregCr 0:e6ceb13d2d05 114 SetChannel( initialFreq );
GregCr 0:e6ceb13d2d05 115 }
GregCr 0:e6ceb13d2d05 116
GregCr 0:e6ceb13d2d05 117 RadioState SX1276::GetState( void )
GregCr 0:e6ceb13d2d05 118 {
GregCr 0:e6ceb13d2d05 119 return this->settings.State;
GregCr 0:e6ceb13d2d05 120 }
GregCr 0:e6ceb13d2d05 121
GregCr 0:e6ceb13d2d05 122 void SX1276::SetChannel( uint32_t freq )
GregCr 0:e6ceb13d2d05 123 {
GregCr 0:e6ceb13d2d05 124 this->settings.Channel = freq;
GregCr 0:e6ceb13d2d05 125 freq = ( uint32_t )( ( double )freq / ( double )FREQ_STEP );
GregCr 0:e6ceb13d2d05 126 Write( REG_FRFMSB, ( uint8_t )( ( freq >> 16 ) & 0xFF ) );
GregCr 0:e6ceb13d2d05 127 Write( REG_FRFMID, ( uint8_t )( ( freq >> 8 ) & 0xFF ) );
GregCr 0:e6ceb13d2d05 128 Write( REG_FRFLSB, ( uint8_t )( freq & 0xFF ) );
GregCr 0:e6ceb13d2d05 129 }
GregCr 0:e6ceb13d2d05 130
GregCr 0:e6ceb13d2d05 131 bool SX1276::IsChannelFree( ModemType modem, uint32_t freq, int8_t rssiThresh )
GregCr 0:e6ceb13d2d05 132 {
GregCr 7:2b555111463f 133 int16_t rssi = 0;
GregCr 0:e6ceb13d2d05 134
GregCr 0:e6ceb13d2d05 135 SetModem( modem );
GregCr 0:e6ceb13d2d05 136
GregCr 0:e6ceb13d2d05 137 SetChannel( freq );
GregCr 0:e6ceb13d2d05 138
GregCr 0:e6ceb13d2d05 139 SetOpMode( RF_OPMODE_RECEIVER );
GregCr 0:e6ceb13d2d05 140
GregCr 4:f0ce52e94d3f 141 wait_ms( 1 );
GregCr 0:e6ceb13d2d05 142
GregCr 0:e6ceb13d2d05 143 rssi = GetRssi( modem );
GregCr 0:e6ceb13d2d05 144
GregCr 0:e6ceb13d2d05 145 Sleep( );
GregCr 0:e6ceb13d2d05 146
GregCr 7:2b555111463f 147 if( rssi > ( int16_t )rssiThresh )
GregCr 0:e6ceb13d2d05 148 {
GregCr 0:e6ceb13d2d05 149 return false;
GregCr 0:e6ceb13d2d05 150 }
GregCr 0:e6ceb13d2d05 151 return true;
GregCr 0:e6ceb13d2d05 152 }
GregCr 0:e6ceb13d2d05 153
GregCr 0:e6ceb13d2d05 154 uint32_t SX1276::Random( void )
GregCr 0:e6ceb13d2d05 155 {
GregCr 0:e6ceb13d2d05 156 uint8_t i;
GregCr 0:e6ceb13d2d05 157 uint32_t rnd = 0;
GregCr 0:e6ceb13d2d05 158
GregCr 0:e6ceb13d2d05 159 /*
GregCr 0:e6ceb13d2d05 160 * Radio setup for random number generation
GregCr 0:e6ceb13d2d05 161 */
GregCr 0:e6ceb13d2d05 162 // Set LoRa modem ON
GregCr 0:e6ceb13d2d05 163 SetModem( MODEM_LORA );
GregCr 0:e6ceb13d2d05 164
GregCr 0:e6ceb13d2d05 165 // Disable LoRa modem interrupts
GregCr 0:e6ceb13d2d05 166 Write( REG_LR_IRQFLAGSMASK, RFLR_IRQFLAGS_RXTIMEOUT |
GregCr 0:e6ceb13d2d05 167 RFLR_IRQFLAGS_RXDONE |
GregCr 0:e6ceb13d2d05 168 RFLR_IRQFLAGS_PAYLOADCRCERROR |
GregCr 0:e6ceb13d2d05 169 RFLR_IRQFLAGS_VALIDHEADER |
GregCr 0:e6ceb13d2d05 170 RFLR_IRQFLAGS_TXDONE |
GregCr 0:e6ceb13d2d05 171 RFLR_IRQFLAGS_CADDONE |
GregCr 0:e6ceb13d2d05 172 RFLR_IRQFLAGS_FHSSCHANGEDCHANNEL |
GregCr 0:e6ceb13d2d05 173 RFLR_IRQFLAGS_CADDETECTED );
GregCr 0:e6ceb13d2d05 174
GregCr 0:e6ceb13d2d05 175 // Set radio in continuous reception
GregCr 0:e6ceb13d2d05 176 SetOpMode( RF_OPMODE_RECEIVER );
GregCr 0:e6ceb13d2d05 177
GregCr 0:e6ceb13d2d05 178 for( i = 0; i < 32; i++ )
GregCr 0:e6ceb13d2d05 179 {
GregCr 4:f0ce52e94d3f 180 wait_ms( 1 );
GregCr 0:e6ceb13d2d05 181 // Unfiltered RSSI value reading. Only takes the LSB value
GregCr 0:e6ceb13d2d05 182 rnd |= ( ( uint32_t )Read( REG_LR_RSSIWIDEBAND ) & 0x01 ) << i;
GregCr 0:e6ceb13d2d05 183 }
GregCr 0:e6ceb13d2d05 184
GregCr 0:e6ceb13d2d05 185 Sleep( );
GregCr 0:e6ceb13d2d05 186
GregCr 0:e6ceb13d2d05 187 return rnd;
GregCr 0:e6ceb13d2d05 188 }
GregCr 0:e6ceb13d2d05 189
GregCr 0:e6ceb13d2d05 190 /*!
GregCr 0:e6ceb13d2d05 191 * Returns the known FSK bandwidth registers value
GregCr 0:e6ceb13d2d05 192 *
GregCr 0:e6ceb13d2d05 193 * \param [IN] bandwidth Bandwidth value in Hz
GregCr 0:e6ceb13d2d05 194 * \retval regValue Bandwidth register value.
GregCr 0:e6ceb13d2d05 195 */
GregCr 0:e6ceb13d2d05 196 uint8_t SX1276::GetFskBandwidthRegValue( uint32_t bandwidth )
GregCr 0:e6ceb13d2d05 197 {
GregCr 0:e6ceb13d2d05 198 uint8_t i;
GregCr 0:e6ceb13d2d05 199
GregCr 0:e6ceb13d2d05 200 for( i = 0; i < ( sizeof( FskBandwidths ) / sizeof( FskBandwidth_t ) ) - 1; i++ )
GregCr 0:e6ceb13d2d05 201 {
GregCr 0:e6ceb13d2d05 202 if( ( bandwidth >= FskBandwidths[i].bandwidth ) && ( bandwidth < FskBandwidths[i + 1].bandwidth ) )
GregCr 0:e6ceb13d2d05 203 {
GregCr 0:e6ceb13d2d05 204 return FskBandwidths[i].RegValue;
GregCr 0:e6ceb13d2d05 205 }
GregCr 0:e6ceb13d2d05 206 }
GregCr 0:e6ceb13d2d05 207 // ERROR: Value not found
GregCr 0:e6ceb13d2d05 208 while( 1 );
GregCr 0:e6ceb13d2d05 209 }
GregCr 0:e6ceb13d2d05 210
GregCr 0:e6ceb13d2d05 211 void SX1276::SetRxConfig( ModemType modem, uint32_t bandwidth,
GregCr 0:e6ceb13d2d05 212 uint32_t datarate, uint8_t coderate,
GregCr 0:e6ceb13d2d05 213 uint32_t bandwidthAfc, uint16_t preambleLen,
GregCr 0:e6ceb13d2d05 214 uint16_t symbTimeout, bool fixLen,
mluis 13:618826a997e2 215 uint8_t payloadLen,
mluis 13:618826a997e2 216 bool crcOn, bool freqHopOn, uint8_t hopPeriod,
GregCr 6:e7f02929cd3d 217 bool iqInverted, bool rxContinuous )
GregCr 0:e6ceb13d2d05 218 {
GregCr 0:e6ceb13d2d05 219 SetModem( modem );
GregCr 0:e6ceb13d2d05 220
GregCr 0:e6ceb13d2d05 221 switch( modem )
GregCr 0:e6ceb13d2d05 222 {
GregCr 0:e6ceb13d2d05 223 case MODEM_FSK:
GregCr 0:e6ceb13d2d05 224 {
GregCr 0:e6ceb13d2d05 225 this->settings.Fsk.Bandwidth = bandwidth;
GregCr 0:e6ceb13d2d05 226 this->settings.Fsk.Datarate = datarate;
GregCr 0:e6ceb13d2d05 227 this->settings.Fsk.BandwidthAfc = bandwidthAfc;
GregCr 0:e6ceb13d2d05 228 this->settings.Fsk.FixLen = fixLen;
mluis 13:618826a997e2 229 this->settings.Fsk.PayloadLen = payloadLen;
GregCr 0:e6ceb13d2d05 230 this->settings.Fsk.CrcOn = crcOn;
GregCr 0:e6ceb13d2d05 231 this->settings.Fsk.IqInverted = iqInverted;
GregCr 0:e6ceb13d2d05 232 this->settings.Fsk.RxContinuous = rxContinuous;
GregCr 0:e6ceb13d2d05 233 this->settings.Fsk.PreambleLen = preambleLen;
GregCr 0:e6ceb13d2d05 234
GregCr 0:e6ceb13d2d05 235 datarate = ( uint16_t )( ( double )XTAL_FREQ / ( double )datarate );
GregCr 0:e6ceb13d2d05 236 Write( REG_BITRATEMSB, ( uint8_t )( datarate >> 8 ) );
GregCr 0:e6ceb13d2d05 237 Write( REG_BITRATELSB, ( uint8_t )( datarate & 0xFF ) );
GregCr 0:e6ceb13d2d05 238
GregCr 0:e6ceb13d2d05 239 Write( REG_RXBW, GetFskBandwidthRegValue( bandwidth ) );
GregCr 0:e6ceb13d2d05 240 Write( REG_AFCBW, GetFskBandwidthRegValue( bandwidthAfc ) );
GregCr 0:e6ceb13d2d05 241
mluis 14:8552d0b840be 242 Write( REG_PREAMBLEMSB, ( uint8_t )( ( preambleLen >> 8 ) & 0xFF ) );
mluis 14:8552d0b840be 243 Write( REG_PREAMBLELSB, ( uint8_t )( preambleLen & 0xFF ) );
GregCr 0:e6ceb13d2d05 244
GregCr 0:e6ceb13d2d05 245 Write( REG_PACKETCONFIG1,
GregCr 0:e6ceb13d2d05 246 ( Read( REG_PACKETCONFIG1 ) &
GregCr 0:e6ceb13d2d05 247 RF_PACKETCONFIG1_CRC_MASK &
GregCr 0:e6ceb13d2d05 248 RF_PACKETCONFIG1_PACKETFORMAT_MASK ) |
GregCr 0:e6ceb13d2d05 249 ( ( fixLen == 1 ) ? RF_PACKETCONFIG1_PACKETFORMAT_FIXED : RF_PACKETCONFIG1_PACKETFORMAT_VARIABLE ) |
GregCr 0:e6ceb13d2d05 250 ( crcOn << 4 ) );
mluis 13:618826a997e2 251 if( fixLen == 1 )
mluis 13:618826a997e2 252 {
mluis 13:618826a997e2 253 Write( REG_PAYLOADLENGTH, payloadLen );
mluis 13:618826a997e2 254 }
GregCr 0:e6ceb13d2d05 255 }
GregCr 0:e6ceb13d2d05 256 break;
GregCr 0:e6ceb13d2d05 257 case MODEM_LORA:
GregCr 0:e6ceb13d2d05 258 {
modtronix 16:0927c093fd82 259 if( bandwidth > 9 )
GregCr 0:e6ceb13d2d05 260 {
modtronix 16:0927c093fd82 261 // Fatal error: Bandwidth must be 0-9 (7.8 - 500khz)
GregCr 0:e6ceb13d2d05 262 while( 1 );
GregCr 0:e6ceb13d2d05 263 }
modtronix 16:0927c093fd82 264 //bandwidth += 7; //Changed bandwidth from 0-2 to 0-10
GregCr 0:e6ceb13d2d05 265 this->settings.LoRa.Bandwidth = bandwidth;
GregCr 0:e6ceb13d2d05 266 this->settings.LoRa.Datarate = datarate;
GregCr 0:e6ceb13d2d05 267 this->settings.LoRa.Coderate = coderate;
GregCr 0:e6ceb13d2d05 268 this->settings.LoRa.FixLen = fixLen;
mluis 13:618826a997e2 269 this->settings.LoRa.PayloadLen = payloadLen;
GregCr 0:e6ceb13d2d05 270 this->settings.LoRa.CrcOn = crcOn;
mluis 13:618826a997e2 271 this->settings.LoRa.FreqHopOn = freqHopOn;
mluis 13:618826a997e2 272 this->settings.LoRa.HopPeriod = hopPeriod;
GregCr 0:e6ceb13d2d05 273 this->settings.LoRa.IqInverted = iqInverted;
GregCr 0:e6ceb13d2d05 274 this->settings.LoRa.RxContinuous = rxContinuous;
mluis 13:618826a997e2 275
GregCr 0:e6ceb13d2d05 276 if( datarate > 12 )
GregCr 0:e6ceb13d2d05 277 {
GregCr 0:e6ceb13d2d05 278 datarate = 12;
GregCr 0:e6ceb13d2d05 279 }
GregCr 0:e6ceb13d2d05 280 else if( datarate < 6 )
GregCr 0:e6ceb13d2d05 281 {
GregCr 0:e6ceb13d2d05 282 datarate = 6;
GregCr 0:e6ceb13d2d05 283 }
GregCr 0:e6ceb13d2d05 284
modtronix 16:0927c093fd82 285 //bandwidth 7=125, 8=250, 9=500, datarate=SF
GregCr 0:e6ceb13d2d05 286 if( ( ( bandwidth == 7 ) && ( ( datarate == 11 ) || ( datarate == 12 ) ) ) ||
GregCr 0:e6ceb13d2d05 287 ( ( bandwidth == 8 ) && ( datarate == 12 ) ) )
GregCr 0:e6ceb13d2d05 288 {
GregCr 0:e6ceb13d2d05 289 this->settings.LoRa.LowDatarateOptimize = 0x01;
GregCr 0:e6ceb13d2d05 290 }
GregCr 0:e6ceb13d2d05 291 else
GregCr 0:e6ceb13d2d05 292 {
GregCr 0:e6ceb13d2d05 293 this->settings.LoRa.LowDatarateOptimize = 0x00;
GregCr 0:e6ceb13d2d05 294 }
GregCr 0:e6ceb13d2d05 295
GregCr 0:e6ceb13d2d05 296 Write( REG_LR_MODEMCONFIG1,
GregCr 0:e6ceb13d2d05 297 ( Read( REG_LR_MODEMCONFIG1 ) &
GregCr 0:e6ceb13d2d05 298 RFLR_MODEMCONFIG1_BW_MASK &
GregCr 0:e6ceb13d2d05 299 RFLR_MODEMCONFIG1_CODINGRATE_MASK &
GregCr 0:e6ceb13d2d05 300 RFLR_MODEMCONFIG1_IMPLICITHEADER_MASK ) |
GregCr 0:e6ceb13d2d05 301 ( bandwidth << 4 ) | ( coderate << 1 ) |
GregCr 0:e6ceb13d2d05 302 fixLen );
GregCr 0:e6ceb13d2d05 303
GregCr 0:e6ceb13d2d05 304 Write( REG_LR_MODEMCONFIG2,
GregCr 0:e6ceb13d2d05 305 ( Read( REG_LR_MODEMCONFIG2 ) &
GregCr 0:e6ceb13d2d05 306 RFLR_MODEMCONFIG2_SF_MASK &
GregCr 0:e6ceb13d2d05 307 RFLR_MODEMCONFIG2_RXPAYLOADCRC_MASK &
GregCr 0:e6ceb13d2d05 308 RFLR_MODEMCONFIG2_SYMBTIMEOUTMSB_MASK ) |
GregCr 0:e6ceb13d2d05 309 ( datarate << 4 ) | ( crcOn << 2 ) |
GregCr 0:e6ceb13d2d05 310 ( ( symbTimeout >> 8 ) & ~RFLR_MODEMCONFIG2_SYMBTIMEOUTMSB_MASK ) );
GregCr 0:e6ceb13d2d05 311
GregCr 0:e6ceb13d2d05 312 Write( REG_LR_MODEMCONFIG3,
GregCr 0:e6ceb13d2d05 313 ( Read( REG_LR_MODEMCONFIG3 ) &
GregCr 0:e6ceb13d2d05 314 RFLR_MODEMCONFIG3_LOWDATARATEOPTIMIZE_MASK ) |
GregCr 0:e6ceb13d2d05 315 ( this->settings.LoRa.LowDatarateOptimize << 3 ) );
GregCr 0:e6ceb13d2d05 316
GregCr 0:e6ceb13d2d05 317 Write( REG_LR_SYMBTIMEOUTLSB, ( uint8_t )( symbTimeout & 0xFF ) );
GregCr 0:e6ceb13d2d05 318
GregCr 0:e6ceb13d2d05 319 Write( REG_LR_PREAMBLEMSB, ( uint8_t )( ( preambleLen >> 8 ) & 0xFF ) );
GregCr 0:e6ceb13d2d05 320 Write( REG_LR_PREAMBLELSB, ( uint8_t )( preambleLen & 0xFF ) );
GregCr 0:e6ceb13d2d05 321
mluis 13:618826a997e2 322 if( fixLen == 1 )
mluis 13:618826a997e2 323 {
mluis 13:618826a997e2 324 Write( REG_LR_PAYLOADLENGTH, payloadLen );
mluis 13:618826a997e2 325 }
mluis 13:618826a997e2 326
GregCr 6:e7f02929cd3d 327 if( this->settings.LoRa.FreqHopOn == true )
GregCr 6:e7f02929cd3d 328 {
GregCr 6:e7f02929cd3d 329 Write( REG_LR_PLLHOP, ( Read( REG_LR_PLLHOP ) & RFLR_PLLHOP_FASTHOP_MASK ) | RFLR_PLLHOP_FASTHOP_ON );
GregCr 6:e7f02929cd3d 330 Write( REG_LR_HOPPERIOD, this->settings.LoRa.HopPeriod );
GregCr 6:e7f02929cd3d 331 }
GregCr 6:e7f02929cd3d 332
GregCr 0:e6ceb13d2d05 333 if( datarate == 6 )
GregCr 0:e6ceb13d2d05 334 {
GregCr 0:e6ceb13d2d05 335 Write( REG_LR_DETECTOPTIMIZE,
GregCr 0:e6ceb13d2d05 336 ( Read( REG_LR_DETECTOPTIMIZE ) &
GregCr 0:e6ceb13d2d05 337 RFLR_DETECTIONOPTIMIZE_MASK ) |
GregCr 0:e6ceb13d2d05 338 RFLR_DETECTIONOPTIMIZE_SF6 );
GregCr 0:e6ceb13d2d05 339 Write( REG_LR_DETECTIONTHRESHOLD,
GregCr 0:e6ceb13d2d05 340 RFLR_DETECTIONTHRESH_SF6 );
GregCr 0:e6ceb13d2d05 341 }
GregCr 0:e6ceb13d2d05 342 else
GregCr 0:e6ceb13d2d05 343 {
GregCr 0:e6ceb13d2d05 344 Write( REG_LR_DETECTOPTIMIZE,
GregCr 0:e6ceb13d2d05 345 ( Read( REG_LR_DETECTOPTIMIZE ) &
GregCr 0:e6ceb13d2d05 346 RFLR_DETECTIONOPTIMIZE_MASK ) |
GregCr 0:e6ceb13d2d05 347 RFLR_DETECTIONOPTIMIZE_SF7_TO_SF12 );
GregCr 0:e6ceb13d2d05 348 Write( REG_LR_DETECTIONTHRESHOLD,
GregCr 0:e6ceb13d2d05 349 RFLR_DETECTIONTHRESH_SF7_TO_SF12 );
GregCr 0:e6ceb13d2d05 350 }
GregCr 0:e6ceb13d2d05 351 }
GregCr 0:e6ceb13d2d05 352 break;
GregCr 0:e6ceb13d2d05 353 }
GregCr 0:e6ceb13d2d05 354 }
GregCr 0:e6ceb13d2d05 355
GregCr 0:e6ceb13d2d05 356 void SX1276::SetTxConfig( ModemType modem, int8_t power, uint32_t fdev,
GregCr 0:e6ceb13d2d05 357 uint32_t bandwidth, uint32_t datarate,
GregCr 0:e6ceb13d2d05 358 uint8_t coderate, uint16_t preambleLen,
mluis 13:618826a997e2 359 bool fixLen, bool crcOn, bool freqHopOn,
mluis 13:618826a997e2 360 uint8_t hopPeriod, bool iqInverted, uint32_t timeout )
GregCr 0:e6ceb13d2d05 361 {
GregCr 0:e6ceb13d2d05 362 uint8_t paConfig = 0;
GregCr 0:e6ceb13d2d05 363 uint8_t paDac = 0;
GregCr 0:e6ceb13d2d05 364
GregCr 0:e6ceb13d2d05 365 SetModem( modem );
GregCr 0:e6ceb13d2d05 366
GregCr 0:e6ceb13d2d05 367 paConfig = Read( REG_PACONFIG );
GregCr 0:e6ceb13d2d05 368 paDac = Read( REG_PADAC );
GregCr 0:e6ceb13d2d05 369
GregCr 0:e6ceb13d2d05 370 paConfig = ( paConfig & RF_PACONFIG_PASELECT_MASK ) | GetPaSelect( this->settings.Channel );
GregCr 0:e6ceb13d2d05 371 paConfig = ( paConfig & RF_PACONFIG_MAX_POWER_MASK ) | 0x70;
GregCr 0:e6ceb13d2d05 372
GregCr 0:e6ceb13d2d05 373 if( ( paConfig & RF_PACONFIG_PASELECT_PABOOST ) == RF_PACONFIG_PASELECT_PABOOST )
GregCr 0:e6ceb13d2d05 374 {
GregCr 0:e6ceb13d2d05 375 if( power > 17 )
GregCr 0:e6ceb13d2d05 376 {
GregCr 0:e6ceb13d2d05 377 paDac = ( paDac & RF_PADAC_20DBM_MASK ) | RF_PADAC_20DBM_ON;
GregCr 0:e6ceb13d2d05 378 }
GregCr 0:e6ceb13d2d05 379 else
GregCr 0:e6ceb13d2d05 380 {
GregCr 0:e6ceb13d2d05 381 paDac = ( paDac & RF_PADAC_20DBM_MASK ) | RF_PADAC_20DBM_OFF;
GregCr 0:e6ceb13d2d05 382 }
GregCr 0:e6ceb13d2d05 383 if( ( paDac & RF_PADAC_20DBM_ON ) == RF_PADAC_20DBM_ON )
GregCr 0:e6ceb13d2d05 384 {
GregCr 0:e6ceb13d2d05 385 if( power < 5 )
GregCr 0:e6ceb13d2d05 386 {
GregCr 0:e6ceb13d2d05 387 power = 5;
GregCr 0:e6ceb13d2d05 388 }
GregCr 0:e6ceb13d2d05 389 if( power > 20 )
GregCr 0:e6ceb13d2d05 390 {
GregCr 0:e6ceb13d2d05 391 power = 20;
GregCr 0:e6ceb13d2d05 392 }
GregCr 0:e6ceb13d2d05 393 paConfig = ( paConfig & RF_PACONFIG_OUTPUTPOWER_MASK ) | ( uint8_t )( ( uint16_t )( power - 5 ) & 0x0F );
GregCr 0:e6ceb13d2d05 394 }
GregCr 0:e6ceb13d2d05 395 else
GregCr 0:e6ceb13d2d05 396 {
GregCr 0:e6ceb13d2d05 397 if( power < 2 )
GregCr 0:e6ceb13d2d05 398 {
GregCr 0:e6ceb13d2d05 399 power = 2;
GregCr 0:e6ceb13d2d05 400 }
GregCr 0:e6ceb13d2d05 401 if( power > 17 )
GregCr 0:e6ceb13d2d05 402 {
GregCr 0:e6ceb13d2d05 403 power = 17;
GregCr 0:e6ceb13d2d05 404 }
GregCr 0:e6ceb13d2d05 405 paConfig = ( paConfig & RF_PACONFIG_OUTPUTPOWER_MASK ) | ( uint8_t )( ( uint16_t )( power - 2 ) & 0x0F );
GregCr 0:e6ceb13d2d05 406 }
GregCr 0:e6ceb13d2d05 407 }
GregCr 0:e6ceb13d2d05 408 else
GregCr 0:e6ceb13d2d05 409 {
GregCr 0:e6ceb13d2d05 410 if( power < -1 )
GregCr 0:e6ceb13d2d05 411 {
GregCr 0:e6ceb13d2d05 412 power = -1;
GregCr 0:e6ceb13d2d05 413 }
GregCr 0:e6ceb13d2d05 414 if( power > 14 )
GregCr 0:e6ceb13d2d05 415 {
GregCr 0:e6ceb13d2d05 416 power = 14;
GregCr 0:e6ceb13d2d05 417 }
GregCr 0:e6ceb13d2d05 418 paConfig = ( paConfig & RF_PACONFIG_OUTPUTPOWER_MASK ) | ( uint8_t )( ( uint16_t )( power + 1 ) & 0x0F );
GregCr 0:e6ceb13d2d05 419 }
GregCr 0:e6ceb13d2d05 420 Write( REG_PACONFIG, paConfig );
GregCr 0:e6ceb13d2d05 421 Write( REG_PADAC, paDac );
GregCr 0:e6ceb13d2d05 422
GregCr 0:e6ceb13d2d05 423 switch( modem )
GregCr 0:e6ceb13d2d05 424 {
GregCr 0:e6ceb13d2d05 425 case MODEM_FSK:
GregCr 0:e6ceb13d2d05 426 {
GregCr 0:e6ceb13d2d05 427 this->settings.Fsk.Power = power;
GregCr 0:e6ceb13d2d05 428 this->settings.Fsk.Fdev = fdev;
GregCr 0:e6ceb13d2d05 429 this->settings.Fsk.Bandwidth = bandwidth;
GregCr 0:e6ceb13d2d05 430 this->settings.Fsk.Datarate = datarate;
GregCr 0:e6ceb13d2d05 431 this->settings.Fsk.PreambleLen = preambleLen;
GregCr 0:e6ceb13d2d05 432 this->settings.Fsk.FixLen = fixLen;
GregCr 0:e6ceb13d2d05 433 this->settings.Fsk.CrcOn = crcOn;
GregCr 0:e6ceb13d2d05 434 this->settings.Fsk.IqInverted = iqInverted;
GregCr 0:e6ceb13d2d05 435 this->settings.Fsk.TxTimeout = timeout;
GregCr 0:e6ceb13d2d05 436
GregCr 0:e6ceb13d2d05 437 fdev = ( uint16_t )( ( double )fdev / ( double )FREQ_STEP );
GregCr 0:e6ceb13d2d05 438 Write( REG_FDEVMSB, ( uint8_t )( fdev >> 8 ) );
GregCr 0:e6ceb13d2d05 439 Write( REG_FDEVLSB, ( uint8_t )( fdev & 0xFF ) );
GregCr 0:e6ceb13d2d05 440
GregCr 0:e6ceb13d2d05 441 datarate = ( uint16_t )( ( double )XTAL_FREQ / ( double )datarate );
GregCr 0:e6ceb13d2d05 442 Write( REG_BITRATEMSB, ( uint8_t )( datarate >> 8 ) );
GregCr 0:e6ceb13d2d05 443 Write( REG_BITRATELSB, ( uint8_t )( datarate & 0xFF ) );
GregCr 0:e6ceb13d2d05 444
GregCr 0:e6ceb13d2d05 445 Write( REG_PREAMBLEMSB, ( preambleLen >> 8 ) & 0x00FF );
GregCr 0:e6ceb13d2d05 446 Write( REG_PREAMBLELSB, preambleLen & 0xFF );
GregCr 0:e6ceb13d2d05 447
GregCr 0:e6ceb13d2d05 448 Write( REG_PACKETCONFIG1,
GregCr 0:e6ceb13d2d05 449 ( Read( REG_PACKETCONFIG1 ) &
GregCr 0:e6ceb13d2d05 450 RF_PACKETCONFIG1_CRC_MASK &
GregCr 0:e6ceb13d2d05 451 RF_PACKETCONFIG1_PACKETFORMAT_MASK ) |
GregCr 0:e6ceb13d2d05 452 ( ( fixLen == 1 ) ? RF_PACKETCONFIG1_PACKETFORMAT_FIXED : RF_PACKETCONFIG1_PACKETFORMAT_VARIABLE ) |
GregCr 0:e6ceb13d2d05 453 ( crcOn << 4 ) );
GregCr 0:e6ceb13d2d05 454 }
GregCr 0:e6ceb13d2d05 455 break;
GregCr 0:e6ceb13d2d05 456 case MODEM_LORA:
GregCr 0:e6ceb13d2d05 457 {
GregCr 0:e6ceb13d2d05 458 this->settings.LoRa.Power = power;
modtronix 16:0927c093fd82 459 if( bandwidth > 9 )
GregCr 0:e6ceb13d2d05 460 {
modtronix 16:0927c093fd82 461 // Fatal error: Bandwidth must be 0-9 (7.8 - 500khz)
GregCr 0:e6ceb13d2d05 462 while( 1 );
GregCr 0:e6ceb13d2d05 463 }
modtronix 16:0927c093fd82 464 //bandwidth += 7;
GregCr 0:e6ceb13d2d05 465 this->settings.LoRa.Bandwidth = bandwidth;
GregCr 0:e6ceb13d2d05 466 this->settings.LoRa.Datarate = datarate;
GregCr 0:e6ceb13d2d05 467 this->settings.LoRa.Coderate = coderate;
GregCr 0:e6ceb13d2d05 468 this->settings.LoRa.PreambleLen = preambleLen;
GregCr 0:e6ceb13d2d05 469 this->settings.LoRa.FixLen = fixLen;
GregCr 0:e6ceb13d2d05 470 this->settings.LoRa.CrcOn = crcOn;
mluis 13:618826a997e2 471 this->settings.LoRa.FreqHopOn = freqHopOn;
mluis 13:618826a997e2 472 this->settings.LoRa.HopPeriod = hopPeriod;
GregCr 0:e6ceb13d2d05 473 this->settings.LoRa.IqInverted = iqInverted;
GregCr 0:e6ceb13d2d05 474 this->settings.LoRa.TxTimeout = timeout;
GregCr 0:e6ceb13d2d05 475
GregCr 0:e6ceb13d2d05 476 if( datarate > 12 )
GregCr 0:e6ceb13d2d05 477 {
GregCr 0:e6ceb13d2d05 478 datarate = 12;
GregCr 0:e6ceb13d2d05 479 }
GregCr 0:e6ceb13d2d05 480 else if( datarate < 6 )
GregCr 0:e6ceb13d2d05 481 {
GregCr 0:e6ceb13d2d05 482 datarate = 6;
GregCr 0:e6ceb13d2d05 483 }
modtronix 16:0927c093fd82 484 //bandwidth 7=125, 8=250, 9=500, datarate=SF
GregCr 0:e6ceb13d2d05 485 if( ( ( bandwidth == 7 ) && ( ( datarate == 11 ) || ( datarate == 12 ) ) ) ||
GregCr 0:e6ceb13d2d05 486 ( ( bandwidth == 8 ) && ( datarate == 12 ) ) )
GregCr 0:e6ceb13d2d05 487 {
GregCr 0:e6ceb13d2d05 488 this->settings.LoRa.LowDatarateOptimize = 0x01;
GregCr 0:e6ceb13d2d05 489 }
GregCr 0:e6ceb13d2d05 490 else
GregCr 0:e6ceb13d2d05 491 {
GregCr 0:e6ceb13d2d05 492 this->settings.LoRa.LowDatarateOptimize = 0x00;
GregCr 0:e6ceb13d2d05 493 }
GregCr 6:e7f02929cd3d 494
GregCr 6:e7f02929cd3d 495 if( this->settings.LoRa.FreqHopOn == true )
GregCr 6:e7f02929cd3d 496 {
GregCr 6:e7f02929cd3d 497 Write( REG_LR_PLLHOP, ( Read( REG_LR_PLLHOP ) & RFLR_PLLHOP_FASTHOP_MASK ) | RFLR_PLLHOP_FASTHOP_ON );
GregCr 6:e7f02929cd3d 498 Write( REG_LR_HOPPERIOD, this->settings.LoRa.HopPeriod );
GregCr 6:e7f02929cd3d 499 }
GregCr 6:e7f02929cd3d 500
GregCr 0:e6ceb13d2d05 501 Write( REG_LR_MODEMCONFIG1,
GregCr 0:e6ceb13d2d05 502 ( Read( REG_LR_MODEMCONFIG1 ) &
GregCr 0:e6ceb13d2d05 503 RFLR_MODEMCONFIG1_BW_MASK &
GregCr 0:e6ceb13d2d05 504 RFLR_MODEMCONFIG1_CODINGRATE_MASK &
GregCr 0:e6ceb13d2d05 505 RFLR_MODEMCONFIG1_IMPLICITHEADER_MASK ) |
GregCr 0:e6ceb13d2d05 506 ( bandwidth << 4 ) | ( coderate << 1 ) |
GregCr 0:e6ceb13d2d05 507 fixLen );
GregCr 0:e6ceb13d2d05 508
GregCr 0:e6ceb13d2d05 509 Write( REG_LR_MODEMCONFIG2,
GregCr 0:e6ceb13d2d05 510 ( Read( REG_LR_MODEMCONFIG2 ) &
GregCr 0:e6ceb13d2d05 511 RFLR_MODEMCONFIG2_SF_MASK &
GregCr 0:e6ceb13d2d05 512 RFLR_MODEMCONFIG2_RXPAYLOADCRC_MASK ) |
GregCr 0:e6ceb13d2d05 513 ( datarate << 4 ) | ( crcOn << 2 ) );
GregCr 0:e6ceb13d2d05 514
GregCr 0:e6ceb13d2d05 515 Write( REG_LR_MODEMCONFIG3,
GregCr 0:e6ceb13d2d05 516 ( Read( REG_LR_MODEMCONFIG3 ) &
GregCr 0:e6ceb13d2d05 517 RFLR_MODEMCONFIG3_LOWDATARATEOPTIMIZE_MASK ) |
GregCr 0:e6ceb13d2d05 518 ( this->settings.LoRa.LowDatarateOptimize << 3 ) );
GregCr 0:e6ceb13d2d05 519
GregCr 0:e6ceb13d2d05 520 Write( REG_LR_PREAMBLEMSB, ( preambleLen >> 8 ) & 0x00FF );
GregCr 0:e6ceb13d2d05 521 Write( REG_LR_PREAMBLELSB, preambleLen & 0xFF );
GregCr 0:e6ceb13d2d05 522
GregCr 0:e6ceb13d2d05 523 if( datarate == 6 )
GregCr 0:e6ceb13d2d05 524 {
GregCr 0:e6ceb13d2d05 525 Write( REG_LR_DETECTOPTIMIZE,
GregCr 0:e6ceb13d2d05 526 ( Read( REG_LR_DETECTOPTIMIZE ) &
GregCr 0:e6ceb13d2d05 527 RFLR_DETECTIONOPTIMIZE_MASK ) |
GregCr 0:e6ceb13d2d05 528 RFLR_DETECTIONOPTIMIZE_SF6 );
GregCr 0:e6ceb13d2d05 529 Write( REG_LR_DETECTIONTHRESHOLD,
GregCr 0:e6ceb13d2d05 530 RFLR_DETECTIONTHRESH_SF6 );
GregCr 0:e6ceb13d2d05 531 }
GregCr 0:e6ceb13d2d05 532 else
GregCr 0:e6ceb13d2d05 533 {
GregCr 0:e6ceb13d2d05 534 Write( REG_LR_DETECTOPTIMIZE,
GregCr 0:e6ceb13d2d05 535 ( Read( REG_LR_DETECTOPTIMIZE ) &
GregCr 0:e6ceb13d2d05 536 RFLR_DETECTIONOPTIMIZE_MASK ) |
GregCr 0:e6ceb13d2d05 537 RFLR_DETECTIONOPTIMIZE_SF7_TO_SF12 );
GregCr 0:e6ceb13d2d05 538 Write( REG_LR_DETECTIONTHRESHOLD,
GregCr 0:e6ceb13d2d05 539 RFLR_DETECTIONTHRESH_SF7_TO_SF12 );
GregCr 0:e6ceb13d2d05 540 }
GregCr 0:e6ceb13d2d05 541 }
GregCr 0:e6ceb13d2d05 542 break;
GregCr 0:e6ceb13d2d05 543 }
GregCr 0:e6ceb13d2d05 544 }
GregCr 0:e6ceb13d2d05 545
GregCr 0:e6ceb13d2d05 546 double SX1276::TimeOnAir( ModemType modem, uint8_t pktLen )
GregCr 0:e6ceb13d2d05 547 {
GregCr 0:e6ceb13d2d05 548 double airTime = 0.0;
GregCr 0:e6ceb13d2d05 549
GregCr 0:e6ceb13d2d05 550 switch( modem )
GregCr 0:e6ceb13d2d05 551 {
GregCr 0:e6ceb13d2d05 552 case MODEM_FSK:
GregCr 0:e6ceb13d2d05 553 {
GregCr 4:f0ce52e94d3f 554 airTime = ceil( ( 8 * ( this->settings.Fsk.PreambleLen +
GregCr 0:e6ceb13d2d05 555 ( ( Read( REG_SYNCCONFIG ) & ~RF_SYNCCONFIG_SYNCSIZE_MASK ) + 1 ) +
GregCr 0:e6ceb13d2d05 556 ( ( this->settings.Fsk.FixLen == 0x01 ) ? 0.0 : 1.0 ) +
GregCr 0:e6ceb13d2d05 557 ( ( ( Read( REG_PACKETCONFIG1 ) & ~RF_PACKETCONFIG1_ADDRSFILTERING_MASK ) != 0x00 ) ? 1.0 : 0 ) +
GregCr 0:e6ceb13d2d05 558 pktLen +
GregCr 0:e6ceb13d2d05 559 ( ( this->settings.Fsk.CrcOn == 0x01 ) ? 2.0 : 0 ) ) /
GregCr 0:e6ceb13d2d05 560 this->settings.Fsk.Datarate ) * 1e6 );
GregCr 0:e6ceb13d2d05 561 }
GregCr 0:e6ceb13d2d05 562 break;
GregCr 0:e6ceb13d2d05 563 case MODEM_LORA:
GregCr 0:e6ceb13d2d05 564 {
GregCr 0:e6ceb13d2d05 565 double bw = 0.0;
GregCr 0:e6ceb13d2d05 566 switch( this->settings.LoRa.Bandwidth )
GregCr 0:e6ceb13d2d05 567 {
modtronix 16:0927c093fd82 568 case 0: // 7.8 kHz
modtronix 16:0927c093fd82 569 bw = 78e2;
modtronix 16:0927c093fd82 570 break;
modtronix 16:0927c093fd82 571 case 1: // 10.4 kHz
modtronix 16:0927c093fd82 572 bw = 104e2;
modtronix 16:0927c093fd82 573 break;
modtronix 16:0927c093fd82 574 case 2: // 15.6 kHz
modtronix 16:0927c093fd82 575 bw = 156e2;
modtronix 16:0927c093fd82 576 break;
modtronix 16:0927c093fd82 577 case 3: // 20.8 kHz
modtronix 16:0927c093fd82 578 bw = 208e2;
modtronix 16:0927c093fd82 579 break;
modtronix 16:0927c093fd82 580 case 4: // 31.2 kHz
modtronix 16:0927c093fd82 581 bw = 312e2;
modtronix 16:0927c093fd82 582 break;
modtronix 16:0927c093fd82 583 case 5: // 41.4 kHz
modtronix 16:0927c093fd82 584 bw = 414e2;
modtronix 16:0927c093fd82 585 break;
modtronix 16:0927c093fd82 586 case 6: // 62.5 kHz
modtronix 16:0927c093fd82 587 bw = 625e2;
modtronix 16:0927c093fd82 588 break;
GregCr 0:e6ceb13d2d05 589 case 7: // 125 kHz
GregCr 0:e6ceb13d2d05 590 bw = 125e3;
GregCr 0:e6ceb13d2d05 591 break;
GregCr 0:e6ceb13d2d05 592 case 8: // 250 kHz
GregCr 0:e6ceb13d2d05 593 bw = 250e3;
GregCr 0:e6ceb13d2d05 594 break;
GregCr 0:e6ceb13d2d05 595 case 9: // 500 kHz
GregCr 0:e6ceb13d2d05 596 bw = 500e3;
GregCr 0:e6ceb13d2d05 597 break;
GregCr 0:e6ceb13d2d05 598 }
GregCr 0:e6ceb13d2d05 599
GregCr 0:e6ceb13d2d05 600 // Symbol rate : time for one symbol (secs)
GregCr 0:e6ceb13d2d05 601 double rs = bw / ( 1 << this->settings.LoRa.Datarate );
GregCr 0:e6ceb13d2d05 602 double ts = 1 / rs;
GregCr 0:e6ceb13d2d05 603 // time of preamble
GregCr 0:e6ceb13d2d05 604 double tPreamble = ( this->settings.LoRa.PreambleLen + 4.25 ) * ts;
GregCr 0:e6ceb13d2d05 605 // Symbol length of payload and time
GregCr 0:e6ceb13d2d05 606 double tmp = ceil( ( 8 * pktLen - 4 * this->settings.LoRa.Datarate +
GregCr 0:e6ceb13d2d05 607 28 + 16 * this->settings.LoRa.CrcOn -
GregCr 0:e6ceb13d2d05 608 ( this->settings.LoRa.FixLen ? 20 : 0 ) ) /
GregCr 0:e6ceb13d2d05 609 ( double )( 4 * this->settings.LoRa.Datarate -
GregCr 0:e6ceb13d2d05 610 ( ( this->settings.LoRa.LowDatarateOptimize > 0 ) ? 8 : 0 ) ) ) *
GregCr 0:e6ceb13d2d05 611 ( this->settings.LoRa.Coderate + 4 );
GregCr 0:e6ceb13d2d05 612 double nPayload = 8 + ( ( tmp > 0 ) ? tmp : 0 );
GregCr 0:e6ceb13d2d05 613 double tPayload = nPayload * ts;
GregCr 0:e6ceb13d2d05 614 // Time on air
GregCr 0:e6ceb13d2d05 615 double tOnAir = tPreamble + tPayload;
GregCr 0:e6ceb13d2d05 616 // return us secs
GregCr 0:e6ceb13d2d05 617 airTime = floor( tOnAir * 1e6 + 0.999 );
GregCr 0:e6ceb13d2d05 618 }
GregCr 0:e6ceb13d2d05 619 break;
GregCr 0:e6ceb13d2d05 620 }
GregCr 0:e6ceb13d2d05 621 return airTime;
GregCr 0:e6ceb13d2d05 622 }
GregCr 0:e6ceb13d2d05 623
GregCr 0:e6ceb13d2d05 624 void SX1276::Send( uint8_t *buffer, uint8_t size )
GregCr 0:e6ceb13d2d05 625 {
GregCr 0:e6ceb13d2d05 626 uint32_t txTimeout = 0;
GregCr 0:e6ceb13d2d05 627
GregCr 5:11ec8a6ba4f0 628 this->settings.State = IDLE;
GregCr 5:11ec8a6ba4f0 629
GregCr 0:e6ceb13d2d05 630 switch( this->settings.Modem )
GregCr 0:e6ceb13d2d05 631 {
GregCr 0:e6ceb13d2d05 632 case MODEM_FSK:
GregCr 0:e6ceb13d2d05 633 {
GregCr 0:e6ceb13d2d05 634 this->settings.FskPacketHandler.NbBytes = 0;
GregCr 0:e6ceb13d2d05 635 this->settings.FskPacketHandler.Size = size;
GregCr 0:e6ceb13d2d05 636
GregCr 0:e6ceb13d2d05 637 if( this->settings.Fsk.FixLen == false )
GregCr 0:e6ceb13d2d05 638 {
GregCr 0:e6ceb13d2d05 639 WriteFifo( ( uint8_t* )&size, 1 );
GregCr 0:e6ceb13d2d05 640 }
GregCr 0:e6ceb13d2d05 641 else
GregCr 0:e6ceb13d2d05 642 {
GregCr 0:e6ceb13d2d05 643 Write( REG_PAYLOADLENGTH, size );
GregCr 0:e6ceb13d2d05 644 }
GregCr 0:e6ceb13d2d05 645
GregCr 0:e6ceb13d2d05 646 if( ( size > 0 ) && ( size <= 64 ) )
GregCr 0:e6ceb13d2d05 647 {
GregCr 0:e6ceb13d2d05 648 this->settings.FskPacketHandler.ChunkSize = size;
GregCr 0:e6ceb13d2d05 649 }
GregCr 0:e6ceb13d2d05 650 else
GregCr 0:e6ceb13d2d05 651 {
GregCr 0:e6ceb13d2d05 652 this->settings.FskPacketHandler.ChunkSize = 32;
GregCr 0:e6ceb13d2d05 653 }
GregCr 0:e6ceb13d2d05 654
GregCr 0:e6ceb13d2d05 655 // Write payload buffer
GregCr 0:e6ceb13d2d05 656 WriteFifo( buffer, this->settings.FskPacketHandler.ChunkSize );
GregCr 0:e6ceb13d2d05 657 this->settings.FskPacketHandler.NbBytes += this->settings.FskPacketHandler.ChunkSize;
GregCr 0:e6ceb13d2d05 658 txTimeout = this->settings.Fsk.TxTimeout;
GregCr 0:e6ceb13d2d05 659 }
GregCr 0:e6ceb13d2d05 660 break;
GregCr 0:e6ceb13d2d05 661 case MODEM_LORA:
GregCr 0:e6ceb13d2d05 662 {
GregCr 0:e6ceb13d2d05 663 if( this->settings.LoRa.IqInverted == true )
GregCr 0:e6ceb13d2d05 664 {
GregCr 0:e6ceb13d2d05 665 Write( REG_LR_INVERTIQ, ( ( Read( REG_LR_INVERTIQ ) & RFLR_INVERTIQ_TX_MASK & RFLR_INVERTIQ_RX_MASK ) | RFLR_INVERTIQ_RX_OFF | RFLR_INVERTIQ_TX_ON ) );
GregCr 0:e6ceb13d2d05 666 }
GregCr 0:e6ceb13d2d05 667 else
GregCr 0:e6ceb13d2d05 668 {
GregCr 0:e6ceb13d2d05 669 Write( REG_LR_INVERTIQ, ( ( Read( REG_LR_INVERTIQ ) & RFLR_INVERTIQ_TX_MASK & RFLR_INVERTIQ_RX_MASK ) | RFLR_INVERTIQ_RX_OFF | RFLR_INVERTIQ_TX_OFF ) );
GregCr 0:e6ceb13d2d05 670 }
GregCr 0:e6ceb13d2d05 671
GregCr 0:e6ceb13d2d05 672 this->settings.LoRaPacketHandler.Size = size;
GregCr 0:e6ceb13d2d05 673
GregCr 0:e6ceb13d2d05 674 // Initializes the payload size
GregCr 0:e6ceb13d2d05 675 Write( REG_LR_PAYLOADLENGTH, size );
GregCr 0:e6ceb13d2d05 676
GregCr 0:e6ceb13d2d05 677 // Full buffer used for Tx
GregCr 0:e6ceb13d2d05 678 Write( REG_LR_FIFOTXBASEADDR, 0 );
GregCr 0:e6ceb13d2d05 679 Write( REG_LR_FIFOADDRPTR, 0 );
GregCr 0:e6ceb13d2d05 680
GregCr 0:e6ceb13d2d05 681 // FIFO operations can not take place in Sleep mode
GregCr 0:e6ceb13d2d05 682 if( ( Read( REG_OPMODE ) & ~RF_OPMODE_MASK ) == RF_OPMODE_SLEEP )
GregCr 0:e6ceb13d2d05 683 {
GregCr 0:e6ceb13d2d05 684 Standby( );
GregCr 4:f0ce52e94d3f 685 wait_ms( 1 );
GregCr 0:e6ceb13d2d05 686 }
GregCr 0:e6ceb13d2d05 687 // Write payload buffer
GregCr 0:e6ceb13d2d05 688 WriteFifo( buffer, size );
GregCr 0:e6ceb13d2d05 689 txTimeout = this->settings.LoRa.TxTimeout;
GregCr 0:e6ceb13d2d05 690 }
GregCr 0:e6ceb13d2d05 691 break;
GregCr 0:e6ceb13d2d05 692 }
GregCr 0:e6ceb13d2d05 693
GregCr 0:e6ceb13d2d05 694 Tx( txTimeout );
GregCr 0:e6ceb13d2d05 695 }
GregCr 0:e6ceb13d2d05 696
GregCr 0:e6ceb13d2d05 697 void SX1276::Sleep( void )
GregCr 0:e6ceb13d2d05 698 {
mluis 13:618826a997e2 699 // Initialize driver timeout timers
mluis 13:618826a997e2 700 txTimeoutTimer.detach( );
GregCr 0:e6ceb13d2d05 701 rxTimeoutTimer.detach( );
GregCr 0:e6ceb13d2d05 702 SetOpMode( RF_OPMODE_SLEEP );
GregCr 0:e6ceb13d2d05 703 }
GregCr 0:e6ceb13d2d05 704
GregCr 0:e6ceb13d2d05 705 void SX1276::Standby( void )
GregCr 0:e6ceb13d2d05 706 {
GregCr 0:e6ceb13d2d05 707 txTimeoutTimer.detach( );
GregCr 0:e6ceb13d2d05 708 rxTimeoutTimer.detach( );
GregCr 0:e6ceb13d2d05 709 SetOpMode( RF_OPMODE_STANDBY );
GregCr 0:e6ceb13d2d05 710 }
GregCr 0:e6ceb13d2d05 711
GregCr 0:e6ceb13d2d05 712 void SX1276::Rx( uint32_t timeout )
GregCr 0:e6ceb13d2d05 713 {
GregCr 0:e6ceb13d2d05 714 bool rxContinuous = false;
GregCr 6:e7f02929cd3d 715
GregCr 0:e6ceb13d2d05 716 switch( this->settings.Modem )
GregCr 0:e6ceb13d2d05 717 {
GregCr 0:e6ceb13d2d05 718 case MODEM_FSK:
GregCr 0:e6ceb13d2d05 719 {
GregCr 0:e6ceb13d2d05 720 rxContinuous = this->settings.Fsk.RxContinuous;
GregCr 0:e6ceb13d2d05 721
GregCr 0:e6ceb13d2d05 722 // DIO0=PayloadReady
GregCr 0:e6ceb13d2d05 723 // DIO1=FifoLevel
GregCr 0:e6ceb13d2d05 724 // DIO2=SyncAddr
GregCr 0:e6ceb13d2d05 725 // DIO3=FifoEmpty
GregCr 0:e6ceb13d2d05 726 // DIO4=Preamble
GregCr 0:e6ceb13d2d05 727 // DIO5=ModeReady
GregCr 5:11ec8a6ba4f0 728 Write( REG_DIOMAPPING1, ( Read( REG_DIOMAPPING1 ) & RF_DIOMAPPING1_DIO0_MASK & RF_DIOMAPPING1_DIO1_MASK &
GregCr 0:e6ceb13d2d05 729 RF_DIOMAPPING1_DIO2_MASK ) |
GregCr 0:e6ceb13d2d05 730 RF_DIOMAPPING1_DIO0_00 |
GregCr 0:e6ceb13d2d05 731 RF_DIOMAPPING1_DIO2_11 );
GregCr 0:e6ceb13d2d05 732
GregCr 0:e6ceb13d2d05 733 Write( REG_DIOMAPPING2, ( Read( REG_DIOMAPPING2 ) & RF_DIOMAPPING2_DIO4_MASK &
GregCr 0:e6ceb13d2d05 734 RF_DIOMAPPING2_MAP_MASK ) |
GregCr 0:e6ceb13d2d05 735 RF_DIOMAPPING2_DIO4_11 |
GregCr 0:e6ceb13d2d05 736 RF_DIOMAPPING2_MAP_PREAMBLEDETECT );
GregCr 0:e6ceb13d2d05 737
GregCr 0:e6ceb13d2d05 738 this->settings.FskPacketHandler.FifoThresh = Read( REG_FIFOTHRESH ) & 0x3F;
GregCr 0:e6ceb13d2d05 739
GregCr 0:e6ceb13d2d05 740 this->settings.FskPacketHandler.PreambleDetected = false;
GregCr 0:e6ceb13d2d05 741 this->settings.FskPacketHandler.SyncWordDetected = false;
GregCr 0:e6ceb13d2d05 742 this->settings.FskPacketHandler.NbBytes = 0;
GregCr 0:e6ceb13d2d05 743 this->settings.FskPacketHandler.Size = 0;
GregCr 0:e6ceb13d2d05 744 }
GregCr 0:e6ceb13d2d05 745 break;
GregCr 0:e6ceb13d2d05 746 case MODEM_LORA:
GregCr 0:e6ceb13d2d05 747 {
GregCr 0:e6ceb13d2d05 748 if( this->settings.LoRa.IqInverted == true )
GregCr 0:e6ceb13d2d05 749 {
GregCr 0:e6ceb13d2d05 750 Write( REG_LR_INVERTIQ, ( ( Read( REG_LR_INVERTIQ ) & RFLR_INVERTIQ_TX_MASK & RFLR_INVERTIQ_RX_MASK ) | RFLR_INVERTIQ_RX_ON | RFLR_INVERTIQ_TX_OFF ) );
GregCr 0:e6ceb13d2d05 751 }
GregCr 0:e6ceb13d2d05 752 else
GregCr 0:e6ceb13d2d05 753 {
GregCr 0:e6ceb13d2d05 754 Write( REG_LR_INVERTIQ, ( ( Read( REG_LR_INVERTIQ ) & RFLR_INVERTIQ_TX_MASK & RFLR_INVERTIQ_RX_MASK ) | RFLR_INVERTIQ_RX_OFF | RFLR_INVERTIQ_TX_OFF ) );
GregCr 0:e6ceb13d2d05 755 }
GregCr 0:e6ceb13d2d05 756
GregCr 0:e6ceb13d2d05 757 rxContinuous = this->settings.LoRa.RxContinuous;
GregCr 0:e6ceb13d2d05 758
GregCr 6:e7f02929cd3d 759 if( this->settings.LoRa.FreqHopOn == true )
GregCr 6:e7f02929cd3d 760 {
GregCr 6:e7f02929cd3d 761 Write( REG_LR_IRQFLAGSMASK, //RFLR_IRQFLAGS_RXTIMEOUT |
GregCr 0:e6ceb13d2d05 762 //RFLR_IRQFLAGS_RXDONE |
GregCr 0:e6ceb13d2d05 763 //RFLR_IRQFLAGS_PAYLOADCRCERROR |
GregCr 4:f0ce52e94d3f 764 RFLR_IRQFLAGS_VALIDHEADER |
GregCr 0:e6ceb13d2d05 765 RFLR_IRQFLAGS_TXDONE |
GregCr 0:e6ceb13d2d05 766 RFLR_IRQFLAGS_CADDONE |
GregCr 6:e7f02929cd3d 767 //RFLR_IRQFLAGS_FHSSCHANGEDCHANNEL |
GregCr 0:e6ceb13d2d05 768 RFLR_IRQFLAGS_CADDETECTED );
GregCr 6:e7f02929cd3d 769
mluis 13:618826a997e2 770 // DIO0=RxDone, DIO2=FhssChangeChannel
mluis 13:618826a997e2 771 Write( REG_DIOMAPPING1, ( Read( REG_DIOMAPPING1 ) & RFLR_DIOMAPPING1_DIO0_MASK & RFLR_DIOMAPPING1_DIO2_MASK ) | RFLR_DIOMAPPING1_DIO0_00 | RFLR_DIOMAPPING1_DIO2_00 );
GregCr 6:e7f02929cd3d 772 }
GregCr 6:e7f02929cd3d 773 else
GregCr 6:e7f02929cd3d 774 {
GregCr 6:e7f02929cd3d 775 Write( REG_LR_IRQFLAGSMASK, //RFLR_IRQFLAGS_RXTIMEOUT |
GregCr 6:e7f02929cd3d 776 //RFLR_IRQFLAGS_RXDONE |
GregCr 6:e7f02929cd3d 777 //RFLR_IRQFLAGS_PAYLOADCRCERROR |
GregCr 6:e7f02929cd3d 778 RFLR_IRQFLAGS_VALIDHEADER |
GregCr 6:e7f02929cd3d 779 RFLR_IRQFLAGS_TXDONE |
GregCr 6:e7f02929cd3d 780 RFLR_IRQFLAGS_CADDONE |
GregCr 8:0fe3e0e8007b 781 RFLR_IRQFLAGS_FHSSCHANGEDCHANNEL |
GregCr 6:e7f02929cd3d 782 RFLR_IRQFLAGS_CADDETECTED );
GregCr 6:e7f02929cd3d 783
GregCr 6:e7f02929cd3d 784 // DIO0=RxDone
GregCr 6:e7f02929cd3d 785 Write( REG_DIOMAPPING1, ( Read( REG_DIOMAPPING1 ) & RFLR_DIOMAPPING1_DIO0_MASK ) | RFLR_DIOMAPPING1_DIO0_00 );
GregCr 6:e7f02929cd3d 786 }
GregCr 0:e6ceb13d2d05 787
GregCr 0:e6ceb13d2d05 788 Write( REG_LR_FIFORXBASEADDR, 0 );
GregCr 0:e6ceb13d2d05 789 Write( REG_LR_FIFOADDRPTR, 0 );
GregCr 0:e6ceb13d2d05 790 }
GregCr 0:e6ceb13d2d05 791 break;
GregCr 0:e6ceb13d2d05 792 }
GregCr 0:e6ceb13d2d05 793
GregCr 0:e6ceb13d2d05 794 memset( rxBuffer, 0, ( size_t )RX_BUFFER_SIZE );
GregCr 0:e6ceb13d2d05 795
GregCr 0:e6ceb13d2d05 796 this->settings.State = RX;
GregCr 0:e6ceb13d2d05 797 if( timeout != 0 )
GregCr 0:e6ceb13d2d05 798 {
GregCr 0:e6ceb13d2d05 799 rxTimeoutTimer.attach_us( this, &SX1276::OnTimeoutIrq, timeout );
GregCr 0:e6ceb13d2d05 800 }
GregCr 0:e6ceb13d2d05 801
GregCr 0:e6ceb13d2d05 802 if( this->settings.Modem == MODEM_FSK )
GregCr 0:e6ceb13d2d05 803 {
GregCr 0:e6ceb13d2d05 804 SetOpMode( RF_OPMODE_RECEIVER );
GregCr 0:e6ceb13d2d05 805
GregCr 0:e6ceb13d2d05 806 if( rxContinuous == false )
GregCr 0:e6ceb13d2d05 807 {
GregCr 0:e6ceb13d2d05 808 rxTimeoutSyncWord.attach_us( this, &SX1276::OnTimeoutIrq, ( 8.0 * ( this->settings.Fsk.PreambleLen +
GregCr 0:e6ceb13d2d05 809 ( ( Read( REG_SYNCCONFIG ) &
GregCr 0:e6ceb13d2d05 810 ~RF_SYNCCONFIG_SYNCSIZE_MASK ) +
GregCr 0:e6ceb13d2d05 811 1.0 ) + 1.0 ) /
GregCr 0:e6ceb13d2d05 812 ( double )this->settings.Fsk.Datarate ) * 1e6 ) ;
GregCr 0:e6ceb13d2d05 813 }
GregCr 0:e6ceb13d2d05 814 }
GregCr 0:e6ceb13d2d05 815 else
GregCr 0:e6ceb13d2d05 816 {
GregCr 0:e6ceb13d2d05 817 if( rxContinuous == true )
GregCr 0:e6ceb13d2d05 818 {
GregCr 0:e6ceb13d2d05 819 SetOpMode( RFLR_OPMODE_RECEIVER );
GregCr 0:e6ceb13d2d05 820 }
GregCr 0:e6ceb13d2d05 821 else
GregCr 0:e6ceb13d2d05 822 {
GregCr 0:e6ceb13d2d05 823 SetOpMode( RFLR_OPMODE_RECEIVER_SINGLE );
GregCr 0:e6ceb13d2d05 824 }
GregCr 0:e6ceb13d2d05 825 }
GregCr 0:e6ceb13d2d05 826 }
GregCr 0:e6ceb13d2d05 827
GregCr 0:e6ceb13d2d05 828 void SX1276::Tx( uint32_t timeout )
GregCr 0:e6ceb13d2d05 829 {
GregCr 0:e6ceb13d2d05 830 switch( this->settings.Modem )
GregCr 0:e6ceb13d2d05 831 {
GregCr 0:e6ceb13d2d05 832 case MODEM_FSK:
GregCr 0:e6ceb13d2d05 833 {
GregCr 0:e6ceb13d2d05 834 // DIO0=PacketSent
GregCr 0:e6ceb13d2d05 835 // DIO1=FifoLevel
GregCr 0:e6ceb13d2d05 836 // DIO2=FifoFull
GregCr 0:e6ceb13d2d05 837 // DIO3=FifoEmpty
GregCr 0:e6ceb13d2d05 838 // DIO4=LowBat
GregCr 0:e6ceb13d2d05 839 // DIO5=ModeReady
GregCr 5:11ec8a6ba4f0 840 Write( REG_DIOMAPPING1, ( Read( REG_DIOMAPPING1 ) & RF_DIOMAPPING1_DIO0_MASK & RF_DIOMAPPING1_DIO1_MASK &
GregCr 0:e6ceb13d2d05 841 RF_DIOMAPPING1_DIO2_MASK ) );
GregCr 0:e6ceb13d2d05 842
GregCr 0:e6ceb13d2d05 843 Write( REG_DIOMAPPING2, ( Read( REG_DIOMAPPING2 ) & RF_DIOMAPPING2_DIO4_MASK &
GregCr 0:e6ceb13d2d05 844 RF_DIOMAPPING2_MAP_MASK ) );
GregCr 0:e6ceb13d2d05 845 this->settings.FskPacketHandler.FifoThresh = Read( REG_FIFOTHRESH ) & 0x3F;
GregCr 0:e6ceb13d2d05 846 }
GregCr 0:e6ceb13d2d05 847 break;
GregCr 0:e6ceb13d2d05 848 case MODEM_LORA:
GregCr 0:e6ceb13d2d05 849 {
GregCr 6:e7f02929cd3d 850
GregCr 6:e7f02929cd3d 851 if( this->settings.LoRa.FreqHopOn == true )
GregCr 6:e7f02929cd3d 852 {
GregCr 6:e7f02929cd3d 853 Write( REG_LR_IRQFLAGSMASK, RFLR_IRQFLAGS_RXTIMEOUT |
GregCr 6:e7f02929cd3d 854 RFLR_IRQFLAGS_RXDONE |
GregCr 6:e7f02929cd3d 855 RFLR_IRQFLAGS_PAYLOADCRCERROR |
GregCr 6:e7f02929cd3d 856 RFLR_IRQFLAGS_VALIDHEADER |
GregCr 6:e7f02929cd3d 857 //RFLR_IRQFLAGS_TXDONE |
GregCr 6:e7f02929cd3d 858 RFLR_IRQFLAGS_CADDONE |
GregCr 6:e7f02929cd3d 859 //RFLR_IRQFLAGS_FHSSCHANGEDCHANNEL |
GregCr 6:e7f02929cd3d 860 RFLR_IRQFLAGS_CADDETECTED );
GregCr 6:e7f02929cd3d 861
GregCr 6:e7f02929cd3d 862 // DIO0=TxDone
GregCr 8:0fe3e0e8007b 863 Write( REG_DIOMAPPING1, ( Read( REG_DIOMAPPING1 ) & RFLR_DIOMAPPING1_DIO0_MASK ) | RFLR_DIOMAPPING1_DIO0_01 );
GregCr 6:e7f02929cd3d 864 // DIO2=FhssChangeChannel
GregCr 6:e7f02929cd3d 865 Write( REG_DIOMAPPING1, ( Read( REG_DIOMAPPING1 ) & RFLR_DIOMAPPING1_DIO2_MASK ) | RFLR_DIOMAPPING1_DIO2_00 );
GregCr 6:e7f02929cd3d 866 }
GregCr 6:e7f02929cd3d 867 else
GregCr 6:e7f02929cd3d 868 {
GregCr 6:e7f02929cd3d 869 Write( REG_LR_IRQFLAGSMASK, RFLR_IRQFLAGS_RXTIMEOUT |
GregCr 0:e6ceb13d2d05 870 RFLR_IRQFLAGS_RXDONE |
GregCr 0:e6ceb13d2d05 871 RFLR_IRQFLAGS_PAYLOADCRCERROR |
GregCr 0:e6ceb13d2d05 872 RFLR_IRQFLAGS_VALIDHEADER |
GregCr 0:e6ceb13d2d05 873 //RFLR_IRQFLAGS_TXDONE |
GregCr 0:e6ceb13d2d05 874 RFLR_IRQFLAGS_CADDONE |
GregCr 0:e6ceb13d2d05 875 RFLR_IRQFLAGS_FHSSCHANGEDCHANNEL |
GregCr 0:e6ceb13d2d05 876 RFLR_IRQFLAGS_CADDETECTED );
GregCr 6:e7f02929cd3d 877
GregCr 6:e7f02929cd3d 878 // DIO0=TxDone
GregCr 6:e7f02929cd3d 879 Write( REG_DIOMAPPING1, ( Read( REG_DIOMAPPING1 ) & RFLR_DIOMAPPING1_DIO0_MASK ) | RFLR_DIOMAPPING1_DIO0_01 );
GregCr 6:e7f02929cd3d 880 }
GregCr 0:e6ceb13d2d05 881 }
GregCr 0:e6ceb13d2d05 882 break;
GregCr 0:e6ceb13d2d05 883 }
GregCr 0:e6ceb13d2d05 884
GregCr 0:e6ceb13d2d05 885 this->settings.State = TX;
mluis 13:618826a997e2 886 txTimeoutTimer.attach_us( this, &SX1276::OnTimeoutIrq, timeout );
GregCr 0:e6ceb13d2d05 887 SetOpMode( RF_OPMODE_TRANSMITTER );
GregCr 0:e6ceb13d2d05 888 }
GregCr 0:e6ceb13d2d05 889
GregCr 7:2b555111463f 890 void SX1276::StartCad( void )
GregCr 0:e6ceb13d2d05 891 {
GregCr 7:2b555111463f 892 switch( this->settings.Modem )
GregCr 7:2b555111463f 893 {
GregCr 7:2b555111463f 894 case MODEM_FSK:
GregCr 7:2b555111463f 895 {
GregCr 7:2b555111463f 896
GregCr 7:2b555111463f 897 }
GregCr 7:2b555111463f 898 break;
GregCr 7:2b555111463f 899 case MODEM_LORA:
GregCr 7:2b555111463f 900 {
GregCr 7:2b555111463f 901 Write( REG_LR_IRQFLAGSMASK, RFLR_IRQFLAGS_RXTIMEOUT |
GregCr 7:2b555111463f 902 RFLR_IRQFLAGS_RXDONE |
GregCr 7:2b555111463f 903 RFLR_IRQFLAGS_PAYLOADCRCERROR |
GregCr 7:2b555111463f 904 RFLR_IRQFLAGS_VALIDHEADER |
GregCr 7:2b555111463f 905 RFLR_IRQFLAGS_TXDONE |
GregCr 7:2b555111463f 906 //RFLR_IRQFLAGS_CADDONE |
GregCr 12:aa5b3bf7fdf4 907 RFLR_IRQFLAGS_FHSSCHANGEDCHANNEL // |
GregCr 12:aa5b3bf7fdf4 908 //RFLR_IRQFLAGS_CADDETECTED
GregCr 12:aa5b3bf7fdf4 909 );
GregCr 7:2b555111463f 910
GregCr 7:2b555111463f 911 // DIO3=CADDone
GregCr 7:2b555111463f 912 Write( REG_DIOMAPPING1, ( Read( REG_DIOMAPPING1 ) & RFLR_DIOMAPPING1_DIO0_MASK ) | RFLR_DIOMAPPING1_DIO0_00 );
GregCr 7:2b555111463f 913
GregCr 7:2b555111463f 914 this->settings.State = CAD;
GregCr 7:2b555111463f 915 SetOpMode( RFLR_OPMODE_CAD );
GregCr 7:2b555111463f 916 }
GregCr 7:2b555111463f 917 break;
GregCr 7:2b555111463f 918 default:
GregCr 7:2b555111463f 919 break;
GregCr 7:2b555111463f 920 }
GregCr 7:2b555111463f 921 }
GregCr 7:2b555111463f 922
GregCr 7:2b555111463f 923 int16_t SX1276::GetRssi( ModemType modem )
GregCr 7:2b555111463f 924 {
GregCr 7:2b555111463f 925 int16_t rssi = 0;
GregCr 0:e6ceb13d2d05 926
GregCr 0:e6ceb13d2d05 927 switch( modem )
GregCr 0:e6ceb13d2d05 928 {
GregCr 0:e6ceb13d2d05 929 case MODEM_FSK:
GregCr 0:e6ceb13d2d05 930 rssi = -( Read( REG_RSSIVALUE ) >> 1 );
GregCr 0:e6ceb13d2d05 931 break;
GregCr 0:e6ceb13d2d05 932 case MODEM_LORA:
GregCr 0:e6ceb13d2d05 933 if( this->settings.Channel > RF_MID_BAND_THRESH )
GregCr 0:e6ceb13d2d05 934 {
GregCr 0:e6ceb13d2d05 935 rssi = RSSI_OFFSET_HF + Read( REG_LR_RSSIVALUE );
GregCr 0:e6ceb13d2d05 936 }
GregCr 0:e6ceb13d2d05 937 else
GregCr 0:e6ceb13d2d05 938 {
GregCr 0:e6ceb13d2d05 939 rssi = RSSI_OFFSET_LF + Read( REG_LR_RSSIVALUE );
GregCr 0:e6ceb13d2d05 940 }
GregCr 0:e6ceb13d2d05 941 break;
GregCr 0:e6ceb13d2d05 942 default:
GregCr 0:e6ceb13d2d05 943 rssi = -1;
GregCr 0:e6ceb13d2d05 944 break;
GregCr 0:e6ceb13d2d05 945 }
GregCr 0:e6ceb13d2d05 946 return rssi;
GregCr 0:e6ceb13d2d05 947 }
GregCr 0:e6ceb13d2d05 948
GregCr 0:e6ceb13d2d05 949 void SX1276::SetOpMode( uint8_t opMode )
GregCr 0:e6ceb13d2d05 950 {
GregCr 0:e6ceb13d2d05 951 if( opMode != previousOpMode )
GregCr 0:e6ceb13d2d05 952 {
GregCr 0:e6ceb13d2d05 953 previousOpMode = opMode;
GregCr 0:e6ceb13d2d05 954 if( opMode == RF_OPMODE_SLEEP )
GregCr 0:e6ceb13d2d05 955 {
GregCr 0:e6ceb13d2d05 956 SetAntSwLowPower( true );
GregCr 0:e6ceb13d2d05 957 }
GregCr 0:e6ceb13d2d05 958 else
GregCr 0:e6ceb13d2d05 959 {
GregCr 0:e6ceb13d2d05 960 SetAntSwLowPower( false );
GregCr 0:e6ceb13d2d05 961 if( opMode == RF_OPMODE_TRANSMITTER )
GregCr 0:e6ceb13d2d05 962 {
GregCr 0:e6ceb13d2d05 963 SetAntSw( 1 );
GregCr 0:e6ceb13d2d05 964 }
GregCr 0:e6ceb13d2d05 965 else
GregCr 0:e6ceb13d2d05 966 {
GregCr 0:e6ceb13d2d05 967 SetAntSw( 0 );
GregCr 0:e6ceb13d2d05 968 }
GregCr 0:e6ceb13d2d05 969 }
GregCr 0:e6ceb13d2d05 970 Write( REG_OPMODE, ( Read( REG_OPMODE ) & RF_OPMODE_MASK ) | opMode );
GregCr 0:e6ceb13d2d05 971 }
GregCr 0:e6ceb13d2d05 972 }
GregCr 0:e6ceb13d2d05 973
GregCr 0:e6ceb13d2d05 974 void SX1276::SetModem( ModemType modem )
GregCr 0:e6ceb13d2d05 975 {
GregCr 4:f0ce52e94d3f 976 if( this->settings.Modem != modem )
GregCr 0:e6ceb13d2d05 977 {
mluis 13:618826a997e2 978 this->settings.Modem = modem;
mluis 13:618826a997e2 979 switch( this->settings.Modem )
mluis 13:618826a997e2 980 {
mluis 13:618826a997e2 981 default:
mluis 13:618826a997e2 982 case MODEM_FSK:
mluis 13:618826a997e2 983 SetOpMode( RF_OPMODE_SLEEP );
mluis 13:618826a997e2 984 Write( REG_OPMODE, ( Read( REG_OPMODE ) & RFLR_OPMODE_LONGRANGEMODE_MASK ) | RFLR_OPMODE_LONGRANGEMODE_OFF );
mluis 13:618826a997e2 985
mluis 13:618826a997e2 986 Write( REG_DIOMAPPING1, 0x00 );
mluis 13:618826a997e2 987 Write( REG_DIOMAPPING2, 0x30 ); // DIO5=ModeReady
mluis 13:618826a997e2 988 break;
mluis 13:618826a997e2 989 case MODEM_LORA:
mluis 13:618826a997e2 990 SetOpMode( RF_OPMODE_SLEEP );
mluis 13:618826a997e2 991 Write( REG_OPMODE, ( Read( REG_OPMODE ) & RFLR_OPMODE_LONGRANGEMODE_MASK ) | RFLR_OPMODE_LONGRANGEMODE_ON );
mluis 13:618826a997e2 992 Write( 0x30, 0x00 ); // IF = 0
mluis 13:618826a997e2 993 Write( REG_LR_DETECTOPTIMIZE, ( Read( REG_LR_DETECTOPTIMIZE ) & 0x7F ) ); // Manual IF
mluis 13:618826a997e2 994 Write( REG_DIOMAPPING1, 0x00 );
mluis 13:618826a997e2 995 Write( REG_DIOMAPPING2, 0x00 );
mluis 13:618826a997e2 996 break;
mluis 13:618826a997e2 997 }
GregCr 0:e6ceb13d2d05 998 }
GregCr 0:e6ceb13d2d05 999 }
GregCr 0:e6ceb13d2d05 1000
GregCr 0:e6ceb13d2d05 1001 void SX1276::OnTimeoutIrq( void )
GregCr 0:e6ceb13d2d05 1002 {
GregCr 0:e6ceb13d2d05 1003 switch( this->settings.State )
GregCr 0:e6ceb13d2d05 1004 {
GregCr 0:e6ceb13d2d05 1005 case RX:
GregCr 0:e6ceb13d2d05 1006 if( this->settings.Modem == MODEM_FSK )
GregCr 0:e6ceb13d2d05 1007 {
GregCr 0:e6ceb13d2d05 1008 this->settings.FskPacketHandler.PreambleDetected = false;
GregCr 0:e6ceb13d2d05 1009 this->settings.FskPacketHandler.SyncWordDetected = false;
GregCr 0:e6ceb13d2d05 1010 this->settings.FskPacketHandler.NbBytes = 0;
GregCr 0:e6ceb13d2d05 1011 this->settings.FskPacketHandler.Size = 0;
GregCr 0:e6ceb13d2d05 1012
GregCr 0:e6ceb13d2d05 1013 // Clear Irqs
GregCr 0:e6ceb13d2d05 1014 Write( REG_IRQFLAGS1, RF_IRQFLAGS1_RSSI |
GregCr 0:e6ceb13d2d05 1015 RF_IRQFLAGS1_PREAMBLEDETECT |
GregCr 0:e6ceb13d2d05 1016 RF_IRQFLAGS1_SYNCADDRESSMATCH );
GregCr 0:e6ceb13d2d05 1017 Write( REG_IRQFLAGS2, RF_IRQFLAGS2_FIFOOVERRUN );
GregCr 0:e6ceb13d2d05 1018
GregCr 0:e6ceb13d2d05 1019 if( this->settings.Fsk.RxContinuous == true )
GregCr 0:e6ceb13d2d05 1020 {
GregCr 0:e6ceb13d2d05 1021 // Continuous mode restart Rx chain
GregCr 0:e6ceb13d2d05 1022 Write( REG_RXCONFIG, Read( REG_RXCONFIG ) | RF_RXCONFIG_RESTARTRXWITHOUTPLLLOCK );
GregCr 0:e6ceb13d2d05 1023 }
GregCr 0:e6ceb13d2d05 1024 else
GregCr 0:e6ceb13d2d05 1025 {
GregCr 5:11ec8a6ba4f0 1026 this->settings.State = IDLE;
GregCr 5:11ec8a6ba4f0 1027 rxTimeoutSyncWord.detach( );
GregCr 0:e6ceb13d2d05 1028 }
GregCr 0:e6ceb13d2d05 1029 }
GregCr 0:e6ceb13d2d05 1030 if( ( rxTimeout != NULL ) )
GregCr 0:e6ceb13d2d05 1031 {
GregCr 0:e6ceb13d2d05 1032 rxTimeout( );
GregCr 0:e6ceb13d2d05 1033 }
GregCr 0:e6ceb13d2d05 1034 break;
GregCr 0:e6ceb13d2d05 1035 case TX:
mluis 13:618826a997e2 1036 this->settings.State = IDLE;
GregCr 0:e6ceb13d2d05 1037 if( ( txTimeout != NULL ) )
GregCr 0:e6ceb13d2d05 1038 {
GregCr 0:e6ceb13d2d05 1039 txTimeout( );
GregCr 0:e6ceb13d2d05 1040 }
GregCr 0:e6ceb13d2d05 1041 break;
GregCr 0:e6ceb13d2d05 1042 default:
GregCr 0:e6ceb13d2d05 1043 break;
GregCr 0:e6ceb13d2d05 1044 }
GregCr 0:e6ceb13d2d05 1045 }
GregCr 0:e6ceb13d2d05 1046
GregCr 0:e6ceb13d2d05 1047 void SX1276::OnDio0Irq( void )
GregCr 0:e6ceb13d2d05 1048 {
GregCr 0:e6ceb13d2d05 1049 __IO uint8_t irqFlags = 0;
GregCr 0:e6ceb13d2d05 1050
GregCr 0:e6ceb13d2d05 1051 switch( this->settings.State )
GregCr 0:e6ceb13d2d05 1052 {
GregCr 0:e6ceb13d2d05 1053 case RX:
GregCr 0:e6ceb13d2d05 1054 //TimerStop( &RxTimeoutTimer );
GregCr 0:e6ceb13d2d05 1055 // RxDone interrupt
GregCr 0:e6ceb13d2d05 1056 switch( this->settings.Modem )
GregCr 0:e6ceb13d2d05 1057 {
GregCr 0:e6ceb13d2d05 1058 case MODEM_FSK:
GregCr 0:e6ceb13d2d05 1059 irqFlags = Read( REG_IRQFLAGS2 );
GregCr 0:e6ceb13d2d05 1060 if( ( irqFlags & RF_IRQFLAGS2_CRCOK ) != RF_IRQFLAGS2_CRCOK )
GregCr 0:e6ceb13d2d05 1061 {
GregCr 0:e6ceb13d2d05 1062 // Clear Irqs
GregCr 0:e6ceb13d2d05 1063 Write( REG_IRQFLAGS1, RF_IRQFLAGS1_RSSI |
GregCr 0:e6ceb13d2d05 1064 RF_IRQFLAGS1_PREAMBLEDETECT |
GregCr 0:e6ceb13d2d05 1065 RF_IRQFLAGS1_SYNCADDRESSMATCH );
GregCr 0:e6ceb13d2d05 1066 Write( REG_IRQFLAGS2, RF_IRQFLAGS2_FIFOOVERRUN );
GregCr 0:e6ceb13d2d05 1067
GregCr 0:e6ceb13d2d05 1068 if( this->settings.Fsk.RxContinuous == false )
GregCr 0:e6ceb13d2d05 1069 {
GregCr 0:e6ceb13d2d05 1070 this->settings.State = IDLE;
GregCr 0:e6ceb13d2d05 1071 rxTimeoutSyncWord.attach_us( this, &SX1276::OnTimeoutIrq, ( 8.0 * ( this->settings.Fsk.PreambleLen +
GregCr 0:e6ceb13d2d05 1072 ( ( Read( REG_SYNCCONFIG ) &
GregCr 0:e6ceb13d2d05 1073 ~RF_SYNCCONFIG_SYNCSIZE_MASK ) +
GregCr 0:e6ceb13d2d05 1074 1.0 ) + 1.0 ) /
GregCr 0:e6ceb13d2d05 1075 ( double )this->settings.Fsk.Datarate ) * 1e6 ) ;
GregCr 0:e6ceb13d2d05 1076 }
GregCr 0:e6ceb13d2d05 1077 else
GregCr 0:e6ceb13d2d05 1078 {
GregCr 0:e6ceb13d2d05 1079 // Continuous mode restart Rx chain
GregCr 0:e6ceb13d2d05 1080 Write( REG_RXCONFIG, Read( REG_RXCONFIG ) | RF_RXCONFIG_RESTARTRXWITHOUTPLLLOCK );
GregCr 0:e6ceb13d2d05 1081 }
GregCr 0:e6ceb13d2d05 1082 rxTimeoutTimer.detach( );
GregCr 0:e6ceb13d2d05 1083
GregCr 0:e6ceb13d2d05 1084 if( ( rxError != NULL ) )
GregCr 0:e6ceb13d2d05 1085 {
GregCr 0:e6ceb13d2d05 1086 rxError( );
GregCr 0:e6ceb13d2d05 1087 }
GregCr 0:e6ceb13d2d05 1088 this->settings.FskPacketHandler.PreambleDetected = false;
GregCr 0:e6ceb13d2d05 1089 this->settings.FskPacketHandler.SyncWordDetected = false;
GregCr 0:e6ceb13d2d05 1090 this->settings.FskPacketHandler.NbBytes = 0;
GregCr 0:e6ceb13d2d05 1091 this->settings.FskPacketHandler.Size = 0;
GregCr 0:e6ceb13d2d05 1092 break;
GregCr 0:e6ceb13d2d05 1093 }
GregCr 0:e6ceb13d2d05 1094
GregCr 0:e6ceb13d2d05 1095 // Read received packet size
GregCr 0:e6ceb13d2d05 1096 if( ( this->settings.FskPacketHandler.Size == 0 ) && ( this->settings.FskPacketHandler.NbBytes == 0 ) )
GregCr 0:e6ceb13d2d05 1097 {
GregCr 0:e6ceb13d2d05 1098 if( this->settings.Fsk.FixLen == false )
GregCr 0:e6ceb13d2d05 1099 {
GregCr 0:e6ceb13d2d05 1100 ReadFifo( ( uint8_t* )&this->settings.FskPacketHandler.Size, 1 );
GregCr 0:e6ceb13d2d05 1101 }
GregCr 0:e6ceb13d2d05 1102 else
GregCr 0:e6ceb13d2d05 1103 {
GregCr 0:e6ceb13d2d05 1104 this->settings.FskPacketHandler.Size = Read( REG_PAYLOADLENGTH );
GregCr 0:e6ceb13d2d05 1105 }
GregCr 0:e6ceb13d2d05 1106 ReadFifo( rxBuffer + this->settings.FskPacketHandler.NbBytes, this->settings.FskPacketHandler.Size - this->settings.FskPacketHandler.NbBytes );
GregCr 0:e6ceb13d2d05 1107 this->settings.FskPacketHandler.NbBytes += ( this->settings.FskPacketHandler.Size - this->settings.FskPacketHandler.NbBytes );
GregCr 0:e6ceb13d2d05 1108 }
GregCr 0:e6ceb13d2d05 1109 else
GregCr 0:e6ceb13d2d05 1110 {
GregCr 0:e6ceb13d2d05 1111 ReadFifo( rxBuffer + this->settings.FskPacketHandler.NbBytes, this->settings.FskPacketHandler.Size - this->settings.FskPacketHandler.NbBytes );
GregCr 0:e6ceb13d2d05 1112 this->settings.FskPacketHandler.NbBytes += ( this->settings.FskPacketHandler.Size - this->settings.FskPacketHandler.NbBytes );
GregCr 0:e6ceb13d2d05 1113 }
GregCr 0:e6ceb13d2d05 1114
GregCr 0:e6ceb13d2d05 1115 if( this->settings.Fsk.RxContinuous == false )
GregCr 0:e6ceb13d2d05 1116 {
GregCr 0:e6ceb13d2d05 1117 this->settings.State = IDLE;
GregCr 0:e6ceb13d2d05 1118 rxTimeoutSyncWord.attach_us( this, &SX1276::OnTimeoutIrq, ( 8.0 * ( this->settings.Fsk.PreambleLen +
GregCr 0:e6ceb13d2d05 1119 ( ( Read( REG_SYNCCONFIG ) &
GregCr 0:e6ceb13d2d05 1120 ~RF_SYNCCONFIG_SYNCSIZE_MASK ) +
GregCr 0:e6ceb13d2d05 1121 1.0 ) + 1.0 ) /
GregCr 0:e6ceb13d2d05 1122 ( double )this->settings.Fsk.Datarate ) * 1e6 ) ;
GregCr 0:e6ceb13d2d05 1123 }
GregCr 0:e6ceb13d2d05 1124 else
GregCr 0:e6ceb13d2d05 1125 {
GregCr 0:e6ceb13d2d05 1126 // Continuous mode restart Rx chain
GregCr 0:e6ceb13d2d05 1127 Write( REG_RXCONFIG, Read( REG_RXCONFIG ) | RF_RXCONFIG_RESTARTRXWITHOUTPLLLOCK );
GregCr 0:e6ceb13d2d05 1128 }
GregCr 0:e6ceb13d2d05 1129 rxTimeoutTimer.detach( );
GregCr 0:e6ceb13d2d05 1130
GregCr 0:e6ceb13d2d05 1131 if( (rxDone != NULL ) )
GregCr 0:e6ceb13d2d05 1132 {
GregCr 0:e6ceb13d2d05 1133 rxDone( rxBuffer, this->settings.FskPacketHandler.Size, this->settings.FskPacketHandler.RssiValue, 0 );
GregCr 0:e6ceb13d2d05 1134 }
GregCr 0:e6ceb13d2d05 1135 this->settings.FskPacketHandler.PreambleDetected = false;
GregCr 0:e6ceb13d2d05 1136 this->settings.FskPacketHandler.SyncWordDetected = false;
GregCr 0:e6ceb13d2d05 1137 this->settings.FskPacketHandler.NbBytes = 0;
GregCr 0:e6ceb13d2d05 1138 this->settings.FskPacketHandler.Size = 0;
GregCr 0:e6ceb13d2d05 1139 break;
GregCr 0:e6ceb13d2d05 1140 case MODEM_LORA:
GregCr 0:e6ceb13d2d05 1141 {
GregCr 0:e6ceb13d2d05 1142 uint8_t snr = 0;
GregCr 0:e6ceb13d2d05 1143
GregCr 0:e6ceb13d2d05 1144 // Clear Irq
GregCr 0:e6ceb13d2d05 1145 Write( REG_LR_IRQFLAGS, RFLR_IRQFLAGS_RXDONE );
GregCr 0:e6ceb13d2d05 1146
GregCr 0:e6ceb13d2d05 1147 irqFlags = Read( REG_LR_IRQFLAGS );
GregCr 0:e6ceb13d2d05 1148 if( ( irqFlags & RFLR_IRQFLAGS_PAYLOADCRCERROR_MASK ) == RFLR_IRQFLAGS_PAYLOADCRCERROR )
GregCr 0:e6ceb13d2d05 1149 {
GregCr 0:e6ceb13d2d05 1150 // Clear Irq
GregCr 0:e6ceb13d2d05 1151 Write( REG_LR_IRQFLAGS, RFLR_IRQFLAGS_PAYLOADCRCERROR );
GregCr 0:e6ceb13d2d05 1152
GregCr 0:e6ceb13d2d05 1153 if( this->settings.LoRa.RxContinuous == false )
GregCr 0:e6ceb13d2d05 1154 {
GregCr 0:e6ceb13d2d05 1155 this->settings.State = IDLE;
GregCr 0:e6ceb13d2d05 1156 }
GregCr 0:e6ceb13d2d05 1157 rxTimeoutTimer.detach( );
GregCr 0:e6ceb13d2d05 1158
GregCr 4:f0ce52e94d3f 1159 if( ( rxError != NULL ) )
GregCr 0:e6ceb13d2d05 1160 {
GregCr 0:e6ceb13d2d05 1161 rxError( );
GregCr 0:e6ceb13d2d05 1162 }
GregCr 0:e6ceb13d2d05 1163 break;
GregCr 0:e6ceb13d2d05 1164 }
GregCr 0:e6ceb13d2d05 1165
GregCr 0:e6ceb13d2d05 1166 this->settings.LoRaPacketHandler.SnrValue = Read( REG_LR_PKTSNRVALUE );
GregCr 0:e6ceb13d2d05 1167 if( this->settings.LoRaPacketHandler.SnrValue & 0x80 ) // The SNR sign bit is 1
GregCr 0:e6ceb13d2d05 1168 {
GregCr 0:e6ceb13d2d05 1169 // Invert and divide by 4
GregCr 0:e6ceb13d2d05 1170 snr = ( ( ~this->settings.LoRaPacketHandler.SnrValue + 1 ) & 0xFF ) >> 2;
GregCr 0:e6ceb13d2d05 1171 snr = -snr;
GregCr 0:e6ceb13d2d05 1172 }
GregCr 0:e6ceb13d2d05 1173 else
GregCr 0:e6ceb13d2d05 1174 {
GregCr 0:e6ceb13d2d05 1175 // Divide by 4
GregCr 0:e6ceb13d2d05 1176 snr = ( this->settings.LoRaPacketHandler.SnrValue & 0xFF ) >> 2;
GregCr 0:e6ceb13d2d05 1177 }
GregCr 0:e6ceb13d2d05 1178
GregCr 7:2b555111463f 1179 int16_t rssi = Read( REG_LR_PKTRSSIVALUE );
GregCr 0:e6ceb13d2d05 1180 if( this->settings.LoRaPacketHandler.SnrValue < 0 )
GregCr 0:e6ceb13d2d05 1181 {
GregCr 0:e6ceb13d2d05 1182 if( this->settings.Channel > RF_MID_BAND_THRESH )
GregCr 0:e6ceb13d2d05 1183 {
GregCr 0:e6ceb13d2d05 1184 this->settings.LoRaPacketHandler.RssiValue = RSSI_OFFSET_HF + rssi + ( rssi >> 4 ) +
GregCr 0:e6ceb13d2d05 1185 snr;
GregCr 0:e6ceb13d2d05 1186 }
GregCr 0:e6ceb13d2d05 1187 else
GregCr 0:e6ceb13d2d05 1188 {
GregCr 0:e6ceb13d2d05 1189 this->settings.LoRaPacketHandler.RssiValue = RSSI_OFFSET_LF + rssi + ( rssi >> 4 ) +
GregCr 0:e6ceb13d2d05 1190 snr;
GregCr 0:e6ceb13d2d05 1191 }
GregCr 0:e6ceb13d2d05 1192 }
GregCr 0:e6ceb13d2d05 1193 else
GregCr 0:e6ceb13d2d05 1194 {
GregCr 0:e6ceb13d2d05 1195 if( this->settings.Channel > RF_MID_BAND_THRESH )
GregCr 0:e6ceb13d2d05 1196 {
GregCr 0:e6ceb13d2d05 1197 this->settings.LoRaPacketHandler.RssiValue = RSSI_OFFSET_HF + rssi + ( rssi >> 4 );
GregCr 0:e6ceb13d2d05 1198 }
GregCr 0:e6ceb13d2d05 1199 else
GregCr 0:e6ceb13d2d05 1200 {
GregCr 0:e6ceb13d2d05 1201 this->settings.LoRaPacketHandler.RssiValue = RSSI_OFFSET_LF + rssi + ( rssi >> 4 );
GregCr 0:e6ceb13d2d05 1202 }
GregCr 0:e6ceb13d2d05 1203 }
GregCr 0:e6ceb13d2d05 1204
GregCr 0:e6ceb13d2d05 1205 this->settings.LoRaPacketHandler.Size = Read( REG_LR_RXNBBYTES );
GregCr 0:e6ceb13d2d05 1206 ReadFifo( rxBuffer, this->settings.LoRaPacketHandler.Size );
GregCr 0:e6ceb13d2d05 1207
GregCr 0:e6ceb13d2d05 1208 if( this->settings.LoRa.RxContinuous == false )
GregCr 0:e6ceb13d2d05 1209 {
GregCr 0:e6ceb13d2d05 1210 this->settings.State = IDLE;
GregCr 0:e6ceb13d2d05 1211 }
GregCr 0:e6ceb13d2d05 1212 rxTimeoutTimer.detach( );
GregCr 0:e6ceb13d2d05 1213
GregCr 0:e6ceb13d2d05 1214 if( ( rxDone != NULL ) )
GregCr 0:e6ceb13d2d05 1215 {
GregCr 0:e6ceb13d2d05 1216 rxDone( rxBuffer, this->settings.LoRaPacketHandler.Size, this->settings.LoRaPacketHandler.RssiValue, this->settings.LoRaPacketHandler.SnrValue );
GregCr 0:e6ceb13d2d05 1217 }
GregCr 0:e6ceb13d2d05 1218 }
GregCr 0:e6ceb13d2d05 1219 break;
GregCr 0:e6ceb13d2d05 1220 default:
GregCr 0:e6ceb13d2d05 1221 break;
GregCr 0:e6ceb13d2d05 1222 }
GregCr 0:e6ceb13d2d05 1223 break;
GregCr 0:e6ceb13d2d05 1224 case TX:
GregCr 0:e6ceb13d2d05 1225 txTimeoutTimer.detach( );
GregCr 0:e6ceb13d2d05 1226 // TxDone interrupt
GregCr 0:e6ceb13d2d05 1227 switch( this->settings.Modem )
GregCr 0:e6ceb13d2d05 1228 {
GregCr 0:e6ceb13d2d05 1229 case MODEM_LORA:
GregCr 0:e6ceb13d2d05 1230 // Clear Irq
GregCr 0:e6ceb13d2d05 1231 Write( REG_LR_IRQFLAGS, RFLR_IRQFLAGS_TXDONE );
GregCr 0:e6ceb13d2d05 1232 // Intentional fall through
GregCr 0:e6ceb13d2d05 1233 case MODEM_FSK:
GregCr 0:e6ceb13d2d05 1234 default:
GregCr 0:e6ceb13d2d05 1235 this->settings.State = IDLE;
GregCr 0:e6ceb13d2d05 1236 if( ( txDone != NULL ) )
GregCr 0:e6ceb13d2d05 1237 {
GregCr 0:e6ceb13d2d05 1238 txDone( );
GregCr 0:e6ceb13d2d05 1239 }
GregCr 0:e6ceb13d2d05 1240 break;
GregCr 0:e6ceb13d2d05 1241 }
GregCr 0:e6ceb13d2d05 1242 break;
GregCr 0:e6ceb13d2d05 1243 default:
GregCr 0:e6ceb13d2d05 1244 break;
GregCr 0:e6ceb13d2d05 1245 }
GregCr 0:e6ceb13d2d05 1246 }
GregCr 0:e6ceb13d2d05 1247
GregCr 0:e6ceb13d2d05 1248 void SX1276::OnDio1Irq( void )
GregCr 0:e6ceb13d2d05 1249 {
GregCr 0:e6ceb13d2d05 1250 switch( this->settings.State )
GregCr 0:e6ceb13d2d05 1251 {
GregCr 0:e6ceb13d2d05 1252 case RX:
GregCr 0:e6ceb13d2d05 1253 switch( this->settings.Modem )
GregCr 0:e6ceb13d2d05 1254 {
GregCr 0:e6ceb13d2d05 1255 case MODEM_FSK:
GregCr 0:e6ceb13d2d05 1256 // FifoLevel interrupt
GregCr 0:e6ceb13d2d05 1257 // Read received packet size
GregCr 0:e6ceb13d2d05 1258 if( ( this->settings.FskPacketHandler.Size == 0 ) && ( this->settings.FskPacketHandler.NbBytes == 0 ) )
GregCr 0:e6ceb13d2d05 1259 {
GregCr 0:e6ceb13d2d05 1260 if( this->settings.Fsk.FixLen == false )
GregCr 0:e6ceb13d2d05 1261 {
GregCr 0:e6ceb13d2d05 1262 ReadFifo( ( uint8_t* )&this->settings.FskPacketHandler.Size, 1 );
GregCr 0:e6ceb13d2d05 1263 }
GregCr 0:e6ceb13d2d05 1264 else
GregCr 0:e6ceb13d2d05 1265 {
GregCr 0:e6ceb13d2d05 1266 this->settings.FskPacketHandler.Size = Read( REG_PAYLOADLENGTH );
GregCr 0:e6ceb13d2d05 1267 }
GregCr 0:e6ceb13d2d05 1268 }
GregCr 0:e6ceb13d2d05 1269
GregCr 0:e6ceb13d2d05 1270 if( ( this->settings.FskPacketHandler.Size - this->settings.FskPacketHandler.NbBytes ) > this->settings.FskPacketHandler.FifoThresh )
GregCr 0:e6ceb13d2d05 1271 {
GregCr 0:e6ceb13d2d05 1272 ReadFifo( ( rxBuffer + this->settings.FskPacketHandler.NbBytes ), this->settings.FskPacketHandler.FifoThresh );
GregCr 0:e6ceb13d2d05 1273 this->settings.FskPacketHandler.NbBytes += this->settings.FskPacketHandler.FifoThresh;
GregCr 0:e6ceb13d2d05 1274 }
GregCr 0:e6ceb13d2d05 1275 else
GregCr 0:e6ceb13d2d05 1276 {
GregCr 0:e6ceb13d2d05 1277 ReadFifo( ( rxBuffer + this->settings.FskPacketHandler.NbBytes ), this->settings.FskPacketHandler.Size - this->settings.FskPacketHandler.NbBytes );
GregCr 0:e6ceb13d2d05 1278 this->settings.FskPacketHandler.NbBytes += ( this->settings.FskPacketHandler.Size - this->settings.FskPacketHandler.NbBytes );
GregCr 0:e6ceb13d2d05 1279 }
GregCr 0:e6ceb13d2d05 1280 break;
GregCr 0:e6ceb13d2d05 1281 case MODEM_LORA:
GregCr 0:e6ceb13d2d05 1282 // Sync time out
GregCr 0:e6ceb13d2d05 1283 rxTimeoutTimer.detach( );
GregCr 0:e6ceb13d2d05 1284 this->settings.State = IDLE;
GregCr 0:e6ceb13d2d05 1285 if( ( rxTimeout != NULL ) )
GregCr 0:e6ceb13d2d05 1286 {
GregCr 0:e6ceb13d2d05 1287 rxTimeout( );
GregCr 0:e6ceb13d2d05 1288 }
GregCr 0:e6ceb13d2d05 1289 break;
GregCr 0:e6ceb13d2d05 1290 default:
GregCr 0:e6ceb13d2d05 1291 break;
GregCr 0:e6ceb13d2d05 1292 }
GregCr 0:e6ceb13d2d05 1293 break;
GregCr 0:e6ceb13d2d05 1294 case TX:
GregCr 0:e6ceb13d2d05 1295 switch( this->settings.Modem )
GregCr 0:e6ceb13d2d05 1296 {
GregCr 0:e6ceb13d2d05 1297 case MODEM_FSK:
GregCr 0:e6ceb13d2d05 1298 // FifoLevel interrupt
GregCr 0:e6ceb13d2d05 1299 if( ( this->settings.FskPacketHandler.Size - this->settings.FskPacketHandler.NbBytes ) > this->settings.FskPacketHandler.ChunkSize )
GregCr 0:e6ceb13d2d05 1300 {
GregCr 0:e6ceb13d2d05 1301 WriteFifo( ( rxBuffer + this->settings.FskPacketHandler.NbBytes ), this->settings.FskPacketHandler.ChunkSize );
GregCr 0:e6ceb13d2d05 1302 this->settings.FskPacketHandler.NbBytes += this->settings.FskPacketHandler.ChunkSize;
GregCr 0:e6ceb13d2d05 1303 }
GregCr 0:e6ceb13d2d05 1304 else
GregCr 0:e6ceb13d2d05 1305 {
GregCr 0:e6ceb13d2d05 1306 // Write the last chunk of data
GregCr 0:e6ceb13d2d05 1307 WriteFifo( rxBuffer + this->settings.FskPacketHandler.NbBytes, this->settings.FskPacketHandler.Size - this->settings.FskPacketHandler.NbBytes );
GregCr 0:e6ceb13d2d05 1308 this->settings.FskPacketHandler.NbBytes += this->settings.FskPacketHandler.Size - this->settings.FskPacketHandler.NbBytes;
GregCr 0:e6ceb13d2d05 1309 }
GregCr 0:e6ceb13d2d05 1310 break;
GregCr 0:e6ceb13d2d05 1311 case MODEM_LORA:
GregCr 0:e6ceb13d2d05 1312 break;
GregCr 0:e6ceb13d2d05 1313 default:
GregCr 0:e6ceb13d2d05 1314 break;
GregCr 0:e6ceb13d2d05 1315 }
GregCr 0:e6ceb13d2d05 1316 break;
GregCr 0:e6ceb13d2d05 1317 default:
GregCr 0:e6ceb13d2d05 1318 break;
GregCr 0:e6ceb13d2d05 1319 }
GregCr 0:e6ceb13d2d05 1320 }
GregCr 0:e6ceb13d2d05 1321
GregCr 0:e6ceb13d2d05 1322 void SX1276::OnDio2Irq( void )
GregCr 0:e6ceb13d2d05 1323 {
GregCr 0:e6ceb13d2d05 1324 switch( this->settings.State )
GregCr 0:e6ceb13d2d05 1325 {
GregCr 0:e6ceb13d2d05 1326 case RX:
GregCr 0:e6ceb13d2d05 1327 switch( this->settings.Modem )
GregCr 0:e6ceb13d2d05 1328 {
GregCr 0:e6ceb13d2d05 1329 case MODEM_FSK:
GregCr 0:e6ceb13d2d05 1330 if( ( this->settings.FskPacketHandler.PreambleDetected == true ) && ( this->settings.FskPacketHandler.SyncWordDetected == false ) )
GregCr 0:e6ceb13d2d05 1331 {
GregCr 0:e6ceb13d2d05 1332 rxTimeoutSyncWord.detach( );
GregCr 0:e6ceb13d2d05 1333
GregCr 0:e6ceb13d2d05 1334 this->settings.FskPacketHandler.SyncWordDetected = true;
GregCr 0:e6ceb13d2d05 1335
GregCr 0:e6ceb13d2d05 1336 this->settings.FskPacketHandler.RssiValue = -( Read( REG_RSSIVALUE ) >> 1 );
GregCr 0:e6ceb13d2d05 1337
GregCr 0:e6ceb13d2d05 1338 this->settings.FskPacketHandler.AfcValue = ( int32_t )( double )( ( ( uint16_t )Read( REG_AFCMSB ) << 8 ) |
GregCr 0:e6ceb13d2d05 1339 ( uint16_t )Read( REG_AFCLSB ) ) *
GregCr 0:e6ceb13d2d05 1340 ( double )FREQ_STEP;
GregCr 0:e6ceb13d2d05 1341 this->settings.FskPacketHandler.RxGain = ( Read( REG_LNA ) >> 5 ) & 0x07;
GregCr 0:e6ceb13d2d05 1342 }
GregCr 0:e6ceb13d2d05 1343 break;
GregCr 0:e6ceb13d2d05 1344 case MODEM_LORA:
GregCr 6:e7f02929cd3d 1345 if( this->settings.LoRa.FreqHopOn == true )
GregCr 6:e7f02929cd3d 1346 {
GregCr 6:e7f02929cd3d 1347 // Clear Irq
GregCr 6:e7f02929cd3d 1348 Write( REG_LR_IRQFLAGS, RFLR_IRQFLAGS_FHSSCHANGEDCHANNEL );
GregCr 6:e7f02929cd3d 1349
mluis 13:618826a997e2 1350 if( ( fhssChangeChannel != NULL ) )
mluis 13:618826a997e2 1351 {
mluis 13:618826a997e2 1352 fhssChangeChannel( ( Read( REG_LR_HOPCHANNEL ) & RFLR_HOPCHANNEL_CHANNEL_MASK ) );
mluis 13:618826a997e2 1353 }
GregCr 6:e7f02929cd3d 1354 }
GregCr 0:e6ceb13d2d05 1355 break;
GregCr 0:e6ceb13d2d05 1356 default:
GregCr 0:e6ceb13d2d05 1357 break;
GregCr 0:e6ceb13d2d05 1358 }
GregCr 0:e6ceb13d2d05 1359 break;
GregCr 0:e6ceb13d2d05 1360 case TX:
GregCr 0:e6ceb13d2d05 1361 switch( this->settings.Modem )
GregCr 0:e6ceb13d2d05 1362 {
GregCr 0:e6ceb13d2d05 1363 case MODEM_FSK:
GregCr 0:e6ceb13d2d05 1364 break;
GregCr 0:e6ceb13d2d05 1365 case MODEM_LORA:
GregCr 6:e7f02929cd3d 1366 if( this->settings.LoRa.FreqHopOn == true )
GregCr 6:e7f02929cd3d 1367 {
GregCr 6:e7f02929cd3d 1368 // Clear Irq
GregCr 6:e7f02929cd3d 1369 Write( REG_LR_IRQFLAGS, RFLR_IRQFLAGS_FHSSCHANGEDCHANNEL );
GregCr 6:e7f02929cd3d 1370
mluis 13:618826a997e2 1371 if( ( fhssChangeChannel != NULL ) )
mluis 13:618826a997e2 1372 {
mluis 13:618826a997e2 1373 fhssChangeChannel( ( Read( REG_LR_HOPCHANNEL ) & RFLR_HOPCHANNEL_CHANNEL_MASK ) );
mluis 13:618826a997e2 1374 }
GregCr 6:e7f02929cd3d 1375 }
GregCr 0:e6ceb13d2d05 1376 break;
GregCr 0:e6ceb13d2d05 1377 default:
GregCr 0:e6ceb13d2d05 1378 break;
GregCr 0:e6ceb13d2d05 1379 }
GregCr 0:e6ceb13d2d05 1380 break;
GregCr 0:e6ceb13d2d05 1381 default:
GregCr 0:e6ceb13d2d05 1382 break;
GregCr 0:e6ceb13d2d05 1383 }
GregCr 0:e6ceb13d2d05 1384 }
GregCr 0:e6ceb13d2d05 1385
GregCr 0:e6ceb13d2d05 1386 void SX1276::OnDio3Irq( void )
GregCr 0:e6ceb13d2d05 1387 {
GregCr 0:e6ceb13d2d05 1388 switch( this->settings.Modem )
GregCr 0:e6ceb13d2d05 1389 {
GregCr 0:e6ceb13d2d05 1390 case MODEM_FSK:
GregCr 0:e6ceb13d2d05 1391 break;
GregCr 0:e6ceb13d2d05 1392 case MODEM_LORA:
mluis 13:618826a997e2 1393 if( ( Read( REG_LR_IRQFLAGS ) & 0x01 ) == 0x01 )
mluis 13:618826a997e2 1394 {
mluis 13:618826a997e2 1395 // Clear Irq
mluis 13:618826a997e2 1396 Write( REG_LR_IRQFLAGS, RFLR_IRQFLAGS_CADDETECTED_MASK | RFLR_IRQFLAGS_CADDONE);
mluis 13:618826a997e2 1397 if( ( cadDone != NULL ) )
mluis 13:618826a997e2 1398 {
mluis 13:618826a997e2 1399 cadDone( true );
mluis 13:618826a997e2 1400 }
GregCr 12:aa5b3bf7fdf4 1401 }
GregCr 12:aa5b3bf7fdf4 1402 else
mluis 13:618826a997e2 1403 {
mluis 13:618826a997e2 1404 // Clear Irq
mluis 13:618826a997e2 1405 Write( REG_LR_IRQFLAGS, RFLR_IRQFLAGS_CADDONE );
mluis 13:618826a997e2 1406 if( ( cadDone != NULL ) )
mluis 13:618826a997e2 1407 {
mluis 13:618826a997e2 1408 cadDone( false );
mluis 13:618826a997e2 1409 }
GregCr 7:2b555111463f 1410 }
GregCr 0:e6ceb13d2d05 1411 break;
GregCr 0:e6ceb13d2d05 1412 default:
GregCr 0:e6ceb13d2d05 1413 break;
GregCr 0:e6ceb13d2d05 1414 }
GregCr 0:e6ceb13d2d05 1415 }
GregCr 0:e6ceb13d2d05 1416
GregCr 0:e6ceb13d2d05 1417 void SX1276::OnDio4Irq( void )
GregCr 0:e6ceb13d2d05 1418 {
GregCr 0:e6ceb13d2d05 1419 switch( this->settings.Modem )
GregCr 0:e6ceb13d2d05 1420 {
GregCr 0:e6ceb13d2d05 1421 case MODEM_FSK:
GregCr 0:e6ceb13d2d05 1422 {
GregCr 0:e6ceb13d2d05 1423 if( this->settings.FskPacketHandler.PreambleDetected == false )
GregCr 0:e6ceb13d2d05 1424 {
GregCr 0:e6ceb13d2d05 1425 this->settings.FskPacketHandler.PreambleDetected = true;
GregCr 0:e6ceb13d2d05 1426 }
GregCr 0:e6ceb13d2d05 1427 }
GregCr 0:e6ceb13d2d05 1428 break;
GregCr 0:e6ceb13d2d05 1429 case MODEM_LORA:
GregCr 0:e6ceb13d2d05 1430 break;
GregCr 0:e6ceb13d2d05 1431 default:
GregCr 0:e6ceb13d2d05 1432 break;
GregCr 0:e6ceb13d2d05 1433 }
GregCr 0:e6ceb13d2d05 1434 }
GregCr 0:e6ceb13d2d05 1435
GregCr 0:e6ceb13d2d05 1436 void SX1276::OnDio5Irq( void )
GregCr 0:e6ceb13d2d05 1437 {
GregCr 0:e6ceb13d2d05 1438 switch( this->settings.Modem )
GregCr 0:e6ceb13d2d05 1439 {
GregCr 0:e6ceb13d2d05 1440 case MODEM_FSK:
GregCr 0:e6ceb13d2d05 1441 break;
GregCr 0:e6ceb13d2d05 1442 case MODEM_LORA:
GregCr 0:e6ceb13d2d05 1443 break;
GregCr 0:e6ceb13d2d05 1444 default:
GregCr 0:e6ceb13d2d05 1445 break;
GregCr 0:e6ceb13d2d05 1446 }
mluis 13:618826a997e2 1447 }