CRAC Team / CRAC-Strat_2017_HOMOLOGATION_PETIT_ROBOT

code petit robot pour homologation

Fork of CRAC-Strat_2017_V2 by CRAC Team

mbed/LPC1768/LPC17xx.h@0:ad97421fb1fb, 2016-04-13 (annotated)

Committer:
antbig
Date:
Wed Apr 13 22:04:54 2016 +0000
Revision:
0:ad97421fb1fb
Ajout interruption fin de match

Who changed what in which revision?

UserRevisionLine numberNew contents of line
antbig 0:ad97421fb1fb 1 /**************************************************************************//**
antbig 0:ad97421fb1fb 2 * @file LPC17xx.h
antbig 0:ad97421fb1fb 3 * @brief CMSIS Cortex-M3 Core Peripheral Access Layer Header File for
antbig 0:ad97421fb1fb 4 * NXP LPC17xx Device Series
antbig 0:ad97421fb1fb 5 * @version: V1.09
antbig 0:ad97421fb1fb 6 * @date: 17. March 2010
antbig 0:ad97421fb1fb 7
antbig 0:ad97421fb1fb 8 *
antbig 0:ad97421fb1fb 9 * @note
antbig 0:ad97421fb1fb 10 * Copyright (C) 2009 ARM Limited. All rights reserved.
antbig 0:ad97421fb1fb 11 *
antbig 0:ad97421fb1fb 12 * @par
antbig 0:ad97421fb1fb 13 * ARM Limited (ARM) is supplying this software for use with Cortex-M
antbig 0:ad97421fb1fb 14 * processor based microcontrollers. This file can be freely distributed
antbig 0:ad97421fb1fb 15 * within development tools that are supporting such ARM based processors.
antbig 0:ad97421fb1fb 16 *
antbig 0:ad97421fb1fb 17 * @par
antbig 0:ad97421fb1fb 18 * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
antbig 0:ad97421fb1fb 19 * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
antbig 0:ad97421fb1fb 20 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
antbig 0:ad97421fb1fb 21 * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
antbig 0:ad97421fb1fb 22 * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
antbig 0:ad97421fb1fb 23 *
antbig 0:ad97421fb1fb 24 ******************************************************************************/
antbig 0:ad97421fb1fb 25
antbig 0:ad97421fb1fb 26
antbig 0:ad97421fb1fb 27 #ifndef __LPC17xx_H__
antbig 0:ad97421fb1fb 28 #define __LPC17xx_H__
antbig 0:ad97421fb1fb 29
antbig 0:ad97421fb1fb 30 /*
antbig 0:ad97421fb1fb 31 * ==========================================================================
antbig 0:ad97421fb1fb 32 * ---------- Interrupt Number Definition -----------------------------------
antbig 0:ad97421fb1fb 33 * ==========================================================================
antbig 0:ad97421fb1fb 34 */
antbig 0:ad97421fb1fb 35
antbig 0:ad97421fb1fb 36 typedef enum IRQn
antbig 0:ad97421fb1fb 37 {
antbig 0:ad97421fb1fb 38 /****** Cortex-M3 Processor Exceptions Numbers ***************************************************/
antbig 0:ad97421fb1fb 39 NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */
antbig 0:ad97421fb1fb 40 MemoryManagement_IRQn = -12, /*!< 4 Cortex-M3 Memory Management Interrupt */
antbig 0:ad97421fb1fb 41 BusFault_IRQn = -11, /*!< 5 Cortex-M3 Bus Fault Interrupt */
antbig 0:ad97421fb1fb 42 UsageFault_IRQn = -10, /*!< 6 Cortex-M3 Usage Fault Interrupt */
antbig 0:ad97421fb1fb 43 SVCall_IRQn = -5, /*!< 11 Cortex-M3 SV Call Interrupt */
antbig 0:ad97421fb1fb 44 DebugMonitor_IRQn = -4, /*!< 12 Cortex-M3 Debug Monitor Interrupt */
antbig 0:ad97421fb1fb 45 PendSV_IRQn = -2, /*!< 14 Cortex-M3 Pend SV Interrupt */
antbig 0:ad97421fb1fb 46 SysTick_IRQn = -1, /*!< 15 Cortex-M3 System Tick Interrupt */
antbig 0:ad97421fb1fb 47
antbig 0:ad97421fb1fb 48 /****** LPC17xx Specific Interrupt Numbers *******************************************************/
antbig 0:ad97421fb1fb 49 WDT_IRQn = 0, /*!< Watchdog Timer Interrupt */
antbig 0:ad97421fb1fb 50 TIMER0_IRQn = 1, /*!< Timer0 Interrupt */
antbig 0:ad97421fb1fb 51 TIMER1_IRQn = 2, /*!< Timer1 Interrupt */
antbig 0:ad97421fb1fb 52 TIMER2_IRQn = 3, /*!< Timer2 Interrupt */
antbig 0:ad97421fb1fb 53 TIMER3_IRQn = 4, /*!< Timer3 Interrupt */
antbig 0:ad97421fb1fb 54 UART0_IRQn = 5, /*!< UART0 Interrupt */
antbig 0:ad97421fb1fb 55 UART1_IRQn = 6, /*!< UART1 Interrupt */
antbig 0:ad97421fb1fb 56 UART2_IRQn = 7, /*!< UART2 Interrupt */
antbig 0:ad97421fb1fb 57 UART3_IRQn = 8, /*!< UART3 Interrupt */
antbig 0:ad97421fb1fb 58 PWM1_IRQn = 9, /*!< PWM1 Interrupt */
antbig 0:ad97421fb1fb 59 I2C0_IRQn = 10, /*!< I2C0 Interrupt */
antbig 0:ad97421fb1fb 60 I2C1_IRQn = 11, /*!< I2C1 Interrupt */
antbig 0:ad97421fb1fb 61 I2C2_IRQn = 12, /*!< I2C2 Interrupt */
antbig 0:ad97421fb1fb 62 SPI_IRQn = 13, /*!< SPI Interrupt */
antbig 0:ad97421fb1fb 63 SSP0_IRQn = 14, /*!< SSP0 Interrupt */
antbig 0:ad97421fb1fb 64 SSP1_IRQn = 15, /*!< SSP1 Interrupt */
antbig 0:ad97421fb1fb 65 PLL0_IRQn = 16, /*!< PLL0 Lock (Main PLL) Interrupt */
antbig 0:ad97421fb1fb 66 RTC_IRQn = 17, /*!< Real Time Clock Interrupt */
antbig 0:ad97421fb1fb 67 EINT0_IRQn = 18, /*!< External Interrupt 0 Interrupt */
antbig 0:ad97421fb1fb 68 EINT1_IRQn = 19, /*!< External Interrupt 1 Interrupt */
antbig 0:ad97421fb1fb 69 EINT2_IRQn = 20, /*!< External Interrupt 2 Interrupt */
antbig 0:ad97421fb1fb 70 EINT3_IRQn = 21, /*!< External Interrupt 3 Interrupt */
antbig 0:ad97421fb1fb 71 ADC_IRQn = 22, /*!< A/D Converter Interrupt */
antbig 0:ad97421fb1fb 72 BOD_IRQn = 23, /*!< Brown-Out Detect Interrupt */
antbig 0:ad97421fb1fb 73 USB_IRQn = 24, /*!< USB Interrupt */
antbig 0:ad97421fb1fb 74 CAN_IRQn = 25, /*!< CAN Interrupt */
antbig 0:ad97421fb1fb 75 DMA_IRQn = 26, /*!< General Purpose DMA Interrupt */
antbig 0:ad97421fb1fb 76 I2S_IRQn = 27, /*!< I2S Interrupt */
antbig 0:ad97421fb1fb 77 ENET_IRQn = 28, /*!< Ethernet Interrupt */
antbig 0:ad97421fb1fb 78 RIT_IRQn = 29, /*!< Repetitive Interrupt Timer Interrupt */
antbig 0:ad97421fb1fb 79 MCPWM_IRQn = 30, /*!< Motor Control PWM Interrupt */
antbig 0:ad97421fb1fb 80 QEI_IRQn = 31, /*!< Quadrature Encoder Interface Interrupt */
antbig 0:ad97421fb1fb 81 PLL1_IRQn = 32, /*!< PLL1 Lock (USB PLL) Interrupt */
antbig 0:ad97421fb1fb 82 USBActivity_IRQn = 33, /* USB Activity interrupt */
antbig 0:ad97421fb1fb 83 CANActivity_IRQn = 34, /* CAN Activity interrupt */
antbig 0:ad97421fb1fb 84 } IRQn_Type;
antbig 0:ad97421fb1fb 85
antbig 0:ad97421fb1fb 86
antbig 0:ad97421fb1fb 87 /*
antbig 0:ad97421fb1fb 88 * ==========================================================================
antbig 0:ad97421fb1fb 89 * ----------- Processor and Core Peripheral Section ------------------------
antbig 0:ad97421fb1fb 90 * ==========================================================================
antbig 0:ad97421fb1fb 91 */
antbig 0:ad97421fb1fb 92
antbig 0:ad97421fb1fb 93 /* Configuration of the Cortex-M3 Processor and Core Peripherals */
antbig 0:ad97421fb1fb 94 #define __MPU_PRESENT 1 /*!< MPU present or not */
antbig 0:ad97421fb1fb 95 #define __NVIC_PRIO_BITS 5 /*!< Number of Bits used for Priority Levels */
antbig 0:ad97421fb1fb 96 #define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
antbig 0:ad97421fb1fb 97
antbig 0:ad97421fb1fb 98
antbig 0:ad97421fb1fb 99 #include "core_cm3.h" /* Cortex-M3 processor and core peripherals */
antbig 0:ad97421fb1fb 100 #include "system_LPC17xx.h" /* System Header */
antbig 0:ad97421fb1fb 101
antbig 0:ad97421fb1fb 102
antbig 0:ad97421fb1fb 103 /******************************************************************************/
antbig 0:ad97421fb1fb 104 /* Device Specific Peripheral registers structures */
antbig 0:ad97421fb1fb 105 /******************************************************************************/
antbig 0:ad97421fb1fb 106
antbig 0:ad97421fb1fb 107 #if defined ( __CC_ARM )
antbig 0:ad97421fb1fb 108 #pragma anon_unions
antbig 0:ad97421fb1fb 109 #endif
antbig 0:ad97421fb1fb 110
antbig 0:ad97421fb1fb 111 /*------------- System Control (SC) ------------------------------------------*/
antbig 0:ad97421fb1fb 112 typedef struct
antbig 0:ad97421fb1fb 113 {
antbig 0:ad97421fb1fb 114 __IO uint32_t FLASHCFG; /* Flash Accelerator Module */
antbig 0:ad97421fb1fb 115 uint32_t RESERVED0[31];
antbig 0:ad97421fb1fb 116 __IO uint32_t PLL0CON; /* Clocking and Power Control */
antbig 0:ad97421fb1fb 117 __IO uint32_t PLL0CFG;
antbig 0:ad97421fb1fb 118 __I uint32_t PLL0STAT;
antbig 0:ad97421fb1fb 119 __O uint32_t PLL0FEED;
antbig 0:ad97421fb1fb 120 uint32_t RESERVED1[4];
antbig 0:ad97421fb1fb 121 __IO uint32_t PLL1CON;
antbig 0:ad97421fb1fb 122 __IO uint32_t PLL1CFG;
antbig 0:ad97421fb1fb 123 __I uint32_t PLL1STAT;
antbig 0:ad97421fb1fb 124 __O uint32_t PLL1FEED;
antbig 0:ad97421fb1fb 125 uint32_t RESERVED2[4];
antbig 0:ad97421fb1fb 126 __IO uint32_t PCON;
antbig 0:ad97421fb1fb 127 __IO uint32_t PCONP;
antbig 0:ad97421fb1fb 128 uint32_t RESERVED3[15];
antbig 0:ad97421fb1fb 129 __IO uint32_t CCLKCFG;
antbig 0:ad97421fb1fb 130 __IO uint32_t USBCLKCFG;
antbig 0:ad97421fb1fb 131 __IO uint32_t CLKSRCSEL;
antbig 0:ad97421fb1fb 132 __IO uint32_t CANSLEEPCLR;
antbig 0:ad97421fb1fb 133 __IO uint32_t CANWAKEFLAGS;
antbig 0:ad97421fb1fb 134 uint32_t RESERVED4[10];
antbig 0:ad97421fb1fb 135 __IO uint32_t EXTINT; /* External Interrupts */
antbig 0:ad97421fb1fb 136 uint32_t RESERVED5;
antbig 0:ad97421fb1fb 137 __IO uint32_t EXTMODE;
antbig 0:ad97421fb1fb 138 __IO uint32_t EXTPOLAR;
antbig 0:ad97421fb1fb 139 uint32_t RESERVED6[12];
antbig 0:ad97421fb1fb 140 __IO uint32_t RSID; /* Reset */
antbig 0:ad97421fb1fb 141 uint32_t RESERVED7[7];
antbig 0:ad97421fb1fb 142 __IO uint32_t SCS; /* Syscon Miscellaneous Registers */
antbig 0:ad97421fb1fb 143 __IO uint32_t IRCTRIM; /* Clock Dividers */
antbig 0:ad97421fb1fb 144 __IO uint32_t PCLKSEL0;
antbig 0:ad97421fb1fb 145 __IO uint32_t PCLKSEL1;
antbig 0:ad97421fb1fb 146 uint32_t RESERVED8[4];
antbig 0:ad97421fb1fb 147 __IO uint32_t USBIntSt; /* USB Device/OTG Interrupt Register */
antbig 0:ad97421fb1fb 148 __IO uint32_t DMAREQSEL;
antbig 0:ad97421fb1fb 149 __IO uint32_t CLKOUTCFG; /* Clock Output Configuration */
antbig 0:ad97421fb1fb 150 } LPC_SC_TypeDef;
antbig 0:ad97421fb1fb 151
antbig 0:ad97421fb1fb 152 /*------------- Pin Connect Block (PINCON) -----------------------------------*/
antbig 0:ad97421fb1fb 153 typedef struct
antbig 0:ad97421fb1fb 154 {
antbig 0:ad97421fb1fb 155 __IO uint32_t PINSEL0;
antbig 0:ad97421fb1fb 156 __IO uint32_t PINSEL1;
antbig 0:ad97421fb1fb 157 __IO uint32_t PINSEL2;
antbig 0:ad97421fb1fb 158 __IO uint32_t PINSEL3;
antbig 0:ad97421fb1fb 159 __IO uint32_t PINSEL4;
antbig 0:ad97421fb1fb 160 __IO uint32_t PINSEL5;
antbig 0:ad97421fb1fb 161 __IO uint32_t PINSEL6;
antbig 0:ad97421fb1fb 162 __IO uint32_t PINSEL7;
antbig 0:ad97421fb1fb 163 __IO uint32_t PINSEL8;
antbig 0:ad97421fb1fb 164 __IO uint32_t PINSEL9;
antbig 0:ad97421fb1fb 165 __IO uint32_t PINSEL10;
antbig 0:ad97421fb1fb 166 uint32_t RESERVED0[5];
antbig 0:ad97421fb1fb 167 __IO uint32_t PINMODE0;
antbig 0:ad97421fb1fb 168 __IO uint32_t PINMODE1;
antbig 0:ad97421fb1fb 169 __IO uint32_t PINMODE2;
antbig 0:ad97421fb1fb 170 __IO uint32_t PINMODE3;
antbig 0:ad97421fb1fb 171 __IO uint32_t PINMODE4;
antbig 0:ad97421fb1fb 172 __IO uint32_t PINMODE5;
antbig 0:ad97421fb1fb 173 __IO uint32_t PINMODE6;
antbig 0:ad97421fb1fb 174 __IO uint32_t PINMODE7;
antbig 0:ad97421fb1fb 175 __IO uint32_t PINMODE8;
antbig 0:ad97421fb1fb 176 __IO uint32_t PINMODE9;
antbig 0:ad97421fb1fb 177 __IO uint32_t PINMODE_OD0;
antbig 0:ad97421fb1fb 178 __IO uint32_t PINMODE_OD1;
antbig 0:ad97421fb1fb 179 __IO uint32_t PINMODE_OD2;
antbig 0:ad97421fb1fb 180 __IO uint32_t PINMODE_OD3;
antbig 0:ad97421fb1fb 181 __IO uint32_t PINMODE_OD4;
antbig 0:ad97421fb1fb 182 __IO uint32_t I2CPADCFG;
antbig 0:ad97421fb1fb 183 } LPC_PINCON_TypeDef;
antbig 0:ad97421fb1fb 184
antbig 0:ad97421fb1fb 185 /*------------- General Purpose Input/Output (GPIO) --------------------------*/
antbig 0:ad97421fb1fb 186 typedef struct
antbig 0:ad97421fb1fb 187 {
antbig 0:ad97421fb1fb 188 union {
antbig 0:ad97421fb1fb 189 __IO uint32_t FIODIR;
antbig 0:ad97421fb1fb 190 struct {
antbig 0:ad97421fb1fb 191 __IO uint16_t FIODIRL;
antbig 0:ad97421fb1fb 192 __IO uint16_t FIODIRH;
antbig 0:ad97421fb1fb 193 };
antbig 0:ad97421fb1fb 194 struct {
antbig 0:ad97421fb1fb 195 __IO uint8_t FIODIR0;
antbig 0:ad97421fb1fb 196 __IO uint8_t FIODIR1;
antbig 0:ad97421fb1fb 197 __IO uint8_t FIODIR2;
antbig 0:ad97421fb1fb 198 __IO uint8_t FIODIR3;
antbig 0:ad97421fb1fb 199 };
antbig 0:ad97421fb1fb 200 };
antbig 0:ad97421fb1fb 201 uint32_t RESERVED0[3];
antbig 0:ad97421fb1fb 202 union {
antbig 0:ad97421fb1fb 203 __IO uint32_t FIOMASK;
antbig 0:ad97421fb1fb 204 struct {
antbig 0:ad97421fb1fb 205 __IO uint16_t FIOMASKL;
antbig 0:ad97421fb1fb 206 __IO uint16_t FIOMASKH;
antbig 0:ad97421fb1fb 207 };
antbig 0:ad97421fb1fb 208 struct {
antbig 0:ad97421fb1fb 209 __IO uint8_t FIOMASK0;
antbig 0:ad97421fb1fb 210 __IO uint8_t FIOMASK1;
antbig 0:ad97421fb1fb 211 __IO uint8_t FIOMASK2;
antbig 0:ad97421fb1fb 212 __IO uint8_t FIOMASK3;
antbig 0:ad97421fb1fb 213 };
antbig 0:ad97421fb1fb 214 };
antbig 0:ad97421fb1fb 215 union {
antbig 0:ad97421fb1fb 216 __IO uint32_t FIOPIN;
antbig 0:ad97421fb1fb 217 struct {
antbig 0:ad97421fb1fb 218 __IO uint16_t FIOPINL;
antbig 0:ad97421fb1fb 219 __IO uint16_t FIOPINH;
antbig 0:ad97421fb1fb 220 };
antbig 0:ad97421fb1fb 221 struct {
antbig 0:ad97421fb1fb 222 __IO uint8_t FIOPIN0;
antbig 0:ad97421fb1fb 223 __IO uint8_t FIOPIN1;
antbig 0:ad97421fb1fb 224 __IO uint8_t FIOPIN2;
antbig 0:ad97421fb1fb 225 __IO uint8_t FIOPIN3;
antbig 0:ad97421fb1fb 226 };
antbig 0:ad97421fb1fb 227 };
antbig 0:ad97421fb1fb 228 union {
antbig 0:ad97421fb1fb 229 __IO uint32_t FIOSET;
antbig 0:ad97421fb1fb 230 struct {
antbig 0:ad97421fb1fb 231 __IO uint16_t FIOSETL;
antbig 0:ad97421fb1fb 232 __IO uint16_t FIOSETH;
antbig 0:ad97421fb1fb 233 };
antbig 0:ad97421fb1fb 234 struct {
antbig 0:ad97421fb1fb 235 __IO uint8_t FIOSET0;
antbig 0:ad97421fb1fb 236 __IO uint8_t FIOSET1;
antbig 0:ad97421fb1fb 237 __IO uint8_t FIOSET2;
antbig 0:ad97421fb1fb 238 __IO uint8_t FIOSET3;
antbig 0:ad97421fb1fb 239 };
antbig 0:ad97421fb1fb 240 };
antbig 0:ad97421fb1fb 241 union {
antbig 0:ad97421fb1fb 242 __O uint32_t FIOCLR;
antbig 0:ad97421fb1fb 243 struct {
antbig 0:ad97421fb1fb 244 __O uint16_t FIOCLRL;
antbig 0:ad97421fb1fb 245 __O uint16_t FIOCLRH;
antbig 0:ad97421fb1fb 246 };
antbig 0:ad97421fb1fb 247 struct {
antbig 0:ad97421fb1fb 248 __O uint8_t FIOCLR0;
antbig 0:ad97421fb1fb 249 __O uint8_t FIOCLR1;
antbig 0:ad97421fb1fb 250 __O uint8_t FIOCLR2;
antbig 0:ad97421fb1fb 251 __O uint8_t FIOCLR3;
antbig 0:ad97421fb1fb 252 };
antbig 0:ad97421fb1fb 253 };
antbig 0:ad97421fb1fb 254 } LPC_GPIO_TypeDef;
antbig 0:ad97421fb1fb 255
antbig 0:ad97421fb1fb 256 typedef struct
antbig 0:ad97421fb1fb 257 {
antbig 0:ad97421fb1fb 258 __I uint32_t IntStatus;
antbig 0:ad97421fb1fb 259 __I uint32_t IO0IntStatR;
antbig 0:ad97421fb1fb 260 __I uint32_t IO0IntStatF;
antbig 0:ad97421fb1fb 261 __O uint32_t IO0IntClr;
antbig 0:ad97421fb1fb 262 __IO uint32_t IO0IntEnR;
antbig 0:ad97421fb1fb 263 __IO uint32_t IO0IntEnF;
antbig 0:ad97421fb1fb 264 uint32_t RESERVED0[3];
antbig 0:ad97421fb1fb 265 __I uint32_t IO2IntStatR;
antbig 0:ad97421fb1fb 266 __I uint32_t IO2IntStatF;
antbig 0:ad97421fb1fb 267 __O uint32_t IO2IntClr;
antbig 0:ad97421fb1fb 268 __IO uint32_t IO2IntEnR;
antbig 0:ad97421fb1fb 269 __IO uint32_t IO2IntEnF;
antbig 0:ad97421fb1fb 270 } LPC_GPIOINT_TypeDef;
antbig 0:ad97421fb1fb 271
antbig 0:ad97421fb1fb 272 /*------------- Timer (TIM) --------------------------------------------------*/
antbig 0:ad97421fb1fb 273 typedef struct
antbig 0:ad97421fb1fb 274 {
antbig 0:ad97421fb1fb 275 __IO uint32_t IR;
antbig 0:ad97421fb1fb 276 __IO uint32_t TCR;
antbig 0:ad97421fb1fb 277 __IO uint32_t TC;
antbig 0:ad97421fb1fb 278 __IO uint32_t PR;
antbig 0:ad97421fb1fb 279 __IO uint32_t PC;
antbig 0:ad97421fb1fb 280 __IO uint32_t MCR;
antbig 0:ad97421fb1fb 281 __IO uint32_t MR0;
antbig 0:ad97421fb1fb 282 __IO uint32_t MR1;
antbig 0:ad97421fb1fb 283 __IO uint32_t MR2;
antbig 0:ad97421fb1fb 284 __IO uint32_t MR3;
antbig 0:ad97421fb1fb 285 __IO uint32_t CCR;
antbig 0:ad97421fb1fb 286 __I uint32_t CR0;
antbig 0:ad97421fb1fb 287 __I uint32_t CR1;
antbig 0:ad97421fb1fb 288 uint32_t RESERVED0[2];
antbig 0:ad97421fb1fb 289 __IO uint32_t EMR;
antbig 0:ad97421fb1fb 290 uint32_t RESERVED1[12];
antbig 0:ad97421fb1fb 291 __IO uint32_t CTCR;
antbig 0:ad97421fb1fb 292 } LPC_TIM_TypeDef;
antbig 0:ad97421fb1fb 293
antbig 0:ad97421fb1fb 294 /*------------- Pulse-Width Modulation (PWM) ---------------------------------*/
antbig 0:ad97421fb1fb 295 typedef struct
antbig 0:ad97421fb1fb 296 {
antbig 0:ad97421fb1fb 297 __IO uint32_t IR;
antbig 0:ad97421fb1fb 298 __IO uint32_t TCR;
antbig 0:ad97421fb1fb 299 __IO uint32_t TC;
antbig 0:ad97421fb1fb 300 __IO uint32_t PR;
antbig 0:ad97421fb1fb 301 __IO uint32_t PC;
antbig 0:ad97421fb1fb 302 __IO uint32_t MCR;
antbig 0:ad97421fb1fb 303 __IO uint32_t MR0;
antbig 0:ad97421fb1fb 304 __IO uint32_t MR1;
antbig 0:ad97421fb1fb 305 __IO uint32_t MR2;
antbig 0:ad97421fb1fb 306 __IO uint32_t MR3;
antbig 0:ad97421fb1fb 307 __IO uint32_t CCR;
antbig 0:ad97421fb1fb 308 __I uint32_t CR0;
antbig 0:ad97421fb1fb 309 __I uint32_t CR1;
antbig 0:ad97421fb1fb 310 __I uint32_t CR2;
antbig 0:ad97421fb1fb 311 __I uint32_t CR3;
antbig 0:ad97421fb1fb 312 uint32_t RESERVED0;
antbig 0:ad97421fb1fb 313 __IO uint32_t MR4;
antbig 0:ad97421fb1fb 314 __IO uint32_t MR5;
antbig 0:ad97421fb1fb 315 __IO uint32_t MR6;
antbig 0:ad97421fb1fb 316 __IO uint32_t PCR;
antbig 0:ad97421fb1fb 317 __IO uint32_t LER;
antbig 0:ad97421fb1fb 318 uint32_t RESERVED1[7];
antbig 0:ad97421fb1fb 319 __IO uint32_t CTCR;
antbig 0:ad97421fb1fb 320 } LPC_PWM_TypeDef;
antbig 0:ad97421fb1fb 321
antbig 0:ad97421fb1fb 322 /*------------- Universal Asynchronous Receiver Transmitter (UART) -----------*/
antbig 0:ad97421fb1fb 323 typedef struct
antbig 0:ad97421fb1fb 324 {
antbig 0:ad97421fb1fb 325 union {
antbig 0:ad97421fb1fb 326 __I uint8_t RBR;
antbig 0:ad97421fb1fb 327 __O uint8_t THR;
antbig 0:ad97421fb1fb 328 __IO uint8_t DLL;
antbig 0:ad97421fb1fb 329 uint32_t RESERVED0;
antbig 0:ad97421fb1fb 330 };
antbig 0:ad97421fb1fb 331 union {
antbig 0:ad97421fb1fb 332 __IO uint8_t DLM;
antbig 0:ad97421fb1fb 333 __IO uint32_t IER;
antbig 0:ad97421fb1fb 334 };
antbig 0:ad97421fb1fb 335 union {
antbig 0:ad97421fb1fb 336 __I uint32_t IIR;
antbig 0:ad97421fb1fb 337 __O uint8_t FCR;
antbig 0:ad97421fb1fb 338 };
antbig 0:ad97421fb1fb 339 __IO uint8_t LCR;
antbig 0:ad97421fb1fb 340 uint8_t RESERVED1[7];
antbig 0:ad97421fb1fb 341 __I uint8_t LSR;
antbig 0:ad97421fb1fb 342 uint8_t RESERVED2[7];
antbig 0:ad97421fb1fb 343 __IO uint8_t SCR;
antbig 0:ad97421fb1fb 344 uint8_t RESERVED3[3];
antbig 0:ad97421fb1fb 345 __IO uint32_t ACR;
antbig 0:ad97421fb1fb 346 __IO uint8_t ICR;
antbig 0:ad97421fb1fb 347 uint8_t RESERVED4[3];
antbig 0:ad97421fb1fb 348 __IO uint8_t FDR;
antbig 0:ad97421fb1fb 349 uint8_t RESERVED5[7];
antbig 0:ad97421fb1fb 350 __IO uint8_t TER;
antbig 0:ad97421fb1fb 351 uint8_t RESERVED6[39];
antbig 0:ad97421fb1fb 352 __IO uint32_t FIFOLVL;
antbig 0:ad97421fb1fb 353 } LPC_UART_TypeDef;
antbig 0:ad97421fb1fb 354
antbig 0:ad97421fb1fb 355 typedef struct
antbig 0:ad97421fb1fb 356 {
antbig 0:ad97421fb1fb 357 union {
antbig 0:ad97421fb1fb 358 __I uint8_t RBR;
antbig 0:ad97421fb1fb 359 __O uint8_t THR;
antbig 0:ad97421fb1fb 360 __IO uint8_t DLL;
antbig 0:ad97421fb1fb 361 uint32_t RESERVED0;
antbig 0:ad97421fb1fb 362 };
antbig 0:ad97421fb1fb 363 union {
antbig 0:ad97421fb1fb 364 __IO uint8_t DLM;
antbig 0:ad97421fb1fb 365 __IO uint32_t IER;
antbig 0:ad97421fb1fb 366 };
antbig 0:ad97421fb1fb 367 union {
antbig 0:ad97421fb1fb 368 __I uint32_t IIR;
antbig 0:ad97421fb1fb 369 __O uint8_t FCR;
antbig 0:ad97421fb1fb 370 };
antbig 0:ad97421fb1fb 371 __IO uint8_t LCR;
antbig 0:ad97421fb1fb 372 uint8_t RESERVED1[7];
antbig 0:ad97421fb1fb 373 __I uint8_t LSR;
antbig 0:ad97421fb1fb 374 uint8_t RESERVED2[7];
antbig 0:ad97421fb1fb 375 __IO uint8_t SCR;
antbig 0:ad97421fb1fb 376 uint8_t RESERVED3[3];
antbig 0:ad97421fb1fb 377 __IO uint32_t ACR;
antbig 0:ad97421fb1fb 378 __IO uint8_t ICR;
antbig 0:ad97421fb1fb 379 uint8_t RESERVED4[3];
antbig 0:ad97421fb1fb 380 __IO uint8_t FDR;
antbig 0:ad97421fb1fb 381 uint8_t RESERVED5[7];
antbig 0:ad97421fb1fb 382 __IO uint8_t TER;
antbig 0:ad97421fb1fb 383 uint8_t RESERVED6[39];
antbig 0:ad97421fb1fb 384 __IO uint32_t FIFOLVL;
antbig 0:ad97421fb1fb 385 } LPC_UART0_TypeDef;
antbig 0:ad97421fb1fb 386
antbig 0:ad97421fb1fb 387 typedef struct
antbig 0:ad97421fb1fb 388 {
antbig 0:ad97421fb1fb 389 union {
antbig 0:ad97421fb1fb 390 __I uint8_t RBR;
antbig 0:ad97421fb1fb 391 __O uint8_t THR;
antbig 0:ad97421fb1fb 392 __IO uint8_t DLL;
antbig 0:ad97421fb1fb 393 uint32_t RESERVED0;
antbig 0:ad97421fb1fb 394 };
antbig 0:ad97421fb1fb 395 union {
antbig 0:ad97421fb1fb 396 __IO uint8_t DLM;
antbig 0:ad97421fb1fb 397 __IO uint32_t IER;
antbig 0:ad97421fb1fb 398 };
antbig 0:ad97421fb1fb 399 union {
antbig 0:ad97421fb1fb 400 __I uint32_t IIR;
antbig 0:ad97421fb1fb 401 __O uint8_t FCR;
antbig 0:ad97421fb1fb 402 };
antbig 0:ad97421fb1fb 403 __IO uint8_t LCR;
antbig 0:ad97421fb1fb 404 uint8_t RESERVED1[3];
antbig 0:ad97421fb1fb 405 __IO uint8_t MCR;
antbig 0:ad97421fb1fb 406 uint8_t RESERVED2[3];
antbig 0:ad97421fb1fb 407 __I uint8_t LSR;
antbig 0:ad97421fb1fb 408 uint8_t RESERVED3[3];
antbig 0:ad97421fb1fb 409 __I uint8_t MSR;
antbig 0:ad97421fb1fb 410 uint8_t RESERVED4[3];
antbig 0:ad97421fb1fb 411 __IO uint8_t SCR;
antbig 0:ad97421fb1fb 412 uint8_t RESERVED5[3];
antbig 0:ad97421fb1fb 413 __IO uint32_t ACR;
antbig 0:ad97421fb1fb 414 uint32_t RESERVED6;
antbig 0:ad97421fb1fb 415 __IO uint32_t FDR;
antbig 0:ad97421fb1fb 416 uint32_t RESERVED7;
antbig 0:ad97421fb1fb 417 __IO uint8_t TER;
antbig 0:ad97421fb1fb 418 uint8_t RESERVED8[27];
antbig 0:ad97421fb1fb 419 __IO uint8_t RS485CTRL;
antbig 0:ad97421fb1fb 420 uint8_t RESERVED9[3];
antbig 0:ad97421fb1fb 421 __IO uint8_t ADRMATCH;
antbig 0:ad97421fb1fb 422 uint8_t RESERVED10[3];
antbig 0:ad97421fb1fb 423 __IO uint8_t RS485DLY;
antbig 0:ad97421fb1fb 424 uint8_t RESERVED11[3];
antbig 0:ad97421fb1fb 425 __IO uint32_t FIFOLVL;
antbig 0:ad97421fb1fb 426 } LPC_UART1_TypeDef;
antbig 0:ad97421fb1fb 427
antbig 0:ad97421fb1fb 428 /*------------- Serial Peripheral Interface (SPI) ----------------------------*/
antbig 0:ad97421fb1fb 429 typedef struct
antbig 0:ad97421fb1fb 430 {
antbig 0:ad97421fb1fb 431 __IO uint32_t SPCR;
antbig 0:ad97421fb1fb 432 __I uint32_t SPSR;
antbig 0:ad97421fb1fb 433 __IO uint32_t SPDR;
antbig 0:ad97421fb1fb 434 __IO uint32_t SPCCR;
antbig 0:ad97421fb1fb 435 uint32_t RESERVED0[3];
antbig 0:ad97421fb1fb 436 __IO uint32_t SPINT;
antbig 0:ad97421fb1fb 437 } LPC_SPI_TypeDef;
antbig 0:ad97421fb1fb 438
antbig 0:ad97421fb1fb 439 /*------------- Synchronous Serial Communication (SSP) -----------------------*/
antbig 0:ad97421fb1fb 440 typedef struct
antbig 0:ad97421fb1fb 441 {
antbig 0:ad97421fb1fb 442 __IO uint32_t CR0;
antbig 0:ad97421fb1fb 443 __IO uint32_t CR1;
antbig 0:ad97421fb1fb 444 __IO uint32_t DR;
antbig 0:ad97421fb1fb 445 __I uint32_t SR;
antbig 0:ad97421fb1fb 446 __IO uint32_t CPSR;
antbig 0:ad97421fb1fb 447 __IO uint32_t IMSC;
antbig 0:ad97421fb1fb 448 __IO uint32_t RIS;
antbig 0:ad97421fb1fb 449 __IO uint32_t MIS;
antbig 0:ad97421fb1fb 450 __IO uint32_t ICR;
antbig 0:ad97421fb1fb 451 __IO uint32_t DMACR;
antbig 0:ad97421fb1fb 452 } LPC_SSP_TypeDef;
antbig 0:ad97421fb1fb 453
antbig 0:ad97421fb1fb 454 /*------------- Inter-Integrated Circuit (I2C) -------------------------------*/
antbig 0:ad97421fb1fb 455 typedef struct
antbig 0:ad97421fb1fb 456 {
antbig 0:ad97421fb1fb 457 __IO uint32_t I2CONSET;
antbig 0:ad97421fb1fb 458 __I uint32_t I2STAT;
antbig 0:ad97421fb1fb 459 __IO uint32_t I2DAT;
antbig 0:ad97421fb1fb 460 __IO uint32_t I2ADR0;
antbig 0:ad97421fb1fb 461 __IO uint32_t I2SCLH;
antbig 0:ad97421fb1fb 462 __IO uint32_t I2SCLL;
antbig 0:ad97421fb1fb 463 __O uint32_t I2CONCLR;
antbig 0:ad97421fb1fb 464 __IO uint32_t MMCTRL;
antbig 0:ad97421fb1fb 465 __IO uint32_t I2ADR1;
antbig 0:ad97421fb1fb 466 __IO uint32_t I2ADR2;
antbig 0:ad97421fb1fb 467 __IO uint32_t I2ADR3;
antbig 0:ad97421fb1fb 468 __I uint32_t I2DATA_BUFFER;
antbig 0:ad97421fb1fb 469 __IO uint32_t I2MASK0;
antbig 0:ad97421fb1fb 470 __IO uint32_t I2MASK1;
antbig 0:ad97421fb1fb 471 __IO uint32_t I2MASK2;
antbig 0:ad97421fb1fb 472 __IO uint32_t I2MASK3;
antbig 0:ad97421fb1fb 473 } LPC_I2C_TypeDef;
antbig 0:ad97421fb1fb 474
antbig 0:ad97421fb1fb 475 /*------------- Inter IC Sound (I2S) -----------------------------------------*/
antbig 0:ad97421fb1fb 476 typedef struct
antbig 0:ad97421fb1fb 477 {
antbig 0:ad97421fb1fb 478 __IO uint32_t I2SDAO;
antbig 0:ad97421fb1fb 479 __IO uint32_t I2SDAI;
antbig 0:ad97421fb1fb 480 __O uint32_t I2STXFIFO;
antbig 0:ad97421fb1fb 481 __I uint32_t I2SRXFIFO;
antbig 0:ad97421fb1fb 482 __I uint32_t I2SSTATE;
antbig 0:ad97421fb1fb 483 __IO uint32_t I2SDMA1;
antbig 0:ad97421fb1fb 484 __IO uint32_t I2SDMA2;
antbig 0:ad97421fb1fb 485 __IO uint32_t I2SIRQ;
antbig 0:ad97421fb1fb 486 __IO uint32_t I2STXRATE;
antbig 0:ad97421fb1fb 487 __IO uint32_t I2SRXRATE;
antbig 0:ad97421fb1fb 488 __IO uint32_t I2STXBITRATE;
antbig 0:ad97421fb1fb 489 __IO uint32_t I2SRXBITRATE;
antbig 0:ad97421fb1fb 490 __IO uint32_t I2STXMODE;
antbig 0:ad97421fb1fb 491 __IO uint32_t I2SRXMODE;
antbig 0:ad97421fb1fb 492 } LPC_I2S_TypeDef;
antbig 0:ad97421fb1fb 493
antbig 0:ad97421fb1fb 494 /*------------- Repetitive Interrupt Timer (RIT) -----------------------------*/
antbig 0:ad97421fb1fb 495 typedef struct
antbig 0:ad97421fb1fb 496 {
antbig 0:ad97421fb1fb 497 __IO uint32_t RICOMPVAL;
antbig 0:ad97421fb1fb 498 __IO uint32_t RIMASK;
antbig 0:ad97421fb1fb 499 __IO uint8_t RICTRL;
antbig 0:ad97421fb1fb 500 uint8_t RESERVED0[3];
antbig 0:ad97421fb1fb 501 __IO uint32_t RICOUNTER;
antbig 0:ad97421fb1fb 502 } LPC_RIT_TypeDef;
antbig 0:ad97421fb1fb 503
antbig 0:ad97421fb1fb 504 /*------------- Real-Time Clock (RTC) ----------------------------------------*/
antbig 0:ad97421fb1fb 505 typedef struct
antbig 0:ad97421fb1fb 506 {
antbig 0:ad97421fb1fb 507 __IO uint8_t ILR;
antbig 0:ad97421fb1fb 508 uint8_t RESERVED0[7];
antbig 0:ad97421fb1fb 509 __IO uint8_t CCR;
antbig 0:ad97421fb1fb 510 uint8_t RESERVED1[3];
antbig 0:ad97421fb1fb 511 __IO uint8_t CIIR;
antbig 0:ad97421fb1fb 512 uint8_t RESERVED2[3];
antbig 0:ad97421fb1fb 513 __IO uint8_t AMR;
antbig 0:ad97421fb1fb 514 uint8_t RESERVED3[3];
antbig 0:ad97421fb1fb 515 __I uint32_t CTIME0;
antbig 0:ad97421fb1fb 516 __I uint32_t CTIME1;
antbig 0:ad97421fb1fb 517 __I uint32_t CTIME2;
antbig 0:ad97421fb1fb 518 __IO uint8_t SEC;
antbig 0:ad97421fb1fb 519 uint8_t RESERVED4[3];
antbig 0:ad97421fb1fb 520 __IO uint8_t MIN;
antbig 0:ad97421fb1fb 521 uint8_t RESERVED5[3];
antbig 0:ad97421fb1fb 522 __IO uint8_t HOUR;
antbig 0:ad97421fb1fb 523 uint8_t RESERVED6[3];
antbig 0:ad97421fb1fb 524 __IO uint8_t DOM;
antbig 0:ad97421fb1fb 525 uint8_t RESERVED7[3];
antbig 0:ad97421fb1fb 526 __IO uint8_t DOW;
antbig 0:ad97421fb1fb 527 uint8_t RESERVED8[3];
antbig 0:ad97421fb1fb 528 __IO uint16_t DOY;
antbig 0:ad97421fb1fb 529 uint16_t RESERVED9;
antbig 0:ad97421fb1fb 530 __IO uint8_t MONTH;
antbig 0:ad97421fb1fb 531 uint8_t RESERVED10[3];
antbig 0:ad97421fb1fb 532 __IO uint16_t YEAR;
antbig 0:ad97421fb1fb 533 uint16_t RESERVED11;
antbig 0:ad97421fb1fb 534 __IO uint32_t CALIBRATION;
antbig 0:ad97421fb1fb 535 __IO uint32_t GPREG0;
antbig 0:ad97421fb1fb 536 __IO uint32_t GPREG1;
antbig 0:ad97421fb1fb 537 __IO uint32_t GPREG2;
antbig 0:ad97421fb1fb 538 __IO uint32_t GPREG3;
antbig 0:ad97421fb1fb 539 __IO uint32_t GPREG4;
antbig 0:ad97421fb1fb 540 __IO uint8_t RTC_AUXEN;
antbig 0:ad97421fb1fb 541 uint8_t RESERVED12[3];
antbig 0:ad97421fb1fb 542 __IO uint8_t RTC_AUX;
antbig 0:ad97421fb1fb 543 uint8_t RESERVED13[3];
antbig 0:ad97421fb1fb 544 __IO uint8_t ALSEC;
antbig 0:ad97421fb1fb 545 uint8_t RESERVED14[3];
antbig 0:ad97421fb1fb 546 __IO uint8_t ALMIN;
antbig 0:ad97421fb1fb 547 uint8_t RESERVED15[3];
antbig 0:ad97421fb1fb 548 __IO uint8_t ALHOUR;
antbig 0:ad97421fb1fb 549 uint8_t RESERVED16[3];
antbig 0:ad97421fb1fb 550 __IO uint8_t ALDOM;
antbig 0:ad97421fb1fb 551 uint8_t RESERVED17[3];
antbig 0:ad97421fb1fb 552 __IO uint8_t ALDOW;
antbig 0:ad97421fb1fb 553 uint8_t RESERVED18[3];
antbig 0:ad97421fb1fb 554 __IO uint16_t ALDOY;
antbig 0:ad97421fb1fb 555 uint16_t RESERVED19;
antbig 0:ad97421fb1fb 556 __IO uint8_t ALMON;
antbig 0:ad97421fb1fb 557 uint8_t RESERVED20[3];
antbig 0:ad97421fb1fb 558 __IO uint16_t ALYEAR;
antbig 0:ad97421fb1fb 559 uint16_t RESERVED21;
antbig 0:ad97421fb1fb 560 } LPC_RTC_TypeDef;
antbig 0:ad97421fb1fb 561
antbig 0:ad97421fb1fb 562 /*------------- Watchdog Timer (WDT) -----------------------------------------*/
antbig 0:ad97421fb1fb 563 typedef struct
antbig 0:ad97421fb1fb 564 {
antbig 0:ad97421fb1fb 565 __IO uint8_t WDMOD;
antbig 0:ad97421fb1fb 566 uint8_t RESERVED0[3];
antbig 0:ad97421fb1fb 567 __IO uint32_t WDTC;
antbig 0:ad97421fb1fb 568 __O uint8_t WDFEED;
antbig 0:ad97421fb1fb 569 uint8_t RESERVED1[3];
antbig 0:ad97421fb1fb 570 __I uint32_t WDTV;
antbig 0:ad97421fb1fb 571 __IO uint32_t WDCLKSEL;
antbig 0:ad97421fb1fb 572 } LPC_WDT_TypeDef;
antbig 0:ad97421fb1fb 573
antbig 0:ad97421fb1fb 574 /*------------- Analog-to-Digital Converter (ADC) ----------------------------*/
antbig 0:ad97421fb1fb 575 typedef struct
antbig 0:ad97421fb1fb 576 {
antbig 0:ad97421fb1fb 577 __IO uint32_t ADCR;
antbig 0:ad97421fb1fb 578 __IO uint32_t ADGDR;
antbig 0:ad97421fb1fb 579 uint32_t RESERVED0;
antbig 0:ad97421fb1fb 580 __IO uint32_t ADINTEN;
antbig 0:ad97421fb1fb 581 __I uint32_t ADDR0;
antbig 0:ad97421fb1fb 582 __I uint32_t ADDR1;
antbig 0:ad97421fb1fb 583 __I uint32_t ADDR2;
antbig 0:ad97421fb1fb 584 __I uint32_t ADDR3;
antbig 0:ad97421fb1fb 585 __I uint32_t ADDR4;
antbig 0:ad97421fb1fb 586 __I uint32_t ADDR5;
antbig 0:ad97421fb1fb 587 __I uint32_t ADDR6;
antbig 0:ad97421fb1fb 588 __I uint32_t ADDR7;
antbig 0:ad97421fb1fb 589 __I uint32_t ADSTAT;
antbig 0:ad97421fb1fb 590 __IO uint32_t ADTRM;
antbig 0:ad97421fb1fb 591 } LPC_ADC_TypeDef;
antbig 0:ad97421fb1fb 592
antbig 0:ad97421fb1fb 593 /*------------- Digital-to-Analog Converter (DAC) ----------------------------*/
antbig 0:ad97421fb1fb 594 typedef struct
antbig 0:ad97421fb1fb 595 {
antbig 0:ad97421fb1fb 596 __IO uint32_t DACR;
antbig 0:ad97421fb1fb 597 __IO uint32_t DACCTRL;
antbig 0:ad97421fb1fb 598 __IO uint16_t DACCNTVAL;
antbig 0:ad97421fb1fb 599 } LPC_DAC_TypeDef;
antbig 0:ad97421fb1fb 600
antbig 0:ad97421fb1fb 601 /*------------- Motor Control Pulse-Width Modulation (MCPWM) -----------------*/
antbig 0:ad97421fb1fb 602 typedef struct
antbig 0:ad97421fb1fb 603 {
antbig 0:ad97421fb1fb 604 __I uint32_t MCCON;
antbig 0:ad97421fb1fb 605 __O uint32_t MCCON_SET;
antbig 0:ad97421fb1fb 606 __O uint32_t MCCON_CLR;
antbig 0:ad97421fb1fb 607 __I uint32_t MCCAPCON;
antbig 0:ad97421fb1fb 608 __O uint32_t MCCAPCON_SET;
antbig 0:ad97421fb1fb 609 __O uint32_t MCCAPCON_CLR;
antbig 0:ad97421fb1fb 610 __IO uint32_t MCTIM0;
antbig 0:ad97421fb1fb 611 __IO uint32_t MCTIM1;
antbig 0:ad97421fb1fb 612 __IO uint32_t MCTIM2;
antbig 0:ad97421fb1fb 613 __IO uint32_t MCPER0;
antbig 0:ad97421fb1fb 614 __IO uint32_t MCPER1;
antbig 0:ad97421fb1fb 615 __IO uint32_t MCPER2;
antbig 0:ad97421fb1fb 616 __IO uint32_t MCPW0;
antbig 0:ad97421fb1fb 617 __IO uint32_t MCPW1;
antbig 0:ad97421fb1fb 618 __IO uint32_t MCPW2;
antbig 0:ad97421fb1fb 619 __IO uint32_t MCDEADTIME;
antbig 0:ad97421fb1fb 620 __IO uint32_t MCCCP;
antbig 0:ad97421fb1fb 621 __IO uint32_t MCCR0;
antbig 0:ad97421fb1fb 622 __IO uint32_t MCCR1;
antbig 0:ad97421fb1fb 623 __IO uint32_t MCCR2;
antbig 0:ad97421fb1fb 624 __I uint32_t MCINTEN;
antbig 0:ad97421fb1fb 625 __O uint32_t MCINTEN_SET;
antbig 0:ad97421fb1fb 626 __O uint32_t MCINTEN_CLR;
antbig 0:ad97421fb1fb 627 __I uint32_t MCCNTCON;
antbig 0:ad97421fb1fb 628 __O uint32_t MCCNTCON_SET;
antbig 0:ad97421fb1fb 629 __O uint32_t MCCNTCON_CLR;
antbig 0:ad97421fb1fb 630 __I uint32_t MCINTFLAG;
antbig 0:ad97421fb1fb 631 __O uint32_t MCINTFLAG_SET;
antbig 0:ad97421fb1fb 632 __O uint32_t MCINTFLAG_CLR;
antbig 0:ad97421fb1fb 633 __O uint32_t MCCAP_CLR;
antbig 0:ad97421fb1fb 634 } LPC_MCPWM_TypeDef;
antbig 0:ad97421fb1fb 635
antbig 0:ad97421fb1fb 636 /*------------- Quadrature Encoder Interface (QEI) ---------------------------*/
antbig 0:ad97421fb1fb 637 typedef struct
antbig 0:ad97421fb1fb 638 {
antbig 0:ad97421fb1fb 639 __O uint32_t QEICON;
antbig 0:ad97421fb1fb 640 __I uint32_t QEISTAT;
antbig 0:ad97421fb1fb 641 __IO uint32_t QEICONF;
antbig 0:ad97421fb1fb 642 __I uint32_t QEIPOS;
antbig 0:ad97421fb1fb 643 __IO uint32_t QEIMAXPOS;
antbig 0:ad97421fb1fb 644 __IO uint32_t CMPOS0;
antbig 0:ad97421fb1fb 645 __IO uint32_t CMPOS1;
antbig 0:ad97421fb1fb 646 __IO uint32_t CMPOS2;
antbig 0:ad97421fb1fb 647 __I uint32_t INXCNT;
antbig 0:ad97421fb1fb 648 __IO uint32_t INXCMP;
antbig 0:ad97421fb1fb 649 __IO uint32_t QEILOAD;
antbig 0:ad97421fb1fb 650 __I uint32_t QEITIME;
antbig 0:ad97421fb1fb 651 __I uint32_t QEIVEL;
antbig 0:ad97421fb1fb 652 __I uint32_t QEICAP;
antbig 0:ad97421fb1fb 653 __IO uint32_t VELCOMP;
antbig 0:ad97421fb1fb 654 __IO uint32_t FILTER;
antbig 0:ad97421fb1fb 655 uint32_t RESERVED0[998];
antbig 0:ad97421fb1fb 656 __O uint32_t QEIIEC;
antbig 0:ad97421fb1fb 657 __O uint32_t QEIIES;
antbig 0:ad97421fb1fb 658 __I uint32_t QEIINTSTAT;
antbig 0:ad97421fb1fb 659 __I uint32_t QEIIE;
antbig 0:ad97421fb1fb 660 __O uint32_t QEICLR;
antbig 0:ad97421fb1fb 661 __O uint32_t QEISET;
antbig 0:ad97421fb1fb 662 } LPC_QEI_TypeDef;
antbig 0:ad97421fb1fb 663
antbig 0:ad97421fb1fb 664 /*------------- Controller Area Network (CAN) --------------------------------*/
antbig 0:ad97421fb1fb 665 typedef struct
antbig 0:ad97421fb1fb 666 {
antbig 0:ad97421fb1fb 667 __IO uint32_t mask[512]; /* ID Masks */
antbig 0:ad97421fb1fb 668 } LPC_CANAF_RAM_TypeDef;
antbig 0:ad97421fb1fb 669
antbig 0:ad97421fb1fb 670 typedef struct /* Acceptance Filter Registers */
antbig 0:ad97421fb1fb 671 {
antbig 0:ad97421fb1fb 672 __IO uint32_t AFMR;
antbig 0:ad97421fb1fb 673 __IO uint32_t SFF_sa;
antbig 0:ad97421fb1fb 674 __IO uint32_t SFF_GRP_sa;
antbig 0:ad97421fb1fb 675 __IO uint32_t EFF_sa;
antbig 0:ad97421fb1fb 676 __IO uint32_t EFF_GRP_sa;
antbig 0:ad97421fb1fb 677 __IO uint32_t ENDofTable;
antbig 0:ad97421fb1fb 678 __I uint32_t LUTerrAd;
antbig 0:ad97421fb1fb 679 __I uint32_t LUTerr;
antbig 0:ad97421fb1fb 680 __IO uint32_t FCANIE;
antbig 0:ad97421fb1fb 681 __IO uint32_t FCANIC0;
antbig 0:ad97421fb1fb 682 __IO uint32_t FCANIC1;
antbig 0:ad97421fb1fb 683 } LPC_CANAF_TypeDef;
antbig 0:ad97421fb1fb 684
antbig 0:ad97421fb1fb 685 typedef struct /* Central Registers */
antbig 0:ad97421fb1fb 686 {
antbig 0:ad97421fb1fb 687 __I uint32_t CANTxSR;
antbig 0:ad97421fb1fb 688 __I uint32_t CANRxSR;
antbig 0:ad97421fb1fb 689 __I uint32_t CANMSR;
antbig 0:ad97421fb1fb 690 } LPC_CANCR_TypeDef;
antbig 0:ad97421fb1fb 691
antbig 0:ad97421fb1fb 692 typedef struct /* Controller Registers */
antbig 0:ad97421fb1fb 693 {
antbig 0:ad97421fb1fb 694 __IO uint32_t MOD;
antbig 0:ad97421fb1fb 695 __O uint32_t CMR;
antbig 0:ad97421fb1fb 696 __IO uint32_t GSR;
antbig 0:ad97421fb1fb 697 __I uint32_t ICR;
antbig 0:ad97421fb1fb 698 __IO uint32_t IER;
antbig 0:ad97421fb1fb 699 __IO uint32_t BTR;
antbig 0:ad97421fb1fb 700 __IO uint32_t EWL;
antbig 0:ad97421fb1fb 701 __I uint32_t SR;
antbig 0:ad97421fb1fb 702 __IO uint32_t RFS;
antbig 0:ad97421fb1fb 703 __IO uint32_t RID;
antbig 0:ad97421fb1fb 704 __IO uint32_t RDA;
antbig 0:ad97421fb1fb 705 __IO uint32_t RDB;
antbig 0:ad97421fb1fb 706 __IO uint32_t TFI1;
antbig 0:ad97421fb1fb 707 __IO uint32_t TID1;
antbig 0:ad97421fb1fb 708 __IO uint32_t TDA1;
antbig 0:ad97421fb1fb 709 __IO uint32_t TDB1;
antbig 0:ad97421fb1fb 710 __IO uint32_t TFI2;
antbig 0:ad97421fb1fb 711 __IO uint32_t TID2;
antbig 0:ad97421fb1fb 712 __IO uint32_t TDA2;
antbig 0:ad97421fb1fb 713 __IO uint32_t TDB2;
antbig 0:ad97421fb1fb 714 __IO uint32_t TFI3;
antbig 0:ad97421fb1fb 715 __IO uint32_t TID3;
antbig 0:ad97421fb1fb 716 __IO uint32_t TDA3;
antbig 0:ad97421fb1fb 717 __IO uint32_t TDB3;
antbig 0:ad97421fb1fb 718 } LPC_CAN_TypeDef;
antbig 0:ad97421fb1fb 719
antbig 0:ad97421fb1fb 720 /*------------- General Purpose Direct Memory Access (GPDMA) -----------------*/
antbig 0:ad97421fb1fb 721 typedef struct /* Common Registers */
antbig 0:ad97421fb1fb 722 {
antbig 0:ad97421fb1fb 723 __I uint32_t DMACIntStat;
antbig 0:ad97421fb1fb 724 __I uint32_t DMACIntTCStat;
antbig 0:ad97421fb1fb 725 __O uint32_t DMACIntTCClear;
antbig 0:ad97421fb1fb 726 __I uint32_t DMACIntErrStat;
antbig 0:ad97421fb1fb 727 __O uint32_t DMACIntErrClr;
antbig 0:ad97421fb1fb 728 __I uint32_t DMACRawIntTCStat;
antbig 0:ad97421fb1fb 729 __I uint32_t DMACRawIntErrStat;
antbig 0:ad97421fb1fb 730 __I uint32_t DMACEnbldChns;
antbig 0:ad97421fb1fb 731 __IO uint32_t DMACSoftBReq;
antbig 0:ad97421fb1fb 732 __IO uint32_t DMACSoftSReq;
antbig 0:ad97421fb1fb 733 __IO uint32_t DMACSoftLBReq;
antbig 0:ad97421fb1fb 734 __IO uint32_t DMACSoftLSReq;
antbig 0:ad97421fb1fb 735 __IO uint32_t DMACConfig;
antbig 0:ad97421fb1fb 736 __IO uint32_t DMACSync;
antbig 0:ad97421fb1fb 737 } LPC_GPDMA_TypeDef;
antbig 0:ad97421fb1fb 738
antbig 0:ad97421fb1fb 739 typedef struct /* Channel Registers */
antbig 0:ad97421fb1fb 740 {
antbig 0:ad97421fb1fb 741 __IO uint32_t DMACCSrcAddr;
antbig 0:ad97421fb1fb 742 __IO uint32_t DMACCDestAddr;
antbig 0:ad97421fb1fb 743 __IO uint32_t DMACCLLI;
antbig 0:ad97421fb1fb 744 __IO uint32_t DMACCControl;
antbig 0:ad97421fb1fb 745 __IO uint32_t DMACCConfig;
antbig 0:ad97421fb1fb 746 } LPC_GPDMACH_TypeDef;
antbig 0:ad97421fb1fb 747
antbig 0:ad97421fb1fb 748 /*------------- Universal Serial Bus (USB) -----------------------------------*/
antbig 0:ad97421fb1fb 749 typedef struct
antbig 0:ad97421fb1fb 750 {
antbig 0:ad97421fb1fb 751 __I uint32_t HcRevision; /* USB Host Registers */
antbig 0:ad97421fb1fb 752 __IO uint32_t HcControl;
antbig 0:ad97421fb1fb 753 __IO uint32_t HcCommandStatus;
antbig 0:ad97421fb1fb 754 __IO uint32_t HcInterruptStatus;
antbig 0:ad97421fb1fb 755 __IO uint32_t HcInterruptEnable;
antbig 0:ad97421fb1fb 756 __IO uint32_t HcInterruptDisable;
antbig 0:ad97421fb1fb 757 __IO uint32_t HcHCCA;
antbig 0:ad97421fb1fb 758 __I uint32_t HcPeriodCurrentED;
antbig 0:ad97421fb1fb 759 __IO uint32_t HcControlHeadED;
antbig 0:ad97421fb1fb 760 __IO uint32_t HcControlCurrentED;
antbig 0:ad97421fb1fb 761 __IO uint32_t HcBulkHeadED;
antbig 0:ad97421fb1fb 762 __IO uint32_t HcBulkCurrentED;
antbig 0:ad97421fb1fb 763 __I uint32_t HcDoneHead;
antbig 0:ad97421fb1fb 764 __IO uint32_t HcFmInterval;
antbig 0:ad97421fb1fb 765 __I uint32_t HcFmRemaining;
antbig 0:ad97421fb1fb 766 __I uint32_t HcFmNumber;
antbig 0:ad97421fb1fb 767 __IO uint32_t HcPeriodicStart;
antbig 0:ad97421fb1fb 768 __IO uint32_t HcLSTreshold;
antbig 0:ad97421fb1fb 769 __IO uint32_t HcRhDescriptorA;
antbig 0:ad97421fb1fb 770 __IO uint32_t HcRhDescriptorB;
antbig 0:ad97421fb1fb 771 __IO uint32_t HcRhStatus;
antbig 0:ad97421fb1fb 772 __IO uint32_t HcRhPortStatus1;
antbig 0:ad97421fb1fb 773 __IO uint32_t HcRhPortStatus2;
antbig 0:ad97421fb1fb 774 uint32_t RESERVED0[40];
antbig 0:ad97421fb1fb 775 __I uint32_t Module_ID;
antbig 0:ad97421fb1fb 776
antbig 0:ad97421fb1fb 777 __I uint32_t OTGIntSt; /* USB On-The-Go Registers */
antbig 0:ad97421fb1fb 778 __IO uint32_t OTGIntEn;
antbig 0:ad97421fb1fb 779 __O uint32_t OTGIntSet;
antbig 0:ad97421fb1fb 780 __O uint32_t OTGIntClr;
antbig 0:ad97421fb1fb 781 __IO uint32_t OTGStCtrl;
antbig 0:ad97421fb1fb 782 __IO uint32_t OTGTmr;
antbig 0:ad97421fb1fb 783 uint32_t RESERVED1[58];
antbig 0:ad97421fb1fb 784
antbig 0:ad97421fb1fb 785 __I uint32_t USBDevIntSt; /* USB Device Interrupt Registers */
antbig 0:ad97421fb1fb 786 __IO uint32_t USBDevIntEn;
antbig 0:ad97421fb1fb 787 __O uint32_t USBDevIntClr;
antbig 0:ad97421fb1fb 788 __O uint32_t USBDevIntSet;
antbig 0:ad97421fb1fb 789
antbig 0:ad97421fb1fb 790 __O uint32_t USBCmdCode; /* USB Device SIE Command Registers */
antbig 0:ad97421fb1fb 791 __I uint32_t USBCmdData;
antbig 0:ad97421fb1fb 792
antbig 0:ad97421fb1fb 793 __I uint32_t USBRxData; /* USB Device Transfer Registers */
antbig 0:ad97421fb1fb 794 __O uint32_t USBTxData;
antbig 0:ad97421fb1fb 795 __I uint32_t USBRxPLen;
antbig 0:ad97421fb1fb 796 __O uint32_t USBTxPLen;
antbig 0:ad97421fb1fb 797 __IO uint32_t USBCtrl;
antbig 0:ad97421fb1fb 798 __O uint32_t USBDevIntPri;
antbig 0:ad97421fb1fb 799
antbig 0:ad97421fb1fb 800 __I uint32_t USBEpIntSt; /* USB Device Endpoint Interrupt Regs */
antbig 0:ad97421fb1fb 801 __IO uint32_t USBEpIntEn;
antbig 0:ad97421fb1fb 802 __O uint32_t USBEpIntClr;
antbig 0:ad97421fb1fb 803 __O uint32_t USBEpIntSet;
antbig 0:ad97421fb1fb 804 __O uint32_t USBEpIntPri;
antbig 0:ad97421fb1fb 805
antbig 0:ad97421fb1fb 806 __IO uint32_t USBReEp; /* USB Device Endpoint Realization Reg*/
antbig 0:ad97421fb1fb 807 __O uint32_t USBEpInd;
antbig 0:ad97421fb1fb 808 __IO uint32_t USBMaxPSize;
antbig 0:ad97421fb1fb 809
antbig 0:ad97421fb1fb 810 __I uint32_t USBDMARSt; /* USB Device DMA Registers */
antbig 0:ad97421fb1fb 811 __O uint32_t USBDMARClr;
antbig 0:ad97421fb1fb 812 __O uint32_t USBDMARSet;
antbig 0:ad97421fb1fb 813 uint32_t RESERVED2[9];
antbig 0:ad97421fb1fb 814 __IO uint32_t USBUDCAH;
antbig 0:ad97421fb1fb 815 __I uint32_t USBEpDMASt;
antbig 0:ad97421fb1fb 816 __O uint32_t USBEpDMAEn;
antbig 0:ad97421fb1fb 817 __O uint32_t USBEpDMADis;
antbig 0:ad97421fb1fb 818 __I uint32_t USBDMAIntSt;
antbig 0:ad97421fb1fb 819 __IO uint32_t USBDMAIntEn;
antbig 0:ad97421fb1fb 820 uint32_t RESERVED3[2];
antbig 0:ad97421fb1fb 821 __I uint32_t USBEoTIntSt;
antbig 0:ad97421fb1fb 822 __O uint32_t USBEoTIntClr;
antbig 0:ad97421fb1fb 823 __O uint32_t USBEoTIntSet;
antbig 0:ad97421fb1fb 824 __I uint32_t USBNDDRIntSt;
antbig 0:ad97421fb1fb 825 __O uint32_t USBNDDRIntClr;
antbig 0:ad97421fb1fb 826 __O uint32_t USBNDDRIntSet;
antbig 0:ad97421fb1fb 827 __I uint32_t USBSysErrIntSt;
antbig 0:ad97421fb1fb 828 __O uint32_t USBSysErrIntClr;
antbig 0:ad97421fb1fb 829 __O uint32_t USBSysErrIntSet;
antbig 0:ad97421fb1fb 830 uint32_t RESERVED4[15];
antbig 0:ad97421fb1fb 831
antbig 0:ad97421fb1fb 832 union {
antbig 0:ad97421fb1fb 833 __I uint32_t I2C_RX; /* USB OTG I2C Registers */
antbig 0:ad97421fb1fb 834 __O uint32_t I2C_TX;
antbig 0:ad97421fb1fb 835 };
antbig 0:ad97421fb1fb 836 __I uint32_t I2C_STS;
antbig 0:ad97421fb1fb 837 __IO uint32_t I2C_CTL;
antbig 0:ad97421fb1fb 838 __IO uint32_t I2C_CLKHI;
antbig 0:ad97421fb1fb 839 __O uint32_t I2C_CLKLO;
antbig 0:ad97421fb1fb 840 uint32_t RESERVED5[824];
antbig 0:ad97421fb1fb 841
antbig 0:ad97421fb1fb 842 union {
antbig 0:ad97421fb1fb 843 __IO uint32_t USBClkCtrl; /* USB Clock Control Registers */
antbig 0:ad97421fb1fb 844 __IO uint32_t OTGClkCtrl;
antbig 0:ad97421fb1fb 845 };
antbig 0:ad97421fb1fb 846 union {
antbig 0:ad97421fb1fb 847 __I uint32_t USBClkSt;
antbig 0:ad97421fb1fb 848 __I uint32_t OTGClkSt;
antbig 0:ad97421fb1fb 849 };
antbig 0:ad97421fb1fb 850 } LPC_USB_TypeDef;
antbig 0:ad97421fb1fb 851
antbig 0:ad97421fb1fb 852 /*------------- Ethernet Media Access Controller (EMAC) ----------------------*/
antbig 0:ad97421fb1fb 853 typedef struct
antbig 0:ad97421fb1fb 854 {
antbig 0:ad97421fb1fb 855 __IO uint32_t MAC1; /* MAC Registers */
antbig 0:ad97421fb1fb 856 __IO uint32_t MAC2;
antbig 0:ad97421fb1fb 857 __IO uint32_t IPGT;
antbig 0:ad97421fb1fb 858 __IO uint32_t IPGR;
antbig 0:ad97421fb1fb 859 __IO uint32_t CLRT;
antbig 0:ad97421fb1fb 860 __IO uint32_t MAXF;
antbig 0:ad97421fb1fb 861 __IO uint32_t SUPP;
antbig 0:ad97421fb1fb 862 __IO uint32_t TEST;
antbig 0:ad97421fb1fb 863 __IO uint32_t MCFG;
antbig 0:ad97421fb1fb 864 __IO uint32_t MCMD;
antbig 0:ad97421fb1fb 865 __IO uint32_t MADR;
antbig 0:ad97421fb1fb 866 __O uint32_t MWTD;
antbig 0:ad97421fb1fb 867 __I uint32_t MRDD;
antbig 0:ad97421fb1fb 868 __I uint32_t MIND;
antbig 0:ad97421fb1fb 869 uint32_t RESERVED0[2];
antbig 0:ad97421fb1fb 870 __IO uint32_t SA0;
antbig 0:ad97421fb1fb 871 __IO uint32_t SA1;
antbig 0:ad97421fb1fb 872 __IO uint32_t SA2;
antbig 0:ad97421fb1fb 873 uint32_t RESERVED1[45];
antbig 0:ad97421fb1fb 874 __IO uint32_t Command; /* Control Registers */
antbig 0:ad97421fb1fb 875 __I uint32_t Status;
antbig 0:ad97421fb1fb 876 __IO uint32_t RxDescriptor;
antbig 0:ad97421fb1fb 877 __IO uint32_t RxStatus;
antbig 0:ad97421fb1fb 878 __IO uint32_t RxDescriptorNumber;
antbig 0:ad97421fb1fb 879 __I uint32_t RxProduceIndex;
antbig 0:ad97421fb1fb 880 __IO uint32_t RxConsumeIndex;
antbig 0:ad97421fb1fb 881 __IO uint32_t TxDescriptor;
antbig 0:ad97421fb1fb 882 __IO uint32_t TxStatus;
antbig 0:ad97421fb1fb 883 __IO uint32_t TxDescriptorNumber;
antbig 0:ad97421fb1fb 884 __IO uint32_t TxProduceIndex;
antbig 0:ad97421fb1fb 885 __I uint32_t TxConsumeIndex;
antbig 0:ad97421fb1fb 886 uint32_t RESERVED2[10];
antbig 0:ad97421fb1fb 887 __I uint32_t TSV0;
antbig 0:ad97421fb1fb 888 __I uint32_t TSV1;
antbig 0:ad97421fb1fb 889 __I uint32_t RSV;
antbig 0:ad97421fb1fb 890 uint32_t RESERVED3[3];
antbig 0:ad97421fb1fb 891 __IO uint32_t FlowControlCounter;
antbig 0:ad97421fb1fb 892 __I uint32_t FlowControlStatus;
antbig 0:ad97421fb1fb 893 uint32_t RESERVED4[34];
antbig 0:ad97421fb1fb 894 __IO uint32_t RxFilterCtrl; /* Rx Filter Registers */
antbig 0:ad97421fb1fb 895 __IO uint32_t RxFilterWoLStatus;
antbig 0:ad97421fb1fb 896 __IO uint32_t RxFilterWoLClear;
antbig 0:ad97421fb1fb 897 uint32_t RESERVED5;
antbig 0:ad97421fb1fb 898 __IO uint32_t HashFilterL;
antbig 0:ad97421fb1fb 899 __IO uint32_t HashFilterH;
antbig 0:ad97421fb1fb 900 uint32_t RESERVED6[882];
antbig 0:ad97421fb1fb 901 __I uint32_t IntStatus; /* Module Control Registers */
antbig 0:ad97421fb1fb 902 __IO uint32_t IntEnable;
antbig 0:ad97421fb1fb 903 __O uint32_t IntClear;
antbig 0:ad97421fb1fb 904 __O uint32_t IntSet;
antbig 0:ad97421fb1fb 905 uint32_t RESERVED7;
antbig 0:ad97421fb1fb 906 __IO uint32_t PowerDown;
antbig 0:ad97421fb1fb 907 uint32_t RESERVED8;
antbig 0:ad97421fb1fb 908 __IO uint32_t Module_ID;
antbig 0:ad97421fb1fb 909 } LPC_EMAC_TypeDef;
antbig 0:ad97421fb1fb 910
antbig 0:ad97421fb1fb 911 #if defined ( __CC_ARM )
antbig 0:ad97421fb1fb 912 #pragma no_anon_unions
antbig 0:ad97421fb1fb 913 #endif
antbig 0:ad97421fb1fb 914
antbig 0:ad97421fb1fb 915
antbig 0:ad97421fb1fb 916 /******************************************************************************/
antbig 0:ad97421fb1fb 917 /* Peripheral memory map */
antbig 0:ad97421fb1fb 918 /******************************************************************************/
antbig 0:ad97421fb1fb 919 /* Base addresses */
antbig 0:ad97421fb1fb 920 #define LPC_FLASH_BASE (0x00000000UL)
antbig 0:ad97421fb1fb 921 #define LPC_RAM_BASE (0x10000000UL)
antbig 0:ad97421fb1fb 922 #define LPC_GPIO_BASE (0x2009C000UL)
antbig 0:ad97421fb1fb 923 #define LPC_APB0_BASE (0x40000000UL)
antbig 0:ad97421fb1fb 924 #define LPC_APB1_BASE (0x40080000UL)
antbig 0:ad97421fb1fb 925 #define LPC_AHB_BASE (0x50000000UL)
antbig 0:ad97421fb1fb 926 #define LPC_CM3_BASE (0xE0000000UL)
antbig 0:ad97421fb1fb 927
antbig 0:ad97421fb1fb 928 /* APB0 peripherals */
antbig 0:ad97421fb1fb 929 #define LPC_WDT_BASE (LPC_APB0_BASE + 0x00000)
antbig 0:ad97421fb1fb 930 #define LPC_TIM0_BASE (LPC_APB0_BASE + 0x04000)
antbig 0:ad97421fb1fb 931 #define LPC_TIM1_BASE (LPC_APB0_BASE + 0x08000)
antbig 0:ad97421fb1fb 932 #define LPC_UART0_BASE (LPC_APB0_BASE + 0x0C000)
antbig 0:ad97421fb1fb 933 #define LPC_UART1_BASE (LPC_APB0_BASE + 0x10000)
antbig 0:ad97421fb1fb 934 #define LPC_PWM1_BASE (LPC_APB0_BASE + 0x18000)
antbig 0:ad97421fb1fb 935 #define LPC_I2C0_BASE (LPC_APB0_BASE + 0x1C000)
antbig 0:ad97421fb1fb 936 #define LPC_SPI_BASE (LPC_APB0_BASE + 0x20000)
antbig 0:ad97421fb1fb 937 #define LPC_RTC_BASE (LPC_APB0_BASE + 0x24000)
antbig 0:ad97421fb1fb 938 #define LPC_GPIOINT_BASE (LPC_APB0_BASE + 0x28080)
antbig 0:ad97421fb1fb 939 #define LPC_PINCON_BASE (LPC_APB0_BASE + 0x2C000)
antbig 0:ad97421fb1fb 940 #define LPC_SSP1_BASE (LPC_APB0_BASE + 0x30000)
antbig 0:ad97421fb1fb 941 #define LPC_ADC_BASE (LPC_APB0_BASE + 0x34000)
antbig 0:ad97421fb1fb 942 #define LPC_CANAF_RAM_BASE (LPC_APB0_BASE + 0x38000)
antbig 0:ad97421fb1fb 943 #define LPC_CANAF_BASE (LPC_APB0_BASE + 0x3C000)
antbig 0:ad97421fb1fb 944 #define LPC_CANCR_BASE (LPC_APB0_BASE + 0x40000)
antbig 0:ad97421fb1fb 945 #define LPC_CAN1_BASE (LPC_APB0_BASE + 0x44000)
antbig 0:ad97421fb1fb 946 #define LPC_CAN2_BASE (LPC_APB0_BASE + 0x48000)
antbig 0:ad97421fb1fb 947 #define LPC_I2C1_BASE (LPC_APB0_BASE + 0x5C000)
antbig 0:ad97421fb1fb 948
antbig 0:ad97421fb1fb 949 /* APB1 peripherals */
antbig 0:ad97421fb1fb 950 #define LPC_SSP0_BASE (LPC_APB1_BASE + 0x08000)
antbig 0:ad97421fb1fb 951 #define LPC_DAC_BASE (LPC_APB1_BASE + 0x0C000)
antbig 0:ad97421fb1fb 952 #define LPC_TIM2_BASE (LPC_APB1_BASE + 0x10000)
antbig 0:ad97421fb1fb 953 #define LPC_TIM3_BASE (LPC_APB1_BASE + 0x14000)
antbig 0:ad97421fb1fb 954 #define LPC_UART2_BASE (LPC_APB1_BASE + 0x18000)
antbig 0:ad97421fb1fb 955 #define LPC_UART3_BASE (LPC_APB1_BASE + 0x1C000)
antbig 0:ad97421fb1fb 956 #define LPC_I2C2_BASE (LPC_APB1_BASE + 0x20000)
antbig 0:ad97421fb1fb 957 #define LPC_I2S_BASE (LPC_APB1_BASE + 0x28000)
antbig 0:ad97421fb1fb 958 #define LPC_RIT_BASE (LPC_APB1_BASE + 0x30000)
antbig 0:ad97421fb1fb 959 #define LPC_MCPWM_BASE (LPC_APB1_BASE + 0x38000)
antbig 0:ad97421fb1fb 960 #define LPC_QEI_BASE (LPC_APB1_BASE + 0x3C000)
antbig 0:ad97421fb1fb 961 #define LPC_SC_BASE (LPC_APB1_BASE + 0x7C000)
antbig 0:ad97421fb1fb 962
antbig 0:ad97421fb1fb 963 /* AHB peripherals */
antbig 0:ad97421fb1fb 964 #define LPC_EMAC_BASE (LPC_AHB_BASE + 0x00000)
antbig 0:ad97421fb1fb 965 #define LPC_GPDMA_BASE (LPC_AHB_BASE + 0x04000)
antbig 0:ad97421fb1fb 966 #define LPC_GPDMACH0_BASE (LPC_AHB_BASE + 0x04100)
antbig 0:ad97421fb1fb 967 #define LPC_GPDMACH1_BASE (LPC_AHB_BASE + 0x04120)
antbig 0:ad97421fb1fb 968 #define LPC_GPDMACH2_BASE (LPC_AHB_BASE + 0x04140)
antbig 0:ad97421fb1fb 969 #define LPC_GPDMACH3_BASE (LPC_AHB_BASE + 0x04160)
antbig 0:ad97421fb1fb 970 #define LPC_GPDMACH4_BASE (LPC_AHB_BASE + 0x04180)
antbig 0:ad97421fb1fb 971 #define LPC_GPDMACH5_BASE (LPC_AHB_BASE + 0x041A0)
antbig 0:ad97421fb1fb 972 #define LPC_GPDMACH6_BASE (LPC_AHB_BASE + 0x041C0)
antbig 0:ad97421fb1fb 973 #define LPC_GPDMACH7_BASE (LPC_AHB_BASE + 0x041E0)
antbig 0:ad97421fb1fb 974 #define LPC_USB_BASE (LPC_AHB_BASE + 0x0C000)
antbig 0:ad97421fb1fb 975
antbig 0:ad97421fb1fb 976 /* GPIOs */
antbig 0:ad97421fb1fb 977 #define LPC_GPIO0_BASE (LPC_GPIO_BASE + 0x00000)
antbig 0:ad97421fb1fb 978 #define LPC_GPIO1_BASE (LPC_GPIO_BASE + 0x00020)
antbig 0:ad97421fb1fb 979 #define LPC_GPIO2_BASE (LPC_GPIO_BASE + 0x00040)
antbig 0:ad97421fb1fb 980 #define LPC_GPIO3_BASE (LPC_GPIO_BASE + 0x00060)
antbig 0:ad97421fb1fb 981 #define LPC_GPIO4_BASE (LPC_GPIO_BASE + 0x00080)
antbig 0:ad97421fb1fb 982
antbig 0:ad97421fb1fb 983
antbig 0:ad97421fb1fb 984 /******************************************************************************/
antbig 0:ad97421fb1fb 985 /* Peripheral declaration */
antbig 0:ad97421fb1fb 986 /******************************************************************************/
antbig 0:ad97421fb1fb 987 #define LPC_SC ((LPC_SC_TypeDef *) LPC_SC_BASE )
antbig 0:ad97421fb1fb 988 #define LPC_GPIO0 ((LPC_GPIO_TypeDef *) LPC_GPIO0_BASE )
antbig 0:ad97421fb1fb 989 #define LPC_GPIO1 ((LPC_GPIO_TypeDef *) LPC_GPIO1_BASE )
antbig 0:ad97421fb1fb 990 #define LPC_GPIO2 ((LPC_GPIO_TypeDef *) LPC_GPIO2_BASE )
antbig 0:ad97421fb1fb 991 #define LPC_GPIO3 ((LPC_GPIO_TypeDef *) LPC_GPIO3_BASE )
antbig 0:ad97421fb1fb 992 #define LPC_GPIO4 ((LPC_GPIO_TypeDef *) LPC_GPIO4_BASE )
antbig 0:ad97421fb1fb 993 #define LPC_WDT ((LPC_WDT_TypeDef *) LPC_WDT_BASE )
antbig 0:ad97421fb1fb 994 #define LPC_TIM0 ((LPC_TIM_TypeDef *) LPC_TIM0_BASE )
antbig 0:ad97421fb1fb 995 #define LPC_TIM1 ((LPC_TIM_TypeDef *) LPC_TIM1_BASE )
antbig 0:ad97421fb1fb 996 #define LPC_TIM2 ((LPC_TIM_TypeDef *) LPC_TIM2_BASE )
antbig 0:ad97421fb1fb 997 #define LPC_TIM3 ((LPC_TIM_TypeDef *) LPC_TIM3_BASE )
antbig 0:ad97421fb1fb 998 #define LPC_RIT ((LPC_RIT_TypeDef *) LPC_RIT_BASE )
antbig 0:ad97421fb1fb 999 #define LPC_UART0 ((LPC_UART0_TypeDef *) LPC_UART0_BASE )
antbig 0:ad97421fb1fb 1000 #define LPC_UART1 ((LPC_UART1_TypeDef *) LPC_UART1_BASE )
antbig 0:ad97421fb1fb 1001 #define LPC_UART2 ((LPC_UART_TypeDef *) LPC_UART2_BASE )
antbig 0:ad97421fb1fb 1002 #define LPC_UART3 ((LPC_UART_TypeDef *) LPC_UART3_BASE )
antbig 0:ad97421fb1fb 1003 #define LPC_PWM1 ((LPC_PWM_TypeDef *) LPC_PWM1_BASE )
antbig 0:ad97421fb1fb 1004 #define LPC_I2C0 ((LPC_I2C_TypeDef *) LPC_I2C0_BASE )
antbig 0:ad97421fb1fb 1005 #define LPC_I2C1 ((LPC_I2C_TypeDef *) LPC_I2C1_BASE )
antbig 0:ad97421fb1fb 1006 #define LPC_I2C2 ((LPC_I2C_TypeDef *) LPC_I2C2_BASE )
antbig 0:ad97421fb1fb 1007 #define LPC_I2S ((LPC_I2S_TypeDef *) LPC_I2S_BASE )
antbig 0:ad97421fb1fb 1008 #define LPC_SPI ((LPC_SPI_TypeDef *) LPC_SPI_BASE )
antbig 0:ad97421fb1fb 1009 #define LPC_RTC ((LPC_RTC_TypeDef *) LPC_RTC_BASE )
antbig 0:ad97421fb1fb 1010 #define LPC_GPIOINT ((LPC_GPIOINT_TypeDef *) LPC_GPIOINT_BASE )
antbig 0:ad97421fb1fb 1011 #define LPC_PINCON ((LPC_PINCON_TypeDef *) LPC_PINCON_BASE )
antbig 0:ad97421fb1fb 1012 #define LPC_SSP0 ((LPC_SSP_TypeDef *) LPC_SSP0_BASE )
antbig 0:ad97421fb1fb 1013 #define LPC_SSP1 ((LPC_SSP_TypeDef *) LPC_SSP1_BASE )
antbig 0:ad97421fb1fb 1014 #define LPC_ADC ((LPC_ADC_TypeDef *) LPC_ADC_BASE )
antbig 0:ad97421fb1fb 1015 #define LPC_DAC ((LPC_DAC_TypeDef *) LPC_DAC_BASE )
antbig 0:ad97421fb1fb 1016 #define LPC_CANAF_RAM ((LPC_CANAF_RAM_TypeDef *) LPC_CANAF_RAM_BASE)
antbig 0:ad97421fb1fb 1017 #define LPC_CANAF ((LPC_CANAF_TypeDef *) LPC_CANAF_BASE )
antbig 0:ad97421fb1fb 1018 #define LPC_CANCR ((LPC_CANCR_TypeDef *) LPC_CANCR_BASE )
antbig 0:ad97421fb1fb 1019 #define LPC_CAN1 ((LPC_CAN_TypeDef *) LPC_CAN1_BASE )
antbig 0:ad97421fb1fb 1020 #define LPC_CAN2 ((LPC_CAN_TypeDef *) LPC_CAN2_BASE )
antbig 0:ad97421fb1fb 1021 #define LPC_MCPWM ((LPC_MCPWM_TypeDef *) LPC_MCPWM_BASE )
antbig 0:ad97421fb1fb 1022 #define LPC_QEI ((LPC_QEI_TypeDef *) LPC_QEI_BASE )
antbig 0:ad97421fb1fb 1023 #define LPC_EMAC ((LPC_EMAC_TypeDef *) LPC_EMAC_BASE )
antbig 0:ad97421fb1fb 1024 #define LPC_GPDMA ((LPC_GPDMA_TypeDef *) LPC_GPDMA_BASE )
antbig 0:ad97421fb1fb 1025 #define LPC_GPDMACH0 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH0_BASE )
antbig 0:ad97421fb1fb 1026 #define LPC_GPDMACH1 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH1_BASE )
antbig 0:ad97421fb1fb 1027 #define LPC_GPDMACH2 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH2_BASE )
antbig 0:ad97421fb1fb 1028 #define LPC_GPDMACH3 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH3_BASE )
antbig 0:ad97421fb1fb 1029 #define LPC_GPDMACH4 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH4_BASE )
antbig 0:ad97421fb1fb 1030 #define LPC_GPDMACH5 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH5_BASE )
antbig 0:ad97421fb1fb 1031 #define LPC_GPDMACH6 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH6_BASE )
antbig 0:ad97421fb1fb 1032 #define LPC_GPDMACH7 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH7_BASE )
antbig 0:ad97421fb1fb 1033 #define LPC_USB ((LPC_USB_TypeDef *) LPC_USB_BASE )
antbig 0:ad97421fb1fb 1034
antbig 0:ad97421fb1fb 1035 #endif // __LPC17xx_H__