CQ Publishing / MARMEX_VB

MARMEX-VB : "Mary Camera module" library

Dependents:   MARMEX_VB_test MARMEX_VB_Hello

MARMEX-VB (MARY-VB) camera module library for mbed. (This module may be available in Japan only.)

Kown problem / 既知の問題

The read data may have contouring. In this case, it may require reset or changing order of data reading. The order change API is available as "read_order_change()" function.
カメラから読み出したデータに擬似輪郭が発生することがあります．この問題にはシステム全体のリセットを行うか，または読み出し順の変更を行うことで対処して下さい．読み出し順の変更はAPIの"read_order_change()"関数を使うことができます．

MARMEX_VB.cpp@1:b2324313d4da, 2014-06-09 (annotated)

Committer:
nxpfan
Date:
Mon Jun 09 19:41:32 2014 +0000
Revision:
1:b2324313d4da
Parent:
0:c4d14dd5d479
Child:
2:88213c3ca312
MARMEX-VB version 0.2

Who changed what in which revision?

UserRevisionLine numberNew contents of line
nxpfan 0:c4d14dd5d479 1 /** MARMEX_VB Camera control library
nxpfan 0:c4d14dd5d479 2 *
nxpfan 0:c4d14dd5d479 3 * @class MARMEX_VB
nxpfan 1:b2324313d4da 4 * @version 0.2
nxpfan 0:c4d14dd5d479 5 * @date 10-Jun-2014
nxpfan 0:c4d14dd5d479 6 *
nxpfan 0:c4d14dd5d479 7 * Released under the Apache License, Version 2.0 : http://mbed.org/handbook/Apache-Licence
nxpfan 0:c4d14dd5d479 8 *
nxpfan 0:c4d14dd5d479 9 * MARMEX_VB Camera control library for mbed
nxpfan 0:c4d14dd5d479 10 */
nxpfan 0:c4d14dd5d479 11
nxpfan 0:c4d14dd5d479 12 #include "mbed.h"
nxpfan 0:c4d14dd5d479 13 #include "MARMEX_VB.h"
nxpfan 0:c4d14dd5d479 14
nxpfan 0:c4d14dd5d479 15 #define SPI_FREQUENCY (12 * 1000 * 1000)
nxpfan 0:c4d14dd5d479 16
nxpfan 0:c4d14dd5d479 17 MARMEX_VB::MARMEX_VB(
nxpfan 0:c4d14dd5d479 18 PinName SPI_mosi,
nxpfan 0:c4d14dd5d479 19 PinName SPI_miso,
nxpfan 0:c4d14dd5d479 20 PinName SPI_sck,
nxpfan 0:c4d14dd5d479 21 PinName SPI_cs,
nxpfan 0:c4d14dd5d479 22 PinName cam_reset,
nxpfan 0:c4d14dd5d479 23 PinName I2C_sda,
nxpfan 0:c4d14dd5d479 24 PinName I2C_scl
nxpfan 0:c4d14dd5d479 25 ) :
nxpfan 0:c4d14dd5d479 26 _spi( SPI_mosi, SPI_miso, SPI_sck ),
nxpfan 0:c4d14dd5d479 27 _cs( SPI_cs ),
nxpfan 0:c4d14dd5d479 28 _reset( cam_reset ),
nxpfan 0:c4d14dd5d479 29 _i2c( I2C_sda, I2C_scl )
nxpfan 0:c4d14dd5d479 30 {
nxpfan 0:c4d14dd5d479 31 #ifdef IGNORE_INITIALIZATION_ERROR
nxpfan 0:c4d14dd5d479 32 init();
nxpfan 0:c4d14dd5d479 33 #else
nxpfan 0:c4d14dd5d479 34 if ( 0 != init() )
nxpfan 0:c4d14dd5d479 35 error( "camera initialization failed." );
nxpfan 0:c4d14dd5d479 36 #endif
nxpfan 0:c4d14dd5d479 37 }
nxpfan 0:c4d14dd5d479 38
nxpfan 0:c4d14dd5d479 39
nxpfan 0:c4d14dd5d479 40 #define CAM_I2C_ADDR 0x42
nxpfan 0:c4d14dd5d479 41
nxpfan 0:c4d14dd5d479 42 #define COMMAND_WRITE 0x00
nxpfan 0:c4d14dd5d479 43 #define COMMAND_READ 0x80
nxpfan 0:c4d14dd5d479 44 #define COMMAND_ADDR_INCREMENT 0x20
nxpfan 0:c4d14dd5d479 45
nxpfan 0:c4d14dd5d479 46 #define MEMORY_ADDR_LOW__REGISTER 0x0
nxpfan 0:c4d14dd5d479 47 #define MEMORY_ADDR_MID__REGISTER 0x1
nxpfan 0:c4d14dd5d479 48 #define MEMORY_ADDR_HIGH_REGISTER 0x2
nxpfan 0:c4d14dd5d479 49 #define CAMERA_DATA_REGISTER 0x8
nxpfan 0:c4d14dd5d479 50 #define CONTROL_DATA_REGISTER 0x3
nxpfan 0:c4d14dd5d479 51 #define STATUS_REGISTER 0x4
nxpfan 0:c4d14dd5d479 52
nxpfan 0:c4d14dd5d479 53 #define CONTROL__PAUSE_BUFFER_UPDATE 0x01
nxpfan 0:c4d14dd5d479 54 #define CONTROL__RESUME_BUFFER_UPDATE 0x00
nxpfan 0:c4d14dd5d479 55
nxpfan 0:c4d14dd5d479 56
nxpfan 0:c4d14dd5d479 57 int MARMEX_VB::init( CameraResolution res )
nxpfan 0:c4d14dd5d479 58 {
nxpfan 0:c4d14dd5d479 59 #define PARAM_NUM 99
nxpfan 0:c4d14dd5d479 60 #define RES_CHANGE_PARAM_NUM 12
nxpfan 0:c4d14dd5d479 61 #define RESET_PULSE_WIDTH 100 // mili-seconds
nxpfan 0:c4d14dd5d479 62 #define RESET_RECOVERY_TIME 100 // mili-seconds
nxpfan 0:c4d14dd5d479 63 #define COMMAND_INTERVAL 20 // mili-seconds
nxpfan 0:c4d14dd5d479 64
nxpfan 0:c4d14dd5d479 65 char camera_register_setting[ PARAM_NUM ][ 2 ] = {
nxpfan 0:c4d14dd5d479 66 { 0x01, 0x40 }, { 0x02, 0x60 }, { 0x03, 0x02 }, { 0x0C, 0x0C },
nxpfan 0:c4d14dd5d479 67 { 0x0E, 0x61 }, { 0x0F, 0x4B }, { 0x11, 0x80 }, { 0x12, 0x04 },
nxpfan 0:c4d14dd5d479 68 { 0x15, 0x00 }, { 0x16, 0x02 }, { 0x17, 0x39 }, { 0x18, 0x03 },
nxpfan 0:c4d14dd5d479 69 { 0x19, 0x03 }, { 0x1A, 0x7B }, { 0x1E, 0x37 }, { 0x21, 0x02 },
nxpfan 0:c4d14dd5d479 70 { 0x22, 0x91 }, { 0x29, 0x07 }, { 0x32, 0x80 }, { 0x33, 0x0B },
nxpfan 0:c4d14dd5d479 71 { 0x34, 0x11 }, { 0x35, 0x0B }, { 0x37, 0x1D }, { 0x38, 0x71 },
nxpfan 0:c4d14dd5d479 72 { 0x39, 0x2A }, { 0x3B, 0x12 }, { 0x3C, 0x78 }, { 0x3D, 0xC3 },
nxpfan 0:c4d14dd5d479 73 { 0x3E, 0x11 }, { 0x3F, 0x00 }, { 0x40, 0xD0 }, { 0x41, 0x08 },
nxpfan 0:c4d14dd5d479 74 { 0x41, 0x38 }, { 0x43, 0x0A }, { 0x44, 0xF0 }, { 0x45, 0x34 },
nxpfan 0:c4d14dd5d479 75 { 0x46, 0x58 }, { 0x47, 0x28 }, { 0x48, 0x3A }, { 0x4B, 0x09 },
nxpfan 0:c4d14dd5d479 76 { 0x4C, 0x00 }, { 0x4D, 0x40 }, { 0x4E, 0x20 }, { 0x4F, 0x80 },
nxpfan 0:c4d14dd5d479 77 { 0x50, 0x80 }, { 0x51, 0x00 }, { 0x52, 0x22 }, { 0x53, 0x5E },
nxpfan 0:c4d14dd5d479 78 { 0x54, 0x80 }, { 0x56, 0x40 }, { 0x58, 0x9E }, { 0x59, 0x88 },
nxpfan 0:c4d14dd5d479 79 { 0x5A, 0x88 }, { 0x5B, 0x44 }, { 0x5C, 0x67 }, { 0x5D, 0x49 },
nxpfan 0:c4d14dd5d479 80 { 0x5E, 0x0E }, { 0x69, 0x00 }, { 0x6A, 0x40 }, { 0x6B, 0x0A },
nxpfan 0:c4d14dd5d479 81 { 0x6C, 0x0A }, { 0x6D, 0x55 }, { 0x6E, 0x11 }, { 0x6F, 0x9F },
nxpfan 0:c4d14dd5d479 82 { 0x70, 0x3A }, { 0x71, 0x35 }, { 0x72, 0x11 }, { 0x73, 0xF1 },
nxpfan 0:c4d14dd5d479 83 { 0x74, 0x10 }, { 0x75, 0x05 }, { 0x76, 0xE1 }, { 0x77, 0x01 },
nxpfan 0:c4d14dd5d479 84 { 0x78, 0x04 }, { 0x79, 0x01 }, { 0x8D, 0x4F }, { 0x8E, 0x00 },
nxpfan 0:c4d14dd5d479 85 { 0x8F, 0x00 }, { 0x90, 0x00 }, { 0x91, 0x00 }, { 0x96, 0x00 },
nxpfan 0:c4d14dd5d479 86 { 0x96, 0x00 }, { 0x97, 0x30 }, { 0x98, 0x20 }, { 0x99, 0x30 },
nxpfan 0:c4d14dd5d479 87 { 0x9A, 0x00 }, { 0x9A, 0x84 }, { 0x9B, 0x29 }, { 0x9C, 0x03 },
nxpfan 0:c4d14dd5d479 88 { 0x9D, 0x4C }, { 0x9E, 0x3F }, { 0xA2, 0x52 }, { 0xA4, 0x88 },
nxpfan 0:c4d14dd5d479 89 { 0xB0, 0x84 }, { 0xB1, 0x0C }, { 0xB2, 0x0E }, { 0xB3, 0x82 },
nxpfan 0:c4d14dd5d479 90 { 0xB8, 0x0A }, { 0xC8, 0xF0 }, { 0xC9, 0x60 },
nxpfan 0:c4d14dd5d479 91 };
nxpfan 0:c4d14dd5d479 92 const char res_change_param[ 5 ][ RES_CHANGE_PARAM_NUM ] = {
nxpfan 0:c4d14dd5d479 93 { 0x17, 0x18, 0x32, 0x19, 0x1a, 0x03, 0x0c, 0x3e, 0x71, 0x72, 0x73, 0xa2 }, // register addr
nxpfan 0:c4d14dd5d479 94 { 0x39, 0x03, 0x80, 0x03, 0x7b, 0x02, 0x0c, 0x11, 0x35, 0x11, 0xf1, 0x52 }, // QSIF
nxpfan 0:c4d14dd5d479 95 { 0x13, 0x01, 0xb6, 0x02, 0x7a, 0x0a, 0x00, 0x00, 0x35, 0x11, 0xf0, 0x02 }, // VGA
nxpfan 0:c4d14dd5d479 96 { 0x16, 0x04, 0x80, 0x02, 0x7a, 0x0a, 0x04, 0x19, 0x35, 0x11, 0xf1, 0x02 }, // QVGA
nxpfan 0:c4d14dd5d479 97 { 0x16, 0x04, 0xa4, 0x02, 0x7a, 0x0a, 0x04, 0x1a, 0x35, 0x22, 0xf2, 0x02 }, // QQVGA
nxpfan 0:c4d14dd5d479 98 };
nxpfan 0:c4d14dd5d479 99 const char camera_reset_command[] = { 0x12, 0x80 };
nxpfan 0:c4d14dd5d479 100
nxpfan 0:c4d14dd5d479 101 _read_order_change = 0;
nxpfan 0:c4d14dd5d479 102
nxpfan 0:c4d14dd5d479 103 // SPI settings
nxpfan 0:c4d14dd5d479 104
nxpfan 1:b2324313d4da 105
nxpfan 0:c4d14dd5d479 106 _cs = 1; // set ChipSelect signal HIGH
nxpfan 0:c4d14dd5d479 107 _spi.format( 8 ); // camera SPI : 8bits/transfer
nxpfan 0:c4d14dd5d479 108 _spi.frequency( SPI_FREQUENCY ); // SPI frequency setting
nxpfan 0:c4d14dd5d479 109 _i2c.frequency( 400 * 1000 );
nxpfan 0:c4d14dd5d479 110
nxpfan 0:c4d14dd5d479 111 // reset
nxpfan 0:c4d14dd5d479 112
nxpfan 0:c4d14dd5d479 113 _reset = 0;
nxpfan 0:c4d14dd5d479 114 wait_ms( RESET_PULSE_WIDTH ); // assert RESET signal
nxpfan 0:c4d14dd5d479 115 _reset = 1;
nxpfan 0:c4d14dd5d479 116 wait_ms( RESET_RECOVERY_TIME ); // deassert RESET signal
nxpfan 0:c4d14dd5d479 117
nxpfan 0:c4d14dd5d479 118 if ( 0 != (_error_state = _i2c.write( CAM_I2C_ADDR, camera_reset_command, 2 )) )
nxpfan 0:c4d14dd5d479 119 return _error_state; // return non-zero if I2C access failed
nxpfan 0:c4d14dd5d479 120
nxpfan 0:c4d14dd5d479 121 wait_ms( 100 ); // reset (via I2C) recovery time
nxpfan 0:c4d14dd5d479 122
nxpfan 0:c4d14dd5d479 123 _horizontal_size = QCIF_PIXEL_PER_LINE;
nxpfan 0:c4d14dd5d479 124 _vertical_size = QCIF_LINE_PER_FRAME;
nxpfan 0:c4d14dd5d479 125
nxpfan 0:c4d14dd5d479 126 #ifdef UNIFIED_RESOLUTION_CHANGE
nxpfan 0:c4d14dd5d479 127 if ( QCIF != res ) {
nxpfan 0:c4d14dd5d479 128 for ( int i = 0; i < RES_CHANGE_PARAM_NUM; i++ ) {
nxpfan 0:c4d14dd5d479 129 for ( int j = 0; j < PARAM_NUM; j++ ) {
nxpfan 0:c4d14dd5d479 130 if ( camera_register_setting[ j ][ 0 ] == res_change_param[ 0 ][ i ] ) {
nxpfan 0:c4d14dd5d479 131 camera_register_setting[ j ][ 1 ] = res_change_param[ res ][ i ];
nxpfan 0:c4d14dd5d479 132 }
nxpfan 0:c4d14dd5d479 133 }
nxpfan 0:c4d14dd5d479 134 }
nxpfan 0:c4d14dd5d479 135 }
nxpfan 0:c4d14dd5d479 136
nxpfan 0:c4d14dd5d479 137 switch ( res ) {
nxpfan 0:c4d14dd5d479 138 case QCIF:
nxpfan 0:c4d14dd5d479 139 _horizontal_size = QCIF_PIXEL_PER_LINE;
nxpfan 0:c4d14dd5d479 140 _vertical_size = QCIF_LINE_PER_FRAME;
nxpfan 0:c4d14dd5d479 141 break;
nxpfan 0:c4d14dd5d479 142 case VGA:
nxpfan 0:c4d14dd5d479 143 _horizontal_size = VGA_PIXEL_PER_LINE;
nxpfan 0:c4d14dd5d479 144 _vertical_size = VGA_LINE_PER_FRAME;
nxpfan 0:c4d14dd5d479 145 break;
nxpfan 0:c4d14dd5d479 146 case QVGA:
nxpfan 0:c4d14dd5d479 147 _horizontal_size = VGA_PIXEL_PER_LINE / 2;
nxpfan 0:c4d14dd5d479 148 _vertical_size = VGA_LINE_PER_FRAME / 2;
nxpfan 0:c4d14dd5d479 149 break;
nxpfan 0:c4d14dd5d479 150 case QQVGA:
nxpfan 0:c4d14dd5d479 151 _horizontal_size = VGA_PIXEL_PER_LINE / 4;
nxpfan 0:c4d14dd5d479 152 _vertical_size = VGA_LINE_PER_FRAME / 4;
nxpfan 0:c4d14dd5d479 153 break;
nxpfan 0:c4d14dd5d479 154 }
nxpfan 0:c4d14dd5d479 155 #endif
nxpfan 0:c4d14dd5d479 156
nxpfan 0:c4d14dd5d479 157
nxpfan 0:c4d14dd5d479 158 for ( int i = 0; i < PARAM_NUM; i++ ) {
nxpfan 0:c4d14dd5d479 159 if ( 0 != (_error_state = _i2c.write( CAM_I2C_ADDR, camera_register_setting[ i ], 2 )) )
nxpfan 0:c4d14dd5d479 160 break;
nxpfan 0:c4d14dd5d479 161
nxpfan 0:c4d14dd5d479 162 wait_ms( COMMAND_INTERVAL ); // camera register writing requires this interval
nxpfan 0:c4d14dd5d479 163 }
nxpfan 0:c4d14dd5d479 164
nxpfan 0:c4d14dd5d479 165 #ifndef UNIFIED_RESOLUTION_CHANGE
nxpfan 0:c4d14dd5d479 166 if ( QCIF != res ) {
nxpfan 0:c4d14dd5d479 167 char d[ 2 ];
nxpfan 0:c4d14dd5d479 168 for ( int i = 0; i < RES_CHANGE_PARAM_NUM; i++ ) {
nxpfan 0:c4d14dd5d479 169 d[ 0 ] = res_change_param[ 0 ][ i ];
nxpfan 0:c4d14dd5d479 170 d[ 1 ] = res_change_param[ res ][ i ];
nxpfan 0:c4d14dd5d479 171
nxpfan 0:c4d14dd5d479 172 if ( 0 != (_error_state = _i2c.write( CAM_I2C_ADDR, d, 2 )) )
nxpfan 0:c4d14dd5d479 173 break;
nxpfan 0:c4d14dd5d479 174
nxpfan 0:c4d14dd5d479 175 wait_ms( COMMAND_INTERVAL ); // camera register writing requires this interval
nxpfan 0:c4d14dd5d479 176 }
nxpfan 0:c4d14dd5d479 177 }
nxpfan 0:c4d14dd5d479 178
nxpfan 0:c4d14dd5d479 179 switch ( res ) {
nxpfan 0:c4d14dd5d479 180 case QCIF:
nxpfan 0:c4d14dd5d479 181 _horizontal_size = QCIF_PIXEL_PER_LINE;
nxpfan 0:c4d14dd5d479 182 _vertical_size = QCIF_LINE_PER_FRAME;
nxpfan 0:c4d14dd5d479 183 break;
nxpfan 0:c4d14dd5d479 184 case VGA:
nxpfan 0:c4d14dd5d479 185 _horizontal_size = VGA_PIXEL_PER_LINE;
nxpfan 0:c4d14dd5d479 186 _vertical_size = VGA_LINE_PER_FRAME;
nxpfan 0:c4d14dd5d479 187 break;
nxpfan 0:c4d14dd5d479 188 case QVGA:
nxpfan 0:c4d14dd5d479 189 _horizontal_size = VGA_PIXEL_PER_LINE / 2;
nxpfan 0:c4d14dd5d479 190 _vertical_size = VGA_LINE_PER_FRAME / 2;
nxpfan 0:c4d14dd5d479 191 break;
nxpfan 0:c4d14dd5d479 192 case QQVGA:
nxpfan 0:c4d14dd5d479 193 _horizontal_size = VGA_PIXEL_PER_LINE / 4;
nxpfan 0:c4d14dd5d479 194 _vertical_size = VGA_LINE_PER_FRAME / 4;
nxpfan 0:c4d14dd5d479 195 break;
nxpfan 0:c4d14dd5d479 196 }
nxpfan 0:c4d14dd5d479 197 #endif
nxpfan 0:c4d14dd5d479 198
nxpfan 0:c4d14dd5d479 199 return _error_state; // return non-zero if I2C access failed
nxpfan 0:c4d14dd5d479 200 }
nxpfan 0:c4d14dd5d479 201
nxpfan 0:c4d14dd5d479 202 void MARMEX_VB::colorbar( SwitchState sw )
nxpfan 0:c4d14dd5d479 203 {
nxpfan 0:c4d14dd5d479 204 char s[ 2 ];
nxpfan 0:c4d14dd5d479 205
nxpfan 0:c4d14dd5d479 206 s[ 0 ] = 0x12;
nxpfan 0:c4d14dd5d479 207 s[ 1 ] = sw ? 0x06 : 0x04;
nxpfan 0:c4d14dd5d479 208
nxpfan 0:c4d14dd5d479 209 _error_state = _i2c.write( CAM_I2C_ADDR, s, 2 );
nxpfan 0:c4d14dd5d479 210 }
nxpfan 0:c4d14dd5d479 211
nxpfan 0:c4d14dd5d479 212 int MARMEX_VB::get_horizontal_size( void )
nxpfan 0:c4d14dd5d479 213 {
nxpfan 0:c4d14dd5d479 214 return _horizontal_size; // return last state of I2C access
nxpfan 0:c4d14dd5d479 215 }
nxpfan 0:c4d14dd5d479 216
nxpfan 0:c4d14dd5d479 217 int MARMEX_VB::get_vertical_size( void )
nxpfan 0:c4d14dd5d479 218 {
nxpfan 0:c4d14dd5d479 219 return _vertical_size; // return last state of I2C access
nxpfan 0:c4d14dd5d479 220 }
nxpfan 0:c4d14dd5d479 221
nxpfan 0:c4d14dd5d479 222 int MARMEX_VB::ready( void )
nxpfan 0:c4d14dd5d479 223 {
nxpfan 0:c4d14dd5d479 224 return _error_state; // return last state of I2C access
nxpfan 0:c4d14dd5d479 225 }
nxpfan 0:c4d14dd5d479 226
nxpfan 0:c4d14dd5d479 227 extern int read_order_change;
nxpfan 0:c4d14dd5d479 228
nxpfan 0:c4d14dd5d479 229 void MARMEX_VB::read_a_line( short *p, int line_number, int x_offset, int n_of_pixels )
nxpfan 0:c4d14dd5d479 230 {
nxpfan 0:c4d14dd5d479 231 #if 0
nxpfan 0:c4d14dd5d479 232
nxpfan 0:c4d14dd5d479 233 char tmp;
nxpfan 0:c4d14dd5d479 234
nxpfan 0:c4d14dd5d479 235 if ( line_number < 0 )
nxpfan 0:c4d14dd5d479 236 return;
nxpfan 0:c4d14dd5d479 237
nxpfan 0:c4d14dd5d479 238 // set camera module's buffer address
nxpfan 0:c4d14dd5d479 239 set_address( line_number * get_horizontal_size() * BYTE_PER_PIXEL + x_offset * BYTE_PER_PIXEL );
nxpfan 0:c4d14dd5d479 240
nxpfan 0:c4d14dd5d479 241 // put a read command, first return byte should be ignored
nxpfan 0:c4d14dd5d479 242 read_register( CAMERA_DATA_REGISTER );
nxpfan 0:c4d14dd5d479 243
nxpfan 0:c4d14dd5d479 244 for( int x = 0; x < n_of_pixels; x++ ) {
nxpfan 0:c4d14dd5d479 245 // perform 2 bytes read. a pixel data is in RGB565 format (16bits)
nxpfan 0:c4d14dd5d479 246 tmp = read_register( CAMERA_DATA_REGISTER ); // read lower byte
nxpfan 0:c4d14dd5d479 247 *p++ = (read_register( CAMERA_DATA_REGISTER ) << 8) | tmp; // read upper byte
nxpfan 0:c4d14dd5d479 248 }
nxpfan 0:c4d14dd5d479 249
nxpfan 0:c4d14dd5d479 250 #else
nxpfan 0:c4d14dd5d479 251
nxpfan 0:c4d14dd5d479 252
nxpfan 0:c4d14dd5d479 253 short tmp;
nxpfan 0:c4d14dd5d479 254
nxpfan 0:c4d14dd5d479 255 if ( line_number < 0 )
nxpfan 0:c4d14dd5d479 256 return;
nxpfan 0:c4d14dd5d479 257
nxpfan 0:c4d14dd5d479 258 // set camera module's buffer address
nxpfan 0:c4d14dd5d479 259 set_address( line_number * get_horizontal_size() * BYTE_PER_PIXEL + x_offset * BYTE_PER_PIXEL );
nxpfan 0:c4d14dd5d479 260
nxpfan 0:c4d14dd5d479 261 // put a read command, first return byte should be ignored
nxpfan 0:c4d14dd5d479 262 read_register( CAMERA_DATA_REGISTER );
nxpfan 0:c4d14dd5d479 263
nxpfan 0:c4d14dd5d479 264
nxpfan 0:c4d14dd5d479 265 if ( _read_order_change ) {
nxpfan 0:c4d14dd5d479 266
nxpfan 0:c4d14dd5d479 267 read_register( CAMERA_DATA_REGISTER );
nxpfan 0:c4d14dd5d479 268
nxpfan 0:c4d14dd5d479 269 for( int x = 0; x < n_of_pixels; x++ ) {
nxpfan 0:c4d14dd5d479 270 // perform 2 bytes read. a pixel data is in RGB565 format (16bits)
nxpfan 0:c4d14dd5d479 271 tmp = read_register( CAMERA_DATA_REGISTER ) << 8; // read lower byte
nxpfan 0:c4d14dd5d479 272 *p++ = (read_register( CAMERA_DATA_REGISTER ) << 0) | tmp; // read upper byte
nxpfan 0:c4d14dd5d479 273 }
nxpfan 0:c4d14dd5d479 274
nxpfan 0:c4d14dd5d479 275 } else {
nxpfan 0:c4d14dd5d479 276
nxpfan 1:b2324313d4da 277 #define OPTIMIZE_BY_GPIO_REGISTER_ACCESS
nxpfan 1:b2324313d4da 278 #if defined( TARGET_MBED_LPC1768 ) && defined (OPTIMIZE_BY_GPIO_REGISTER_ACCESS )
nxpfan 1:b2324313d4da 279 // optimized by IO register access and loop unroll
nxpfan 1:b2324313d4da 280 LPC_GPIO2->FIOMASK = ~0x10;
nxpfan 1:b2324313d4da 281
nxpfan 1:b2324313d4da 282 char reg = COMMAND_READ | CAMERA_DATA_REGISTER | COMMAND_ADDR_INCREMENT;
nxpfan 1:b2324313d4da 283
nxpfan 1:b2324313d4da 284 for( int x = 0; x < n_of_pixels; x += 8 ) {
nxpfan 1:b2324313d4da 285 // perform 2 bytes read. a pixel data is in RGB565 format (16bits)
nxpfan 1:b2324313d4da 286
nxpfan 1:b2324313d4da 287 LPC_GPIO2->FIOCLR = 0x10;
nxpfan 1:b2324313d4da 288 *p = _spi.write( reg );
nxpfan 1:b2324313d4da 289 LPC_GPIO2->FIOSET = 0x10;
nxpfan 1:b2324313d4da 290
nxpfan 1:b2324313d4da 291 LPC_GPIO2->FIOCLR = 0x10;
nxpfan 1:b2324313d4da 292 *p++ |= _spi.write( reg ) << 8;
nxpfan 1:b2324313d4da 293 LPC_GPIO2->FIOSET = 0x10;
nxpfan 1:b2324313d4da 294
nxpfan 1:b2324313d4da 295 LPC_GPIO2->FIOCLR = 0x10;
nxpfan 1:b2324313d4da 296 *p = _spi.write( reg );
nxpfan 1:b2324313d4da 297 LPC_GPIO2->FIOSET = 0x10;
nxpfan 1:b2324313d4da 298
nxpfan 1:b2324313d4da 299 LPC_GPIO2->FIOCLR = 0x10;
nxpfan 1:b2324313d4da 300 *p++ |= _spi.write( reg ) << 8;
nxpfan 1:b2324313d4da 301 LPC_GPIO2->FIOSET = 0x10;
nxpfan 1:b2324313d4da 302
nxpfan 1:b2324313d4da 303 LPC_GPIO2->FIOCLR = 0x10;
nxpfan 1:b2324313d4da 304 *p = _spi.write( reg );
nxpfan 1:b2324313d4da 305 LPC_GPIO2->FIOSET = 0x10;
nxpfan 1:b2324313d4da 306
nxpfan 1:b2324313d4da 307 LPC_GPIO2->FIOCLR = 0x10;
nxpfan 1:b2324313d4da 308 *p++ |= _spi.write( reg ) << 8;
nxpfan 1:b2324313d4da 309 LPC_GPIO2->FIOSET = 0x10;
nxpfan 1:b2324313d4da 310
nxpfan 1:b2324313d4da 311 LPC_GPIO2->FIOCLR = 0x10;
nxpfan 1:b2324313d4da 312 *p = _spi.write( reg );
nxpfan 1:b2324313d4da 313 LPC_GPIO2->FIOSET = 0x10;
nxpfan 1:b2324313d4da 314
nxpfan 1:b2324313d4da 315 LPC_GPIO2->FIOCLR = 0x10;
nxpfan 1:b2324313d4da 316 *p++ |= _spi.write( reg ) << 8;
nxpfan 1:b2324313d4da 317 LPC_GPIO2->FIOSET = 0x10;
nxpfan 1:b2324313d4da 318
nxpfan 1:b2324313d4da 319 LPC_GPIO2->FIOCLR = 0x10;
nxpfan 1:b2324313d4da 320 *p = _spi.write( reg );
nxpfan 1:b2324313d4da 321 LPC_GPIO2->FIOSET = 0x10;
nxpfan 1:b2324313d4da 322
nxpfan 1:b2324313d4da 323 LPC_GPIO2->FIOCLR = 0x10;
nxpfan 1:b2324313d4da 324 *p++ |= _spi.write( reg ) << 8;
nxpfan 1:b2324313d4da 325 LPC_GPIO2->FIOSET = 0x10;
nxpfan 1:b2324313d4da 326
nxpfan 1:b2324313d4da 327 LPC_GPIO2->FIOCLR = 0x10;
nxpfan 1:b2324313d4da 328 *p = _spi.write( reg );
nxpfan 1:b2324313d4da 329 LPC_GPIO2->FIOSET = 0x10;
nxpfan 1:b2324313d4da 330
nxpfan 1:b2324313d4da 331 LPC_GPIO2->FIOCLR = 0x10;
nxpfan 1:b2324313d4da 332 *p++ |= _spi.write( reg ) << 8;
nxpfan 1:b2324313d4da 333 LPC_GPIO2->FIOSET = 0x10;
nxpfan 1:b2324313d4da 334
nxpfan 1:b2324313d4da 335 LPC_GPIO2->FIOCLR = 0x10;
nxpfan 1:b2324313d4da 336 *p = _spi.write( reg );
nxpfan 1:b2324313d4da 337 LPC_GPIO2->FIOSET = 0x10;
nxpfan 1:b2324313d4da 338
nxpfan 1:b2324313d4da 339 LPC_GPIO2->FIOCLR = 0x10;
nxpfan 1:b2324313d4da 340 *p++ |= _spi.write( reg ) << 8;
nxpfan 1:b2324313d4da 341 LPC_GPIO2->FIOSET = 0x10;
nxpfan 1:b2324313d4da 342
nxpfan 1:b2324313d4da 343 LPC_GPIO2->FIOCLR = 0x10;
nxpfan 1:b2324313d4da 344 *p = _spi.write( reg );
nxpfan 1:b2324313d4da 345 LPC_GPIO2->FIOSET = 0x10;
nxpfan 1:b2324313d4da 346
nxpfan 1:b2324313d4da 347 LPC_GPIO2->FIOCLR = 0x10;
nxpfan 1:b2324313d4da 348 *p++ |= _spi.write( reg ) << 8;
nxpfan 1:b2324313d4da 349 LPC_GPIO2->FIOSET = 0x10;
nxpfan 1:b2324313d4da 350 }
nxpfan 1:b2324313d4da 351
nxpfan 1:b2324313d4da 352 #else
nxpfan 0:c4d14dd5d479 353 for( int x = 0; x < n_of_pixels; x++ ) {
nxpfan 0:c4d14dd5d479 354 // perform 2 bytes read. a pixel data is in RGB565 format (16bits)
nxpfan 0:c4d14dd5d479 355 tmp = read_register( CAMERA_DATA_REGISTER ); // read lower byte
nxpfan 0:c4d14dd5d479 356 *p++ = (read_register( CAMERA_DATA_REGISTER ) << 8) | tmp; // read upper byte
nxpfan 0:c4d14dd5d479 357 }
nxpfan 1:b2324313d4da 358 #endif
nxpfan 0:c4d14dd5d479 359 }
nxpfan 0:c4d14dd5d479 360
nxpfan 0:c4d14dd5d479 361 #endif
nxpfan 0:c4d14dd5d479 362 }
nxpfan 0:c4d14dd5d479 363
nxpfan 0:c4d14dd5d479 364 void MARMEX_VB::open_transfer( void )
nxpfan 0:c4d14dd5d479 365 {
nxpfan 0:c4d14dd5d479 366 // send command to pause the camera buffer update
nxpfan 0:c4d14dd5d479 367 write_register( CONTROL_DATA_REGISTER, CONTROL__PAUSE_BUFFER_UPDATE );
nxpfan 0:c4d14dd5d479 368
nxpfan 0:c4d14dd5d479 369 // read status register (first return byte should be ignored)
nxpfan 0:c4d14dd5d479 370 read_register( STATUS_REGISTER );
nxpfan 0:c4d14dd5d479 371
nxpfan 0:c4d14dd5d479 372 // wait until the status register become 0x51(ready to transfer data)
nxpfan 0:c4d14dd5d479 373 while ( 0x51 != read_register( STATUS_REGISTER ) )
nxpfan 0:c4d14dd5d479 374 ;
nxpfan 0:c4d14dd5d479 375 }
nxpfan 0:c4d14dd5d479 376
nxpfan 0:c4d14dd5d479 377 void MARMEX_VB::close_transfer( void )
nxpfan 0:c4d14dd5d479 378 {
nxpfan 0:c4d14dd5d479 379 // send command to resume the camera buffer update
nxpfan 0:c4d14dd5d479 380 write_register( CONTROL_DATA_REGISTER, CONTROL__RESUME_BUFFER_UPDATE );
nxpfan 0:c4d14dd5d479 381
nxpfan 0:c4d14dd5d479 382 // read status register (first return byte should be ignored)
nxpfan 0:c4d14dd5d479 383 read_register( STATUS_REGISTER );
nxpfan 0:c4d14dd5d479 384
nxpfan 0:c4d14dd5d479 385 // wait until the status register become 0x50(camera updating the buffer)
nxpfan 0:c4d14dd5d479 386 while ( 0x50 != read_register( STATUS_REGISTER ) )
nxpfan 0:c4d14dd5d479 387 ;
nxpfan 0:c4d14dd5d479 388 }
nxpfan 0:c4d14dd5d479 389
nxpfan 0:c4d14dd5d479 390 int MARMEX_VB::read_order_change( void )
nxpfan 0:c4d14dd5d479 391 {
nxpfan 0:c4d14dd5d479 392 return ( _read_order_change = !_read_order_change );
nxpfan 0:c4d14dd5d479 393 }
nxpfan 0:c4d14dd5d479 394
nxpfan 0:c4d14dd5d479 395 void MARMEX_VB::set_address( int address )
nxpfan 0:c4d14dd5d479 396 {
nxpfan 0:c4d14dd5d479 397 // set memory address (3 bytes)
nxpfan 0:c4d14dd5d479 398
nxpfan 0:c4d14dd5d479 399 write_register( MEMORY_ADDR_LOW__REGISTER, (address >> 0) & 0xFF );
nxpfan 0:c4d14dd5d479 400 write_register( MEMORY_ADDR_MID__REGISTER, (address >> 8) & 0xFF );
nxpfan 0:c4d14dd5d479 401 write_register( MEMORY_ADDR_HIGH_REGISTER, (address >> 16) & 0xFF );
nxpfan 0:c4d14dd5d479 402 }
nxpfan 0:c4d14dd5d479 403
nxpfan 0:c4d14dd5d479 404 void MARMEX_VB::write_register( char reg, char value )
nxpfan 0:c4d14dd5d479 405 {
nxpfan 0:c4d14dd5d479 406 // camera register write
nxpfan 0:c4d14dd5d479 407
nxpfan 0:c4d14dd5d479 408 send_spi( COMMAND_WRITE | reg ); // send command and register number
nxpfan 0:c4d14dd5d479 409 send_spi( value ); // send register value
nxpfan 0:c4d14dd5d479 410 }
nxpfan 0:c4d14dd5d479 411
nxpfan 0:c4d14dd5d479 412 int MARMEX_VB::read_register( char reg )
nxpfan 0:c4d14dd5d479 413 {
nxpfan 0:c4d14dd5d479 414 // camera register read
nxpfan 0:c4d14dd5d479 415 // returning current data in SPI buffer (data returned by previous command)
nxpfan 0:c4d14dd5d479 416
nxpfan 0:c4d14dd5d479 417 return ( send_spi( COMMAND_READ | reg | ((reg == CAMERA_DATA_REGISTER) ? COMMAND_ADDR_INCREMENT : 0x00) ) );
nxpfan 0:c4d14dd5d479 418 }
nxpfan 0:c4d14dd5d479 419
nxpfan 0:c4d14dd5d479 420 int MARMEX_VB::send_spi( char data )
nxpfan 0:c4d14dd5d479 421 {
nxpfan 0:c4d14dd5d479 422 int tmp;
nxpfan 0:c4d14dd5d479 423
nxpfan 0:c4d14dd5d479 424 // SPI access
nxpfan 0:c4d14dd5d479 425 _cs = 0;
nxpfan 1:b2324313d4da 426 LPC_GPIO2->FIOCLR = 0x10;
nxpfan 0:c4d14dd5d479 427 tmp = _spi.write( data );
nxpfan 0:c4d14dd5d479 428 _cs = 1;
nxpfan 0:c4d14dd5d479 429
nxpfan 0:c4d14dd5d479 430 return ( tmp );
nxpfan 0:c4d14dd5d479 431 }