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(Working) Code to interface 3 LoadCells to ADISense1000 and display values using the Labview code.
Fork of 4Bridge_ADISense1000_Example_copy by
src/adi_sense_1000/ADISENSE1000_REGISTERS_typedefs.h@0:76fed7dd9235, 2018-01-25 (annotated)
- Committer:
- seanwilson10
- Date:
- Thu Jan 25 16:00:23 2018 +0000
- Revision:
- 0:76fed7dd9235
initial;
Who changed what in which revision?
User | Revision | Line number | New contents of line |
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seanwilson10 | 0:76fed7dd9235 | 1 | /* ================================================================================ |
seanwilson10 | 0:76fed7dd9235 | 2 | |
seanwilson10 | 0:76fed7dd9235 | 3 | Created by : sherry |
seanwilson10 | 0:76fed7dd9235 | 4 | Created on : 2017 Nov 14, 10:55 GMT |
seanwilson10 | 0:76fed7dd9235 | 5 | |
seanwilson10 | 0:76fed7dd9235 | 6 | Project : ADISENSE1000_REGISTERS |
seanwilson10 | 0:76fed7dd9235 | 7 | File : ADISENSE1000_REGISTERS_typedefs.h |
seanwilson10 | 0:76fed7dd9235 | 8 | Description : C Register Structures |
seanwilson10 | 0:76fed7dd9235 | 9 | |
seanwilson10 | 0:76fed7dd9235 | 10 | !! ADI Confidential !! |
seanwilson10 | 0:76fed7dd9235 | 11 | INTERNAL USE ONLY |
seanwilson10 | 0:76fed7dd9235 | 12 | |
seanwilson10 | 0:76fed7dd9235 | 13 | Copyright (c) 2017 Analog Devices, Inc. All Rights Reserved. |
seanwilson10 | 0:76fed7dd9235 | 14 | This software is proprietary and confidential to Analog Devices, Inc. and |
seanwilson10 | 0:76fed7dd9235 | 15 | its licensors. |
seanwilson10 | 0:76fed7dd9235 | 16 | |
seanwilson10 | 0:76fed7dd9235 | 17 | This file was auto-generated. Do not make local changes to this file. |
seanwilson10 | 0:76fed7dd9235 | 18 | |
seanwilson10 | 0:76fed7dd9235 | 19 | Auto generation script information: |
seanwilson10 | 0:76fed7dd9235 | 20 | Script: /usr/cadtools/bin/yoda.dir/generators/inc/genHeaders |
seanwilson10 | 0:76fed7dd9235 | 21 | Last modified: 26-SEP-2017 |
seanwilson10 | 0:76fed7dd9235 | 22 | |
seanwilson10 | 0:76fed7dd9235 | 23 | ================================================================================ */ |
seanwilson10 | 0:76fed7dd9235 | 24 | |
seanwilson10 | 0:76fed7dd9235 | 25 | #ifndef _ADISENSE1000_REGISTERS_TYPEDEFS_H |
seanwilson10 | 0:76fed7dd9235 | 26 | #define _ADISENSE1000_REGISTERS_TYPEDEFS_H |
seanwilson10 | 0:76fed7dd9235 | 27 | |
seanwilson10 | 0:76fed7dd9235 | 28 | /* pickup integer types */ |
seanwilson10 | 0:76fed7dd9235 | 29 | #if defined(_LANGUAGE_C) || (defined(__GNUC__) && !defined(__ASSEMBLER__)) |
seanwilson10 | 0:76fed7dd9235 | 30 | #include <stdint.h> |
seanwilson10 | 0:76fed7dd9235 | 31 | #endif /* _LANGUAGE_C */ |
seanwilson10 | 0:76fed7dd9235 | 32 | |
seanwilson10 | 0:76fed7dd9235 | 33 | #if defined ( __CC_ARM ) |
seanwilson10 | 0:76fed7dd9235 | 34 | #pragma push |
seanwilson10 | 0:76fed7dd9235 | 35 | #pragma anon_unions |
seanwilson10 | 0:76fed7dd9235 | 36 | #endif |
seanwilson10 | 0:76fed7dd9235 | 37 | |
seanwilson10 | 0:76fed7dd9235 | 38 | /** @defgroup Interface_Config_A Interface Configuration A (Interface_Config_A) Register |
seanwilson10 | 0:76fed7dd9235 | 39 | * Interface Configuration A (Interface_Config_A) Register. |
seanwilson10 | 0:76fed7dd9235 | 40 | * @{ |
seanwilson10 | 0:76fed7dd9235 | 41 | */ |
seanwilson10 | 0:76fed7dd9235 | 42 | |
seanwilson10 | 0:76fed7dd9235 | 43 | /* ========================================================================= |
seanwilson10 | 0:76fed7dd9235 | 44 | *! \enum ADI_ADISENSE_SPI_Interface_Config_A_Addr_Ascension |
seanwilson10 | 0:76fed7dd9235 | 45 | *! \brief Determines Sequential Addressing Behavior (Addr_Ascension) Enumerations |
seanwilson10 | 0:76fed7dd9235 | 46 | * ========================================================================= */ |
seanwilson10 | 0:76fed7dd9235 | 47 | typedef enum |
seanwilson10 | 0:76fed7dd9235 | 48 | { |
seanwilson10 | 0:76fed7dd9235 | 49 | ADISENSE_SPI_INTERFACE_CONFIG_A_DESCEND = 0, /**< Address accessed is decremented by one for each data byte when streaming */ |
seanwilson10 | 0:76fed7dd9235 | 50 | ADISENSE_SPI_INTERFACE_CONFIG_A_ASCEND = 1 /**< Address accessed is incremented by one for each data byte when streaming */ |
seanwilson10 | 0:76fed7dd9235 | 51 | } ADI_ADISENSE_SPI_Interface_Config_A_Addr_Ascension; |
seanwilson10 | 0:76fed7dd9235 | 52 | |
seanwilson10 | 0:76fed7dd9235 | 53 | |
seanwilson10 | 0:76fed7dd9235 | 54 | /* ========================================================================== |
seanwilson10 | 0:76fed7dd9235 | 55 | *! \struct ADI_ADISENSE_SPI_Interface_Config_A_Struct |
seanwilson10 | 0:76fed7dd9235 | 56 | *! \brief Interface Configuration A Register bit field structure |
seanwilson10 | 0:76fed7dd9235 | 57 | * ========================================================================== */ |
seanwilson10 | 0:76fed7dd9235 | 58 | typedef struct _ADI_ADISENSE_SPI_Interface_Config_A_t { |
seanwilson10 | 0:76fed7dd9235 | 59 | union { |
seanwilson10 | 0:76fed7dd9235 | 60 | struct { |
seanwilson10 | 0:76fed7dd9235 | 61 | uint8_t SW_ResetX : 1; /**< Second of Two of SW_RESET Bits. */ |
seanwilson10 | 0:76fed7dd9235 | 62 | uint8_t reserved1 : 3; |
seanwilson10 | 0:76fed7dd9235 | 63 | uint8_t SDO_Enable : 1; /**< SDO Pin Enable */ |
seanwilson10 | 0:76fed7dd9235 | 64 | uint8_t Addr_Ascension : 1; /**< Determines Sequential Addressing Behavior */ |
seanwilson10 | 0:76fed7dd9235 | 65 | uint8_t reserved6 : 1; |
seanwilson10 | 0:76fed7dd9235 | 66 | uint8_t SW_Reset : 1; /**< First of Two of SW_RESET Bits. */ |
seanwilson10 | 0:76fed7dd9235 | 67 | }; |
seanwilson10 | 0:76fed7dd9235 | 68 | uint8_t VALUE8; |
seanwilson10 | 0:76fed7dd9235 | 69 | }; |
seanwilson10 | 0:76fed7dd9235 | 70 | } ADI_ADISENSE_SPI_Interface_Config_A_t; |
seanwilson10 | 0:76fed7dd9235 | 71 | |
seanwilson10 | 0:76fed7dd9235 | 72 | /*@}*/ |
seanwilson10 | 0:76fed7dd9235 | 73 | |
seanwilson10 | 0:76fed7dd9235 | 74 | /** @defgroup Interface_Config_B Interface Configuration B (Interface_Config_B) Register |
seanwilson10 | 0:76fed7dd9235 | 75 | * Interface Configuration B (Interface_Config_B) Register. |
seanwilson10 | 0:76fed7dd9235 | 76 | * @{ |
seanwilson10 | 0:76fed7dd9235 | 77 | */ |
seanwilson10 | 0:76fed7dd9235 | 78 | |
seanwilson10 | 0:76fed7dd9235 | 79 | /* ========================================================================= |
seanwilson10 | 0:76fed7dd9235 | 80 | *! \enum ADI_ADISENSE_SPI_Interface_Config_B_Single_Inst |
seanwilson10 | 0:76fed7dd9235 | 81 | *! \brief Select Streaming or Single Instruction Mode (Single_Inst) Enumerations |
seanwilson10 | 0:76fed7dd9235 | 82 | * ========================================================================= */ |
seanwilson10 | 0:76fed7dd9235 | 83 | typedef enum |
seanwilson10 | 0:76fed7dd9235 | 84 | { |
seanwilson10 | 0:76fed7dd9235 | 85 | ADISENSE_SPI_INTERFACE_CONFIG_B_STREAMING_MODE = 0, /**< Streaming mode is enabled */ |
seanwilson10 | 0:76fed7dd9235 | 86 | ADISENSE_SPI_INTERFACE_CONFIG_B_SINGLE_INSTRUCTION_MODE = 1 /**< Single Instruction mode is enabled */ |
seanwilson10 | 0:76fed7dd9235 | 87 | } ADI_ADISENSE_SPI_Interface_Config_B_Single_Inst; |
seanwilson10 | 0:76fed7dd9235 | 88 | |
seanwilson10 | 0:76fed7dd9235 | 89 | |
seanwilson10 | 0:76fed7dd9235 | 90 | /* ========================================================================== |
seanwilson10 | 0:76fed7dd9235 | 91 | *! \struct ADI_ADISENSE_SPI_Interface_Config_B_Struct |
seanwilson10 | 0:76fed7dd9235 | 92 | *! \brief Interface Configuration B Register bit field structure |
seanwilson10 | 0:76fed7dd9235 | 93 | * ========================================================================== */ |
seanwilson10 | 0:76fed7dd9235 | 94 | typedef struct _ADI_ADISENSE_SPI_Interface_Config_B_t { |
seanwilson10 | 0:76fed7dd9235 | 95 | union { |
seanwilson10 | 0:76fed7dd9235 | 96 | struct { |
seanwilson10 | 0:76fed7dd9235 | 97 | uint8_t reserved0 : 7; |
seanwilson10 | 0:76fed7dd9235 | 98 | uint8_t Single_Inst : 1; /**< Select Streaming or Single Instruction Mode */ |
seanwilson10 | 0:76fed7dd9235 | 99 | }; |
seanwilson10 | 0:76fed7dd9235 | 100 | uint8_t VALUE8; |
seanwilson10 | 0:76fed7dd9235 | 101 | }; |
seanwilson10 | 0:76fed7dd9235 | 102 | } ADI_ADISENSE_SPI_Interface_Config_B_t; |
seanwilson10 | 0:76fed7dd9235 | 103 | |
seanwilson10 | 0:76fed7dd9235 | 104 | /*@}*/ |
seanwilson10 | 0:76fed7dd9235 | 105 | |
seanwilson10 | 0:76fed7dd9235 | 106 | /** @defgroup Device_Config Device Configuration (Device_Config) Register |
seanwilson10 | 0:76fed7dd9235 | 107 | * Device Configuration (Device_Config) Register. |
seanwilson10 | 0:76fed7dd9235 | 108 | * @{ |
seanwilson10 | 0:76fed7dd9235 | 109 | */ |
seanwilson10 | 0:76fed7dd9235 | 110 | |
seanwilson10 | 0:76fed7dd9235 | 111 | /* ========================================================================= |
seanwilson10 | 0:76fed7dd9235 | 112 | *! \enum ADI_ADISENSE_SPI_Device_Config_Operating_Modes |
seanwilson10 | 0:76fed7dd9235 | 113 | *! \brief Power Modes (Operating_Modes) Enumerations |
seanwilson10 | 0:76fed7dd9235 | 114 | * ========================================================================= */ |
seanwilson10 | 0:76fed7dd9235 | 115 | typedef enum |
seanwilson10 | 0:76fed7dd9235 | 116 | { |
seanwilson10 | 0:76fed7dd9235 | 117 | ADISENSE_SPI_DEVICE_CONFIG_NORMAL = 0, /**< Normal Operating Mode */ |
seanwilson10 | 0:76fed7dd9235 | 118 | ADISENSE_SPI_DEVICE_CONFIG_SLEEP = 3 /**< Low Power Mode */ |
seanwilson10 | 0:76fed7dd9235 | 119 | } ADI_ADISENSE_SPI_Device_Config_Operating_Modes; |
seanwilson10 | 0:76fed7dd9235 | 120 | |
seanwilson10 | 0:76fed7dd9235 | 121 | |
seanwilson10 | 0:76fed7dd9235 | 122 | /* ========================================================================== |
seanwilson10 | 0:76fed7dd9235 | 123 | *! \struct ADI_ADISENSE_SPI_Device_Config_Struct |
seanwilson10 | 0:76fed7dd9235 | 124 | *! \brief Device Configuration Register bit field structure |
seanwilson10 | 0:76fed7dd9235 | 125 | * ========================================================================== */ |
seanwilson10 | 0:76fed7dd9235 | 126 | typedef struct _ADI_ADISENSE_SPI_Device_Config_t { |
seanwilson10 | 0:76fed7dd9235 | 127 | union { |
seanwilson10 | 0:76fed7dd9235 | 128 | struct { |
seanwilson10 | 0:76fed7dd9235 | 129 | uint8_t Operating_Modes : 2; /**< Power Modes */ |
seanwilson10 | 0:76fed7dd9235 | 130 | uint8_t reserved2 : 6; |
seanwilson10 | 0:76fed7dd9235 | 131 | }; |
seanwilson10 | 0:76fed7dd9235 | 132 | uint8_t VALUE8; |
seanwilson10 | 0:76fed7dd9235 | 133 | }; |
seanwilson10 | 0:76fed7dd9235 | 134 | } ADI_ADISENSE_SPI_Device_Config_t; |
seanwilson10 | 0:76fed7dd9235 | 135 | |
seanwilson10 | 0:76fed7dd9235 | 136 | /*@}*/ |
seanwilson10 | 0:76fed7dd9235 | 137 | |
seanwilson10 | 0:76fed7dd9235 | 138 | /** @defgroup Chip_Type Chip Type (Chip_Type) Register |
seanwilson10 | 0:76fed7dd9235 | 139 | * Chip Type (Chip_Type) Register. |
seanwilson10 | 0:76fed7dd9235 | 140 | * @{ |
seanwilson10 | 0:76fed7dd9235 | 141 | */ |
seanwilson10 | 0:76fed7dd9235 | 142 | |
seanwilson10 | 0:76fed7dd9235 | 143 | /* ========================================================================== |
seanwilson10 | 0:76fed7dd9235 | 144 | *! \struct ADI_ADISENSE_SPI_Chip_Type_Struct |
seanwilson10 | 0:76fed7dd9235 | 145 | *! \brief Chip Type Register bit field structure |
seanwilson10 | 0:76fed7dd9235 | 146 | * ========================================================================== */ |
seanwilson10 | 0:76fed7dd9235 | 147 | typedef struct _ADI_ADISENSE_SPI_Chip_Type_t { |
seanwilson10 | 0:76fed7dd9235 | 148 | union { |
seanwilson10 | 0:76fed7dd9235 | 149 | struct { |
seanwilson10 | 0:76fed7dd9235 | 150 | uint8_t Chip_Type : 4; /**< Precision ADC */ |
seanwilson10 | 0:76fed7dd9235 | 151 | uint8_t reserved4 : 4; |
seanwilson10 | 0:76fed7dd9235 | 152 | }; |
seanwilson10 | 0:76fed7dd9235 | 153 | uint8_t VALUE8; |
seanwilson10 | 0:76fed7dd9235 | 154 | }; |
seanwilson10 | 0:76fed7dd9235 | 155 | } ADI_ADISENSE_SPI_Chip_Type_t; |
seanwilson10 | 0:76fed7dd9235 | 156 | |
seanwilson10 | 0:76fed7dd9235 | 157 | /*@}*/ |
seanwilson10 | 0:76fed7dd9235 | 158 | |
seanwilson10 | 0:76fed7dd9235 | 159 | /** @defgroup Product_ID_L Product ID Low (Product_ID_L) Register |
seanwilson10 | 0:76fed7dd9235 | 160 | * Product ID Low (Product_ID_L) Register. |
seanwilson10 | 0:76fed7dd9235 | 161 | * @{ |
seanwilson10 | 0:76fed7dd9235 | 162 | */ |
seanwilson10 | 0:76fed7dd9235 | 163 | |
seanwilson10 | 0:76fed7dd9235 | 164 | /* ========================================================================== |
seanwilson10 | 0:76fed7dd9235 | 165 | *! \struct ADI_ADISENSE_SPI_Product_ID_L_Struct |
seanwilson10 | 0:76fed7dd9235 | 166 | *! \brief Product ID Low Register bit field structure |
seanwilson10 | 0:76fed7dd9235 | 167 | * ========================================================================== */ |
seanwilson10 | 0:76fed7dd9235 | 168 | typedef struct _ADI_ADISENSE_SPI_Product_ID_L_t { |
seanwilson10 | 0:76fed7dd9235 | 169 | union { |
seanwilson10 | 0:76fed7dd9235 | 170 | struct { |
seanwilson10 | 0:76fed7dd9235 | 171 | uint8_t Product_ID_Trim_Bits : 4; /**< These Bits Vary on Die Configured for Multiple Generics */ |
seanwilson10 | 0:76fed7dd9235 | 172 | uint8_t Product_ID_Fixed_Bits : 4; /**< Product_ID_Fixed_Bits[3:0] These Bits are Fixed on Die Configured for Multiple Generics */ |
seanwilson10 | 0:76fed7dd9235 | 173 | }; |
seanwilson10 | 0:76fed7dd9235 | 174 | uint8_t VALUE8; |
seanwilson10 | 0:76fed7dd9235 | 175 | }; |
seanwilson10 | 0:76fed7dd9235 | 176 | } ADI_ADISENSE_SPI_Product_ID_L_t; |
seanwilson10 | 0:76fed7dd9235 | 177 | |
seanwilson10 | 0:76fed7dd9235 | 178 | /*@}*/ |
seanwilson10 | 0:76fed7dd9235 | 179 | |
seanwilson10 | 0:76fed7dd9235 | 180 | /** @defgroup Product_ID_H Product ID High (Product_ID_H) Register |
seanwilson10 | 0:76fed7dd9235 | 181 | * Product ID High (Product_ID_H) Register. |
seanwilson10 | 0:76fed7dd9235 | 182 | * @{ |
seanwilson10 | 0:76fed7dd9235 | 183 | */ |
seanwilson10 | 0:76fed7dd9235 | 184 | |
seanwilson10 | 0:76fed7dd9235 | 185 | /* ========================================================================== |
seanwilson10 | 0:76fed7dd9235 | 186 | *! \struct ADI_ADISENSE_SPI_Product_ID_H_Struct |
seanwilson10 | 0:76fed7dd9235 | 187 | *! \brief Product ID High Register bit field structure |
seanwilson10 | 0:76fed7dd9235 | 188 | * ========================================================================== */ |
seanwilson10 | 0:76fed7dd9235 | 189 | typedef struct _ADI_ADISENSE_SPI_Product_ID_H_t { |
seanwilson10 | 0:76fed7dd9235 | 190 | union { |
seanwilson10 | 0:76fed7dd9235 | 191 | struct { |
seanwilson10 | 0:76fed7dd9235 | 192 | uint8_t Product_ID_Fixed_Bits : 8; /**< Product_ID_Fixed_Bits[11:4] These Bits are Fixed on Die Configured for Multiple Generics */ |
seanwilson10 | 0:76fed7dd9235 | 193 | }; |
seanwilson10 | 0:76fed7dd9235 | 194 | uint8_t VALUE8; |
seanwilson10 | 0:76fed7dd9235 | 195 | }; |
seanwilson10 | 0:76fed7dd9235 | 196 | } ADI_ADISENSE_SPI_Product_ID_H_t; |
seanwilson10 | 0:76fed7dd9235 | 197 | |
seanwilson10 | 0:76fed7dd9235 | 198 | /*@}*/ |
seanwilson10 | 0:76fed7dd9235 | 199 | |
seanwilson10 | 0:76fed7dd9235 | 200 | /** @defgroup Chip_Grade Chip Grade (Chip_Grade) Register |
seanwilson10 | 0:76fed7dd9235 | 201 | * Chip Grade (Chip_Grade) Register. |
seanwilson10 | 0:76fed7dd9235 | 202 | * @{ |
seanwilson10 | 0:76fed7dd9235 | 203 | */ |
seanwilson10 | 0:76fed7dd9235 | 204 | |
seanwilson10 | 0:76fed7dd9235 | 205 | /* ========================================================================== |
seanwilson10 | 0:76fed7dd9235 | 206 | *! \struct ADI_ADISENSE_SPI_Chip_Grade_Struct |
seanwilson10 | 0:76fed7dd9235 | 207 | *! \brief Chip Grade Register bit field structure |
seanwilson10 | 0:76fed7dd9235 | 208 | * ========================================================================== */ |
seanwilson10 | 0:76fed7dd9235 | 209 | typedef struct _ADI_ADISENSE_SPI_Chip_Grade_t { |
seanwilson10 | 0:76fed7dd9235 | 210 | union { |
seanwilson10 | 0:76fed7dd9235 | 211 | struct { |
seanwilson10 | 0:76fed7dd9235 | 212 | uint8_t Device_Revision : 4; /**< This is the Device Hardware Revision */ |
seanwilson10 | 0:76fed7dd9235 | 213 | uint8_t Grade : 4; /**< This is the Device Performance Grade */ |
seanwilson10 | 0:76fed7dd9235 | 214 | }; |
seanwilson10 | 0:76fed7dd9235 | 215 | uint8_t VALUE8; |
seanwilson10 | 0:76fed7dd9235 | 216 | }; |
seanwilson10 | 0:76fed7dd9235 | 217 | } ADI_ADISENSE_SPI_Chip_Grade_t; |
seanwilson10 | 0:76fed7dd9235 | 218 | |
seanwilson10 | 0:76fed7dd9235 | 219 | /*@}*/ |
seanwilson10 | 0:76fed7dd9235 | 220 | |
seanwilson10 | 0:76fed7dd9235 | 221 | /** @defgroup Scratch_Pad Scratch Pad (Scratch_Pad) Register |
seanwilson10 | 0:76fed7dd9235 | 222 | * Scratch Pad (Scratch_Pad) Register. |
seanwilson10 | 0:76fed7dd9235 | 223 | * @{ |
seanwilson10 | 0:76fed7dd9235 | 224 | */ |
seanwilson10 | 0:76fed7dd9235 | 225 | |
seanwilson10 | 0:76fed7dd9235 | 226 | /* ========================================================================== |
seanwilson10 | 0:76fed7dd9235 | 227 | *! \struct ADI_ADISENSE_SPI_Scratch_Pad_Struct |
seanwilson10 | 0:76fed7dd9235 | 228 | *! \brief Scratch Pad Register bit field structure |
seanwilson10 | 0:76fed7dd9235 | 229 | * ========================================================================== */ |
seanwilson10 | 0:76fed7dd9235 | 230 | typedef struct _ADI_ADISENSE_SPI_Scratch_Pad_t { |
seanwilson10 | 0:76fed7dd9235 | 231 | union { |
seanwilson10 | 0:76fed7dd9235 | 232 | struct { |
seanwilson10 | 0:76fed7dd9235 | 233 | uint8_t Scratch_Value : 8; /**< Software Scratchpad */ |
seanwilson10 | 0:76fed7dd9235 | 234 | }; |
seanwilson10 | 0:76fed7dd9235 | 235 | uint8_t VALUE8; |
seanwilson10 | 0:76fed7dd9235 | 236 | }; |
seanwilson10 | 0:76fed7dd9235 | 237 | } ADI_ADISENSE_SPI_Scratch_Pad_t; |
seanwilson10 | 0:76fed7dd9235 | 238 | |
seanwilson10 | 0:76fed7dd9235 | 239 | /*@}*/ |
seanwilson10 | 0:76fed7dd9235 | 240 | |
seanwilson10 | 0:76fed7dd9235 | 241 | /** @defgroup SPI_Revision SPI Revision (SPI_Revision) Register |
seanwilson10 | 0:76fed7dd9235 | 242 | * SPI Revision (SPI_Revision) Register. |
seanwilson10 | 0:76fed7dd9235 | 243 | * @{ |
seanwilson10 | 0:76fed7dd9235 | 244 | */ |
seanwilson10 | 0:76fed7dd9235 | 245 | |
seanwilson10 | 0:76fed7dd9235 | 246 | /* ========================================================================= |
seanwilson10 | 0:76fed7dd9235 | 247 | *! \enum ADI_ADISENSE_SPI_SPI_Revision_Version |
seanwilson10 | 0:76fed7dd9235 | 248 | *! \brief SPI Version (Version) Enumerations |
seanwilson10 | 0:76fed7dd9235 | 249 | * ========================================================================= */ |
seanwilson10 | 0:76fed7dd9235 | 250 | typedef enum |
seanwilson10 | 0:76fed7dd9235 | 251 | { |
seanwilson10 | 0:76fed7dd9235 | 252 | ADISENSE_SPI_SPI_REVISION_REV1_0 = 2 /**< Revision 1.0 */ |
seanwilson10 | 0:76fed7dd9235 | 253 | } ADI_ADISENSE_SPI_SPI_Revision_Version; |
seanwilson10 | 0:76fed7dd9235 | 254 | |
seanwilson10 | 0:76fed7dd9235 | 255 | |
seanwilson10 | 0:76fed7dd9235 | 256 | /* ========================================================================= |
seanwilson10 | 0:76fed7dd9235 | 257 | *! \enum ADI_ADISENSE_SPI_SPI_Revision_SPI_Type |
seanwilson10 | 0:76fed7dd9235 | 258 | *! \brief Always Reads as 0x2 (SPI_Type) Enumerations |
seanwilson10 | 0:76fed7dd9235 | 259 | * ========================================================================= */ |
seanwilson10 | 0:76fed7dd9235 | 260 | typedef enum |
seanwilson10 | 0:76fed7dd9235 | 261 | { |
seanwilson10 | 0:76fed7dd9235 | 262 | ADISENSE_SPI_SPI_REVISION_ADI_SPI = 0, /**< */ |
seanwilson10 | 0:76fed7dd9235 | 263 | ADISENSE_SPI_SPI_REVISION_LPT_SPI = 2 /**< */ |
seanwilson10 | 0:76fed7dd9235 | 264 | } ADI_ADISENSE_SPI_SPI_Revision_SPI_Type; |
seanwilson10 | 0:76fed7dd9235 | 265 | |
seanwilson10 | 0:76fed7dd9235 | 266 | |
seanwilson10 | 0:76fed7dd9235 | 267 | /* ========================================================================== |
seanwilson10 | 0:76fed7dd9235 | 268 | *! \struct ADI_ADISENSE_SPI_SPI_Revision_Struct |
seanwilson10 | 0:76fed7dd9235 | 269 | *! \brief SPI Revision Register bit field structure |
seanwilson10 | 0:76fed7dd9235 | 270 | * ========================================================================== */ |
seanwilson10 | 0:76fed7dd9235 | 271 | typedef struct _ADI_ADISENSE_SPI_SPI_Revision_t { |
seanwilson10 | 0:76fed7dd9235 | 272 | union { |
seanwilson10 | 0:76fed7dd9235 | 273 | struct { |
seanwilson10 | 0:76fed7dd9235 | 274 | uint8_t Version : 6; /**< SPI Version */ |
seanwilson10 | 0:76fed7dd9235 | 275 | uint8_t SPI_Type : 2; /**< Always Reads as 0x2 */ |
seanwilson10 | 0:76fed7dd9235 | 276 | }; |
seanwilson10 | 0:76fed7dd9235 | 277 | uint8_t VALUE8; |
seanwilson10 | 0:76fed7dd9235 | 278 | }; |
seanwilson10 | 0:76fed7dd9235 | 279 | } ADI_ADISENSE_SPI_SPI_Revision_t; |
seanwilson10 | 0:76fed7dd9235 | 280 | |
seanwilson10 | 0:76fed7dd9235 | 281 | /*@}*/ |
seanwilson10 | 0:76fed7dd9235 | 282 | |
seanwilson10 | 0:76fed7dd9235 | 283 | /** @defgroup Vendor_L Vendor ID Low (Vendor_L) Register |
seanwilson10 | 0:76fed7dd9235 | 284 | * Vendor ID Low (Vendor_L) Register. |
seanwilson10 | 0:76fed7dd9235 | 285 | * @{ |
seanwilson10 | 0:76fed7dd9235 | 286 | */ |
seanwilson10 | 0:76fed7dd9235 | 287 | |
seanwilson10 | 0:76fed7dd9235 | 288 | /* ========================================================================== |
seanwilson10 | 0:76fed7dd9235 | 289 | *! \struct ADI_ADISENSE_SPI_Vendor_L_Struct |
seanwilson10 | 0:76fed7dd9235 | 290 | *! \brief Vendor ID Low Register bit field structure |
seanwilson10 | 0:76fed7dd9235 | 291 | * ========================================================================== */ |
seanwilson10 | 0:76fed7dd9235 | 292 | typedef struct _ADI_ADISENSE_SPI_Vendor_L_t { |
seanwilson10 | 0:76fed7dd9235 | 293 | union { |
seanwilson10 | 0:76fed7dd9235 | 294 | struct { |
seanwilson10 | 0:76fed7dd9235 | 295 | uint8_t VID : 8; /**< VID[7:0] Analog Devices Vendor ID */ |
seanwilson10 | 0:76fed7dd9235 | 296 | }; |
seanwilson10 | 0:76fed7dd9235 | 297 | uint8_t VALUE8; |
seanwilson10 | 0:76fed7dd9235 | 298 | }; |
seanwilson10 | 0:76fed7dd9235 | 299 | } ADI_ADISENSE_SPI_Vendor_L_t; |
seanwilson10 | 0:76fed7dd9235 | 300 | |
seanwilson10 | 0:76fed7dd9235 | 301 | /*@}*/ |
seanwilson10 | 0:76fed7dd9235 | 302 | |
seanwilson10 | 0:76fed7dd9235 | 303 | /** @defgroup Vendor_H Vendor ID High (Vendor_H) Register |
seanwilson10 | 0:76fed7dd9235 | 304 | * Vendor ID High (Vendor_H) Register. |
seanwilson10 | 0:76fed7dd9235 | 305 | * @{ |
seanwilson10 | 0:76fed7dd9235 | 306 | */ |
seanwilson10 | 0:76fed7dd9235 | 307 | |
seanwilson10 | 0:76fed7dd9235 | 308 | /* ========================================================================== |
seanwilson10 | 0:76fed7dd9235 | 309 | *! \struct ADI_ADISENSE_SPI_Vendor_H_Struct |
seanwilson10 | 0:76fed7dd9235 | 310 | *! \brief Vendor ID High Register bit field structure |
seanwilson10 | 0:76fed7dd9235 | 311 | * ========================================================================== */ |
seanwilson10 | 0:76fed7dd9235 | 312 | typedef struct _ADI_ADISENSE_SPI_Vendor_H_t { |
seanwilson10 | 0:76fed7dd9235 | 313 | union { |
seanwilson10 | 0:76fed7dd9235 | 314 | struct { |
seanwilson10 | 0:76fed7dd9235 | 315 | uint8_t VID : 8; /**< VID[15:8] Analog Devices Vendor ID */ |
seanwilson10 | 0:76fed7dd9235 | 316 | }; |
seanwilson10 | 0:76fed7dd9235 | 317 | uint8_t VALUE8; |
seanwilson10 | 0:76fed7dd9235 | 318 | }; |
seanwilson10 | 0:76fed7dd9235 | 319 | } ADI_ADISENSE_SPI_Vendor_H_t; |
seanwilson10 | 0:76fed7dd9235 | 320 | |
seanwilson10 | 0:76fed7dd9235 | 321 | /*@}*/ |
seanwilson10 | 0:76fed7dd9235 | 322 | |
seanwilson10 | 0:76fed7dd9235 | 323 | /** @defgroup Stream_Mode Stream Mode (Stream_Mode) Register |
seanwilson10 | 0:76fed7dd9235 | 324 | * Stream Mode (Stream_Mode) Register. |
seanwilson10 | 0:76fed7dd9235 | 325 | * @{ |
seanwilson10 | 0:76fed7dd9235 | 326 | */ |
seanwilson10 | 0:76fed7dd9235 | 327 | |
seanwilson10 | 0:76fed7dd9235 | 328 | /* ========================================================================== |
seanwilson10 | 0:76fed7dd9235 | 329 | *! \struct ADI_ADISENSE_SPI_Stream_Mode_Struct |
seanwilson10 | 0:76fed7dd9235 | 330 | *! \brief Stream Mode Register bit field structure |
seanwilson10 | 0:76fed7dd9235 | 331 | * ========================================================================== */ |
seanwilson10 | 0:76fed7dd9235 | 332 | typedef struct _ADI_ADISENSE_SPI_Stream_Mode_t { |
seanwilson10 | 0:76fed7dd9235 | 333 | union { |
seanwilson10 | 0:76fed7dd9235 | 334 | struct { |
seanwilson10 | 0:76fed7dd9235 | 335 | uint8_t Loop_Count : 8; /**< Sets the Data Byte Count Before Looping to Start Address */ |
seanwilson10 | 0:76fed7dd9235 | 336 | }; |
seanwilson10 | 0:76fed7dd9235 | 337 | uint8_t VALUE8; |
seanwilson10 | 0:76fed7dd9235 | 338 | }; |
seanwilson10 | 0:76fed7dd9235 | 339 | } ADI_ADISENSE_SPI_Stream_Mode_t; |
seanwilson10 | 0:76fed7dd9235 | 340 | |
seanwilson10 | 0:76fed7dd9235 | 341 | /*@}*/ |
seanwilson10 | 0:76fed7dd9235 | 342 | |
seanwilson10 | 0:76fed7dd9235 | 343 | /** @defgroup Transfer_Config Transfer Config (Transfer_Config) Register |
seanwilson10 | 0:76fed7dd9235 | 344 | * Transfer Config (Transfer_Config) Register. |
seanwilson10 | 0:76fed7dd9235 | 345 | * @{ |
seanwilson10 | 0:76fed7dd9235 | 346 | */ |
seanwilson10 | 0:76fed7dd9235 | 347 | |
seanwilson10 | 0:76fed7dd9235 | 348 | /* ========================================================================= |
seanwilson10 | 0:76fed7dd9235 | 349 | *! \enum ADI_ADISENSE_SPI_Transfer_Config_Stream_Mode |
seanwilson10 | 0:76fed7dd9235 | 350 | *! \brief When Streaming, Controls Master-Slave Transfer (Stream_Mode) Enumerations |
seanwilson10 | 0:76fed7dd9235 | 351 | * ========================================================================= */ |
seanwilson10 | 0:76fed7dd9235 | 352 | typedef enum |
seanwilson10 | 0:76fed7dd9235 | 353 | { |
seanwilson10 | 0:76fed7dd9235 | 354 | ADISENSE_SPI_TRANSFER_CONFIG_UPDATE_ON_WRITE = 0, /**< Transfers after each byte/mulit-byte register */ |
seanwilson10 | 0:76fed7dd9235 | 355 | ADISENSE_SPI_TRANSFER_CONFIG_UPDATE_ON_ADDRESS_LOOP = 1 /**< Transfers when address loops */ |
seanwilson10 | 0:76fed7dd9235 | 356 | } ADI_ADISENSE_SPI_Transfer_Config_Stream_Mode; |
seanwilson10 | 0:76fed7dd9235 | 357 | |
seanwilson10 | 0:76fed7dd9235 | 358 | |
seanwilson10 | 0:76fed7dd9235 | 359 | /* ========================================================================== |
seanwilson10 | 0:76fed7dd9235 | 360 | *! \struct ADI_ADISENSE_SPI_Transfer_Config_Struct |
seanwilson10 | 0:76fed7dd9235 | 361 | *! \brief Transfer Config Register bit field structure |
seanwilson10 | 0:76fed7dd9235 | 362 | * ========================================================================== */ |
seanwilson10 | 0:76fed7dd9235 | 363 | typedef struct _ADI_ADISENSE_SPI_Transfer_Config_t { |
seanwilson10 | 0:76fed7dd9235 | 364 | union { |
seanwilson10 | 0:76fed7dd9235 | 365 | struct { |
seanwilson10 | 0:76fed7dd9235 | 366 | uint8_t reserved0 : 1; |
seanwilson10 | 0:76fed7dd9235 | 367 | uint8_t Stream_Mode : 1; /**< When Streaming, Controls Master-Slave Transfer */ |
seanwilson10 | 0:76fed7dd9235 | 368 | uint8_t reserved2 : 6; |
seanwilson10 | 0:76fed7dd9235 | 369 | }; |
seanwilson10 | 0:76fed7dd9235 | 370 | uint8_t VALUE8; |
seanwilson10 | 0:76fed7dd9235 | 371 | }; |
seanwilson10 | 0:76fed7dd9235 | 372 | } ADI_ADISENSE_SPI_Transfer_Config_t; |
seanwilson10 | 0:76fed7dd9235 | 373 | |
seanwilson10 | 0:76fed7dd9235 | 374 | /*@}*/ |
seanwilson10 | 0:76fed7dd9235 | 375 | |
seanwilson10 | 0:76fed7dd9235 | 376 | /** @defgroup Interface_Config_C Interface Configuration C (Interface_Config_C) Register |
seanwilson10 | 0:76fed7dd9235 | 377 | * Interface Configuration C (Interface_Config_C) Register. |
seanwilson10 | 0:76fed7dd9235 | 378 | * @{ |
seanwilson10 | 0:76fed7dd9235 | 379 | */ |
seanwilson10 | 0:76fed7dd9235 | 380 | |
seanwilson10 | 0:76fed7dd9235 | 381 | /* ========================================================================= |
seanwilson10 | 0:76fed7dd9235 | 382 | *! \enum ADI_ADISENSE_SPI_Interface_Config_C_Strict_Register_Access |
seanwilson10 | 0:76fed7dd9235 | 383 | *! \brief Multi-byte Registers Must Be Read/Written in Full (Strict_Register_Access) Enumerations |
seanwilson10 | 0:76fed7dd9235 | 384 | * ========================================================================= */ |
seanwilson10 | 0:76fed7dd9235 | 385 | typedef enum |
seanwilson10 | 0:76fed7dd9235 | 386 | { |
seanwilson10 | 0:76fed7dd9235 | 387 | ADISENSE_SPI_INTERFACE_CONFIG_C_NORMAL_ACCESS = 0, /**< Normal mode, no access restrictions */ |
seanwilson10 | 0:76fed7dd9235 | 388 | ADISENSE_SPI_INTERFACE_CONFIG_C_STRICT_ACCESS = 1 /**< Strict mode, multi-byte registers require all bytes read/written */ |
seanwilson10 | 0:76fed7dd9235 | 389 | } ADI_ADISENSE_SPI_Interface_Config_C_Strict_Register_Access; |
seanwilson10 | 0:76fed7dd9235 | 390 | |
seanwilson10 | 0:76fed7dd9235 | 391 | |
seanwilson10 | 0:76fed7dd9235 | 392 | /* ========================================================================= |
seanwilson10 | 0:76fed7dd9235 | 393 | *! \enum ADI_ADISENSE_SPI_Interface_Config_C_CRC_Enable |
seanwilson10 | 0:76fed7dd9235 | 394 | *! \brief CRC Enable (CRC_Enable) Enumerations |
seanwilson10 | 0:76fed7dd9235 | 395 | * ========================================================================= */ |
seanwilson10 | 0:76fed7dd9235 | 396 | typedef enum |
seanwilson10 | 0:76fed7dd9235 | 397 | { |
seanwilson10 | 0:76fed7dd9235 | 398 | ADISENSE_SPI_INTERFACE_CONFIG_C_DISABLED = 0, /**< CRC Disabled */ |
seanwilson10 | 0:76fed7dd9235 | 399 | ADISENSE_SPI_INTERFACE_CONFIG_C_ENABLED = 1 /**< CRC Enabled */ |
seanwilson10 | 0:76fed7dd9235 | 400 | } ADI_ADISENSE_SPI_Interface_Config_C_CRC_Enable; |
seanwilson10 | 0:76fed7dd9235 | 401 | |
seanwilson10 | 0:76fed7dd9235 | 402 | |
seanwilson10 | 0:76fed7dd9235 | 403 | /* ========================================================================== |
seanwilson10 | 0:76fed7dd9235 | 404 | *! \struct ADI_ADISENSE_SPI_Interface_Config_C_Struct |
seanwilson10 | 0:76fed7dd9235 | 405 | *! \brief Interface Configuration C Register bit field structure |
seanwilson10 | 0:76fed7dd9235 | 406 | * ========================================================================== */ |
seanwilson10 | 0:76fed7dd9235 | 407 | typedef struct _ADI_ADISENSE_SPI_Interface_Config_C_t { |
seanwilson10 | 0:76fed7dd9235 | 408 | union { |
seanwilson10 | 0:76fed7dd9235 | 409 | struct { |
seanwilson10 | 0:76fed7dd9235 | 410 | uint8_t CRC_EnableB : 2; /**< Inverted CRC Enable */ |
seanwilson10 | 0:76fed7dd9235 | 411 | uint8_t reserved2 : 3; |
seanwilson10 | 0:76fed7dd9235 | 412 | uint8_t Strict_Register_Access : 1; /**< Multi-byte Registers Must Be Read/Written in Full */ |
seanwilson10 | 0:76fed7dd9235 | 413 | uint8_t CRC_Enable : 2; /**< CRC Enable */ |
seanwilson10 | 0:76fed7dd9235 | 414 | }; |
seanwilson10 | 0:76fed7dd9235 | 415 | uint8_t VALUE8; |
seanwilson10 | 0:76fed7dd9235 | 416 | }; |
seanwilson10 | 0:76fed7dd9235 | 417 | } ADI_ADISENSE_SPI_Interface_Config_C_t; |
seanwilson10 | 0:76fed7dd9235 | 418 | |
seanwilson10 | 0:76fed7dd9235 | 419 | /*@}*/ |
seanwilson10 | 0:76fed7dd9235 | 420 | |
seanwilson10 | 0:76fed7dd9235 | 421 | /** @defgroup Interface_Status_A Interface Status A (Interface_Status_A) Register |
seanwilson10 | 0:76fed7dd9235 | 422 | * Interface Status A (Interface_Status_A) Register. |
seanwilson10 | 0:76fed7dd9235 | 423 | * @{ |
seanwilson10 | 0:76fed7dd9235 | 424 | */ |
seanwilson10 | 0:76fed7dd9235 | 425 | |
seanwilson10 | 0:76fed7dd9235 | 426 | /* ========================================================================== |
seanwilson10 | 0:76fed7dd9235 | 427 | *! \struct ADI_ADISENSE_SPI_Interface_Status_A_Struct |
seanwilson10 | 0:76fed7dd9235 | 428 | *! \brief Interface Status A Register bit field structure |
seanwilson10 | 0:76fed7dd9235 | 429 | * ========================================================================== */ |
seanwilson10 | 0:76fed7dd9235 | 430 | typedef struct _ADI_ADISENSE_SPI_Interface_Status_A_t { |
seanwilson10 | 0:76fed7dd9235 | 431 | union { |
seanwilson10 | 0:76fed7dd9235 | 432 | struct { |
seanwilson10 | 0:76fed7dd9235 | 433 | uint8_t Address_Invalid_Error : 1; /**< Attempt to Read/Write Non-existent Register Address */ |
seanwilson10 | 0:76fed7dd9235 | 434 | uint8_t Register_Partial_Access_Error : 1; /**< Set When Fewer Than Expected Number of Bytes Read/Written */ |
seanwilson10 | 0:76fed7dd9235 | 435 | uint8_t Wr_To_Rd_Only_Reg_Error : 1; /**< Write to Read-Only Register Attempted */ |
seanwilson10 | 0:76fed7dd9235 | 436 | uint8_t CRC_Error : 1; /**< Invalid/No CRC Received */ |
seanwilson10 | 0:76fed7dd9235 | 437 | uint8_t Clock_Count_Error : 1; /**< Incorrect Number of Clocks Detected in a Transaction */ |
seanwilson10 | 0:76fed7dd9235 | 438 | uint8_t reserved5 : 2; |
seanwilson10 | 0:76fed7dd9235 | 439 | uint8_t Not_Ready_Error : 1; /**< Device Not Ready for Transaction */ |
seanwilson10 | 0:76fed7dd9235 | 440 | }; |
seanwilson10 | 0:76fed7dd9235 | 441 | uint8_t VALUE8; |
seanwilson10 | 0:76fed7dd9235 | 442 | }; |
seanwilson10 | 0:76fed7dd9235 | 443 | } ADI_ADISENSE_SPI_Interface_Status_A_t; |
seanwilson10 | 0:76fed7dd9235 | 444 | |
seanwilson10 | 0:76fed7dd9235 | 445 | /*@}*/ |
seanwilson10 | 0:76fed7dd9235 | 446 | |
seanwilson10 | 0:76fed7dd9235 | 447 | /** @defgroup Command Special Command (Command) Register |
seanwilson10 | 0:76fed7dd9235 | 448 | * Special Command (Command) Register. |
seanwilson10 | 0:76fed7dd9235 | 449 | * @{ |
seanwilson10 | 0:76fed7dd9235 | 450 | */ |
seanwilson10 | 0:76fed7dd9235 | 451 | |
seanwilson10 | 0:76fed7dd9235 | 452 | /* ========================================================================= |
seanwilson10 | 0:76fed7dd9235 | 453 | *! \enum ADI_ADISENSE_CORE_Command_Special_Command |
seanwilson10 | 0:76fed7dd9235 | 454 | *! \brief Special Command (Special_Command) Enumerations |
seanwilson10 | 0:76fed7dd9235 | 455 | * ========================================================================= */ |
seanwilson10 | 0:76fed7dd9235 | 456 | typedef enum |
seanwilson10 | 0:76fed7dd9235 | 457 | { |
seanwilson10 | 0:76fed7dd9235 | 458 | ADISENSE_CORE_COMMAND_NOP = 0, /**< No Command */ |
seanwilson10 | 0:76fed7dd9235 | 459 | ADISENSE_CORE_COMMAND_CONVERT = 1, /**< Start ADC Conversions */ |
seanwilson10 | 0:76fed7dd9235 | 460 | ADISENSE_CORE_COMMAND_CONVERT_WITH_RAW = 2, /**< Start Conversions with Added RAW ADC Data */ |
seanwilson10 | 0:76fed7dd9235 | 461 | ADISENSE_CORE_COMMAND_RUN_DIAGNOSTICS = 3, /**< Initiate a Diagnostics Cycle */ |
seanwilson10 | 0:76fed7dd9235 | 462 | ADISENSE_CORE_COMMAND_SELF_CALIBRATION = 4, /**< Initiate a Self-Calibration Cycle */ |
seanwilson10 | 0:76fed7dd9235 | 463 | ADISENSE_CORE_COMMAND_LOAD_CONFIG = 5, /**< Load Registers with Configuration from FLASH */ |
seanwilson10 | 0:76fed7dd9235 | 464 | ADISENSE_CORE_COMMAND_SAVE_CONFIG = 6, /**< Store Current Register Configuration to FLASH */ |
seanwilson10 | 0:76fed7dd9235 | 465 | ADISENSE_CORE_COMMAND_LATCH_CONFIG = 7, /**< Latch Configuration. */ |
seanwilson10 | 0:76fed7dd9235 | 466 | ADISENSE_CORE_COMMAND_LOAD_LUT = 8, /**< Load LUT from FLASH */ |
seanwilson10 | 0:76fed7dd9235 | 467 | ADISENSE_CORE_COMMAND_SAVE_LUT2 = 9, /**< Save LUT to FLASH */ |
seanwilson10 | 0:76fed7dd9235 | 468 | ADISENSE_CORE_COMMAND_SYSTEM_CHECK = 10 /**< Full Suite of Measurement Diagnostics */ |
seanwilson10 | 0:76fed7dd9235 | 469 | } ADI_ADISENSE_CORE_Command_Special_Command; |
seanwilson10 | 0:76fed7dd9235 | 470 | |
seanwilson10 | 0:76fed7dd9235 | 471 | |
seanwilson10 | 0:76fed7dd9235 | 472 | /* ========================================================================== |
seanwilson10 | 0:76fed7dd9235 | 473 | *! \struct ADI_ADISENSE_CORE_Command_Struct |
seanwilson10 | 0:76fed7dd9235 | 474 | *! \brief Special Command Register bit field structure |
seanwilson10 | 0:76fed7dd9235 | 475 | * ========================================================================== */ |
seanwilson10 | 0:76fed7dd9235 | 476 | typedef struct _ADI_ADISENSE_CORE_Command_t { |
seanwilson10 | 0:76fed7dd9235 | 477 | union { |
seanwilson10 | 0:76fed7dd9235 | 478 | struct { |
seanwilson10 | 0:76fed7dd9235 | 479 | uint8_t Special_Command : 8; /**< Special Command */ |
seanwilson10 | 0:76fed7dd9235 | 480 | }; |
seanwilson10 | 0:76fed7dd9235 | 481 | uint8_t VALUE8; |
seanwilson10 | 0:76fed7dd9235 | 482 | }; |
seanwilson10 | 0:76fed7dd9235 | 483 | } ADI_ADISENSE_CORE_Command_t; |
seanwilson10 | 0:76fed7dd9235 | 484 | |
seanwilson10 | 0:76fed7dd9235 | 485 | /*@}*/ |
seanwilson10 | 0:76fed7dd9235 | 486 | |
seanwilson10 | 0:76fed7dd9235 | 487 | /** @defgroup Mode Operating Mode and DRDY Control (Mode) Register |
seanwilson10 | 0:76fed7dd9235 | 488 | * Operating Mode and DRDY Control (Mode) Register. |
seanwilson10 | 0:76fed7dd9235 | 489 | * @{ |
seanwilson10 | 0:76fed7dd9235 | 490 | */ |
seanwilson10 | 0:76fed7dd9235 | 491 | |
seanwilson10 | 0:76fed7dd9235 | 492 | /* ========================================================================= |
seanwilson10 | 0:76fed7dd9235 | 493 | *! \enum ADI_ADISENSE_CORE_Mode_Conversion_Mode |
seanwilson10 | 0:76fed7dd9235 | 494 | *! \brief Conversion Mode (Conversion_Mode) Enumerations |
seanwilson10 | 0:76fed7dd9235 | 495 | * ========================================================================= */ |
seanwilson10 | 0:76fed7dd9235 | 496 | typedef enum |
seanwilson10 | 0:76fed7dd9235 | 497 | { |
seanwilson10 | 0:76fed7dd9235 | 498 | ADISENSE_CORE_MODE_SINGLECYCLE = 0, /**< Single Cycle */ |
seanwilson10 | 0:76fed7dd9235 | 499 | ADISENSE_CORE_MODE_MULTICYCLE = 1, /**< Multi Cycle */ |
seanwilson10 | 0:76fed7dd9235 | 500 | ADISENSE_CORE_MODE_CONTINUOUS = 2, /**< Continuous Conversion */ |
seanwilson10 | 0:76fed7dd9235 | 501 | ADISENSE_CORE_MODE_MODE3 = 3 /**< Undefined */ |
seanwilson10 | 0:76fed7dd9235 | 502 | } ADI_ADISENSE_CORE_Mode_Conversion_Mode; |
seanwilson10 | 0:76fed7dd9235 | 503 | |
seanwilson10 | 0:76fed7dd9235 | 504 | |
seanwilson10 | 0:76fed7dd9235 | 505 | /* ========================================================================= |
seanwilson10 | 0:76fed7dd9235 | 506 | *! \enum ADI_ADISENSE_CORE_Mode_Drdy_Mode |
seanwilson10 | 0:76fed7dd9235 | 507 | *! \brief Indicates Behavior of DRDY with Respect to FIFO State (Drdy_Mode) Enumerations |
seanwilson10 | 0:76fed7dd9235 | 508 | * ========================================================================= */ |
seanwilson10 | 0:76fed7dd9235 | 509 | typedef enum |
seanwilson10 | 0:76fed7dd9235 | 510 | { |
seanwilson10 | 0:76fed7dd9235 | 511 | ADISENSE_CORE_MODE_DRDY_PER_CONVERSION = 0, /**< Data Ready Per Conversion */ |
seanwilson10 | 0:76fed7dd9235 | 512 | ADISENSE_CORE_MODE_DRDY_PER_CYCLE = 1, /**< Data Ready Per Cycle */ |
seanwilson10 | 0:76fed7dd9235 | 513 | ADISENSE_CORE_MODE_DRDY_PER_FIFO_FILL = 2, /**< Data Ready Per FIFO Fill */ |
seanwilson10 | 0:76fed7dd9235 | 514 | ADISENSE_CORE_MODE_DRDY_MODE3 = 3 /**< Undefined */ |
seanwilson10 | 0:76fed7dd9235 | 515 | } ADI_ADISENSE_CORE_Mode_Drdy_Mode; |
seanwilson10 | 0:76fed7dd9235 | 516 | |
seanwilson10 | 0:76fed7dd9235 | 517 | |
seanwilson10 | 0:76fed7dd9235 | 518 | /* ========================================================================== |
seanwilson10 | 0:76fed7dd9235 | 519 | *! \struct ADI_ADISENSE_CORE_Mode_Struct |
seanwilson10 | 0:76fed7dd9235 | 520 | *! \brief Operating Mode and DRDY Control Register bit field structure |
seanwilson10 | 0:76fed7dd9235 | 521 | * ========================================================================== */ |
seanwilson10 | 0:76fed7dd9235 | 522 | typedef struct _ADI_ADISENSE_CORE_Mode_t { |
seanwilson10 | 0:76fed7dd9235 | 523 | union { |
seanwilson10 | 0:76fed7dd9235 | 524 | struct { |
seanwilson10 | 0:76fed7dd9235 | 525 | uint8_t Conversion_Mode : 2; /**< Conversion Mode */ |
seanwilson10 | 0:76fed7dd9235 | 526 | uint8_t Drdy_Mode : 2; /**< Indicates Behavior of DRDY with Respect to FIFO State */ |
seanwilson10 | 0:76fed7dd9235 | 527 | uint8_t reserved4 : 4; |
seanwilson10 | 0:76fed7dd9235 | 528 | }; |
seanwilson10 | 0:76fed7dd9235 | 529 | uint8_t VALUE8; |
seanwilson10 | 0:76fed7dd9235 | 530 | }; |
seanwilson10 | 0:76fed7dd9235 | 531 | } ADI_ADISENSE_CORE_Mode_t; |
seanwilson10 | 0:76fed7dd9235 | 532 | |
seanwilson10 | 0:76fed7dd9235 | 533 | /*@}*/ |
seanwilson10 | 0:76fed7dd9235 | 534 | |
seanwilson10 | 0:76fed7dd9235 | 535 | /** @defgroup Power_Config General Configuration (Power_Config) Register |
seanwilson10 | 0:76fed7dd9235 | 536 | * General Configuration (Power_Config) Register. |
seanwilson10 | 0:76fed7dd9235 | 537 | * @{ |
seanwilson10 | 0:76fed7dd9235 | 538 | */ |
seanwilson10 | 0:76fed7dd9235 | 539 | |
seanwilson10 | 0:76fed7dd9235 | 540 | /* ========================================================================= |
seanwilson10 | 0:76fed7dd9235 | 541 | *! \enum ADI_ADISENSE_CORE_Power_Config_Power_Mode_ADC |
seanwilson10 | 0:76fed7dd9235 | 542 | *! \brief ADC Power Mode (Power_Mode_ADC) Enumerations |
seanwilson10 | 0:76fed7dd9235 | 543 | * ========================================================================= */ |
seanwilson10 | 0:76fed7dd9235 | 544 | typedef enum |
seanwilson10 | 0:76fed7dd9235 | 545 | { |
seanwilson10 | 0:76fed7dd9235 | 546 | ADISENSE_CORE_POWER_CONFIG_ADC_LOW_POWER = 0, /**< ADC Low Power Mode */ |
seanwilson10 | 0:76fed7dd9235 | 547 | ADISENSE_CORE_POWER_CONFIG_ADC_MID_POWER = 1, /**< ADC Mid Power Mode */ |
seanwilson10 | 0:76fed7dd9235 | 548 | ADISENSE_CORE_POWER_CONFIG_ADC_FULL_POWER = 2, /**< ADC Full Power Mode */ |
seanwilson10 | 0:76fed7dd9235 | 549 | ADISENSE_CORE_POWER_CONFIG_ADC_FULL_POWER2 = 3 /**< ADC Full Power Mode2 */ |
seanwilson10 | 0:76fed7dd9235 | 550 | } ADI_ADISENSE_CORE_Power_Config_Power_Mode_ADC; |
seanwilson10 | 0:76fed7dd9235 | 551 | |
seanwilson10 | 0:76fed7dd9235 | 552 | |
seanwilson10 | 0:76fed7dd9235 | 553 | /* ========================================================================== |
seanwilson10 | 0:76fed7dd9235 | 554 | *! \struct ADI_ADISENSE_CORE_Power_Config_Struct |
seanwilson10 | 0:76fed7dd9235 | 555 | *! \brief General Configuration Register bit field structure |
seanwilson10 | 0:76fed7dd9235 | 556 | * ========================================================================== */ |
seanwilson10 | 0:76fed7dd9235 | 557 | typedef struct _ADI_ADISENSE_CORE_Power_Config_t { |
seanwilson10 | 0:76fed7dd9235 | 558 | union { |
seanwilson10 | 0:76fed7dd9235 | 559 | struct { |
seanwilson10 | 0:76fed7dd9235 | 560 | uint8_t Power_Mode_ADC : 2; /**< ADC Power Mode */ |
seanwilson10 | 0:76fed7dd9235 | 561 | uint8_t Power_Mode_MCU : 2; /**< MCU Power Mode */ |
seanwilson10 | 0:76fed7dd9235 | 562 | uint8_t Stdby_En : 1; /**< Standby */ |
seanwilson10 | 0:76fed7dd9235 | 563 | uint8_t reserved5 : 3; |
seanwilson10 | 0:76fed7dd9235 | 564 | }; |
seanwilson10 | 0:76fed7dd9235 | 565 | uint8_t VALUE8; |
seanwilson10 | 0:76fed7dd9235 | 566 | }; |
seanwilson10 | 0:76fed7dd9235 | 567 | } ADI_ADISENSE_CORE_Power_Config_t; |
seanwilson10 | 0:76fed7dd9235 | 568 | |
seanwilson10 | 0:76fed7dd9235 | 569 | /*@}*/ |
seanwilson10 | 0:76fed7dd9235 | 570 | |
seanwilson10 | 0:76fed7dd9235 | 571 | /** @defgroup Cycle_Control Measurement Cycle (Cycle_Control) Register |
seanwilson10 | 0:76fed7dd9235 | 572 | * Measurement Cycle (Cycle_Control) Register. |
seanwilson10 | 0:76fed7dd9235 | 573 | * @{ |
seanwilson10 | 0:76fed7dd9235 | 574 | */ |
seanwilson10 | 0:76fed7dd9235 | 575 | |
seanwilson10 | 0:76fed7dd9235 | 576 | /* ========================================================================= |
seanwilson10 | 0:76fed7dd9235 | 577 | *! \enum ADI_ADISENSE_CORE_Cycle_Control_Cycle_Time_Units |
seanwilson10 | 0:76fed7dd9235 | 578 | *! \brief Units for Cycle Time (Cycle_Time_Units) Enumerations |
seanwilson10 | 0:76fed7dd9235 | 579 | * ========================================================================= */ |
seanwilson10 | 0:76fed7dd9235 | 580 | typedef enum |
seanwilson10 | 0:76fed7dd9235 | 581 | { |
seanwilson10 | 0:76fed7dd9235 | 582 | ADISENSE_CORE_CYCLE_CONTROL_MICROSECONDS = 0, /**< Micro-Seconds */ |
seanwilson10 | 0:76fed7dd9235 | 583 | ADISENSE_CORE_CYCLE_CONTROL_MILLISECONDS = 1, /**< Milli-Seconds */ |
seanwilson10 | 0:76fed7dd9235 | 584 | ADISENSE_CORE_CYCLE_CONTROL_SECONDS = 2, /**< Seconds */ |
seanwilson10 | 0:76fed7dd9235 | 585 | ADISENSE_CORE_CYCLE_CONTROL_UNDEFINED = 3 /**< Undefined */ |
seanwilson10 | 0:76fed7dd9235 | 586 | } ADI_ADISENSE_CORE_Cycle_Control_Cycle_Time_Units; |
seanwilson10 | 0:76fed7dd9235 | 587 | |
seanwilson10 | 0:76fed7dd9235 | 588 | |
seanwilson10 | 0:76fed7dd9235 | 589 | /* ========================================================================== |
seanwilson10 | 0:76fed7dd9235 | 590 | *! \struct ADI_ADISENSE_CORE_Cycle_Control_Struct |
seanwilson10 | 0:76fed7dd9235 | 591 | *! \brief Measurement Cycle Register bit field structure |
seanwilson10 | 0:76fed7dd9235 | 592 | * ========================================================================== */ |
seanwilson10 | 0:76fed7dd9235 | 593 | typedef struct _ADI_ADISENSE_CORE_Cycle_Control_t { |
seanwilson10 | 0:76fed7dd9235 | 594 | union { |
seanwilson10 | 0:76fed7dd9235 | 595 | struct { |
seanwilson10 | 0:76fed7dd9235 | 596 | uint16_t Cycle_Time : 12; /**< Duration of a Full Measurement Cycle */ |
seanwilson10 | 0:76fed7dd9235 | 597 | uint16_t reserved12 : 2; |
seanwilson10 | 0:76fed7dd9235 | 598 | uint16_t Cycle_Time_Units : 2; /**< Units for Cycle Time */ |
seanwilson10 | 0:76fed7dd9235 | 599 | }; |
seanwilson10 | 0:76fed7dd9235 | 600 | uint16_t VALUE16; |
seanwilson10 | 0:76fed7dd9235 | 601 | }; |
seanwilson10 | 0:76fed7dd9235 | 602 | } ADI_ADISENSE_CORE_Cycle_Control_t; |
seanwilson10 | 0:76fed7dd9235 | 603 | |
seanwilson10 | 0:76fed7dd9235 | 604 | /*@}*/ |
seanwilson10 | 0:76fed7dd9235 | 605 | |
seanwilson10 | 0:76fed7dd9235 | 606 | /** @defgroup Fifo_Num_Cycles Number of Measurement Cycles to Store in FIFO (Fifo_Num_Cycles) Register |
seanwilson10 | 0:76fed7dd9235 | 607 | * Number of Measurement Cycles to Store in FIFO (Fifo_Num_Cycles) Register. |
seanwilson10 | 0:76fed7dd9235 | 608 | * @{ |
seanwilson10 | 0:76fed7dd9235 | 609 | */ |
seanwilson10 | 0:76fed7dd9235 | 610 | |
seanwilson10 | 0:76fed7dd9235 | 611 | /* ========================================================================== |
seanwilson10 | 0:76fed7dd9235 | 612 | *! \struct ADI_ADISENSE_CORE_Fifo_Num_Cycles_Struct |
seanwilson10 | 0:76fed7dd9235 | 613 | *! \brief Number of Measurement Cycles to Store in FIFO Register bit field structure |
seanwilson10 | 0:76fed7dd9235 | 614 | * ========================================================================== */ |
seanwilson10 | 0:76fed7dd9235 | 615 | typedef struct _ADI_ADISENSE_CORE_Fifo_Num_Cycles_t { |
seanwilson10 | 0:76fed7dd9235 | 616 | union { |
seanwilson10 | 0:76fed7dd9235 | 617 | struct { |
seanwilson10 | 0:76fed7dd9235 | 618 | uint8_t Fifo_Num_Cycles : 8; /**< How Many Cycles to Fill FIFO */ |
seanwilson10 | 0:76fed7dd9235 | 619 | }; |
seanwilson10 | 0:76fed7dd9235 | 620 | uint8_t VALUE8; |
seanwilson10 | 0:76fed7dd9235 | 621 | }; |
seanwilson10 | 0:76fed7dd9235 | 622 | } ADI_ADISENSE_CORE_Fifo_Num_Cycles_t; |
seanwilson10 | 0:76fed7dd9235 | 623 | |
seanwilson10 | 0:76fed7dd9235 | 624 | /*@}*/ |
seanwilson10 | 0:76fed7dd9235 | 625 | |
seanwilson10 | 0:76fed7dd9235 | 626 | /** @defgroup Multi_Cycle_Repeat_Interval Time Between Repeats of Multi-Cycle Conversions.... (Multi_Cycle_Repeat_Interval) Register |
seanwilson10 | 0:76fed7dd9235 | 627 | * Time Between Repeats of Multi-Cycle Conversions.... (Multi_Cycle_Repeat_Interval) Register. |
seanwilson10 | 0:76fed7dd9235 | 628 | * @{ |
seanwilson10 | 0:76fed7dd9235 | 629 | */ |
seanwilson10 | 0:76fed7dd9235 | 630 | |
seanwilson10 | 0:76fed7dd9235 | 631 | /* ========================================================================== |
seanwilson10 | 0:76fed7dd9235 | 632 | *! \struct ADI_ADISENSE_CORE_Multi_Cycle_Repeat_Interval_Struct |
seanwilson10 | 0:76fed7dd9235 | 633 | *! \brief Time Between Repeats of Multi-Cycle Conversions.... Register bit field structure |
seanwilson10 | 0:76fed7dd9235 | 634 | * ========================================================================== */ |
seanwilson10 | 0:76fed7dd9235 | 635 | typedef struct _ADI_ADISENSE_CORE_Multi_Cycle_Repeat_Interval_t { |
seanwilson10 | 0:76fed7dd9235 | 636 | union { |
seanwilson10 | 0:76fed7dd9235 | 637 | struct { |
seanwilson10 | 0:76fed7dd9235 | 638 | uint32_t Multi_Cycle_Repeat_Interval : 24; /**< Defines Time Between Repetitions of Measurement Cycles. */ |
seanwilson10 | 0:76fed7dd9235 | 639 | uint32_t reserved24 : 8; |
seanwilson10 | 0:76fed7dd9235 | 640 | }; |
seanwilson10 | 0:76fed7dd9235 | 641 | uint32_t VALUE32; |
seanwilson10 | 0:76fed7dd9235 | 642 | }; |
seanwilson10 | 0:76fed7dd9235 | 643 | } ADI_ADISENSE_CORE_Multi_Cycle_Repeat_Interval_t; |
seanwilson10 | 0:76fed7dd9235 | 644 | |
seanwilson10 | 0:76fed7dd9235 | 645 | /*@}*/ |
seanwilson10 | 0:76fed7dd9235 | 646 | |
seanwilson10 | 0:76fed7dd9235 | 647 | /** @defgroup Status General Status (Status) Register |
seanwilson10 | 0:76fed7dd9235 | 648 | * General Status (Status) Register. |
seanwilson10 | 0:76fed7dd9235 | 649 | * @{ |
seanwilson10 | 0:76fed7dd9235 | 650 | */ |
seanwilson10 | 0:76fed7dd9235 | 651 | |
seanwilson10 | 0:76fed7dd9235 | 652 | /* ========================================================================== |
seanwilson10 | 0:76fed7dd9235 | 653 | *! \struct ADI_ADISENSE_CORE_Status_Struct |
seanwilson10 | 0:76fed7dd9235 | 654 | *! \brief General Status Register bit field structure |
seanwilson10 | 0:76fed7dd9235 | 655 | * ========================================================================== */ |
seanwilson10 | 0:76fed7dd9235 | 656 | typedef struct _ADI_ADISENSE_CORE_Status_t { |
seanwilson10 | 0:76fed7dd9235 | 657 | union { |
seanwilson10 | 0:76fed7dd9235 | 658 | struct { |
seanwilson10 | 0:76fed7dd9235 | 659 | uint8_t reserved0 : 1; |
seanwilson10 | 0:76fed7dd9235 | 660 | uint8_t Alert_Active : 1; /**< Indicates One or More Sensors Alerts are Active */ |
seanwilson10 | 0:76fed7dd9235 | 661 | uint8_t Error : 1; /**< Indicates an Error */ |
seanwilson10 | 0:76fed7dd9235 | 662 | uint8_t Drdy : 1; /**< Indicates a New Sensor Result is Available to Be Read */ |
seanwilson10 | 0:76fed7dd9235 | 663 | uint8_t Cmd_Running : 1; /**< Indicates a Special Command is Active */ |
seanwilson10 | 0:76fed7dd9235 | 664 | uint8_t FIFO_Error : 1; /**< Indicates Error with FIFO */ |
seanwilson10 | 0:76fed7dd9235 | 665 | uint8_t reserved6 : 2; |
seanwilson10 | 0:76fed7dd9235 | 666 | }; |
seanwilson10 | 0:76fed7dd9235 | 667 | uint8_t VALUE8; |
seanwilson10 | 0:76fed7dd9235 | 668 | }; |
seanwilson10 | 0:76fed7dd9235 | 669 | } ADI_ADISENSE_CORE_Status_t; |
seanwilson10 | 0:76fed7dd9235 | 670 | |
seanwilson10 | 0:76fed7dd9235 | 671 | /*@}*/ |
seanwilson10 | 0:76fed7dd9235 | 672 | |
seanwilson10 | 0:76fed7dd9235 | 673 | /** @defgroup Diagnostics_Status Diagnostics Status (Diagnostics_Status) Register |
seanwilson10 | 0:76fed7dd9235 | 674 | * Diagnostics Status (Diagnostics_Status) Register. |
seanwilson10 | 0:76fed7dd9235 | 675 | * @{ |
seanwilson10 | 0:76fed7dd9235 | 676 | */ |
seanwilson10 | 0:76fed7dd9235 | 677 | |
seanwilson10 | 0:76fed7dd9235 | 678 | /* ========================================================================== |
seanwilson10 | 0:76fed7dd9235 | 679 | *! \struct ADI_ADISENSE_CORE_Diagnostics_Status_Struct |
seanwilson10 | 0:76fed7dd9235 | 680 | *! \brief Diagnostics Status Register bit field structure |
seanwilson10 | 0:76fed7dd9235 | 681 | * ========================================================================== */ |
seanwilson10 | 0:76fed7dd9235 | 682 | typedef struct _ADI_ADISENSE_CORE_Diagnostics_Status_t { |
seanwilson10 | 0:76fed7dd9235 | 683 | union { |
seanwilson10 | 0:76fed7dd9235 | 684 | struct { |
seanwilson10 | 0:76fed7dd9235 | 685 | uint16_t Diag_Checksum_Error : 1; /**< Indicates Error on Internal Checksum Calculations */ |
seanwilson10 | 0:76fed7dd9235 | 686 | uint16_t Diag_Comms_Error : 1; /**< Indicates Error on Internal Device Communications */ |
seanwilson10 | 0:76fed7dd9235 | 687 | uint16_t Diag_Supply_Monitor_Error : 1; /**< Indicates Low Voltage on Internal Supply Voltages */ |
seanwilson10 | 0:76fed7dd9235 | 688 | uint16_t Diag_Supply_Cap_Error : 1; /**< Indicates Fault on Internal Supply Regulator Capacitor */ |
seanwilson10 | 0:76fed7dd9235 | 689 | uint16_t reserved4 : 4; |
seanwilson10 | 0:76fed7dd9235 | 690 | uint16_t Diag_Ainm_UV_Error : 1; /**< Indicates Under-Voltage Error on Negative Analog Input */ |
seanwilson10 | 0:76fed7dd9235 | 691 | uint16_t Diag_Ainm_OV_Error : 1; /**< Indicates Over-Voltage Error on Negative Analog Input */ |
seanwilson10 | 0:76fed7dd9235 | 692 | uint16_t Diag_Ainp_UV_Error : 1; /**< Indicates Under-Voltage Error on Positive Analog Input */ |
seanwilson10 | 0:76fed7dd9235 | 693 | uint16_t Diag_Ainp_OV_Error : 1; /**< Indicates Over-Voltage Error on Positive Analog Input */ |
seanwilson10 | 0:76fed7dd9235 | 694 | uint16_t Diag_Conversion_Error : 1; /**< Indicates Error During Internal ADC Conversions */ |
seanwilson10 | 0:76fed7dd9235 | 695 | uint16_t Diag_Calibration_Error : 1; /**< Indicates Error During Internal Device Calibrations */ |
seanwilson10 | 0:76fed7dd9235 | 696 | uint16_t Diagnostics_Status_Sundry : 2; /**< Sundry Diagnostics Status */ |
seanwilson10 | 0:76fed7dd9235 | 697 | }; |
seanwilson10 | 0:76fed7dd9235 | 698 | uint16_t VALUE16; |
seanwilson10 | 0:76fed7dd9235 | 699 | }; |
seanwilson10 | 0:76fed7dd9235 | 700 | } ADI_ADISENSE_CORE_Diagnostics_Status_t; |
seanwilson10 | 0:76fed7dd9235 | 701 | |
seanwilson10 | 0:76fed7dd9235 | 702 | /*@}*/ |
seanwilson10 | 0:76fed7dd9235 | 703 | |
seanwilson10 | 0:76fed7dd9235 | 704 | /** @defgroup Channel_Alert_Status Alert Status Summary (Channel_Alert_Status) Register |
seanwilson10 | 0:76fed7dd9235 | 705 | * Alert Status Summary (Channel_Alert_Status) Register. |
seanwilson10 | 0:76fed7dd9235 | 706 | * @{ |
seanwilson10 | 0:76fed7dd9235 | 707 | */ |
seanwilson10 | 0:76fed7dd9235 | 708 | |
seanwilson10 | 0:76fed7dd9235 | 709 | /* ========================================================================== |
seanwilson10 | 0:76fed7dd9235 | 710 | *! \struct ADI_ADISENSE_CORE_Channel_Alert_Status_Struct |
seanwilson10 | 0:76fed7dd9235 | 711 | *! \brief Alert Status Summary Register bit field structure |
seanwilson10 | 0:76fed7dd9235 | 712 | * ========================================================================== */ |
seanwilson10 | 0:76fed7dd9235 | 713 | typedef struct _ADI_ADISENSE_CORE_Channel_Alert_Status_t { |
seanwilson10 | 0:76fed7dd9235 | 714 | union { |
seanwilson10 | 0:76fed7dd9235 | 715 | struct { |
seanwilson10 | 0:76fed7dd9235 | 716 | uint16_t Alert_Ch0 : 1; /**< Indicates Channel Alert is Active */ |
seanwilson10 | 0:76fed7dd9235 | 717 | uint16_t Alert_Ch1 : 1; /**< Indicates Channel Alert is Active */ |
seanwilson10 | 0:76fed7dd9235 | 718 | uint16_t Alert_Ch2 : 1; /**< Indicates Channel Alert is Active */ |
seanwilson10 | 0:76fed7dd9235 | 719 | uint16_t Alert_Ch3 : 1; /**< Indicates Channel Alert is Active */ |
seanwilson10 | 0:76fed7dd9235 | 720 | uint16_t Alert_Ch4 : 1; /**< Indicates Channel Alert is Active */ |
seanwilson10 | 0:76fed7dd9235 | 721 | uint16_t Alert_Ch5 : 1; /**< Indicates Channel Alert is Active */ |
seanwilson10 | 0:76fed7dd9235 | 722 | uint16_t Alert_Ch6 : 1; /**< Indicates Channel Alert is Active */ |
seanwilson10 | 0:76fed7dd9235 | 723 | uint16_t Alert_Ch7 : 1; /**< Indicates Channel Alert is Active */ |
seanwilson10 | 0:76fed7dd9235 | 724 | uint16_t Alert_Ch8 : 1; /**< Indicates Channel Alert is Active */ |
seanwilson10 | 0:76fed7dd9235 | 725 | uint16_t Alert_Ch9 : 1; /**< Indicates Channel Alert is Active */ |
seanwilson10 | 0:76fed7dd9235 | 726 | uint16_t Alert_Ch10 : 1; /**< Indicates Channel Alert is Active */ |
seanwilson10 | 0:76fed7dd9235 | 727 | uint16_t Alert_Ch11 : 1; /**< Indicates Channel Alert is Active */ |
seanwilson10 | 0:76fed7dd9235 | 728 | uint16_t Alert_Ch12 : 1; /**< Indicates Channel Alert is Active */ |
seanwilson10 | 0:76fed7dd9235 | 729 | uint16_t reserved13 : 3; |
seanwilson10 | 0:76fed7dd9235 | 730 | }; |
seanwilson10 | 0:76fed7dd9235 | 731 | uint16_t VALUE16; |
seanwilson10 | 0:76fed7dd9235 | 732 | }; |
seanwilson10 | 0:76fed7dd9235 | 733 | } ADI_ADISENSE_CORE_Channel_Alert_Status_t; |
seanwilson10 | 0:76fed7dd9235 | 734 | |
seanwilson10 | 0:76fed7dd9235 | 735 | /*@}*/ |
seanwilson10 | 0:76fed7dd9235 | 736 | |
seanwilson10 | 0:76fed7dd9235 | 737 | /** @defgroup Alert_Status_2 Additional Alert Status Information (Alert_Status_2) Register |
seanwilson10 | 0:76fed7dd9235 | 738 | * Additional Alert Status Information (Alert_Status_2) Register. |
seanwilson10 | 0:76fed7dd9235 | 739 | * @{ |
seanwilson10 | 0:76fed7dd9235 | 740 | */ |
seanwilson10 | 0:76fed7dd9235 | 741 | |
seanwilson10 | 0:76fed7dd9235 | 742 | /* ========================================================================== |
seanwilson10 | 0:76fed7dd9235 | 743 | *! \struct ADI_ADISENSE_CORE_Alert_Status_2_Struct |
seanwilson10 | 0:76fed7dd9235 | 744 | *! \brief Additional Alert Status Information Register bit field structure |
seanwilson10 | 0:76fed7dd9235 | 745 | * ========================================================================== */ |
seanwilson10 | 0:76fed7dd9235 | 746 | typedef struct _ADI_ADISENSE_CORE_Alert_Status_2_t { |
seanwilson10 | 0:76fed7dd9235 | 747 | union { |
seanwilson10 | 0:76fed7dd9235 | 748 | struct { |
seanwilson10 | 0:76fed7dd9235 | 749 | uint16_t reserved0 : 1; |
seanwilson10 | 0:76fed7dd9235 | 750 | uint16_t LUT_Error : 1; /**< Indicates Error with One or More Look-Up-Tables */ |
seanwilson10 | 0:76fed7dd9235 | 751 | uint16_t Configuration_Error : 1; /**< Indicates Error with Programmed Configuration */ |
seanwilson10 | 0:76fed7dd9235 | 752 | uint16_t reserved3 : 13; |
seanwilson10 | 0:76fed7dd9235 | 753 | }; |
seanwilson10 | 0:76fed7dd9235 | 754 | uint16_t VALUE16; |
seanwilson10 | 0:76fed7dd9235 | 755 | }; |
seanwilson10 | 0:76fed7dd9235 | 756 | } ADI_ADISENSE_CORE_Alert_Status_2_t; |
seanwilson10 | 0:76fed7dd9235 | 757 | |
seanwilson10 | 0:76fed7dd9235 | 758 | /*@}*/ |
seanwilson10 | 0:76fed7dd9235 | 759 | |
seanwilson10 | 0:76fed7dd9235 | 760 | /** @defgroup Alert_Detail_Ch Detailed Error Information (Alert_Detail_Ch) Register |
seanwilson10 | 0:76fed7dd9235 | 761 | * Detailed Error Information (Alert_Detail_Ch) Register. |
seanwilson10 | 0:76fed7dd9235 | 762 | * @{ |
seanwilson10 | 0:76fed7dd9235 | 763 | */ |
seanwilson10 | 0:76fed7dd9235 | 764 | |
seanwilson10 | 0:76fed7dd9235 | 765 | /* ========================================================================== |
seanwilson10 | 0:76fed7dd9235 | 766 | *! \struct ADI_ADISENSE_CORE_Alert_Detail_Ch_Struct |
seanwilson10 | 0:76fed7dd9235 | 767 | *! \brief Detailed Error Information Register bit field structure |
seanwilson10 | 0:76fed7dd9235 | 768 | * ========================================================================== */ |
seanwilson10 | 0:76fed7dd9235 | 769 | typedef struct _ADI_ADISENSE_CORE_Alert_Detail_Ch_t { |
seanwilson10 | 0:76fed7dd9235 | 770 | union { |
seanwilson10 | 0:76fed7dd9235 | 771 | struct { |
seanwilson10 | 0:76fed7dd9235 | 772 | uint16_t Time_Out : 1; /**< Indicates Time-Out Error from Digital Sensor */ |
seanwilson10 | 0:76fed7dd9235 | 773 | uint16_t Under_Range : 1; /**< Indicates Channel Under-Range */ |
seanwilson10 | 0:76fed7dd9235 | 774 | uint16_t Over_Range : 1; /**< Indicates Channel Over-Range */ |
seanwilson10 | 0:76fed7dd9235 | 775 | uint16_t Low_Limit : 1; /**< Indicates Sensor Result is Less Than Low Limit */ |
seanwilson10 | 0:76fed7dd9235 | 776 | uint16_t High_Limit : 1; /**< Indicates Sensor Result is Greater Than High Limit */ |
seanwilson10 | 0:76fed7dd9235 | 777 | uint16_t Sensor_Open : 1; /**< Indicates Sensor Input is Open Circuit */ |
seanwilson10 | 0:76fed7dd9235 | 778 | uint16_t Ref_Detect : 1; /**< Indicates Whether ADC Reference is Valid */ |
seanwilson10 | 0:76fed7dd9235 | 779 | uint16_t reserved7 : 1; |
seanwilson10 | 0:76fed7dd9235 | 780 | uint16_t Config_Err : 1; /**< Indicates Configuration Error on Channel */ |
seanwilson10 | 0:76fed7dd9235 | 781 | uint16_t LUT_Error_Ch : 1; /**< Indicates Error with Channel Look-Up-Table */ |
seanwilson10 | 0:76fed7dd9235 | 782 | uint16_t Under_Voltage : 1; /**< Indicates Channel Under-Voltage */ |
seanwilson10 | 0:76fed7dd9235 | 783 | uint16_t Over_Voltage : 1; /**< Indicates Channel Over-Voltage */ |
seanwilson10 | 0:76fed7dd9235 | 784 | uint16_t Correction_UnderRange : 1; /**< Indicates Result Less Than LUT/Equation Range */ |
seanwilson10 | 0:76fed7dd9235 | 785 | uint16_t Correction_OverRange : 1; /**< Indicates Result Larger Than LUT/Equation Range */ |
seanwilson10 | 0:76fed7dd9235 | 786 | uint16_t Sensor_Not_Ready : 1; /**< Indicates Digital Sensor Not Ready When Read */ |
seanwilson10 | 0:76fed7dd9235 | 787 | uint16_t Comp_Not_Ready : 1; /**< Indicates Compensation Channel Not Ready When Required */ |
seanwilson10 | 0:76fed7dd9235 | 788 | }; |
seanwilson10 | 0:76fed7dd9235 | 789 | uint16_t VALUE16; |
seanwilson10 | 0:76fed7dd9235 | 790 | }; |
seanwilson10 | 0:76fed7dd9235 | 791 | } ADI_ADISENSE_CORE_Alert_Detail_Ch_t; |
seanwilson10 | 0:76fed7dd9235 | 792 | |
seanwilson10 | 0:76fed7dd9235 | 793 | /*@}*/ |
seanwilson10 | 0:76fed7dd9235 | 794 | |
seanwilson10 | 0:76fed7dd9235 | 795 | /** @defgroup Error_Code Code Indicating Source of Error (Error_Code) Register |
seanwilson10 | 0:76fed7dd9235 | 796 | * Code Indicating Source of Error (Error_Code) Register. |
seanwilson10 | 0:76fed7dd9235 | 797 | * @{ |
seanwilson10 | 0:76fed7dd9235 | 798 | */ |
seanwilson10 | 0:76fed7dd9235 | 799 | |
seanwilson10 | 0:76fed7dd9235 | 800 | /* ========================================================================== |
seanwilson10 | 0:76fed7dd9235 | 801 | *! \struct ADI_ADISENSE_CORE_Error_Code_Struct |
seanwilson10 | 0:76fed7dd9235 | 802 | *! \brief Code Indicating Source of Error Register bit field structure |
seanwilson10 | 0:76fed7dd9235 | 803 | * ========================================================================== */ |
seanwilson10 | 0:76fed7dd9235 | 804 | typedef struct _ADI_ADISENSE_CORE_Error_Code_t { |
seanwilson10 | 0:76fed7dd9235 | 805 | union { |
seanwilson10 | 0:76fed7dd9235 | 806 | struct { |
seanwilson10 | 0:76fed7dd9235 | 807 | uint16_t Error_Code : 16; /**< Code Indicating Type of Error */ |
seanwilson10 | 0:76fed7dd9235 | 808 | }; |
seanwilson10 | 0:76fed7dd9235 | 809 | uint16_t VALUE16; |
seanwilson10 | 0:76fed7dd9235 | 810 | }; |
seanwilson10 | 0:76fed7dd9235 | 811 | } ADI_ADISENSE_CORE_Error_Code_t; |
seanwilson10 | 0:76fed7dd9235 | 812 | |
seanwilson10 | 0:76fed7dd9235 | 813 | /*@}*/ |
seanwilson10 | 0:76fed7dd9235 | 814 | |
seanwilson10 | 0:76fed7dd9235 | 815 | /** @defgroup Alert_Code Code Indicating Source of Alert (Alert_Code) Register |
seanwilson10 | 0:76fed7dd9235 | 816 | * Code Indicating Source of Alert (Alert_Code) Register. |
seanwilson10 | 0:76fed7dd9235 | 817 | * @{ |
seanwilson10 | 0:76fed7dd9235 | 818 | */ |
seanwilson10 | 0:76fed7dd9235 | 819 | |
seanwilson10 | 0:76fed7dd9235 | 820 | /* ========================================================================== |
seanwilson10 | 0:76fed7dd9235 | 821 | *! \struct ADI_ADISENSE_CORE_Alert_Code_Struct |
seanwilson10 | 0:76fed7dd9235 | 822 | *! \brief Code Indicating Source of Alert Register bit field structure |
seanwilson10 | 0:76fed7dd9235 | 823 | * ========================================================================== */ |
seanwilson10 | 0:76fed7dd9235 | 824 | typedef struct _ADI_ADISENSE_CORE_Alert_Code_t { |
seanwilson10 | 0:76fed7dd9235 | 825 | union { |
seanwilson10 | 0:76fed7dd9235 | 826 | struct { |
seanwilson10 | 0:76fed7dd9235 | 827 | uint16_t Alert_Code : 16; /**< Code Indicating Type of Alert */ |
seanwilson10 | 0:76fed7dd9235 | 828 | }; |
seanwilson10 | 0:76fed7dd9235 | 829 | uint16_t VALUE16; |
seanwilson10 | 0:76fed7dd9235 | 830 | }; |
seanwilson10 | 0:76fed7dd9235 | 831 | } ADI_ADISENSE_CORE_Alert_Code_t; |
seanwilson10 | 0:76fed7dd9235 | 832 | |
seanwilson10 | 0:76fed7dd9235 | 833 | /*@}*/ |
seanwilson10 | 0:76fed7dd9235 | 834 | |
seanwilson10 | 0:76fed7dd9235 | 835 | /** @defgroup External_Reference1 External Reference Information (External_Reference1) Register |
seanwilson10 | 0:76fed7dd9235 | 836 | * External Reference Information (External_Reference1) Register. |
seanwilson10 | 0:76fed7dd9235 | 837 | * @{ |
seanwilson10 | 0:76fed7dd9235 | 838 | */ |
seanwilson10 | 0:76fed7dd9235 | 839 | |
seanwilson10 | 0:76fed7dd9235 | 840 | /* ========================================================================== |
seanwilson10 | 0:76fed7dd9235 | 841 | *! \struct ADI_ADISENSE_CORE_External_Reference1_Struct |
seanwilson10 | 0:76fed7dd9235 | 842 | *! \brief External Reference Information Register bit field structure |
seanwilson10 | 0:76fed7dd9235 | 843 | * ========================================================================== */ |
seanwilson10 | 0:76fed7dd9235 | 844 | typedef struct _ADI_ADISENSE_CORE_External_Reference1_t { |
seanwilson10 | 0:76fed7dd9235 | 845 | union { |
seanwilson10 | 0:76fed7dd9235 | 846 | struct { |
seanwilson10 | 0:76fed7dd9235 | 847 | float Ext_Refin1_Value; /**< Refin1 Value */ |
seanwilson10 | 0:76fed7dd9235 | 848 | }; |
seanwilson10 | 0:76fed7dd9235 | 849 | float VALUE32; |
seanwilson10 | 0:76fed7dd9235 | 850 | }; |
seanwilson10 | 0:76fed7dd9235 | 851 | } ADI_ADISENSE_CORE_External_Reference1_t; |
seanwilson10 | 0:76fed7dd9235 | 852 | |
seanwilson10 | 0:76fed7dd9235 | 853 | /*@}*/ |
seanwilson10 | 0:76fed7dd9235 | 854 | |
seanwilson10 | 0:76fed7dd9235 | 855 | /** @defgroup External_Reference2 External Reference Information (External_Reference2) Register |
seanwilson10 | 0:76fed7dd9235 | 856 | * External Reference Information (External_Reference2) Register. |
seanwilson10 | 0:76fed7dd9235 | 857 | * @{ |
seanwilson10 | 0:76fed7dd9235 | 858 | */ |
seanwilson10 | 0:76fed7dd9235 | 859 | |
seanwilson10 | 0:76fed7dd9235 | 860 | /* ========================================================================== |
seanwilson10 | 0:76fed7dd9235 | 861 | *! \struct ADI_ADISENSE_CORE_External_Reference2_Struct |
seanwilson10 | 0:76fed7dd9235 | 862 | *! \brief External Reference Information Register bit field structure |
seanwilson10 | 0:76fed7dd9235 | 863 | * ========================================================================== */ |
seanwilson10 | 0:76fed7dd9235 | 864 | typedef struct _ADI_ADISENSE_CORE_External_Reference2_t { |
seanwilson10 | 0:76fed7dd9235 | 865 | union { |
seanwilson10 | 0:76fed7dd9235 | 866 | struct { |
seanwilson10 | 0:76fed7dd9235 | 867 | float Ext_Refin2_Value; /**< Refin2 Value */ |
seanwilson10 | 0:76fed7dd9235 | 868 | }; |
seanwilson10 | 0:76fed7dd9235 | 869 | float VALUE32; |
seanwilson10 | 0:76fed7dd9235 | 870 | }; |
seanwilson10 | 0:76fed7dd9235 | 871 | } ADI_ADISENSE_CORE_External_Reference2_t; |
seanwilson10 | 0:76fed7dd9235 | 872 | |
seanwilson10 | 0:76fed7dd9235 | 873 | /*@}*/ |
seanwilson10 | 0:76fed7dd9235 | 874 | |
seanwilson10 | 0:76fed7dd9235 | 875 | /** @defgroup AVDD_Voltage AVDD Voltage (AVDD_Voltage) Register |
seanwilson10 | 0:76fed7dd9235 | 876 | * AVDD Voltage (AVDD_Voltage) Register. |
seanwilson10 | 0:76fed7dd9235 | 877 | * @{ |
seanwilson10 | 0:76fed7dd9235 | 878 | */ |
seanwilson10 | 0:76fed7dd9235 | 879 | |
seanwilson10 | 0:76fed7dd9235 | 880 | /* ========================================================================== |
seanwilson10 | 0:76fed7dd9235 | 881 | *! \struct ADI_ADISENSE_CORE_AVDD_Voltage_Struct |
seanwilson10 | 0:76fed7dd9235 | 882 | *! \brief AVDD Voltage Register bit field structure |
seanwilson10 | 0:76fed7dd9235 | 883 | * ========================================================================== */ |
seanwilson10 | 0:76fed7dd9235 | 884 | typedef struct _ADI_ADISENSE_CORE_AVDD_Voltage_t { |
seanwilson10 | 0:76fed7dd9235 | 885 | union { |
seanwilson10 | 0:76fed7dd9235 | 886 | struct { |
seanwilson10 | 0:76fed7dd9235 | 887 | float Avdd_Voltage; /**< AVDD Voltage */ |
seanwilson10 | 0:76fed7dd9235 | 888 | }; |
seanwilson10 | 0:76fed7dd9235 | 889 | float VALUE32; |
seanwilson10 | 0:76fed7dd9235 | 890 | }; |
seanwilson10 | 0:76fed7dd9235 | 891 | } ADI_ADISENSE_CORE_AVDD_Voltage_t; |
seanwilson10 | 0:76fed7dd9235 | 892 | |
seanwilson10 | 0:76fed7dd9235 | 893 | /*@}*/ |
seanwilson10 | 0:76fed7dd9235 | 894 | |
seanwilson10 | 0:76fed7dd9235 | 895 | /** @defgroup Diagnostics_Control Diagnostic Control (Diagnostics_Control) Register |
seanwilson10 | 0:76fed7dd9235 | 896 | * Diagnostic Control (Diagnostics_Control) Register. |
seanwilson10 | 0:76fed7dd9235 | 897 | * @{ |
seanwilson10 | 0:76fed7dd9235 | 898 | */ |
seanwilson10 | 0:76fed7dd9235 | 899 | |
seanwilson10 | 0:76fed7dd9235 | 900 | /* ========================================================================= |
seanwilson10 | 0:76fed7dd9235 | 901 | *! \enum ADI_ADISENSE_CORE_Diagnostics_Control_Diag_OSD_Freq |
seanwilson10 | 0:76fed7dd9235 | 902 | *! \brief Diagnostics Open Sensor Detect Frequency (Diag_OSD_Freq) Enumerations |
seanwilson10 | 0:76fed7dd9235 | 903 | * ========================================================================= */ |
seanwilson10 | 0:76fed7dd9235 | 904 | typedef enum |
seanwilson10 | 0:76fed7dd9235 | 905 | { |
seanwilson10 | 0:76fed7dd9235 | 906 | ADISENSE_CORE_DIAGNOSTICS_CONTROL_OCD_OFF = 0, /**< No Open-Circuit Detection During Measurement */ |
seanwilson10 | 0:76fed7dd9235 | 907 | ADISENSE_CORE_DIAGNOSTICS_CONTROL_OCD_PER_1_CYCLE = 1, /**< Open-Circuit Detection Performed Once Per Measurement Cycle */ |
seanwilson10 | 0:76fed7dd9235 | 908 | ADISENSE_CORE_DIAGNOSTICS_CONTROL_OCD_PER_100_CYCLES = 2, /**< Open-Circuit Detection Performed Once Per Hundred Measurement Cycles */ |
seanwilson10 | 0:76fed7dd9235 | 909 | ADISENSE_CORE_DIAGNOSTICS_CONTROL_OCD_PER_1000_CYCLES = 3 /**< Open-Circuit Detection Performed Once Per Thousand Measurement Cycles */ |
seanwilson10 | 0:76fed7dd9235 | 910 | } ADI_ADISENSE_CORE_Diagnostics_Control_Diag_OSD_Freq; |
seanwilson10 | 0:76fed7dd9235 | 911 | |
seanwilson10 | 0:76fed7dd9235 | 912 | |
seanwilson10 | 0:76fed7dd9235 | 913 | /* ========================================================================== |
seanwilson10 | 0:76fed7dd9235 | 914 | *! \struct ADI_ADISENSE_CORE_Diagnostics_Control_Struct |
seanwilson10 | 0:76fed7dd9235 | 915 | *! \brief Diagnostic Control Register bit field structure |
seanwilson10 | 0:76fed7dd9235 | 916 | * ========================================================================== */ |
seanwilson10 | 0:76fed7dd9235 | 917 | typedef struct _ADI_ADISENSE_CORE_Diagnostics_Control_t { |
seanwilson10 | 0:76fed7dd9235 | 918 | union { |
seanwilson10 | 0:76fed7dd9235 | 919 | struct { |
seanwilson10 | 0:76fed7dd9235 | 920 | uint16_t Diag_Global_En : 1; /**< Diagnostics Global Enable */ |
seanwilson10 | 0:76fed7dd9235 | 921 | uint16_t Diag_Meas_En : 1; /**< Diagnostics Measure Enable */ |
seanwilson10 | 0:76fed7dd9235 | 922 | uint16_t Diag_OSD_Freq : 2; /**< Diagnostics Open Sensor Detect Frequency */ |
seanwilson10 | 0:76fed7dd9235 | 923 | uint16_t reserved4 : 4; |
seanwilson10 | 0:76fed7dd9235 | 924 | uint16_t Diagnostics_Extra : 8; /**< Additional Diagnostics Control */ |
seanwilson10 | 0:76fed7dd9235 | 925 | }; |
seanwilson10 | 0:76fed7dd9235 | 926 | uint16_t VALUE16; |
seanwilson10 | 0:76fed7dd9235 | 927 | }; |
seanwilson10 | 0:76fed7dd9235 | 928 | } ADI_ADISENSE_CORE_Diagnostics_Control_t; |
seanwilson10 | 0:76fed7dd9235 | 929 | |
seanwilson10 | 0:76fed7dd9235 | 930 | /*@}*/ |
seanwilson10 | 0:76fed7dd9235 | 931 | |
seanwilson10 | 0:76fed7dd9235 | 932 | /** @defgroup Data_FIFO FIFO of Sensor Results (Data_FIFO) Register |
seanwilson10 | 0:76fed7dd9235 | 933 | * FIFO of Sensor Results (Data_FIFO) Register. |
seanwilson10 | 0:76fed7dd9235 | 934 | * @{ |
seanwilson10 | 0:76fed7dd9235 | 935 | */ |
seanwilson10 | 0:76fed7dd9235 | 936 | |
seanwilson10 | 0:76fed7dd9235 | 937 | /* ========================================================================== |
seanwilson10 | 0:76fed7dd9235 | 938 | *! \struct ADI_ADISENSE_CORE_Data_FIFO_Struct |
seanwilson10 | 0:76fed7dd9235 | 939 | *! \brief FIFO of Sensor Results Register bit field structure |
seanwilson10 | 0:76fed7dd9235 | 940 | * ========================================================================== */ |
seanwilson10 | 0:76fed7dd9235 | 941 | typedef struct _ADI_ADISENSE_CORE_Data_FIFO_t { |
seanwilson10 | 0:76fed7dd9235 | 942 | union { |
seanwilson10 | 0:76fed7dd9235 | 943 | struct { |
seanwilson10 | 0:76fed7dd9235 | 944 | float32_t Sensor_Result; /**< Linearized and Compensated Sensor Result */ |
seanwilson10 | 0:76fed7dd9235 | 945 | uint32_t Channel_ID : 4; /**< Indicates Which Channel This FIFO Data Corresponds to */ |
seanwilson10 | 0:76fed7dd9235 | 946 | uint32_t Ch_Error : 1; /**< Indicates Error on Channel */ |
seanwilson10 | 0:76fed7dd9235 | 947 | uint32_t Ch_Alert : 1; /**< Indicates Alert on Channel */ |
seanwilson10 | 0:76fed7dd9235 | 948 | uint32_t Ch_Raw : 1; /**< Indicates If RAW Data is Valid */ |
seanwilson10 | 0:76fed7dd9235 | 949 | uint32_t Ch_Valid : 1; /**< Indicates Whether Valid Data Read from FIFO */ |
seanwilson10 | 0:76fed7dd9235 | 950 | uint32_t Raw_Sample : 24; /**< ADC Result */ |
seanwilson10 | 0:76fed7dd9235 | 951 | }; |
seanwilson10 | 0:76fed7dd9235 | 952 | uint64_t VALUE64; |
seanwilson10 | 0:76fed7dd9235 | 953 | }; |
seanwilson10 | 0:76fed7dd9235 | 954 | } ADI_ADISENSE_CORE_Data_FIFO_t; |
seanwilson10 | 0:76fed7dd9235 | 955 | |
seanwilson10 | 0:76fed7dd9235 | 956 | /*@}*/ |
seanwilson10 | 0:76fed7dd9235 | 957 | |
seanwilson10 | 0:76fed7dd9235 | 958 | /** @defgroup LUT_Select Read/Write Strobe (LUT_Select) Register |
seanwilson10 | 0:76fed7dd9235 | 959 | * Read/Write Strobe (LUT_Select) Register. |
seanwilson10 | 0:76fed7dd9235 | 960 | * @{ |
seanwilson10 | 0:76fed7dd9235 | 961 | */ |
seanwilson10 | 0:76fed7dd9235 | 962 | |
seanwilson10 | 0:76fed7dd9235 | 963 | /* ========================================================================= |
seanwilson10 | 0:76fed7dd9235 | 964 | *! \enum ADI_ADISENSE_CORE_LUT_Select_LUT_RW |
seanwilson10 | 0:76fed7dd9235 | 965 | *! \brief Read or Write LUT Data (LUT_RW) Enumerations |
seanwilson10 | 0:76fed7dd9235 | 966 | * ========================================================================= */ |
seanwilson10 | 0:76fed7dd9235 | 967 | typedef enum |
seanwilson10 | 0:76fed7dd9235 | 968 | { |
seanwilson10 | 0:76fed7dd9235 | 969 | ADISENSE_CORE_LUT_SELECT_LUT_READ = 0, /**< Read Addressed LUT Data */ |
seanwilson10 | 0:76fed7dd9235 | 970 | ADISENSE_CORE_LUT_SELECT_LUT_WRITE = 1 /**< Write Addressed LUT Data */ |
seanwilson10 | 0:76fed7dd9235 | 971 | } ADI_ADISENSE_CORE_LUT_Select_LUT_RW; |
seanwilson10 | 0:76fed7dd9235 | 972 | |
seanwilson10 | 0:76fed7dd9235 | 973 | |
seanwilson10 | 0:76fed7dd9235 | 974 | /* ========================================================================== |
seanwilson10 | 0:76fed7dd9235 | 975 | *! \struct ADI_ADISENSE_CORE_LUT_Select_Struct |
seanwilson10 | 0:76fed7dd9235 | 976 | *! \brief Read/Write Strobe Register bit field structure |
seanwilson10 | 0:76fed7dd9235 | 977 | * ========================================================================== */ |
seanwilson10 | 0:76fed7dd9235 | 978 | typedef struct _ADI_ADISENSE_CORE_LUT_Select_t { |
seanwilson10 | 0:76fed7dd9235 | 979 | union { |
seanwilson10 | 0:76fed7dd9235 | 980 | struct { |
seanwilson10 | 0:76fed7dd9235 | 981 | uint8_t reserved0 : 7; |
seanwilson10 | 0:76fed7dd9235 | 982 | uint8_t LUT_RW : 1; /**< Read or Write LUT Data */ |
seanwilson10 | 0:76fed7dd9235 | 983 | }; |
seanwilson10 | 0:76fed7dd9235 | 984 | uint8_t VALUE8; |
seanwilson10 | 0:76fed7dd9235 | 985 | }; |
seanwilson10 | 0:76fed7dd9235 | 986 | } ADI_ADISENSE_CORE_LUT_Select_t; |
seanwilson10 | 0:76fed7dd9235 | 987 | |
seanwilson10 | 0:76fed7dd9235 | 988 | /*@}*/ |
seanwilson10 | 0:76fed7dd9235 | 989 | |
seanwilson10 | 0:76fed7dd9235 | 990 | /** @defgroup LUT_Offset Offset into Selected LUT (LUT_Offset) Register |
seanwilson10 | 0:76fed7dd9235 | 991 | * Offset into Selected LUT (LUT_Offset) Register. |
seanwilson10 | 0:76fed7dd9235 | 992 | * @{ |
seanwilson10 | 0:76fed7dd9235 | 993 | */ |
seanwilson10 | 0:76fed7dd9235 | 994 | |
seanwilson10 | 0:76fed7dd9235 | 995 | /* ========================================================================== |
seanwilson10 | 0:76fed7dd9235 | 996 | *! \struct ADI_ADISENSE_CORE_LUT_Offset_Struct |
seanwilson10 | 0:76fed7dd9235 | 997 | *! \brief Offset into Selected LUT Register bit field structure |
seanwilson10 | 0:76fed7dd9235 | 998 | * ========================================================================== */ |
seanwilson10 | 0:76fed7dd9235 | 999 | typedef struct _ADI_ADISENSE_CORE_LUT_Offset_t { |
seanwilson10 | 0:76fed7dd9235 | 1000 | union { |
seanwilson10 | 0:76fed7dd9235 | 1001 | struct { |
seanwilson10 | 0:76fed7dd9235 | 1002 | uint16_t LUT_Offset : 14; /**< Offset into Look-Up-Table */ |
seanwilson10 | 0:76fed7dd9235 | 1003 | uint16_t reserved14 : 2; |
seanwilson10 | 0:76fed7dd9235 | 1004 | }; |
seanwilson10 | 0:76fed7dd9235 | 1005 | uint16_t VALUE16; |
seanwilson10 | 0:76fed7dd9235 | 1006 | }; |
seanwilson10 | 0:76fed7dd9235 | 1007 | } ADI_ADISENSE_CORE_LUT_Offset_t; |
seanwilson10 | 0:76fed7dd9235 | 1008 | |
seanwilson10 | 0:76fed7dd9235 | 1009 | /*@}*/ |
seanwilson10 | 0:76fed7dd9235 | 1010 | |
seanwilson10 | 0:76fed7dd9235 | 1011 | /** @defgroup LUT_Data Data to Read/Write from Addressed LUT Entry (LUT_Data) Register |
seanwilson10 | 0:76fed7dd9235 | 1012 | * Data to Read/Write from Addressed LUT Entry (LUT_Data) Register. |
seanwilson10 | 0:76fed7dd9235 | 1013 | * @{ |
seanwilson10 | 0:76fed7dd9235 | 1014 | */ |
seanwilson10 | 0:76fed7dd9235 | 1015 | |
seanwilson10 | 0:76fed7dd9235 | 1016 | /* ========================================================================== |
seanwilson10 | 0:76fed7dd9235 | 1017 | *! \struct ADI_ADISENSE_CORE_LUT_Data_Struct |
seanwilson10 | 0:76fed7dd9235 | 1018 | *! \brief Data to Read/Write from Addressed LUT Entry Register bit field structure |
seanwilson10 | 0:76fed7dd9235 | 1019 | * ========================================================================== */ |
seanwilson10 | 0:76fed7dd9235 | 1020 | typedef struct _ADI_ADISENSE_CORE_LUT_Data_t { |
seanwilson10 | 0:76fed7dd9235 | 1021 | union { |
seanwilson10 | 0:76fed7dd9235 | 1022 | struct { |
seanwilson10 | 0:76fed7dd9235 | 1023 | uint8_t LUT_Data : 8; /**< Data Byte to Write to / Read from Look-Up-Table */ |
seanwilson10 | 0:76fed7dd9235 | 1024 | }; |
seanwilson10 | 0:76fed7dd9235 | 1025 | uint8_t VALUE8; |
seanwilson10 | 0:76fed7dd9235 | 1026 | }; |
seanwilson10 | 0:76fed7dd9235 | 1027 | } ADI_ADISENSE_CORE_LUT_Data_t; |
seanwilson10 | 0:76fed7dd9235 | 1028 | |
seanwilson10 | 0:76fed7dd9235 | 1029 | /*@}*/ |
seanwilson10 | 0:76fed7dd9235 | 1030 | |
seanwilson10 | 0:76fed7dd9235 | 1031 | /** @defgroup CAL_Offset Offset into Selected Calibration Values (CAL_Offset) Register |
seanwilson10 | 0:76fed7dd9235 | 1032 | * Offset into Selected Calibration Values (CAL_Offset) Register. |
seanwilson10 | 0:76fed7dd9235 | 1033 | * @{ |
seanwilson10 | 0:76fed7dd9235 | 1034 | */ |
seanwilson10 | 0:76fed7dd9235 | 1035 | |
seanwilson10 | 0:76fed7dd9235 | 1036 | /* ========================================================================== |
seanwilson10 | 0:76fed7dd9235 | 1037 | *! \struct ADI_ADISENSE_CORE_CAL_Offset_Struct |
seanwilson10 | 0:76fed7dd9235 | 1038 | *! \brief Offset into Selected Calibration Values Register bit field structure |
seanwilson10 | 0:76fed7dd9235 | 1039 | * ========================================================================== */ |
seanwilson10 | 0:76fed7dd9235 | 1040 | typedef struct _ADI_ADISENSE_CORE_CAL_Offset_t { |
seanwilson10 | 0:76fed7dd9235 | 1041 | union { |
seanwilson10 | 0:76fed7dd9235 | 1042 | struct { |
seanwilson10 | 0:76fed7dd9235 | 1043 | uint16_t CAL_Offset : 14; /**< Offset into Calibration Data */ |
seanwilson10 | 0:76fed7dd9235 | 1044 | uint16_t reserved14 : 2; |
seanwilson10 | 0:76fed7dd9235 | 1045 | }; |
seanwilson10 | 0:76fed7dd9235 | 1046 | uint16_t VALUE16; |
seanwilson10 | 0:76fed7dd9235 | 1047 | }; |
seanwilson10 | 0:76fed7dd9235 | 1048 | } ADI_ADISENSE_CORE_CAL_Offset_t; |
seanwilson10 | 0:76fed7dd9235 | 1049 | |
seanwilson10 | 0:76fed7dd9235 | 1050 | /*@}*/ |
seanwilson10 | 0:76fed7dd9235 | 1051 | |
seanwilson10 | 0:76fed7dd9235 | 1052 | /** @defgroup CAL_Data Data to Read/Write from Addressed Calibration Values (CAL_Data) Register |
seanwilson10 | 0:76fed7dd9235 | 1053 | * Data to Read/Write from Addressed Calibration Values (CAL_Data) Register. |
seanwilson10 | 0:76fed7dd9235 | 1054 | * @{ |
seanwilson10 | 0:76fed7dd9235 | 1055 | */ |
seanwilson10 | 0:76fed7dd9235 | 1056 | |
seanwilson10 | 0:76fed7dd9235 | 1057 | /* ========================================================================== |
seanwilson10 | 0:76fed7dd9235 | 1058 | *! \struct ADI_ADISENSE_CORE_CAL_Data_Struct |
seanwilson10 | 0:76fed7dd9235 | 1059 | *! \brief Data to Read/Write from Addressed Calibration Values Register bit field structure |
seanwilson10 | 0:76fed7dd9235 | 1060 | * ========================================================================== */ |
seanwilson10 | 0:76fed7dd9235 | 1061 | typedef struct _ADI_ADISENSE_CORE_CAL_Data_t { |
seanwilson10 | 0:76fed7dd9235 | 1062 | union { |
seanwilson10 | 0:76fed7dd9235 | 1063 | struct { |
seanwilson10 | 0:76fed7dd9235 | 1064 | uint8_t CAL_Data : 8; /**< Data to Write to / Read from Calibration Data */ |
seanwilson10 | 0:76fed7dd9235 | 1065 | }; |
seanwilson10 | 0:76fed7dd9235 | 1066 | uint8_t VALUE8; |
seanwilson10 | 0:76fed7dd9235 | 1067 | }; |
seanwilson10 | 0:76fed7dd9235 | 1068 | } ADI_ADISENSE_CORE_CAL_Data_t; |
seanwilson10 | 0:76fed7dd9235 | 1069 | |
seanwilson10 | 0:76fed7dd9235 | 1070 | /*@}*/ |
seanwilson10 | 0:76fed7dd9235 | 1071 | |
seanwilson10 | 0:76fed7dd9235 | 1072 | /** @defgroup Revision Hardware, Firmware Revision (Revision) Register |
seanwilson10 | 0:76fed7dd9235 | 1073 | * Hardware, Firmware Revision (Revision) Register. |
seanwilson10 | 0:76fed7dd9235 | 1074 | * @{ |
seanwilson10 | 0:76fed7dd9235 | 1075 | */ |
seanwilson10 | 0:76fed7dd9235 | 1076 | |
seanwilson10 | 0:76fed7dd9235 | 1077 | /* ========================================================================== |
seanwilson10 | 0:76fed7dd9235 | 1078 | *! \struct ADI_ADISENSE_CORE_Revision_Struct |
seanwilson10 | 0:76fed7dd9235 | 1079 | *! \brief Hardware, Firmware Revision Register bit field structure |
seanwilson10 | 0:76fed7dd9235 | 1080 | * ========================================================================== */ |
seanwilson10 | 0:76fed7dd9235 | 1081 | typedef struct _ADI_ADISENSE_CORE_Revision_t { |
seanwilson10 | 0:76fed7dd9235 | 1082 | union { |
seanwilson10 | 0:76fed7dd9235 | 1083 | struct { |
seanwilson10 | 0:76fed7dd9235 | 1084 | uint32_t Firmware_Revision : 8; /**< ID Info */ |
seanwilson10 | 0:76fed7dd9235 | 1085 | uint32_t Hardware_Revision : 8; /**< ID Info */ |
seanwilson10 | 0:76fed7dd9235 | 1086 | uint32_t Comms_Protocol : 8; /**< ID Info */ |
seanwilson10 | 0:76fed7dd9235 | 1087 | uint32_t reserved24 : 8; |
seanwilson10 | 0:76fed7dd9235 | 1088 | }; |
seanwilson10 | 0:76fed7dd9235 | 1089 | uint32_t VALUE32; |
seanwilson10 | 0:76fed7dd9235 | 1090 | }; |
seanwilson10 | 0:76fed7dd9235 | 1091 | } ADI_ADISENSE_CORE_Revision_t; |
seanwilson10 | 0:76fed7dd9235 | 1092 | |
seanwilson10 | 0:76fed7dd9235 | 1093 | /*@}*/ |
seanwilson10 | 0:76fed7dd9235 | 1094 | |
seanwilson10 | 0:76fed7dd9235 | 1095 | /** @defgroup Channel_Count Number of Channel Occurrences per Measurement Cycle (Channel_Count) Register |
seanwilson10 | 0:76fed7dd9235 | 1096 | * Number of Channel Occurrences per Measurement Cycle (Channel_Count) Register. |
seanwilson10 | 0:76fed7dd9235 | 1097 | * @{ |
seanwilson10 | 0:76fed7dd9235 | 1098 | */ |
seanwilson10 | 0:76fed7dd9235 | 1099 | |
seanwilson10 | 0:76fed7dd9235 | 1100 | /* ========================================================================== |
seanwilson10 | 0:76fed7dd9235 | 1101 | *! \struct ADI_ADISENSE_CORE_Channel_Count_Struct |
seanwilson10 | 0:76fed7dd9235 | 1102 | *! \brief Number of Channel Occurrences per Measurement Cycle Register bit field structure |
seanwilson10 | 0:76fed7dd9235 | 1103 | * ========================================================================== */ |
seanwilson10 | 0:76fed7dd9235 | 1104 | typedef struct _ADI_ADISENSE_CORE_Channel_Count_t { |
seanwilson10 | 0:76fed7dd9235 | 1105 | union { |
seanwilson10 | 0:76fed7dd9235 | 1106 | struct { |
seanwilson10 | 0:76fed7dd9235 | 1107 | uint8_t Channel_Count : 7; /**< How Many Times Channel Should Appear in One Cycle */ |
seanwilson10 | 0:76fed7dd9235 | 1108 | uint8_t Channel_Enable : 1; /**< Enable Channel in Measurement Cycle */ |
seanwilson10 | 0:76fed7dd9235 | 1109 | }; |
seanwilson10 | 0:76fed7dd9235 | 1110 | uint8_t VALUE8; |
seanwilson10 | 0:76fed7dd9235 | 1111 | }; |
seanwilson10 | 0:76fed7dd9235 | 1112 | } ADI_ADISENSE_CORE_Channel_Count_t; |
seanwilson10 | 0:76fed7dd9235 | 1113 | |
seanwilson10 | 0:76fed7dd9235 | 1114 | /*@}*/ |
seanwilson10 | 0:76fed7dd9235 | 1115 | |
seanwilson10 | 0:76fed7dd9235 | 1116 | /** @defgroup Sensor_Type Sensor Select (Sensor_Type) Register |
seanwilson10 | 0:76fed7dd9235 | 1117 | * Sensor Select (Sensor_Type) Register. |
seanwilson10 | 0:76fed7dd9235 | 1118 | * @{ |
seanwilson10 | 0:76fed7dd9235 | 1119 | */ |
seanwilson10 | 0:76fed7dd9235 | 1120 | |
seanwilson10 | 0:76fed7dd9235 | 1121 | /* ========================================================================= |
seanwilson10 | 0:76fed7dd9235 | 1122 | *! \enum ADI_ADISENSE_CORE_Sensor_Type_Sensor_Type |
seanwilson10 | 0:76fed7dd9235 | 1123 | *! \brief Sensor Type (Sensor_Type) Enumerations |
seanwilson10 | 0:76fed7dd9235 | 1124 | * ========================================================================= */ |
seanwilson10 | 0:76fed7dd9235 | 1125 | typedef enum |
seanwilson10 | 0:76fed7dd9235 | 1126 | { |
seanwilson10 | 0:76fed7dd9235 | 1127 | ADISENSE_CORE_SENSOR_TYPE_SENSOR_THERMOCOUPLE_T_DEF_L1 = 0, /**< Thermocouple T-Type Sensor Defined Level 1 */ |
seanwilson10 | 0:76fed7dd9235 | 1128 | ADISENSE_CORE_SENSOR_TYPE_SENSOR_THERMOCOUPLE_J_DEF_L1 = 1, /**< Thermocouple J-Type Sensor Defined Level 1 */ |
seanwilson10 | 0:76fed7dd9235 | 1129 | ADISENSE_CORE_SENSOR_TYPE_SENSOR_THERMOCOUPLE_K_DEF_L1 = 2, /**< Thermocouple K-Type Sensor Defined Level 1 */ |
seanwilson10 | 0:76fed7dd9235 | 1130 | ADISENSE_CORE_SENSOR_TYPE_SENSOR_THERMOCOUPLE_1_DEF_L2 = 12, /**< Thermocouple Sensor 1 Defined Level 2 */ |
seanwilson10 | 0:76fed7dd9235 | 1131 | ADISENSE_CORE_SENSOR_TYPE_SENSOR_THERMOCOUPLE_2_DEF_L2 = 13, /**< Thermocouple Sensor 2 Defined Level 2 */ |
seanwilson10 | 0:76fed7dd9235 | 1132 | ADISENSE_CORE_SENSOR_TYPE_SENSOR_THERMOCOUPLE_3_DEF_L2 = 14, /**< Thermocouple Sensor 3 Defined Level 2 */ |
seanwilson10 | 0:76fed7dd9235 | 1133 | ADISENSE_CORE_SENSOR_TYPE_SENSOR_THERMOCOUPLE_4_DEF_L2 = 15, /**< Thermocouple Sensor 4 Defined Level 2 */ |
seanwilson10 | 0:76fed7dd9235 | 1134 | ADISENSE_CORE_SENSOR_TYPE_SENSOR_THERMOCOUPLE_T_ADV_L1 = 16, /**< Thermocouple T-Type Sensor Advanced Level 1 */ |
seanwilson10 | 0:76fed7dd9235 | 1135 | ADISENSE_CORE_SENSOR_TYPE_SENSOR_THERMOCOUPLE_J_ADV_L1 = 17, /**< Thermocouple J-Type Sensor Advanced Level 1 */ |
seanwilson10 | 0:76fed7dd9235 | 1136 | ADISENSE_CORE_SENSOR_TYPE_SENSOR_THERMOCOUPLE_K_ADV_L1 = 18, /**< Thermocouple K-Type Sensor Advanced Level 1 */ |
seanwilson10 | 0:76fed7dd9235 | 1137 | ADISENSE_CORE_SENSOR_TYPE_SENSOR_THERMOCOUPLE_1_ADV_L2 = 28, /**< Thermocouple Sensor 1 Advanced Level 2 */ |
seanwilson10 | 0:76fed7dd9235 | 1138 | ADISENSE_CORE_SENSOR_TYPE_SENSOR_THERMOCOUPLE_2_ADV_L2 = 29, /**< Thermocouple Sensor 2 Advanced Level 2 */ |
seanwilson10 | 0:76fed7dd9235 | 1139 | ADISENSE_CORE_SENSOR_TYPE_SENSOR_THERMOCOUPLE_3_ADV_L2 = 30, /**< Thermocouple Sensor 3 Advanced Level 2 */ |
seanwilson10 | 0:76fed7dd9235 | 1140 | ADISENSE_CORE_SENSOR_TYPE_SENSOR_THERMOCOUPLE_4_ADV_L2 = 31, /**< Thermocouple Sensor 4 Advanced Level 2 */ |
seanwilson10 | 0:76fed7dd9235 | 1141 | ADISENSE_CORE_SENSOR_TYPE_SENSOR_RTD_2W_PT100_DEF_L1 = 32, /**< RTD 2 Wire PT100 Sensor Defined Level 1 */ |
seanwilson10 | 0:76fed7dd9235 | 1142 | ADISENSE_CORE_SENSOR_TYPE_SENSOR_RTD_2W_PT1000_DEF_L1 = 33, /**< RTD 2 Wire PT1000 Sensor Defined Level 1 */ |
seanwilson10 | 0:76fed7dd9235 | 1143 | ADISENSE_CORE_SENSOR_TYPE_SENSOR_RTD_2W_1_DEF_L2 = 44, /**< RTD 2 Wire Sensor 1 Defined Level 2 */ |
seanwilson10 | 0:76fed7dd9235 | 1144 | ADISENSE_CORE_SENSOR_TYPE_SENSOR_RTD_2W_2_DEF_L2 = 45, /**< RTD 2 Wire Sensor 2 Defined Level 2 */ |
seanwilson10 | 0:76fed7dd9235 | 1145 | ADISENSE_CORE_SENSOR_TYPE_SENSOR_RTD_2W_3_DEF_L2 = 46, /**< RTD 2 Wire Sensor 3 Defined Level 2 */ |
seanwilson10 | 0:76fed7dd9235 | 1146 | ADISENSE_CORE_SENSOR_TYPE_SENSOR_RTD_2W_4_DEF_L2 = 47, /**< RTD 2 Wire Sensor 4 Defined Level 2 */ |
seanwilson10 | 0:76fed7dd9235 | 1147 | ADISENSE_CORE_SENSOR_TYPE_SENSOR_RTD_2W_PT100_ADV_L1 = 48, /**< RTD 2 Wire PT100 Sensor Advanced Level 1 */ |
seanwilson10 | 0:76fed7dd9235 | 1148 | ADISENSE_CORE_SENSOR_TYPE_SENSOR_RTD_2W_PT1000_ADV_L1 = 49, /**< RTD 2 Wire PT1000 Sensor Advanced Level 1 */ |
seanwilson10 | 0:76fed7dd9235 | 1149 | ADISENSE_CORE_SENSOR_TYPE_SENSOR_RTD_2W_1_ADV_L2 = 60, /**< RTD 2 Wire Sensor 1 Advanced Level 2 */ |
seanwilson10 | 0:76fed7dd9235 | 1150 | ADISENSE_CORE_SENSOR_TYPE_SENSOR_RTD_2W_2_ADV_L2 = 61, /**< RTD 2 Wire Sensor 2 Advanced Level 2 */ |
seanwilson10 | 0:76fed7dd9235 | 1151 | ADISENSE_CORE_SENSOR_TYPE_SENSOR_RTD_2W_3_ADV_L2 = 62, /**< RTD 2 Wire Sensor 3 Advanced Level 2 */ |
seanwilson10 | 0:76fed7dd9235 | 1152 | ADISENSE_CORE_SENSOR_TYPE_SENSOR_RTD_2W_4_ADV_L2 = 63, /**< RTD 2 Wire Sensor 4 Advanced Level 2 */ |
seanwilson10 | 0:76fed7dd9235 | 1153 | ADISENSE_CORE_SENSOR_TYPE_SENSOR_RTD_3W_PT100_DEF_L1 = 64, /**< RTD 3 Wire PT100 Sensor Defined Level 1 */ |
seanwilson10 | 0:76fed7dd9235 | 1154 | ADISENSE_CORE_SENSOR_TYPE_SENSOR_RTD_3W_PT1000_DEF_L1 = 65, /**< RTD 3 Wire PT1000 Sensor Defined Level 1 */ |
seanwilson10 | 0:76fed7dd9235 | 1155 | ADISENSE_CORE_SENSOR_TYPE_SENSOR_RTD_3W_1_DEF_L2 = 76, /**< RTD 3 Wire Sensor 1 Defined Level 2 */ |
seanwilson10 | 0:76fed7dd9235 | 1156 | ADISENSE_CORE_SENSOR_TYPE_SENSOR_RTD_3W_2_DEF_L2 = 77, /**< RTD 3 Wire Sensor 2 Defined Level 2 */ |
seanwilson10 | 0:76fed7dd9235 | 1157 | ADISENSE_CORE_SENSOR_TYPE_SENSOR_RTD_3W_3_DEF_L2 = 78, /**< RTD 3 Wire Sensor 3 Defined Level 2 */ |
seanwilson10 | 0:76fed7dd9235 | 1158 | ADISENSE_CORE_SENSOR_TYPE_SENSOR_RTD_3W_4_DEF_L2 = 79, /**< RTD 3 Wire Sensor 4 Defined Level 2 */ |
seanwilson10 | 0:76fed7dd9235 | 1159 | ADISENSE_CORE_SENSOR_TYPE_SENSOR_RTD_3W_PT100_ADV_L1 = 80, /**< RTD 3 Wire PT100 Sensor Advanced Level 1 */ |
seanwilson10 | 0:76fed7dd9235 | 1160 | ADISENSE_CORE_SENSOR_TYPE_SENSOR_RTD_3W_PT1000_ADV_L1 = 81, /**< RTD 3 Wire PT1000 Sensor Advanced Level 1 */ |
seanwilson10 | 0:76fed7dd9235 | 1161 | ADISENSE_CORE_SENSOR_TYPE_SENSOR_RTD_3W_1_ADV_L2 = 92, /**< RTD 3 Wire Sensor 1 Advanced Level 2 */ |
seanwilson10 | 0:76fed7dd9235 | 1162 | ADISENSE_CORE_SENSOR_TYPE_SENSOR_RTD_3W_2_ADV_L2 = 93, /**< RTD 3 Wire Sensor 2 Advanced Level 2 */ |
seanwilson10 | 0:76fed7dd9235 | 1163 | ADISENSE_CORE_SENSOR_TYPE_SENSOR_RTD_3W_3_ADV_L2 = 94, /**< RTD 3 Wire Sensor 3 Advanced Level 2 */ |
seanwilson10 | 0:76fed7dd9235 | 1164 | ADISENSE_CORE_SENSOR_TYPE_SENSOR_RTD_3W_4_ADV_L2 = 95, /**< RTD 3 Wire Sensor 4 Advanced Level 2 */ |
seanwilson10 | 0:76fed7dd9235 | 1165 | ADISENSE_CORE_SENSOR_TYPE_SENSOR_RTD_4W_PT100_DEF_L1 = 96, /**< RTD 4 Wire PT100 Sensor Defined Level 1 */ |
seanwilson10 | 0:76fed7dd9235 | 1166 | ADISENSE_CORE_SENSOR_TYPE_SENSOR_RTD_4W_PT1000_DEF_L1 = 97, /**< RTD 4 Wire PT1000 Sensor Defined Level 1 */ |
seanwilson10 | 0:76fed7dd9235 | 1167 | ADISENSE_CORE_SENSOR_TYPE_SENSOR_RTD_4W_1_DEF_L2 = 108, /**< RTD 4 Wire Sensor 1 Defined Level 2 */ |
seanwilson10 | 0:76fed7dd9235 | 1168 | ADISENSE_CORE_SENSOR_TYPE_SENSOR_RTD_4W_2_DEF_L2 = 109, /**< RTD 4 Wire Sensor 2 Defined Level 2 */ |
seanwilson10 | 0:76fed7dd9235 | 1169 | ADISENSE_CORE_SENSOR_TYPE_SENSOR_RTD_4W_3_DEF_L2 = 110, /**< RTD 4 Wire Sensor 3 Defined Level 2 */ |
seanwilson10 | 0:76fed7dd9235 | 1170 | ADISENSE_CORE_SENSOR_TYPE_SENSOR_RTD_4W_4_DEF_L2 = 111, /**< RTD 4 Wire Sensor 4 Defined Level 2 */ |
seanwilson10 | 0:76fed7dd9235 | 1171 | ADISENSE_CORE_SENSOR_TYPE_SENSOR_RTD_4W_PT100_ADV_L1 = 112, /**< RTD 4 Wire PT100 Sensor Advanced Level 1 */ |
seanwilson10 | 0:76fed7dd9235 | 1172 | ADISENSE_CORE_SENSOR_TYPE_SENSOR_RTD_4W_PT1000_ADV_L1 = 113, /**< RTD 4 Wire PT1000 Sensor Advanced Level 1 */ |
seanwilson10 | 0:76fed7dd9235 | 1173 | ADISENSE_CORE_SENSOR_TYPE_SENSOR_RTD_4W_1_ADV_L2 = 124, /**< RTD 4 Wire Sensor 1 Advanced Level 2 */ |
seanwilson10 | 0:76fed7dd9235 | 1174 | ADISENSE_CORE_SENSOR_TYPE_SENSOR_RTD_4W_2_ADV_L2 = 125, /**< RTD 4 Wire Sensor 2 Advanced Level 2 */ |
seanwilson10 | 0:76fed7dd9235 | 1175 | ADISENSE_CORE_SENSOR_TYPE_SENSOR_RTD_4W_3_ADV_L2 = 126, /**< RTD 4 Wire Sensor 3 Advanced Level 2 */ |
seanwilson10 | 0:76fed7dd9235 | 1176 | ADISENSE_CORE_SENSOR_TYPE_SENSOR_RTD_4W_4_ADV_L2 = 127, /**< RTD 4 Wire Sensor 4 Advanced Level 2 */ |
seanwilson10 | 0:76fed7dd9235 | 1177 | ADISENSE_CORE_SENSOR_TYPE_SENSOR_THERMISTOR_A_10K_DEF_L1 = 128, /**< Thermistor Type A 10kOhm Sensor Defined Level 1 */ |
seanwilson10 | 0:76fed7dd9235 | 1178 | ADISENSE_CORE_SENSOR_TYPE_SENSOR_THERMISTOR_B_10K_DEF_L1 = 129, /**< Thermistor Type B 10kOhm Sensor Defined Level 1 */ |
seanwilson10 | 0:76fed7dd9235 | 1179 | ADISENSE_CORE_SENSOR_TYPE_SENSOR_THERMISTOR_1_DEF_L2 = 140, /**< Thermistor Sensor 1 Defined Level 2 */ |
seanwilson10 | 0:76fed7dd9235 | 1180 | ADISENSE_CORE_SENSOR_TYPE_SENSOR_THERMISTOR_2_DEF_L2 = 141, /**< Thermistor Sensor 2 Defined Level 2 */ |
seanwilson10 | 0:76fed7dd9235 | 1181 | ADISENSE_CORE_SENSOR_TYPE_SENSOR_THERMISTOR_3_DEF_L2 = 142, /**< Thermistor Sensor 3 Defined Level 2 */ |
seanwilson10 | 0:76fed7dd9235 | 1182 | ADISENSE_CORE_SENSOR_TYPE_SENSOR_THERMISTOR_4_DEF_L2 = 143, /**< Thermistor Sensor 4 Defined Level 2 */ |
seanwilson10 | 0:76fed7dd9235 | 1183 | ADISENSE_CORE_SENSOR_TYPE_SENSOR_THERMISTOR_A_10K_ADV_L1 = 144, /**< Thermistor Type A 10kOhm Sensor Advanced Level 1 */ |
seanwilson10 | 0:76fed7dd9235 | 1184 | ADISENSE_CORE_SENSOR_TYPE_SENSOR_THERMISTOR_B_10K_ADV_L1 = 145, /**< Thermistor Type B 10kOhm Sensor Advanced Level 1 */ |
seanwilson10 | 0:76fed7dd9235 | 1185 | ADISENSE_CORE_SENSOR_TYPE_SENSOR_THERMISTOR_1_ADV_L2 = 156, /**< Thermistor Sensor 1 Advanced Level 2 */ |
seanwilson10 | 0:76fed7dd9235 | 1186 | ADISENSE_CORE_SENSOR_TYPE_SENSOR_THERMISTOR_2_ADV_L2 = 157, /**< Thermistor Sensor 2 Advanced Level 2 */ |
seanwilson10 | 0:76fed7dd9235 | 1187 | ADISENSE_CORE_SENSOR_TYPE_SENSOR_THERMISTOR_3_ADV_L2 = 158, /**< Thermistor Sensor 3 Advanced Level 2 */ |
seanwilson10 | 0:76fed7dd9235 | 1188 | ADISENSE_CORE_SENSOR_TYPE_SENSOR_THERMISTOR_4_ADV_L2 = 159, /**< Thermistor Sensor 4 Advanced Level 2 */ |
seanwilson10 | 0:76fed7dd9235 | 1189 | ADISENSE_CORE_SENSOR_TYPE_SENSOR_BRIDGE_4W_1_DEF_L2 = 160, /**< Bridge 4 Wire Sensor 1 Defined Level 2 */ |
seanwilson10 | 0:76fed7dd9235 | 1190 | ADISENSE_CORE_SENSOR_TYPE_SENSOR_BRIDGE_4W_2_DEF_L2 = 161, /**< Bridge 4 Wire Sensor 2 Defined Level 2 */ |
seanwilson10 | 0:76fed7dd9235 | 1191 | ADISENSE_CORE_SENSOR_TYPE_SENSOR_BRIDGE_4W_3_DEF_L2 = 162, /**< Bridge 4 Wire Sensor 3 Defined Level 2 */ |
seanwilson10 | 0:76fed7dd9235 | 1192 | ADISENSE_CORE_SENSOR_TYPE_SENSOR_BRIDGE_4W_4_DEF_L2 = 163, /**< Bridge 4 Wire Sensor 4 Defined Level 2 */ |
seanwilson10 | 0:76fed7dd9235 | 1193 | ADISENSE_CORE_SENSOR_TYPE_SENSOR_BRIDGE_4W_1_ADV_L2 = 176, /**< Bridge 4 Wire Sensor 1 Advanced Level 2 */ |
seanwilson10 | 0:76fed7dd9235 | 1194 | ADISENSE_CORE_SENSOR_TYPE_SENSOR_BRIDGE_4W_2_ADV_L2 = 177, /**< Bridge 4 Wire Sensor 2 Advanced Level 2 */ |
seanwilson10 | 0:76fed7dd9235 | 1195 | ADISENSE_CORE_SENSOR_TYPE_SENSOR_BRIDGE_4W_3_ADV_L2 = 178, /**< Bridge 4 Wire Sensor 2 Advanced Level 2 */ |
seanwilson10 | 0:76fed7dd9235 | 1196 | ADISENSE_CORE_SENSOR_TYPE_SENSOR_BRIDGE_4W_4_ADV_L2 = 179, /**< Bridge 4 Wire Sensor 2 Advanced Level 2 */ |
seanwilson10 | 0:76fed7dd9235 | 1197 | ADISENSE_CORE_SENSOR_TYPE_SENSOR_BRIDGE_6W_1_DEF_L2 = 192, /**< Bridge 6 Wire Sensor 1 Defined Level 2 */ |
seanwilson10 | 0:76fed7dd9235 | 1198 | ADISENSE_CORE_SENSOR_TYPE_SENSOR_BRIDGE_6W_2_DEF_L2 = 193, /**< Bridge 6 Wire Sensor 2 Defined Level 2 */ |
seanwilson10 | 0:76fed7dd9235 | 1199 | ADISENSE_CORE_SENSOR_TYPE_SENSOR_BRIDGE_6W_3_DEF_L2 = 194, /**< Bridge 6 Wire Sensor 3 Defined Level 2 */ |
seanwilson10 | 0:76fed7dd9235 | 1200 | ADISENSE_CORE_SENSOR_TYPE_SENSOR_BRIDGE_6W_4_DEF_L2 = 195, /**< Bridge 6 Wire Sensor 4 Defined Level 2 */ |
seanwilson10 | 0:76fed7dd9235 | 1201 | ADISENSE_CORE_SENSOR_TYPE_SENSOR_BRIDGE_6W_1_ADV_L2 = 208, /**< Bridge 6 Wire Sensor 1 Advanced Level 2 */ |
seanwilson10 | 0:76fed7dd9235 | 1202 | ADISENSE_CORE_SENSOR_TYPE_SENSOR_BRIDGE_6W_2_ADV_L2 = 209, /**< Bridge 6 Wire Sensor 2 Advanced Level 2 */ |
seanwilson10 | 0:76fed7dd9235 | 1203 | ADISENSE_CORE_SENSOR_TYPE_SENSOR_BRIDGE_6W_3_ADV_L2 = 210, /**< Bridge 6 Wire Sensor 3 Advanced Level 2 */ |
seanwilson10 | 0:76fed7dd9235 | 1204 | ADISENSE_CORE_SENSOR_TYPE_SENSOR_BRIDGE_6W_4_ADV_L2 = 211, /**< Bridge 6 Wire Sensor 4 Advanced Level 2 */ |
seanwilson10 | 0:76fed7dd9235 | 1205 | ADISENSE_CORE_SENSOR_TYPE_SENSOR_VOLTAGE = 256, /**< Voltage Input */ |
seanwilson10 | 0:76fed7dd9235 | 1206 | ADISENSE_CORE_SENSOR_TYPE_SENSOR_VOLTAGE_PRESSURE_HONEYWELL_TRUSTABILITY = 272, /**< Voltage Output Pressure Sensor 1 */ |
seanwilson10 | 0:76fed7dd9235 | 1207 | ADISENSE_CORE_SENSOR_TYPE_SENSOR_VOLTAGE_PRESSURE_AMPHENOL_NPA300X = 273, /**< Voltage Output Pressure Sensor 2 */ |
seanwilson10 | 0:76fed7dd9235 | 1208 | ADISENSE_CORE_SENSOR_TYPE_SENSOR_VOLTAGE_PRESSURE_3_DEF = 274, /**< Voltage Output Pressure Sensor 3 */ |
seanwilson10 | 0:76fed7dd9235 | 1209 | ADISENSE_CORE_SENSOR_TYPE_SENSOR_CURRENT = 384, /**< Current Input */ |
seanwilson10 | 0:76fed7dd9235 | 1210 | ADISENSE_CORE_SENSOR_TYPE_SENSOR_CURRENT_PRESSURE_HONEYWELL_PX2 = 385, /**< Current Output Pressure Sensor 1 */ |
seanwilson10 | 0:76fed7dd9235 | 1211 | ADISENSE_CORE_SENSOR_TYPE_SENSOR_CURRENT_PRESSURE_2 = 386, /**< Current Output Pressure Sensor 2 */ |
seanwilson10 | 0:76fed7dd9235 | 1212 | ADISENSE_CORE_SENSOR_TYPE_CUSTOM1 = 512, /**< Custom1 */ |
seanwilson10 | 0:76fed7dd9235 | 1213 | ADISENSE_CORE_SENSOR_TYPE_SENSOR_I2C_PRESSURE_1 = 2048, /**< I2C Pressure Sensor 1 */ |
seanwilson10 | 0:76fed7dd9235 | 1214 | ADISENSE_CORE_SENSOR_TYPE_SENSOR_I2C_PRESSURE_2 = 2049, /**< I2C Pressure Sensor 2 */ |
seanwilson10 | 0:76fed7dd9235 | 1215 | ADISENSE_CORE_SENSOR_TYPE_SENSOR_I2C_HUMIDITY_HONEYWELL_HUMIDICON = 2112, /**< I2C Humidity Sensor 1 */ |
seanwilson10 | 0:76fed7dd9235 | 1216 | ADISENSE_CORE_SENSOR_TYPE_SENSOR_I2C_HUMIDITY_SENSIRION_SHT3X = 2113, /**< I2C Humidity Sensor 2 */ |
seanwilson10 | 0:76fed7dd9235 | 1217 | ADISENSE_CORE_SENSOR_TYPE_SENSOR_SPI_PRESSURE_HONEYWELL_TRUSTABILITY = 3072, /**< SPI Pressure Sensor 1 */ |
seanwilson10 | 0:76fed7dd9235 | 1218 | ADISENSE_CORE_SENSOR_TYPE_SENSOR_SPI_PRESSURE_2 = 3073, /**< SPI Pressure Sensor 2 */ |
seanwilson10 | 0:76fed7dd9235 | 1219 | ADISENSE_CORE_SENSOR_TYPE_SENSOR_SPI_HUMIDITY_1 = 3136, /**< SPI Humidity Sensor Type 1 */ |
seanwilson10 | 0:76fed7dd9235 | 1220 | ADISENSE_CORE_SENSOR_TYPE_SENSOR_SPI_HUMIDITY_2 = 3137, /**< SPI Humidity Sensor Type 2 */ |
seanwilson10 | 0:76fed7dd9235 | 1221 | ADISENSE_CORE_SENSOR_TYPE_SENSOR_SPI_ACCELEROMETER_1 = 3200, /**< SPI Accelerometer Sensor Type 1 3-Axis */ |
seanwilson10 | 0:76fed7dd9235 | 1222 | ADISENSE_CORE_SENSOR_TYPE_SENSOR_SPI_ACCELEROMETER_2 = 3201 /**< SPI Accelerometer Sensor Type 2 3-Axis */ |
seanwilson10 | 0:76fed7dd9235 | 1223 | } ADI_ADISENSE_CORE_Sensor_Type_Sensor_Type; |
seanwilson10 | 0:76fed7dd9235 | 1224 | |
seanwilson10 | 0:76fed7dd9235 | 1225 | |
seanwilson10 | 0:76fed7dd9235 | 1226 | /* ========================================================================== |
seanwilson10 | 0:76fed7dd9235 | 1227 | *! \struct ADI_ADISENSE_CORE_Sensor_Type_Struct |
seanwilson10 | 0:76fed7dd9235 | 1228 | *! \brief Sensor Select Register bit field structure |
seanwilson10 | 0:76fed7dd9235 | 1229 | * ========================================================================== */ |
seanwilson10 | 0:76fed7dd9235 | 1230 | typedef struct _ADI_ADISENSE_CORE_Sensor_Type_t { |
seanwilson10 | 0:76fed7dd9235 | 1231 | union { |
seanwilson10 | 0:76fed7dd9235 | 1232 | struct { |
seanwilson10 | 0:76fed7dd9235 | 1233 | uint16_t Sensor_Type : 12; /**< Sensor Type */ |
seanwilson10 | 0:76fed7dd9235 | 1234 | uint16_t reserved12 : 4; |
seanwilson10 | 0:76fed7dd9235 | 1235 | }; |
seanwilson10 | 0:76fed7dd9235 | 1236 | uint16_t VALUE16; |
seanwilson10 | 0:76fed7dd9235 | 1237 | }; |
seanwilson10 | 0:76fed7dd9235 | 1238 | } ADI_ADISENSE_CORE_Sensor_Type_t; |
seanwilson10 | 0:76fed7dd9235 | 1239 | |
seanwilson10 | 0:76fed7dd9235 | 1240 | /*@}*/ |
seanwilson10 | 0:76fed7dd9235 | 1241 | |
seanwilson10 | 0:76fed7dd9235 | 1242 | /** @defgroup Sensor_Details Sensor Details (Sensor_Details) Register |
seanwilson10 | 0:76fed7dd9235 | 1243 | * Sensor Details (Sensor_Details) Register. |
seanwilson10 | 0:76fed7dd9235 | 1244 | * @{ |
seanwilson10 | 0:76fed7dd9235 | 1245 | */ |
seanwilson10 | 0:76fed7dd9235 | 1246 | |
seanwilson10 | 0:76fed7dd9235 | 1247 | /* ========================================================================= |
seanwilson10 | 0:76fed7dd9235 | 1248 | *! \enum ADI_ADISENSE_CORE_Sensor_Details_Measurement_Units |
seanwilson10 | 0:76fed7dd9235 | 1249 | *! \brief Units of Sensor Measurement (Measurement_Units) Enumerations |
seanwilson10 | 0:76fed7dd9235 | 1250 | * ========================================================================= */ |
seanwilson10 | 0:76fed7dd9235 | 1251 | typedef enum |
seanwilson10 | 0:76fed7dd9235 | 1252 | { |
seanwilson10 | 0:76fed7dd9235 | 1253 | ADISENSE_CORE_SENSOR_DETAILS_UNITS_DEGC = 0, /**< Degrees C */ |
seanwilson10 | 0:76fed7dd9235 | 1254 | ADISENSE_CORE_SENSOR_DETAILS_UNITS_DEGF = 1 /**< Degrees F */ |
seanwilson10 | 0:76fed7dd9235 | 1255 | } ADI_ADISENSE_CORE_Sensor_Details_Measurement_Units; |
seanwilson10 | 0:76fed7dd9235 | 1256 | |
seanwilson10 | 0:76fed7dd9235 | 1257 | |
seanwilson10 | 0:76fed7dd9235 | 1258 | /* ========================================================================= |
seanwilson10 | 0:76fed7dd9235 | 1259 | *! \enum ADI_ADISENSE_CORE_Sensor_Details_Reference_Select |
seanwilson10 | 0:76fed7dd9235 | 1260 | *! \brief Reference Selection (Reference_Select) Enumerations |
seanwilson10 | 0:76fed7dd9235 | 1261 | * ========================================================================= */ |
seanwilson10 | 0:76fed7dd9235 | 1262 | typedef enum |
seanwilson10 | 0:76fed7dd9235 | 1263 | { |
seanwilson10 | 0:76fed7dd9235 | 1264 | ADISENSE_CORE_SENSOR_DETAILS_REF_INT = 0, /**< Internal Reference */ |
seanwilson10 | 0:76fed7dd9235 | 1265 | ADISENSE_CORE_SENSOR_DETAILS_REF_AVDD = 1, /**< AVDD */ |
seanwilson10 | 0:76fed7dd9235 | 1266 | ADISENSE_CORE_SENSOR_DETAILS_REF_VEXT1 = 2, /**< External Voltage on Refin1 */ |
seanwilson10 | 0:76fed7dd9235 | 1267 | ADISENSE_CORE_SENSOR_DETAILS_REF_VEXT2 = 3, /**< External Voltage on Refin2 */ |
seanwilson10 | 0:76fed7dd9235 | 1268 | ADISENSE_CORE_SENSOR_DETAILS_REF_RINT1 = 4, /**< Internal Resistor1 */ |
seanwilson10 | 0:76fed7dd9235 | 1269 | ADISENSE_CORE_SENSOR_DETAILS_REF_RINT2 = 5, /**< Internal Resistor2 */ |
seanwilson10 | 0:76fed7dd9235 | 1270 | ADISENSE_CORE_SENSOR_DETAILS_REF_REXT1 = 6, /**< External Resistor on Refin1 */ |
seanwilson10 | 0:76fed7dd9235 | 1271 | ADISENSE_CORE_SENSOR_DETAILS_REF_REXT2 = 7, /**< External Resistor on Refin2 */ |
seanwilson10 | 0:76fed7dd9235 | 1272 | ADISENSE_CORE_SENSOR_DETAILS_REF_EXC = 8 /**< Bridge Excitation Voltage */ |
seanwilson10 | 0:76fed7dd9235 | 1273 | } ADI_ADISENSE_CORE_Sensor_Details_Reference_Select; |
seanwilson10 | 0:76fed7dd9235 | 1274 | |
seanwilson10 | 0:76fed7dd9235 | 1275 | |
seanwilson10 | 0:76fed7dd9235 | 1276 | /* ========================================================================= |
seanwilson10 | 0:76fed7dd9235 | 1277 | *! \enum ADI_ADISENSE_CORE_Sensor_Details_PGA_Gain |
seanwilson10 | 0:76fed7dd9235 | 1278 | *! \brief PGA Gain (PGA_Gain) Enumerations |
seanwilson10 | 0:76fed7dd9235 | 1279 | * ========================================================================= */ |
seanwilson10 | 0:76fed7dd9235 | 1280 | typedef enum |
seanwilson10 | 0:76fed7dd9235 | 1281 | { |
seanwilson10 | 0:76fed7dd9235 | 1282 | ADISENSE_CORE_SENSOR_DETAILS_PGA_GAIN_1 = 0, /**< Gain of 1 */ |
seanwilson10 | 0:76fed7dd9235 | 1283 | ADISENSE_CORE_SENSOR_DETAILS_PGA_GAIN_2 = 1, /**< Gain of 2 */ |
seanwilson10 | 0:76fed7dd9235 | 1284 | ADISENSE_CORE_SENSOR_DETAILS_PGA_GAIN_4 = 2, /**< Gain of 4 */ |
seanwilson10 | 0:76fed7dd9235 | 1285 | ADISENSE_CORE_SENSOR_DETAILS_PGA_GAIN_8 = 3, /**< Gain of 8 */ |
seanwilson10 | 0:76fed7dd9235 | 1286 | ADISENSE_CORE_SENSOR_DETAILS_PGA_GAIN_16 = 4, /**< Gain of 16 */ |
seanwilson10 | 0:76fed7dd9235 | 1287 | ADISENSE_CORE_SENSOR_DETAILS_PGA_GAIN_32 = 5, /**< Gain of 32 */ |
seanwilson10 | 0:76fed7dd9235 | 1288 | ADISENSE_CORE_SENSOR_DETAILS_PGA_GAIN_64 = 6, /**< Gain of 64 */ |
seanwilson10 | 0:76fed7dd9235 | 1289 | ADISENSE_CORE_SENSOR_DETAILS_PGA_GAIN_128 = 7 /**< Gain of 128 */ |
seanwilson10 | 0:76fed7dd9235 | 1290 | } ADI_ADISENSE_CORE_Sensor_Details_PGA_Gain; |
seanwilson10 | 0:76fed7dd9235 | 1291 | |
seanwilson10 | 0:76fed7dd9235 | 1292 | |
seanwilson10 | 0:76fed7dd9235 | 1293 | /* ========================================================================== |
seanwilson10 | 0:76fed7dd9235 | 1294 | *! \struct ADI_ADISENSE_CORE_Sensor_Details_Struct |
seanwilson10 | 0:76fed7dd9235 | 1295 | *! \brief Sensor Details Register bit field structure |
seanwilson10 | 0:76fed7dd9235 | 1296 | * ========================================================================== */ |
seanwilson10 | 0:76fed7dd9235 | 1297 | typedef struct _ADI_ADISENSE_CORE_Sensor_Details_t { |
seanwilson10 | 0:76fed7dd9235 | 1298 | union { |
seanwilson10 | 0:76fed7dd9235 | 1299 | struct { |
seanwilson10 | 0:76fed7dd9235 | 1300 | uint32_t Measurement_Units : 4; /**< Units of Sensor Measurement */ |
seanwilson10 | 0:76fed7dd9235 | 1301 | uint32_t Compensation_Channel : 4; /**< Indicates Which Channel is Used to Compensate Sensor Result */ |
seanwilson10 | 0:76fed7dd9235 | 1302 | uint32_t Compensation_Channel2 : 4; /**< Indicates Channel for Second Term of Compensation */ |
seanwilson10 | 0:76fed7dd9235 | 1303 | uint32_t Compensation_Channel3 : 4; /**< Indicates Channel for Third Term of Compensation */ |
seanwilson10 | 0:76fed7dd9235 | 1304 | uint32_t reserved16 : 1; |
seanwilson10 | 0:76fed7dd9235 | 1305 | uint32_t Do_Not_Publish : 1; /**< Do Not Publish Channel Result */ |
seanwilson10 | 0:76fed7dd9235 | 1306 | uint32_t Reference_Buffer_Disable : 1; /**< Enable or Disable ADC Reference Buffer */ |
seanwilson10 | 0:76fed7dd9235 | 1307 | uint32_t Vbias : 1; /**< Controls ADC Vbias Output */ |
seanwilson10 | 0:76fed7dd9235 | 1308 | uint32_t Reference_Select : 4; /**< Reference Selection */ |
seanwilson10 | 0:76fed7dd9235 | 1309 | uint32_t PGA_Gain : 3; /**< PGA Gain */ |
seanwilson10 | 0:76fed7dd9235 | 1310 | uint32_t reserved27 : 1; |
seanwilson10 | 0:76fed7dd9235 | 1311 | uint32_t Averaging : 3; /**< Number of ADC Results to Average */ |
seanwilson10 | 0:76fed7dd9235 | 1312 | uint32_t reserved31 : 1; |
seanwilson10 | 0:76fed7dd9235 | 1313 | }; |
seanwilson10 | 0:76fed7dd9235 | 1314 | uint32_t VALUE32; |
seanwilson10 | 0:76fed7dd9235 | 1315 | }; |
seanwilson10 | 0:76fed7dd9235 | 1316 | } ADI_ADISENSE_CORE_Sensor_Details_t; |
seanwilson10 | 0:76fed7dd9235 | 1317 | |
seanwilson10 | 0:76fed7dd9235 | 1318 | /*@}*/ |
seanwilson10 | 0:76fed7dd9235 | 1319 | |
seanwilson10 | 0:76fed7dd9235 | 1320 | /** @defgroup Channel_Excitation Excitation Current (Channel_Excitation) Register |
seanwilson10 | 0:76fed7dd9235 | 1321 | * Excitation Current (Channel_Excitation) Register. |
seanwilson10 | 0:76fed7dd9235 | 1322 | * @{ |
seanwilson10 | 0:76fed7dd9235 | 1323 | */ |
seanwilson10 | 0:76fed7dd9235 | 1324 | |
seanwilson10 | 0:76fed7dd9235 | 1325 | /* ========================================================================= |
seanwilson10 | 0:76fed7dd9235 | 1326 | *! \enum ADI_ADISENSE_CORE_Channel_Excitation_IOUT_Excitation_Current |
seanwilson10 | 0:76fed7dd9235 | 1327 | *! \brief Current Source Value (IOUT_Excitation_Current) Enumerations |
seanwilson10 | 0:76fed7dd9235 | 1328 | * ========================================================================= */ |
seanwilson10 | 0:76fed7dd9235 | 1329 | typedef enum |
seanwilson10 | 0:76fed7dd9235 | 1330 | { |
seanwilson10 | 0:76fed7dd9235 | 1331 | ADISENSE_CORE_CHANNEL_EXCITATION_IEXC_OFF = 0, /**< Disabled */ |
seanwilson10 | 0:76fed7dd9235 | 1332 | ADISENSE_CORE_CHANNEL_EXCITATION_IEXC_50UA = 1, /**< 50 \mu;A */ |
seanwilson10 | 0:76fed7dd9235 | 1333 | ADISENSE_CORE_CHANNEL_EXCITATION_IEXC_100UA = 2, /**< 100 \mu;A */ |
seanwilson10 | 0:76fed7dd9235 | 1334 | ADISENSE_CORE_CHANNEL_EXCITATION_IEXC_250UA = 3, /**< 250 \mu;A */ |
seanwilson10 | 0:76fed7dd9235 | 1335 | ADISENSE_CORE_CHANNEL_EXCITATION_IEXC_500UA = 4, /**< 500 \mu;A */ |
seanwilson10 | 0:76fed7dd9235 | 1336 | ADISENSE_CORE_CHANNEL_EXCITATION_IEXC_750UA = 5, /**< 750 \mu;A */ |
seanwilson10 | 0:76fed7dd9235 | 1337 | ADISENSE_CORE_CHANNEL_EXCITATION_IEXC_1000UA = 6, /**< 1000 \mu;A */ |
seanwilson10 | 0:76fed7dd9235 | 1338 | ADISENSE_CORE_CHANNEL_EXCITATION_IEXC_1000UA_2 = 7 /**< 1000 \mu;A */ |
seanwilson10 | 0:76fed7dd9235 | 1339 | } ADI_ADISENSE_CORE_Channel_Excitation_IOUT_Excitation_Current; |
seanwilson10 | 0:76fed7dd9235 | 1340 | |
seanwilson10 | 0:76fed7dd9235 | 1341 | |
seanwilson10 | 0:76fed7dd9235 | 1342 | /* ========================================================================== |
seanwilson10 | 0:76fed7dd9235 | 1343 | *! \struct ADI_ADISENSE_CORE_Channel_Excitation_Struct |
seanwilson10 | 0:76fed7dd9235 | 1344 | *! \brief Excitation Current Register bit field structure |
seanwilson10 | 0:76fed7dd9235 | 1345 | * ========================================================================== */ |
seanwilson10 | 0:76fed7dd9235 | 1346 | typedef struct _ADI_ADISENSE_CORE_Channel_Excitation_t { |
seanwilson10 | 0:76fed7dd9235 | 1347 | union { |
seanwilson10 | 0:76fed7dd9235 | 1348 | struct { |
seanwilson10 | 0:76fed7dd9235 | 1349 | uint8_t IOUT_Excitation_Current : 3; /**< Current Source Value */ |
seanwilson10 | 0:76fed7dd9235 | 1350 | uint8_t IOUT0_Disable : 1; /**< Disable First Current Source */ |
seanwilson10 | 0:76fed7dd9235 | 1351 | uint8_t IOUT1_Disable : 1; /**< Disable Second Current Source */ |
seanwilson10 | 0:76fed7dd9235 | 1352 | uint8_t reserved5 : 1; |
seanwilson10 | 0:76fed7dd9235 | 1353 | uint8_t IOUT_Static_Swap_3Wire : 1; /**< Indicates 3-Wire Excitation Currents Should Be Swapped */ |
seanwilson10 | 0:76fed7dd9235 | 1354 | uint8_t IOUT_Dont_Swap_3Wire : 1; /**< Indicates 3-Wire Excitation Currents Should Not Be Swapped */ |
seanwilson10 | 0:76fed7dd9235 | 1355 | }; |
seanwilson10 | 0:76fed7dd9235 | 1356 | uint8_t VALUE8; |
seanwilson10 | 0:76fed7dd9235 | 1357 | }; |
seanwilson10 | 0:76fed7dd9235 | 1358 | } ADI_ADISENSE_CORE_Channel_Excitation_t; |
seanwilson10 | 0:76fed7dd9235 | 1359 | |
seanwilson10 | 0:76fed7dd9235 | 1360 | /*@}*/ |
seanwilson10 | 0:76fed7dd9235 | 1361 | |
seanwilson10 | 0:76fed7dd9235 | 1362 | /** @defgroup Settling_Time Settling Time (Settling_Time) Register |
seanwilson10 | 0:76fed7dd9235 | 1363 | * Settling Time (Settling_Time) Register. |
seanwilson10 | 0:76fed7dd9235 | 1364 | * @{ |
seanwilson10 | 0:76fed7dd9235 | 1365 | */ |
seanwilson10 | 0:76fed7dd9235 | 1366 | |
seanwilson10 | 0:76fed7dd9235 | 1367 | /* ========================================================================== |
seanwilson10 | 0:76fed7dd9235 | 1368 | *! \struct ADI_ADISENSE_CORE_Settling_Time_Struct |
seanwilson10 | 0:76fed7dd9235 | 1369 | *! \brief Settling Time Register bit field structure |
seanwilson10 | 0:76fed7dd9235 | 1370 | * ========================================================================== */ |
seanwilson10 | 0:76fed7dd9235 | 1371 | typedef struct _ADI_ADISENSE_CORE_Settling_Time_t { |
seanwilson10 | 0:76fed7dd9235 | 1372 | union { |
seanwilson10 | 0:76fed7dd9235 | 1373 | struct { |
seanwilson10 | 0:76fed7dd9235 | 1374 | uint16_t Settling_Time : 16; /**< Settling Time to Allow When Switching to Channel */ |
seanwilson10 | 0:76fed7dd9235 | 1375 | }; |
seanwilson10 | 0:76fed7dd9235 | 1376 | uint16_t VALUE16; |
seanwilson10 | 0:76fed7dd9235 | 1377 | }; |
seanwilson10 | 0:76fed7dd9235 | 1378 | } ADI_ADISENSE_CORE_Settling_Time_t; |
seanwilson10 | 0:76fed7dd9235 | 1379 | |
seanwilson10 | 0:76fed7dd9235 | 1380 | /*@}*/ |
seanwilson10 | 0:76fed7dd9235 | 1381 | |
seanwilson10 | 0:76fed7dd9235 | 1382 | /** @defgroup Filter_Select ADC Digital Filter Selection (Filter_Select) Register |
seanwilson10 | 0:76fed7dd9235 | 1383 | * ADC Digital Filter Selection (Filter_Select) Register. |
seanwilson10 | 0:76fed7dd9235 | 1384 | * @{ |
seanwilson10 | 0:76fed7dd9235 | 1385 | */ |
seanwilson10 | 0:76fed7dd9235 | 1386 | |
seanwilson10 | 0:76fed7dd9235 | 1387 | /* ========================================================================= |
seanwilson10 | 0:76fed7dd9235 | 1388 | *! \enum ADI_ADISENSE_CORE_Filter_Select_ADC_Filter_Type |
seanwilson10 | 0:76fed7dd9235 | 1389 | *! \brief ADC Digital Filter Type (ADC_Filter_Type) Enumerations |
seanwilson10 | 0:76fed7dd9235 | 1390 | * ========================================================================= */ |
seanwilson10 | 0:76fed7dd9235 | 1391 | typedef enum |
seanwilson10 | 0:76fed7dd9235 | 1392 | { |
seanwilson10 | 0:76fed7dd9235 | 1393 | ADISENSE_CORE_FILTER_SELECT_FILTER_FIR_25SPS = 0, /**< FIR Filter 25 SPS */ |
seanwilson10 | 0:76fed7dd9235 | 1394 | ADISENSE_CORE_FILTER_SELECT_FILTER_FIR_20SPS = 1, /**< FIR Filter 20 SPS */ |
seanwilson10 | 0:76fed7dd9235 | 1395 | ADISENSE_CORE_FILTER_SELECT_FILTER_SINC4 = 2, /**< Sinc4 Filter */ |
seanwilson10 | 0:76fed7dd9235 | 1396 | ADISENSE_CORE_FILTER_SELECT_FILTER_TBD = 3 /**< TBD Filter */ |
seanwilson10 | 0:76fed7dd9235 | 1397 | } ADI_ADISENSE_CORE_Filter_Select_ADC_Filter_Type; |
seanwilson10 | 0:76fed7dd9235 | 1398 | |
seanwilson10 | 0:76fed7dd9235 | 1399 | |
seanwilson10 | 0:76fed7dd9235 | 1400 | /* ========================================================================== |
seanwilson10 | 0:76fed7dd9235 | 1401 | *! \struct ADI_ADISENSE_CORE_Filter_Select_Struct |
seanwilson10 | 0:76fed7dd9235 | 1402 | *! \brief ADC Digital Filter Selection Register bit field structure |
seanwilson10 | 0:76fed7dd9235 | 1403 | * ========================================================================== */ |
seanwilson10 | 0:76fed7dd9235 | 1404 | typedef struct _ADI_ADISENSE_CORE_Filter_Select_t { |
seanwilson10 | 0:76fed7dd9235 | 1405 | union { |
seanwilson10 | 0:76fed7dd9235 | 1406 | struct { |
seanwilson10 | 0:76fed7dd9235 | 1407 | uint32_t ADC_FS : 11; /**< ADC Digital Filter Select */ |
seanwilson10 | 0:76fed7dd9235 | 1408 | uint32_t ADC_Filter_Type : 5; /**< ADC Digital Filter Type */ |
seanwilson10 | 0:76fed7dd9235 | 1409 | uint32_t reserved16 : 16; |
seanwilson10 | 0:76fed7dd9235 | 1410 | }; |
seanwilson10 | 0:76fed7dd9235 | 1411 | uint32_t VALUE32; |
seanwilson10 | 0:76fed7dd9235 | 1412 | }; |
seanwilson10 | 0:76fed7dd9235 | 1413 | } ADI_ADISENSE_CORE_Filter_Select_t; |
seanwilson10 | 0:76fed7dd9235 | 1414 | |
seanwilson10 | 0:76fed7dd9235 | 1415 | /*@}*/ |
seanwilson10 | 0:76fed7dd9235 | 1416 | |
seanwilson10 | 0:76fed7dd9235 | 1417 | /** @defgroup High_Threshold_Limit High Threshold (High_Threshold_Limit) Register |
seanwilson10 | 0:76fed7dd9235 | 1418 | * High Threshold (High_Threshold_Limit) Register. |
seanwilson10 | 0:76fed7dd9235 | 1419 | * @{ |
seanwilson10 | 0:76fed7dd9235 | 1420 | */ |
seanwilson10 | 0:76fed7dd9235 | 1421 | |
seanwilson10 | 0:76fed7dd9235 | 1422 | /* ========================================================================== |
seanwilson10 | 0:76fed7dd9235 | 1423 | *! \struct ADI_ADISENSE_CORE_High_Threshold_Limit_Struct |
seanwilson10 | 0:76fed7dd9235 | 1424 | *! \brief High Threshold Register bit field structure |
seanwilson10 | 0:76fed7dd9235 | 1425 | * ========================================================================== */ |
seanwilson10 | 0:76fed7dd9235 | 1426 | typedef struct _ADI_ADISENSE_CORE_High_Threshold_Limit_t { |
seanwilson10 | 0:76fed7dd9235 | 1427 | union { |
seanwilson10 | 0:76fed7dd9235 | 1428 | struct { |
seanwilson10 | 0:76fed7dd9235 | 1429 | float High_Threshold; /**< Upper Limit for Sensor Alert Comparison */ |
seanwilson10 | 0:76fed7dd9235 | 1430 | }; |
seanwilson10 | 0:76fed7dd9235 | 1431 | float VALUE32; |
seanwilson10 | 0:76fed7dd9235 | 1432 | }; |
seanwilson10 | 0:76fed7dd9235 | 1433 | } ADI_ADISENSE_CORE_High_Threshold_Limit_t; |
seanwilson10 | 0:76fed7dd9235 | 1434 | |
seanwilson10 | 0:76fed7dd9235 | 1435 | /*@}*/ |
seanwilson10 | 0:76fed7dd9235 | 1436 | |
seanwilson10 | 0:76fed7dd9235 | 1437 | /** @defgroup Low_Threshold_Limit Low Threshold (Low_Threshold_Limit) Register |
seanwilson10 | 0:76fed7dd9235 | 1438 | * Low Threshold (Low_Threshold_Limit) Register. |
seanwilson10 | 0:76fed7dd9235 | 1439 | * @{ |
seanwilson10 | 0:76fed7dd9235 | 1440 | */ |
seanwilson10 | 0:76fed7dd9235 | 1441 | |
seanwilson10 | 0:76fed7dd9235 | 1442 | /* ========================================================================== |
seanwilson10 | 0:76fed7dd9235 | 1443 | *! \struct ADI_ADISENSE_CORE_Low_Threshold_Limit_Struct |
seanwilson10 | 0:76fed7dd9235 | 1444 | *! \brief Low Threshold Register bit field structure |
seanwilson10 | 0:76fed7dd9235 | 1445 | * ========================================================================== */ |
seanwilson10 | 0:76fed7dd9235 | 1446 | typedef struct _ADI_ADISENSE_CORE_Low_Threshold_Limit_t { |
seanwilson10 | 0:76fed7dd9235 | 1447 | union { |
seanwilson10 | 0:76fed7dd9235 | 1448 | struct { |
seanwilson10 | 0:76fed7dd9235 | 1449 | float Low_Threshold; /**< Lower Limit for Sensor Alert Comparison */ |
seanwilson10 | 0:76fed7dd9235 | 1450 | }; |
seanwilson10 | 0:76fed7dd9235 | 1451 | float VALUE32; |
seanwilson10 | 0:76fed7dd9235 | 1452 | }; |
seanwilson10 | 0:76fed7dd9235 | 1453 | } ADI_ADISENSE_CORE_Low_Threshold_Limit_t; |
seanwilson10 | 0:76fed7dd9235 | 1454 | |
seanwilson10 | 0:76fed7dd9235 | 1455 | /*@}*/ |
seanwilson10 | 0:76fed7dd9235 | 1456 | |
seanwilson10 | 0:76fed7dd9235 | 1457 | /** @defgroup Sensor_Offset Sensor Offset Adjustment (Sensor_Offset) Register |
seanwilson10 | 0:76fed7dd9235 | 1458 | * Sensor Offset Adjustment (Sensor_Offset) Register. |
seanwilson10 | 0:76fed7dd9235 | 1459 | * @{ |
seanwilson10 | 0:76fed7dd9235 | 1460 | */ |
seanwilson10 | 0:76fed7dd9235 | 1461 | |
seanwilson10 | 0:76fed7dd9235 | 1462 | /* ========================================================================== |
seanwilson10 | 0:76fed7dd9235 | 1463 | *! \struct ADI_ADISENSE_CORE_Sensor_Offset_Struct |
seanwilson10 | 0:76fed7dd9235 | 1464 | *! \brief Sensor Offset Adjustment Register bit field structure |
seanwilson10 | 0:76fed7dd9235 | 1465 | * ========================================================================== */ |
seanwilson10 | 0:76fed7dd9235 | 1466 | typedef struct _ADI_ADISENSE_CORE_Sensor_Offset_t { |
seanwilson10 | 0:76fed7dd9235 | 1467 | union { |
seanwilson10 | 0:76fed7dd9235 | 1468 | struct { |
seanwilson10 | 0:76fed7dd9235 | 1469 | float Sensor_Offset; /**< Sensor Offset Adjustment */ |
seanwilson10 | 0:76fed7dd9235 | 1470 | }; |
seanwilson10 | 0:76fed7dd9235 | 1471 | float VALUE32; |
seanwilson10 | 0:76fed7dd9235 | 1472 | }; |
seanwilson10 | 0:76fed7dd9235 | 1473 | } ADI_ADISENSE_CORE_Sensor_Offset_t; |
seanwilson10 | 0:76fed7dd9235 | 1474 | |
seanwilson10 | 0:76fed7dd9235 | 1475 | /*@}*/ |
seanwilson10 | 0:76fed7dd9235 | 1476 | |
seanwilson10 | 0:76fed7dd9235 | 1477 | /** @defgroup Sensor_Gain Sensor Gain Adjustment (Sensor_Gain) Register |
seanwilson10 | 0:76fed7dd9235 | 1478 | * Sensor Gain Adjustment (Sensor_Gain) Register. |
seanwilson10 | 0:76fed7dd9235 | 1479 | * @{ |
seanwilson10 | 0:76fed7dd9235 | 1480 | */ |
seanwilson10 | 0:76fed7dd9235 | 1481 | |
seanwilson10 | 0:76fed7dd9235 | 1482 | /* ========================================================================== |
seanwilson10 | 0:76fed7dd9235 | 1483 | *! \struct ADI_ADISENSE_CORE_Sensor_Gain_Struct |
seanwilson10 | 0:76fed7dd9235 | 1484 | *! \brief Sensor Gain Adjustment Register bit field structure |
seanwilson10 | 0:76fed7dd9235 | 1485 | * ========================================================================== */ |
seanwilson10 | 0:76fed7dd9235 | 1486 | typedef struct _ADI_ADISENSE_CORE_Sensor_Gain_t { |
seanwilson10 | 0:76fed7dd9235 | 1487 | union { |
seanwilson10 | 0:76fed7dd9235 | 1488 | struct { |
seanwilson10 | 0:76fed7dd9235 | 1489 | float Sensor_Gain; /**< Sensor Gain Adjustment */ |
seanwilson10 | 0:76fed7dd9235 | 1490 | }; |
seanwilson10 | 0:76fed7dd9235 | 1491 | float VALUE32; |
seanwilson10 | 0:76fed7dd9235 | 1492 | }; |
seanwilson10 | 0:76fed7dd9235 | 1493 | } ADI_ADISENSE_CORE_Sensor_Gain_t; |
seanwilson10 | 0:76fed7dd9235 | 1494 | |
seanwilson10 | 0:76fed7dd9235 | 1495 | /*@}*/ |
seanwilson10 | 0:76fed7dd9235 | 1496 | |
seanwilson10 | 0:76fed7dd9235 | 1497 | /** @defgroup Alert_Code_Ch Per-Channel Detailed Alert-Code Information (Alert_Code_Ch) Register |
seanwilson10 | 0:76fed7dd9235 | 1498 | * Per-Channel Detailed Alert-Code Information (Alert_Code_Ch) Register. |
seanwilson10 | 0:76fed7dd9235 | 1499 | * @{ |
seanwilson10 | 0:76fed7dd9235 | 1500 | */ |
seanwilson10 | 0:76fed7dd9235 | 1501 | |
seanwilson10 | 0:76fed7dd9235 | 1502 | /* ========================================================================== |
seanwilson10 | 0:76fed7dd9235 | 1503 | *! \struct ADI_ADISENSE_CORE_Alert_Code_Ch_Struct |
seanwilson10 | 0:76fed7dd9235 | 1504 | *! \brief Per-Channel Detailed Alert-Code Information Register bit field structure |
seanwilson10 | 0:76fed7dd9235 | 1505 | * ========================================================================== */ |
seanwilson10 | 0:76fed7dd9235 | 1506 | typedef struct _ADI_ADISENSE_CORE_Alert_Code_Ch_t { |
seanwilson10 | 0:76fed7dd9235 | 1507 | union { |
seanwilson10 | 0:76fed7dd9235 | 1508 | struct { |
seanwilson10 | 0:76fed7dd9235 | 1509 | uint16_t Alert_Code_Ch : 16; /**< Per-Channel Code Indicating Type of Alert */ |
seanwilson10 | 0:76fed7dd9235 | 1510 | }; |
seanwilson10 | 0:76fed7dd9235 | 1511 | uint16_t VALUE16; |
seanwilson10 | 0:76fed7dd9235 | 1512 | }; |
seanwilson10 | 0:76fed7dd9235 | 1513 | } ADI_ADISENSE_CORE_Alert_Code_Ch_t; |
seanwilson10 | 0:76fed7dd9235 | 1514 | |
seanwilson10 | 0:76fed7dd9235 | 1515 | /*@}*/ |
seanwilson10 | 0:76fed7dd9235 | 1516 | |
seanwilson10 | 0:76fed7dd9235 | 1517 | /** @defgroup Digital_Sensor_Config Digital Sensor Data Coding (Digital_Sensor_Config) Register |
seanwilson10 | 0:76fed7dd9235 | 1518 | * Digital Sensor Data Coding (Digital_Sensor_Config) Register. |
seanwilson10 | 0:76fed7dd9235 | 1519 | * @{ |
seanwilson10 | 0:76fed7dd9235 | 1520 | */ |
seanwilson10 | 0:76fed7dd9235 | 1521 | |
seanwilson10 | 0:76fed7dd9235 | 1522 | /* ========================================================================= |
seanwilson10 | 0:76fed7dd9235 | 1523 | *! \enum ADI_ADISENSE_CORE_Digital_Sensor_Config_Digital_Sensor_Coding |
seanwilson10 | 0:76fed7dd9235 | 1524 | *! \brief Data Encoding of Sensor Result (Digital_Sensor_Coding) Enumerations |
seanwilson10 | 0:76fed7dd9235 | 1525 | * ========================================================================= */ |
seanwilson10 | 0:76fed7dd9235 | 1526 | typedef enum |
seanwilson10 | 0:76fed7dd9235 | 1527 | { |
seanwilson10 | 0:76fed7dd9235 | 1528 | ADISENSE_CORE_DIGITAL_SENSOR_CONFIG_CODING_NONE = 0, /**< None/Invalid */ |
seanwilson10 | 0:76fed7dd9235 | 1529 | ADISENSE_CORE_DIGITAL_SENSOR_CONFIG_CODING_UNIPOLAR = 1, /**< Unipolar */ |
seanwilson10 | 0:76fed7dd9235 | 1530 | ADISENSE_CORE_DIGITAL_SENSOR_CONFIG_CODING_TWOS_COMPL = 2, /**< Twos Complement */ |
seanwilson10 | 0:76fed7dd9235 | 1531 | ADISENSE_CORE_DIGITAL_SENSOR_CONFIG_CODING_OFFSET_BINARY = 3, /**< Offset Binary */ |
seanwilson10 | 0:76fed7dd9235 | 1532 | } ADI_ADISENSE_CORE_Digital_Sensor_Config_Digital_Sensor_Coding; |
seanwilson10 | 0:76fed7dd9235 | 1533 | |
seanwilson10 | 0:76fed7dd9235 | 1534 | /* ========================================================================== |
seanwilson10 | 0:76fed7dd9235 | 1535 | *! \struct ADI_ADISENSE_CORE_Digital_Sensor_Config_Struct |
seanwilson10 | 0:76fed7dd9235 | 1536 | *! \brief Digital Sensor Data Coding Register bit field structure |
seanwilson10 | 0:76fed7dd9235 | 1537 | * ========================================================================== */ |
seanwilson10 | 0:76fed7dd9235 | 1538 | typedef struct _ADI_ADISENSE_CORE_Digital_Sensor_Config_t { |
seanwilson10 | 0:76fed7dd9235 | 1539 | union { |
seanwilson10 | 0:76fed7dd9235 | 1540 | struct { |
seanwilson10 | 0:76fed7dd9235 | 1541 | uint16_t Digital_Sensor_Coding : 2; /**< Data Encoding of Sensor Result */ |
seanwilson10 | 0:76fed7dd9235 | 1542 | uint16_t Digital_Sensor_LittleEndian : 1; /**< Data Endianness of Sensor Result */ |
seanwilson10 | 0:76fed7dd9235 | 1543 | uint16_t Digital_Sensor_LeftAligned : 1; /**< Data Alignment within the data frame */ |
seanwilson10 | 0:76fed7dd9235 | 1544 | uint16_t Digital_Sensor_Bit_Offset : 4; /**< Data Bit Offset, relative to alignment */ |
seanwilson10 | 0:76fed7dd9235 | 1545 | uint16_t Digital_Sensor_Read_Bytes : 3; /**< Number of bytes to read from the sensor, minus 1 */ |
seanwilson10 | 0:76fed7dd9235 | 1546 | uint16_t Digital_Sensor_Data_Bits : 5; /**< Number of Relevant Data Bits, minus 1 */ |
seanwilson10 | 0:76fed7dd9235 | 1547 | }; |
seanwilson10 | 0:76fed7dd9235 | 1548 | uint16_t VALUE16; |
seanwilson10 | 0:76fed7dd9235 | 1549 | }; |
seanwilson10 | 0:76fed7dd9235 | 1550 | } ADI_ADISENSE_CORE_Digital_Sensor_Config_t; |
seanwilson10 | 0:76fed7dd9235 | 1551 | |
seanwilson10 | 0:76fed7dd9235 | 1552 | /*@}*/ |
seanwilson10 | 0:76fed7dd9235 | 1553 | |
seanwilson10 | 0:76fed7dd9235 | 1554 | /** @defgroup Digital_Sensor_Address Sensor Address (Digital_Sensor_Address) Register |
seanwilson10 | 0:76fed7dd9235 | 1555 | * Sensor Address (Digital_Sensor_Address) Register. |
seanwilson10 | 0:76fed7dd9235 | 1556 | * @{ |
seanwilson10 | 0:76fed7dd9235 | 1557 | */ |
seanwilson10 | 0:76fed7dd9235 | 1558 | |
seanwilson10 | 0:76fed7dd9235 | 1559 | /* ========================================================================== |
seanwilson10 | 0:76fed7dd9235 | 1560 | *! \struct ADI_ADISENSE_CORE_Digital_Sensor_Address_Struct |
seanwilson10 | 0:76fed7dd9235 | 1561 | *! \brief Sensor Address Register bit field structure |
seanwilson10 | 0:76fed7dd9235 | 1562 | * ========================================================================== */ |
seanwilson10 | 0:76fed7dd9235 | 1563 | typedef struct _ADI_ADISENSE_CORE_Digital_Sensor_Address_t { |
seanwilson10 | 0:76fed7dd9235 | 1564 | union { |
seanwilson10 | 0:76fed7dd9235 | 1565 | struct { |
seanwilson10 | 0:76fed7dd9235 | 1566 | uint8_t Digital_Sensor_Address : 8; /**< I2C Address or Write Address Command for SPI Sensor */ |
seanwilson10 | 0:76fed7dd9235 | 1567 | }; |
seanwilson10 | 0:76fed7dd9235 | 1568 | uint8_t VALUE8; |
seanwilson10 | 0:76fed7dd9235 | 1569 | }; |
seanwilson10 | 0:76fed7dd9235 | 1570 | } ADI_ADISENSE_CORE_Digital_Sensor_Address_t; |
seanwilson10 | 0:76fed7dd9235 | 1571 | |
seanwilson10 | 0:76fed7dd9235 | 1572 | /*@}*/ |
seanwilson10 | 0:76fed7dd9235 | 1573 | |
seanwilson10 | 0:76fed7dd9235 | 1574 | /** @defgroup Digital_Sensor_Num_Cmds Number of Configuration, Read Commands for Digital Sensors (Digital_Sensor_Num_Cmds) Register |
seanwilson10 | 0:76fed7dd9235 | 1575 | * Number of Configuration, Read Commands for Digital Sensors (Digital_Sensor_Num_Cmds) Register. |
seanwilson10 | 0:76fed7dd9235 | 1576 | * @{ |
seanwilson10 | 0:76fed7dd9235 | 1577 | */ |
seanwilson10 | 0:76fed7dd9235 | 1578 | |
seanwilson10 | 0:76fed7dd9235 | 1579 | /* ========================================================================== |
seanwilson10 | 0:76fed7dd9235 | 1580 | *! \struct ADI_ADISENSE_CORE_Digital_Sensor_Num_Cmds_Struct |
seanwilson10 | 0:76fed7dd9235 | 1581 | *! \brief Number of Configuration, Read Commands for Digital Sensors Register bit field structure |
seanwilson10 | 0:76fed7dd9235 | 1582 | * ========================================================================== */ |
seanwilson10 | 0:76fed7dd9235 | 1583 | typedef struct _ADI_ADISENSE_CORE_Digital_Sensor_Num_Cmds_t { |
seanwilson10 | 0:76fed7dd9235 | 1584 | union { |
seanwilson10 | 0:76fed7dd9235 | 1585 | struct { |
seanwilson10 | 0:76fed7dd9235 | 1586 | uint8_t Digital_Sensor_Num_Cfg_Cmds : 3; /**< Number of Configuration Commands for Digital Sensor */ |
seanwilson10 | 0:76fed7dd9235 | 1587 | uint8_t reserved3 : 1; |
seanwilson10 | 0:76fed7dd9235 | 1588 | uint8_t Digital_Sensor_Num_Read_Cmds : 3; /**< Number of Read Commands for Digital Sensor */ |
seanwilson10 | 0:76fed7dd9235 | 1589 | uint8_t reserved7 : 1; |
seanwilson10 | 0:76fed7dd9235 | 1590 | }; |
seanwilson10 | 0:76fed7dd9235 | 1591 | uint8_t VALUE8; |
seanwilson10 | 0:76fed7dd9235 | 1592 | }; |
seanwilson10 | 0:76fed7dd9235 | 1593 | } ADI_ADISENSE_CORE_Digital_Sensor_Num_Cmds_t; |
seanwilson10 | 0:76fed7dd9235 | 1594 | |
seanwilson10 | 0:76fed7dd9235 | 1595 | /*@}*/ |
seanwilson10 | 0:76fed7dd9235 | 1596 | |
seanwilson10 | 0:76fed7dd9235 | 1597 | /** @defgroup Digital_Sensor_Command1 Sensor Configuration Command1 (Digital_Sensor_Command1) Register |
seanwilson10 | 0:76fed7dd9235 | 1598 | * Sensor Configuration Command1 (Digital_Sensor_Command1) Register. |
seanwilson10 | 0:76fed7dd9235 | 1599 | * @{ |
seanwilson10 | 0:76fed7dd9235 | 1600 | */ |
seanwilson10 | 0:76fed7dd9235 | 1601 | |
seanwilson10 | 0:76fed7dd9235 | 1602 | /* ========================================================================== |
seanwilson10 | 0:76fed7dd9235 | 1603 | *! \struct ADI_ADISENSE_CORE_Digital_Sensor_Command1_Struct |
seanwilson10 | 0:76fed7dd9235 | 1604 | *! \brief Sensor Configuration Command1 Register bit field structure |
seanwilson10 | 0:76fed7dd9235 | 1605 | * ========================================================================== */ |
seanwilson10 | 0:76fed7dd9235 | 1606 | typedef struct _ADI_ADISENSE_CORE_Digital_Sensor_Command1_t { |
seanwilson10 | 0:76fed7dd9235 | 1607 | union { |
seanwilson10 | 0:76fed7dd9235 | 1608 | struct { |
seanwilson10 | 0:76fed7dd9235 | 1609 | uint8_t Digital_Sensor_Command1 : 8; /**< Configuration Command to Send to Digital I2C/SPI Sensor */ |
seanwilson10 | 0:76fed7dd9235 | 1610 | }; |
seanwilson10 | 0:76fed7dd9235 | 1611 | uint8_t VALUE8; |
seanwilson10 | 0:76fed7dd9235 | 1612 | }; |
seanwilson10 | 0:76fed7dd9235 | 1613 | } ADI_ADISENSE_CORE_Digital_Sensor_Command1_t; |
seanwilson10 | 0:76fed7dd9235 | 1614 | |
seanwilson10 | 0:76fed7dd9235 | 1615 | /*@}*/ |
seanwilson10 | 0:76fed7dd9235 | 1616 | |
seanwilson10 | 0:76fed7dd9235 | 1617 | /** @defgroup Digital_Sensor_Command2 Sensor Configuration Command2 (Digital_Sensor_Command2) Register |
seanwilson10 | 0:76fed7dd9235 | 1618 | * Sensor Configuration Command2 (Digital_Sensor_Command2) Register. |
seanwilson10 | 0:76fed7dd9235 | 1619 | * @{ |
seanwilson10 | 0:76fed7dd9235 | 1620 | */ |
seanwilson10 | 0:76fed7dd9235 | 1621 | |
seanwilson10 | 0:76fed7dd9235 | 1622 | /* ========================================================================== |
seanwilson10 | 0:76fed7dd9235 | 1623 | *! \struct ADI_ADISENSE_CORE_Digital_Sensor_Command2_Struct |
seanwilson10 | 0:76fed7dd9235 | 1624 | *! \brief Sensor Configuration Command2 Register bit field structure |
seanwilson10 | 0:76fed7dd9235 | 1625 | * ========================================================================== */ |
seanwilson10 | 0:76fed7dd9235 | 1626 | typedef struct _ADI_ADISENSE_CORE_Digital_Sensor_Command2_t { |
seanwilson10 | 0:76fed7dd9235 | 1627 | union { |
seanwilson10 | 0:76fed7dd9235 | 1628 | struct { |
seanwilson10 | 0:76fed7dd9235 | 1629 | uint8_t Digital_Sensor_Command2 : 8; /**< Configuration Command to Send to Digital I2C/SPI Sensor */ |
seanwilson10 | 0:76fed7dd9235 | 1630 | }; |
seanwilson10 | 0:76fed7dd9235 | 1631 | uint8_t VALUE8; |
seanwilson10 | 0:76fed7dd9235 | 1632 | }; |
seanwilson10 | 0:76fed7dd9235 | 1633 | } ADI_ADISENSE_CORE_Digital_Sensor_Command2_t; |
seanwilson10 | 0:76fed7dd9235 | 1634 | |
seanwilson10 | 0:76fed7dd9235 | 1635 | /*@}*/ |
seanwilson10 | 0:76fed7dd9235 | 1636 | |
seanwilson10 | 0:76fed7dd9235 | 1637 | /** @defgroup Digital_Sensor_Command3 Sensor Configuration Command3 (Digital_Sensor_Command3) Register |
seanwilson10 | 0:76fed7dd9235 | 1638 | * Sensor Configuration Command3 (Digital_Sensor_Command3) Register. |
seanwilson10 | 0:76fed7dd9235 | 1639 | * @{ |
seanwilson10 | 0:76fed7dd9235 | 1640 | */ |
seanwilson10 | 0:76fed7dd9235 | 1641 | |
seanwilson10 | 0:76fed7dd9235 | 1642 | /* ========================================================================== |
seanwilson10 | 0:76fed7dd9235 | 1643 | *! \struct ADI_ADISENSE_CORE_Digital_Sensor_Command3_Struct |
seanwilson10 | 0:76fed7dd9235 | 1644 | *! \brief Sensor Configuration Command3 Register bit field structure |
seanwilson10 | 0:76fed7dd9235 | 1645 | * ========================================================================== */ |
seanwilson10 | 0:76fed7dd9235 | 1646 | typedef struct _ADI_ADISENSE_CORE_Digital_Sensor_Command3_t { |
seanwilson10 | 0:76fed7dd9235 | 1647 | union { |
seanwilson10 | 0:76fed7dd9235 | 1648 | struct { |
seanwilson10 | 0:76fed7dd9235 | 1649 | uint8_t Digital_Sensor_Command3 : 8; /**< Configuration Command to Send to Digital I2C/SPI Sensor */ |
seanwilson10 | 0:76fed7dd9235 | 1650 | }; |
seanwilson10 | 0:76fed7dd9235 | 1651 | uint8_t VALUE8; |
seanwilson10 | 0:76fed7dd9235 | 1652 | }; |
seanwilson10 | 0:76fed7dd9235 | 1653 | } ADI_ADISENSE_CORE_Digital_Sensor_Command3_t; |
seanwilson10 | 0:76fed7dd9235 | 1654 | |
seanwilson10 | 0:76fed7dd9235 | 1655 | /*@}*/ |
seanwilson10 | 0:76fed7dd9235 | 1656 | |
seanwilson10 | 0:76fed7dd9235 | 1657 | /** @defgroup Digital_Sensor_Command4 Sensor Configuration Command4 (Digital_Sensor_Command4) Register |
seanwilson10 | 0:76fed7dd9235 | 1658 | * Sensor Configuration Command4 (Digital_Sensor_Command4) Register. |
seanwilson10 | 0:76fed7dd9235 | 1659 | * @{ |
seanwilson10 | 0:76fed7dd9235 | 1660 | */ |
seanwilson10 | 0:76fed7dd9235 | 1661 | |
seanwilson10 | 0:76fed7dd9235 | 1662 | /* ========================================================================== |
seanwilson10 | 0:76fed7dd9235 | 1663 | *! \struct ADI_ADISENSE_CORE_Digital_Sensor_Command4_Struct |
seanwilson10 | 0:76fed7dd9235 | 1664 | *! \brief Sensor Configuration Command4 Register bit field structure |
seanwilson10 | 0:76fed7dd9235 | 1665 | * ========================================================================== */ |
seanwilson10 | 0:76fed7dd9235 | 1666 | typedef struct _ADI_ADISENSE_CORE_Digital_Sensor_Command4_t { |
seanwilson10 | 0:76fed7dd9235 | 1667 | union { |
seanwilson10 | 0:76fed7dd9235 | 1668 | struct { |
seanwilson10 | 0:76fed7dd9235 | 1669 | uint8_t Digital_Sensor_Command4 : 8; /**< Configuration Command to Send to Digital I2C/SPI Sensor */ |
seanwilson10 | 0:76fed7dd9235 | 1670 | }; |
seanwilson10 | 0:76fed7dd9235 | 1671 | uint8_t VALUE8; |
seanwilson10 | 0:76fed7dd9235 | 1672 | }; |
seanwilson10 | 0:76fed7dd9235 | 1673 | } ADI_ADISENSE_CORE_Digital_Sensor_Command4_t; |
seanwilson10 | 0:76fed7dd9235 | 1674 | |
seanwilson10 | 0:76fed7dd9235 | 1675 | /*@}*/ |
seanwilson10 | 0:76fed7dd9235 | 1676 | |
seanwilson10 | 0:76fed7dd9235 | 1677 | /** @defgroup Digital_Sensor_Command5 Sensor Configuration Command5 (Digital_Sensor_Command5) Register |
seanwilson10 | 0:76fed7dd9235 | 1678 | * Sensor Configuration Command5 (Digital_Sensor_Command5) Register. |
seanwilson10 | 0:76fed7dd9235 | 1679 | * @{ |
seanwilson10 | 0:76fed7dd9235 | 1680 | */ |
seanwilson10 | 0:76fed7dd9235 | 1681 | |
seanwilson10 | 0:76fed7dd9235 | 1682 | /* ========================================================================== |
seanwilson10 | 0:76fed7dd9235 | 1683 | *! \struct ADI_ADISENSE_CORE_Digital_Sensor_Command5_Struct |
seanwilson10 | 0:76fed7dd9235 | 1684 | *! \brief Sensor Configuration Command5 Register bit field structure |
seanwilson10 | 0:76fed7dd9235 | 1685 | * ========================================================================== */ |
seanwilson10 | 0:76fed7dd9235 | 1686 | typedef struct _ADI_ADISENSE_CORE_Digital_Sensor_Command5_t { |
seanwilson10 | 0:76fed7dd9235 | 1687 | union { |
seanwilson10 | 0:76fed7dd9235 | 1688 | struct { |
seanwilson10 | 0:76fed7dd9235 | 1689 | uint8_t Digital_Sensor_Command5 : 8; /**< Configuration Command to Send to Digital I2C/SPI Sensor */ |
seanwilson10 | 0:76fed7dd9235 | 1690 | }; |
seanwilson10 | 0:76fed7dd9235 | 1691 | uint8_t VALUE8; |
seanwilson10 | 0:76fed7dd9235 | 1692 | }; |
seanwilson10 | 0:76fed7dd9235 | 1693 | } ADI_ADISENSE_CORE_Digital_Sensor_Command5_t; |
seanwilson10 | 0:76fed7dd9235 | 1694 | |
seanwilson10 | 0:76fed7dd9235 | 1695 | /*@}*/ |
seanwilson10 | 0:76fed7dd9235 | 1696 | |
seanwilson10 | 0:76fed7dd9235 | 1697 | /** @defgroup Digital_Sensor_Command6 Sensor Configuration Command6 (Digital_Sensor_Command6) Register |
seanwilson10 | 0:76fed7dd9235 | 1698 | * Sensor Configuration Command6 (Digital_Sensor_Command6) Register. |
seanwilson10 | 0:76fed7dd9235 | 1699 | * @{ |
seanwilson10 | 0:76fed7dd9235 | 1700 | */ |
seanwilson10 | 0:76fed7dd9235 | 1701 | |
seanwilson10 | 0:76fed7dd9235 | 1702 | /* ========================================================================== |
seanwilson10 | 0:76fed7dd9235 | 1703 | *! \struct ADI_ADISENSE_CORE_Digital_Sensor_Command6_Struct |
seanwilson10 | 0:76fed7dd9235 | 1704 | *! \brief Sensor Configuration Command6 Register bit field structure |
seanwilson10 | 0:76fed7dd9235 | 1705 | * ========================================================================== */ |
seanwilson10 | 0:76fed7dd9235 | 1706 | typedef struct _ADI_ADISENSE_CORE_Digital_Sensor_Command6_t { |
seanwilson10 | 0:76fed7dd9235 | 1707 | union { |
seanwilson10 | 0:76fed7dd9235 | 1708 | struct { |
seanwilson10 | 0:76fed7dd9235 | 1709 | uint8_t Digital_Sensor_Command6 : 8; /**< Configuration Command to Send to Digital I2C/SPI Sensor */ |
seanwilson10 | 0:76fed7dd9235 | 1710 | }; |
seanwilson10 | 0:76fed7dd9235 | 1711 | uint8_t VALUE8; |
seanwilson10 | 0:76fed7dd9235 | 1712 | }; |
seanwilson10 | 0:76fed7dd9235 | 1713 | } ADI_ADISENSE_CORE_Digital_Sensor_Command6_t; |
seanwilson10 | 0:76fed7dd9235 | 1714 | |
seanwilson10 | 0:76fed7dd9235 | 1715 | /*@}*/ |
seanwilson10 | 0:76fed7dd9235 | 1716 | |
seanwilson10 | 0:76fed7dd9235 | 1717 | /** @defgroup Digital_Sensor_Command7 Sensor Configuration Command7 (Digital_Sensor_Command7) Register |
seanwilson10 | 0:76fed7dd9235 | 1718 | * Sensor Configuration Command7 (Digital_Sensor_Command7) Register. |
seanwilson10 | 0:76fed7dd9235 | 1719 | * @{ |
seanwilson10 | 0:76fed7dd9235 | 1720 | */ |
seanwilson10 | 0:76fed7dd9235 | 1721 | |
seanwilson10 | 0:76fed7dd9235 | 1722 | /* ========================================================================== |
seanwilson10 | 0:76fed7dd9235 | 1723 | *! \struct ADI_ADISENSE_CORE_Digital_Sensor_Command7_Struct |
seanwilson10 | 0:76fed7dd9235 | 1724 | *! \brief Sensor Configuration Command7 Register bit field structure |
seanwilson10 | 0:76fed7dd9235 | 1725 | * ========================================================================== */ |
seanwilson10 | 0:76fed7dd9235 | 1726 | typedef struct _ADI_ADISENSE_CORE_Digital_Sensor_Command7_t { |
seanwilson10 | 0:76fed7dd9235 | 1727 | union { |
seanwilson10 | 0:76fed7dd9235 | 1728 | struct { |
seanwilson10 | 0:76fed7dd9235 | 1729 | uint8_t Digital_Sensor_Command7 : 8; /**< Configuration Command to Send to Digital I2C/SPI Sensor */ |
seanwilson10 | 0:76fed7dd9235 | 1730 | }; |
seanwilson10 | 0:76fed7dd9235 | 1731 | uint8_t VALUE8; |
seanwilson10 | 0:76fed7dd9235 | 1732 | }; |
seanwilson10 | 0:76fed7dd9235 | 1733 | } ADI_ADISENSE_CORE_Digital_Sensor_Command7_t; |
seanwilson10 | 0:76fed7dd9235 | 1734 | |
seanwilson10 | 0:76fed7dd9235 | 1735 | /*@}*/ |
seanwilson10 | 0:76fed7dd9235 | 1736 | |
seanwilson10 | 0:76fed7dd9235 | 1737 | /** @defgroup Digital_Sensor_Read_Cmd1 Sensor Read Command1 (Digital_Sensor_Read_Cmd1) Register |
seanwilson10 | 0:76fed7dd9235 | 1738 | * Sensor Read Command1 (Digital_Sensor_Read_Cmd1) Register. |
seanwilson10 | 0:76fed7dd9235 | 1739 | * @{ |
seanwilson10 | 0:76fed7dd9235 | 1740 | */ |
seanwilson10 | 0:76fed7dd9235 | 1741 | |
seanwilson10 | 0:76fed7dd9235 | 1742 | /* ========================================================================== |
seanwilson10 | 0:76fed7dd9235 | 1743 | *! \struct ADI_ADISENSE_CORE_Digital_Sensor_Read_Cmd1_Struct |
seanwilson10 | 0:76fed7dd9235 | 1744 | *! \brief Sensor Read Command1 Register bit field structure |
seanwilson10 | 0:76fed7dd9235 | 1745 | * ========================================================================== */ |
seanwilson10 | 0:76fed7dd9235 | 1746 | typedef struct _ADI_ADISENSE_CORE_Digital_Sensor_Read_Cmd1_t { |
seanwilson10 | 0:76fed7dd9235 | 1747 | union { |
seanwilson10 | 0:76fed7dd9235 | 1748 | struct { |
seanwilson10 | 0:76fed7dd9235 | 1749 | uint8_t Digital_Sensor_Read_Cmd1 : 8; /**< Per Conversion Command to Send to Digital I2C/SPI Sensor */ |
seanwilson10 | 0:76fed7dd9235 | 1750 | }; |
seanwilson10 | 0:76fed7dd9235 | 1751 | uint8_t VALUE8; |
seanwilson10 | 0:76fed7dd9235 | 1752 | }; |
seanwilson10 | 0:76fed7dd9235 | 1753 | } ADI_ADISENSE_CORE_Digital_Sensor_Read_Cmd1_t; |
seanwilson10 | 0:76fed7dd9235 | 1754 | |
seanwilson10 | 0:76fed7dd9235 | 1755 | /*@}*/ |
seanwilson10 | 0:76fed7dd9235 | 1756 | |
seanwilson10 | 0:76fed7dd9235 | 1757 | /** @defgroup Digital_Sensor_Read_Cmd2 Sensor Read Command2 (Digital_Sensor_Read_Cmd2) Register |
seanwilson10 | 0:76fed7dd9235 | 1758 | * Sensor Read Command2 (Digital_Sensor_Read_Cmd2) Register. |
seanwilson10 | 0:76fed7dd9235 | 1759 | * @{ |
seanwilson10 | 0:76fed7dd9235 | 1760 | */ |
seanwilson10 | 0:76fed7dd9235 | 1761 | |
seanwilson10 | 0:76fed7dd9235 | 1762 | /* ========================================================================== |
seanwilson10 | 0:76fed7dd9235 | 1763 | *! \struct ADI_ADISENSE_CORE_Digital_Sensor_Read_Cmd2_Struct |
seanwilson10 | 0:76fed7dd9235 | 1764 | *! \brief Sensor Read Command2 Register bit field structure |
seanwilson10 | 0:76fed7dd9235 | 1765 | * ========================================================================== */ |
seanwilson10 | 0:76fed7dd9235 | 1766 | typedef struct _ADI_ADISENSE_CORE_Digital_Sensor_Read_Cmd2_t { |
seanwilson10 | 0:76fed7dd9235 | 1767 | union { |
seanwilson10 | 0:76fed7dd9235 | 1768 | struct { |
seanwilson10 | 0:76fed7dd9235 | 1769 | uint8_t Digital_Sensor_Read_Cmd2 : 8; /**< Per Conversion Command to Send to Digital I2C/SPI Sensor */ |
seanwilson10 | 0:76fed7dd9235 | 1770 | }; |
seanwilson10 | 0:76fed7dd9235 | 1771 | uint8_t VALUE8; |
seanwilson10 | 0:76fed7dd9235 | 1772 | }; |
seanwilson10 | 0:76fed7dd9235 | 1773 | } ADI_ADISENSE_CORE_Digital_Sensor_Read_Cmd2_t; |
seanwilson10 | 0:76fed7dd9235 | 1774 | |
seanwilson10 | 0:76fed7dd9235 | 1775 | /*@}*/ |
seanwilson10 | 0:76fed7dd9235 | 1776 | |
seanwilson10 | 0:76fed7dd9235 | 1777 | /** @defgroup Digital_Sensor_Read_Cmd3 Sensor Read Command3 (Digital_Sensor_Read_Cmd3) Register |
seanwilson10 | 0:76fed7dd9235 | 1778 | * Sensor Read Command3 (Digital_Sensor_Read_Cmd3) Register. |
seanwilson10 | 0:76fed7dd9235 | 1779 | * @{ |
seanwilson10 | 0:76fed7dd9235 | 1780 | */ |
seanwilson10 | 0:76fed7dd9235 | 1781 | |
seanwilson10 | 0:76fed7dd9235 | 1782 | /* ========================================================================== |
seanwilson10 | 0:76fed7dd9235 | 1783 | *! \struct ADI_ADISENSE_CORE_Digital_Sensor_Read_Cmd3_Struct |
seanwilson10 | 0:76fed7dd9235 | 1784 | *! \brief Sensor Read Command3 Register bit field structure |
seanwilson10 | 0:76fed7dd9235 | 1785 | * ========================================================================== */ |
seanwilson10 | 0:76fed7dd9235 | 1786 | typedef struct _ADI_ADISENSE_CORE_Digital_Sensor_Read_Cmd3_t { |
seanwilson10 | 0:76fed7dd9235 | 1787 | union { |
seanwilson10 | 0:76fed7dd9235 | 1788 | struct { |
seanwilson10 | 0:76fed7dd9235 | 1789 | uint8_t Digital_Sensor_Read_Cmd3 : 8; /**< Per Conversion Command to Send to Digital I2C/SPI Sensor */ |
seanwilson10 | 0:76fed7dd9235 | 1790 | }; |
seanwilson10 | 0:76fed7dd9235 | 1791 | uint8_t VALUE8; |
seanwilson10 | 0:76fed7dd9235 | 1792 | }; |
seanwilson10 | 0:76fed7dd9235 | 1793 | } ADI_ADISENSE_CORE_Digital_Sensor_Read_Cmd3_t; |
seanwilson10 | 0:76fed7dd9235 | 1794 | |
seanwilson10 | 0:76fed7dd9235 | 1795 | /*@}*/ |
seanwilson10 | 0:76fed7dd9235 | 1796 | |
seanwilson10 | 0:76fed7dd9235 | 1797 | /** @defgroup Digital_Sensor_Read_Cmd4 Sensor Read Command4 (Digital_Sensor_Read_Cmd4) Register |
seanwilson10 | 0:76fed7dd9235 | 1798 | * Sensor Read Command4 (Digital_Sensor_Read_Cmd4) Register. |
seanwilson10 | 0:76fed7dd9235 | 1799 | * @{ |
seanwilson10 | 0:76fed7dd9235 | 1800 | */ |
seanwilson10 | 0:76fed7dd9235 | 1801 | |
seanwilson10 | 0:76fed7dd9235 | 1802 | /* ========================================================================== |
seanwilson10 | 0:76fed7dd9235 | 1803 | *! \struct ADI_ADISENSE_CORE_Digital_Sensor_Read_Cmd4_Struct |
seanwilson10 | 0:76fed7dd9235 | 1804 | *! \brief Sensor Read Command4 Register bit field structure |
seanwilson10 | 0:76fed7dd9235 | 1805 | * ========================================================================== */ |
seanwilson10 | 0:76fed7dd9235 | 1806 | typedef struct _ADI_ADISENSE_CORE_Digital_Sensor_Read_Cmd4_t { |
seanwilson10 | 0:76fed7dd9235 | 1807 | union { |
seanwilson10 | 0:76fed7dd9235 | 1808 | struct { |
seanwilson10 | 0:76fed7dd9235 | 1809 | uint8_t Digital_Sensor_Read_Cmd4 : 8; /**< Per Conversion Command to Send to Digital I2C/SPI Sensor */ |
seanwilson10 | 0:76fed7dd9235 | 1810 | }; |
seanwilson10 | 0:76fed7dd9235 | 1811 | uint8_t VALUE8; |
seanwilson10 | 0:76fed7dd9235 | 1812 | }; |
seanwilson10 | 0:76fed7dd9235 | 1813 | } ADI_ADISENSE_CORE_Digital_Sensor_Read_Cmd4_t; |
seanwilson10 | 0:76fed7dd9235 | 1814 | |
seanwilson10 | 0:76fed7dd9235 | 1815 | /*@}*/ |
seanwilson10 | 0:76fed7dd9235 | 1816 | |
seanwilson10 | 0:76fed7dd9235 | 1817 | /** @defgroup Digital_Sensor_Read_Cmd5 Sensor Read Command5 (Digital_Sensor_Read_Cmd5) Register |
seanwilson10 | 0:76fed7dd9235 | 1818 | * Sensor Read Command5 (Digital_Sensor_Read_Cmd5) Register. |
seanwilson10 | 0:76fed7dd9235 | 1819 | * @{ |
seanwilson10 | 0:76fed7dd9235 | 1820 | */ |
seanwilson10 | 0:76fed7dd9235 | 1821 | |
seanwilson10 | 0:76fed7dd9235 | 1822 | /* ========================================================================== |
seanwilson10 | 0:76fed7dd9235 | 1823 | *! \struct ADI_ADISENSE_CORE_Digital_Sensor_Read_Cmd5_Struct |
seanwilson10 | 0:76fed7dd9235 | 1824 | *! \brief Sensor Read Command5 Register bit field structure |
seanwilson10 | 0:76fed7dd9235 | 1825 | * ========================================================================== */ |
seanwilson10 | 0:76fed7dd9235 | 1826 | typedef struct _ADI_ADISENSE_CORE_Digital_Sensor_Read_Cmd5_t { |
seanwilson10 | 0:76fed7dd9235 | 1827 | union { |
seanwilson10 | 0:76fed7dd9235 | 1828 | struct { |
seanwilson10 | 0:76fed7dd9235 | 1829 | uint8_t Digital_Sensor_Read_Cmd5 : 8; /**< Per Conversion Command to Send to Digital I2C/SPI Sensor */ |
seanwilson10 | 0:76fed7dd9235 | 1830 | }; |
seanwilson10 | 0:76fed7dd9235 | 1831 | uint8_t VALUE8; |
seanwilson10 | 0:76fed7dd9235 | 1832 | }; |
seanwilson10 | 0:76fed7dd9235 | 1833 | } ADI_ADISENSE_CORE_Digital_Sensor_Read_Cmd5_t; |
seanwilson10 | 0:76fed7dd9235 | 1834 | |
seanwilson10 | 0:76fed7dd9235 | 1835 | /*@}*/ |
seanwilson10 | 0:76fed7dd9235 | 1836 | |
seanwilson10 | 0:76fed7dd9235 | 1837 | /** @defgroup Digital_Sensor_Read_Cmd6 Sensor Read Command6 (Digital_Sensor_Read_Cmd6) Register |
seanwilson10 | 0:76fed7dd9235 | 1838 | * Sensor Read Command6 (Digital_Sensor_Read_Cmd6) Register. |
seanwilson10 | 0:76fed7dd9235 | 1839 | * @{ |
seanwilson10 | 0:76fed7dd9235 | 1840 | */ |
seanwilson10 | 0:76fed7dd9235 | 1841 | |
seanwilson10 | 0:76fed7dd9235 | 1842 | /* ========================================================================== |
seanwilson10 | 0:76fed7dd9235 | 1843 | *! \struct ADI_ADISENSE_CORE_Digital_Sensor_Read_Cmd6_Struct |
seanwilson10 | 0:76fed7dd9235 | 1844 | *! \brief Sensor Read Command6 Register bit field structure |
seanwilson10 | 0:76fed7dd9235 | 1845 | * ========================================================================== */ |
seanwilson10 | 0:76fed7dd9235 | 1846 | typedef struct _ADI_ADISENSE_CORE_Digital_Sensor_Read_Cmd6_t { |
seanwilson10 | 0:76fed7dd9235 | 1847 | union { |
seanwilson10 | 0:76fed7dd9235 | 1848 | struct { |
seanwilson10 | 0:76fed7dd9235 | 1849 | uint8_t Digital_Sensor_Read_Cmd6 : 8; /**< Per Conversion Command to Send to Digital I2C/SPI Sensor */ |
seanwilson10 | 0:76fed7dd9235 | 1850 | }; |
seanwilson10 | 0:76fed7dd9235 | 1851 | uint8_t VALUE8; |
seanwilson10 | 0:76fed7dd9235 | 1852 | }; |
seanwilson10 | 0:76fed7dd9235 | 1853 | } ADI_ADISENSE_CORE_Digital_Sensor_Read_Cmd6_t; |
seanwilson10 | 0:76fed7dd9235 | 1854 | |
seanwilson10 | 0:76fed7dd9235 | 1855 | /*@}*/ |
seanwilson10 | 0:76fed7dd9235 | 1856 | |
seanwilson10 | 0:76fed7dd9235 | 1857 | /** @defgroup Digital_Sensor_Read_Cmd7 Sensor Read Command7 (Digital_Sensor_Read_Cmd7) Register |
seanwilson10 | 0:76fed7dd9235 | 1858 | * Sensor Read Command7 (Digital_Sensor_Read_Cmd7) Register. |
seanwilson10 | 0:76fed7dd9235 | 1859 | * @{ |
seanwilson10 | 0:76fed7dd9235 | 1860 | */ |
seanwilson10 | 0:76fed7dd9235 | 1861 | |
seanwilson10 | 0:76fed7dd9235 | 1862 | /* ========================================================================== |
seanwilson10 | 0:76fed7dd9235 | 1863 | *! \struct ADI_ADISENSE_CORE_Digital_Sensor_Read_Cmd7_Struct |
seanwilson10 | 0:76fed7dd9235 | 1864 | *! \brief Sensor Read Command7 Register bit field structure |
seanwilson10 | 0:76fed7dd9235 | 1865 | * ========================================================================== */ |
seanwilson10 | 0:76fed7dd9235 | 1866 | typedef struct _ADI_ADISENSE_CORE_Digital_Sensor_Read_Cmd7_t { |
seanwilson10 | 0:76fed7dd9235 | 1867 | union { |
seanwilson10 | 0:76fed7dd9235 | 1868 | struct { |
seanwilson10 | 0:76fed7dd9235 | 1869 | uint8_t Digital_Sensor_Read_Cmd7 : 8; /**< Per Conversion Command to Send to Digital I2C/SPI Sensor */ |
seanwilson10 | 0:76fed7dd9235 | 1870 | }; |
seanwilson10 | 0:76fed7dd9235 | 1871 | uint8_t VALUE8; |
seanwilson10 | 0:76fed7dd9235 | 1872 | }; |
seanwilson10 | 0:76fed7dd9235 | 1873 | } ADI_ADISENSE_CORE_Digital_Sensor_Read_Cmd7_t; |
seanwilson10 | 0:76fed7dd9235 | 1874 | |
seanwilson10 | 0:76fed7dd9235 | 1875 | /*@}*/ |
seanwilson10 | 0:76fed7dd9235 | 1876 | |
seanwilson10 | 0:76fed7dd9235 | 1877 | /** @defgroup test_reg_0 Test Register 0 (test_reg_0) Register |
seanwilson10 | 0:76fed7dd9235 | 1878 | * Test Register 0 (test_reg_0) Register. |
seanwilson10 | 0:76fed7dd9235 | 1879 | * @{ |
seanwilson10 | 0:76fed7dd9235 | 1880 | */ |
seanwilson10 | 0:76fed7dd9235 | 1881 | |
seanwilson10 | 0:76fed7dd9235 | 1882 | /* ========================================================================== |
seanwilson10 | 0:76fed7dd9235 | 1883 | *! \struct ADI_ADSENSE_TEST_test_reg_0_Struct |
seanwilson10 | 0:76fed7dd9235 | 1884 | *! \brief Test Register 0 Register bit field structure |
seanwilson10 | 0:76fed7dd9235 | 1885 | * ========================================================================== */ |
seanwilson10 | 0:76fed7dd9235 | 1886 | typedef struct _ADI_ADSENSE_TEST_test_reg_0_t { |
seanwilson10 | 0:76fed7dd9235 | 1887 | union { |
seanwilson10 | 0:76fed7dd9235 | 1888 | struct { |
seanwilson10 | 0:76fed7dd9235 | 1889 | uint8_t Test_Command : 8; /**< Test_Command */ |
seanwilson10 | 0:76fed7dd9235 | 1890 | }; |
seanwilson10 | 0:76fed7dd9235 | 1891 | }; |
seanwilson10 | 0:76fed7dd9235 | 1892 | } ADI_ADSENSE_TEST_test_reg_0_t; |
seanwilson10 | 0:76fed7dd9235 | 1893 | |
seanwilson10 | 0:76fed7dd9235 | 1894 | /*@}*/ |
seanwilson10 | 0:76fed7dd9235 | 1895 | |
seanwilson10 | 0:76fed7dd9235 | 1896 | |
seanwilson10 | 0:76fed7dd9235 | 1897 | /* ========================================================================== |
seanwilson10 | 0:76fed7dd9235 | 1898 | *! \struct ADI_ADISENSE_CORE_test_adc_cal_temp |
seanwilson10 | 0:76fed7dd9235 | 1899 | *! \brief ADC-derived calibration temperature |
seanwilson10 | 0:76fed7dd9235 | 1900 | * ========================================================================== */ |
seanwilson10 | 0:76fed7dd9235 | 1901 | typedef struct _ADI_ADISENSE_CORE_test_adc_cal_temp_t { |
seanwilson10 | 0:76fed7dd9235 | 1902 | union { |
seanwilson10 | 0:76fed7dd9235 | 1903 | struct { |
seanwilson10 | 0:76fed7dd9235 | 1904 | float Temperature; /**< Current temperature from ADC, used for calibration unless REG_ADISENSE_TEST_USER_CAL_TEMP is set */ |
seanwilson10 | 0:76fed7dd9235 | 1905 | }; |
seanwilson10 | 0:76fed7dd9235 | 1906 | float VALUE32; |
seanwilson10 | 0:76fed7dd9235 | 1907 | }; |
seanwilson10 | 0:76fed7dd9235 | 1908 | } ADI_ADISENSE_CORE_test_adc_cal_temp_t; |
seanwilson10 | 0:76fed7dd9235 | 1909 | |
seanwilson10 | 0:76fed7dd9235 | 1910 | |
seanwilson10 | 0:76fed7dd9235 | 1911 | /* ========================================================================== |
seanwilson10 | 0:76fed7dd9235 | 1912 | *! \struct ADI_ADISENSE_CORE_test_user_cal_temp |
seanwilson10 | 0:76fed7dd9235 | 1913 | *! \brief User-specified calibration temperature |
seanwilson10 | 0:76fed7dd9235 | 1914 | * ========================================================================== */ |
seanwilson10 | 0:76fed7dd9235 | 1915 | typedef struct _ADI_ADISENSE_CORE_test_user_cal_temp_t { |
seanwilson10 | 0:76fed7dd9235 | 1916 | union { |
seanwilson10 | 0:76fed7dd9235 | 1917 | struct { |
seanwilson10 | 0:76fed7dd9235 | 1918 | float Temperature; /**< Fixed temperature reference to use for calibration. Ignored if set as NaN. */ |
seanwilson10 | 0:76fed7dd9235 | 1919 | }; |
seanwilson10 | 0:76fed7dd9235 | 1920 | float VALUE32; |
seanwilson10 | 0:76fed7dd9235 | 1921 | }; |
seanwilson10 | 0:76fed7dd9235 | 1922 | } ADI_ADISENSE_CORE_test_user_cal_temp_t; |
seanwilson10 | 0:76fed7dd9235 | 1923 | |
seanwilson10 | 0:76fed7dd9235 | 1924 | #if defined (__CC_ARM) |
seanwilson10 | 0:76fed7dd9235 | 1925 | #pragma pop |
seanwilson10 | 0:76fed7dd9235 | 1926 | #endif |
seanwilson10 | 0:76fed7dd9235 | 1927 | |
seanwilson10 | 0:76fed7dd9235 | 1928 | #endif |
seanwilson10 | 0:76fed7dd9235 | 1929 |