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LPC17xx.h File Reference
CMSIS Cortex-M3 Core Peripheral Access Layer Header File for NXP LPC17xx Device Series.
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enum IRQn { NonMaskableInt_IRQn = -14,
MemoryManagement_IRQn = -12,
BusFault_IRQn = -11,
UsageFault_IRQn = -10,
SVCall_IRQn = -5,
DebugMonitor_IRQn = -4,
PendSV_IRQn = -2,
SysTick_IRQn = -1,
WDT_IRQn = 0,
TIMER0_IRQn = 1,
TIMER1_IRQn = 2,
TIMER2_IRQn = 3,
TIMER3_IRQn = 4,
UART0_IRQn = 5,
UART1_IRQn = 6,
UART2_IRQn = 7,
UART3_IRQn = 8,
PWM1_IRQn = 9,
I2C0_IRQn = 10,
I2C1_IRQn = 11,
I2C2_IRQn = 12,
SPI_IRQn = 13,
SSP0_IRQn = 14,
SSP1_IRQn = 15,
PLL0_IRQn = 16,
RTC_IRQn = 17,
EINT0_IRQn = 18,
EINT1_IRQn = 19,
EINT2_IRQn = 20,
EINT3_IRQn = 21,
ADC_IRQn = 22,
BOD_IRQn = 23,
USB_IRQn = 24,
CAN_IRQn = 25,
DMA_IRQn = 26,
I2S_IRQn = 27,
ENET_IRQn = 28,
RIT_IRQn = 29,
MCPWM_IRQn = 30,
QEI_IRQn = 31,
PLL1_IRQn = 32
, NonMaskableInt_IRQn = -14,
MemoryManagement_IRQn = -12,
BusFault_IRQn = -11,
UsageFault_IRQn = -10,
SVCall_IRQn = -5,
DebugMonitor_IRQn = -4,
PendSV_IRQn = -2,
SysTick_IRQn = -1,
WDT_IRQn = 0,
TIMER0_IRQn = 1,
TIMER1_IRQn = 2,
TIMER2_IRQn = 3,
TIMER3_IRQn = 4,
UART0_IRQn = 5,
UART1_IRQn = 6,
UART2_IRQn = 7,
UART3_IRQn = 8,
PWM1_IRQn = 9,
I2C0_IRQn = 10,
I2C1_IRQn = 11,
I2C2_IRQn = 12,
SPI_IRQn = 13,
SSP0_IRQn = 14,
SSP1_IRQn = 15,
PLL0_IRQn = 16,
RTC_IRQn = 17,
EINT0_IRQn = 18,
EINT1_IRQn = 19,
EINT2_IRQn = 20,
EINT3_IRQn = 21,
ADC_IRQn = 22,
BOD_IRQn = 23,
USB_IRQn = 24,
CAN_IRQn = 25,
DMA_IRQn = 26,
I2S_IRQn = 27,
ENET_IRQn = 28,
RIT_IRQn = 29,
MCPWM_IRQn = 30,
QEI_IRQn = 31,
PLL1_IRQn = 32
Detailed Description
CMSIS Cortex-M3 Core Peripheral Access Layer Header File for NXP LPC17xx Device Series.
Version: : V1.09 Date: : 17. March 2010 Note: Copyright (C) 2009 ARM Limited. All rights reserved. ARM Limited (ARM) is supplying this software for use with Cortex-M processor based microcontrollers. This file can be freely distributed within development tools that are supporting such ARM based processors. THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. Definition in file LPC17xx.h .
Enumeration Type Documentation
Enumerator:
2 Non Maskable Interrupt
4 Cortex-M3 Memory Management Interrupt
5 Cortex-M3 Bus Fault Interrupt
6 Cortex-M3 Usage Fault Interrupt
11 Cortex-M3 SV Call Interrupt
12 Cortex-M3 Debug Monitor Interrupt
14 Cortex-M3 Pend SV Interrupt
15 Cortex-M3 System Tick Interrupt
Watchdog Timer Interrupt
Timer0 Interrupt
Timer1 Interrupt
Timer2 Interrupt
Timer3 Interrupt
UART0 Interrupt
UART1 Interrupt
UART2 Interrupt
UART3 Interrupt
PWM1 Interrupt
I2C0 Interrupt
I2C1 Interrupt
I2C2 Interrupt
SPI Interrupt
SSP0 Interrupt
SSP1 Interrupt
PLL0 Lock (Main PLL) Interrupt
Real Time Clock Interrupt
External Interrupt 0 Interrupt
External Interrupt 1 Interrupt
External Interrupt 2 Interrupt
External Interrupt 3 Interrupt
A/D Converter Interrupt
Brown-Out Detect Interrupt
USB Interrupt
CAN Interrupt
General Purpose DMA Interrupt
I2S Interrupt
Ethernet Interrupt
Repetitive Interrupt Timer Interrupt
Motor Control PWM Interrupt
Quadrature Encoder Interface Interrupt
PLL1 Lock (USB PLL) Interrupt
Definition at line 33 of file LPC17xx.h .
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