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mbed-rtos
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LPC17xx.h
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00001 /****************************************************************************** 00002 * @file: LPC17xx.h 00003 * @purpose: CMSIS Cortex-M3 Core Peripheral Access Layer Header File for 00004 * NXP LPC17xx Device Series 00005 * @version: V1.09 00006 * @date: 17. March 2010 00007 *---------------------------------------------------------------------------- 00008 * 00009 * Copyright (C) 2008 ARM Limited. All rights reserved. 00010 * 00011 * ARM Limited (ARM) is supplying this software for use with Cortex-M3 00012 * processor based microcontrollers. This file can be freely distributed 00013 * within development tools that are supporting such ARM based processors. 00014 * 00015 * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED 00016 * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF 00017 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. 00018 * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR 00019 * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. 00020 * 00021 ******************************************************************************/ 00022 00023 00024 #ifndef __LPC17xx_H__ 00025 #define __LPC17xx_H__ 00026 00027 /* 00028 * ========================================================================== 00029 * ---------- Interrupt Number Definition ----------------------------------- 00030 * ========================================================================== 00031 */ 00032 00033 typedef enum IRQn 00034 { 00035 /****** Cortex-M3 Processor Exceptions Numbers ***************************************************/ 00036 NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */ 00037 MemoryManagement_IRQn = -12, /*!< 4 Cortex-M3 Memory Management Interrupt */ 00038 BusFault_IRQn = -11, /*!< 5 Cortex-M3 Bus Fault Interrupt */ 00039 UsageFault_IRQn = -10, /*!< 6 Cortex-M3 Usage Fault Interrupt */ 00040 SVCall_IRQn = -5, /*!< 11 Cortex-M3 SV Call Interrupt */ 00041 DebugMonitor_IRQn = -4, /*!< 12 Cortex-M3 Debug Monitor Interrupt */ 00042 PendSV_IRQn = -2, /*!< 14 Cortex-M3 Pend SV Interrupt */ 00043 SysTick_IRQn = -1, /*!< 15 Cortex-M3 System Tick Interrupt */ 00044 00045 /****** LPC17xx Specific Interrupt Numbers *******************************************************/ 00046 WDT_IRQn = 0, /*!< Watchdog Timer Interrupt */ 00047 TIMER0_IRQn = 1, /*!< Timer0 Interrupt */ 00048 TIMER1_IRQn = 2, /*!< Timer1 Interrupt */ 00049 TIMER2_IRQn = 3, /*!< Timer2 Interrupt */ 00050 TIMER3_IRQn = 4, /*!< Timer3 Interrupt */ 00051 UART0_IRQn = 5, /*!< UART0 Interrupt */ 00052 UART1_IRQn = 6, /*!< UART1 Interrupt */ 00053 UART2_IRQn = 7, /*!< UART2 Interrupt */ 00054 UART3_IRQn = 8, /*!< UART3 Interrupt */ 00055 PWM1_IRQn = 9, /*!< PWM1 Interrupt */ 00056 I2C0_IRQn = 10, /*!< I2C0 Interrupt */ 00057 I2C1_IRQn = 11, /*!< I2C1 Interrupt */ 00058 I2C2_IRQn = 12, /*!< I2C2 Interrupt */ 00059 SPI_IRQn = 13, /*!< SPI Interrupt */ 00060 SSP0_IRQn = 14, /*!< SSP0 Interrupt */ 00061 SSP1_IRQn = 15, /*!< SSP1 Interrupt */ 00062 PLL0_IRQn = 16, /*!< PLL0 Lock (Main PLL) Interrupt */ 00063 RTC_IRQn = 17, /*!< Real Time Clock Interrupt */ 00064 EINT0_IRQn = 18, /*!< External Interrupt 0 Interrupt */ 00065 EINT1_IRQn = 19, /*!< External Interrupt 1 Interrupt */ 00066 EINT2_IRQn = 20, /*!< External Interrupt 2 Interrupt */ 00067 EINT3_IRQn = 21, /*!< External Interrupt 3 Interrupt */ 00068 ADC_IRQn = 22, /*!< A/D Converter Interrupt */ 00069 BOD_IRQn = 23, /*!< Brown-Out Detect Interrupt */ 00070 USB_IRQn = 24, /*!< USB Interrupt */ 00071 CAN_IRQn = 25, /*!< CAN Interrupt */ 00072 DMA_IRQn = 26, /*!< General Purpose DMA Interrupt */ 00073 I2S_IRQn = 27, /*!< I2S Interrupt */ 00074 ENET_IRQn = 28, /*!< Ethernet Interrupt */ 00075 RIT_IRQn = 29, /*!< Repetitive Interrupt Timer Interrupt */ 00076 MCPWM_IRQn = 30, /*!< Motor Control PWM Interrupt */ 00077 QEI_IRQn = 31, /*!< Quadrature Encoder Interface Interrupt */ 00078 PLL1_IRQn = 32, /*!< PLL1 Lock (USB PLL) Interrupt */ 00079 USBActivity_IRQn = 33, /* USB Activity interrupt */ 00080 CANActivity_IRQn = 34, /* CAN Activity interrupt */ 00081 } IRQn_Type; 00082 00083 00084 /* 00085 * ========================================================================== 00086 * ----------- Processor and Core Peripheral Section ------------------------ 00087 * ========================================================================== 00088 */ 00089 00090 /* Configuration of the Cortex-M3 Processor and Core Peripherals */ 00091 #define __MPU_PRESENT 1 /*!< MPU present or not */ 00092 #define __NVIC_PRIO_BITS 5 /*!< Number of Bits used for Priority Levels */ 00093 #define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ 00094 00095 00096 #include <core_cm3.h> /* Cortex-M3 processor and core peripherals */ 00097 #include "system_LPC17xx.h" /* System Header */ 00098 00099 00100 /******************************************************************************/ 00101 /* Device Specific Peripheral registers structures */ 00102 /******************************************************************************/ 00103 00104 #if defined ( __CC_ARM ) 00105 #pragma anon_unions 00106 #endif 00107 00108 /*------------- System Control (SC) ------------------------------------------*/ 00109 typedef struct 00110 { 00111 __IO uint32_t FLASHCFG; /* Flash Accelerator Module */ 00112 uint32_t RESERVED0[31]; 00113 __IO uint32_t PLL0CON; /* Clocking and Power Control */ 00114 __IO uint32_t PLL0CFG; 00115 __I uint32_t PLL0STAT; 00116 __O uint32_t PLL0FEED; 00117 uint32_t RESERVED1[4]; 00118 __IO uint32_t PLL1CON; 00119 __IO uint32_t PLL1CFG; 00120 __I uint32_t PLL1STAT; 00121 __O uint32_t PLL1FEED; 00122 uint32_t RESERVED2[4]; 00123 __IO uint32_t PCON; 00124 __IO uint32_t PCONP; 00125 uint32_t RESERVED3[15]; 00126 __IO uint32_t CCLKCFG; 00127 __IO uint32_t USBCLKCFG; 00128 __IO uint32_t CLKSRCSEL; 00129 __IO uint32_t CANSLEEPCLR; 00130 __IO uint32_t CANWAKEFLAGS; 00131 uint32_t RESERVED4[10]; 00132 __IO uint32_t EXTINT; /* External Interrupts */ 00133 uint32_t RESERVED5; 00134 __IO uint32_t EXTMODE; 00135 __IO uint32_t EXTPOLAR; 00136 uint32_t RESERVED6[12]; 00137 __IO uint32_t RSID; /* Reset */ 00138 uint32_t RESERVED7[7]; 00139 __IO uint32_t SCS; /* Syscon Miscellaneous Registers */ 00140 __IO uint32_t IRCTRIM; /* Clock Dividers */ 00141 __IO uint32_t PCLKSEL0; 00142 __IO uint32_t PCLKSEL1; 00143 uint32_t RESERVED8[4]; 00144 __IO uint32_t USBIntSt; /* USB Device/OTG Interrupt Register */ 00145 __IO uint32_t DMAREQSEL; 00146 __IO uint32_t CLKOUTCFG; /* Clock Output Configuration */ 00147 } LPC_SC_TypeDef; 00148 00149 /*------------- Pin Connect Block (PINCON) -----------------------------------*/ 00150 typedef struct 00151 { 00152 __IO uint32_t PINSEL0; 00153 __IO uint32_t PINSEL1; 00154 __IO uint32_t PINSEL2; 00155 __IO uint32_t PINSEL3; 00156 __IO uint32_t PINSEL4; 00157 __IO uint32_t PINSEL5; 00158 __IO uint32_t PINSEL6; 00159 __IO uint32_t PINSEL7; 00160 __IO uint32_t PINSEL8; 00161 __IO uint32_t PINSEL9; 00162 __IO uint32_t PINSEL10; 00163 uint32_t RESERVED0[5]; 00164 __IO uint32_t PINMODE0; 00165 __IO uint32_t PINMODE1; 00166 __IO uint32_t PINMODE2; 00167 __IO uint32_t PINMODE3; 00168 __IO uint32_t PINMODE4; 00169 __IO uint32_t PINMODE5; 00170 __IO uint32_t PINMODE6; 00171 __IO uint32_t PINMODE7; 00172 __IO uint32_t PINMODE8; 00173 __IO uint32_t PINMODE9; 00174 __IO uint32_t PINMODE_OD0; 00175 __IO uint32_t PINMODE_OD1; 00176 __IO uint32_t PINMODE_OD2; 00177 __IO uint32_t PINMODE_OD3; 00178 __IO uint32_t PINMODE_OD4; 00179 __IO uint32_t I2CPADCFG; 00180 } LPC_PINCON_TypeDef; 00181 00182 /*------------- General Purpose Input/Output (GPIO) --------------------------*/ 00183 typedef struct 00184 { 00185 union { 00186 __IO uint32_t FIODIR; 00187 struct { 00188 __IO uint16_t FIODIRL; 00189 __IO uint16_t FIODIRH; 00190 }; 00191 struct { 00192 __IO uint8_t FIODIR0; 00193 __IO uint8_t FIODIR1; 00194 __IO uint8_t FIODIR2; 00195 __IO uint8_t FIODIR3; 00196 }; 00197 }; 00198 uint32_t RESERVED0[3]; 00199 union { 00200 __IO uint32_t FIOMASK; 00201 struct { 00202 __IO uint16_t FIOMASKL; 00203 __IO uint16_t FIOMASKH; 00204 }; 00205 struct { 00206 __IO uint8_t FIOMASK0; 00207 __IO uint8_t FIOMASK1; 00208 __IO uint8_t FIOMASK2; 00209 __IO uint8_t FIOMASK3; 00210 }; 00211 }; 00212 union { 00213 __IO uint32_t FIOPIN; 00214 struct { 00215 __IO uint16_t FIOPINL; 00216 __IO uint16_t FIOPINH; 00217 }; 00218 struct { 00219 __IO uint8_t FIOPIN0; 00220 __IO uint8_t FIOPIN1; 00221 __IO uint8_t FIOPIN2; 00222 __IO uint8_t FIOPIN3; 00223 }; 00224 }; 00225 union { 00226 __IO uint32_t FIOSET; 00227 struct { 00228 __IO uint16_t FIOSETL; 00229 __IO uint16_t FIOSETH; 00230 }; 00231 struct { 00232 __IO uint8_t FIOSET0; 00233 __IO uint8_t FIOSET1; 00234 __IO uint8_t FIOSET2; 00235 __IO uint8_t FIOSET3; 00236 }; 00237 }; 00238 union { 00239 __O uint32_t FIOCLR; 00240 struct { 00241 __O uint16_t FIOCLRL; 00242 __O uint16_t FIOCLRH; 00243 }; 00244 struct { 00245 __O uint8_t FIOCLR0; 00246 __O uint8_t FIOCLR1; 00247 __O uint8_t FIOCLR2; 00248 __O uint8_t FIOCLR3; 00249 }; 00250 }; 00251 } LPC_GPIO_TypeDef; 00252 00253 typedef struct 00254 { 00255 __I uint32_t IntStatus; 00256 __I uint32_t IO0IntStatR; 00257 __I uint32_t IO0IntStatF; 00258 __O uint32_t IO0IntClr; 00259 __IO uint32_t IO0IntEnR; 00260 __IO uint32_t IO0IntEnF; 00261 uint32_t RESERVED0[3]; 00262 __I uint32_t IO2IntStatR; 00263 __I uint32_t IO2IntStatF; 00264 __O uint32_t IO2IntClr; 00265 __IO uint32_t IO2IntEnR; 00266 __IO uint32_t IO2IntEnF; 00267 } LPC_GPIOINT_TypeDef; 00268 00269 /*------------- Timer (TIM) --------------------------------------------------*/ 00270 typedef struct 00271 { 00272 __IO uint32_t IR; 00273 __IO uint32_t TCR; 00274 __IO uint32_t TC; 00275 __IO uint32_t PR; 00276 __IO uint32_t PC; 00277 __IO uint32_t MCR; 00278 __IO uint32_t MR0; 00279 __IO uint32_t MR1; 00280 __IO uint32_t MR2; 00281 __IO uint32_t MR3; 00282 __IO uint32_t CCR; 00283 __I uint32_t CR0; 00284 __I uint32_t CR1; 00285 uint32_t RESERVED0[2]; 00286 __IO uint32_t EMR; 00287 uint32_t RESERVED1[12]; 00288 __IO uint32_t CTCR; 00289 } LPC_TIM_TypeDef; 00290 00291 /*------------- Pulse-Width Modulation (PWM) ---------------------------------*/ 00292 typedef struct 00293 { 00294 __IO uint32_t IR; 00295 __IO uint32_t TCR; 00296 __IO uint32_t TC; 00297 __IO uint32_t PR; 00298 __IO uint32_t PC; 00299 __IO uint32_t MCR; 00300 __IO uint32_t MR0; 00301 __IO uint32_t MR1; 00302 __IO uint32_t MR2; 00303 __IO uint32_t MR3; 00304 __IO uint32_t CCR; 00305 __I uint32_t CR0; 00306 __I uint32_t CR1; 00307 __I uint32_t CR2; 00308 __I uint32_t CR3; 00309 uint32_t RESERVED0; 00310 __IO uint32_t MR4; 00311 __IO uint32_t MR5; 00312 __IO uint32_t MR6; 00313 __IO uint32_t PCR; 00314 __IO uint32_t LER; 00315 uint32_t RESERVED1[7]; 00316 __IO uint32_t CTCR; 00317 } LPC_PWM_TypeDef; 00318 00319 /*------------- Universal Asynchronous Receiver Transmitter (UART) -----------*/ 00320 typedef struct 00321 { 00322 union { 00323 __I uint8_t RBR; 00324 __O uint8_t THR; 00325 __IO uint8_t DLL; 00326 uint32_t RESERVED0; 00327 }; 00328 union { 00329 __IO uint8_t DLM; 00330 __IO uint32_t IER; 00331 }; 00332 union { 00333 __I uint32_t IIR; 00334 __O uint8_t FCR; 00335 }; 00336 __IO uint8_t LCR; 00337 uint8_t RESERVED1[7]; 00338 __I uint8_t LSR; 00339 uint8_t RESERVED2[7]; 00340 __IO uint8_t SCR; 00341 uint8_t RESERVED3[3]; 00342 __IO uint32_t ACR; 00343 __IO uint8_t ICR; 00344 uint8_t RESERVED4[3]; 00345 __IO uint8_t FDR; 00346 uint8_t RESERVED5[7]; 00347 __IO uint8_t TER; 00348 uint8_t RESERVED6[39]; 00349 __IO uint32_t FIFOLVL; 00350 } LPC_UART_TypeDef; 00351 00352 typedef struct 00353 { 00354 union { 00355 __I uint8_t RBR; 00356 __O uint8_t THR; 00357 __IO uint8_t DLL; 00358 uint32_t RESERVED0; 00359 }; 00360 union { 00361 __IO uint8_t DLM; 00362 __IO uint32_t IER; 00363 }; 00364 union { 00365 __I uint32_t IIR; 00366 __O uint8_t FCR; 00367 }; 00368 __IO uint8_t LCR; 00369 uint8_t RESERVED1[7]; 00370 __I uint8_t LSR; 00371 uint8_t RESERVED2[7]; 00372 __IO uint8_t SCR; 00373 uint8_t RESERVED3[3]; 00374 __IO uint32_t ACR; 00375 __IO uint8_t ICR; 00376 uint8_t RESERVED4[3]; 00377 __IO uint8_t FDR; 00378 uint8_t RESERVED5[7]; 00379 __IO uint8_t TER; 00380 uint8_t RESERVED6[39]; 00381 __IO uint32_t FIFOLVL; 00382 } LPC_UART0_TypeDef; 00383 00384 typedef struct 00385 { 00386 union { 00387 __I uint8_t RBR; 00388 __O uint8_t THR; 00389 __IO uint8_t DLL; 00390 uint32_t RESERVED0; 00391 }; 00392 union { 00393 __IO uint8_t DLM; 00394 __IO uint32_t IER; 00395 }; 00396 union { 00397 __I uint32_t IIR; 00398 __O uint8_t FCR; 00399 }; 00400 __IO uint8_t LCR; 00401 uint8_t RESERVED1[3]; 00402 __IO uint8_t MCR; 00403 uint8_t RESERVED2[3]; 00404 __I uint8_t LSR; 00405 uint8_t RESERVED3[3]; 00406 __I uint8_t MSR; 00407 uint8_t RESERVED4[3]; 00408 __IO uint8_t SCR; 00409 uint8_t RESERVED5[3]; 00410 __IO uint32_t ACR; 00411 uint32_t RESERVED6; 00412 __IO uint32_t FDR; 00413 uint32_t RESERVED7; 00414 __IO uint8_t TER; 00415 uint8_t RESERVED8[27]; 00416 __IO uint8_t RS485CTRL; 00417 uint8_t RESERVED9[3]; 00418 __IO uint8_t ADRMATCH; 00419 uint8_t RESERVED10[3]; 00420 __IO uint8_t RS485DLY; 00421 uint8_t RESERVED11[3]; 00422 __IO uint32_t FIFOLVL; 00423 } LPC_UART1_TypeDef; 00424 00425 /*------------- Serial Peripheral Interface (SPI) ----------------------------*/ 00426 typedef struct 00427 { 00428 __IO uint32_t SPCR; 00429 __I uint32_t SPSR; 00430 __IO uint32_t SPDR; 00431 __IO uint32_t SPCCR; 00432 uint32_t RESERVED0[3]; 00433 __IO uint32_t SPINT; 00434 } LPC_SPI_TypeDef; 00435 00436 /*------------- Synchronous Serial Communication (SSP) -----------------------*/ 00437 typedef struct 00438 { 00439 __IO uint32_t CR0; 00440 __IO uint32_t CR1; 00441 __IO uint32_t DR; 00442 __I uint32_t SR; 00443 __IO uint32_t CPSR; 00444 __IO uint32_t IMSC; 00445 __IO uint32_t RIS; 00446 __IO uint32_t MIS; 00447 __IO uint32_t ICR; 00448 __IO uint32_t DMACR; 00449 } LPC_SSP_TypeDef; 00450 00451 /*------------- Inter-Integrated Circuit (I2C) -------------------------------*/ 00452 typedef struct 00453 { 00454 __IO uint32_t I2CONSET; 00455 __I uint32_t I2STAT; 00456 __IO uint32_t I2DAT; 00457 __IO uint32_t I2ADR0; 00458 __IO uint32_t I2SCLH; 00459 __IO uint32_t I2SCLL; 00460 __O uint32_t I2CONCLR; 00461 __IO uint32_t MMCTRL; 00462 __IO uint32_t I2ADR1; 00463 __IO uint32_t I2ADR2; 00464 __IO uint32_t I2ADR3; 00465 __I uint32_t I2DATA_BUFFER; 00466 __IO uint32_t I2MASK0; 00467 __IO uint32_t I2MASK1; 00468 __IO uint32_t I2MASK2; 00469 __IO uint32_t I2MASK3; 00470 } LPC_I2C_TypeDef; 00471 00472 /*------------- Inter IC Sound (I2S) -----------------------------------------*/ 00473 typedef struct 00474 { 00475 __IO uint32_t I2SDAO; 00476 __IO uint32_t I2SDAI; 00477 __O uint32_t I2STXFIFO; 00478 __I uint32_t I2SRXFIFO; 00479 __I uint32_t I2SSTATE; 00480 __IO uint32_t I2SDMA1; 00481 __IO uint32_t I2SDMA2; 00482 __IO uint32_t I2SIRQ; 00483 __IO uint32_t I2STXRATE; 00484 __IO uint32_t I2SRXRATE; 00485 __IO uint32_t I2STXBITRATE; 00486 __IO uint32_t I2SRXBITRATE; 00487 __IO uint32_t I2STXMODE; 00488 __IO uint32_t I2SRXMODE; 00489 } LPC_I2S_TypeDef; 00490 00491 /*------------- Repetitive Interrupt Timer (RIT) -----------------------------*/ 00492 typedef struct 00493 { 00494 __IO uint32_t RICOMPVAL; 00495 __IO uint32_t RIMASK; 00496 __IO uint8_t RICTRL; 00497 uint8_t RESERVED0[3]; 00498 __IO uint32_t RICOUNTER; 00499 } LPC_RIT_TypeDef; 00500 00501 /*------------- Real-Time Clock (RTC) ----------------------------------------*/ 00502 typedef struct 00503 { 00504 __IO uint8_t ILR; 00505 uint8_t RESERVED0[7]; 00506 __IO uint8_t CCR; 00507 uint8_t RESERVED1[3]; 00508 __IO uint8_t CIIR; 00509 uint8_t RESERVED2[3]; 00510 __IO uint8_t AMR; 00511 uint8_t RESERVED3[3]; 00512 __I uint32_t CTIME0; 00513 __I uint32_t CTIME1; 00514 __I uint32_t CTIME2; 00515 __IO uint8_t SEC; 00516 uint8_t RESERVED4[3]; 00517 __IO uint8_t MIN; 00518 uint8_t RESERVED5[3]; 00519 __IO uint8_t HOUR; 00520 uint8_t RESERVED6[3]; 00521 __IO uint8_t DOM; 00522 uint8_t RESERVED7[3]; 00523 __IO uint8_t DOW; 00524 uint8_t RESERVED8[3]; 00525 __IO uint16_t DOY; 00526 uint16_t RESERVED9; 00527 __IO uint8_t MONTH; 00528 uint8_t RESERVED10[3]; 00529 __IO uint16_t YEAR; 00530 uint16_t RESERVED11; 00531 __IO uint32_t CALIBRATION; 00532 __IO uint32_t GPREG0; 00533 __IO uint32_t GPREG1; 00534 __IO uint32_t GPREG2; 00535 __IO uint32_t GPREG3; 00536 __IO uint32_t GPREG4; 00537 __IO uint8_t RTC_AUXEN; 00538 uint8_t RESERVED12[3]; 00539 __IO uint8_t RTC_AUX; 00540 uint8_t RESERVED13[3]; 00541 __IO uint8_t ALSEC; 00542 uint8_t RESERVED14[3]; 00543 __IO uint8_t ALMIN; 00544 uint8_t RESERVED15[3]; 00545 __IO uint8_t ALHOUR; 00546 uint8_t RESERVED16[3]; 00547 __IO uint8_t ALDOM; 00548 uint8_t RESERVED17[3]; 00549 __IO uint8_t ALDOW; 00550 uint8_t RESERVED18[3]; 00551 __IO uint16_t ALDOY; 00552 uint16_t RESERVED19; 00553 __IO uint8_t ALMON; 00554 uint8_t RESERVED20[3]; 00555 __IO uint16_t ALYEAR; 00556 uint16_t RESERVED21; 00557 } LPC_RTC_TypeDef; 00558 00559 /*------------- Watchdog Timer (WDT) -----------------------------------------*/ 00560 typedef struct 00561 { 00562 __IO uint8_t WDMOD; 00563 uint8_t RESERVED0[3]; 00564 __IO uint32_t WDTC; 00565 __O uint8_t WDFEED; 00566 uint8_t RESERVED1[3]; 00567 __I uint32_t WDTV; 00568 __IO uint32_t WDCLKSEL; 00569 } LPC_WDT_TypeDef; 00570 00571 /*------------- Analog-to-Digital Converter (ADC) ----------------------------*/ 00572 typedef struct 00573 { 00574 __IO uint32_t ADCR; 00575 __IO uint32_t ADGDR; 00576 uint32_t RESERVED0; 00577 __IO uint32_t ADINTEN; 00578 __I uint32_t ADDR0; 00579 __I uint32_t ADDR1; 00580 __I uint32_t ADDR2; 00581 __I uint32_t ADDR3; 00582 __I uint32_t ADDR4; 00583 __I uint32_t ADDR5; 00584 __I uint32_t ADDR6; 00585 __I uint32_t ADDR7; 00586 __I uint32_t ADSTAT; 00587 __IO uint32_t ADTRM; 00588 } LPC_ADC_TypeDef; 00589 00590 /*------------- Digital-to-Analog Converter (DAC) ----------------------------*/ 00591 typedef struct 00592 { 00593 __IO uint32_t DACR; 00594 __IO uint32_t DACCTRL; 00595 __IO uint16_t DACCNTVAL; 00596 } LPC_DAC_TypeDef; 00597 00598 /*------------- Motor Control Pulse-Width Modulation (MCPWM) -----------------*/ 00599 typedef struct 00600 { 00601 __I uint32_t MCCON; 00602 __O uint32_t MCCON_SET; 00603 __O uint32_t MCCON_CLR; 00604 __I uint32_t MCCAPCON; 00605 __O uint32_t MCCAPCON_SET; 00606 __O uint32_t MCCAPCON_CLR; 00607 __IO uint32_t MCTIM0; 00608 __IO uint32_t MCTIM1; 00609 __IO uint32_t MCTIM2; 00610 __IO uint32_t MCPER0; 00611 __IO uint32_t MCPER1; 00612 __IO uint32_t MCPER2; 00613 __IO uint32_t MCPW0; 00614 __IO uint32_t MCPW1; 00615 __IO uint32_t MCPW2; 00616 __IO uint32_t MCDEADTIME; 00617 __IO uint32_t MCCCP; 00618 __IO uint32_t MCCR0; 00619 __IO uint32_t MCCR1; 00620 __IO uint32_t MCCR2; 00621 __I uint32_t MCINTEN; 00622 __O uint32_t MCINTEN_SET; 00623 __O uint32_t MCINTEN_CLR; 00624 __I uint32_t MCCNTCON; 00625 __O uint32_t MCCNTCON_SET; 00626 __O uint32_t MCCNTCON_CLR; 00627 __I uint32_t MCINTFLAG; 00628 __O uint32_t MCINTFLAG_SET; 00629 __O uint32_t MCINTFLAG_CLR; 00630 __O uint32_t MCCAP_CLR; 00631 } LPC_MCPWM_TypeDef; 00632 00633 /*------------- Quadrature Encoder Interface (QEI) ---------------------------*/ 00634 typedef struct 00635 { 00636 __O uint32_t QEICON; 00637 __I uint32_t QEISTAT; 00638 __IO uint32_t QEICONF; 00639 __I uint32_t QEIPOS; 00640 __IO uint32_t QEIMAXPOS; 00641 __IO uint32_t CMPOS0; 00642 __IO uint32_t CMPOS1; 00643 __IO uint32_t CMPOS2; 00644 __I uint32_t INXCNT; 00645 __IO uint32_t INXCMP; 00646 __IO uint32_t QEILOAD; 00647 __I uint32_t QEITIME; 00648 __I uint32_t QEIVEL; 00649 __I uint32_t QEICAP; 00650 __IO uint32_t VELCOMP; 00651 __IO uint32_t FILTER; 00652 uint32_t RESERVED0[998]; 00653 __O uint32_t QEIIEC; 00654 __O uint32_t QEIIES; 00655 __I uint32_t QEIINTSTAT; 00656 __I uint32_t QEIIE; 00657 __O uint32_t QEICLR; 00658 __O uint32_t QEISET; 00659 } LPC_QEI_TypeDef; 00660 00661 /*------------- Controller Area Network (CAN) --------------------------------*/ 00662 typedef struct 00663 { 00664 __IO uint32_t mask[512]; /* ID Masks */ 00665 } LPC_CANAF_RAM_TypeDef; 00666 00667 typedef struct /* Acceptance Filter Registers */ 00668 { 00669 __IO uint32_t AFMR; 00670 __IO uint32_t SFF_sa; 00671 __IO uint32_t SFF_GRP_sa; 00672 __IO uint32_t EFF_sa; 00673 __IO uint32_t EFF_GRP_sa; 00674 __IO uint32_t ENDofTable; 00675 __I uint32_t LUTerrAd; 00676 __I uint32_t LUTerr; 00677 __IO uint32_t FCANIE; 00678 __IO uint32_t FCANIC0; 00679 __IO uint32_t FCANIC1; 00680 } LPC_CANAF_TypeDef; 00681 00682 typedef struct /* Central Registers */ 00683 { 00684 __I uint32_t CANTxSR; 00685 __I uint32_t CANRxSR; 00686 __I uint32_t CANMSR; 00687 } LPC_CANCR_TypeDef; 00688 00689 typedef struct /* Controller Registers */ 00690 { 00691 __IO uint32_t MOD; 00692 __O uint32_t CMR; 00693 __IO uint32_t GSR; 00694 __I uint32_t ICR; 00695 __IO uint32_t IER; 00696 __IO uint32_t BTR; 00697 __IO uint32_t EWL; 00698 __I uint32_t SR; 00699 __IO uint32_t RFS; 00700 __IO uint32_t RID; 00701 __IO uint32_t RDA; 00702 __IO uint32_t RDB; 00703 __IO uint32_t TFI1; 00704 __IO uint32_t TID1; 00705 __IO uint32_t TDA1; 00706 __IO uint32_t TDB1; 00707 __IO uint32_t TFI2; 00708 __IO uint32_t TID2; 00709 __IO uint32_t TDA2; 00710 __IO uint32_t TDB2; 00711 __IO uint32_t TFI3; 00712 __IO uint32_t TID3; 00713 __IO uint32_t TDA3; 00714 __IO uint32_t TDB3; 00715 } LPC_CAN_TypeDef; 00716 00717 /*------------- General Purpose Direct Memory Access (GPDMA) -----------------*/ 00718 typedef struct /* Common Registers */ 00719 { 00720 __I uint32_t DMACIntStat; 00721 __I uint32_t DMACIntTCStat; 00722 __O uint32_t DMACIntTCClear; 00723 __I uint32_t DMACIntErrStat; 00724 __O uint32_t DMACIntErrClr; 00725 __I uint32_t DMACRawIntTCStat; 00726 __I uint32_t DMACRawIntErrStat; 00727 __I uint32_t DMACEnbldChns; 00728 __IO uint32_t DMACSoftBReq; 00729 __IO uint32_t DMACSoftSReq; 00730 __IO uint32_t DMACSoftLBReq; 00731 __IO uint32_t DMACSoftLSReq; 00732 __IO uint32_t DMACConfig; 00733 __IO uint32_t DMACSync; 00734 } LPC_GPDMA_TypeDef; 00735 00736 typedef struct /* Channel Registers */ 00737 { 00738 __IO uint32_t DMACCSrcAddr; 00739 __IO uint32_t DMACCDestAddr; 00740 __IO uint32_t DMACCLLI; 00741 __IO uint32_t DMACCControl; 00742 __IO uint32_t DMACCConfig; 00743 } LPC_GPDMACH_TypeDef; 00744 00745 /*------------- Universal Serial Bus (USB) -----------------------------------*/ 00746 typedef struct 00747 { 00748 __I uint32_t HcRevision; /* USB Host Registers */ 00749 __IO uint32_t HcControl; 00750 __IO uint32_t HcCommandStatus; 00751 __IO uint32_t HcInterruptStatus; 00752 __IO uint32_t HcInterruptEnable; 00753 __IO uint32_t HcInterruptDisable; 00754 __IO uint32_t HcHCCA; 00755 __I uint32_t HcPeriodCurrentED; 00756 __IO uint32_t HcControlHeadED; 00757 __IO uint32_t HcControlCurrentED; 00758 __IO uint32_t HcBulkHeadED; 00759 __IO uint32_t HcBulkCurrentED; 00760 __I uint32_t HcDoneHead; 00761 __IO uint32_t HcFmInterval; 00762 __I uint32_t HcFmRemaining; 00763 __I uint32_t HcFmNumber; 00764 __IO uint32_t HcPeriodicStart; 00765 __IO uint32_t HcLSTreshold; 00766 __IO uint32_t HcRhDescriptorA; 00767 __IO uint32_t HcRhDescriptorB; 00768 __IO uint32_t HcRhStatus; 00769 __IO uint32_t HcRhPortStatus1; 00770 __IO uint32_t HcRhPortStatus2; 00771 uint32_t RESERVED0[40]; 00772 __I uint32_t Module_ID; 00773 00774 __I uint32_t OTGIntSt; /* USB On-The-Go Registers */ 00775 __IO uint32_t OTGIntEn; 00776 __O uint32_t OTGIntSet; 00777 __O uint32_t OTGIntClr; 00778 __IO uint32_t OTGStCtrl; 00779 __IO uint32_t OTGTmr; 00780 uint32_t RESERVED1[58]; 00781 00782 __I uint32_t USBDevIntSt; /* USB Device Interrupt Registers */ 00783 __IO uint32_t USBDevIntEn; 00784 __O uint32_t USBDevIntClr; 00785 __O uint32_t USBDevIntSet; 00786 00787 __O uint32_t USBCmdCode; /* USB Device SIE Command Registers */ 00788 __I uint32_t USBCmdData; 00789 00790 __I uint32_t USBRxData; /* USB Device Transfer Registers */ 00791 __O uint32_t USBTxData; 00792 __I uint32_t USBRxPLen; 00793 __O uint32_t USBTxPLen; 00794 __IO uint32_t USBCtrl; 00795 __O uint32_t USBDevIntPri; 00796 00797 __I uint32_t USBEpIntSt; /* USB Device Endpoint Interrupt Regs */ 00798 __IO uint32_t USBEpIntEn; 00799 __O uint32_t USBEpIntClr; 00800 __O uint32_t USBEpIntSet; 00801 __O uint32_t USBEpIntPri; 00802 00803 __IO uint32_t USBReEp; /* USB Device Endpoint Realization Reg*/ 00804 __O uint32_t USBEpInd; 00805 __IO uint32_t USBMaxPSize; 00806 00807 __I uint32_t USBDMARSt; /* USB Device DMA Registers */ 00808 __O uint32_t USBDMARClr; 00809 __O uint32_t USBDMARSet; 00810 uint32_t RESERVED2[9]; 00811 __IO uint32_t USBUDCAH; 00812 __I uint32_t USBEpDMASt; 00813 __O uint32_t USBEpDMAEn; 00814 __O uint32_t USBEpDMADis; 00815 __I uint32_t USBDMAIntSt; 00816 __IO uint32_t USBDMAIntEn; 00817 uint32_t RESERVED3[2]; 00818 __I uint32_t USBEoTIntSt; 00819 __O uint32_t USBEoTIntClr; 00820 __O uint32_t USBEoTIntSet; 00821 __I uint32_t USBNDDRIntSt; 00822 __O uint32_t USBNDDRIntClr; 00823 __O uint32_t USBNDDRIntSet; 00824 __I uint32_t USBSysErrIntSt; 00825 __O uint32_t USBSysErrIntClr; 00826 __O uint32_t USBSysErrIntSet; 00827 uint32_t RESERVED4[15]; 00828 00829 union { 00830 __I uint32_t I2C_RX; /* USB OTG I2C Registers */ 00831 __O uint32_t I2C_TX; 00832 }; 00833 __I uint32_t I2C_STS; 00834 __IO uint32_t I2C_CTL; 00835 __IO uint32_t I2C_CLKHI; 00836 __O uint32_t I2C_CLKLO; 00837 uint32_t RESERVED5[824]; 00838 00839 union { 00840 __IO uint32_t USBClkCtrl; /* USB Clock Control Registers */ 00841 __IO uint32_t OTGClkCtrl; 00842 }; 00843 union { 00844 __I uint32_t USBClkSt; 00845 __I uint32_t OTGClkSt; 00846 }; 00847 } LPC_USB_TypeDef; 00848 00849 /*------------- Ethernet Media Access Controller (EMAC) ----------------------*/ 00850 typedef struct 00851 { 00852 __IO uint32_t MAC1; /* MAC Registers */ 00853 __IO uint32_t MAC2; 00854 __IO uint32_t IPGT; 00855 __IO uint32_t IPGR; 00856 __IO uint32_t CLRT; 00857 __IO uint32_t MAXF; 00858 __IO uint32_t SUPP; 00859 __IO uint32_t TEST; 00860 __IO uint32_t MCFG; 00861 __IO uint32_t MCMD; 00862 __IO uint32_t MADR; 00863 __O uint32_t MWTD; 00864 __I uint32_t MRDD; 00865 __I uint32_t MIND; 00866 uint32_t RESERVED0[2]; 00867 __IO uint32_t SA0; 00868 __IO uint32_t SA1; 00869 __IO uint32_t SA2; 00870 uint32_t RESERVED1[45]; 00871 __IO uint32_t Command; /* Control Registers */ 00872 __I uint32_t Status; 00873 __IO uint32_t RxDescriptor; 00874 __IO uint32_t RxStatus; 00875 __IO uint32_t RxDescriptorNumber; 00876 __I uint32_t RxProduceIndex; 00877 __IO uint32_t RxConsumeIndex; 00878 __IO uint32_t TxDescriptor; 00879 __IO uint32_t TxStatus; 00880 __IO uint32_t TxDescriptorNumber; 00881 __IO uint32_t TxProduceIndex; 00882 __I uint32_t TxConsumeIndex; 00883 uint32_t RESERVED2[10]; 00884 __I uint32_t TSV0; 00885 __I uint32_t TSV1; 00886 __I uint32_t RSV; 00887 uint32_t RESERVED3[3]; 00888 __IO uint32_t FlowControlCounter; 00889 __I uint32_t FlowControlStatus; 00890 uint32_t RESERVED4[34]; 00891 __IO uint32_t RxFilterCtrl; /* Rx Filter Registers */ 00892 __IO uint32_t RxFilterWoLStatus; 00893 __IO uint32_t RxFilterWoLClear; 00894 uint32_t RESERVED5; 00895 __IO uint32_t HashFilterL; 00896 __IO uint32_t HashFilterH; 00897 uint32_t RESERVED6[882]; 00898 __I uint32_t IntStatus; /* Module Control Registers */ 00899 __IO uint32_t IntEnable; 00900 __O uint32_t IntClear; 00901 __O uint32_t IntSet; 00902 uint32_t RESERVED7; 00903 __IO uint32_t PowerDown; 00904 uint32_t RESERVED8; 00905 __IO uint32_t Module_ID; 00906 } LPC_EMAC_TypeDef; 00907 00908 #if defined ( __CC_ARM ) 00909 #pragma no_anon_unions 00910 #endif 00911 00912 00913 /******************************************************************************/ 00914 /* Peripheral memory map */ 00915 /******************************************************************************/ 00916 /* Base addresses */ 00917 #define LPC_FLASH_BASE (0x00000000UL) 00918 #define LPC_RAM_BASE (0x10000000UL) 00919 #define LPC_GPIO_BASE (0x2009C000UL) 00920 #define LPC_APB0_BASE (0x40000000UL) 00921 #define LPC_APB1_BASE (0x40080000UL) 00922 #define LPC_AHB_BASE (0x50000000UL) 00923 #define LPC_CM3_BASE (0xE0000000UL) 00924 00925 /* APB0 peripherals */ 00926 #define LPC_WDT_BASE (LPC_APB0_BASE + 0x00000) 00927 #define LPC_TIM0_BASE (LPC_APB0_BASE + 0x04000) 00928 #define LPC_TIM1_BASE (LPC_APB0_BASE + 0x08000) 00929 #define LPC_UART0_BASE (LPC_APB0_BASE + 0x0C000) 00930 #define LPC_UART1_BASE (LPC_APB0_BASE + 0x10000) 00931 #define LPC_PWM1_BASE (LPC_APB0_BASE + 0x18000) 00932 #define LPC_I2C0_BASE (LPC_APB0_BASE + 0x1C000) 00933 #define LPC_SPI_BASE (LPC_APB0_BASE + 0x20000) 00934 #define LPC_RTC_BASE (LPC_APB0_BASE + 0x24000) 00935 #define LPC_GPIOINT_BASE (LPC_APB0_BASE + 0x28080) 00936 #define LPC_PINCON_BASE (LPC_APB0_BASE + 0x2C000) 00937 #define LPC_SSP1_BASE (LPC_APB0_BASE + 0x30000) 00938 #define LPC_ADC_BASE (LPC_APB0_BASE + 0x34000) 00939 #define LPC_CANAF_RAM_BASE (LPC_APB0_BASE + 0x38000) 00940 #define LPC_CANAF_BASE (LPC_APB0_BASE + 0x3C000) 00941 #define LPC_CANCR_BASE (LPC_APB0_BASE + 0x40000) 00942 #define LPC_CAN1_BASE (LPC_APB0_BASE + 0x44000) 00943 #define LPC_CAN2_BASE (LPC_APB0_BASE + 0x48000) 00944 #define LPC_I2C1_BASE (LPC_APB0_BASE + 0x5C000) 00945 00946 /* APB1 peripherals */ 00947 #define LPC_SSP0_BASE (LPC_APB1_BASE + 0x08000) 00948 #define LPC_DAC_BASE (LPC_APB1_BASE + 0x0C000) 00949 #define LPC_TIM2_BASE (LPC_APB1_BASE + 0x10000) 00950 #define LPC_TIM3_BASE (LPC_APB1_BASE + 0x14000) 00951 #define LPC_UART2_BASE (LPC_APB1_BASE + 0x18000) 00952 #define LPC_UART3_BASE (LPC_APB1_BASE + 0x1C000) 00953 #define LPC_I2C2_BASE (LPC_APB1_BASE + 0x20000) 00954 #define LPC_I2S_BASE (LPC_APB1_BASE + 0x28000) 00955 #define LPC_RIT_BASE (LPC_APB1_BASE + 0x30000) 00956 #define LPC_MCPWM_BASE (LPC_APB1_BASE + 0x38000) 00957 #define LPC_QEI_BASE (LPC_APB1_BASE + 0x3C000) 00958 #define LPC_SC_BASE (LPC_APB1_BASE + 0x7C000) 00959 00960 /* AHB peripherals */ 00961 #define LPC_EMAC_BASE (LPC_AHB_BASE + 0x00000) 00962 #define LPC_GPDMA_BASE (LPC_AHB_BASE + 0x04000) 00963 #define LPC_GPDMACH0_BASE (LPC_AHB_BASE + 0x04100) 00964 #define LPC_GPDMACH1_BASE (LPC_AHB_BASE + 0x04120) 00965 #define LPC_GPDMACH2_BASE (LPC_AHB_BASE + 0x04140) 00966 #define LPC_GPDMACH3_BASE (LPC_AHB_BASE + 0x04160) 00967 #define LPC_GPDMACH4_BASE (LPC_AHB_BASE + 0x04180) 00968 #define LPC_GPDMACH5_BASE (LPC_AHB_BASE + 0x041A0) 00969 #define LPC_GPDMACH6_BASE (LPC_AHB_BASE + 0x041C0) 00970 #define LPC_GPDMACH7_BASE (LPC_AHB_BASE + 0x041E0) 00971 #define LPC_USB_BASE (LPC_AHB_BASE + 0x0C000) 00972 00973 /* GPIOs */ 00974 #define LPC_GPIO0_BASE (LPC_GPIO_BASE + 0x00000) 00975 #define LPC_GPIO1_BASE (LPC_GPIO_BASE + 0x00020) 00976 #define LPC_GPIO2_BASE (LPC_GPIO_BASE + 0x00040) 00977 #define LPC_GPIO3_BASE (LPC_GPIO_BASE + 0x00060) 00978 #define LPC_GPIO4_BASE (LPC_GPIO_BASE + 0x00080) 00979 00980 00981 /******************************************************************************/ 00982 /* Peripheral declaration */ 00983 /******************************************************************************/ 00984 #define LPC_SC ((LPC_SC_TypeDef *) LPC_SC_BASE ) 00985 #define LPC_GPIO0 ((LPC_GPIO_TypeDef *) LPC_GPIO0_BASE ) 00986 #define LPC_GPIO1 ((LPC_GPIO_TypeDef *) LPC_GPIO1_BASE ) 00987 #define LPC_GPIO2 ((LPC_GPIO_TypeDef *) LPC_GPIO2_BASE ) 00988 #define LPC_GPIO3 ((LPC_GPIO_TypeDef *) LPC_GPIO3_BASE ) 00989 #define LPC_GPIO4 ((LPC_GPIO_TypeDef *) LPC_GPIO4_BASE ) 00990 #define LPC_WDT ((LPC_WDT_TypeDef *) LPC_WDT_BASE ) 00991 #define LPC_TIM0 ((LPC_TIM_TypeDef *) LPC_TIM0_BASE ) 00992 #define LPC_TIM1 ((LPC_TIM_TypeDef *) LPC_TIM1_BASE ) 00993 #define LPC_TIM2 ((LPC_TIM_TypeDef *) LPC_TIM2_BASE ) 00994 #define LPC_TIM3 ((LPC_TIM_TypeDef *) LPC_TIM3_BASE ) 00995 #define LPC_RIT ((LPC_RIT_TypeDef *) LPC_RIT_BASE ) 00996 #define LPC_UART0 ((LPC_UART0_TypeDef *) LPC_UART0_BASE ) 00997 #define LPC_UART1 ((LPC_UART1_TypeDef *) LPC_UART1_BASE ) 00998 #define LPC_UART2 ((LPC_UART_TypeDef *) LPC_UART2_BASE ) 00999 #define LPC_UART3 ((LPC_UART_TypeDef *) LPC_UART3_BASE ) 01000 #define LPC_PWM1 ((LPC_PWM_TypeDef *) LPC_PWM1_BASE ) 01001 #define LPC_I2C0 ((LPC_I2C_TypeDef *) LPC_I2C0_BASE ) 01002 #define LPC_I2C1 ((LPC_I2C_TypeDef *) LPC_I2C1_BASE ) 01003 #define LPC_I2C2 ((LPC_I2C_TypeDef *) LPC_I2C2_BASE ) 01004 #define LPC_I2S ((LPC_I2S_TypeDef *) LPC_I2S_BASE ) 01005 #define LPC_SPI ((LPC_SPI_TypeDef *) LPC_SPI_BASE ) 01006 #define LPC_RTC ((LPC_RTC_TypeDef *) LPC_RTC_BASE ) 01007 #define LPC_GPIOINT ((LPC_GPIOINT_TypeDef *) LPC_GPIOINT_BASE ) 01008 #define LPC_PINCON ((LPC_PINCON_TypeDef *) LPC_PINCON_BASE ) 01009 #define LPC_SSP0 ((LPC_SSP_TypeDef *) LPC_SSP0_BASE ) 01010 #define LPC_SSP1 ((LPC_SSP_TypeDef *) LPC_SSP1_BASE ) 01011 #define LPC_ADC ((LPC_ADC_TypeDef *) LPC_ADC_BASE ) 01012 #define LPC_DAC ((LPC_DAC_TypeDef *) LPC_DAC_BASE ) 01013 #define LPC_CANAF_RAM ((LPC_CANAF_RAM_TypeDef *) LPC_CANAF_RAM_BASE) 01014 #define LPC_CANAF ((LPC_CANAF_TypeDef *) LPC_CANAF_BASE ) 01015 #define LPC_CANCR ((LPC_CANCR_TypeDef *) LPC_CANCR_BASE ) 01016 #define LPC_CAN1 ((LPC_CAN_TypeDef *) LPC_CAN1_BASE ) 01017 #define LPC_CAN2 ((LPC_CAN_TypeDef *) LPC_CAN2_BASE ) 01018 #define LPC_MCPWM ((LPC_MCPWM_TypeDef *) LPC_MCPWM_BASE ) 01019 #define LPC_QEI ((LPC_QEI_TypeDef *) LPC_QEI_BASE ) 01020 #define LPC_EMAC ((LPC_EMAC_TypeDef *) LPC_EMAC_BASE ) 01021 #define LPC_GPDMA ((LPC_GPDMA_TypeDef *) LPC_GPDMA_BASE ) 01022 #define LPC_GPDMACH0 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH0_BASE ) 01023 #define LPC_GPDMACH1 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH1_BASE ) 01024 #define LPC_GPDMACH2 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH2_BASE ) 01025 #define LPC_GPDMACH3 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH3_BASE ) 01026 #define LPC_GPDMACH4 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH4_BASE ) 01027 #define LPC_GPDMACH5 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH5_BASE ) 01028 #define LPC_GPDMACH6 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH6_BASE ) 01029 #define LPC_GPDMACH7 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH7_BASE ) 01030 #define LPC_USB ((LPC_USB_TypeDef *) LPC_USB_BASE ) 01031 01032 #endif // __LPC17xx_H__
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