Some improvement on mrcrsch's RF24 library
Fork of RF24_fork by
RF24.cpp@13:d295c8b3f742, 2018-09-19 (annotated)
- Committer:
- gume
- Date:
- Wed Sep 19 22:50:11 2018 +0000
- Revision:
- 13:d295c8b3f742
- Parent:
- 10:0a3f44454ee7
adapted radio presence test
Who changed what in which revision?
User | Revision | Line number | New contents of line |
---|---|---|---|
akashvibhute | 0:bb74812ac6bb | 1 | /* |
akashvibhute | 0:bb74812ac6bb | 2 | Copyright (C) 2011 J. Coliz <maniacbug@ymail.com> |
akashvibhute | 0:bb74812ac6bb | 3 | |
akashvibhute | 0:bb74812ac6bb | 4 | This program is free software; you can redistribute it and/or |
akashvibhute | 0:bb74812ac6bb | 5 | modify it under the terms of the GNU General Public License |
akashvibhute | 0:bb74812ac6bb | 6 | version 2 as published by the Free Software Foundation. |
akashvibhute | 0:bb74812ac6bb | 7 | */ |
akashvibhute | 6:5cc7136648d1 | 8 | |
akashvibhute | 3:e94be00fd19e | 9 | /* |
akashvibhute | 3:e94be00fd19e | 10 | * Mbed support added by Akash Vibhute <akash.roboticist@gmail.com> |
akashvibhute | 3:e94be00fd19e | 11 | * Porting completed on Nov/05/2015 |
akashvibhute | 3:e94be00fd19e | 12 | * |
akashvibhute | 6:5cc7136648d1 | 13 | * Updated 1: Synced with TMRh20's RF24 library on Nov/04/2015 from https://github.com/TMRh20 |
akashvibhute | 6:5cc7136648d1 | 14 | * Updated 2: Synced with TMRh20's RF24 library on Apr/18/2015 from https://github.com/TMRh20 |
akashvibhute | 3:e94be00fd19e | 15 | * |
akashvibhute | 3:e94be00fd19e | 16 | */ |
akashvibhute | 6:5cc7136648d1 | 17 | |
akashvibhute | 2:3bdf0d9bb71f | 18 | #include "nRF24L01.h" |
akashvibhute | 2:3bdf0d9bb71f | 19 | #include "RF24_config.h" |
akashvibhute | 0:bb74812ac6bb | 20 | #include "RF24.h" |
akashvibhute | 0:bb74812ac6bb | 21 | |
akashvibhute | 0:bb74812ac6bb | 22 | /****************************************************************************/ |
akashvibhute | 0:bb74812ac6bb | 23 | |
akashvibhute | 2:3bdf0d9bb71f | 24 | void RF24::csn(bool mode) |
akashvibhute | 0:bb74812ac6bb | 25 | { |
akashvibhute | 6:5cc7136648d1 | 26 | |
akashvibhute | 6:5cc7136648d1 | 27 | csn_pin = mode; |
akashvibhute | 6:5cc7136648d1 | 28 | |
akashvibhute | 0:bb74812ac6bb | 29 | } |
akashvibhute | 0:bb74812ac6bb | 30 | |
akashvibhute | 0:bb74812ac6bb | 31 | /****************************************************************************/ |
akashvibhute | 0:bb74812ac6bb | 32 | |
akashvibhute | 2:3bdf0d9bb71f | 33 | void RF24::ce(bool level) |
akashvibhute | 0:bb74812ac6bb | 34 | { |
akashvibhute | 6:5cc7136648d1 | 35 | ce_pin = level; |
akashvibhute | 6:5cc7136648d1 | 36 | |
akashvibhute | 0:bb74812ac6bb | 37 | } |
akashvibhute | 0:bb74812ac6bb | 38 | |
akashvibhute | 0:bb74812ac6bb | 39 | /****************************************************************************/ |
akashvibhute | 0:bb74812ac6bb | 40 | |
akashvibhute | 6:5cc7136648d1 | 41 | inline void RF24::beginTransaction() { |
akashvibhute | 6:5cc7136648d1 | 42 | csn(LOW); |
mrcrsch | 10:0a3f44454ee7 | 43 | |
akashvibhute | 6:5cc7136648d1 | 44 | } |
akashvibhute | 2:3bdf0d9bb71f | 45 | |
akashvibhute | 2:3bdf0d9bb71f | 46 | /****************************************************************************/ |
akashvibhute | 2:3bdf0d9bb71f | 47 | |
akashvibhute | 6:5cc7136648d1 | 48 | inline void RF24::endTransaction() { |
akashvibhute | 6:5cc7136648d1 | 49 | csn(HIGH); |
akashvibhute | 6:5cc7136648d1 | 50 | |
akashvibhute | 6:5cc7136648d1 | 51 | } |
akashvibhute | 2:3bdf0d9bb71f | 52 | |
akashvibhute | 2:3bdf0d9bb71f | 53 | /****************************************************************************/ |
akashvibhute | 2:3bdf0d9bb71f | 54 | |
akashvibhute | 0:bb74812ac6bb | 55 | uint8_t RF24::read_register(uint8_t reg, uint8_t* buf, uint8_t len) |
akashvibhute | 0:bb74812ac6bb | 56 | { |
akashvibhute | 6:5cc7136648d1 | 57 | uint8_t status; |
akashvibhute | 0:bb74812ac6bb | 58 | |
akashvibhute | 3:e94be00fd19e | 59 | |
akashvibhute | 6:5cc7136648d1 | 60 | beginTransaction(); |
akashvibhute | 6:5cc7136648d1 | 61 | status = spi.write( R_REGISTER | ( REGISTER_MASK & reg ) ); |
akashvibhute | 6:5cc7136648d1 | 62 | while ( len-- ){ |
akashvibhute | 6:5cc7136648d1 | 63 | *buf++ = spi.write(0xff); |
akashvibhute | 6:5cc7136648d1 | 64 | } |
akashvibhute | 6:5cc7136648d1 | 65 | endTransaction(); |
akashvibhute | 6:5cc7136648d1 | 66 | |
akashvibhute | 6:5cc7136648d1 | 67 | |
akashvibhute | 6:5cc7136648d1 | 68 | |
akashvibhute | 6:5cc7136648d1 | 69 | return status; |
akashvibhute | 0:bb74812ac6bb | 70 | } |
akashvibhute | 0:bb74812ac6bb | 71 | |
akashvibhute | 0:bb74812ac6bb | 72 | /****************************************************************************/ |
akashvibhute | 0:bb74812ac6bb | 73 | |
akashvibhute | 0:bb74812ac6bb | 74 | uint8_t RF24::read_register(uint8_t reg) |
akashvibhute | 0:bb74812ac6bb | 75 | { |
mrcrsch | 10:0a3f44454ee7 | 76 | uint8_t result; |
akashvibhute | 0:bb74812ac6bb | 77 | |
akashvibhute | 6:5cc7136648d1 | 78 | beginTransaction(); |
akashvibhute | 6:5cc7136648d1 | 79 | spi.write( R_REGISTER | ( REGISTER_MASK & reg ) ); |
akashvibhute | 6:5cc7136648d1 | 80 | result = spi.write(0xff); |
akashvibhute | 6:5cc7136648d1 | 81 | endTransaction(); |
akashvibhute | 3:e94be00fd19e | 82 | |
akashvibhute | 6:5cc7136648d1 | 83 | |
akashvibhute | 6:5cc7136648d1 | 84 | |
akashvibhute | 6:5cc7136648d1 | 85 | return result; |
akashvibhute | 0:bb74812ac6bb | 86 | } |
akashvibhute | 0:bb74812ac6bb | 87 | |
akashvibhute | 0:bb74812ac6bb | 88 | /****************************************************************************/ |
akashvibhute | 0:bb74812ac6bb | 89 | |
akashvibhute | 0:bb74812ac6bb | 90 | uint8_t RF24::write_register(uint8_t reg, const uint8_t* buf, uint8_t len) |
akashvibhute | 0:bb74812ac6bb | 91 | { |
mrcrsch | 10:0a3f44454ee7 | 92 | uint8_t status; |
akashvibhute | 3:e94be00fd19e | 93 | |
akashvibhute | 6:5cc7136648d1 | 94 | beginTransaction(); |
akashvibhute | 6:5cc7136648d1 | 95 | status = spi.write( W_REGISTER | ( REGISTER_MASK & reg ) ); |
akashvibhute | 6:5cc7136648d1 | 96 | while ( len-- ) |
akashvibhute | 6:5cc7136648d1 | 97 | spi.write(*buf++); |
akashvibhute | 6:5cc7136648d1 | 98 | endTransaction(); |
akashvibhute | 6:5cc7136648d1 | 99 | |
akashvibhute | 6:5cc7136648d1 | 100 | |
akashvibhute | 6:5cc7136648d1 | 101 | |
akashvibhute | 6:5cc7136648d1 | 102 | return status; |
akashvibhute | 0:bb74812ac6bb | 103 | } |
akashvibhute | 0:bb74812ac6bb | 104 | |
akashvibhute | 0:bb74812ac6bb | 105 | /****************************************************************************/ |
akashvibhute | 0:bb74812ac6bb | 106 | |
akashvibhute | 0:bb74812ac6bb | 107 | uint8_t RF24::write_register(uint8_t reg, uint8_t value) |
akashvibhute | 0:bb74812ac6bb | 108 | { |
akashvibhute | 6:5cc7136648d1 | 109 | uint8_t status; |
akashvibhute | 2:3bdf0d9bb71f | 110 | |
akashvibhute | 6:5cc7136648d1 | 111 | IF_SERIAL_DEBUG(printf_P(PSTR("write_register(%02x,%02x)\r\n"),reg,value)); |
akashvibhute | 2:3bdf0d9bb71f | 112 | |
akashvibhute | 6:5cc7136648d1 | 113 | |
akashvibhute | 6:5cc7136648d1 | 114 | |
akashvibhute | 6:5cc7136648d1 | 115 | beginTransaction(); |
akashvibhute | 6:5cc7136648d1 | 116 | status = spi.write( W_REGISTER | ( REGISTER_MASK & reg ) ); |
akashvibhute | 6:5cc7136648d1 | 117 | spi.write(value); |
akashvibhute | 6:5cc7136648d1 | 118 | endTransaction(); |
akashvibhute | 6:5cc7136648d1 | 119 | |
akashvibhute | 6:5cc7136648d1 | 120 | |
akashvibhute | 6:5cc7136648d1 | 121 | |
akashvibhute | 6:5cc7136648d1 | 122 | return status; |
akashvibhute | 2:3bdf0d9bb71f | 123 | } |
akashvibhute | 2:3bdf0d9bb71f | 124 | |
akashvibhute | 2:3bdf0d9bb71f | 125 | /****************************************************************************/ |
akashvibhute | 6:5cc7136648d1 | 126 | |
akashvibhute | 6:5cc7136648d1 | 127 | uint8_t RF24::write_payload(const void* buf, uint8_t data_len, const uint8_t writeType) |
akashvibhute | 2:3bdf0d9bb71f | 128 | { |
akashvibhute | 6:5cc7136648d1 | 129 | uint8_t status; |
akashvibhute | 6:5cc7136648d1 | 130 | const uint8_t* current = reinterpret_cast<const uint8_t*>(buf); |
akashvibhute | 2:3bdf0d9bb71f | 131 | |
akashvibhute | 6:5cc7136648d1 | 132 | data_len = rf24_min(data_len, payload_size); |
akashvibhute | 6:5cc7136648d1 | 133 | uint8_t blank_len = dynamic_payloads_enabled ? 0 : payload_size - data_len; |
akashvibhute | 6:5cc7136648d1 | 134 | |
akashvibhute | 6:5cc7136648d1 | 135 | //printf("[Writing %u bytes %u blanks]",data_len,blank_len); |
akashvibhute | 6:5cc7136648d1 | 136 | IF_SERIAL_DEBUG( printf("[Writing %u bytes %u blanks]\n",data_len,blank_len); ); |
akashvibhute | 6:5cc7136648d1 | 137 | |
akashvibhute | 6:5cc7136648d1 | 138 | |
akashvibhute | 6:5cc7136648d1 | 139 | beginTransaction(); |
akashvibhute | 6:5cc7136648d1 | 140 | status = spi.write( writeType ); |
akashvibhute | 6:5cc7136648d1 | 141 | while ( data_len-- ) { |
akashvibhute | 6:5cc7136648d1 | 142 | spi.write(*current++); |
akashvibhute | 6:5cc7136648d1 | 143 | } |
akashvibhute | 6:5cc7136648d1 | 144 | while ( blank_len-- ) { |
akashvibhute | 6:5cc7136648d1 | 145 | spi.write(0); |
akashvibhute | 6:5cc7136648d1 | 146 | } |
akashvibhute | 6:5cc7136648d1 | 147 | endTransaction(); |
akashvibhute | 3:e94be00fd19e | 148 | |
akashvibhute | 6:5cc7136648d1 | 149 | |
akashvibhute | 6:5cc7136648d1 | 150 | |
akashvibhute | 6:5cc7136648d1 | 151 | return status; |
akashvibhute | 0:bb74812ac6bb | 152 | } |
akashvibhute | 0:bb74812ac6bb | 153 | |
akashvibhute | 0:bb74812ac6bb | 154 | /****************************************************************************/ |
akashvibhute | 0:bb74812ac6bb | 155 | |
akashvibhute | 2:3bdf0d9bb71f | 156 | uint8_t RF24::read_payload(void* buf, uint8_t data_len) |
akashvibhute | 0:bb74812ac6bb | 157 | { |
akashvibhute | 6:5cc7136648d1 | 158 | uint8_t status; |
akashvibhute | 6:5cc7136648d1 | 159 | uint8_t* current = reinterpret_cast<uint8_t*>(buf); |
akashvibhute | 2:3bdf0d9bb71f | 160 | |
akashvibhute | 6:5cc7136648d1 | 161 | if(data_len > payload_size) data_len = payload_size; |
akashvibhute | 6:5cc7136648d1 | 162 | uint8_t blank_len = dynamic_payloads_enabled ? 0 : payload_size - data_len; |
akashvibhute | 6:5cc7136648d1 | 163 | |
akashvibhute | 6:5cc7136648d1 | 164 | //printf("[Reading %u bytes %u blanks]",data_len,blank_len); |
akashvibhute | 0:bb74812ac6bb | 165 | |
akashvibhute | 6:5cc7136648d1 | 166 | IF_SERIAL_DEBUG( printf("[Reading %u bytes %u blanks]\n",data_len,blank_len); ); |
akashvibhute | 6:5cc7136648d1 | 167 | |
akashvibhute | 6:5cc7136648d1 | 168 | beginTransaction(); |
akashvibhute | 6:5cc7136648d1 | 169 | status = spi.write( R_RX_PAYLOAD ); |
akashvibhute | 6:5cc7136648d1 | 170 | while ( data_len-- ) { |
akashvibhute | 6:5cc7136648d1 | 171 | *current++ = spi.write(0xFF); |
akashvibhute | 6:5cc7136648d1 | 172 | } |
akashvibhute | 6:5cc7136648d1 | 173 | while ( blank_len-- ) { |
akashvibhute | 6:5cc7136648d1 | 174 | spi.write(0xff); |
akashvibhute | 6:5cc7136648d1 | 175 | } |
akashvibhute | 6:5cc7136648d1 | 176 | endTransaction(); |
akashvibhute | 6:5cc7136648d1 | 177 | |
akashvibhute | 6:5cc7136648d1 | 178 | |
akashvibhute | 6:5cc7136648d1 | 179 | |
akashvibhute | 6:5cc7136648d1 | 180 | return status; |
akashvibhute | 0:bb74812ac6bb | 181 | } |
akashvibhute | 0:bb74812ac6bb | 182 | |
akashvibhute | 0:bb74812ac6bb | 183 | /****************************************************************************/ |
akashvibhute | 0:bb74812ac6bb | 184 | |
akashvibhute | 0:bb74812ac6bb | 185 | uint8_t RF24::flush_rx(void) |
akashvibhute | 0:bb74812ac6bb | 186 | { |
akashvibhute | 6:5cc7136648d1 | 187 | return spiTrans( FLUSH_RX ); |
akashvibhute | 0:bb74812ac6bb | 188 | } |
akashvibhute | 0:bb74812ac6bb | 189 | |
akashvibhute | 0:bb74812ac6bb | 190 | /****************************************************************************/ |
akashvibhute | 0:bb74812ac6bb | 191 | |
akashvibhute | 0:bb74812ac6bb | 192 | uint8_t RF24::flush_tx(void) |
akashvibhute | 0:bb74812ac6bb | 193 | { |
akashvibhute | 6:5cc7136648d1 | 194 | return spiTrans( FLUSH_TX ); |
akashvibhute | 2:3bdf0d9bb71f | 195 | } |
akashvibhute | 2:3bdf0d9bb71f | 196 | |
akashvibhute | 2:3bdf0d9bb71f | 197 | /****************************************************************************/ |
akashvibhute | 2:3bdf0d9bb71f | 198 | |
akashvibhute | 6:5cc7136648d1 | 199 | uint8_t RF24::spiTrans(uint8_t cmd){ |
akashvibhute | 0:bb74812ac6bb | 200 | |
akashvibhute | 6:5cc7136648d1 | 201 | uint8_t status; |
akashvibhute | 6:5cc7136648d1 | 202 | |
akashvibhute | 6:5cc7136648d1 | 203 | beginTransaction(); |
akashvibhute | 6:5cc7136648d1 | 204 | status = spi.write( cmd ); |
akashvibhute | 6:5cc7136648d1 | 205 | endTransaction(); |
akashvibhute | 6:5cc7136648d1 | 206 | |
akashvibhute | 6:5cc7136648d1 | 207 | return status; |
akashvibhute | 0:bb74812ac6bb | 208 | } |
akashvibhute | 0:bb74812ac6bb | 209 | |
akashvibhute | 0:bb74812ac6bb | 210 | /****************************************************************************/ |
akashvibhute | 0:bb74812ac6bb | 211 | |
akashvibhute | 0:bb74812ac6bb | 212 | uint8_t RF24::get_status(void) |
akashvibhute | 0:bb74812ac6bb | 213 | { |
akashvibhute | 6:5cc7136648d1 | 214 | return spiTrans(NOP); |
akashvibhute | 0:bb74812ac6bb | 215 | } |
akashvibhute | 0:bb74812ac6bb | 216 | |
akashvibhute | 0:bb74812ac6bb | 217 | /****************************************************************************/ |
akashvibhute | 2:3bdf0d9bb71f | 218 | #if !defined (MINIMAL) |
akashvibhute | 0:bb74812ac6bb | 219 | void RF24::print_status(uint8_t status) |
akashvibhute | 0:bb74812ac6bb | 220 | { |
akashvibhute | 6:5cc7136648d1 | 221 | printf_P(PSTR("STATUS\t\t = 0x%02x RX_DR=%x TX_DS=%x MAX_RT=%x RX_P_NO=%x TX_FULL=%x\r\n"), |
akashvibhute | 0:bb74812ac6bb | 222 | status, |
akashvibhute | 0:bb74812ac6bb | 223 | (status & _BV(RX_DR))?1:0, |
akashvibhute | 0:bb74812ac6bb | 224 | (status & _BV(TX_DS))?1:0, |
akashvibhute | 0:bb74812ac6bb | 225 | (status & _BV(MAX_RT))?1:0, |
akashvibhute | 6:5cc7136648d1 | 226 | ((status >> RX_P_NO) & 0b111), |
akashvibhute | 0:bb74812ac6bb | 227 | (status & _BV(TX_FULL))?1:0 |
akashvibhute | 0:bb74812ac6bb | 228 | ); |
akashvibhute | 0:bb74812ac6bb | 229 | } |
akashvibhute | 0:bb74812ac6bb | 230 | |
akashvibhute | 0:bb74812ac6bb | 231 | /****************************************************************************/ |
akashvibhute | 0:bb74812ac6bb | 232 | |
akashvibhute | 0:bb74812ac6bb | 233 | void RF24::print_observe_tx(uint8_t value) |
akashvibhute | 0:bb74812ac6bb | 234 | { |
akashvibhute | 6:5cc7136648d1 | 235 | printf_P(PSTR("OBSERVE_TX=%02x: POLS_CNT=%x ARC_CNT=%x\r\n"), |
akashvibhute | 0:bb74812ac6bb | 236 | value, |
akashvibhute | 6:5cc7136648d1 | 237 | (value >> PLOS_CNT) & 0b1111, |
akashvibhute | 6:5cc7136648d1 | 238 | (value >> ARC_CNT) & 0b1111 |
akashvibhute | 0:bb74812ac6bb | 239 | ); |
akashvibhute | 0:bb74812ac6bb | 240 | } |
akashvibhute | 0:bb74812ac6bb | 241 | |
akashvibhute | 0:bb74812ac6bb | 242 | /****************************************************************************/ |
akashvibhute | 0:bb74812ac6bb | 243 | |
akashvibhute | 0:bb74812ac6bb | 244 | void RF24::print_byte_register(const char* name, uint8_t reg, uint8_t qty) |
akashvibhute | 0:bb74812ac6bb | 245 | { |
akashvibhute | 6:5cc7136648d1 | 246 | //char extra_tab = strlen_P(name) < 8 ? '\t' : 0; |
akashvibhute | 6:5cc7136648d1 | 247 | //printf_P(PSTR(PRIPSTR"\t%c ="),name,extra_tab); |
akashvibhute | 6:5cc7136648d1 | 248 | |
akashvibhute | 6:5cc7136648d1 | 249 | |
akashvibhute | 6:5cc7136648d1 | 250 | |
akashvibhute | 6:5cc7136648d1 | 251 | printf_P(PSTR(PRIPSTR"\t ="),name); |
akashvibhute | 6:5cc7136648d1 | 252 | |
akashvibhute | 6:5cc7136648d1 | 253 | while (qty--) |
akashvibhute | 6:5cc7136648d1 | 254 | printf_P(PSTR(" 0x%02x"),read_register(reg++)); |
akashvibhute | 6:5cc7136648d1 | 255 | printf_P(PSTR("\r\n")); |
akashvibhute | 0:bb74812ac6bb | 256 | } |
akashvibhute | 0:bb74812ac6bb | 257 | |
akashvibhute | 0:bb74812ac6bb | 258 | /****************************************************************************/ |
akashvibhute | 0:bb74812ac6bb | 259 | |
akashvibhute | 0:bb74812ac6bb | 260 | void RF24::print_address_register(const char* name, uint8_t reg, uint8_t qty) |
akashvibhute | 0:bb74812ac6bb | 261 | { |
akashvibhute | 0:bb74812ac6bb | 262 | |
akashvibhute | 6:5cc7136648d1 | 263 | |
akashvibhute | 6:5cc7136648d1 | 264 | |
akashvibhute | 6:5cc7136648d1 | 265 | |
akashvibhute | 6:5cc7136648d1 | 266 | printf_P(PSTR(PRIPSTR"\t ="),name); |
akashvibhute | 6:5cc7136648d1 | 267 | |
akashvibhute | 6:5cc7136648d1 | 268 | while (qty--) |
akashvibhute | 6:5cc7136648d1 | 269 | { |
akashvibhute | 6:5cc7136648d1 | 270 | uint8_t buffer[addr_width]; |
akashvibhute | 6:5cc7136648d1 | 271 | read_register(reg++,buffer,sizeof buffer); |
akashvibhute | 0:bb74812ac6bb | 272 | |
akashvibhute | 6:5cc7136648d1 | 273 | printf_P(PSTR(" 0x")); |
akashvibhute | 6:5cc7136648d1 | 274 | uint8_t* bufptr = buffer + sizeof buffer; |
akashvibhute | 6:5cc7136648d1 | 275 | while( --bufptr >= buffer ) |
akashvibhute | 6:5cc7136648d1 | 276 | printf_P(PSTR("%02x"),*bufptr); |
akashvibhute | 6:5cc7136648d1 | 277 | } |
akashvibhute | 3:e94be00fd19e | 278 | |
akashvibhute | 6:5cc7136648d1 | 279 | printf_P(PSTR("\r\n")); |
akashvibhute | 2:3bdf0d9bb71f | 280 | } |
akashvibhute | 2:3bdf0d9bb71f | 281 | #endif |
akashvibhute | 2:3bdf0d9bb71f | 282 | /****************************************************************************/ |
akashvibhute | 2:3bdf0d9bb71f | 283 | RF24::RF24(PinName mosi, PinName miso, PinName sck, PinName _cepin, PinName _csnpin): |
akashvibhute | 6:5cc7136648d1 | 284 | spi(mosi, miso, sck), ce_pin(_cepin), csn_pin(_csnpin), p_variant(true), |
akashvibhute | 6:5cc7136648d1 | 285 | payload_size(32), dynamic_payloads_enabled(false), addr_width(5) |
akashvibhute | 2:3bdf0d9bb71f | 286 | { |
akashvibhute | 6:5cc7136648d1 | 287 | pipe0_reading_address[0]=0; |
akashvibhute | 6:5cc7136648d1 | 288 | |
akashvibhute | 6:5cc7136648d1 | 289 | //spi.frequency(10000000/5); // 2Mbit, 1/5th the maximum transfer rate for the spi bus |
akashvibhute | 6:5cc7136648d1 | 290 | spi.frequency(10000000); |
akashvibhute | 6:5cc7136648d1 | 291 | //spi.format(8,0); // 8-bit, ClockPhase = 0, ClockPolarity = 0 |
akashvibhute | 6:5cc7136648d1 | 292 | spi.format(8,0); |
akashvibhute | 6:5cc7136648d1 | 293 | wait_ms(10); |
akashvibhute | 0:bb74812ac6bb | 294 | } |
akashvibhute | 0:bb74812ac6bb | 295 | |
akashvibhute | 2:3bdf0d9bb71f | 296 | |
akashvibhute | 2:3bdf0d9bb71f | 297 | |
akashvibhute | 0:bb74812ac6bb | 298 | |
akashvibhute | 2:3bdf0d9bb71f | 299 | |
akashvibhute | 2:3bdf0d9bb71f | 300 | |
akashvibhute | 2:3bdf0d9bb71f | 301 | |
akashvibhute | 0:bb74812ac6bb | 302 | |
akashvibhute | 0:bb74812ac6bb | 303 | /****************************************************************************/ |
akashvibhute | 0:bb74812ac6bb | 304 | |
akashvibhute | 0:bb74812ac6bb | 305 | void RF24::setChannel(uint8_t channel) |
akashvibhute | 0:bb74812ac6bb | 306 | { |
akashvibhute | 6:5cc7136648d1 | 307 | const uint8_t max_channel = 125; |
akashvibhute | 6:5cc7136648d1 | 308 | write_register(RF_CH,rf24_min(channel,max_channel)); |
akashvibhute | 0:bb74812ac6bb | 309 | } |
akashvibhute | 0:bb74812ac6bb | 310 | |
akashvibhute | 2:3bdf0d9bb71f | 311 | uint8_t RF24::getChannel() |
akashvibhute | 2:3bdf0d9bb71f | 312 | { |
akashvibhute | 6:5cc7136648d1 | 313 | |
akashvibhute | 6:5cc7136648d1 | 314 | return read_register(RF_CH); |
akashvibhute | 2:3bdf0d9bb71f | 315 | } |
akashvibhute | 0:bb74812ac6bb | 316 | /****************************************************************************/ |
akashvibhute | 0:bb74812ac6bb | 317 | |
akashvibhute | 0:bb74812ac6bb | 318 | void RF24::setPayloadSize(uint8_t size) |
akashvibhute | 0:bb74812ac6bb | 319 | { |
akashvibhute | 6:5cc7136648d1 | 320 | payload_size = rf24_min(size,32); |
akashvibhute | 0:bb74812ac6bb | 321 | } |
akashvibhute | 0:bb74812ac6bb | 322 | |
akashvibhute | 0:bb74812ac6bb | 323 | /****************************************************************************/ |
akashvibhute | 0:bb74812ac6bb | 324 | |
akashvibhute | 0:bb74812ac6bb | 325 | uint8_t RF24::getPayloadSize(void) |
akashvibhute | 0:bb74812ac6bb | 326 | { |
akashvibhute | 6:5cc7136648d1 | 327 | return payload_size; |
akashvibhute | 0:bb74812ac6bb | 328 | } |
akashvibhute | 0:bb74812ac6bb | 329 | |
akashvibhute | 0:bb74812ac6bb | 330 | /****************************************************************************/ |
akashvibhute | 0:bb74812ac6bb | 331 | |
akashvibhute | 2:3bdf0d9bb71f | 332 | #if !defined (MINIMAL) |
akashvibhute | 2:3bdf0d9bb71f | 333 | |
akashvibhute | 2:3bdf0d9bb71f | 334 | static const char rf24_datarate_e_str_0[] PROGMEM = "1MBPS"; |
akashvibhute | 2:3bdf0d9bb71f | 335 | static const char rf24_datarate_e_str_1[] PROGMEM = "2MBPS"; |
akashvibhute | 2:3bdf0d9bb71f | 336 | static const char rf24_datarate_e_str_2[] PROGMEM = "250KBPS"; |
akashvibhute | 2:3bdf0d9bb71f | 337 | static const char * const rf24_datarate_e_str_P[] PROGMEM = { |
akashvibhute | 6:5cc7136648d1 | 338 | rf24_datarate_e_str_0, |
akashvibhute | 6:5cc7136648d1 | 339 | rf24_datarate_e_str_1, |
akashvibhute | 6:5cc7136648d1 | 340 | rf24_datarate_e_str_2, |
akashvibhute | 0:bb74812ac6bb | 341 | }; |
akashvibhute | 2:3bdf0d9bb71f | 342 | static const char rf24_model_e_str_0[] PROGMEM = "nRF24L01"; |
akashvibhute | 2:3bdf0d9bb71f | 343 | static const char rf24_model_e_str_1[] PROGMEM = "nRF24L01+"; |
akashvibhute | 2:3bdf0d9bb71f | 344 | static const char * const rf24_model_e_str_P[] PROGMEM = { |
akashvibhute | 6:5cc7136648d1 | 345 | rf24_model_e_str_0, |
akashvibhute | 6:5cc7136648d1 | 346 | rf24_model_e_str_1, |
akashvibhute | 0:bb74812ac6bb | 347 | }; |
akashvibhute | 2:3bdf0d9bb71f | 348 | static const char rf24_crclength_e_str_0[] PROGMEM = "Disabled"; |
akashvibhute | 2:3bdf0d9bb71f | 349 | static const char rf24_crclength_e_str_1[] PROGMEM = "8 bits"; |
akashvibhute | 2:3bdf0d9bb71f | 350 | static const char rf24_crclength_e_str_2[] PROGMEM = "16 bits" ; |
akashvibhute | 2:3bdf0d9bb71f | 351 | static const char * const rf24_crclength_e_str_P[] PROGMEM = { |
akashvibhute | 6:5cc7136648d1 | 352 | rf24_crclength_e_str_0, |
akashvibhute | 6:5cc7136648d1 | 353 | rf24_crclength_e_str_1, |
akashvibhute | 6:5cc7136648d1 | 354 | rf24_crclength_e_str_2, |
akashvibhute | 0:bb74812ac6bb | 355 | }; |
akashvibhute | 2:3bdf0d9bb71f | 356 | static const char rf24_pa_dbm_e_str_0[] PROGMEM = "PA_MIN"; |
akashvibhute | 2:3bdf0d9bb71f | 357 | static const char rf24_pa_dbm_e_str_1[] PROGMEM = "PA_LOW"; |
akashvibhute | 2:3bdf0d9bb71f | 358 | static const char rf24_pa_dbm_e_str_2[] PROGMEM = "PA_HIGH"; |
akashvibhute | 2:3bdf0d9bb71f | 359 | static const char rf24_pa_dbm_e_str_3[] PROGMEM = "PA_MAX"; |
akashvibhute | 2:3bdf0d9bb71f | 360 | static const char * const rf24_pa_dbm_e_str_P[] PROGMEM = { |
akashvibhute | 6:5cc7136648d1 | 361 | rf24_pa_dbm_e_str_0, |
akashvibhute | 6:5cc7136648d1 | 362 | rf24_pa_dbm_e_str_1, |
akashvibhute | 6:5cc7136648d1 | 363 | rf24_pa_dbm_e_str_2, |
akashvibhute | 6:5cc7136648d1 | 364 | rf24_pa_dbm_e_str_3, |
akashvibhute | 0:bb74812ac6bb | 365 | }; |
akashvibhute | 0:bb74812ac6bb | 366 | |
akashvibhute | 6:5cc7136648d1 | 367 | |
akashvibhute | 6:5cc7136648d1 | 368 | |
akashvibhute | 6:5cc7136648d1 | 369 | |
akashvibhute | 0:bb74812ac6bb | 370 | void RF24::printDetails(void) |
akashvibhute | 0:bb74812ac6bb | 371 | { |
akashvibhute | 6:5cc7136648d1 | 372 | print_status(get_status()); |
akashvibhute | 6:5cc7136648d1 | 373 | |
akashvibhute | 6:5cc7136648d1 | 374 | print_address_register(PSTR("RX_ADDR_P0-1"),RX_ADDR_P0,2); |
akashvibhute | 6:5cc7136648d1 | 375 | print_byte_register(PSTR("RX_ADDR_P2-5"),RX_ADDR_P2,4); |
akashvibhute | 6:5cc7136648d1 | 376 | print_address_register(PSTR("TX_ADDR\t"),TX_ADDR); |
akashvibhute | 0:bb74812ac6bb | 377 | |
akashvibhute | 6:5cc7136648d1 | 378 | print_byte_register(PSTR("RX_PW_P0-6"),RX_PW_P0,6); |
akashvibhute | 6:5cc7136648d1 | 379 | print_byte_register(PSTR("EN_AA\t"),EN_AA); |
akashvibhute | 6:5cc7136648d1 | 380 | print_byte_register(PSTR("EN_RXADDR"),EN_RXADDR); |
akashvibhute | 6:5cc7136648d1 | 381 | print_byte_register(PSTR("RF_CH\t"),RF_CH); |
akashvibhute | 6:5cc7136648d1 | 382 | print_byte_register(PSTR("RF_SETUP"),RF_SETUP); |
akashvibhute | 6:5cc7136648d1 | 383 | print_byte_register(PSTR("CONFIG\t"),NRF_CONFIG); |
akashvibhute | 6:5cc7136648d1 | 384 | print_byte_register(PSTR("DYNPD/FEATURE"),DYNPD,2); |
akashvibhute | 6:5cc7136648d1 | 385 | |
akashvibhute | 6:5cc7136648d1 | 386 | printf_P(PSTR("Data Rate\t = " PRIPSTR "\r\n"),pgm_read_word(&rf24_datarate_e_str_P[getDataRate()])); |
akashvibhute | 6:5cc7136648d1 | 387 | printf_P(PSTR("Model\t\t = " PRIPSTR "\r\n"),pgm_read_word(&rf24_model_e_str_P[isPVariant()])); |
akashvibhute | 6:5cc7136648d1 | 388 | printf_P(PSTR("CRC Length\t = " PRIPSTR "\r\n"),pgm_read_word(&rf24_crclength_e_str_P[getCRCLength()])); |
akashvibhute | 6:5cc7136648d1 | 389 | printf_P(PSTR("PA Power\t = " PRIPSTR "\r\n"), pgm_read_word(&rf24_pa_dbm_e_str_P[getPALevel()])); |
akashvibhute | 2:3bdf0d9bb71f | 390 | |
akashvibhute | 0:bb74812ac6bb | 391 | } |
akashvibhute | 0:bb74812ac6bb | 392 | |
akashvibhute | 2:3bdf0d9bb71f | 393 | #endif |
akashvibhute | 0:bb74812ac6bb | 394 | /****************************************************************************/ |
akashvibhute | 0:bb74812ac6bb | 395 | |
akashvibhute | 2:3bdf0d9bb71f | 396 | bool RF24::begin(void) |
akashvibhute | 0:bb74812ac6bb | 397 | { |
akashvibhute | 6:5cc7136648d1 | 398 | |
akashvibhute | 6:5cc7136648d1 | 399 | uint8_t setup=0; |
akashvibhute | 6:5cc7136648d1 | 400 | |
akashvibhute | 6:5cc7136648d1 | 401 | mainTimer.start(); |
akashvibhute | 6:5cc7136648d1 | 402 | |
akashvibhute | 6:5cc7136648d1 | 403 | ce(LOW); |
akashvibhute | 6:5cc7136648d1 | 404 | csn(HIGH); |
akashvibhute | 6:5cc7136648d1 | 405 | |
akashvibhute | 6:5cc7136648d1 | 406 | wait_ms(100); |
akashvibhute | 6:5cc7136648d1 | 407 | |
akashvibhute | 6:5cc7136648d1 | 408 | |
akashvibhute | 6:5cc7136648d1 | 409 | // Must allow the radio time to settle else configuration bits will not necessarily stick. |
akashvibhute | 6:5cc7136648d1 | 410 | // This is actually only required following power up but some settling time also appears to |
akashvibhute | 6:5cc7136648d1 | 411 | // be required after resets too. For full coverage, we'll always assume the worst. |
akashvibhute | 6:5cc7136648d1 | 412 | // Enabling 16b CRC is by far the most obvious case if the wrong timing is used - or skipped. |
akashvibhute | 6:5cc7136648d1 | 413 | // Technically we require 4.5ms + 14us as a worst case. We'll just call it 5ms for good measure. |
akashvibhute | 6:5cc7136648d1 | 414 | // WARNING: Delay is based on P-variant whereby non-P *may* require different timing. |
akashvibhute | 6:5cc7136648d1 | 415 | wait_ms( 5 ) ; |
akashvibhute | 0:bb74812ac6bb | 416 | |
akashvibhute | 6:5cc7136648d1 | 417 | // Reset NRF_CONFIG and enable 16-bit CRC. |
akashvibhute | 6:5cc7136648d1 | 418 | write_register( NRF_CONFIG, 0b00001100 ) ; |
akashvibhute | 6:5cc7136648d1 | 419 | |
akashvibhute | 6:5cc7136648d1 | 420 | // Set 1500uS (minimum for 32B payload in ESB@250KBPS) timeouts, to make testing a little easier |
akashvibhute | 6:5cc7136648d1 | 421 | // WARNING: If this is ever lowered, either 250KBS mode with AA is broken or maximum packet |
akashvibhute | 6:5cc7136648d1 | 422 | // sizes must never be used. See documentation for a more complete explanation. |
akashvibhute | 6:5cc7136648d1 | 423 | setRetries(5,15); |
akashvibhute | 6:5cc7136648d1 | 424 | |
akashvibhute | 6:5cc7136648d1 | 425 | // Reset value is MAX |
akashvibhute | 6:5cc7136648d1 | 426 | //setPALevel( RF24_PA_MAX ) ; |
akashvibhute | 0:bb74812ac6bb | 427 | |
akashvibhute | 6:5cc7136648d1 | 428 | // check for connected module and if this is a p nRF24l01 variant |
akashvibhute | 6:5cc7136648d1 | 429 | // |
akashvibhute | 6:5cc7136648d1 | 430 | if( setDataRate( RF24_250KBPS ) ) |
akashvibhute | 6:5cc7136648d1 | 431 | { |
akashvibhute | 6:5cc7136648d1 | 432 | p_variant = true ; |
akashvibhute | 6:5cc7136648d1 | 433 | } |
akashvibhute | 6:5cc7136648d1 | 434 | setup = read_register(RF_SETUP); |
akashvibhute | 6:5cc7136648d1 | 435 | /*if( setup == 0b00001110 ) // register default for nRF24L01P |
akashvibhute | 6:5cc7136648d1 | 436 | { |
akashvibhute | 6:5cc7136648d1 | 437 | p_variant = true ; |
akashvibhute | 6:5cc7136648d1 | 438 | }*/ |
akashvibhute | 6:5cc7136648d1 | 439 | |
akashvibhute | 6:5cc7136648d1 | 440 | // Then set the data rate to the slowest (and most reliable) speed supported by all |
akashvibhute | 6:5cc7136648d1 | 441 | // hardware. |
akashvibhute | 6:5cc7136648d1 | 442 | //setDataRate( RF24_1MBPS ) ; |
akashvibhute | 6:5cc7136648d1 | 443 | setDataRate( RF24_2MBPS ) ; |
akashvibhute | 0:bb74812ac6bb | 444 | |
akashvibhute | 6:5cc7136648d1 | 445 | // Initialize CRC and request 2-byte (16bit) CRC |
akashvibhute | 6:5cc7136648d1 | 446 | //setCRCLength( RF24_CRC_16 ) ; |
akashvibhute | 2:3bdf0d9bb71f | 447 | |
akashvibhute | 6:5cc7136648d1 | 448 | // Disable dynamic payloads, to match dynamic_payloads_enabled setting - Reset value is 0 |
akashvibhute | 6:5cc7136648d1 | 449 | toggle_features(); |
akashvibhute | 6:5cc7136648d1 | 450 | write_register(FEATURE,0 ); |
akashvibhute | 6:5cc7136648d1 | 451 | write_register(DYNPD,0); |
akashvibhute | 6:5cc7136648d1 | 452 | |
akashvibhute | 6:5cc7136648d1 | 453 | // Reset current status |
akashvibhute | 6:5cc7136648d1 | 454 | // Notice reset and flush is the last thing we do |
akashvibhute | 6:5cc7136648d1 | 455 | write_register(NRF_STATUS,_BV(RX_DR) | _BV(TX_DS) | _BV(MAX_RT) ); |
akashvibhute | 0:bb74812ac6bb | 456 | |
akashvibhute | 6:5cc7136648d1 | 457 | // Set up default configuration. Callers can always change it later. |
akashvibhute | 6:5cc7136648d1 | 458 | // This channel should be universally safe and not bleed over into adjacent |
akashvibhute | 6:5cc7136648d1 | 459 | // spectrum. |
akashvibhute | 6:5cc7136648d1 | 460 | setChannel(76); |
akashvibhute | 0:bb74812ac6bb | 461 | |
akashvibhute | 6:5cc7136648d1 | 462 | // Flush buffers |
akashvibhute | 6:5cc7136648d1 | 463 | flush_rx(); |
akashvibhute | 6:5cc7136648d1 | 464 | flush_tx(); |
akashvibhute | 2:3bdf0d9bb71f | 465 | |
akashvibhute | 6:5cc7136648d1 | 466 | powerUp(); //Power up by default when begin() is called |
akashvibhute | 2:3bdf0d9bb71f | 467 | |
akashvibhute | 6:5cc7136648d1 | 468 | // Enable PTX, do not write CE high so radio will remain in standby I mode ( 130us max to transition to RX or TX instead of 1500us from powerUp ) |
akashvibhute | 6:5cc7136648d1 | 469 | // PTX should use only 22uA of power |
akashvibhute | 6:5cc7136648d1 | 470 | write_register(NRF_CONFIG, ( read_register(NRF_CONFIG) ) & ~_BV(PRIM_RX) ); |
akashvibhute | 8:b70b1d82f1d7 | 471 | //printDetails(); |
akashvibhute | 6:5cc7136648d1 | 472 | // if setup is 0 or ff then there was no response from module |
akashvibhute | 6:5cc7136648d1 | 473 | return ( setup != 0 && setup != 0xff ); |
akashvibhute | 0:bb74812ac6bb | 474 | } |
akashvibhute | 0:bb74812ac6bb | 475 | |
akashvibhute | 0:bb74812ac6bb | 476 | /****************************************************************************/ |
akashvibhute | 0:bb74812ac6bb | 477 | |
akashvibhute | 0:bb74812ac6bb | 478 | void RF24::startListening(void) |
akashvibhute | 0:bb74812ac6bb | 479 | { |
akashvibhute | 6:5cc7136648d1 | 480 | |
akashvibhute | 6:5cc7136648d1 | 481 | |
akashvibhute | 6:5cc7136648d1 | 482 | |
akashvibhute | 6:5cc7136648d1 | 483 | write_register(NRF_CONFIG, read_register(NRF_CONFIG) | _BV(PRIM_RX)); |
akashvibhute | 6:5cc7136648d1 | 484 | write_register(NRF_STATUS, _BV(RX_DR) | _BV(TX_DS) | _BV(MAX_RT) ); |
akashvibhute | 6:5cc7136648d1 | 485 | ce(HIGH); |
akashvibhute | 6:5cc7136648d1 | 486 | // Restore the pipe0 adddress, if exists |
akashvibhute | 6:5cc7136648d1 | 487 | if (pipe0_reading_address[0] > 0){ |
akashvibhute | 6:5cc7136648d1 | 488 | write_register(RX_ADDR_P0, pipe0_reading_address, addr_width); |
akashvibhute | 6:5cc7136648d1 | 489 | }else{ |
akashvibhute | 6:5cc7136648d1 | 490 | closeReadingPipe(0); |
akashvibhute | 6:5cc7136648d1 | 491 | } |
akashvibhute | 0:bb74812ac6bb | 492 | |
akashvibhute | 6:5cc7136648d1 | 493 | // Flush buffers |
akashvibhute | 6:5cc7136648d1 | 494 | //flush_rx(); |
akashvibhute | 6:5cc7136648d1 | 495 | if(read_register(FEATURE) & _BV(EN_ACK_PAY)){ |
akashvibhute | 6:5cc7136648d1 | 496 | flush_tx(); |
akashvibhute | 6:5cc7136648d1 | 497 | } |
akashvibhute | 0:bb74812ac6bb | 498 | |
akashvibhute | 6:5cc7136648d1 | 499 | // Go! |
akashvibhute | 6:5cc7136648d1 | 500 | //delayMicroseconds(100); |
akashvibhute | 0:bb74812ac6bb | 501 | } |
akashvibhute | 0:bb74812ac6bb | 502 | |
akashvibhute | 0:bb74812ac6bb | 503 | /****************************************************************************/ |
akashvibhute | 6:5cc7136648d1 | 504 | static const uint8_t child_pipe_enable[] PROGMEM = |
akashvibhute | 6:5cc7136648d1 | 505 | { |
akashvibhute | 6:5cc7136648d1 | 506 | ERX_P0, ERX_P1, ERX_P2, ERX_P3, ERX_P4, ERX_P5 |
akashvibhute | 2:3bdf0d9bb71f | 507 | }; |
akashvibhute | 0:bb74812ac6bb | 508 | |
akashvibhute | 0:bb74812ac6bb | 509 | void RF24::stopListening(void) |
akashvibhute | 6:5cc7136648d1 | 510 | { |
akashvibhute | 6:5cc7136648d1 | 511 | ce(LOW); |
akashvibhute | 2:3bdf0d9bb71f | 512 | |
akashvibhute | 6:5cc7136648d1 | 513 | wait_us(txRxDelay); |
akashvibhute | 6:5cc7136648d1 | 514 | |
akashvibhute | 6:5cc7136648d1 | 515 | if(read_register(FEATURE) & _BV(EN_ACK_PAY)){ |
akashvibhute | 6:5cc7136648d1 | 516 | wait_us(txRxDelay); //200 |
akashvibhute | 6:5cc7136648d1 | 517 | flush_tx(); |
akashvibhute | 6:5cc7136648d1 | 518 | } |
akashvibhute | 6:5cc7136648d1 | 519 | //flush_rx(); |
akashvibhute | 6:5cc7136648d1 | 520 | write_register(NRF_CONFIG, ( read_register(NRF_CONFIG) ) & ~_BV(PRIM_RX) ); |
akashvibhute | 6:5cc7136648d1 | 521 | |
akashvibhute | 6:5cc7136648d1 | 522 | |
akashvibhute | 6:5cc7136648d1 | 523 | |
akashvibhute | 6:5cc7136648d1 | 524 | |
akashvibhute | 6:5cc7136648d1 | 525 | |
akashvibhute | 6:5cc7136648d1 | 526 | |
akashvibhute | 6:5cc7136648d1 | 527 | |
akashvibhute | 6:5cc7136648d1 | 528 | |
akashvibhute | 6:5cc7136648d1 | 529 | write_register(EN_RXADDR,read_register(EN_RXADDR) | _BV(pgm_read_byte(&child_pipe_enable[0]))); // Enable RX on pipe0 |
akashvibhute | 6:5cc7136648d1 | 530 | |
akashvibhute | 6:5cc7136648d1 | 531 | //delayMicroseconds(100); |
akashvibhute | 2:3bdf0d9bb71f | 532 | |
akashvibhute | 0:bb74812ac6bb | 533 | } |
akashvibhute | 0:bb74812ac6bb | 534 | |
akashvibhute | 0:bb74812ac6bb | 535 | /****************************************************************************/ |
akashvibhute | 0:bb74812ac6bb | 536 | |
akashvibhute | 0:bb74812ac6bb | 537 | void RF24::powerDown(void) |
akashvibhute | 0:bb74812ac6bb | 538 | { |
akashvibhute | 6:5cc7136648d1 | 539 | ce(LOW); // Guarantee CE is low on powerDown |
akashvibhute | 6:5cc7136648d1 | 540 | write_register(NRF_CONFIG,read_register(NRF_CONFIG) & ~_BV(PWR_UP)); |
akashvibhute | 0:bb74812ac6bb | 541 | } |
akashvibhute | 0:bb74812ac6bb | 542 | |
akashvibhute | 0:bb74812ac6bb | 543 | /****************************************************************************/ |
akashvibhute | 0:bb74812ac6bb | 544 | |
akashvibhute | 2:3bdf0d9bb71f | 545 | //Power up now. Radio will not power down unless instructed by MCU for config changes etc. |
akashvibhute | 0:bb74812ac6bb | 546 | void RF24::powerUp(void) |
akashvibhute | 0:bb74812ac6bb | 547 | { |
akashvibhute | 6:5cc7136648d1 | 548 | uint8_t cfg = read_register(NRF_CONFIG); |
akashvibhute | 2:3bdf0d9bb71f | 549 | |
akashvibhute | 6:5cc7136648d1 | 550 | // if not powered up then power up and wait for the radio to initialize |
akashvibhute | 6:5cc7136648d1 | 551 | if (!(cfg & _BV(PWR_UP))){ |
akashvibhute | 6:5cc7136648d1 | 552 | write_register(NRF_CONFIG, cfg | _BV(PWR_UP)); |
akashvibhute | 2:3bdf0d9bb71f | 553 | |
akashvibhute | 6:5cc7136648d1 | 554 | // For nRF24L01+ to go from power down mode to TX or RX mode it must first pass through stand-by mode. |
akashvibhute | 6:5cc7136648d1 | 555 | // There must be a delay of Tpd2stby (see Table 16.) after the nRF24L01+ leaves power down mode before |
akashvibhute | 6:5cc7136648d1 | 556 | // the CEis set high. - Tpd2stby can be up to 5ms per the 1.0 datasheet |
akashvibhute | 6:5cc7136648d1 | 557 | wait_ms(5); |
akashvibhute | 6:5cc7136648d1 | 558 | } |
akashvibhute | 0:bb74812ac6bb | 559 | } |
akashvibhute | 0:bb74812ac6bb | 560 | |
akashvibhute | 0:bb74812ac6bb | 561 | /******************************************************************/ |
akashvibhute | 6:5cc7136648d1 | 562 | #if defined (FAILURE_HANDLING) || defined (RF24_LINUX) |
akashvibhute | 6:5cc7136648d1 | 563 | void RF24::errNotify(){ |
akashvibhute | 6:5cc7136648d1 | 564 | #if defined (SERIAL_DEBUG) || defined (RF24_LINUX) |
akashvibhute | 6:5cc7136648d1 | 565 | printf_P(PSTR("RF24 HARDWARE FAIL: Radio not responding, verify pin connections, wiring, etc.\r\n")); |
akashvibhute | 6:5cc7136648d1 | 566 | #endif |
akashvibhute | 6:5cc7136648d1 | 567 | #if defined (FAILURE_HANDLING) |
akashvibhute | 6:5cc7136648d1 | 568 | failureDetected = 1; |
akashvibhute | 6:5cc7136648d1 | 569 | #else |
akashvibhute | 6:5cc7136648d1 | 570 | wait_ms(5000); |
akashvibhute | 6:5cc7136648d1 | 571 | #endif |
akashvibhute | 2:3bdf0d9bb71f | 572 | } |
akashvibhute | 2:3bdf0d9bb71f | 573 | #endif |
akashvibhute | 2:3bdf0d9bb71f | 574 | /******************************************************************/ |
akashvibhute | 0:bb74812ac6bb | 575 | |
akashvibhute | 2:3bdf0d9bb71f | 576 | //Similar to the previous write, clears the interrupt flags |
akashvibhute | 2:3bdf0d9bb71f | 577 | bool RF24::write( const void* buf, uint8_t len, const bool multicast ) |
akashvibhute | 2:3bdf0d9bb71f | 578 | { |
akashvibhute | 6:5cc7136648d1 | 579 | //Start Writing |
akashvibhute | 6:5cc7136648d1 | 580 | startFastWrite(buf,len,multicast); |
akashvibhute | 3:e94be00fd19e | 581 | |
akashvibhute | 6:5cc7136648d1 | 582 | //Wait until complete or failed |
akashvibhute | 6:5cc7136648d1 | 583 | #if defined (FAILURE_HANDLING) || defined (RF24_LINUX) |
akashvibhute | 6:5cc7136648d1 | 584 | uint32_t timer = mainTimer.read_ms(); |
akashvibhute | 6:5cc7136648d1 | 585 | #endif |
akashvibhute | 6:5cc7136648d1 | 586 | |
akashvibhute | 6:5cc7136648d1 | 587 | while( ! ( get_status() & ( _BV(TX_DS) | _BV(MAX_RT) ))) { |
akashvibhute | 6:5cc7136648d1 | 588 | #if defined (FAILURE_HANDLING) || defined (RF24_LINUX) |
akashvibhute | 6:5cc7136648d1 | 589 | if(mainTimer.read_ms() - timer > 95){ |
akashvibhute | 6:5cc7136648d1 | 590 | errNotify(); |
akashvibhute | 6:5cc7136648d1 | 591 | #if defined (FAILURE_HANDLING) |
akashvibhute | 6:5cc7136648d1 | 592 | return 0; |
akashvibhute | 6:5cc7136648d1 | 593 | #else |
akashvibhute | 6:5cc7136648d1 | 594 | wait_ms(100); |
akashvibhute | 6:5cc7136648d1 | 595 | #endif |
akashvibhute | 6:5cc7136648d1 | 596 | } |
akashvibhute | 6:5cc7136648d1 | 597 | #endif |
akashvibhute | 6:5cc7136648d1 | 598 | } |
akashvibhute | 6:5cc7136648d1 | 599 | |
akashvibhute | 6:5cc7136648d1 | 600 | ce(LOW); |
akashvibhute | 3:e94be00fd19e | 601 | |
akashvibhute | 6:5cc7136648d1 | 602 | uint8_t status = write_register(NRF_STATUS,_BV(RX_DR) | _BV(TX_DS) | _BV(MAX_RT) ); |
akashvibhute | 0:bb74812ac6bb | 603 | |
akashvibhute | 6:5cc7136648d1 | 604 | //Max retries exceeded |
akashvibhute | 6:5cc7136648d1 | 605 | if( status & _BV(MAX_RT)){ |
akashvibhute | 6:5cc7136648d1 | 606 | flush_tx(); //Only going to be 1 packet int the FIFO at a time using this method, so just flush |
akashvibhute | 6:5cc7136648d1 | 607 | return 0; |
akashvibhute | 6:5cc7136648d1 | 608 | } |
akashvibhute | 6:5cc7136648d1 | 609 | //TX OK 1 or 0 |
akashvibhute | 6:5cc7136648d1 | 610 | return 1; |
akashvibhute | 2:3bdf0d9bb71f | 611 | } |
akashvibhute | 0:bb74812ac6bb | 612 | |
akashvibhute | 6:5cc7136648d1 | 613 | bool RF24::write( const void* buf, uint8_t len ){ |
akashvibhute | 6:5cc7136648d1 | 614 | return write(buf,len,0); |
akashvibhute | 0:bb74812ac6bb | 615 | } |
akashvibhute | 0:bb74812ac6bb | 616 | /****************************************************************************/ |
akashvibhute | 0:bb74812ac6bb | 617 | |
akashvibhute | 2:3bdf0d9bb71f | 618 | //For general use, the interrupt flags are not important to clear |
akashvibhute | 2:3bdf0d9bb71f | 619 | bool RF24::writeBlocking( const void* buf, uint8_t len, uint32_t timeout ) |
akashvibhute | 2:3bdf0d9bb71f | 620 | { |
akashvibhute | 6:5cc7136648d1 | 621 | //Block until the FIFO is NOT full. |
akashvibhute | 6:5cc7136648d1 | 622 | //Keep track of the MAX retries and set auto-retry if seeing failures |
akashvibhute | 6:5cc7136648d1 | 623 | //This way the FIFO will fill up and allow blocking until packets go through |
akashvibhute | 6:5cc7136648d1 | 624 | //The radio will auto-clear everything in the FIFO as long as CE remains high |
akashvibhute | 2:3bdf0d9bb71f | 625 | |
akashvibhute | 6:5cc7136648d1 | 626 | uint32_t timer = mainTimer.read_ms(); //Get the time that the payload transmission started |
akashvibhute | 2:3bdf0d9bb71f | 627 | |
akashvibhute | 6:5cc7136648d1 | 628 | while( ( get_status() & ( _BV(TX_FULL) ))) { //Blocking only if FIFO is full. This will loop and block until TX is successful or timeout |
akashvibhute | 2:3bdf0d9bb71f | 629 | |
akashvibhute | 6:5cc7136648d1 | 630 | if( get_status() & _BV(MAX_RT)){ //If MAX Retries have been reached |
akashvibhute | 6:5cc7136648d1 | 631 | reUseTX(); //Set re-transmit and clear the MAX_RT interrupt flag |
akashvibhute | 6:5cc7136648d1 | 632 | if(mainTimer.read_ms() - timer > timeout){ return 0; } //If this payload has exceeded the user-defined timeout, exit and return 0 |
akashvibhute | 6:5cc7136648d1 | 633 | } |
akashvibhute | 6:5cc7136648d1 | 634 | #if defined (FAILURE_HANDLING) || defined (RF24_LINUX) |
akashvibhute | 6:5cc7136648d1 | 635 | if(mainTimer.read_ms() - timer > (timeout+95) ){ |
akashvibhute | 6:5cc7136648d1 | 636 | errNotify(); |
akashvibhute | 6:5cc7136648d1 | 637 | #if defined (FAILURE_HANDLING) |
akashvibhute | 6:5cc7136648d1 | 638 | return 0; |
akashvibhute | 6:5cc7136648d1 | 639 | #endif |
akashvibhute | 6:5cc7136648d1 | 640 | } |
akashvibhute | 6:5cc7136648d1 | 641 | #endif |
akashvibhute | 2:3bdf0d9bb71f | 642 | |
akashvibhute | 6:5cc7136648d1 | 643 | } |
akashvibhute | 2:3bdf0d9bb71f | 644 | |
akashvibhute | 6:5cc7136648d1 | 645 | //Start Writing |
akashvibhute | 6:5cc7136648d1 | 646 | startFastWrite(buf,len,0); //Write the payload if a buffer is clear |
akashvibhute | 6:5cc7136648d1 | 647 | |
akashvibhute | 6:5cc7136648d1 | 648 | return 1; //Return 1 to indicate successful transmission |
akashvibhute | 2:3bdf0d9bb71f | 649 | } |
akashvibhute | 2:3bdf0d9bb71f | 650 | |
akashvibhute | 2:3bdf0d9bb71f | 651 | /****************************************************************************/ |
akashvibhute | 2:3bdf0d9bb71f | 652 | |
akashvibhute | 6:5cc7136648d1 | 653 | void RF24::reUseTX(){ |
akashvibhute | 6:5cc7136648d1 | 654 | write_register(NRF_STATUS,_BV(MAX_RT) ); //Clear max retry flag |
akashvibhute | 6:5cc7136648d1 | 655 | spiTrans( REUSE_TX_PL ); |
akashvibhute | 6:5cc7136648d1 | 656 | ce(LOW); //Re-Transfer packet |
akashvibhute | 6:5cc7136648d1 | 657 | ce(HIGH); |
akashvibhute | 2:3bdf0d9bb71f | 658 | } |
akashvibhute | 2:3bdf0d9bb71f | 659 | |
akashvibhute | 2:3bdf0d9bb71f | 660 | /****************************************************************************/ |
akashvibhute | 2:3bdf0d9bb71f | 661 | |
akashvibhute | 2:3bdf0d9bb71f | 662 | bool RF24::writeFast( const void* buf, uint8_t len, const bool multicast ) |
akashvibhute | 0:bb74812ac6bb | 663 | { |
akashvibhute | 6:5cc7136648d1 | 664 | //Block until the FIFO is NOT full. |
akashvibhute | 6:5cc7136648d1 | 665 | //Keep track of the MAX retries and set auto-retry if seeing failures |
akashvibhute | 6:5cc7136648d1 | 666 | //Return 0 so the user can control the retrys and set a timer or failure counter if required |
akashvibhute | 6:5cc7136648d1 | 667 | //The radio will auto-clear everything in the FIFO as long as CE remains high |
akashvibhute | 2:3bdf0d9bb71f | 668 | |
akashvibhute | 6:5cc7136648d1 | 669 | #if defined (FAILURE_HANDLING) || defined (RF24_LINUX) |
akashvibhute | 6:5cc7136648d1 | 670 | uint32_t timer = mainTimer.read_ms(); |
akashvibhute | 6:5cc7136648d1 | 671 | #endif |
akashvibhute | 6:5cc7136648d1 | 672 | |
akashvibhute | 6:5cc7136648d1 | 673 | while( ( get_status() & ( _BV(TX_FULL) ))) { //Blocking only if FIFO is full. This will loop and block until TX is successful or fail |
akashvibhute | 2:3bdf0d9bb71f | 674 | |
akashvibhute | 6:5cc7136648d1 | 675 | if( get_status() & _BV(MAX_RT)){ |
akashvibhute | 6:5cc7136648d1 | 676 | //reUseTX(); //Set re-transmit |
akashvibhute | 6:5cc7136648d1 | 677 | write_register(NRF_STATUS,_BV(MAX_RT) ); //Clear max retry flag |
akashvibhute | 6:5cc7136648d1 | 678 | return 0; //Return 0. The previous payload has been retransmitted |
akashvibhute | 6:5cc7136648d1 | 679 | //From the user perspective, if you get a 0, just keep trying to send the same payload |
akashvibhute | 6:5cc7136648d1 | 680 | } |
akashvibhute | 6:5cc7136648d1 | 681 | #if defined (FAILURE_HANDLING) || defined (RF24_LINUX) |
akashvibhute | 6:5cc7136648d1 | 682 | if(mainTimer.read_ms() - timer > 95 ){ |
akashvibhute | 6:5cc7136648d1 | 683 | errNotify(); |
akashvibhute | 6:5cc7136648d1 | 684 | #if defined (FAILURE_HANDLING) |
akashvibhute | 6:5cc7136648d1 | 685 | return 0; |
akashvibhute | 6:5cc7136648d1 | 686 | #endif |
akashvibhute | 6:5cc7136648d1 | 687 | } |
akashvibhute | 6:5cc7136648d1 | 688 | #endif |
akashvibhute | 6:5cc7136648d1 | 689 | } |
akashvibhute | 6:5cc7136648d1 | 690 | //Start Writing |
akashvibhute | 6:5cc7136648d1 | 691 | startFastWrite(buf,len,multicast); |
akashvibhute | 2:3bdf0d9bb71f | 692 | |
akashvibhute | 6:5cc7136648d1 | 693 | return 1; |
akashvibhute | 2:3bdf0d9bb71f | 694 | } |
akashvibhute | 2:3bdf0d9bb71f | 695 | |
akashvibhute | 6:5cc7136648d1 | 696 | bool RF24::writeFast( const void* buf, uint8_t len ){ |
akashvibhute | 6:5cc7136648d1 | 697 | return writeFast(buf,len,0); |
akashvibhute | 2:3bdf0d9bb71f | 698 | } |
akashvibhute | 2:3bdf0d9bb71f | 699 | |
akashvibhute | 2:3bdf0d9bb71f | 700 | /****************************************************************************/ |
akashvibhute | 2:3bdf0d9bb71f | 701 | |
akashvibhute | 2:3bdf0d9bb71f | 702 | //Per the documentation, we want to set PTX Mode when not listening. Then all we do is write data and set CE high |
akashvibhute | 2:3bdf0d9bb71f | 703 | //In this mode, if we can keep the FIFO buffers loaded, packets will transmit immediately (no 130us delay) |
akashvibhute | 2:3bdf0d9bb71f | 704 | //Otherwise we enter Standby-II mode, which is still faster than standby mode |
akashvibhute | 2:3bdf0d9bb71f | 705 | //Also, we remove the need to keep writing the config register over and over and delaying for 150 us each time if sending a stream of data |
akashvibhute | 2:3bdf0d9bb71f | 706 | |
akashvibhute | 6:5cc7136648d1 | 707 | void RF24::startFastWrite( const void* buf, uint8_t len, const bool multicast, bool startTx){ //TMRh20 |
akashvibhute | 2:3bdf0d9bb71f | 708 | |
akashvibhute | 6:5cc7136648d1 | 709 | //write_payload( buf,len); |
akashvibhute | 6:5cc7136648d1 | 710 | write_payload( buf, len,multicast ? W_TX_PAYLOAD_NO_ACK : W_TX_PAYLOAD ) ; |
akashvibhute | 6:5cc7136648d1 | 711 | if(startTx){ |
akashvibhute | 6:5cc7136648d1 | 712 | ce(HIGH); |
akashvibhute | 6:5cc7136648d1 | 713 | } |
akashvibhute | 6:5cc7136648d1 | 714 | |
akashvibhute | 2:3bdf0d9bb71f | 715 | } |
akashvibhute | 2:3bdf0d9bb71f | 716 | |
akashvibhute | 2:3bdf0d9bb71f | 717 | /****************************************************************************/ |
akashvibhute | 2:3bdf0d9bb71f | 718 | |
akashvibhute | 2:3bdf0d9bb71f | 719 | //Added the original startWrite back in so users can still use interrupts, ack payloads, etc |
akashvibhute | 2:3bdf0d9bb71f | 720 | //Allows the library to pass all tests |
akashvibhute | 6:5cc7136648d1 | 721 | void RF24::startWrite( const void* buf, uint8_t len, const bool multicast ){ |
akashvibhute | 2:3bdf0d9bb71f | 722 | |
akashvibhute | 6:5cc7136648d1 | 723 | // Send the payload |
akashvibhute | 2:3bdf0d9bb71f | 724 | |
akashvibhute | 6:5cc7136648d1 | 725 | //write_payload( buf, len ); |
akashvibhute | 6:5cc7136648d1 | 726 | write_payload( buf, len,multicast? W_TX_PAYLOAD_NO_ACK : W_TX_PAYLOAD ) ; |
akashvibhute | 6:5cc7136648d1 | 727 | ce(HIGH); |
akashvibhute | 6:5cc7136648d1 | 728 | |
akashvibhute | 6:5cc7136648d1 | 729 | wait_us(10); |
akashvibhute | 6:5cc7136648d1 | 730 | |
akashvibhute | 6:5cc7136648d1 | 731 | ce(LOW); |
akashvibhute | 2:3bdf0d9bb71f | 732 | |
akashvibhute | 2:3bdf0d9bb71f | 733 | |
akashvibhute | 2:3bdf0d9bb71f | 734 | } |
akashvibhute | 2:3bdf0d9bb71f | 735 | |
akashvibhute | 2:3bdf0d9bb71f | 736 | /****************************************************************************/ |
akashvibhute | 2:3bdf0d9bb71f | 737 | |
akashvibhute | 6:5cc7136648d1 | 738 | bool RF24::rxFifoFull(){ |
akashvibhute | 6:5cc7136648d1 | 739 | return read_register(FIFO_STATUS) & _BV(RX_FULL); |
akashvibhute | 6:5cc7136648d1 | 740 | } |
akashvibhute | 6:5cc7136648d1 | 741 | /****************************************************************************/ |
akashvibhute | 6:5cc7136648d1 | 742 | |
akashvibhute | 6:5cc7136648d1 | 743 | bool RF24::txStandBy(){ |
akashvibhute | 6:5cc7136648d1 | 744 | |
akashvibhute | 6:5cc7136648d1 | 745 | #if defined (FAILURE_HANDLING) || defined (RF24_LINUX) |
akashvibhute | 6:5cc7136648d1 | 746 | uint32_t timeout = mainTimer.read_ms(); |
akashvibhute | 6:5cc7136648d1 | 747 | #endif |
akashvibhute | 6:5cc7136648d1 | 748 | while( ! (read_register(FIFO_STATUS) & _BV(TX_EMPTY)) ){ |
akashvibhute | 6:5cc7136648d1 | 749 | if( get_status() & _BV(MAX_RT)){ |
akashvibhute | 6:5cc7136648d1 | 750 | write_register(NRF_STATUS,_BV(MAX_RT) ); |
akashvibhute | 6:5cc7136648d1 | 751 | ce(LOW); |
akashvibhute | 6:5cc7136648d1 | 752 | flush_tx(); //Non blocking, flush the data |
akashvibhute | 6:5cc7136648d1 | 753 | return 0; |
akashvibhute | 6:5cc7136648d1 | 754 | } |
akashvibhute | 6:5cc7136648d1 | 755 | #if defined (FAILURE_HANDLING) || defined (RF24_LINUX) |
akashvibhute | 6:5cc7136648d1 | 756 | if( mainTimer.read_ms() - timeout > 95){ |
akashvibhute | 6:5cc7136648d1 | 757 | errNotify(); |
akashvibhute | 6:5cc7136648d1 | 758 | #if defined (FAILURE_HANDLING) |
akashvibhute | 6:5cc7136648d1 | 759 | return 0; |
akashvibhute | 6:5cc7136648d1 | 760 | #endif |
akashvibhute | 6:5cc7136648d1 | 761 | } |
akashvibhute | 6:5cc7136648d1 | 762 | #endif |
akashvibhute | 6:5cc7136648d1 | 763 | } |
akashvibhute | 6:5cc7136648d1 | 764 | |
akashvibhute | 6:5cc7136648d1 | 765 | ce(LOW); //Set STANDBY-I mode |
akashvibhute | 6:5cc7136648d1 | 766 | return 1; |
akashvibhute | 6:5cc7136648d1 | 767 | } |
akashvibhute | 6:5cc7136648d1 | 768 | |
akashvibhute | 6:5cc7136648d1 | 769 | /****************************************************************************/ |
akashvibhute | 6:5cc7136648d1 | 770 | |
akashvibhute | 6:5cc7136648d1 | 771 | bool RF24::txStandBy(uint32_t timeout, bool startTx){ |
akashvibhute | 2:3bdf0d9bb71f | 772 | |
akashvibhute | 6:5cc7136648d1 | 773 | if(startTx){ |
akashvibhute | 6:5cc7136648d1 | 774 | stopListening(); |
akashvibhute | 6:5cc7136648d1 | 775 | ce(HIGH); |
akashvibhute | 6:5cc7136648d1 | 776 | } |
akashvibhute | 6:5cc7136648d1 | 777 | uint32_t start = mainTimer.read_ms(); |
akashvibhute | 6:5cc7136648d1 | 778 | |
akashvibhute | 6:5cc7136648d1 | 779 | while( ! (read_register(FIFO_STATUS) & _BV(TX_EMPTY)) ){ |
akashvibhute | 6:5cc7136648d1 | 780 | if( get_status() & _BV(MAX_RT)){ |
akashvibhute | 6:5cc7136648d1 | 781 | write_register(NRF_STATUS,_BV(MAX_RT) ); |
akashvibhute | 6:5cc7136648d1 | 782 | ce(LOW); //Set re-transmit |
akashvibhute | 6:5cc7136648d1 | 783 | ce(HIGH); |
akashvibhute | 6:5cc7136648d1 | 784 | if(mainTimer.read_ms() - start >= timeout){ |
akashvibhute | 6:5cc7136648d1 | 785 | ce(LOW); flush_tx(); return 0; |
akashvibhute | 6:5cc7136648d1 | 786 | } |
akashvibhute | 6:5cc7136648d1 | 787 | } |
akashvibhute | 6:5cc7136648d1 | 788 | #if defined (FAILURE_HANDLING) || defined (RF24_LINUX) |
akashvibhute | 6:5cc7136648d1 | 789 | if( mainTimer.read_ms() - start > (timeout+95)){ |
akashvibhute | 6:5cc7136648d1 | 790 | errNotify(); |
akashvibhute | 6:5cc7136648d1 | 791 | #if defined (FAILURE_HANDLING) |
akashvibhute | 6:5cc7136648d1 | 792 | return 0; |
akashvibhute | 6:5cc7136648d1 | 793 | #endif |
akashvibhute | 6:5cc7136648d1 | 794 | } |
akashvibhute | 6:5cc7136648d1 | 795 | #endif |
akashvibhute | 6:5cc7136648d1 | 796 | } |
akashvibhute | 6:5cc7136648d1 | 797 | |
akashvibhute | 6:5cc7136648d1 | 798 | |
akashvibhute | 6:5cc7136648d1 | 799 | ce(LOW); //Set STANDBY-I mode |
akashvibhute | 6:5cc7136648d1 | 800 | return 1; |
akashvibhute | 6:5cc7136648d1 | 801 | |
akashvibhute | 6:5cc7136648d1 | 802 | } |
akashvibhute | 6:5cc7136648d1 | 803 | |
akashvibhute | 6:5cc7136648d1 | 804 | /****************************************************************************/ |
akashvibhute | 6:5cc7136648d1 | 805 | |
akashvibhute | 6:5cc7136648d1 | 806 | void RF24::maskIRQ(bool tx, bool fail, bool rx){ |
akashvibhute | 6:5cc7136648d1 | 807 | |
akashvibhute | 6:5cc7136648d1 | 808 | uint8_t config = read_register(NRF_CONFIG); |
akashvibhute | 6:5cc7136648d1 | 809 | /* clear the interrupt flags */ |
akashvibhute | 6:5cc7136648d1 | 810 | config &= ~(1 << MASK_MAX_RT | 1 << MASK_TX_DS | 1 << MASK_RX_DR); |
akashvibhute | 6:5cc7136648d1 | 811 | /* set the specified interrupt flags */ |
akashvibhute | 6:5cc7136648d1 | 812 | config |= fail << MASK_MAX_RT | tx << MASK_TX_DS | rx << MASK_RX_DR; |
akashvibhute | 6:5cc7136648d1 | 813 | write_register(NRF_CONFIG, config); |
akashvibhute | 0:bb74812ac6bb | 814 | } |
akashvibhute | 0:bb74812ac6bb | 815 | |
akashvibhute | 0:bb74812ac6bb | 816 | /****************************************************************************/ |
akashvibhute | 0:bb74812ac6bb | 817 | |
akashvibhute | 0:bb74812ac6bb | 818 | uint8_t RF24::getDynamicPayloadSize(void) |
akashvibhute | 0:bb74812ac6bb | 819 | { |
akashvibhute | 6:5cc7136648d1 | 820 | uint8_t result = 0; |
akashvibhute | 0:bb74812ac6bb | 821 | |
akashvibhute | 6:5cc7136648d1 | 822 | |
akashvibhute | 6:5cc7136648d1 | 823 | |
akashvibhute | 6:5cc7136648d1 | 824 | |
akashvibhute | 6:5cc7136648d1 | 825 | |
akashvibhute | 6:5cc7136648d1 | 826 | |
akashvibhute | 6:5cc7136648d1 | 827 | |
akashvibhute | 6:5cc7136648d1 | 828 | |
akashvibhute | 6:5cc7136648d1 | 829 | |
akashvibhute | 6:5cc7136648d1 | 830 | beginTransaction(); |
akashvibhute | 6:5cc7136648d1 | 831 | spi.write( R_RX_PL_WID ); |
akashvibhute | 6:5cc7136648d1 | 832 | result = spi.write(0xff); |
akashvibhute | 6:5cc7136648d1 | 833 | endTransaction(); |
akashvibhute | 6:5cc7136648d1 | 834 | |
akashvibhute | 0:bb74812ac6bb | 835 | |
akashvibhute | 6:5cc7136648d1 | 836 | if(result > 32) { flush_rx(); wait_ms(2); return 0; } |
akashvibhute | 6:5cc7136648d1 | 837 | return result; |
akashvibhute | 0:bb74812ac6bb | 838 | } |
akashvibhute | 0:bb74812ac6bb | 839 | |
akashvibhute | 0:bb74812ac6bb | 840 | /****************************************************************************/ |
akashvibhute | 0:bb74812ac6bb | 841 | |
akashvibhute | 0:bb74812ac6bb | 842 | bool RF24::available(void) |
akashvibhute | 0:bb74812ac6bb | 843 | { |
akashvibhute | 6:5cc7136648d1 | 844 | return available(NULL); |
akashvibhute | 0:bb74812ac6bb | 845 | } |
akashvibhute | 0:bb74812ac6bb | 846 | |
akashvibhute | 0:bb74812ac6bb | 847 | /****************************************************************************/ |
akashvibhute | 0:bb74812ac6bb | 848 | |
akashvibhute | 0:bb74812ac6bb | 849 | bool RF24::available(uint8_t* pipe_num) |
akashvibhute | 0:bb74812ac6bb | 850 | { |
akashvibhute | 6:5cc7136648d1 | 851 | if (!( read_register(FIFO_STATUS) & _BV(RX_EMPTY) )){ |
akashvibhute | 0:bb74812ac6bb | 852 | |
akashvibhute | 6:5cc7136648d1 | 853 | // If the caller wants the pipe number, include that |
akashvibhute | 6:5cc7136648d1 | 854 | if ( pipe_num ){ |
akashvibhute | 6:5cc7136648d1 | 855 | uint8_t status = get_status(); |
akashvibhute | 6:5cc7136648d1 | 856 | *pipe_num = ( status >> RX_P_NO ) & 0b111; |
akashvibhute | 6:5cc7136648d1 | 857 | } |
akashvibhute | 6:5cc7136648d1 | 858 | return 1; |
akashvibhute | 6:5cc7136648d1 | 859 | } |
akashvibhute | 3:e94be00fd19e | 860 | |
akashvibhute | 6:5cc7136648d1 | 861 | |
akashvibhute | 6:5cc7136648d1 | 862 | return 0; |
akashvibhute | 6:5cc7136648d1 | 863 | |
akashvibhute | 6:5cc7136648d1 | 864 | |
akashvibhute | 0:bb74812ac6bb | 865 | } |
akashvibhute | 0:bb74812ac6bb | 866 | |
akashvibhute | 0:bb74812ac6bb | 867 | /****************************************************************************/ |
akashvibhute | 0:bb74812ac6bb | 868 | |
akashvibhute | 6:5cc7136648d1 | 869 | void RF24::read( void* buf, uint8_t len ){ |
akashvibhute | 2:3bdf0d9bb71f | 870 | |
akashvibhute | 6:5cc7136648d1 | 871 | // Fetch the payload |
akashvibhute | 6:5cc7136648d1 | 872 | read_payload( buf, len ); |
akashvibhute | 0:bb74812ac6bb | 873 | |
akashvibhute | 6:5cc7136648d1 | 874 | //Clear the two possible interrupt flags with one command |
akashvibhute | 6:5cc7136648d1 | 875 | write_register(NRF_STATUS,_BV(RX_DR) | _BV(MAX_RT) | _BV(TX_DS) ); |
akashvibhute | 6:5cc7136648d1 | 876 | |
akashvibhute | 0:bb74812ac6bb | 877 | } |
akashvibhute | 0:bb74812ac6bb | 878 | |
akashvibhute | 0:bb74812ac6bb | 879 | /****************************************************************************/ |
akashvibhute | 0:bb74812ac6bb | 880 | |
akashvibhute | 0:bb74812ac6bb | 881 | void RF24::whatHappened(bool& tx_ok,bool& tx_fail,bool& rx_ready) |
akashvibhute | 0:bb74812ac6bb | 882 | { |
akashvibhute | 6:5cc7136648d1 | 883 | // Read the status & reset the status in one easy call |
akashvibhute | 6:5cc7136648d1 | 884 | // Or is that such a good idea? |
akashvibhute | 6:5cc7136648d1 | 885 | uint8_t status = write_register(NRF_STATUS,_BV(RX_DR) | _BV(TX_DS) | _BV(MAX_RT) ); |
akashvibhute | 0:bb74812ac6bb | 886 | |
akashvibhute | 6:5cc7136648d1 | 887 | // Report to the user what happened |
akashvibhute | 6:5cc7136648d1 | 888 | tx_ok = status & _BV(TX_DS); |
akashvibhute | 6:5cc7136648d1 | 889 | tx_fail = status & _BV(MAX_RT); |
akashvibhute | 6:5cc7136648d1 | 890 | rx_ready = status & _BV(RX_DR); |
akashvibhute | 0:bb74812ac6bb | 891 | } |
akashvibhute | 0:bb74812ac6bb | 892 | |
akashvibhute | 0:bb74812ac6bb | 893 | /****************************************************************************/ |
akashvibhute | 0:bb74812ac6bb | 894 | |
akashvibhute | 0:bb74812ac6bb | 895 | void RF24::openWritingPipe(uint64_t value) |
akashvibhute | 0:bb74812ac6bb | 896 | { |
akashvibhute | 6:5cc7136648d1 | 897 | // Note that AVR 8-bit uC's store this LSB first, and the NRF24L01(+) |
akashvibhute | 6:5cc7136648d1 | 898 | // expects it LSB first too, so we're good. |
akashvibhute | 0:bb74812ac6bb | 899 | |
akashvibhute | 6:5cc7136648d1 | 900 | write_register(RX_ADDR_P0, reinterpret_cast<uint8_t*>(&value), addr_width); |
akashvibhute | 6:5cc7136648d1 | 901 | write_register(TX_ADDR, reinterpret_cast<uint8_t*>(&value), addr_width); |
akashvibhute | 6:5cc7136648d1 | 902 | |
akashvibhute | 6:5cc7136648d1 | 903 | |
akashvibhute | 6:5cc7136648d1 | 904 | //const uint8_t max_payload_size = 32; |
akashvibhute | 6:5cc7136648d1 | 905 | //write_register(RX_PW_P0,rf24_min(payload_size,max_payload_size)); |
akashvibhute | 6:5cc7136648d1 | 906 | write_register(RX_PW_P0,payload_size); |
akashvibhute | 0:bb74812ac6bb | 907 | } |
akashvibhute | 0:bb74812ac6bb | 908 | |
akashvibhute | 0:bb74812ac6bb | 909 | /****************************************************************************/ |
akashvibhute | 2:3bdf0d9bb71f | 910 | void RF24::openWritingPipe(const uint8_t *address) |
akashvibhute | 2:3bdf0d9bb71f | 911 | { |
akashvibhute | 6:5cc7136648d1 | 912 | // Note that AVR 8-bit uC's store this LSB first, and the NRF24L01(+) |
akashvibhute | 6:5cc7136648d1 | 913 | // expects it LSB first too, so we're good. |
akashvibhute | 0:bb74812ac6bb | 914 | |
akashvibhute | 6:5cc7136648d1 | 915 | write_register(RX_ADDR_P0,address, addr_width); |
akashvibhute | 6:5cc7136648d1 | 916 | write_register(TX_ADDR, address, addr_width); |
akashvibhute | 2:3bdf0d9bb71f | 917 | |
akashvibhute | 6:5cc7136648d1 | 918 | //const uint8_t max_payload_size = 32; |
akashvibhute | 6:5cc7136648d1 | 919 | //write_register(RX_PW_P0,rf24_min(payload_size,max_payload_size)); |
akashvibhute | 6:5cc7136648d1 | 920 | write_register(RX_PW_P0,payload_size); |
akashvibhute | 2:3bdf0d9bb71f | 921 | } |
akashvibhute | 2:3bdf0d9bb71f | 922 | |
akashvibhute | 2:3bdf0d9bb71f | 923 | /****************************************************************************/ |
akashvibhute | 6:5cc7136648d1 | 924 | static const uint8_t child_pipe[] PROGMEM = |
akashvibhute | 6:5cc7136648d1 | 925 | { |
akashvibhute | 6:5cc7136648d1 | 926 | RX_ADDR_P0, RX_ADDR_P1, RX_ADDR_P2, RX_ADDR_P3, RX_ADDR_P4, RX_ADDR_P5 |
akashvibhute | 0:bb74812ac6bb | 927 | }; |
akashvibhute | 6:5cc7136648d1 | 928 | static const uint8_t child_payload_size[] PROGMEM = |
akashvibhute | 6:5cc7136648d1 | 929 | { |
akashvibhute | 6:5cc7136648d1 | 930 | RX_PW_P0, RX_PW_P1, RX_PW_P2, RX_PW_P3, RX_PW_P4, RX_PW_P5 |
akashvibhute | 0:bb74812ac6bb | 931 | }; |
akashvibhute | 2:3bdf0d9bb71f | 932 | |
akashvibhute | 0:bb74812ac6bb | 933 | |
akashvibhute | 0:bb74812ac6bb | 934 | void RF24::openReadingPipe(uint8_t child, uint64_t address) |
akashvibhute | 0:bb74812ac6bb | 935 | { |
akashvibhute | 6:5cc7136648d1 | 936 | // If this is pipe 0, cache the address. This is needed because |
akashvibhute | 6:5cc7136648d1 | 937 | // openWritingPipe() will overwrite the pipe 0 address, so |
akashvibhute | 6:5cc7136648d1 | 938 | // startListening() will have to restore it. |
akashvibhute | 6:5cc7136648d1 | 939 | if (child == 0){ |
akashvibhute | 6:5cc7136648d1 | 940 | memcpy(pipe0_reading_address,&address,addr_width); |
akashvibhute | 6:5cc7136648d1 | 941 | } |
akashvibhute | 0:bb74812ac6bb | 942 | |
akashvibhute | 6:5cc7136648d1 | 943 | if (child <= 6) |
akashvibhute | 6:5cc7136648d1 | 944 | { |
akashvibhute | 6:5cc7136648d1 | 945 | // For pipes 2-5, only write the LSB |
akashvibhute | 6:5cc7136648d1 | 946 | if ( child < 2 ) |
akashvibhute | 6:5cc7136648d1 | 947 | write_register(pgm_read_byte(&child_pipe[child]), reinterpret_cast<const uint8_t*>(&address), addr_width); |
akashvibhute | 6:5cc7136648d1 | 948 | else |
akashvibhute | 6:5cc7136648d1 | 949 | write_register(pgm_read_byte(&child_pipe[child]), reinterpret_cast<const uint8_t*>(&address), 1); |
akashvibhute | 0:bb74812ac6bb | 950 | |
akashvibhute | 6:5cc7136648d1 | 951 | write_register(pgm_read_byte(&child_payload_size[child]),payload_size); |
akashvibhute | 0:bb74812ac6bb | 952 | |
akashvibhute | 6:5cc7136648d1 | 953 | // Note it would be more efficient to set all of the bits for all open |
akashvibhute | 6:5cc7136648d1 | 954 | // pipes at once. However, I thought it would make the calling code |
akashvibhute | 6:5cc7136648d1 | 955 | // more simple to do it this way. |
akashvibhute | 6:5cc7136648d1 | 956 | write_register(EN_RXADDR,read_register(EN_RXADDR) | _BV(pgm_read_byte(&child_pipe_enable[child]))); |
akashvibhute | 6:5cc7136648d1 | 957 | } |
akashvibhute | 2:3bdf0d9bb71f | 958 | } |
akashvibhute | 2:3bdf0d9bb71f | 959 | |
akashvibhute | 2:3bdf0d9bb71f | 960 | /****************************************************************************/ |
akashvibhute | 6:5cc7136648d1 | 961 | void RF24::setAddressWidth(uint8_t a_width){ |
akashvibhute | 2:3bdf0d9bb71f | 962 | |
akashvibhute | 6:5cc7136648d1 | 963 | if(a_width -= 2){ |
akashvibhute | 6:5cc7136648d1 | 964 | write_register(SETUP_AW,a_width%4); |
akashvibhute | 6:5cc7136648d1 | 965 | addr_width = (a_width%4) + 2; |
akashvibhute | 6:5cc7136648d1 | 966 | } |
akashvibhute | 6:5cc7136648d1 | 967 | |
akashvibhute | 2:3bdf0d9bb71f | 968 | } |
akashvibhute | 2:3bdf0d9bb71f | 969 | |
akashvibhute | 2:3bdf0d9bb71f | 970 | /****************************************************************************/ |
akashvibhute | 2:3bdf0d9bb71f | 971 | |
akashvibhute | 2:3bdf0d9bb71f | 972 | void RF24::openReadingPipe(uint8_t child, const uint8_t *address) |
akashvibhute | 2:3bdf0d9bb71f | 973 | { |
akashvibhute | 6:5cc7136648d1 | 974 | // If this is pipe 0, cache the address. This is needed because |
akashvibhute | 6:5cc7136648d1 | 975 | // openWritingPipe() will overwrite the pipe 0 address, so |
akashvibhute | 6:5cc7136648d1 | 976 | // startListening() will have to restore it. |
akashvibhute | 6:5cc7136648d1 | 977 | if (child == 0){ |
akashvibhute | 6:5cc7136648d1 | 978 | memcpy(pipe0_reading_address,address,addr_width); |
akashvibhute | 6:5cc7136648d1 | 979 | } |
akashvibhute | 6:5cc7136648d1 | 980 | if (child <= 6) |
akashvibhute | 6:5cc7136648d1 | 981 | { |
akashvibhute | 6:5cc7136648d1 | 982 | // For pipes 2-5, only write the LSB |
akashvibhute | 6:5cc7136648d1 | 983 | if ( child < 2 ){ |
akashvibhute | 6:5cc7136648d1 | 984 | write_register(pgm_read_byte(&child_pipe[child]), address, addr_width); |
akashvibhute | 6:5cc7136648d1 | 985 | }else{ |
akashvibhute | 6:5cc7136648d1 | 986 | write_register(pgm_read_byte(&child_pipe[child]), address, 1); |
akashvibhute | 6:5cc7136648d1 | 987 | } |
akashvibhute | 6:5cc7136648d1 | 988 | write_register(pgm_read_byte(&child_payload_size[child]),payload_size); |
akashvibhute | 2:3bdf0d9bb71f | 989 | |
akashvibhute | 6:5cc7136648d1 | 990 | // Note it would be more efficient to set all of the bits for all open |
akashvibhute | 6:5cc7136648d1 | 991 | // pipes at once. However, I thought it would make the calling code |
akashvibhute | 6:5cc7136648d1 | 992 | // more simple to do it this way. |
akashvibhute | 6:5cc7136648d1 | 993 | write_register(EN_RXADDR,read_register(EN_RXADDR) | _BV(pgm_read_byte(&child_pipe_enable[child]))); |
akashvibhute | 6:5cc7136648d1 | 994 | |
akashvibhute | 6:5cc7136648d1 | 995 | } |
akashvibhute | 2:3bdf0d9bb71f | 996 | } |
akashvibhute | 2:3bdf0d9bb71f | 997 | |
akashvibhute | 2:3bdf0d9bb71f | 998 | /****************************************************************************/ |
akashvibhute | 2:3bdf0d9bb71f | 999 | |
akashvibhute | 2:3bdf0d9bb71f | 1000 | void RF24::closeReadingPipe( uint8_t pipe ) |
akashvibhute | 2:3bdf0d9bb71f | 1001 | { |
akashvibhute | 6:5cc7136648d1 | 1002 | write_register(EN_RXADDR,read_register(EN_RXADDR) & ~_BV(pgm_read_byte(&child_pipe_enable[pipe]))); |
akashvibhute | 0:bb74812ac6bb | 1003 | } |
akashvibhute | 0:bb74812ac6bb | 1004 | |
akashvibhute | 0:bb74812ac6bb | 1005 | /****************************************************************************/ |
akashvibhute | 0:bb74812ac6bb | 1006 | |
akashvibhute | 0:bb74812ac6bb | 1007 | void RF24::toggle_features(void) |
akashvibhute | 0:bb74812ac6bb | 1008 | { |
akashvibhute | 2:3bdf0d9bb71f | 1009 | beginTransaction(); |
akashvibhute | 6:5cc7136648d1 | 1010 | spi.write( ACTIVATE ); |
akashvibhute | 2:3bdf0d9bb71f | 1011 | spi.write( 0x73 ); |
akashvibhute | 6:5cc7136648d1 | 1012 | endTransaction(); |
akashvibhute | 0:bb74812ac6bb | 1013 | } |
akashvibhute | 0:bb74812ac6bb | 1014 | |
akashvibhute | 0:bb74812ac6bb | 1015 | /****************************************************************************/ |
akashvibhute | 0:bb74812ac6bb | 1016 | |
akashvibhute | 0:bb74812ac6bb | 1017 | void RF24::enableDynamicPayloads(void) |
akashvibhute | 0:bb74812ac6bb | 1018 | { |
akashvibhute | 6:5cc7136648d1 | 1019 | // Enable dynamic payload throughout the system |
akashvibhute | 0:bb74812ac6bb | 1020 | |
akashvibhute | 2:3bdf0d9bb71f | 1021 | //toggle_features(); |
akashvibhute | 0:bb74812ac6bb | 1022 | write_register(FEATURE,read_register(FEATURE) | _BV(EN_DPL) ); |
akashvibhute | 2:3bdf0d9bb71f | 1023 | |
akashvibhute | 6:5cc7136648d1 | 1024 | |
akashvibhute | 6:5cc7136648d1 | 1025 | IF_SERIAL_DEBUG(printf("FEATURE=%i\r\n",read_register(FEATURE))); |
akashvibhute | 0:bb74812ac6bb | 1026 | |
akashvibhute | 6:5cc7136648d1 | 1027 | // Enable dynamic payload on all pipes |
akashvibhute | 6:5cc7136648d1 | 1028 | // |
akashvibhute | 6:5cc7136648d1 | 1029 | // Not sure the use case of only having dynamic payload on certain |
akashvibhute | 6:5cc7136648d1 | 1030 | // pipes, so the library does not support it. |
akashvibhute | 6:5cc7136648d1 | 1031 | write_register(DYNPD,read_register(DYNPD) | _BV(DPL_P5) | _BV(DPL_P4) | _BV(DPL_P3) | _BV(DPL_P2) | _BV(DPL_P1) | _BV(DPL_P0)); |
akashvibhute | 0:bb74812ac6bb | 1032 | |
akashvibhute | 6:5cc7136648d1 | 1033 | dynamic_payloads_enabled = true; |
akashvibhute | 0:bb74812ac6bb | 1034 | } |
akashvibhute | 0:bb74812ac6bb | 1035 | |
akashvibhute | 0:bb74812ac6bb | 1036 | /****************************************************************************/ |
akashvibhute | 0:bb74812ac6bb | 1037 | |
akashvibhute | 0:bb74812ac6bb | 1038 | void RF24::enableAckPayload(void) |
akashvibhute | 0:bb74812ac6bb | 1039 | { |
akashvibhute | 6:5cc7136648d1 | 1040 | // |
akashvibhute | 6:5cc7136648d1 | 1041 | // enable ack payload and dynamic payload features |
akashvibhute | 6:5cc7136648d1 | 1042 | // |
akashvibhute | 0:bb74812ac6bb | 1043 | |
akashvibhute | 2:3bdf0d9bb71f | 1044 | //toggle_features(); |
akashvibhute | 2:3bdf0d9bb71f | 1045 | write_register(FEATURE,read_register(FEATURE) | _BV(EN_ACK_PAY) | _BV(EN_DPL) ); |
akashvibhute | 0:bb74812ac6bb | 1046 | |
akashvibhute | 6:5cc7136648d1 | 1047 | IF_SERIAL_DEBUG(printf("FEATURE=%i\r\n",read_register(FEATURE))); |
akashvibhute | 0:bb74812ac6bb | 1048 | |
akashvibhute | 6:5cc7136648d1 | 1049 | // |
akashvibhute | 6:5cc7136648d1 | 1050 | // Enable dynamic payload on pipes 0 & 1 |
akashvibhute | 6:5cc7136648d1 | 1051 | // |
akashvibhute | 0:bb74812ac6bb | 1052 | |
akashvibhute | 6:5cc7136648d1 | 1053 | write_register(DYNPD,read_register(DYNPD) | _BV(DPL_P1) | _BV(DPL_P0)); |
akashvibhute | 6:5cc7136648d1 | 1054 | dynamic_payloads_enabled = true; |
akashvibhute | 2:3bdf0d9bb71f | 1055 | } |
akashvibhute | 2:3bdf0d9bb71f | 1056 | |
akashvibhute | 2:3bdf0d9bb71f | 1057 | /****************************************************************************/ |
akashvibhute | 2:3bdf0d9bb71f | 1058 | |
akashvibhute | 6:5cc7136648d1 | 1059 | void RF24::enableDynamicAck(void){ |
akashvibhute | 6:5cc7136648d1 | 1060 | // |
akashvibhute | 6:5cc7136648d1 | 1061 | // enable dynamic ack features |
akashvibhute | 6:5cc7136648d1 | 1062 | // |
akashvibhute | 2:3bdf0d9bb71f | 1063 | //toggle_features(); |
akashvibhute | 2:3bdf0d9bb71f | 1064 | write_register(FEATURE,read_register(FEATURE) | _BV(EN_DYN_ACK) ); |
akashvibhute | 2:3bdf0d9bb71f | 1065 | |
akashvibhute | 6:5cc7136648d1 | 1066 | IF_SERIAL_DEBUG(printf("FEATURE=%i\r\n",read_register(FEATURE))); |
akashvibhute | 2:3bdf0d9bb71f | 1067 | |
akashvibhute | 2:3bdf0d9bb71f | 1068 | |
akashvibhute | 0:bb74812ac6bb | 1069 | } |
akashvibhute | 0:bb74812ac6bb | 1070 | |
akashvibhute | 0:bb74812ac6bb | 1071 | /****************************************************************************/ |
akashvibhute | 0:bb74812ac6bb | 1072 | |
akashvibhute | 0:bb74812ac6bb | 1073 | void RF24::writeAckPayload(uint8_t pipe, const void* buf, uint8_t len) |
akashvibhute | 0:bb74812ac6bb | 1074 | { |
akashvibhute | 6:5cc7136648d1 | 1075 | const uint8_t* current = reinterpret_cast<const uint8_t*>(buf); |
akashvibhute | 0:bb74812ac6bb | 1076 | |
akashvibhute | 6:5cc7136648d1 | 1077 | uint8_t data_len = rf24_min(len,32); |
akashvibhute | 2:3bdf0d9bb71f | 1078 | |
akashvibhute | 6:5cc7136648d1 | 1079 | |
akashvibhute | 6:5cc7136648d1 | 1080 | |
akashvibhute | 6:5cc7136648d1 | 1081 | |
akashvibhute | 6:5cc7136648d1 | 1082 | |
akashvibhute | 6:5cc7136648d1 | 1083 | |
akashvibhute | 6:5cc7136648d1 | 1084 | |
akashvibhute | 6:5cc7136648d1 | 1085 | |
akashvibhute | 6:5cc7136648d1 | 1086 | |
akashvibhute | 6:5cc7136648d1 | 1087 | |
akashvibhute | 6:5cc7136648d1 | 1088 | |
akashvibhute | 6:5cc7136648d1 | 1089 | |
akashvibhute | 6:5cc7136648d1 | 1090 | |
akashvibhute | 6:5cc7136648d1 | 1091 | beginTransaction(); |
akashvibhute | 6:5cc7136648d1 | 1092 | spi.write(W_ACK_PAYLOAD | ( pipe & 0b111 ) ); |
akashvibhute | 2:3bdf0d9bb71f | 1093 | |
akashvibhute | 6:5cc7136648d1 | 1094 | while ( data_len-- ) |
akashvibhute | 6:5cc7136648d1 | 1095 | spi.write(*current++); |
akashvibhute | 6:5cc7136648d1 | 1096 | endTransaction(); |
akashvibhute | 6:5cc7136648d1 | 1097 | |
akashvibhute | 6:5cc7136648d1 | 1098 | |
akashvibhute | 0:bb74812ac6bb | 1099 | |
akashvibhute | 0:bb74812ac6bb | 1100 | } |
akashvibhute | 0:bb74812ac6bb | 1101 | |
akashvibhute | 0:bb74812ac6bb | 1102 | /****************************************************************************/ |
akashvibhute | 0:bb74812ac6bb | 1103 | |
akashvibhute | 0:bb74812ac6bb | 1104 | bool RF24::isAckPayloadAvailable(void) |
akashvibhute | 0:bb74812ac6bb | 1105 | { |
akashvibhute | 6:5cc7136648d1 | 1106 | return ! (read_register(FIFO_STATUS) & _BV(RX_EMPTY)); |
akashvibhute | 0:bb74812ac6bb | 1107 | } |
akashvibhute | 0:bb74812ac6bb | 1108 | |
akashvibhute | 0:bb74812ac6bb | 1109 | /****************************************************************************/ |
akashvibhute | 0:bb74812ac6bb | 1110 | |
akashvibhute | 0:bb74812ac6bb | 1111 | bool RF24::isPVariant(void) |
akashvibhute | 0:bb74812ac6bb | 1112 | { |
akashvibhute | 6:5cc7136648d1 | 1113 | return p_variant ; |
akashvibhute | 0:bb74812ac6bb | 1114 | } |
akashvibhute | 0:bb74812ac6bb | 1115 | |
akashvibhute | 0:bb74812ac6bb | 1116 | /****************************************************************************/ |
akashvibhute | 0:bb74812ac6bb | 1117 | |
akashvibhute | 0:bb74812ac6bb | 1118 | void RF24::setAutoAck(bool enable) |
akashvibhute | 0:bb74812ac6bb | 1119 | { |
akashvibhute | 6:5cc7136648d1 | 1120 | if ( enable ) |
akashvibhute | 6:5cc7136648d1 | 1121 | write_register(EN_AA, 0b111111); |
akashvibhute | 6:5cc7136648d1 | 1122 | else |
akashvibhute | 6:5cc7136648d1 | 1123 | write_register(EN_AA, 0); |
akashvibhute | 0:bb74812ac6bb | 1124 | } |
akashvibhute | 0:bb74812ac6bb | 1125 | |
akashvibhute | 0:bb74812ac6bb | 1126 | /****************************************************************************/ |
akashvibhute | 0:bb74812ac6bb | 1127 | |
akashvibhute | 0:bb74812ac6bb | 1128 | void RF24::setAutoAck( uint8_t pipe, bool enable ) |
akashvibhute | 0:bb74812ac6bb | 1129 | { |
akashvibhute | 6:5cc7136648d1 | 1130 | if ( pipe <= 6 ) |
akashvibhute | 6:5cc7136648d1 | 1131 | { |
akashvibhute | 6:5cc7136648d1 | 1132 | uint8_t en_aa = read_register( EN_AA ) ; |
akashvibhute | 6:5cc7136648d1 | 1133 | if( enable ) |
akashvibhute | 6:5cc7136648d1 | 1134 | { |
akashvibhute | 6:5cc7136648d1 | 1135 | en_aa |= _BV(pipe) ; |
akashvibhute | 0:bb74812ac6bb | 1136 | } |
akashvibhute | 6:5cc7136648d1 | 1137 | else |
akashvibhute | 6:5cc7136648d1 | 1138 | { |
akashvibhute | 6:5cc7136648d1 | 1139 | en_aa &= ~_BV(pipe) ; |
akashvibhute | 6:5cc7136648d1 | 1140 | } |
akashvibhute | 6:5cc7136648d1 | 1141 | write_register( EN_AA, en_aa ) ; |
akashvibhute | 6:5cc7136648d1 | 1142 | } |
akashvibhute | 0:bb74812ac6bb | 1143 | } |
akashvibhute | 0:bb74812ac6bb | 1144 | |
akashvibhute | 0:bb74812ac6bb | 1145 | /****************************************************************************/ |
akashvibhute | 0:bb74812ac6bb | 1146 | |
akashvibhute | 0:bb74812ac6bb | 1147 | bool RF24::testCarrier(void) |
akashvibhute | 0:bb74812ac6bb | 1148 | { |
akashvibhute | 6:5cc7136648d1 | 1149 | return ( read_register(CD) & 1 ); |
akashvibhute | 0:bb74812ac6bb | 1150 | } |
akashvibhute | 0:bb74812ac6bb | 1151 | |
akashvibhute | 0:bb74812ac6bb | 1152 | /****************************************************************************/ |
akashvibhute | 0:bb74812ac6bb | 1153 | |
akashvibhute | 0:bb74812ac6bb | 1154 | bool RF24::testRPD(void) |
akashvibhute | 0:bb74812ac6bb | 1155 | { |
akashvibhute | 6:5cc7136648d1 | 1156 | return ( read_register(RPD) & 1 ) ; |
akashvibhute | 0:bb74812ac6bb | 1157 | } |
akashvibhute | 0:bb74812ac6bb | 1158 | |
akashvibhute | 0:bb74812ac6bb | 1159 | /****************************************************************************/ |
akashvibhute | 0:bb74812ac6bb | 1160 | |
akashvibhute | 2:3bdf0d9bb71f | 1161 | void RF24::setPALevel(uint8_t level) |
akashvibhute | 0:bb74812ac6bb | 1162 | { |
akashvibhute | 2:3bdf0d9bb71f | 1163 | |
akashvibhute | 6:5cc7136648d1 | 1164 | uint8_t setup = read_register(RF_SETUP) & 0b11111000; |
akashvibhute | 0:bb74812ac6bb | 1165 | |
akashvibhute | 6:5cc7136648d1 | 1166 | if(level > 3){ // If invalid level, go to max PA |
akashvibhute | 6:5cc7136648d1 | 1167 | level = (RF24_PA_MAX << 1) + 1; // +1 to support the SI24R1 chip extra bit |
akashvibhute | 6:5cc7136648d1 | 1168 | }else{ |
akashvibhute | 6:5cc7136648d1 | 1169 | level = (level << 1) + 1; // Else set level as requested |
akashvibhute | 6:5cc7136648d1 | 1170 | } |
akashvibhute | 0:bb74812ac6bb | 1171 | |
akashvibhute | 2:3bdf0d9bb71f | 1172 | |
akashvibhute | 6:5cc7136648d1 | 1173 | write_register( RF_SETUP, setup |= level ) ; // Write it to the chip |
akashvibhute | 0:bb74812ac6bb | 1174 | } |
akashvibhute | 0:bb74812ac6bb | 1175 | |
akashvibhute | 0:bb74812ac6bb | 1176 | /****************************************************************************/ |
akashvibhute | 0:bb74812ac6bb | 1177 | |
akashvibhute | 2:3bdf0d9bb71f | 1178 | uint8_t RF24::getPALevel(void) |
akashvibhute | 0:bb74812ac6bb | 1179 | { |
akashvibhute | 0:bb74812ac6bb | 1180 | |
akashvibhute | 6:5cc7136648d1 | 1181 | return (read_register(RF_SETUP) & (_BV(RF_PWR_LOW) | _BV(RF_PWR_HIGH))) >> 1 ; |
akashvibhute | 0:bb74812ac6bb | 1182 | } |
akashvibhute | 0:bb74812ac6bb | 1183 | |
akashvibhute | 0:bb74812ac6bb | 1184 | /****************************************************************************/ |
akashvibhute | 0:bb74812ac6bb | 1185 | |
akashvibhute | 0:bb74812ac6bb | 1186 | bool RF24::setDataRate(rf24_datarate_e speed) |
akashvibhute | 0:bb74812ac6bb | 1187 | { |
akashvibhute | 6:5cc7136648d1 | 1188 | bool result = false; |
akashvibhute | 6:5cc7136648d1 | 1189 | uint8_t setup = read_register(RF_SETUP) ; |
akashvibhute | 0:bb74812ac6bb | 1190 | |
akashvibhute | 6:5cc7136648d1 | 1191 | // HIGH and LOW '00' is 1Mbs - our default |
akashvibhute | 6:5cc7136648d1 | 1192 | setup &= ~(_BV(RF_DR_LOW) | _BV(RF_DR_HIGH)) ; |
akashvibhute | 6:5cc7136648d1 | 1193 | |
akashvibhute | 6:5cc7136648d1 | 1194 | |
akashvibhute | 6:5cc7136648d1 | 1195 | |
akashvibhute | 6:5cc7136648d1 | 1196 | |
akashvibhute | 2:3bdf0d9bb71f | 1197 | txRxDelay=85; |
akashvibhute | 2:3bdf0d9bb71f | 1198 | |
akashvibhute | 6:5cc7136648d1 | 1199 | if( speed == RF24_250KBPS ) |
akashvibhute | 6:5cc7136648d1 | 1200 | { |
akashvibhute | 6:5cc7136648d1 | 1201 | // Must set the RF_DR_LOW to 1; RF_DR_HIGH (used to be RF_DR) is already 0 |
akashvibhute | 6:5cc7136648d1 | 1202 | // Making it '10'. |
akashvibhute | 6:5cc7136648d1 | 1203 | setup |= _BV( RF_DR_LOW ) ; |
akashvibhute | 6:5cc7136648d1 | 1204 | |
akashvibhute | 6:5cc7136648d1 | 1205 | |
akashvibhute | 6:5cc7136648d1 | 1206 | |
akashvibhute | 6:5cc7136648d1 | 1207 | txRxDelay=155; |
akashvibhute | 6:5cc7136648d1 | 1208 | |
akashvibhute | 6:5cc7136648d1 | 1209 | } |
akashvibhute | 6:5cc7136648d1 | 1210 | else |
akashvibhute | 6:5cc7136648d1 | 1211 | { |
akashvibhute | 6:5cc7136648d1 | 1212 | // Set 2Mbs, RF_DR (RF_DR_HIGH) is set 1 |
akashvibhute | 6:5cc7136648d1 | 1213 | // Making it '01' |
akashvibhute | 6:5cc7136648d1 | 1214 | if ( speed == RF24_2MBPS ) |
akashvibhute | 6:5cc7136648d1 | 1215 | { |
akashvibhute | 6:5cc7136648d1 | 1216 | setup |= _BV(RF_DR_HIGH); |
akashvibhute | 6:5cc7136648d1 | 1217 | |
akashvibhute | 6:5cc7136648d1 | 1218 | |
akashvibhute | 6:5cc7136648d1 | 1219 | //txRxDelay=65; |
akashvibhute | 6:5cc7136648d1 | 1220 | txRxDelay=15; //mbed works fine with this latency |
akashvibhute | 6:5cc7136648d1 | 1221 | |
akashvibhute | 0:bb74812ac6bb | 1222 | } |
akashvibhute | 6:5cc7136648d1 | 1223 | } |
akashvibhute | 6:5cc7136648d1 | 1224 | write_register(RF_SETUP,setup); |
akashvibhute | 0:bb74812ac6bb | 1225 | |
akashvibhute | 6:5cc7136648d1 | 1226 | // Verify our result |
akashvibhute | 6:5cc7136648d1 | 1227 | if ( read_register(RF_SETUP) == setup ) |
akashvibhute | 6:5cc7136648d1 | 1228 | { |
akashvibhute | 6:5cc7136648d1 | 1229 | result = true; |
akashvibhute | 6:5cc7136648d1 | 1230 | } |
akashvibhute | 6:5cc7136648d1 | 1231 | return result; |
akashvibhute | 0:bb74812ac6bb | 1232 | } |
akashvibhute | 0:bb74812ac6bb | 1233 | |
akashvibhute | 0:bb74812ac6bb | 1234 | /****************************************************************************/ |
akashvibhute | 0:bb74812ac6bb | 1235 | |
akashvibhute | 0:bb74812ac6bb | 1236 | rf24_datarate_e RF24::getDataRate( void ) |
akashvibhute | 0:bb74812ac6bb | 1237 | { |
akashvibhute | 6:5cc7136648d1 | 1238 | rf24_datarate_e result ; |
akashvibhute | 6:5cc7136648d1 | 1239 | uint8_t dr = read_register(RF_SETUP) & (_BV(RF_DR_LOW) | _BV(RF_DR_HIGH)); |
akashvibhute | 2:3bdf0d9bb71f | 1240 | |
akashvibhute | 6:5cc7136648d1 | 1241 | // switch uses RAM (evil!) |
akashvibhute | 6:5cc7136648d1 | 1242 | // Order matters in our case below |
akashvibhute | 6:5cc7136648d1 | 1243 | if ( dr == _BV(RF_DR_LOW) ) |
akashvibhute | 6:5cc7136648d1 | 1244 | { |
akashvibhute | 6:5cc7136648d1 | 1245 | // '10' = 250KBPS |
akashvibhute | 6:5cc7136648d1 | 1246 | result = RF24_250KBPS ; |
akashvibhute | 6:5cc7136648d1 | 1247 | } |
akashvibhute | 6:5cc7136648d1 | 1248 | else if ( dr == _BV(RF_DR_HIGH) ) |
akashvibhute | 6:5cc7136648d1 | 1249 | { |
akashvibhute | 6:5cc7136648d1 | 1250 | // '01' = 2MBPS |
akashvibhute | 6:5cc7136648d1 | 1251 | result = RF24_2MBPS ; |
akashvibhute | 6:5cc7136648d1 | 1252 | } |
akashvibhute | 6:5cc7136648d1 | 1253 | else |
akashvibhute | 6:5cc7136648d1 | 1254 | { |
akashvibhute | 6:5cc7136648d1 | 1255 | // '00' = 1MBPS |
akashvibhute | 6:5cc7136648d1 | 1256 | result = RF24_1MBPS ; |
akashvibhute | 6:5cc7136648d1 | 1257 | } |
akashvibhute | 6:5cc7136648d1 | 1258 | return result ; |
akashvibhute | 0:bb74812ac6bb | 1259 | } |
akashvibhute | 0:bb74812ac6bb | 1260 | |
akashvibhute | 0:bb74812ac6bb | 1261 | /****************************************************************************/ |
akashvibhute | 0:bb74812ac6bb | 1262 | |
akashvibhute | 0:bb74812ac6bb | 1263 | void RF24::setCRCLength(rf24_crclength_e length) |
akashvibhute | 0:bb74812ac6bb | 1264 | { |
akashvibhute | 6:5cc7136648d1 | 1265 | uint8_t config = read_register(NRF_CONFIG) & ~( _BV(CRCO) | _BV(EN_CRC)) ; |
akashvibhute | 2:3bdf0d9bb71f | 1266 | |
akashvibhute | 6:5cc7136648d1 | 1267 | // switch uses RAM (evil!) |
akashvibhute | 6:5cc7136648d1 | 1268 | if ( length == RF24_CRC_DISABLED ) |
akashvibhute | 6:5cc7136648d1 | 1269 | { |
akashvibhute | 6:5cc7136648d1 | 1270 | // Do nothing, we turned it off above. |
akashvibhute | 6:5cc7136648d1 | 1271 | } |
akashvibhute | 6:5cc7136648d1 | 1272 | else if ( length == RF24_CRC_8 ) |
akashvibhute | 6:5cc7136648d1 | 1273 | { |
akashvibhute | 6:5cc7136648d1 | 1274 | config |= _BV(EN_CRC); |
akashvibhute | 6:5cc7136648d1 | 1275 | } |
akashvibhute | 6:5cc7136648d1 | 1276 | else |
akashvibhute | 6:5cc7136648d1 | 1277 | { |
akashvibhute | 6:5cc7136648d1 | 1278 | config |= _BV(EN_CRC); |
akashvibhute | 6:5cc7136648d1 | 1279 | config |= _BV( CRCO ); |
akashvibhute | 6:5cc7136648d1 | 1280 | } |
akashvibhute | 6:5cc7136648d1 | 1281 | write_register( NRF_CONFIG, config ) ; |
akashvibhute | 0:bb74812ac6bb | 1282 | } |
akashvibhute | 0:bb74812ac6bb | 1283 | |
akashvibhute | 0:bb74812ac6bb | 1284 | /****************************************************************************/ |
akashvibhute | 0:bb74812ac6bb | 1285 | |
akashvibhute | 0:bb74812ac6bb | 1286 | rf24_crclength_e RF24::getCRCLength(void) |
akashvibhute | 0:bb74812ac6bb | 1287 | { |
akashvibhute | 6:5cc7136648d1 | 1288 | rf24_crclength_e result = RF24_CRC_DISABLED; |
akashvibhute | 6:5cc7136648d1 | 1289 | |
akashvibhute | 6:5cc7136648d1 | 1290 | uint8_t config = read_register(NRF_CONFIG) & ( _BV(CRCO) | _BV(EN_CRC)) ; |
akashvibhute | 6:5cc7136648d1 | 1291 | uint8_t AA = read_register(EN_AA); |
akashvibhute | 6:5cc7136648d1 | 1292 | |
akashvibhute | 6:5cc7136648d1 | 1293 | if ( config & _BV(EN_CRC ) || AA) |
akashvibhute | 6:5cc7136648d1 | 1294 | { |
akashvibhute | 6:5cc7136648d1 | 1295 | if ( config & _BV(CRCO) ) |
akashvibhute | 6:5cc7136648d1 | 1296 | result = RF24_CRC_16; |
akashvibhute | 6:5cc7136648d1 | 1297 | else |
akashvibhute | 6:5cc7136648d1 | 1298 | result = RF24_CRC_8; |
akashvibhute | 6:5cc7136648d1 | 1299 | } |
akashvibhute | 0:bb74812ac6bb | 1300 | |
akashvibhute | 6:5cc7136648d1 | 1301 | return result; |
akashvibhute | 0:bb74812ac6bb | 1302 | } |
akashvibhute | 0:bb74812ac6bb | 1303 | |
akashvibhute | 0:bb74812ac6bb | 1304 | /****************************************************************************/ |
akashvibhute | 0:bb74812ac6bb | 1305 | |
akashvibhute | 0:bb74812ac6bb | 1306 | void RF24::disableCRC( void ) |
akashvibhute | 0:bb74812ac6bb | 1307 | { |
akashvibhute | 6:5cc7136648d1 | 1308 | uint8_t disable = read_register(NRF_CONFIG) & ~_BV(EN_CRC) ; |
akashvibhute | 6:5cc7136648d1 | 1309 | write_register( NRF_CONFIG, disable ) ; |
akashvibhute | 0:bb74812ac6bb | 1310 | } |
akashvibhute | 0:bb74812ac6bb | 1311 | |
akashvibhute | 0:bb74812ac6bb | 1312 | /****************************************************************************/ |
akashvibhute | 0:bb74812ac6bb | 1313 | void RF24::setRetries(uint8_t delay, uint8_t count) |
akashvibhute | 0:bb74812ac6bb | 1314 | { |
akashvibhute | 6:5cc7136648d1 | 1315 | write_register(SETUP_RETR,(delay&0xf)<<ARD | (count&0xf)<<ARC); |
akashvibhute | 0:bb74812ac6bb | 1316 | } |
akashvibhute | 6:5cc7136648d1 | 1317 | |
gume | 13:d295c8b3f742 | 1318 | /****************************************************************************/ |
gume | 13:d295c8b3f742 | 1319 | bool RF24::isChipConnected() |
gume | 13:d295c8b3f742 | 1320 | { |
gume | 13:d295c8b3f742 | 1321 | uint8_t setup = read_register(SETUP_AW); |
gume | 13:d295c8b3f742 | 1322 | if(setup >= 1 && setup <= 3) return true; |
gume | 13:d295c8b3f742 | 1323 | |
gume | 13:d295c8b3f742 | 1324 | return false; |
gume | 13:d295c8b3f742 | 1325 | } |