Added support for the WNC M14A2A Cellular LTE Data Module.

Dependencies:   WNC14A2AInterface

Easy Connect

Easily add all supported connectivity methods to your mbed OS project

This project is derived from https://developer.mbed.org/teams/sandbox/code/simple-mbed-client-example/file/dd6231df71bb/easy-connect.lib. It give user the ability to switch between connectivity methods and includes support for the WNC14A2A Data Module. The `NetworkInterface` API makes this easy, but you still need a mechanism for the user to select the connection method, The selection is made by modifying the `mbed_app.json` file and using `easy_connect()` from your application.

Specifying connectivity method

To add support for the WNC14A2A, add the following to your ``mbed_app.json`` file:

mbed_app.json

{
    "config": {
        "network-interface":{
            "help": "options are ETHERNET,WIFI_ESP8266,WIFI_ODIN,MESH_LOWPAN_ND,MESH_THREAD,WNC14A2A",
            "value": "WNC14A2A"
        }
    },
}

After you choose `WNC14A2A` you'll also need to indicate if you want debug output or not by Enabling (true) or Disabling (false) WNC_DEBUG.

If WNC_DEBUG is enabled, there are 3 different levels of debug output (selected via bit settings). These debug levels are set using the following values:

ValueDescription
1Basic WNC driver debug output
2Comprehensive WNC driver debug output
4Network Layer debug output

You can have any combination of these three bit values for a total value of 0 – 7.

WNC Debug Settings

    "config": {
        "WNC_DEBUG": {
            "value": false
        },
        "WNC_DEBUG_SETTING": {
            "value": 4
        },
    }

Using Easy Connect from your application

Easy Connect has just one function which will either return a `NetworkInterface`-pointer or `NULL`:

Sample Code

#include "easy-connect.h"

int main(int, char**) {
    NetworkInterface* network = easy_connect(true); /* has 1 argument, enable_logging (pass in true to log to serial port) */
    if (!network) {
        printf("Connecting to the network failed... See serial output.\r\n");
        return 1;
    }
 
    // Rest of your program
}

Tested on

  • K64F with Ethernet.
  • AT&T Cellular IoT Starter Kit with WNC M14A2A Cellular Data Module

The WNCInterface class currently supports the following version(s):

  • MPSS: M14A2A_v11.50.164451 APSS: M14A2A_v11.53.164451

License

This library is released under the Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with the License and may obtain a copy of the License at

http://www.apache.org/licenses/LICENSE-2.0

Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the specific language governing permissions and limitations under the License.

Committer:
group-Avnet
Date:
Wed Apr 19 01:08:11 2017 +0000
Revision:
0:478cfd88041f
Initial commit

Who changed what in which revision?

UserRevisionLine numberNew contents of line
group-Avnet 0:478cfd88041f 1 /*!
group-Avnet 0:478cfd88041f 2 * Copyright (c) 2015, Freescale Semiconductor, Inc.
group-Avnet 0:478cfd88041f 3 * All rights reserved.
group-Avnet 0:478cfd88041f 4 *
group-Avnet 0:478cfd88041f 5 * \file MCR20reg.h
group-Avnet 0:478cfd88041f 6 * MCR20 Registers
group-Avnet 0:478cfd88041f 7 *
group-Avnet 0:478cfd88041f 8 * Redistribution and use in source and binary forms, with or without modification,
group-Avnet 0:478cfd88041f 9 * are permitted provided that the following conditions are met:
group-Avnet 0:478cfd88041f 10 *
group-Avnet 0:478cfd88041f 11 * o Redistributions of source code must retain the above copyright notice, this list
group-Avnet 0:478cfd88041f 12 * of conditions and the following disclaimer.
group-Avnet 0:478cfd88041f 13 *
group-Avnet 0:478cfd88041f 14 * o Redistributions in binary form must reproduce the above copyright notice, this
group-Avnet 0:478cfd88041f 15 * list of conditions and the following disclaimer in the documentation and/or
group-Avnet 0:478cfd88041f 16 * other materials provided with the distribution.
group-Avnet 0:478cfd88041f 17 *
group-Avnet 0:478cfd88041f 18 * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
group-Avnet 0:478cfd88041f 19 * contributors may be used to endorse or promote products derived from this
group-Avnet 0:478cfd88041f 20 * software without specific prior written permission.
group-Avnet 0:478cfd88041f 21 *
group-Avnet 0:478cfd88041f 22 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
group-Avnet 0:478cfd88041f 23 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
group-Avnet 0:478cfd88041f 24 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
group-Avnet 0:478cfd88041f 25 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
group-Avnet 0:478cfd88041f 26 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
group-Avnet 0:478cfd88041f 27 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
group-Avnet 0:478cfd88041f 28 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
group-Avnet 0:478cfd88041f 29 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
group-Avnet 0:478cfd88041f 30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
group-Avnet 0:478cfd88041f 31 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
group-Avnet 0:478cfd88041f 32 */
group-Avnet 0:478cfd88041f 33
group-Avnet 0:478cfd88041f 34 #ifndef __MCR20_REG_H__
group-Avnet 0:478cfd88041f 35 #define __MCR20_REG_H__
group-Avnet 0:478cfd88041f 36 /*****************************************************************************
group-Avnet 0:478cfd88041f 37 * INCLUDED HEADERS *
group-Avnet 0:478cfd88041f 38 *---------------------------------------------------------------------------*
group-Avnet 0:478cfd88041f 39 * Add to this section all the headers that this module needs to include. *
group-Avnet 0:478cfd88041f 40 * Note that it is not a good practice to include header files into header *
group-Avnet 0:478cfd88041f 41 * files, so use this section only if there is no other better solution. *
group-Avnet 0:478cfd88041f 42 *---------------------------------------------------------------------------*
group-Avnet 0:478cfd88041f 43 *****************************************************************************/
group-Avnet 0:478cfd88041f 44
group-Avnet 0:478cfd88041f 45 /****************************************************************************/
group-Avnet 0:478cfd88041f 46 /* Transceiver SPI Registers */
group-Avnet 0:478cfd88041f 47 /****************************************************************************/
group-Avnet 0:478cfd88041f 48
group-Avnet 0:478cfd88041f 49 #define TransceiverSPI_IARIndexReg (0x3E)
group-Avnet 0:478cfd88041f 50
group-Avnet 0:478cfd88041f 51 #define TransceiverSPI_ReadSelect (1<<7)
group-Avnet 0:478cfd88041f 52 #define TransceiverSPI_WriteSelect (0<<7)
group-Avnet 0:478cfd88041f 53 #define TransceiverSPI_RegisterAccessSelect (0<<6)
group-Avnet 0:478cfd88041f 54 #define TransceiverSPI_PacketBuffAccessSelect (1<<6)
group-Avnet 0:478cfd88041f 55 #define TransceiverSPI_PacketBuffBurstModeSelect (0<<5)
group-Avnet 0:478cfd88041f 56 #define TransceiverSPI_PacketBuffByteModeSelect (1<<5)
group-Avnet 0:478cfd88041f 57
group-Avnet 0:478cfd88041f 58 #define TransceiverSPI_DirectRegisterAddressMask (0x3F)
group-Avnet 0:478cfd88041f 59
group-Avnet 0:478cfd88041f 60 #define IRQSTS1 0x00
group-Avnet 0:478cfd88041f 61 #define IRQSTS2 0x01
group-Avnet 0:478cfd88041f 62 #define IRQSTS3 0x02
group-Avnet 0:478cfd88041f 63 #define PHY_CTRL1 0x03
group-Avnet 0:478cfd88041f 64 #define PHY_CTRL2 0x04
group-Avnet 0:478cfd88041f 65 #define PHY_CTRL3 0x05
group-Avnet 0:478cfd88041f 66 #define RX_FRM_LEN 0x06
group-Avnet 0:478cfd88041f 67 #define PHY_CTRL4 0x07
group-Avnet 0:478cfd88041f 68 #define SRC_CTRL 0x08
group-Avnet 0:478cfd88041f 69 #define SRC_ADDRS_SUM_LSB 0x09
group-Avnet 0:478cfd88041f 70 #define SRC_ADDRS_SUM_MSB 0x0A
group-Avnet 0:478cfd88041f 71 #define CCA1_ED_FNL 0x0B
group-Avnet 0:478cfd88041f 72 #define EVENT_TMR_LSB 0x0C
group-Avnet 0:478cfd88041f 73 #define EVENT_TMR_MSB 0x0D
group-Avnet 0:478cfd88041f 74 #define EVENT_TMR_USB 0x0E
group-Avnet 0:478cfd88041f 75 #define TIMESTAMP_LSB 0x0F
group-Avnet 0:478cfd88041f 76 #define TIMESTAMP_MSB 0x10
group-Avnet 0:478cfd88041f 77 #define TIMESTAMP_USB 0x11
group-Avnet 0:478cfd88041f 78 #define T3CMP_LSB 0x12
group-Avnet 0:478cfd88041f 79 #define T3CMP_MSB 0x13
group-Avnet 0:478cfd88041f 80 #define T3CMP_USB 0x14
group-Avnet 0:478cfd88041f 81 #define T2PRIMECMP_LSB 0x15
group-Avnet 0:478cfd88041f 82 #define T2PRIMECMP_MSB 0x16
group-Avnet 0:478cfd88041f 83 #define T1CMP_LSB 0x17
group-Avnet 0:478cfd88041f 84 #define T1CMP_MSB 0x18
group-Avnet 0:478cfd88041f 85 #define T1CMP_USB 0x19
group-Avnet 0:478cfd88041f 86 #define T2CMP_LSB 0x1A
group-Avnet 0:478cfd88041f 87 #define T2CMP_MSB 0x1B
group-Avnet 0:478cfd88041f 88 #define T2CMP_USB 0x1C
group-Avnet 0:478cfd88041f 89 #define T4CMP_LSB 0x1D
group-Avnet 0:478cfd88041f 90 #define T4CMP_MSB 0x1E
group-Avnet 0:478cfd88041f 91 #define T4CMP_USB 0x1F
group-Avnet 0:478cfd88041f 92 #define PLL_INT0 0x20
group-Avnet 0:478cfd88041f 93 #define PLL_FRAC0_LSB 0x21
group-Avnet 0:478cfd88041f 94 #define PLL_FRAC0_MSB 0x22
group-Avnet 0:478cfd88041f 95 #define PA_PWR 0x23
group-Avnet 0:478cfd88041f 96 #define SEQ_STATE 0x24
group-Avnet 0:478cfd88041f 97 #define LQI_VALUE 0x25
group-Avnet 0:478cfd88041f 98 #define RSSI_CCA_CONT 0x26
group-Avnet 0:478cfd88041f 99 //-------------- 0x27
group-Avnet 0:478cfd88041f 100 #define ASM_CTRL1 0x28
group-Avnet 0:478cfd88041f 101 #define ASM_CTRL2 0x29
group-Avnet 0:478cfd88041f 102 #define ASM_DATA_0 0x2A
group-Avnet 0:478cfd88041f 103 #define ASM_DATA_1 0x2B
group-Avnet 0:478cfd88041f 104 #define ASM_DATA_2 0x2C
group-Avnet 0:478cfd88041f 105 #define ASM_DATA_3 0x2D
group-Avnet 0:478cfd88041f 106 #define ASM_DATA_4 0x2E
group-Avnet 0:478cfd88041f 107 #define ASM_DATA_5 0x2F
group-Avnet 0:478cfd88041f 108 #define ASM_DATA_6 0x30
group-Avnet 0:478cfd88041f 109 #define ASM_DATA_7 0x31
group-Avnet 0:478cfd88041f 110 #define ASM_DATA_8 0x32
group-Avnet 0:478cfd88041f 111 #define ASM_DATA_9 0x33
group-Avnet 0:478cfd88041f 112 #define ASM_DATA_A 0x34
group-Avnet 0:478cfd88041f 113 #define ASM_DATA_B 0x35
group-Avnet 0:478cfd88041f 114 #define ASM_DATA_C 0x36
group-Avnet 0:478cfd88041f 115 #define ASM_DATA_D 0x37
group-Avnet 0:478cfd88041f 116 #define ASM_DATA_E 0x38
group-Avnet 0:478cfd88041f 117 #define ASM_DATA_F 0x39
group-Avnet 0:478cfd88041f 118 //------------------- 0x3A
group-Avnet 0:478cfd88041f 119 #define OVERWRITE_VER 0x3B
group-Avnet 0:478cfd88041f 120 #define CLK_OUT_CTRL 0x3C
group-Avnet 0:478cfd88041f 121 #define PWR_MODES 0x3D
group-Avnet 0:478cfd88041f 122 #define IAR_INDEX 0x3E
group-Avnet 0:478cfd88041f 123 #define IAR_DATA 0x3F
group-Avnet 0:478cfd88041f 124
group-Avnet 0:478cfd88041f 125
group-Avnet 0:478cfd88041f 126 #define PART_ID 0x00
group-Avnet 0:478cfd88041f 127 #define XTAL_TRIM 0x01
group-Avnet 0:478cfd88041f 128 #define PMC_LP_TRIM 0x02
group-Avnet 0:478cfd88041f 129 #define MACPANID0_LSB 0x03
group-Avnet 0:478cfd88041f 130 #define MACPANID0_MSB 0x04
group-Avnet 0:478cfd88041f 131 #define MACSHORTADDRS0_LSB 0x05
group-Avnet 0:478cfd88041f 132 #define MACSHORTADDRS0_MSB 0x06
group-Avnet 0:478cfd88041f 133 #define MACLONGADDRS0_0 0x07
group-Avnet 0:478cfd88041f 134 #define MACLONGADDRS0_8 0x08
group-Avnet 0:478cfd88041f 135 #define MACLONGADDRS0_16 0x09
group-Avnet 0:478cfd88041f 136 #define MACLONGADDRS0_24 0x0A
group-Avnet 0:478cfd88041f 137 #define MACLONGADDRS0_32 0x0B
group-Avnet 0:478cfd88041f 138 #define MACLONGADDRS0_40 0x0C
group-Avnet 0:478cfd88041f 139 #define MACLONGADDRS0_48 0x0D
group-Avnet 0:478cfd88041f 140 #define MACLONGADDRS0_56 0x0E
group-Avnet 0:478cfd88041f 141 #define RX_FRAME_FILTER 0x0F
group-Avnet 0:478cfd88041f 142 #define PLL_INT1 0x10
group-Avnet 0:478cfd88041f 143 #define PLL_FRAC1_LSB 0x11
group-Avnet 0:478cfd88041f 144 #define PLL_FRAC1_MSB 0x12
group-Avnet 0:478cfd88041f 145 #define MACPANID1_LSB 0x13
group-Avnet 0:478cfd88041f 146 #define MACPANID1_MSB 0x14
group-Avnet 0:478cfd88041f 147 #define MACSHORTADDRS1_LSB 0x15
group-Avnet 0:478cfd88041f 148 #define MACSHORTADDRS1_MSB 0x16
group-Avnet 0:478cfd88041f 149 #define MACLONGADDRS1_0 0x17
group-Avnet 0:478cfd88041f 150 #define MACLONGADDRS1_8 0x18
group-Avnet 0:478cfd88041f 151 #define MACLONGADDRS1_16 0x19
group-Avnet 0:478cfd88041f 152 #define MACLONGADDRS1_24 0x1A
group-Avnet 0:478cfd88041f 153 #define MACLONGADDRS1_32 0x1B
group-Avnet 0:478cfd88041f 154 #define MACLONGADDRS1_40 0x1C
group-Avnet 0:478cfd88041f 155 #define MACLONGADDRS1_48 0x1D
group-Avnet 0:478cfd88041f 156 #define MACLONGADDRS1_56 0x1E
group-Avnet 0:478cfd88041f 157 #define DUAL_PAN_CTRL 0x1F
group-Avnet 0:478cfd88041f 158 #define DUAL_PAN_DWELL 0x20
group-Avnet 0:478cfd88041f 159 #define DUAL_PAN_STS 0x21
group-Avnet 0:478cfd88041f 160 #define CCA1_THRESH 0x22
group-Avnet 0:478cfd88041f 161 #define CCA1_ED_OFFSET_COMP 0x23
group-Avnet 0:478cfd88041f 162 #define LQI_OFFSET_COMP 0x24
group-Avnet 0:478cfd88041f 163 #define CCA_CTRL 0x25
group-Avnet 0:478cfd88041f 164 #define CCA2_CORR_PEAKS 0x26
group-Avnet 0:478cfd88041f 165 #define CCA2_CORR_THRESH 0x27
group-Avnet 0:478cfd88041f 166 #define TMR_PRESCALE 0x28
group-Avnet 0:478cfd88041f 167 //---------------- 0x29
group-Avnet 0:478cfd88041f 168 #define GPIO_DATA 0x2A
group-Avnet 0:478cfd88041f 169 #define GPIO_DIR 0x2B
group-Avnet 0:478cfd88041f 170 #define GPIO_PUL_EN 0x2C
group-Avnet 0:478cfd88041f 171 #define GPIO_PUL_SEL 0x2D
group-Avnet 0:478cfd88041f 172 #define GPIO_DS 0x2E
group-Avnet 0:478cfd88041f 173 //-------------- 0x2F
group-Avnet 0:478cfd88041f 174 #define ANT_PAD_CTRL 0x30
group-Avnet 0:478cfd88041f 175 #define MISC_PAD_CTRL 0x31
group-Avnet 0:478cfd88041f 176 #define BSM_CTRL 0x32
group-Avnet 0:478cfd88041f 177 //--------------- 0x33
group-Avnet 0:478cfd88041f 178 #define _RNG 0x34
group-Avnet 0:478cfd88041f 179 #define RX_BYTE_COUNT 0x35
group-Avnet 0:478cfd88041f 180 #define RX_WTR_MARK 0x36
group-Avnet 0:478cfd88041f 181 #define SOFT_RESET 0x37
group-Avnet 0:478cfd88041f 182 #define TXDELAY 0x38
group-Avnet 0:478cfd88041f 183 #define ACKDELAY 0x39
group-Avnet 0:478cfd88041f 184 #define SEQ_MGR_CTRL 0x3A
group-Avnet 0:478cfd88041f 185 #define SEQ_MGR_STS 0x3B
group-Avnet 0:478cfd88041f 186 #define SEQ_T_STS 0x3C
group-Avnet 0:478cfd88041f 187 #define ABORT_STS 0x3D
group-Avnet 0:478cfd88041f 188 #define CCCA_BUSY_CNT 0x3E
group-Avnet 0:478cfd88041f 189 #define SRC_ADDR_CHECKSUM1 0x3F
group-Avnet 0:478cfd88041f 190 #define SRC_ADDR_CHECKSUM2 0x40
group-Avnet 0:478cfd88041f 191 #define SRC_TBL_VALID1 0x41
group-Avnet 0:478cfd88041f 192 #define SRC_TBL_VALID2 0x42
group-Avnet 0:478cfd88041f 193 #define FILTERFAIL_CODE1 0x43
group-Avnet 0:478cfd88041f 194 #define FILTERFAIL_CODE2 0x44
group-Avnet 0:478cfd88041f 195 #define SLOT_PRELOAD 0x45
group-Avnet 0:478cfd88041f 196 //---------------- 0x46
group-Avnet 0:478cfd88041f 197 #define CORR_VT 0x47
group-Avnet 0:478cfd88041f 198 #define SYNC_CTRL 0x48
group-Avnet 0:478cfd88041f 199 #define PN_LSB_0 0x49
group-Avnet 0:478cfd88041f 200 #define PN_LSB_1 0x4A
group-Avnet 0:478cfd88041f 201 #define PN_MSB_0 0x4B
group-Avnet 0:478cfd88041f 202 #define PN_MSB_1 0x4C
group-Avnet 0:478cfd88041f 203 #define CORR_NVAL 0x4D
group-Avnet 0:478cfd88041f 204 #define TX_MODE_CTRL 0x4E
group-Avnet 0:478cfd88041f 205 #define SNF_THR 0x4F
group-Avnet 0:478cfd88041f 206 #define FAD_THR 0x50
group-Avnet 0:478cfd88041f 207 #define ANT_AGC_CTRL 0x51
group-Avnet 0:478cfd88041f 208 #define AGC_THR1 0x52
group-Avnet 0:478cfd88041f 209 #define AGC_THR2 0x53
group-Avnet 0:478cfd88041f 210 #define AGC_HYS 0x54
group-Avnet 0:478cfd88041f 211 #define AFC 0x55
group-Avnet 0:478cfd88041f 212 //--------------- 0x56
group-Avnet 0:478cfd88041f 213 //--------------- 0x57
group-Avnet 0:478cfd88041f 214 #define PHY_STS 0x58
group-Avnet 0:478cfd88041f 215 #define RX_MAX_CORR 0x59
group-Avnet 0:478cfd88041f 216 #define RX_MAX_PREAMBLE 0x5A
group-Avnet 0:478cfd88041f 217 #define RSSI 0x5B
group-Avnet 0:478cfd88041f 218 //--------------- 0x5C
group-Avnet 0:478cfd88041f 219 //--------------- 0x5D
group-Avnet 0:478cfd88041f 220 #define PLL_DIG_CTRL 0x5E
group-Avnet 0:478cfd88041f 221 #define VCO_CAL 0x5F
group-Avnet 0:478cfd88041f 222 #define VCO_BEST_DIFF 0x60
group-Avnet 0:478cfd88041f 223 #define VCO_BIAS 0x61
group-Avnet 0:478cfd88041f 224 #define KMOD_CTRL 0x62
group-Avnet 0:478cfd88041f 225 #define KMOD_CAL 0x63
group-Avnet 0:478cfd88041f 226 #define PA_CAL 0x64
group-Avnet 0:478cfd88041f 227 #define PA_PWRCAL 0x65
group-Avnet 0:478cfd88041f 228 #define ATT_RSSI1 0x66
group-Avnet 0:478cfd88041f 229 #define ATT_RSSI2 0x67
group-Avnet 0:478cfd88041f 230 #define RSSI_OFFSET 0x68
group-Avnet 0:478cfd88041f 231 #define RSSI_SLOPE 0x69
group-Avnet 0:478cfd88041f 232 #define RSSI_CAL1 0x6A
group-Avnet 0:478cfd88041f 233 #define RSSI_CAL2 0x6B
group-Avnet 0:478cfd88041f 234 //--------------- 0x6C
group-Avnet 0:478cfd88041f 235 //--------------- 0x6D
group-Avnet 0:478cfd88041f 236 #define XTAL_CTRL 0x6E
group-Avnet 0:478cfd88041f 237 #define XTAL_COMP_MIN 0x6F
group-Avnet 0:478cfd88041f 238 #define XTAL_COMP_MAX 0x70
group-Avnet 0:478cfd88041f 239 #define XTAL_GM 0x71
group-Avnet 0:478cfd88041f 240 //--------------- 0x72
group-Avnet 0:478cfd88041f 241 //--------------- 0x73
group-Avnet 0:478cfd88041f 242 #define LNA_TUNE 0x74
group-Avnet 0:478cfd88041f 243 #define LNA_AGCGAIN 0x75
group-Avnet 0:478cfd88041f 244 //--------------- 0x76
group-Avnet 0:478cfd88041f 245 //--------------- 0x77
group-Avnet 0:478cfd88041f 246 #define CHF_PMA_GAIN 0x78
group-Avnet 0:478cfd88041f 247 #define CHF_IBUF 0x79
group-Avnet 0:478cfd88041f 248 #define CHF_QBUF 0x7A
group-Avnet 0:478cfd88041f 249 #define CHF_IRIN 0x7B
group-Avnet 0:478cfd88041f 250 #define CHF_QRIN 0x7C
group-Avnet 0:478cfd88041f 251 #define CHF_IL 0x7D
group-Avnet 0:478cfd88041f 252 #define CHF_QL 0x7E
group-Avnet 0:478cfd88041f 253 #define CHF_CC1 0x7F
group-Avnet 0:478cfd88041f 254 #define CHF_CCL 0x80
group-Avnet 0:478cfd88041f 255 #define CHF_CC2 0x81
group-Avnet 0:478cfd88041f 256 #define CHF_IROUT 0x82
group-Avnet 0:478cfd88041f 257 #define CHF_QROUT 0x83
group-Avnet 0:478cfd88041f 258 //--------------- 0x84
group-Avnet 0:478cfd88041f 259 //--------------- 0x85
group-Avnet 0:478cfd88041f 260 #define RSSI_CTRL 0x86
group-Avnet 0:478cfd88041f 261 //--------------- 0x87
group-Avnet 0:478cfd88041f 262 //--------------- 0x88
group-Avnet 0:478cfd88041f 263 #define PA_BIAS 0x89
group-Avnet 0:478cfd88041f 264 #define PA_TUNING 0x8A
group-Avnet 0:478cfd88041f 265 //--------------- 0x8B
group-Avnet 0:478cfd88041f 266 //--------------- 0x8C
group-Avnet 0:478cfd88041f 267 #define PMC_HP_TRIM 0x8D
group-Avnet 0:478cfd88041f 268 #define VREGA_TRIM 0x8E
group-Avnet 0:478cfd88041f 269 //--------------- 0x8F
group-Avnet 0:478cfd88041f 270 //--------------- 0x90
group-Avnet 0:478cfd88041f 271 #define VCO_CTRL1 0x91
group-Avnet 0:478cfd88041f 272 #define VCO_CTRL2 0x92
group-Avnet 0:478cfd88041f 273 //--------------- 0x93
group-Avnet 0:478cfd88041f 274 //--------------- 0x94
group-Avnet 0:478cfd88041f 275 #define ANA_SPARE_OUT1 0x95
group-Avnet 0:478cfd88041f 276 #define ANA_SPARE_OUT2 0x96
group-Avnet 0:478cfd88041f 277 #define ANA_SPARE_IN 0x97
group-Avnet 0:478cfd88041f 278 #define MISCELLANEOUS 0x98
group-Avnet 0:478cfd88041f 279 //--------------- 0x99
group-Avnet 0:478cfd88041f 280 #define SEQ_MGR_OVRD0 0x9A
group-Avnet 0:478cfd88041f 281 #define SEQ_MGR_OVRD1 0x9B
group-Avnet 0:478cfd88041f 282 #define SEQ_MGR_OVRD2 0x9C
group-Avnet 0:478cfd88041f 283 #define SEQ_MGR_OVRD3 0x9D
group-Avnet 0:478cfd88041f 284 #define SEQ_MGR_OVRD4 0x9E
group-Avnet 0:478cfd88041f 285 #define SEQ_MGR_OVRD5 0x9F
group-Avnet 0:478cfd88041f 286 #define SEQ_MGR_OVRD6 0xA0
group-Avnet 0:478cfd88041f 287 #define SEQ_MGR_OVRD7 0xA1
group-Avnet 0:478cfd88041f 288 //--------------- 0xA2
group-Avnet 0:478cfd88041f 289 #define TESTMODE_CTRL 0xA3
group-Avnet 0:478cfd88041f 290 #define DTM_CTRL1 0xA4
group-Avnet 0:478cfd88041f 291 #define DTM_CTRL2 0xA5
group-Avnet 0:478cfd88041f 292 #define ATM_CTRL1 0xA6
group-Avnet 0:478cfd88041f 293 #define ATM_CTRL2 0xA7
group-Avnet 0:478cfd88041f 294 #define ATM_CTRL3 0xA8
group-Avnet 0:478cfd88041f 295 //--------------- 0xA9
group-Avnet 0:478cfd88041f 296 #define LIM_FE_TEST_CTRL 0xAA
group-Avnet 0:478cfd88041f 297 #define CHF_TEST_CTRL 0xAB
group-Avnet 0:478cfd88041f 298 #define VCO_TEST_CTRL 0xAC
group-Avnet 0:478cfd88041f 299 #define PLL_TEST_CTRL 0xAD
group-Avnet 0:478cfd88041f 300 #define PA_TEST_CTRL 0xAE
group-Avnet 0:478cfd88041f 301 #define PMC_TEST_CTRL 0xAF
group-Avnet 0:478cfd88041f 302 #define SCAN_DTM_PROTECT_1 0xFE
group-Avnet 0:478cfd88041f 303 #define SCAN_DTM_PROTECT_0 0xFF
group-Avnet 0:478cfd88041f 304
group-Avnet 0:478cfd88041f 305 // IRQSTS1 bits
group-Avnet 0:478cfd88041f 306 #define cIRQSTS1_RX_FRM_PEND (1<<7)
group-Avnet 0:478cfd88041f 307 #define cIRQSTS1_PLL_UNLOCK_IRQ (1<<6)
group-Avnet 0:478cfd88041f 308 #define cIRQSTS1_FILTERFAIL_IRQ (1<<5)
group-Avnet 0:478cfd88041f 309 #define cIRQSTS1_RXWTRMRKIRQ (1<<4)
group-Avnet 0:478cfd88041f 310 #define cIRQSTS1_CCAIRQ (1<<3)
group-Avnet 0:478cfd88041f 311 #define cIRQSTS1_RXIRQ (1<<2)
group-Avnet 0:478cfd88041f 312 #define cIRQSTS1_TXIRQ (1<<1)
group-Avnet 0:478cfd88041f 313 #define cIRQSTS1_SEQIRQ (1<<0)
group-Avnet 0:478cfd88041f 314
group-Avnet 0:478cfd88041f 315 typedef union regIRQSTS1_tag{
group-Avnet 0:478cfd88041f 316 uint8_t byte;
group-Avnet 0:478cfd88041f 317 struct{
group-Avnet 0:478cfd88041f 318 uint8_t SEQIRQ:1;
group-Avnet 0:478cfd88041f 319 uint8_t TXIRQ:1;
group-Avnet 0:478cfd88041f 320 uint8_t RXIRQ:1;
group-Avnet 0:478cfd88041f 321 uint8_t CCAIRQ:1;
group-Avnet 0:478cfd88041f 322 uint8_t RXWTRMRKIRQ:1;
group-Avnet 0:478cfd88041f 323 uint8_t FILTERFAIL_IRQ:1;
group-Avnet 0:478cfd88041f 324 uint8_t PLL_UNLOCK_IRQ:1;
group-Avnet 0:478cfd88041f 325 uint8_t RX_FRM_PEND:1;
group-Avnet 0:478cfd88041f 326 }bit;
group-Avnet 0:478cfd88041f 327 } regIRQSTS1_t;
group-Avnet 0:478cfd88041f 328
group-Avnet 0:478cfd88041f 329 // IRQSTS2 bits
group-Avnet 0:478cfd88041f 330 #define cIRQSTS2_CRCVALID (1<<7)
group-Avnet 0:478cfd88041f 331 #define cIRQSTS2_CCA (1<<6)
group-Avnet 0:478cfd88041f 332 #define cIRQSTS2_SRCADDR (1<<5)
group-Avnet 0:478cfd88041f 333 #define cIRQSTS2_PI (1<<4)
group-Avnet 0:478cfd88041f 334 #define cIRQSTS2_TMRSTATUS (1<<3)
group-Avnet 0:478cfd88041f 335 #define cIRQSTS2_ASM_IRQ (1<<2)
group-Avnet 0:478cfd88041f 336 #define cIRQSTS2_PB_ERR_IRQ (1<<1)
group-Avnet 0:478cfd88041f 337 #define cIRQSTS2_WAKE_IRQ (1<<0)
group-Avnet 0:478cfd88041f 338
group-Avnet 0:478cfd88041f 339 typedef union regIRQSTS2_tag{
group-Avnet 0:478cfd88041f 340 uint8_t byte;
group-Avnet 0:478cfd88041f 341 struct{
group-Avnet 0:478cfd88041f 342 uint8_t WAKE_IRQ:1;
group-Avnet 0:478cfd88041f 343 uint8_t PB_ERR_IRQ:1;
group-Avnet 0:478cfd88041f 344 uint8_t ASM_IRQ:1;
group-Avnet 0:478cfd88041f 345 uint8_t TMRSTATUS:1;
group-Avnet 0:478cfd88041f 346 uint8_t PI:1;
group-Avnet 0:478cfd88041f 347 uint8_t SRCADDR:1;
group-Avnet 0:478cfd88041f 348 uint8_t CCA:1;
group-Avnet 0:478cfd88041f 349 uint8_t CRCVALID:1;
group-Avnet 0:478cfd88041f 350 }bit;
group-Avnet 0:478cfd88041f 351 } regIRQSTS2_t;
group-Avnet 0:478cfd88041f 352
group-Avnet 0:478cfd88041f 353 // IRQSTS3 bits
group-Avnet 0:478cfd88041f 354 #define cIRQSTS3_TMR4MSK (1<<7)
group-Avnet 0:478cfd88041f 355 #define cIRQSTS3_TMR3MSK (1<<6)
group-Avnet 0:478cfd88041f 356 #define cIRQSTS3_TMR2MSK (1<<5)
group-Avnet 0:478cfd88041f 357 #define cIRQSTS3_TMR1MSK (1<<4)
group-Avnet 0:478cfd88041f 358 #define cIRQSTS3_TMR4IRQ (1<<3)
group-Avnet 0:478cfd88041f 359 #define cIRQSTS3_TMR3IRQ (1<<2)
group-Avnet 0:478cfd88041f 360 #define cIRQSTS3_TMR2IRQ (1<<1)
group-Avnet 0:478cfd88041f 361 #define cIRQSTS3_TMR1IRQ (1<<0)
group-Avnet 0:478cfd88041f 362
group-Avnet 0:478cfd88041f 363 typedef union regIRQSTS3_tag{
group-Avnet 0:478cfd88041f 364 uint8_t byte;
group-Avnet 0:478cfd88041f 365 struct{
group-Avnet 0:478cfd88041f 366 uint8_t TMR1IRQ:1;
group-Avnet 0:478cfd88041f 367 uint8_t TMR2IRQ:1;
group-Avnet 0:478cfd88041f 368 uint8_t TMR3IRQ:1;
group-Avnet 0:478cfd88041f 369 uint8_t TMR4IRQ:1;
group-Avnet 0:478cfd88041f 370 uint8_t TMR1MSK:1;
group-Avnet 0:478cfd88041f 371 uint8_t TMR2MSK:1;
group-Avnet 0:478cfd88041f 372 uint8_t TMR3MSK:1;
group-Avnet 0:478cfd88041f 373 uint8_t TMR4MSK:1;
group-Avnet 0:478cfd88041f 374 }bit;
group-Avnet 0:478cfd88041f 375 } regIRQSTS3_t;
group-Avnet 0:478cfd88041f 376
group-Avnet 0:478cfd88041f 377 // PHY_CTRL1 bits
group-Avnet 0:478cfd88041f 378 #define cPHY_CTRL1_TMRTRIGEN (1<<7)
group-Avnet 0:478cfd88041f 379 #define cPHY_CTRL1_SLOTTED (1<<6)
group-Avnet 0:478cfd88041f 380 #define cPHY_CTRL1_CCABFRTX (1<<5)
group-Avnet 0:478cfd88041f 381 #define cPHY_CTRL1_RXACKRQD (1<<4)
group-Avnet 0:478cfd88041f 382 #define cPHY_CTRL1_AUTOACK (1<<3)
group-Avnet 0:478cfd88041f 383 #define cPHY_CTRL1_XCVSEQ (7<<0)
group-Avnet 0:478cfd88041f 384
group-Avnet 0:478cfd88041f 385 typedef union regPHY_CTRL1_tag{
group-Avnet 0:478cfd88041f 386 uint8_t byte;
group-Avnet 0:478cfd88041f 387 struct{
group-Avnet 0:478cfd88041f 388 uint8_t XCVSEQ:3;
group-Avnet 0:478cfd88041f 389 uint8_t AUTOACK:1;
group-Avnet 0:478cfd88041f 390 uint8_t RXACKRQD:1;
group-Avnet 0:478cfd88041f 391 uint8_t CCABFRTX:1;
group-Avnet 0:478cfd88041f 392 uint8_t SLOTTED:1;
group-Avnet 0:478cfd88041f 393 uint8_t TMRTRIGEN:1;
group-Avnet 0:478cfd88041f 394 }bit;
group-Avnet 0:478cfd88041f 395 } regPHY_CTRL1_t;
group-Avnet 0:478cfd88041f 396
group-Avnet 0:478cfd88041f 397 // PHY_CTRL2 bits
group-Avnet 0:478cfd88041f 398 #define cPHY_CTRL2_CRC_MSK (1<<7)
group-Avnet 0:478cfd88041f 399 #define cPHY_CTRL2_PLL_UNLOCK_MSK (1<<6)
group-Avnet 0:478cfd88041f 400 #define cPHY_CTRL2_FILTERFAIL_MSK (1<<5)
group-Avnet 0:478cfd88041f 401 #define cPHY_CTRL2_RX_WMRK_MSK (1<<4)
group-Avnet 0:478cfd88041f 402 #define cPHY_CTRL2_CCAMSK (1<<3)
group-Avnet 0:478cfd88041f 403 #define cPHY_CTRL2_RXMSK (1<<2)
group-Avnet 0:478cfd88041f 404 #define cPHY_CTRL2_TXMSK (1<<1)
group-Avnet 0:478cfd88041f 405 #define cPHY_CTRL2_SEQMSK (1<<0)
group-Avnet 0:478cfd88041f 406
group-Avnet 0:478cfd88041f 407 typedef union regPHY_CTRL2_tag{
group-Avnet 0:478cfd88041f 408 uint8_t byte;
group-Avnet 0:478cfd88041f 409 struct{
group-Avnet 0:478cfd88041f 410 uint8_t SEQMSK:1;
group-Avnet 0:478cfd88041f 411 uint8_t TXMSK:1;
group-Avnet 0:478cfd88041f 412 uint8_t RXMSK:1;
group-Avnet 0:478cfd88041f 413 uint8_t CCAMSK:1;
group-Avnet 0:478cfd88041f 414 uint8_t RX_WMRK_MSK:1;
group-Avnet 0:478cfd88041f 415 uint8_t FILTERFAIL_MSK:1;
group-Avnet 0:478cfd88041f 416 uint8_t PLL_UNLOCK_MSK:1;
group-Avnet 0:478cfd88041f 417 uint8_t CRC_MSK:1;
group-Avnet 0:478cfd88041f 418 }bit;
group-Avnet 0:478cfd88041f 419 } regPHY_CTRL2_t;
group-Avnet 0:478cfd88041f 420
group-Avnet 0:478cfd88041f 421 // PHY_CTRL3 bits
group-Avnet 0:478cfd88041f 422 #define cPHY_CTRL3_TMR4CMP_EN (1<<7)
group-Avnet 0:478cfd88041f 423 #define cPHY_CTRL3_TMR3CMP_EN (1<<6)
group-Avnet 0:478cfd88041f 424 #define cPHY_CTRL3_TMR2CMP_EN (1<<5)
group-Avnet 0:478cfd88041f 425 #define cPHY_CTRL3_TMR1CMP_EN (1<<4)
group-Avnet 0:478cfd88041f 426 #define cPHY_CTRL3_ASM_MSK (1<<2)
group-Avnet 0:478cfd88041f 427 #define cPHY_CTRL3_PB_ERR_MSK (1<<1)
group-Avnet 0:478cfd88041f 428 #define cPHY_CTRL3_WAKE_MSK (1<<0)
group-Avnet 0:478cfd88041f 429
group-Avnet 0:478cfd88041f 430 typedef union regPHY_CTRL3_tag{
group-Avnet 0:478cfd88041f 431 uint8_t byte;
group-Avnet 0:478cfd88041f 432 struct{
group-Avnet 0:478cfd88041f 433 uint8_t WAKE_MSK:1;
group-Avnet 0:478cfd88041f 434 uint8_t PB_ERR_MSK:1;
group-Avnet 0:478cfd88041f 435 uint8_t ASM_MSK:1;
group-Avnet 0:478cfd88041f 436 uint8_t RESERVED:1;
group-Avnet 0:478cfd88041f 437 uint8_t TMR1CMP_EN:1;
group-Avnet 0:478cfd88041f 438 uint8_t TMR2CMP_EN:1;
group-Avnet 0:478cfd88041f 439 uint8_t TMR3CMP_EN:1;
group-Avnet 0:478cfd88041f 440 uint8_t TMR4CMP_EN:1;
group-Avnet 0:478cfd88041f 441 }bit;
group-Avnet 0:478cfd88041f 442 } regPHY_CTRL3_t;
group-Avnet 0:478cfd88041f 443
group-Avnet 0:478cfd88041f 444 // RX_FRM_LEN bits
group-Avnet 0:478cfd88041f 445 #define cRX_FRAME_LENGTH (0x7F)
group-Avnet 0:478cfd88041f 446
group-Avnet 0:478cfd88041f 447 // PHY_CTRL4 bits
group-Avnet 0:478cfd88041f 448 #define cPHY_CTRL4_TRCV_MSK (1<<7)
group-Avnet 0:478cfd88041f 449 #define cPHY_CTRL4_TC3TMOUT (1<<6)
group-Avnet 0:478cfd88041f 450 #define cPHY_CTRL4_PANCORDNTR0 (1<<5)
group-Avnet 0:478cfd88041f 451 #define cPHY_CTRL4_CCATYPE (3<<0)
group-Avnet 0:478cfd88041f 452 #define cPHY_CTRL4_CCATYPE_Shift_c (3)
group-Avnet 0:478cfd88041f 453 #define cPHY_CTRL4_TMRLOAD (1<<2)
group-Avnet 0:478cfd88041f 454 #define cPHY_CTRL4_PROMISCUOUS (1<<1)
group-Avnet 0:478cfd88041f 455 #define cPHY_CTRL4_TC2PRIME_EN (1<<0)
group-Avnet 0:478cfd88041f 456
group-Avnet 0:478cfd88041f 457 typedef union regPHY_CTRL4_tag{
group-Avnet 0:478cfd88041f 458 uint8_t byte;
group-Avnet 0:478cfd88041f 459 struct{
group-Avnet 0:478cfd88041f 460 uint8_t TC2PRIME_EN:1;
group-Avnet 0:478cfd88041f 461 uint8_t PROMISCUOUS:1;
group-Avnet 0:478cfd88041f 462 uint8_t TMRLOAD:1;
group-Avnet 0:478cfd88041f 463 uint8_t CCATYPE:2;
group-Avnet 0:478cfd88041f 464 uint8_t PANCORDNTR0:1;
group-Avnet 0:478cfd88041f 465 uint8_t TC3TMOUT:1;
group-Avnet 0:478cfd88041f 466 uint8_t TRCV_MSK:1;
group-Avnet 0:478cfd88041f 467 }bit;
group-Avnet 0:478cfd88041f 468 } regPHY_CTRL4_t;
group-Avnet 0:478cfd88041f 469
group-Avnet 0:478cfd88041f 470 // SRC_CTRL bits
group-Avnet 0:478cfd88041f 471 #define cSRC_CTRL_INDEX (0x0F)
group-Avnet 0:478cfd88041f 472 #define cSRC_CTRL_INDEX_Shift_c (4)
group-Avnet 0:478cfd88041f 473 #define cSRC_CTRL_ACK_FRM_PND (1<<3)
group-Avnet 0:478cfd88041f 474 #define cSRC_CTRL_SRCADDR_EN (1<<2)
group-Avnet 0:478cfd88041f 475 #define cSRC_CTRL_INDEX_EN (1<<1)
group-Avnet 0:478cfd88041f 476 #define cSRC_CTRL_INDEX_DISABLE (1<<0)
group-Avnet 0:478cfd88041f 477
group-Avnet 0:478cfd88041f 478 typedef union regSRC_CTRL_tag{
group-Avnet 0:478cfd88041f 479 uint8_t byte;
group-Avnet 0:478cfd88041f 480 struct{
group-Avnet 0:478cfd88041f 481 uint8_t INDEX_DISABLE:1;
group-Avnet 0:478cfd88041f 482 uint8_t INDEX_EN:1;
group-Avnet 0:478cfd88041f 483 uint8_t SRCADDR_EN:1;
group-Avnet 0:478cfd88041f 484 uint8_t ACK_FRM_PND:1;
group-Avnet 0:478cfd88041f 485 uint8_t INDEX:4;
group-Avnet 0:478cfd88041f 486 }bit;
group-Avnet 0:478cfd88041f 487 } regSRC_CTRL_t;
group-Avnet 0:478cfd88041f 488
group-Avnet 0:478cfd88041f 489 // ASM_CTRL1 bits
group-Avnet 0:478cfd88041f 490 #define cASM_CTRL1_CLEAR (1<<7)
group-Avnet 0:478cfd88041f 491 #define cASM_CTRL1_START (1<<6)
group-Avnet 0:478cfd88041f 492 #define cASM_CTRL1_SELFTST (1<<5)
group-Avnet 0:478cfd88041f 493 #define cASM_CTRL1_CTR (1<<4)
group-Avnet 0:478cfd88041f 494 #define cASM_CTRL1_CBC (1<<3)
group-Avnet 0:478cfd88041f 495 #define cASM_CTRL1_AES (1<<2)
group-Avnet 0:478cfd88041f 496 #define cASM_CTRL1_LOAD_MAC (1<<1)
group-Avnet 0:478cfd88041f 497
group-Avnet 0:478cfd88041f 498 // ASM_CTRL2 bits
group-Avnet 0:478cfd88041f 499 #define cASM_CTRL2_DATA_REG_TYPE_SEL (7)
group-Avnet 0:478cfd88041f 500 #define cASM_CTRL2_DATA_REG_TYPE_SEL_Shift_c (5)
group-Avnet 0:478cfd88041f 501 #define cASM_CTRL2_TSTPAS (1<<1)
group-Avnet 0:478cfd88041f 502
group-Avnet 0:478cfd88041f 503 // CLK_OUT_CTRL bits
group-Avnet 0:478cfd88041f 504 #define cCLK_OUT_CTRL_EXTEND (1<<7)
group-Avnet 0:478cfd88041f 505 #define cCLK_OUT_CTRL_HIZ (1<<6)
group-Avnet 0:478cfd88041f 506 #define cCLK_OUT_CTRL_SR (1<<5)
group-Avnet 0:478cfd88041f 507 #define cCLK_OUT_CTRL_DS (1<<4)
group-Avnet 0:478cfd88041f 508 #define cCLK_OUT_CTRL_EN (1<<3)
group-Avnet 0:478cfd88041f 509 #define cCLK_OUT_CTRL_DIV (7)
group-Avnet 0:478cfd88041f 510
group-Avnet 0:478cfd88041f 511 // PWR_MODES bits
group-Avnet 0:478cfd88041f 512 #define cPWR_MODES_XTAL_READY (1<<5)
group-Avnet 0:478cfd88041f 513 #define cPWR_MODES_XTALEN (1<<4)
group-Avnet 0:478cfd88041f 514 #define cPWR_MODES_ASM_CLK_EN (1<<3)
group-Avnet 0:478cfd88041f 515 #define cPWR_MODES_AUTODOZE (1<<1)
group-Avnet 0:478cfd88041f 516 #define cPWR_MODES_PMC_MODE (1<<0)
group-Avnet 0:478cfd88041f 517
group-Avnet 0:478cfd88041f 518 // RX_FRAME_FILTER bits
group-Avnet 0:478cfd88041f 519 #define cRX_FRAME_FLT_FRM_VER (0xC0)
group-Avnet 0:478cfd88041f 520 #define cRX_FRAME_FLT_FRM_VER_Shift_c (6)
group-Avnet 0:478cfd88041f 521 #define cRX_FRAME_FLT_ACTIVE_PROMISCUOUS (1<<5)
group-Avnet 0:478cfd88041f 522 #define cRX_FRAME_FLT_NS_FT (1<<4)
group-Avnet 0:478cfd88041f 523 #define cRX_FRAME_FLT_CMD_FT (1<<3)
group-Avnet 0:478cfd88041f 524 #define cRX_FRAME_FLT_ACK_FT (1<<2)
group-Avnet 0:478cfd88041f 525 #define cRX_FRAME_FLT_DATA_FT (1<<1)
group-Avnet 0:478cfd88041f 526 #define cRX_FRAME_FLT_BEACON_FT (1<<0)
group-Avnet 0:478cfd88041f 527
group-Avnet 0:478cfd88041f 528 typedef union regRX_FRAME_FILTER_tag{
group-Avnet 0:478cfd88041f 529 uint8_t byte;
group-Avnet 0:478cfd88041f 530 struct{
group-Avnet 0:478cfd88041f 531 uint8_t FRAME_FLT_BEACON_FT:1;
group-Avnet 0:478cfd88041f 532 uint8_t FRAME_FLT_DATA_FT:1;
group-Avnet 0:478cfd88041f 533 uint8_t FRAME_FLT_ACK_FT:1;
group-Avnet 0:478cfd88041f 534 uint8_t FRAME_FLT_CMD_FT:1;
group-Avnet 0:478cfd88041f 535 uint8_t FRAME_FLT_NS_FT:1;
group-Avnet 0:478cfd88041f 536 uint8_t FRAME_FLT_ACTIVE_PROMISCUOUS:1;
group-Avnet 0:478cfd88041f 537 uint8_t FRAME_FLT_FRM_VER:2;
group-Avnet 0:478cfd88041f 538 }bit;
group-Avnet 0:478cfd88041f 539 } regRX_FRAME_FILTER_t;
group-Avnet 0:478cfd88041f 540
group-Avnet 0:478cfd88041f 541 // DUAL_PAN_CTRL bits
group-Avnet 0:478cfd88041f 542 #define cDUAL_PAN_CTRL_DUAL_PAN_SAM_LVL_MSK (0xF0)
group-Avnet 0:478cfd88041f 543 #define cDUAL_PAN_CTRL_DUAL_PAN_SAM_LVL_Shift_c (4)
group-Avnet 0:478cfd88041f 544 #define cDUAL_PAN_CTRL_CURRENT_NETWORK (1<<3)
group-Avnet 0:478cfd88041f 545 #define cDUAL_PAN_CTRL_PANCORDNTR1 (1<<2)
group-Avnet 0:478cfd88041f 546 #define cDUAL_PAN_CTRL_DUAL_PAN_AUTO (1<<1)
group-Avnet 0:478cfd88041f 547 #define cDUAL_PAN_CTRL_ACTIVE_NETWORK (1<<0)
group-Avnet 0:478cfd88041f 548
group-Avnet 0:478cfd88041f 549 // DUAL_PAN_STS bits
group-Avnet 0:478cfd88041f 550 #define cDUAL_PAN_STS_RECD_ON_PAN1 (1<<7)
group-Avnet 0:478cfd88041f 551 #define cDUAL_PAN_STS_RECD_ON_PAN0 (1<<6)
group-Avnet 0:478cfd88041f 552 #define cDUAL_PAN_STS_DUAL_PAN_REMAIN (0x3F)
group-Avnet 0:478cfd88041f 553
group-Avnet 0:478cfd88041f 554 // CCA_CTRL bits
group-Avnet 0:478cfd88041f 555 #define cCCA_CTRL_AGC_FRZ_EN (1<<6)
group-Avnet 0:478cfd88041f 556 #define cCCA_CTRL_CONT_RSSI_EN (1<<5)
group-Avnet 0:478cfd88041f 557 #define cCCA_CTRL_LQI_RSSI_NOT_CORR (1<<4)
group-Avnet 0:478cfd88041f 558 #define cCCA_CTRL_CCA3_AND_NOT_OR (1<<3)
group-Avnet 0:478cfd88041f 559 #define cCCA_CTRL_POWER_COMP_EN_LQI (1<<2)
group-Avnet 0:478cfd88041f 560 #define cCCA_CTRL_POWER_COMP_EN_ED (1<<1)
group-Avnet 0:478cfd88041f 561 #define cCCA_CTRL_POWER_COMP_EN_CCA1 (1<<0)
group-Avnet 0:478cfd88041f 562
group-Avnet 0:478cfd88041f 563 // GPIO_DATA bits
group-Avnet 0:478cfd88041f 564 #define cGPIO_DATA_7 (1<<7)
group-Avnet 0:478cfd88041f 565 #define cGPIO_DATA_6 (1<<6)
group-Avnet 0:478cfd88041f 566 #define cGPIO_DATA_5 (1<<5)
group-Avnet 0:478cfd88041f 567 #define cGPIO_DATA_4 (1<<4)
group-Avnet 0:478cfd88041f 568 #define cGPIO_DATA_3 (1<<3)
group-Avnet 0:478cfd88041f 569 #define cGPIO_DATA_2 (1<<2)
group-Avnet 0:478cfd88041f 570 #define cGPIO_DATA_1 (1<<1)
group-Avnet 0:478cfd88041f 571 #define cGPIO_DATA_0 (1<<0)
group-Avnet 0:478cfd88041f 572
group-Avnet 0:478cfd88041f 573 // GPIO_DIR bits
group-Avnet 0:478cfd88041f 574 #define cGPIO_DIR_7 (1<<7)
group-Avnet 0:478cfd88041f 575 #define cGPIO_DIR_6 (1<<6)
group-Avnet 0:478cfd88041f 576 #define cGPIO_DIR_5 (1<<5)
group-Avnet 0:478cfd88041f 577 #define cGPIO_DIR_4 (1<<4)
group-Avnet 0:478cfd88041f 578 #define cGPIO_DIR_3 (1<<3)
group-Avnet 0:478cfd88041f 579 #define cGPIO_DIR_2 (1<<2)
group-Avnet 0:478cfd88041f 580 #define cGPIO_DIR_1 (1<<1)
group-Avnet 0:478cfd88041f 581 #define cGPIO_DIR_0 (1<<0)
group-Avnet 0:478cfd88041f 582
group-Avnet 0:478cfd88041f 583 // GPIO_PUL_EN bits
group-Avnet 0:478cfd88041f 584 #define cGPIO_PUL_EN_7 (1<<7)
group-Avnet 0:478cfd88041f 585 #define cGPIO_PUL_EN_6 (1<<6)
group-Avnet 0:478cfd88041f 586 #define cGPIO_PUL_EN_5 (1<<5)
group-Avnet 0:478cfd88041f 587 #define cGPIO_PUL_EN_4 (1<<4)
group-Avnet 0:478cfd88041f 588 #define cGPIO_PUL_EN_3 (1<<3)
group-Avnet 0:478cfd88041f 589 #define cGPIO_PUL_EN_2 (1<<2)
group-Avnet 0:478cfd88041f 590 #define cGPIO_PUL_EN_1 (1<<1)
group-Avnet 0:478cfd88041f 591 #define cGPIO_PUL_EN_0 (1<<0)
group-Avnet 0:478cfd88041f 592
group-Avnet 0:478cfd88041f 593 // GPIO_PUL_SEL bits
group-Avnet 0:478cfd88041f 594 #define cGPIO_PUL_SEL_7 (1<<7)
group-Avnet 0:478cfd88041f 595 #define cGPIO_PUL_SEL_6 (1<<6)
group-Avnet 0:478cfd88041f 596 #define cGPIO_PUL_SEL_5 (1<<5)
group-Avnet 0:478cfd88041f 597 #define cGPIO_PUL_SEL_4 (1<<4)
group-Avnet 0:478cfd88041f 598 #define cGPIO_PUL_SEL_3 (1<<3)
group-Avnet 0:478cfd88041f 599 #define cGPIO_PUL_SEL_2 (1<<2)
group-Avnet 0:478cfd88041f 600 #define cGPIO_PUL_SEL_1 (1<<1)
group-Avnet 0:478cfd88041f 601 #define cGPIO_PUL_SEL_0 (1<<0)
group-Avnet 0:478cfd88041f 602
group-Avnet 0:478cfd88041f 603 // GPIO_DS bits
group-Avnet 0:478cfd88041f 604 #define cGPIO_DS_7 (1<<7)
group-Avnet 0:478cfd88041f 605 #define cGPIO_DS_6 (1<<6)
group-Avnet 0:478cfd88041f 606 #define cGPIO_DS_5 (1<<5)
group-Avnet 0:478cfd88041f 607 #define cGPIO_DS_4 (1<<4)
group-Avnet 0:478cfd88041f 608 #define cGPIO_DS_3 (1<<3)
group-Avnet 0:478cfd88041f 609 #define cGPIO_DS_2 (1<<2)
group-Avnet 0:478cfd88041f 610 #define cGPIO_DS_1 (1<<1)
group-Avnet 0:478cfd88041f 611 #define cGPIO_DS_0 (1<<0)
group-Avnet 0:478cfd88041f 612
group-Avnet 0:478cfd88041f 613 // SPI_CTRL bits
group-Avnet 0:478cfd88041f 614 //#define cSPI_CTRL_MISO_HIZ_EN (1<<1)
group-Avnet 0:478cfd88041f 615 //#define cSPI_CTRL_PB_PROTECT (1<<0)
group-Avnet 0:478cfd88041f 616
group-Avnet 0:478cfd88041f 617 // ANT_PAD_CTRL bits
group-Avnet 0:478cfd88041f 618 #define cANT_PAD_CTRL_ANTX_POL (0x0F)
group-Avnet 0:478cfd88041f 619 #define cANT_PAD_CTRL_ANTX_POL_Shift_c (4)
group-Avnet 0:478cfd88041f 620 #define cANT_PAD_CTRL_ANTX_CTRLMODE (1<<3)
group-Avnet 0:478cfd88041f 621 #define cANT_PAD_CTRL_ANTX_HZ (1<<2)
group-Avnet 0:478cfd88041f 622 #define cANT_PAD_CTRL_ANTX_EN (3)
group-Avnet 0:478cfd88041f 623
group-Avnet 0:478cfd88041f 624 // MISC_PAD_CTRL bits
group-Avnet 0:478cfd88041f 625 #define cMISC_PAD_CTRL_MISO_HIZ_EN (1<<3)
group-Avnet 0:478cfd88041f 626 #define cMISC_PAD_CTRL_IRQ_B_OD (1<<2)
group-Avnet 0:478cfd88041f 627 #define cMISC_PAD_CTRL_NON_GPIO_DS (1<<1)
group-Avnet 0:478cfd88041f 628 #define cMISC_PAD_CTRL_ANTX_CURR (1<<0)
group-Avnet 0:478cfd88041f 629
group-Avnet 0:478cfd88041f 630 // ANT_AGC_CTRL bits
group-Avnet 0:478cfd88041f 631 #define cANT_AGC_CTRL_FAD_EN_Shift_c (0)
group-Avnet 0:478cfd88041f 632 #define cANT_AGC_CTRL_FAD_EN_Mask_c (1<<cANT_AGC_CTRL_FAD_EN_Shift_c)
group-Avnet 0:478cfd88041f 633 #define cANT_AGC_CTRL_ANTX_Shift_c (1)
group-Avnet 0:478cfd88041f 634 #define cANT_AGC_CTRL_ANTX_Mask_c (1<<cANT_AGC_CTRL_ANTX_Shift_c)
group-Avnet 0:478cfd88041f 635
group-Avnet 0:478cfd88041f 636 // BSM_CTRL bits
group-Avnet 0:478cfd88041f 637 #define cBSM_CTRL_BSM_EN (1<<0)
group-Avnet 0:478cfd88041f 638
group-Avnet 0:478cfd88041f 639 // SOFT_RESET bits
group-Avnet 0:478cfd88041f 640 #define cSOFT_RESET_SOG_RST (1<<7)
group-Avnet 0:478cfd88041f 641 #define cSOFT_RESET_REGS_RST (1<<4)
group-Avnet 0:478cfd88041f 642 #define cSOFT_RESET_PLL_RST (1<<3)
group-Avnet 0:478cfd88041f 643 #define cSOFT_RESET_TX_RST (1<<2)
group-Avnet 0:478cfd88041f 644 #define cSOFT_RESET_RX_RST (1<<1)
group-Avnet 0:478cfd88041f 645 #define cSOFT_RESET_SEQ_MGR_RST (1<<0)
group-Avnet 0:478cfd88041f 646
group-Avnet 0:478cfd88041f 647 // SEQ_MGR_CTRL bits
group-Avnet 0:478cfd88041f 648 #define cSEQ_MGR_CTRL_SEQ_STATE_CTRL (3)
group-Avnet 0:478cfd88041f 649 #define cSEQ_MGR_CTRL_SEQ_STATE_CTRL_Shift_c (6)
group-Avnet 0:478cfd88041f 650 #define cSEQ_MGR_CTRL_NO_RX_RECYCLE (1<<5)
group-Avnet 0:478cfd88041f 651 #define cSEQ_MGR_CTRL_LATCH_PREAMBLE (1<<4)
group-Avnet 0:478cfd88041f 652 #define cSEQ_MGR_CTRL_EVENT_TMR_DO_NOT_LATCH (1<<3)
group-Avnet 0:478cfd88041f 653 #define cSEQ_MGR_CTRL_CLR_NEW_SEQ_INHIBIT (1<<2)
group-Avnet 0:478cfd88041f 654 #define cSEQ_MGR_CTRL_PSM_LOCK_DIS (1<<1)
group-Avnet 0:478cfd88041f 655 #define cSEQ_MGR_CTRL_PLL_ABORT_OVRD (1<<0)
group-Avnet 0:478cfd88041f 656
group-Avnet 0:478cfd88041f 657 // SEQ_MGR_STS bits
group-Avnet 0:478cfd88041f 658 #define cSEQ_MGR_STS_TMR2_SEQ_TRIG_ARMED (1<<7)
group-Avnet 0:478cfd88041f 659 #define cSEQ_MGR_STS_RX_MODE (1<<6)
group-Avnet 0:478cfd88041f 660 #define cSEQ_MGR_STS_RX_TIMEOUT_PENDING (1<<5)
group-Avnet 0:478cfd88041f 661 #define cSEQ_MGR_STS_NEW_SEQ_INHIBIT (1<<4)
group-Avnet 0:478cfd88041f 662 #define cSEQ_MGR_STS_SEQ_IDLE (1<<3)
group-Avnet 0:478cfd88041f 663 #define cSEQ_MGR_STS_XCVSEQ_ACTUAL (7)
group-Avnet 0:478cfd88041f 664
group-Avnet 0:478cfd88041f 665 // ABORT_STS bits
group-Avnet 0:478cfd88041f 666 #define cABORT_STS_PLL_ABORTED (1<<2)
group-Avnet 0:478cfd88041f 667 #define cABORT_STS_TC3_ABORTED (1<<1)
group-Avnet 0:478cfd88041f 668 #define cABORT_STS_SW_ABORTED (1<<0)
group-Avnet 0:478cfd88041f 669
group-Avnet 0:478cfd88041f 670 // FILTERFAIL_CODE2 bits
group-Avnet 0:478cfd88041f 671 #define cFILTERFAIL_CODE2_PAN_SEL (1<<7)
group-Avnet 0:478cfd88041f 672 #define cFILTERFAIL_CODE2_9_8 (3)
group-Avnet 0:478cfd88041f 673
group-Avnet 0:478cfd88041f 674 // PHY_STS bits
group-Avnet 0:478cfd88041f 675 #define cPHY_STS_PLL_UNLOCK (1<<7)
group-Avnet 0:478cfd88041f 676 #define cPHY_STS_PLL_LOCK_ERR (1<<6)
group-Avnet 0:478cfd88041f 677 #define cPHY_STS_PLL_LOCK (1<<5)
group-Avnet 0:478cfd88041f 678 #define cPHY_STS_CRCVALID (1<<3)
group-Avnet 0:478cfd88041f 679 #define cPHY_STS_FILTERFAIL_FLAG_SEL (1<<2)
group-Avnet 0:478cfd88041f 680 #define cPHY_STS_SFD_DET (1<<1)
group-Avnet 0:478cfd88041f 681 #define cPHY_STS_PREAMBLE_DET (1<<0)
group-Avnet 0:478cfd88041f 682
group-Avnet 0:478cfd88041f 683 // TESTMODE_CTRL bits
group-Avnet 0:478cfd88041f 684 #define cTEST_MODE_CTRL_HOT_ANT (1<<4)
group-Avnet 0:478cfd88041f 685 #define cTEST_MODE_CTRL_IDEAL_RSSI_EN (1<<3)
group-Avnet 0:478cfd88041f 686 #define cTEST_MODE_CTRL_IDEAL_PFC_EN (1<<2)
group-Avnet 0:478cfd88041f 687 #define cTEST_MODE_CTRL_CONTINUOUS_EN (1<<1)
group-Avnet 0:478cfd88041f 688 #define cTEST_MODE_CTRL_FPGA_EN (1<<0)
group-Avnet 0:478cfd88041f 689
group-Avnet 0:478cfd88041f 690 // DTM_CTRL1 bits
group-Avnet 0:478cfd88041f 691 #define cDTM_CTRL1_ATM_LOCKED (1<<7)
group-Avnet 0:478cfd88041f 692 #define cDTM_CTRL1_DTM_EN (1<<6)
group-Avnet 0:478cfd88041f 693 #define cDTM_CTRL1_PAGE5 (1<<5)
group-Avnet 0:478cfd88041f 694 #define cDTM_CTRL1_PAGE4 (1<<4)
group-Avnet 0:478cfd88041f 695 #define cDTM_CTRL1_PAGE3 (1<<3)
group-Avnet 0:478cfd88041f 696 #define cDTM_CTRL1_PAGE2 (1<<2)
group-Avnet 0:478cfd88041f 697 #define cDTM_CTRL1_PAGE1 (1<<1)
group-Avnet 0:478cfd88041f 698 #define cDTM_CTRL1_PAGE0 (1<<0)
group-Avnet 0:478cfd88041f 699
group-Avnet 0:478cfd88041f 700 // TX_MODE_CTRL
group-Avnet 0:478cfd88041f 701 #define cTX_MODE_CTRL_TX_INV (1<<4)
group-Avnet 0:478cfd88041f 702 #define cTX_MODE_CTRL_BT_EN (1<<3)
group-Avnet 0:478cfd88041f 703 #define cTX_MODE_CTRL_DTS2 (1<<2)
group-Avnet 0:478cfd88041f 704 #define cTX_MODE_CTRL_DTS1 (1<<1)
group-Avnet 0:478cfd88041f 705 #define cTX_MODE_CTRL_DTS0 (1<<0)
group-Avnet 0:478cfd88041f 706
group-Avnet 0:478cfd88041f 707 #define cTX_MODE_CTRL_DTS_MASK (7)
group-Avnet 0:478cfd88041f 708
group-Avnet 0:478cfd88041f 709 // CLK_OUT_CTRL bits
group-Avnet 0:478cfd88041f 710 #define cCLK_OUT_EXTEND (1<<7)
group-Avnet 0:478cfd88041f 711 #define cCLK_OUT_HIZ (1<<6)
group-Avnet 0:478cfd88041f 712 #define cCLK_OUT_SR (1<<5)
group-Avnet 0:478cfd88041f 713 #define cCLK_OUT_DS (1<<4)
group-Avnet 0:478cfd88041f 714 #define cCLK_OUT_EN (1<<3)
group-Avnet 0:478cfd88041f 715 #define cCLK_OUT_DIV_Mask (7<<0)
group-Avnet 0:478cfd88041f 716
group-Avnet 0:478cfd88041f 717 #define gCLK_OUT_FREQ_32_MHz (0)
group-Avnet 0:478cfd88041f 718 #define gCLK_OUT_FREQ_16_MHz (1)
group-Avnet 0:478cfd88041f 719 #define gCLK_OUT_FREQ_8_MHz (2)
group-Avnet 0:478cfd88041f 720 #define gCLK_OUT_FREQ_4_MHz (3)
group-Avnet 0:478cfd88041f 721 #define gCLK_OUT_FREQ_1_MHz (4)
group-Avnet 0:478cfd88041f 722 #define gCLK_OUT_FREQ_250_KHz (5)
group-Avnet 0:478cfd88041f 723 #define gCLK_OUT_FREQ_62_5_KHz (6)
group-Avnet 0:478cfd88041f 724 #define gCLK_OUT_FREQ_32_78_KHz (7)
group-Avnet 0:478cfd88041f 725 #define gCLK_OUT_FREQ_DISABLE (8)
group-Avnet 0:478cfd88041f 726
group-Avnet 0:478cfd88041f 727
group-Avnet 0:478cfd88041f 728
group-Avnet 0:478cfd88041f 729
group-Avnet 0:478cfd88041f 730 #endif /* __MCR20_REG_H__ */