system_M480.c

00001 /**************************************************************************//**
00002  * @file     system_M480.c
00003  * @version  V1.000
00004  * @brief    CMSIS Cortex-M4 Core Peripheral Access Layer Source File for M480
00005  *
00006  * @copyright (C) 2016 Nuvoton Technology Corp. All rights reserved.
00007  *
00008  * Redistribution and use in source and binary forms, with or without modification,
00009  * are permitted provided that the following conditions are met:
00010  *   1. Redistributions of source code must retain the above copyright notice,
00011  *      this list of conditions and the following disclaimer.
00012  *   2. Redistributions in binary form must reproduce the above copyright notice,
00013  *      this list of conditions and the following disclaimer in the documentation
00014  *      and/or other materials provided with the distribution.
00015  *   3. Neither the name of Nuvoton Technology Corp. nor the names of its contributors
00016  *      may be used to endorse or promote products derived from this software
00017  *      without specific prior written permission.
00018  * 
00019  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00020  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00021  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00022  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00023  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00024  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00025  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00026  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00027  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00028  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00029 *****************************************************************************/
00030 
00031 #include "NuMicro.h"
00032 
00033 
00034 /*----------------------------------------------------------------------------
00035   DEFINES
00036  *----------------------------------------------------------------------------*/
00037 
00038 
00039 /*----------------------------------------------------------------------------
00040   Clock Variable definitions
00041  *----------------------------------------------------------------------------*/
00042 uint32_t SystemCoreClock  = __SYSTEM_CLOCK;    /*!< System Clock Frequency (Core Clock)*/
00043 uint32_t CyclesPerUs       = (__HSI / 1000000UL); /* Cycles per micro second */
00044 uint32_t PllClock          = __HSI;             /*!< PLL Output Clock Frequency         */
00045 uint32_t gau32ClkSrcTbl[] = {__HXT, __LXT, 0UL, __LIRC, 0UL, 0UL, 0UL, __HIRC};
00046 
00047 /*----------------------------------------------------------------------------
00048   Clock functions
00049  *----------------------------------------------------------------------------*/
00050 void SystemCoreClockUpdate(void)             /* Get Core Clock Frequency      */
00051 {
00052     uint32_t u32Freq, u32ClkSrc;
00053     uint32_t u32HclkDiv;
00054     /* Update PLL Clock */
00055     PllClock  = CLK_GetPLLClockFreq();
00056     u32ClkSrc = CLK->CLKSEL0 & CLK_CLKSEL0_HCLKSEL_Msk;
00057 
00058     if (u32ClkSrc == CLK_CLKSEL0_HCLKSEL_PLL) {
00059         /* Use PLL clock */
00060         u32Freq = PllClock ;
00061     } else {
00062         /* Use the clock sources directly */
00063         u32Freq = gau32ClkSrcTbl[u32ClkSrc];
00064     }
00065 
00066     u32HclkDiv = (CLK->CLKDIV0 & CLK_CLKDIV0_HCLKDIV_Msk) + 1UL;
00067     /* Update System Core Clock */
00068     SystemCoreClock = u32Freq / u32HclkDiv;
00069     //if(SystemCoreClock == 0)
00070     //    __BKPT(0);
00071     CyclesPerUs  = (SystemCoreClock + 500000UL) / 1000000UL;
00072 }
00073 
00074 /**
00075   * @brief      Set PF.2 and PF.3 to input mode
00076   * @param      None
00077   * @return     None
00078   * @details    GPIO default state could be configured as input or quasi through user config.
00079   *             To use HXT, PF.2 and PF.3 must not set as quasi mode. This function changes
00080   *             PF.2 and PF.3 to input mode no matter which mode they are working at.
00081   */
00082 static __INLINE void HXTInit(void)
00083 {
00084     PF->MODE &= ~(GPIO_MODE_MODE2_Msk | GPIO_MODE_MODE3_Msk);
00085 }
00086 
00087 /**
00088  * @brief  Initialize the System
00089  *
00090  * @param  none
00091  * @return none
00092  */
00093 void SystemInit(void)
00094 {
00095     /* Add your system initialize code here.
00096        Do not use global variables because this function is called before
00097        reaching pre-main. RW section maybe overwritten afterwards.          */
00098     /* FPU settings ------------------------------------------------------------*/
00099 #if (__FPU_PRESENT == 1U) && (__FPU_USED == 1U)
00100     SCB->CPACR |= ((3UL << 10 * 2) |               /* set CP10 Full Access */
00101                    (3UL << 11 * 2));               /* set CP11 Full Access */
00102 #endif
00103     /* Set access cycle for CPU @ 192MHz */
00104     FMC->CYCCTL = (FMC->CYCCTL & ~FMC_CYCCTL_CYCLE_Msk) | (8 << FMC_CYCCTL_CYCLE_Pos);
00105     /* Configure power down bias, must set 1 before entering power down mode.
00106        So set it at the very beginning */
00107     CLK->LDOCTL |= CLK_LDOCTL_PDBIASEN_Msk;
00108     /* Hand over the control of PF.4~11 I/O function from RTC module to GPIO module */
00109     CLK->APBCLK0 |= CLK_APBCLK0_RTCCKEN_Msk;
00110     RTC->GPIOCTL0 &= ~(RTC_GPIOCTL0_CTLSEL0_Msk | RTC_GPIOCTL0_CTLSEL1_Msk |
00111                        RTC_GPIOCTL0_CTLSEL2_Msk | RTC_GPIOCTL0_CTLSEL3_Msk);
00112     RTC->GPIOCTL1 &= ~(RTC_GPIOCTL1_CTLSEL4_Msk | RTC_GPIOCTL1_CTLSEL5_Msk |
00113                        RTC_GPIOCTL1_CTLSEL6_Msk | RTC_GPIOCTL1_CTLSEL7_Msk);
00114     CLK->APBCLK0 &= ~CLK_APBCLK0_RTCCKEN_Msk;
00115     HXTInit();
00116 }
00117 /*** (C) COPYRIGHT 2016 Nuvoton Technology Corp. ***/