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CLK Exported Functions
Functions

CLK Exported Functions
[CLK Driver]

Functions

__STATIC_INLINE void CLK_SysTickDelay (uint32_t us)
 This function execute delay function.
__STATIC_INLINE void CLK_SysTickLongDelay (uint32_t us)
 This function execute long delay function.
void CLK_DisableCKO (void)
 Disable clock divider output function.
void CLK_EnableCKO (uint32_t u32ClkSrc, uint32_t u32ClkDiv, uint32_t u32ClkDivBy1En)
 This function enable clock divider output module clock, enable clock divider output function and set frequency selection.
void CLK_PowerDown (void)
 Enter to Power-down mode.
void CLK_Idle (void)
 Enter to Idle mode.
uint32_t CLK_GetHXTFreq (void)
 Get external high speed crystal clock frequency.
uint32_t CLK_GetLXTFreq (void)
 Get external low speed crystal clock frequency.
uint32_t CLK_GetHCLKFreq (void)
 Get HCLK frequency.
uint32_t CLK_GetPCLK0Freq (void)
 Get PCLK0 frequency.
uint32_t CLK_GetPCLK1Freq (void)
 Get PCLK1 frequency.
uint32_t CLK_GetCPUFreq (void)
 Get CPU frequency.
uint32_t CLK_SetCoreClock (uint32_t u32Hclk)
 Set HCLK frequency.
void CLK_SetHCLK (uint32_t u32ClkSrc, uint32_t u32ClkDiv)
 This function set HCLK clock source and HCLK clock divider.
void CLK_SetModuleClock (uint32_t u32ModuleIdx, uint32_t u32ClkSrc, uint32_t u32ClkDiv)
 This function set selected module clock source and module clock divider.
void CLK_SetSysTickClockSrc (uint32_t u32ClkSrc)
 Set SysTick clock source.
void CLK_EnableXtalRC (uint32_t u32ClkMask)
 Enable clock source.
void CLK_DisableXtalRC (uint32_t u32ClkMask)
 Disable clock source.
void CLK_EnableModuleClock (uint32_t u32ModuleIdx)
 Enable module clock.
void CLK_DisableModuleClock (uint32_t u32ModuleIdx)
 Disable module clock.
uint32_t CLK_EnablePLL (uint32_t u32PllClkSrc, uint32_t u32PllFreq)
 Set PLL frequency.
void CLK_DisablePLL (void)
 Disable PLL.
uint32_t CLK_WaitClockReady (uint32_t u32ClkMask)
 This function check selected clock source status.
void CLK_EnableSysTick (uint32_t u32ClkSrc, uint32_t u32Count)
 Enable System Tick counter.
void CLK_DisableSysTick (void)
 Disable System Tick counter.
void CLK_SetPowerDownMode (uint32_t u32PDMode)
 Power-down mode selected.
void CLK_EnableDPDWKPin (uint32_t u32TriggerType)
 Set Wake-up pin trigger type at Deep Power down mode.
uint32_t CLK_GetPMUWKSrc (void)
 Get power manager wake up source.
void CLK_EnableSPDWKPin (uint32_t u32Port, uint32_t u32Pin, uint32_t u32TriggerType, uint32_t u32DebounceEn)
 Set specified GPIO as wake up source at Stand-by Power down mode.
uint32_t CLK_GetPLLClockFreq (void)
 Get PLL clock frequency.
uint32_t CLK_GetModuleClockSource (uint32_t u32ModuleIdx)
 Get selected module clock source.
uint32_t CLK_GetModuleClockDivider (uint32_t u32ModuleIdx)
 Get selected module clock divider number.

Function Documentation

void CLK_DisableCKO ( void   )

Disable clock divider output function.

Parameters:
None
Returns:
None

This function disable clock divider output function.

Definition at line 51 of file m480_clk.c.

void CLK_DisableModuleClock ( uint32_t  u32ModuleIdx )

Disable module clock.

Parameters:
[in]u32ModuleIdxis module index. Including :

  • PDMA_MODULE
  • ISP_MODULE
  • EBI_MODULE
  • EMAC_MODULE
  • SDH0_MODULE
  • CRC_MODULE
  • HSUSBD_MODULE
  • CRPT_MODULE
  • SPIM_MODULE
  • FMCIDLE_MODULE
  • USBH_MODULE
  • SDH1_MODULE
  • WDT_MODULE
  • RTC_MODULE
  • TMR0_MODULE
  • TMR1_MODULE
  • TMR2_MODULE
  • TMR3_MODULE
  • CLKO_MODULE
  • WWDT_MODULE
  • ACMP01_MODULE
  • I2C0_MODULE
  • I2C1_MODULE
  • I2C2_MODULE
  • QSPI0_MODULE
  • SPI0_MODULE
  • SPI1_MODULE
  • SPI2_MODULE
  • UART0_MODULE
  • UART1_MODULE
  • UART2_MODULE
  • UART3_MODULE
  • UART4_MODULE
  • UART5_MODULE
  • CAN0_MODULE
  • CAN1_MODULE
  • OTG_MODULE
  • USBD_MODULE
  • EADC_MODULE
  • I2S0_MODULE
  • HSOTG_MODULE
  • SC0_MODULE
  • SC1_MODULE
  • SC2_MODULE
  • SPI3_MODULE
  • USCI0_MODULE
  • USCI1_MODULE
  • DAC_MODULE
  • EPWM0_MODULE
  • EPWM1_MODULE
  • BPWM0_MODULE
  • BPWM1_MODULE
  • QEI0_MODULE
  • QEI1_MODULE
  • ECAP0_MODULE
  • ECAP1_MODULE
  • OPA_MODULE
Returns:
None

This function is used to disable module clock.

Definition at line 667 of file m480_clk.c.

void CLK_DisablePLL ( void   )

Disable PLL.

Parameters:
None
Returns:
None

This function set PLL in Power-down mode.
The register write-protection function should be disabled before using this function.

Definition at line 806 of file m480_clk.c.

void CLK_DisableSysTick ( void   )

Disable System Tick counter.

Parameters:
None
Returns:
None

This function disable System Tick counter.

Definition at line 879 of file m480_clk.c.

void CLK_DisableXtalRC ( uint32_t  u32ClkMask )

Disable clock source.

Parameters:
[in]u32ClkMaskis clock source mask. Including :

  • CLK_PWRCTL_HXTEN_Msk
  • CLK_PWRCTL_LXTEN_Msk
  • CLK_PWRCTL_HIRCEN_Msk
  • CLK_PWRCTL_LIRCEN_Msk
Returns:
None

This function disable clock source.
The register write-protection function should be disabled before using this function.

Definition at line 527 of file m480_clk.c.

void CLK_EnableCKO ( uint32_t  u32ClkSrc,
uint32_t  u32ClkDiv,
uint32_t  u32ClkDivBy1En 
)

This function enable clock divider output module clock, enable clock divider output function and set frequency selection.

Parameters:
[in]u32ClkSrcis frequency divider function clock source. Including :

  • CLK_CLKSEL1_CLKOSEL_HXT
  • CLK_CLKSEL1_CLKOSEL_LXT
  • CLK_CLKSEL1_CLKOSEL_HCLK
  • CLK_CLKSEL1_CLKOSEL_HIRC
[in]u32ClkDivis divider output frequency selection. It could be 0~15.
[in]u32ClkDivBy1Enis clock divided by one enabled.
Returns:
None

Output selected clock to CKO. The output clock frequency is divided by u32ClkDiv.
The formula is:
CKO frequency = (Clock source frequency) / 2^(u32ClkDiv + 1)
This function is just used to set CKO clock. User must enable I/O for CKO clock output pin by themselves.

Definition at line 74 of file m480_clk.c.

void CLK_EnableDPDWKPin ( uint32_t  u32TriggerType )

Set Wake-up pin trigger type at Deep Power down mode.

Parameters:
[in]u32TriggerType
  • CLK_DPDWKPIN_RISING
  • CLK_DPDWKPIN_FALLING
  • CLK_DPDWKPIN_BOTHEDGE
Returns:
None

This function is used to enable Wake-up pin trigger type.

Definition at line 925 of file m480_clk.c.

void CLK_EnableModuleClock ( uint32_t  u32ModuleIdx )

Enable module clock.

Parameters:
[in]u32ModuleIdxis module index. Including :

  • PDMA_MODULE
  • ISP_MODULE
  • EBI_MODULE
  • EMAC_MODULE
  • SDH0_MODULE
  • CRC_MODULE
  • HSUSBD_MODULE
  • CRPT_MODULE
  • SPIM_MODULE
  • FMCIDLE_MODULE
  • USBH_MODULE
  • SDH1_MODULE
  • WDT_MODULE
  • RTC_MODULE
  • TMR0_MODULE
  • TMR1_MODULE
  • TMR2_MODULE
  • TMR3_MODULE
  • CLKO_MODULE
  • WWDT_MODULE
  • ACMP01_MODULE
  • I2C0_MODULE
  • I2C1_MODULE
  • I2C2_MODULE
  • QSPI0_MODULE
  • SPI0_MODULE
  • SPI1_MODULE
  • SPI2_MODULE
  • UART0_MODULE
  • UART1_MODULE
  • UART2_MODULE
  • UART3_MODULE
  • UART4_MODULE
  • UART5_MODULE
  • CAN0_MODULE
  • CAN1_MODULE
  • OTG_MODULE
  • USBD_MODULE
  • EADC_MODULE
  • I2S0_MODULE
  • HSOTG_MODULE
  • SC0_MODULE
  • SC1_MODULE
  • SC2_MODULE
  • SPI3_MODULE
  • USCI0_MODULE
  • USCI1_MODULE
  • DAC_MODULE
  • EPWM0_MODULE
  • EPWM1_MODULE
  • BPWM0_MODULE
  • BPWM1_MODULE
  • QEI0_MODULE
  • QEI1_MODULE
  • ECAP0_MODULE
  • ECAP1_MODULE
  • OPA_MODULE
Returns:
None

This function is used to enable module clock.

Definition at line 595 of file m480_clk.c.

uint32_t CLK_EnablePLL ( uint32_t  u32PllClkSrc,
uint32_t  u32PllFreq 
)

Set PLL frequency.

Parameters:
[in]u32PllClkSrcis PLL clock source. Including :

  • CLK_PLLCTL_PLLSRC_HXT
  • CLK_PLLCTL_PLLSRC_HIRC
[in]u32PllFreqis PLL frequency.
Returns:
PLL frequency

This function is used to configure PLLCTL register to set specified PLL frequency.
The register write-protection function should be disabled before using this function.

Definition at line 687 of file m480_clk.c.

void CLK_EnableSPDWKPin ( uint32_t  u32Port,
uint32_t  u32Pin,
uint32_t  u32TriggerType,
uint32_t  u32DebounceEn 
)

Set specified GPIO as wake up source at Stand-by Power down mode.

Parameters:
[in]u32PortGPIO port. It could be 0~3.
[in]u32PinThe pin of specified GPIO port. It could be 0 ~ 15.
[in]u32TriggerType
  • CLK_SPDWKPIN_RISING
  • CLK_SPDWKPIN_FALLING
[in]u32DebounceEn
  • CLK_SPDWKPIN_DEBOUNCEEN
  • CLK_SPDWKPIN_DEBOUNCEDIS
Returns:
None

This function is used to set specified GPIO as wake up source at Stand-by Power down mode.

Definition at line 960 of file m480_clk.c.

void CLK_EnableSysTick ( uint32_t  u32ClkSrc,
uint32_t  u32Count 
)

Enable System Tick counter.

Parameters:
[in]u32ClkSrcis System Tick clock source. Including:

  • CLK_CLKSEL0_STCLKSEL_HXT
  • CLK_CLKSEL0_STCLKSEL_LXT
  • CLK_CLKSEL0_STCLKSEL_HXT_DIV2
  • CLK_CLKSEL0_STCLKSEL_HCLK_DIV2
  • CLK_CLKSEL0_STCLKSEL_HIRC_DIV2
  • CLK_CLKSEL0_STCLKSEL_HCLK
[in]u32Countis System Tick reload value. It could be 0~0xFFFFFF.
Returns:
None

This function set System Tick clock source, reload value, enable System Tick counter and interrupt.
The register write-protection function should be disabled before using this function.

Definition at line 853 of file m480_clk.c.

void CLK_EnableXtalRC ( uint32_t  u32ClkMask )

Enable clock source.

Parameters:
[in]u32ClkMaskis clock source mask. Including :

  • CLK_PWRCTL_HXTEN_Msk
  • CLK_PWRCTL_LXTEN_Msk
  • CLK_PWRCTL_HIRCEN_Msk
  • CLK_PWRCTL_LIRCEN_Msk
Returns:
None

This function enable clock source.
The register write-protection function should be disabled before using this function.

Definition at line 511 of file m480_clk.c.

uint32_t CLK_GetCPUFreq ( void   )

Get CPU frequency.

Parameters:
None
Returns:
CPU frequency

This function get CPU frequency. The frequency unit is Hz.

Definition at line 241 of file m480_clk.c.

uint32_t CLK_GetHCLKFreq ( void   )

Get HCLK frequency.

Parameters:
None
Returns:
HCLK frequency

This function get HCLK frequency. The frequency unit is Hz.

Definition at line 228 of file m480_clk.c.

uint32_t CLK_GetHXTFreq ( void   )

Get external high speed crystal clock frequency.

Parameters:
None
Returns:
External high frequency crystal frequency

This function get external high frequency crystal frequency. The frequency unit is Hz.

Definition at line 131 of file m480_clk.c.

uint32_t CLK_GetLXTFreq ( void   )

Get external low speed crystal clock frequency.

Parameters:
None
Returns:
External low speed crystal clock frequency

This function get external low frequency crystal frequency. The frequency unit is Hz.

Definition at line 151 of file m480_clk.c.

uint32_t CLK_GetModuleClockDivider ( uint32_t  u32ModuleIdx )

Get selected module clock divider number.

Parameters:
[in]u32ModuleIdxis module index.

  • UART0_MODULE
  • UART1_MODULE
  • EADC_MODULE
  • SDH0_MODULE
  • SC0_MODULE
  • SC1_MODULE
  • SC2_MODULE
  • EMAC_MODULE
  • SDH1_MODULE
  • UART2_MODULE
  • UART3_MODULE
  • UART4_MODULE
  • UART5_MODULE
Returns:
Selected module clock divider number setting

This function get selected module clock divider number.

Definition at line 1092 of file m480_clk.c.

uint32_t CLK_GetModuleClockSource ( uint32_t  u32ModuleIdx )

Get selected module clock source.

Parameters:
[in]u32ModuleIdxis module index.

  • SDH0_MODULE
  • SDH1_MODULE
  • WDT_MODULE
  • UART0_MODULE
  • UART1_MODULE
  • CLKO_MODULE
  • WWDT_MODULE
  • TMR0_MODULE
  • TMR1_MODULE
  • TMR2_MODULE
  • TMR3_MODULE
  • EPWM0_MODULE
  • EPWM1_MODULE
  • BPWM0_MODULE
  • BPWM1_MODULE
  • QSPI0_MODULE
  • SPI0_MODULE
  • SPI1_MODULE
  • SPI2_MODULE
  • SPI3_MODULE
  • SC0_MODULE
  • SC1_MODULE
  • SC2_MODULE
  • RTC_MODULE
  • I2S0_MODULE
  • UART2_MODULE
  • UART3_MODULE
  • UART4_MODULE
  • UART5_MODULE
Returns:
Selected module clock source setting

This function get selected module clock source.

Definition at line 1049 of file m480_clk.c.

uint32_t CLK_GetPCLK0Freq ( void   )

Get PCLK0 frequency.

Parameters:
None
Returns:
PCLK0 frequency

This function get PCLK0 frequency. The frequency unit is Hz.

Definition at line 170 of file m480_clk.c.

uint32_t CLK_GetPCLK1Freq ( void   )

Get PCLK1 frequency.

Parameters:
None
Returns:
PCLK1 frequency

This function get PCLK1 frequency. The frequency unit is Hz.

Definition at line 199 of file m480_clk.c.

uint32_t CLK_GetPLLClockFreq ( void   )

Get PLL clock frequency.

Parameters:
None
Returns:
PLL frequency

This function get PLL frequency. The frequency unit is Hz.

Definition at line 979 of file m480_clk.c.

uint32_t CLK_GetPMUWKSrc ( void   )

Get power manager wake up source.

Parameters:
[in]None
Returns:
None

This function get power manager wake up source.

Definition at line 939 of file m480_clk.c.

void CLK_Idle ( void   )

Enter to Idle mode.

Parameters:
None
Returns:
None

This function let system enter to Idle mode.
The register write-protection function should be disabled before using this function.

Definition at line 115 of file m480_clk.c.

void CLK_PowerDown ( void   )

Enter to Power-down mode.

Parameters:
None
Returns:
None

This function is used to let system enter to Power-down mode.
The register write-protection function should be disabled before using this function.

Definition at line 91 of file m480_clk.c.

uint32_t CLK_SetCoreClock ( uint32_t  u32Hclk )

Set HCLK frequency.

Parameters:
[in]u32Hclkis HCLK frequency. The range of u32Hclk is running up to 192MHz.
Returns:
HCLK frequency

This function is used to set HCLK frequency. The frequency unit is Hz.
The register write-protection function should be disabled before using this function.

Definition at line 255 of file m480_clk.c.

void CLK_SetHCLK ( uint32_t  u32ClkSrc,
uint32_t  u32ClkDiv 
)

This function set HCLK clock source and HCLK clock divider.

Parameters:
[in]u32ClkSrcis HCLK clock source. Including :

  • CLK_CLKSEL0_HCLKSEL_HXT
  • CLK_CLKSEL0_HCLKSEL_LXT
  • CLK_CLKSEL0_HCLKSEL_PLL
  • CLK_CLKSEL0_HCLKSEL_LIRC
  • CLK_CLKSEL0_HCLKSEL_HIRC
[in]u32ClkDivis HCLK clock divider. Including :

  • CLK_CLKDIV0_HCLK(x)
Returns:
None

This function set HCLK clock source and HCLK clock divider.
The register write-protection function should be disabled before using this function.

Definition at line 311 of file m480_clk.c.

void CLK_SetModuleClock ( uint32_t  u32ModuleIdx,
uint32_t  u32ClkSrc,
uint32_t  u32ClkDiv 
)

This function set selected module clock source and module clock divider.

Parameters:
[in]u32ModuleIdxis module index.
[in]u32ClkSrcis module clock source.
[in]u32ClkDivis module clock divider.
Returns:
None

Valid parameter combinations listed in following table:

|Module index |Clock source |Divider | | :---------------- | :----------------------------------- | :-------------------------- | |SDH0_MODULE |CLK_CLKSEL0_SDH0SEL_HXT |CLK_CLKDIV0_SDH0(x) | |SDH0_MODULE |CLK_CLKSEL0_SDH0SEL_PLL |CLK_CLKDIV0_SDH0(x) | |SDH0_MODULE |CLK_CLKSEL0_SDH0SEL_HIRC |CLK_CLKDIV0_SDH0(x) | |SDH0_MODULE |CLK_CLKSEL0_SDH0SEL_HCLK |CLK_CLKDIV0_SDH0(x) | |SDH1_MODULE |CLK_CLKSEL0_SDH1SEL_HXT |CLK_CLKDIV3_SDH1(x) | |SDH1_MODULE |CLK_CLKSEL0_SDH1SEL_PLL |CLK_CLKDIV3_SDH1(x) | |SDH1_MODULE |CLK_CLKSEL0_SDH1SEL_HIRC |CLK_CLKDIV3_SDH1(x) | |SDH1_MODULE |CLK_CLKSEL0_SDH1SEL_HCLK |CLK_CLKDIV3_SDH1(x) | |WDT_MODULE |CLK_CLKSEL1_WDTSEL_LXT | x | |WDT_MODULE |CLK_CLKSEL1_WDTSEL_LIRC | x | |WDT_MODULE |CLK_CLKSEL1_WDTSEL_HCLK_DIV2048 | x | |TMR0_MODULE |CLK_CLKSEL1_TMR0SEL_HXT | x | |TMR0_MODULE |CLK_CLKSEL1_TMR0SEL_LXT | x | |TMR0_MODULE |CLK_CLKSEL1_TMR0SEL_LIRC | x | |TMR0_MODULE |CLK_CLKSEL1_TMR0SEL_HIRC | x | |TMR0_MODULE |CLK_CLKSEL1_TMR0SEL_PCLK0 | x | |TMR0_MODULE |CLK_CLKSEL1_TMR0SEL_EXT | x | |TMR1_MODULE |CLK_CLKSEL1_TMR1SEL_HXT | x | |TMR1_MODULE |CLK_CLKSEL1_TMR1SEL_LXT | x | |TMR1_MODULE |CLK_CLKSEL1_TMR1SEL_LIRC | x | |TMR1_MODULE |CLK_CLKSEL1_TMR1SEL_HIRC | x | |TMR1_MODULE |CLK_CLKSEL1_TMR1SEL_PCLK0 | x | |TMR1_MODULE |CLK_CLKSEL1_TMR1SEL_EXT | x | |TMR2_MODULE |CLK_CLKSEL1_TMR2SEL_HXT | x | |TMR2_MODULE |CLK_CLKSEL1_TMR2SEL_LXT | x | |TMR2_MODULE |CLK_CLKSEL1_TMR2SEL_LIRC | x | |TMR2_MODULE |CLK_CLKSEL1_TMR2SEL_HIRC | x | |TMR2_MODULE |CLK_CLKSEL1_TMR2SEL_PCLK1 | x | |TMR2_MODULE |CLK_CLKSEL1_TMR2SEL_EXT | x | |TMR3_MODULE |CLK_CLKSEL1_TMR3SEL_HXT | x | |TMR3_MODULE |CLK_CLKSEL1_TMR3SEL_LXT | x | |TMR3_MODULE |CLK_CLKSEL1_TMR3SEL_LIRC | x | |TMR3_MODULE |CLK_CLKSEL1_TMR3SEL_HIRC | x | |TMR3_MODULE |CLK_CLKSEL1_TMR3SEL_PCLK1 | x | |TMR3_MODULE |CLK_CLKSEL1_TMR3SEL_EXT | x | |UART0_MODULE |CLK_CLKSEL1_UART0SEL_HXT |CLK_CLKDIV0_UART0(x) | |UART0_MODULE |CLK_CLKSEL1_UART0SEL_LXT |CLK_CLKDIV0_UART0(x) | |UART0_MODULE |CLK_CLKSEL1_UART0SEL_PLL |CLK_CLKDIV0_UART0(x) | |UART0_MODULE |CLK_CLKSEL1_UART0SEL_HIRC |CLK_CLKDIV0_UART0(x) | |UART1_MODULE |CLK_CLKSEL1_UART1SEL_HXT |CLK_CLKDIV0_UART1(x) | |UART1_MODULE |CLK_CLKSEL1_UART1SEL_LXT |CLK_CLKDIV0_UART1(x) | |UART1_MODULE |CLK_CLKSEL1_UART1SEL_PLL |CLK_CLKDIV0_UART1(x) | |UART1_MODULE |CLK_CLKSEL1_UART1SEL_HIRC |CLK_CLKDIV0_UART1(x) | |CLKO_MODULE |CLK_CLKSEL1_CLKOSEL_HXT | x | |CLKO_MODULE |CLK_CLKSEL1_CLKOSEL_LXT | x | |CLKO_MODULE |CLK_CLKSEL1_CLKOSEL_HIRC | x | |CLKO_MODULE |CLK_CLKSEL1_CLKOSEL_HCLK | x | |WWDT_MODULE |CLK_CLKSEL1_WWDTSEL_LIRC | x | |WWDT_MODULE |CLK_CLKSEL1_WWDTSEL_HCLK_DIV2048 | x | |EPWM0_MODULE |CLK_CLKSEL2_EPWM0SEL_PLL | x | |EPWM0_MODULE |CLK_CLKSEL2_EPWM0SEL_PCLK0 | x | |EPWM1_MODULE |CLK_CLKSEL2_EPWM1SEL_PLL | x | |EPWM1_MODULE |CLK_CLKSEL2_EPWM1SEL_PCLK1 | x | |QSPI0_MODULE |CLK_CLKSEL2_QSPI0SEL_HXT | x | |QSPI0_MODULE |CLK_CLKSEL2_QSPI0SEL_PLL | x | |QSPI0_MODULE |CLK_CLKSEL2_QSPI0SEL_HIRC | x | |QSPI0_MODULE |CLK_CLKSEL2_QSPI0SEL_PCLK0 | x | |SPI0_MODULE |CLK_CLKSEL2_SPI0SEL_HXT | x | |SPI0_MODULE |CLK_CLKSEL2_SPI0SEL_PLL | x | |SPI0_MODULE |CLK_CLKSEL2_SPI0SEL_HIRC | x | |SPI0_MODULE |CLK_CLKSEL2_SPI0SEL_PCLK1 | x | |SPI1_MODULE |CLK_CLKSEL2_SPI1SEL_HXT | x | |SPI1_MODULE |CLK_CLKSEL2_SPI1SEL_PLL | x | |SPI1_MODULE |CLK_CLKSEL2_SPI1SEL_HIRC | x | |SPI1_MODULE |CLK_CLKSEL2_SPI1SEL_PCLK0 | x | |BPWM0_MODULE |CLK_CLKSEL2_BPWM0SEL_PLL | x | |BPWM0_MODULE |CLK_CLKSEL2_BPWM0SEL_PCLK0 | x | |BPWM1_MODULE |CLK_CLKSEL2_BPWM1SEL_PLL | x | |BPWM1_MODULE |CLK_CLKSEL2_BPWM1SEL_PCLK1 | x | |SPI2_MODULE |CLK_CLKSEL2_SPI2SEL_HXT | x | |SPI2_MODULE |CLK_CLKSEL2_SPI2SEL_PLL | x | |SPI2_MODULE |CLK_CLKSEL2_SPI2SEL_HIRC | x | |SPI2_MODULE |CLK_CLKSEL2_SPI2SEL_PCLK1 | x | |SPI3_MODULE |CLK_CLKSEL2_SPI3SEL_HXT | x | |SPI3_MODULE |CLK_CLKSEL2_SPI3SEL_PLL | x | |SPI3_MODULE |CLK_CLKSEL2_SPI3SEL_HIRC | x | |SPI3_MODULE |CLK_CLKSEL2_SPI3SEL_PCLK0 | x | |SC0_MODULE |CLK_CLKSEL3_SC0SEL_HXT |CLK_CLKDIV1_SC0(x) | |SC0_MODULE |CLK_CLKSEL3_SC0SEL_PLL |CLK_CLKDIV1_SC0(x) | |SC0_MODULE |CLK_CLKSEL3_SC0SEL_HIRC |CLK_CLKDIV1_SC0(x) | |SC0_MODULE |CLK_CLKSEL3_SC0SEL_PCLK0 |CLK_CLKDIV1_SC0(x) | |SC1_MODULE |CLK_CLKSEL3_SC1SEL_HXT |CLK_CLKDIV1_SC1(x) | |SC1_MODULE |CLK_CLKSEL3_SC1SEL_PLL |CLK_CLKDIV1_SC1(x) | |SC1_MODULE |CLK_CLKSEL3_SC1SEL_HIRC |CLK_CLKDIV1_SC1(x) | |SC1_MODULE |CLK_CLKSEL3_SC1SEL_PCLK1 |CLK_CLKDIV1_SC1(x) | |SC2_MODULE |CLK_CLKSEL3_SC2SEL_HXT |CLK_CLKDIV1_SC2(x) | |SC2_MODULE |CLK_CLKSEL3_SC2SEL_PLL |CLK_CLKDIV1_SC2(x) | |SC2_MODULE |CLK_CLKSEL3_SC2SEL_HIRC |CLK_CLKDIV1_SC2(x) | |SC2_MODULE |CLK_CLKSEL3_SC2SEL_PCLK0 |CLK_CLKDIV1_SC2(x) | |RTC_MODULE |CLK_CLKSEL3_RTCSEL_LXT | x | |RTC_MODULE |CLK_CLKSEL3_RTCSEL_LIRC | x | |I2S0_MODULE |CLK_CLKSEL3_I2S0SEL_HXT | x | |I2S0_MODULE |CLK_CLKSEL3_I2S0SEL_PLL | x | |I2S0_MODULE |CLK_CLKSEL3_I2S0SEL_HIRC | x | |UART2_MODULE |CLK_CLKSEL3_UART2SEL_HXT |CLK_CLKDIV4_UART2(x) | |UART2_MODULE |CLK_CLKSEL3_UART2SEL_LXT |CLK_CLKDIV4_UART2(x) | |UART2_MODULE |CLK_CLKSEL3_UART2SEL_PLL |CLK_CLKDIV4_UART2(x) | |UART2_MODULE |CLK_CLKSEL3_UART2SEL_HIRC |CLK_CLKDIV4_UART2(x) | |UART3_MODULE |CLK_CLKSEL3_UART3SEL_HXT |CLK_CLKDIV4_UART3(x) | |UART3_MODULE |CLK_CLKSEL3_UART3SEL_LXT |CLK_CLKDIV4_UART3(x) | |UART3_MODULE |CLK_CLKSEL3_UART3SEL_PLL |CLK_CLKDIV4_UART3(x) | |UART3_MODULE |CLK_CLKSEL3_UART3SEL_HIRC |CLK_CLKDIV4_UART3(x) | |UART4_MODULE |CLK_CLKSEL3_UART4SEL_HXT |CLK_CLKDIV4_UART4(x) | |UART4_MODULE |CLK_CLKSEL3_UART4SEL_LXT |CLK_CLKDIV4_UART4(x) | |UART4_MODULE |CLK_CLKSEL3_UART4SEL_PLL |CLK_CLKDIV4_UART4(x) | |UART4_MODULE |CLK_CLKSEL3_UART4SEL_HIRC |CLK_CLKDIV4_UART4(x) | |UART5_MODULE |CLK_CLKSEL3_UART5SEL_HXT |CLK_CLKDIV4_UART5(x) | |UART5_MODULE |CLK_CLKSEL3_UART5SEL_LXT |CLK_CLKDIV4_UART5(x) | |UART5_MODULE |CLK_CLKSEL3_UART5SEL_PLL |CLK_CLKDIV4_UART5(x) | |UART5_MODULE |CLK_CLKSEL3_UART5SEL_HIRC |CLK_CLKDIV4_UART5(x) | |EADC_MODULE | x |CLK_CLKDIV0_EADC(x) | |EMAC_MODULE | x |CLK_CLKDIV3_EMAC(x) |

Definition at line 457 of file m480_clk.c.

void CLK_SetPowerDownMode ( uint32_t  u32PDMode )

Power-down mode selected.

Parameters:
[in]u32PDModeis power down mode index. Including :

  • CLK_PMUCTL_PDMSEL_PD
  • CLK_PMUCTL_PDMSEL_LLPD
  • CLK_PMUCTL_PDMSEL_FWPD
  • CLK_PMUCTL_PDMSEL_SPD0
  • CLK_PMUCTL_PDMSEL_SPD1
  • CLK_PMUCTL_PDMSEL_DPD
Returns:
None

This function is used to set power-down mode.

Note:
Must enable LIRC clock before entering to Standby Power-down Mode

Definition at line 900 of file m480_clk.c.

void CLK_SetSysTickClockSrc ( uint32_t  u32ClkSrc )

Set SysTick clock source.

Parameters:
[in]u32ClkSrcis module clock source. Including:

  • CLK_CLKSEL0_STCLKSEL_HXT
  • CLK_CLKSEL0_STCLKSEL_LXT
  • CLK_CLKSEL0_STCLKSEL_HXT_DIV2
  • CLK_CLKSEL0_STCLKSEL_HCLK_DIV2
  • CLK_CLKSEL0_STCLKSEL_HIRC_DIV2
Returns:
None

This function set SysTick clock source.
The register write-protection function should be disabled before using this function.

Definition at line 495 of file m480_clk.c.

__STATIC_INLINE void CLK_SysTickDelay ( uint32_t  us )

This function execute delay function.

Parameters:
[in]usDelay time. The Max value is 2^24 / CPU Clock(MHz). Ex: 72MHz => 233016us, 50MHz => 335544us, 48MHz => 349525us, 28MHz => 699050us ...
Returns:
None

Use the SysTick to generate the delay time and the unit is in us. The SysTick clock source is from HCLK, i.e the same as system core clock.

Definition at line 536 of file m480_clk.h.

__STATIC_INLINE void CLK_SysTickLongDelay ( uint32_t  us )

This function execute long delay function.

Parameters:
[in]usDelay time.
Returns:
None

Use the SysTick to generate the long delay time and the UNIT is in us. The SysTick clock source is from HCLK, i.e the same as system core clock. User can use SystemCoreClockUpdate() to calculate CyclesPerUs automatically before using this function.

Definition at line 558 of file m480_clk.h.

uint32_t CLK_WaitClockReady ( uint32_t  u32ClkMask )

This function check selected clock source status.

Parameters:
[in]u32ClkMaskis selected clock source. Including :

  • CLK_STATUS_HXTSTB_Msk
  • CLK_STATUS_LXTSTB_Msk
  • CLK_STATUS_HIRCSTB_Msk
  • CLK_STATUS_LIRCSTB_Msk
  • CLK_STATUS_PLLSTB_Msk
Return values:
0clock is not stable
1clock is stable

To wait for clock ready by specified clock source stable flag or timeout (~300ms)

Definition at line 824 of file m480_clk.c.

Generated on Tue Jul 12 2022 15:37:34 by  doxygen 1.7.2