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stm32f103xb.h
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00001 /** 00002 ****************************************************************************** 00003 * @file stm32f103xb.h 00004 * @author MCD Application Team 00005 * @version V4.1.0 00006 * @date 29-April-2016 00007 * @brief CMSIS Cortex-M3 Device Peripheral Access Layer Header File. 00008 * This file contains all the peripheral register's definitions, bits 00009 * definitions and memory mapping for STM32F1xx devices. 00010 * 00011 * This file contains: 00012 * - Data structures and the address mapping for all peripherals 00013 * - Peripheral's registers declarations and bits definition 00014 * - Macros to access peripheral.s registers hardware 00015 * 00016 ****************************************************************************** 00017 * @attention 00018 * 00019 * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2> 00020 * 00021 * Redistribution and use in source and binary forms, with or without modification, 00022 * are permitted provided that the following conditions are met: 00023 * 1. Redistributions of source code must retain the above copyright notice, 00024 * this list of conditions and the following disclaimer. 00025 * 2. Redistributions in binary form must reproduce the above copyright notice, 00026 * this list of conditions and the following disclaimer in the documentation 00027 * and/or other materials provided with the distribution. 00028 * 3. Neither the name of STMicroelectronics nor the names of its contributors 00029 * may be used to endorse or promote products derived from this software 00030 * without specific prior written permission. 00031 * 00032 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 00033 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 00034 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 00035 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE 00036 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 00037 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 00038 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER 00039 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 00040 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 00041 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 00042 * 00043 ****************************************************************************** 00044 */ 00045 00046 00047 /** @addtogroup CMSIS 00048 * @{ 00049 */ 00050 00051 /** @addtogroup stm32f103xb 00052 * @{ 00053 */ 00054 00055 #ifndef __STM32F103xB_H 00056 #define __STM32F103xB_H 00057 00058 #ifdef __cplusplus 00059 extern "C" { 00060 #endif 00061 00062 /** @addtogroup Configuration_section_for_CMSIS 00063 * @{ 00064 */ 00065 /** 00066 * @brief Configuration of the Cortex-M3 Processor and Core Peripherals 00067 */ 00068 #define __MPU_PRESENT 0 /*!< Other STM32 devices does not provide an MPU */ 00069 #define __CM3_REV 0x0200 /*!< Core Revision r2p0 */ 00070 #define __NVIC_PRIO_BITS 4 /*!< STM32 uses 4 Bits for the Priority Levels */ 00071 #define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ 00072 00073 /** 00074 * @} 00075 */ 00076 00077 /** @addtogroup Peripheral_interrupt_number_definition 00078 * @{ 00079 */ 00080 00081 /** 00082 * @brief STM32F10x Interrupt Number Definition, according to the selected device 00083 * in @ref Library_configuration_section 00084 */ 00085 00086 /*!< Interrupt Number Definition */ 00087 typedef enum 00088 { 00089 /****** Cortex-M3 Processor Exceptions Numbers ***************************************************/ 00090 NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */ 00091 HardFault_IRQn = -13, /*!< 3 Cortex-M3 Hard Fault Interrupt */ 00092 MemoryManagement_IRQn = -12, /*!< 4 Cortex-M3 Memory Management Interrupt */ 00093 BusFault_IRQn = -11, /*!< 5 Cortex-M3 Bus Fault Interrupt */ 00094 UsageFault_IRQn = -10, /*!< 6 Cortex-M3 Usage Fault Interrupt */ 00095 SVCall_IRQn = -5, /*!< 11 Cortex-M3 SV Call Interrupt */ 00096 DebugMonitor_IRQn = -4, /*!< 12 Cortex-M3 Debug Monitor Interrupt */ 00097 PendSV_IRQn = -2, /*!< 14 Cortex-M3 Pend SV Interrupt */ 00098 SysTick_IRQn = -1, /*!< 15 Cortex-M3 System Tick Interrupt */ 00099 00100 /****** STM32 specific Interrupt Numbers *********************************************************/ 00101 WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */ 00102 PVD_IRQn = 1, /*!< PVD through EXTI Line detection Interrupt */ 00103 TAMPER_IRQn = 2, /*!< Tamper Interrupt */ 00104 RTC_IRQn = 3, /*!< RTC global Interrupt */ 00105 FLASH_IRQn = 4, /*!< FLASH global Interrupt */ 00106 RCC_IRQn = 5, /*!< RCC global Interrupt */ 00107 EXTI0_IRQn = 6, /*!< EXTI Line0 Interrupt */ 00108 EXTI1_IRQn = 7, /*!< EXTI Line1 Interrupt */ 00109 EXTI2_IRQn = 8, /*!< EXTI Line2 Interrupt */ 00110 EXTI3_IRQn = 9, /*!< EXTI Line3 Interrupt */ 00111 EXTI4_IRQn = 10, /*!< EXTI Line4 Interrupt */ 00112 DMA1_Channel1_IRQn = 11, /*!< DMA1 Channel 1 global Interrupt */ 00113 DMA1_Channel2_IRQn = 12, /*!< DMA1 Channel 2 global Interrupt */ 00114 DMA1_Channel3_IRQn = 13, /*!< DMA1 Channel 3 global Interrupt */ 00115 DMA1_Channel4_IRQn = 14, /*!< DMA1 Channel 4 global Interrupt */ 00116 DMA1_Channel5_IRQn = 15, /*!< DMA1 Channel 5 global Interrupt */ 00117 DMA1_Channel6_IRQn = 16, /*!< DMA1 Channel 6 global Interrupt */ 00118 DMA1_Channel7_IRQn = 17, /*!< DMA1 Channel 7 global Interrupt */ 00119 ADC1_2_IRQn = 18, /*!< ADC1 and ADC2 global Interrupt */ 00120 USB_HP_CAN1_TX_IRQn = 19, /*!< USB Device High Priority or CAN1 TX Interrupts */ 00121 USB_LP_CAN1_RX0_IRQn = 20, /*!< USB Device Low Priority or CAN1 RX0 Interrupts */ 00122 CAN1_RX1_IRQn = 21, /*!< CAN1 RX1 Interrupt */ 00123 CAN1_SCE_IRQn = 22, /*!< CAN1 SCE Interrupt */ 00124 EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */ 00125 TIM1_BRK_IRQn = 24, /*!< TIM1 Break Interrupt */ 00126 TIM1_UP_IRQn = 25, /*!< TIM1 Update Interrupt */ 00127 TIM1_TRG_COM_IRQn = 26, /*!< TIM1 Trigger and Commutation Interrupt */ 00128 TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */ 00129 TIM2_IRQn = 28, /*!< TIM2 global Interrupt */ 00130 TIM3_IRQn = 29, /*!< TIM3 global Interrupt */ 00131 TIM4_IRQn = 30, /*!< TIM4 global Interrupt */ 00132 I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */ 00133 I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */ 00134 I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */ 00135 I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */ 00136 SPI1_IRQn = 35, /*!< SPI1 global Interrupt */ 00137 SPI2_IRQn = 36, /*!< SPI2 global Interrupt */ 00138 USART1_IRQn = 37, /*!< USART1 global Interrupt */ 00139 USART2_IRQn = 38, /*!< USART2 global Interrupt */ 00140 USART3_IRQn = 39, /*!< USART3 global Interrupt */ 00141 EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */ 00142 RTC_Alarm_IRQn = 41, /*!< RTC Alarm through EXTI Line Interrupt */ 00143 USBWakeUp_IRQn = 42, /*!< USB Device WakeUp from suspend through EXTI Line Interrupt */ 00144 } IRQn_Type ; 00145 00146 00147 /** 00148 * @} 00149 */ 00150 00151 #include "core_cm3.h" 00152 #include "system_stm32f1xx.h" 00153 #include <stdint.h> 00154 00155 /** @addtogroup Peripheral_registers_structures 00156 * @{ 00157 */ 00158 00159 /** 00160 * @brief Analog to Digital Converter 00161 */ 00162 00163 typedef struct 00164 { 00165 __IO uint32_t SR; 00166 __IO uint32_t CR1; 00167 __IO uint32_t CR2; 00168 __IO uint32_t SMPR1; 00169 __IO uint32_t SMPR2; 00170 __IO uint32_t JOFR1; 00171 __IO uint32_t JOFR2; 00172 __IO uint32_t JOFR3; 00173 __IO uint32_t JOFR4; 00174 __IO uint32_t HTR; 00175 __IO uint32_t LTR; 00176 __IO uint32_t SQR1; 00177 __IO uint32_t SQR2; 00178 __IO uint32_t SQR3; 00179 __IO uint32_t JSQR; 00180 __IO uint32_t JDR1; 00181 __IO uint32_t JDR2; 00182 __IO uint32_t JDR3; 00183 __IO uint32_t JDR4; 00184 __IO uint32_t DR; 00185 } ADC_TypeDef; 00186 00187 typedef struct 00188 { 00189 __IO uint32_t SR; /*!< ADC status register, used for ADC multimode (bits common to several ADC instances). Address offset: ADC1 base address */ 00190 __IO uint32_t CR1; /*!< ADC control register 1, used for ADC multimode (bits common to several ADC instances). Address offset: ADC1 base address + 0x04 */ 00191 __IO uint32_t CR2; /*!< ADC control register 2, used for ADC multimode (bits common to several ADC instances). Address offset: ADC1 base address + 0x08 */ 00192 uint32_t RESERVED[16]; 00193 __IO uint32_t DR; /*!< ADC data register, used for ADC multimode (bits common to several ADC instances). Address offset: ADC1 base address + 0x4C */ 00194 } ADC_Common_TypeDef; 00195 00196 /** 00197 * @brief Backup Registers 00198 */ 00199 00200 typedef struct 00201 { 00202 uint32_t RESERVED0; 00203 __IO uint32_t DR1; 00204 __IO uint32_t DR2; 00205 __IO uint32_t DR3; 00206 __IO uint32_t DR4; 00207 __IO uint32_t DR5; 00208 __IO uint32_t DR6; 00209 __IO uint32_t DR7; 00210 __IO uint32_t DR8; 00211 __IO uint32_t DR9; 00212 __IO uint32_t DR10; 00213 __IO uint32_t RTCCR; 00214 __IO uint32_t CR; 00215 __IO uint32_t CSR; 00216 } BKP_TypeDef; 00217 00218 /** 00219 * @brief Controller Area Network TxMailBox 00220 */ 00221 00222 typedef struct 00223 { 00224 __IO uint32_t TIR; 00225 __IO uint32_t TDTR; 00226 __IO uint32_t TDLR; 00227 __IO uint32_t TDHR; 00228 } CAN_TxMailBox_TypeDef; 00229 00230 /** 00231 * @brief Controller Area Network FIFOMailBox 00232 */ 00233 00234 typedef struct 00235 { 00236 __IO uint32_t RIR; 00237 __IO uint32_t RDTR; 00238 __IO uint32_t RDLR; 00239 __IO uint32_t RDHR; 00240 } CAN_FIFOMailBox_TypeDef; 00241 00242 /** 00243 * @brief Controller Area Network FilterRegister 00244 */ 00245 00246 typedef struct 00247 { 00248 __IO uint32_t FR1; 00249 __IO uint32_t FR2; 00250 } CAN_FilterRegister_TypeDef; 00251 00252 /** 00253 * @brief Controller Area Network 00254 */ 00255 00256 typedef struct 00257 { 00258 __IO uint32_t MCR; 00259 __IO uint32_t MSR; 00260 __IO uint32_t TSR; 00261 __IO uint32_t RF0R; 00262 __IO uint32_t RF1R; 00263 __IO uint32_t IER; 00264 __IO uint32_t ESR; 00265 __IO uint32_t BTR; 00266 uint32_t RESERVED0[88]; 00267 CAN_TxMailBox_TypeDef sTxMailBox[3]; 00268 CAN_FIFOMailBox_TypeDef sFIFOMailBox[2]; 00269 uint32_t RESERVED1[12]; 00270 __IO uint32_t FMR; 00271 __IO uint32_t FM1R; 00272 uint32_t RESERVED2; 00273 __IO uint32_t FS1R; 00274 uint32_t RESERVED3; 00275 __IO uint32_t FFA1R; 00276 uint32_t RESERVED4; 00277 __IO uint32_t FA1R; 00278 uint32_t RESERVED5[8]; 00279 CAN_FilterRegister_TypeDef sFilterRegister[14]; 00280 } CAN_TypeDef; 00281 00282 /** 00283 * @brief CRC calculation unit 00284 */ 00285 00286 typedef struct 00287 { 00288 __IO uint32_t DR ; /*!< CRC Data register, Address offset: 0x00 */ 00289 __IO uint8_t IDR ; /*!< CRC Independent data register, Address offset: 0x04 */ 00290 uint8_t RESERVED0 ; /*!< Reserved, Address offset: 0x05 */ 00291 uint16_t RESERVED1 ; /*!< Reserved, Address offset: 0x06 */ 00292 __IO uint32_t CR ; /*!< CRC Control register, Address offset: 0x08 */ 00293 } CRC_TypeDef; 00294 00295 00296 /** 00297 * @brief Debug MCU 00298 */ 00299 00300 typedef struct 00301 { 00302 __IO uint32_t IDCODE; 00303 __IO uint32_t CR; 00304 }DBGMCU_TypeDef; 00305 00306 /** 00307 * @brief DMA Controller 00308 */ 00309 00310 typedef struct 00311 { 00312 __IO uint32_t CCR; 00313 __IO uint32_t CNDTR; 00314 __IO uint32_t CPAR; 00315 __IO uint32_t CMAR; 00316 } DMA_Channel_TypeDef; 00317 00318 typedef struct 00319 { 00320 __IO uint32_t ISR; 00321 __IO uint32_t IFCR; 00322 } DMA_TypeDef; 00323 00324 00325 00326 /** 00327 * @brief External Interrupt/Event Controller 00328 */ 00329 00330 typedef struct 00331 { 00332 __IO uint32_t IMR; 00333 __IO uint32_t EMR; 00334 __IO uint32_t RTSR; 00335 __IO uint32_t FTSR; 00336 __IO uint32_t SWIER; 00337 __IO uint32_t PR; 00338 } EXTI_TypeDef; 00339 00340 /** 00341 * @brief FLASH Registers 00342 */ 00343 00344 typedef struct 00345 { 00346 __IO uint32_t ACR; 00347 __IO uint32_t KEYR; 00348 __IO uint32_t OPTKEYR; 00349 __IO uint32_t SR; 00350 __IO uint32_t CR; 00351 __IO uint32_t AR; 00352 __IO uint32_t RESERVED; 00353 __IO uint32_t OBR; 00354 __IO uint32_t WRPR; 00355 } FLASH_TypeDef; 00356 00357 /** 00358 * @brief Option Bytes Registers 00359 */ 00360 00361 typedef struct 00362 { 00363 __IO uint16_t RDP; 00364 __IO uint16_t USER; 00365 __IO uint16_t Data0; 00366 __IO uint16_t Data1; 00367 __IO uint16_t WRP0; 00368 __IO uint16_t WRP1; 00369 __IO uint16_t WRP2; 00370 __IO uint16_t WRP3; 00371 } OB_TypeDef; 00372 00373 /** 00374 * @brief General Purpose I/O 00375 */ 00376 00377 typedef struct 00378 { 00379 __IO uint32_t CRL; 00380 __IO uint32_t CRH; 00381 __IO uint32_t IDR; 00382 __IO uint32_t ODR; 00383 __IO uint32_t BSRR; 00384 __IO uint32_t BRR; 00385 __IO uint32_t LCKR; 00386 } GPIO_TypeDef; 00387 00388 /** 00389 * @brief Alternate Function I/O 00390 */ 00391 00392 typedef struct 00393 { 00394 __IO uint32_t EVCR; 00395 __IO uint32_t MAPR; 00396 __IO uint32_t EXTICR[4]; 00397 uint32_t RESERVED0; 00398 __IO uint32_t MAPR2; 00399 } AFIO_TypeDef; 00400 /** 00401 * @brief Inter Integrated Circuit Interface 00402 */ 00403 00404 typedef struct 00405 { 00406 __IO uint32_t CR1; 00407 __IO uint32_t CR2; 00408 __IO uint32_t OAR1; 00409 __IO uint32_t OAR2; 00410 __IO uint32_t DR; 00411 __IO uint32_t SR1; 00412 __IO uint32_t SR2; 00413 __IO uint32_t CCR; 00414 __IO uint32_t TRISE; 00415 } I2C_TypeDef; 00416 00417 /** 00418 * @brief Independent WATCHDOG 00419 */ 00420 00421 typedef struct 00422 { 00423 __IO uint32_t KR ; /*!< Key register, Address offset: 0x00 */ 00424 __IO uint32_t PR ; /*!< Prescaler register, Address offset: 0x04 */ 00425 __IO uint32_t RLR ; /*!< Reload register, Address offset: 0x08 */ 00426 __IO uint32_t SR ; /*!< Status register, Address offset: 0x0C */ 00427 } IWDG_TypeDef; 00428 00429 /** 00430 * @brief Power Control 00431 */ 00432 00433 typedef struct 00434 { 00435 __IO uint32_t CR; 00436 __IO uint32_t CSR; 00437 } PWR_TypeDef; 00438 00439 /** 00440 * @brief Reset and Clock Control 00441 */ 00442 00443 typedef struct 00444 { 00445 __IO uint32_t CR; 00446 __IO uint32_t CFGR; 00447 __IO uint32_t CIR; 00448 __IO uint32_t APB2RSTR; 00449 __IO uint32_t APB1RSTR; 00450 __IO uint32_t AHBENR; 00451 __IO uint32_t APB2ENR; 00452 __IO uint32_t APB1ENR; 00453 __IO uint32_t BDCR; 00454 __IO uint32_t CSR; 00455 00456 00457 } RCC_TypeDef; 00458 00459 /** 00460 * @brief Real-Time Clock 00461 */ 00462 00463 typedef struct 00464 { 00465 __IO uint32_t CRH; 00466 __IO uint32_t CRL; 00467 __IO uint32_t PRLH; 00468 __IO uint32_t PRLL; 00469 __IO uint32_t DIVH; 00470 __IO uint32_t DIVL; 00471 __IO uint32_t CNTH; 00472 __IO uint32_t CNTL; 00473 __IO uint32_t ALRH; 00474 __IO uint32_t ALRL; 00475 } RTC_TypeDef; 00476 00477 /** 00478 * @brief SD host Interface 00479 */ 00480 00481 typedef struct 00482 { 00483 __IO uint32_t POWER; 00484 __IO uint32_t CLKCR; 00485 __IO uint32_t ARG; 00486 __IO uint32_t CMD; 00487 __I uint32_t RESPCMD; 00488 __I uint32_t RESP1; 00489 __I uint32_t RESP2; 00490 __I uint32_t RESP3; 00491 __I uint32_t RESP4; 00492 __IO uint32_t DTIMER; 00493 __IO uint32_t DLEN; 00494 __IO uint32_t DCTRL; 00495 __I uint32_t DCOUNT; 00496 __I uint32_t STA; 00497 __IO uint32_t ICR; 00498 __IO uint32_t MASK; 00499 uint32_t RESERVED0[2]; 00500 __I uint32_t FIFOCNT; 00501 uint32_t RESERVED1[13]; 00502 __IO uint32_t FIFO; 00503 } SDIO_TypeDef; 00504 00505 /** 00506 * @brief Serial Peripheral Interface 00507 */ 00508 00509 typedef struct 00510 { 00511 __IO uint32_t CR1; 00512 __IO uint32_t CR2; 00513 __IO uint32_t SR; 00514 __IO uint32_t DR; 00515 __IO uint32_t CRCPR; 00516 __IO uint32_t RXCRCR; 00517 __IO uint32_t TXCRCR; 00518 __IO uint32_t I2SCFGR; 00519 } SPI_TypeDef; 00520 00521 /** 00522 * @brief TIM Timers 00523 */ 00524 typedef struct 00525 { 00526 __IO uint32_t CR1 ; /*!< TIM control register 1, Address offset: 0x00 */ 00527 __IO uint32_t CR2 ; /*!< TIM control register 2, Address offset: 0x04 */ 00528 __IO uint32_t SMCR ; /*!< TIM slave Mode Control register, Address offset: 0x08 */ 00529 __IO uint32_t DIER ; /*!< TIM DMA/interrupt enable register, Address offset: 0x0C */ 00530 __IO uint32_t SR ; /*!< TIM status register, Address offset: 0x10 */ 00531 __IO uint32_t EGR ; /*!< TIM event generation register, Address offset: 0x14 */ 00532 __IO uint32_t CCMR1 ; /*!< TIM capture/compare mode register 1, Address offset: 0x18 */ 00533 __IO uint32_t CCMR2 ; /*!< TIM capture/compare mode register 2, Address offset: 0x1C */ 00534 __IO uint32_t CCER ; /*!< TIM capture/compare enable register, Address offset: 0x20 */ 00535 __IO uint32_t CNT ; /*!< TIM counter register, Address offset: 0x24 */ 00536 __IO uint32_t PSC ; /*!< TIM prescaler register, Address offset: 0x28 */ 00537 __IO uint32_t ARR ; /*!< TIM auto-reload register, Address offset: 0x2C */ 00538 __IO uint32_t RCR ; /*!< TIM repetition counter register, Address offset: 0x30 */ 00539 __IO uint32_t CCR1 ; /*!< TIM capture/compare register 1, Address offset: 0x34 */ 00540 __IO uint32_t CCR2 ; /*!< TIM capture/compare register 2, Address offset: 0x38 */ 00541 __IO uint32_t CCR3 ; /*!< TIM capture/compare register 3, Address offset: 0x3C */ 00542 __IO uint32_t CCR4 ; /*!< TIM capture/compare register 4, Address offset: 0x40 */ 00543 __IO uint32_t BDTR ; /*!< TIM break and dead-time register, Address offset: 0x44 */ 00544 __IO uint32_t DCR ; /*!< TIM DMA control register, Address offset: 0x48 */ 00545 __IO uint32_t DMAR ; /*!< TIM DMA address for full transfer register, Address offset: 0x4C */ 00546 __IO uint32_t OR ; /*!< TIM option register, Address offset: 0x50 */ 00547 }TIM_TypeDef; 00548 00549 00550 /** 00551 * @brief Universal Synchronous Asynchronous Receiver Transmitter 00552 */ 00553 00554 typedef struct 00555 { 00556 __IO uint32_t SR ; /*!< USART Status register, Address offset: 0x00 */ 00557 __IO uint32_t DR ; /*!< USART Data register, Address offset: 0x04 */ 00558 __IO uint32_t BRR ; /*!< USART Baud rate register, Address offset: 0x08 */ 00559 __IO uint32_t CR1 ; /*!< USART Control register 1, Address offset: 0x0C */ 00560 __IO uint32_t CR2 ; /*!< USART Control register 2, Address offset: 0x10 */ 00561 __IO uint32_t CR3 ; /*!< USART Control register 3, Address offset: 0x14 */ 00562 __IO uint32_t GTPR ; /*!< USART Guard time and prescaler register, Address offset: 0x18 */ 00563 } USART_TypeDef; 00564 00565 /** 00566 * @brief Universal Serial Bus Full Speed Device 00567 */ 00568 00569 typedef struct 00570 { 00571 __IO uint16_t EP0R ; /*!< USB Endpoint 0 register, Address offset: 0x00 */ 00572 __IO uint16_t RESERVED0 ; /*!< Reserved */ 00573 __IO uint16_t EP1R ; /*!< USB Endpoint 1 register, Address offset: 0x04 */ 00574 __IO uint16_t RESERVED1 ; /*!< Reserved */ 00575 __IO uint16_t EP2R ; /*!< USB Endpoint 2 register, Address offset: 0x08 */ 00576 __IO uint16_t RESERVED2 ; /*!< Reserved */ 00577 __IO uint16_t EP3R ; /*!< USB Endpoint 3 register, Address offset: 0x0C */ 00578 __IO uint16_t RESERVED3 ; /*!< Reserved */ 00579 __IO uint16_t EP4R ; /*!< USB Endpoint 4 register, Address offset: 0x10 */ 00580 __IO uint16_t RESERVED4 ; /*!< Reserved */ 00581 __IO uint16_t EP5R ; /*!< USB Endpoint 5 register, Address offset: 0x14 */ 00582 __IO uint16_t RESERVED5 ; /*!< Reserved */ 00583 __IO uint16_t EP6R ; /*!< USB Endpoint 6 register, Address offset: 0x18 */ 00584 __IO uint16_t RESERVED6 ; /*!< Reserved */ 00585 __IO uint16_t EP7R ; /*!< USB Endpoint 7 register, Address offset: 0x1C */ 00586 __IO uint16_t RESERVED7[17]; /*!< Reserved */ 00587 __IO uint16_t CNTR ; /*!< Control register, Address offset: 0x40 */ 00588 __IO uint16_t RESERVED8 ; /*!< Reserved */ 00589 __IO uint16_t ISTR ; /*!< Interrupt status register, Address offset: 0x44 */ 00590 __IO uint16_t RESERVED9 ; /*!< Reserved */ 00591 __IO uint16_t FNR ; /*!< Frame number register, Address offset: 0x48 */ 00592 __IO uint16_t RESERVEDA ; /*!< Reserved */ 00593 __IO uint16_t DADDR ; /*!< Device address register, Address offset: 0x4C */ 00594 __IO uint16_t RESERVEDB ; /*!< Reserved */ 00595 __IO uint16_t BTABLE ; /*!< Buffer Table address register, Address offset: 0x50 */ 00596 __IO uint16_t RESERVEDC ; /*!< Reserved */ 00597 } USB_TypeDef; 00598 00599 00600 /** 00601 * @brief Window WATCHDOG 00602 */ 00603 00604 typedef struct 00605 { 00606 __IO uint32_t CR ; /*!< WWDG Control register, Address offset: 0x00 */ 00607 __IO uint32_t CFR ; /*!< WWDG Configuration register, Address offset: 0x04 */ 00608 __IO uint32_t SR ; /*!< WWDG Status register, Address offset: 0x08 */ 00609 } WWDG_TypeDef; 00610 00611 /** 00612 * @} 00613 */ 00614 00615 /** @addtogroup Peripheral_memory_map 00616 * @{ 00617 */ 00618 00619 00620 #define FLASH_BASE ((uint32_t)0x08000000) /*!< FLASH base address in the alias region */ 00621 #define FLASH_BANK1_END ((uint32_t)0x0801FFFF) /*!< FLASH END address of bank1 */ 00622 #define SRAM_BASE ((uint32_t)0x20000000) /*!< SRAM base address in the alias region */ 00623 #define PERIPH_BASE ((uint32_t)0x40000000) /*!< Peripheral base address in the alias region */ 00624 00625 #define SRAM_BB_BASE ((uint32_t)0x22000000) /*!< SRAM base address in the bit-band region */ 00626 #define PERIPH_BB_BASE ((uint32_t)0x42000000) /*!< Peripheral base address in the bit-band region */ 00627 00628 00629 /*!< Peripheral memory map */ 00630 #define APB1PERIPH_BASE PERIPH_BASE 00631 #define APB2PERIPH_BASE (PERIPH_BASE + 0x10000) 00632 #define AHBPERIPH_BASE (PERIPH_BASE + 0x20000) 00633 00634 #define TIM2_BASE (APB1PERIPH_BASE + 0x0000) 00635 #define TIM3_BASE (APB1PERIPH_BASE + 0x0400) 00636 #define TIM4_BASE (APB1PERIPH_BASE + 0x0800) 00637 #define RTC_BASE (APB1PERIPH_BASE + 0x2800) 00638 #define WWDG_BASE (APB1PERIPH_BASE + 0x2C00) 00639 #define IWDG_BASE (APB1PERIPH_BASE + 0x3000) 00640 #define SPI2_BASE (APB1PERIPH_BASE + 0x3800) 00641 #define USART2_BASE (APB1PERIPH_BASE + 0x4400) 00642 #define USART3_BASE (APB1PERIPH_BASE + 0x4800) 00643 #define I2C1_BASE (APB1PERIPH_BASE + 0x5400) 00644 #define I2C2_BASE (APB1PERIPH_BASE + 0x5800) 00645 #define CAN1_BASE (APB1PERIPH_BASE + 0x6400) 00646 #define BKP_BASE (APB1PERIPH_BASE + 0x6C00) 00647 #define PWR_BASE (APB1PERIPH_BASE + 0x7000) 00648 #define AFIO_BASE (APB2PERIPH_BASE + 0x0000) 00649 #define EXTI_BASE (APB2PERIPH_BASE + 0x0400) 00650 #define GPIOA_BASE (APB2PERIPH_BASE + 0x0800) 00651 #define GPIOB_BASE (APB2PERIPH_BASE + 0x0C00) 00652 #define GPIOC_BASE (APB2PERIPH_BASE + 0x1000) 00653 #define GPIOD_BASE (APB2PERIPH_BASE + 0x1400) 00654 #define GPIOE_BASE (APB2PERIPH_BASE + 0x1800) 00655 #define ADC1_BASE (APB2PERIPH_BASE + 0x2400) 00656 #define ADC2_BASE (APB2PERIPH_BASE + 0x2800) 00657 #define TIM1_BASE (APB2PERIPH_BASE + 0x2C00) 00658 #define SPI1_BASE (APB2PERIPH_BASE + 0x3000) 00659 #define USART1_BASE (APB2PERIPH_BASE + 0x3800) 00660 00661 #define SDIO_BASE (PERIPH_BASE + 0x18000) 00662 00663 #define DMA1_BASE (AHBPERIPH_BASE + 0x0000) 00664 #define DMA1_Channel1_BASE (AHBPERIPH_BASE + 0x0008) 00665 #define DMA1_Channel2_BASE (AHBPERIPH_BASE + 0x001C) 00666 #define DMA1_Channel3_BASE (AHBPERIPH_BASE + 0x0030) 00667 #define DMA1_Channel4_BASE (AHBPERIPH_BASE + 0x0044) 00668 #define DMA1_Channel5_BASE (AHBPERIPH_BASE + 0x0058) 00669 #define DMA1_Channel6_BASE (AHBPERIPH_BASE + 0x006C) 00670 #define DMA1_Channel7_BASE (AHBPERIPH_BASE + 0x0080) 00671 #define RCC_BASE (AHBPERIPH_BASE + 0x1000) 00672 #define CRC_BASE (AHBPERIPH_BASE + 0x3000) 00673 00674 #define FLASH_R_BASE (AHBPERIPH_BASE + 0x2000) /*!< Flash registers base address */ 00675 #define FLASHSIZE_BASE ((uint32_t)0x1FFFF7E0) /*!< FLASH Size register base address */ 00676 #define UID_BASE ((uint32_t)0x1FFFF7E8) /*!< Unique device ID register base address */ 00677 #define OB_BASE ((uint32_t)0x1FFFF800) /*!< Flash Option Bytes base address */ 00678 00679 00680 00681 #define DBGMCU_BASE ((uint32_t)0xE0042000) /*!< Debug MCU registers base address */ 00682 00683 /* USB device FS */ 00684 #define USB_BASE (APB1PERIPH_BASE + 0x00005C00) /*!< USB_IP Peripheral Registers base address */ 00685 #define USB_PMAADDR (APB1PERIPH_BASE + 0x00006000) /*!< USB_IP Packet Memory Area base address */ 00686 00687 00688 /** 00689 * @} 00690 */ 00691 00692 /** @addtogroup Peripheral_declaration 00693 * @{ 00694 */ 00695 00696 #define TIM2 ((TIM_TypeDef *) TIM2_BASE) 00697 #define TIM3 ((TIM_TypeDef *) TIM3_BASE) 00698 #define TIM4 ((TIM_TypeDef *) TIM4_BASE) 00699 #define RTC ((RTC_TypeDef *) RTC_BASE) 00700 #define WWDG ((WWDG_TypeDef *) WWDG_BASE) 00701 #define IWDG ((IWDG_TypeDef *) IWDG_BASE) 00702 #define SPI2 ((SPI_TypeDef *) SPI2_BASE) 00703 #define USART2 ((USART_TypeDef *) USART2_BASE) 00704 #define USART3 ((USART_TypeDef *) USART3_BASE) 00705 #define I2C1 ((I2C_TypeDef *) I2C1_BASE) 00706 #define I2C2 ((I2C_TypeDef *) I2C2_BASE) 00707 #define USB ((USB_TypeDef *) USB_BASE) 00708 #define CAN1 ((CAN_TypeDef *) CAN1_BASE) 00709 #define BKP ((BKP_TypeDef *) BKP_BASE) 00710 #define PWR ((PWR_TypeDef *) PWR_BASE) 00711 #define AFIO ((AFIO_TypeDef *) AFIO_BASE) 00712 #define EXTI ((EXTI_TypeDef *) EXTI_BASE) 00713 #define GPIOA ((GPIO_TypeDef *) GPIOA_BASE) 00714 #define GPIOB ((GPIO_TypeDef *) GPIOB_BASE) 00715 #define GPIOC ((GPIO_TypeDef *) GPIOC_BASE) 00716 #define GPIOD ((GPIO_TypeDef *) GPIOD_BASE) 00717 #define GPIOE ((GPIO_TypeDef *) GPIOE_BASE) 00718 #define ADC1 ((ADC_TypeDef *) ADC1_BASE) 00719 #define ADC2 ((ADC_TypeDef *) ADC2_BASE) 00720 #define ADC12_COMMON ((ADC_Common_TypeDef *) ADC1_BASE) 00721 #define TIM1 ((TIM_TypeDef *) TIM1_BASE) 00722 #define SPI1 ((SPI_TypeDef *) SPI1_BASE) 00723 #define USART1 ((USART_TypeDef *) USART1_BASE) 00724 #define SDIO ((SDIO_TypeDef *) SDIO_BASE) 00725 #define DMA1 ((DMA_TypeDef *) DMA1_BASE) 00726 #define DMA1_Channel1 ((DMA_Channel_TypeDef *) DMA1_Channel1_BASE) 00727 #define DMA1_Channel2 ((DMA_Channel_TypeDef *) DMA1_Channel2_BASE) 00728 #define DMA1_Channel3 ((DMA_Channel_TypeDef *) DMA1_Channel3_BASE) 00729 #define DMA1_Channel4 ((DMA_Channel_TypeDef *) DMA1_Channel4_BASE) 00730 #define DMA1_Channel5 ((DMA_Channel_TypeDef *) DMA1_Channel5_BASE) 00731 #define DMA1_Channel6 ((DMA_Channel_TypeDef *) DMA1_Channel6_BASE) 00732 #define DMA1_Channel7 ((DMA_Channel_TypeDef *) DMA1_Channel7_BASE) 00733 #define RCC ((RCC_TypeDef *) RCC_BASE) 00734 #define CRC ((CRC_TypeDef *) CRC_BASE) 00735 #define FLASH ((FLASH_TypeDef *) FLASH_R_BASE) 00736 #define OB ((OB_TypeDef *) OB_BASE) 00737 #define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE) 00738 00739 00740 /** 00741 * @} 00742 */ 00743 00744 /** @addtogroup Exported_constants 00745 * @{ 00746 */ 00747 00748 /** @addtogroup Peripheral_Registers_Bits_Definition 00749 * @{ 00750 */ 00751 00752 /******************************************************************************/ 00753 /* Peripheral Registers_Bits_Definition */ 00754 /******************************************************************************/ 00755 00756 /******************************************************************************/ 00757 /* */ 00758 /* CRC calculation unit (CRC) */ 00759 /* */ 00760 /******************************************************************************/ 00761 00762 /******************* Bit definition for CRC_DR register *********************/ 00763 #define CRC_DR_DR_Pos (0U) 00764 #define CRC_DR_DR_Msk (0xFFFFFFFFU << CRC_DR_DR_Pos) /*!< 0xFFFFFFFF */ 00765 #define CRC_DR_DR CRC_DR_DR_Msk /*!< Data register bits */ 00766 00767 /******************* Bit definition for CRC_IDR register ********************/ 00768 #define CRC_IDR_IDR_Pos (0U) 00769 #define CRC_IDR_IDR_Msk (0xFFU << CRC_IDR_IDR_Pos) /*!< 0x000000FF */ 00770 #define CRC_IDR_IDR CRC_IDR_IDR_Msk /*!< General-purpose 8-bit data register bits */ 00771 00772 /******************** Bit definition for CRC_CR register ********************/ 00773 #define CRC_CR_RESET_Pos (0U) 00774 #define CRC_CR_RESET_Msk (0x1U << CRC_CR_RESET_Pos) /*!< 0x00000001 */ 00775 #define CRC_CR_RESET CRC_CR_RESET_Msk /*!< RESET bit */ 00776 00777 /******************************************************************************/ 00778 /* */ 00779 /* Power Control */ 00780 /* */ 00781 /******************************************************************************/ 00782 00783 /******************** Bit definition for PWR_CR register ********************/ 00784 #define PWR_CR_LPDS_Pos (0U) 00785 #define PWR_CR_LPDS_Msk (0x1U << PWR_CR_LPDS_Pos) /*!< 0x00000001 */ 00786 #define PWR_CR_LPDS PWR_CR_LPDS_Msk /*!< Low-Power Deepsleep */ 00787 #define PWR_CR_PDDS_Pos (1U) 00788 #define PWR_CR_PDDS_Msk (0x1U << PWR_CR_PDDS_Pos) /*!< 0x00000002 */ 00789 #define PWR_CR_PDDS PWR_CR_PDDS_Msk /*!< Power Down Deepsleep */ 00790 #define PWR_CR_CWUF_Pos (2U) 00791 #define PWR_CR_CWUF_Msk (0x1U << PWR_CR_CWUF_Pos) /*!< 0x00000004 */ 00792 #define PWR_CR_CWUF PWR_CR_CWUF_Msk /*!< Clear Wakeup Flag */ 00793 #define PWR_CR_CSBF_Pos (3U) 00794 #define PWR_CR_CSBF_Msk (0x1U << PWR_CR_CSBF_Pos) /*!< 0x00000008 */ 00795 #define PWR_CR_CSBF PWR_CR_CSBF_Msk /*!< Clear Standby Flag */ 00796 #define PWR_CR_PVDE_Pos (4U) 00797 #define PWR_CR_PVDE_Msk (0x1U << PWR_CR_PVDE_Pos) /*!< 0x00000010 */ 00798 #define PWR_CR_PVDE PWR_CR_PVDE_Msk /*!< Power Voltage Detector Enable */ 00799 00800 #define PWR_CR_PLS_Pos (5U) 00801 #define PWR_CR_PLS_Msk (0x7U << PWR_CR_PLS_Pos) /*!< 0x000000E0 */ 00802 #define PWR_CR_PLS PWR_CR_PLS_Msk /*!< PLS[2:0] bits (PVD Level Selection) */ 00803 #define PWR_CR_PLS_0 (0x1U << PWR_CR_PLS_Pos) /*!< 0x00000020 */ 00804 #define PWR_CR_PLS_1 (0x2U << PWR_CR_PLS_Pos) /*!< 0x00000040 */ 00805 #define PWR_CR_PLS_2 (0x4U << PWR_CR_PLS_Pos) /*!< 0x00000080 */ 00806 00807 /*!< PVD level configuration */ 00808 #define PWR_CR_PLS_2V2 ((uint32_t)0x00000000) /*!< PVD level 2.2V */ 00809 #define PWR_CR_PLS_2V3 ((uint32_t)0x00000020) /*!< PVD level 2.3V */ 00810 #define PWR_CR_PLS_2V4 ((uint32_t)0x00000040) /*!< PVD level 2.4V */ 00811 #define PWR_CR_PLS_2V5 ((uint32_t)0x00000060) /*!< PVD level 2.5V */ 00812 #define PWR_CR_PLS_2V6 ((uint32_t)0x00000080) /*!< PVD level 2.6V */ 00813 #define PWR_CR_PLS_2V7 ((uint32_t)0x000000A0) /*!< PVD level 2.7V */ 00814 #define PWR_CR_PLS_2V8 ((uint32_t)0x000000C0) /*!< PVD level 2.8V */ 00815 #define PWR_CR_PLS_2V9 ((uint32_t)0x000000E0) /*!< PVD level 2.9V */ 00816 00817 #define PWR_CR_DBP_Pos (8U) 00818 #define PWR_CR_DBP_Msk (0x1U << PWR_CR_DBP_Pos) /*!< 0x00000100 */ 00819 #define PWR_CR_DBP PWR_CR_DBP_Msk /*!< Disable Backup Domain write protection */ 00820 00821 00822 /******************* Bit definition for PWR_CSR register ********************/ 00823 #define PWR_CSR_WUF_Pos (0U) 00824 #define PWR_CSR_WUF_Msk (0x1U << PWR_CSR_WUF_Pos) /*!< 0x00000001 */ 00825 #define PWR_CSR_WUF PWR_CSR_WUF_Msk /*!< Wakeup Flag */ 00826 #define PWR_CSR_SBF_Pos (1U) 00827 #define PWR_CSR_SBF_Msk (0x1U << PWR_CSR_SBF_Pos) /*!< 0x00000002 */ 00828 #define PWR_CSR_SBF PWR_CSR_SBF_Msk /*!< Standby Flag */ 00829 #define PWR_CSR_PVDO_Pos (2U) 00830 #define PWR_CSR_PVDO_Msk (0x1U << PWR_CSR_PVDO_Pos) /*!< 0x00000004 */ 00831 #define PWR_CSR_PVDO PWR_CSR_PVDO_Msk /*!< PVD Output */ 00832 #define PWR_CSR_EWUP_Pos (8U) 00833 #define PWR_CSR_EWUP_Msk (0x1U << PWR_CSR_EWUP_Pos) /*!< 0x00000100 */ 00834 #define PWR_CSR_EWUP PWR_CSR_EWUP_Msk /*!< Enable WKUP pin */ 00835 00836 /******************************************************************************/ 00837 /* */ 00838 /* Backup registers */ 00839 /* */ 00840 /******************************************************************************/ 00841 00842 /******************* Bit definition for BKP_DR1 register ********************/ 00843 #define BKP_DR1_D_Pos (0U) 00844 #define BKP_DR1_D_Msk (0xFFFFU << BKP_DR1_D_Pos) /*!< 0x0000FFFF */ 00845 #define BKP_DR1_D BKP_DR1_D_Msk /*!< Backup data */ 00846 00847 /******************* Bit definition for BKP_DR2 register ********************/ 00848 #define BKP_DR2_D_Pos (0U) 00849 #define BKP_DR2_D_Msk (0xFFFFU << BKP_DR2_D_Pos) /*!< 0x0000FFFF */ 00850 #define BKP_DR2_D BKP_DR2_D_Msk /*!< Backup data */ 00851 00852 /******************* Bit definition for BKP_DR3 register ********************/ 00853 #define BKP_DR3_D_Pos (0U) 00854 #define BKP_DR3_D_Msk (0xFFFFU << BKP_DR3_D_Pos) /*!< 0x0000FFFF */ 00855 #define BKP_DR3_D BKP_DR3_D_Msk /*!< Backup data */ 00856 00857 /******************* Bit definition for BKP_DR4 register ********************/ 00858 #define BKP_DR4_D_Pos (0U) 00859 #define BKP_DR4_D_Msk (0xFFFFU << BKP_DR4_D_Pos) /*!< 0x0000FFFF */ 00860 #define BKP_DR4_D BKP_DR4_D_Msk /*!< Backup data */ 00861 00862 /******************* Bit definition for BKP_DR5 register ********************/ 00863 #define BKP_DR5_D_Pos (0U) 00864 #define BKP_DR5_D_Msk (0xFFFFU << BKP_DR5_D_Pos) /*!< 0x0000FFFF */ 00865 #define BKP_DR5_D BKP_DR5_D_Msk /*!< Backup data */ 00866 00867 /******************* Bit definition for BKP_DR6 register ********************/ 00868 #define BKP_DR6_D_Pos (0U) 00869 #define BKP_DR6_D_Msk (0xFFFFU << BKP_DR6_D_Pos) /*!< 0x0000FFFF */ 00870 #define BKP_DR6_D BKP_DR6_D_Msk /*!< Backup data */ 00871 00872 /******************* Bit definition for BKP_DR7 register ********************/ 00873 #define BKP_DR7_D_Pos (0U) 00874 #define BKP_DR7_D_Msk (0xFFFFU << BKP_DR7_D_Pos) /*!< 0x0000FFFF */ 00875 #define BKP_DR7_D BKP_DR7_D_Msk /*!< Backup data */ 00876 00877 /******************* Bit definition for BKP_DR8 register ********************/ 00878 #define BKP_DR8_D_Pos (0U) 00879 #define BKP_DR8_D_Msk (0xFFFFU << BKP_DR8_D_Pos) /*!< 0x0000FFFF */ 00880 #define BKP_DR8_D BKP_DR8_D_Msk /*!< Backup data */ 00881 00882 /******************* Bit definition for BKP_DR9 register ********************/ 00883 #define BKP_DR9_D_Pos (0U) 00884 #define BKP_DR9_D_Msk (0xFFFFU << BKP_DR9_D_Pos) /*!< 0x0000FFFF */ 00885 #define BKP_DR9_D BKP_DR9_D_Msk /*!< Backup data */ 00886 00887 /******************* Bit definition for BKP_DR10 register *******************/ 00888 #define BKP_DR10_D_Pos (0U) 00889 #define BKP_DR10_D_Msk (0xFFFFU << BKP_DR10_D_Pos) /*!< 0x0000FFFF */ 00890 #define BKP_DR10_D BKP_DR10_D_Msk /*!< Backup data */ 00891 00892 #define RTC_BKP_NUMBER 10 00893 00894 /****************** Bit definition for BKP_RTCCR register *******************/ 00895 #define BKP_RTCCR_CAL_Pos (0U) 00896 #define BKP_RTCCR_CAL_Msk (0x7FU << BKP_RTCCR_CAL_Pos) /*!< 0x0000007F */ 00897 #define BKP_RTCCR_CAL BKP_RTCCR_CAL_Msk /*!< Calibration value */ 00898 #define BKP_RTCCR_CCO_Pos (7U) 00899 #define BKP_RTCCR_CCO_Msk (0x1U << BKP_RTCCR_CCO_Pos) /*!< 0x00000080 */ 00900 #define BKP_RTCCR_CCO BKP_RTCCR_CCO_Msk /*!< Calibration Clock Output */ 00901 #define BKP_RTCCR_ASOE_Pos (8U) 00902 #define BKP_RTCCR_ASOE_Msk (0x1U << BKP_RTCCR_ASOE_Pos) /*!< 0x00000100 */ 00903 #define BKP_RTCCR_ASOE BKP_RTCCR_ASOE_Msk /*!< Alarm or Second Output Enable */ 00904 #define BKP_RTCCR_ASOS_Pos (9U) 00905 #define BKP_RTCCR_ASOS_Msk (0x1U << BKP_RTCCR_ASOS_Pos) /*!< 0x00000200 */ 00906 #define BKP_RTCCR_ASOS BKP_RTCCR_ASOS_Msk /*!< Alarm or Second Output Selection */ 00907 00908 /******************** Bit definition for BKP_CR register ********************/ 00909 #define BKP_CR_TPE_Pos (0U) 00910 #define BKP_CR_TPE_Msk (0x1U << BKP_CR_TPE_Pos) /*!< 0x00000001 */ 00911 #define BKP_CR_TPE BKP_CR_TPE_Msk /*!< TAMPER pin enable */ 00912 #define BKP_CR_TPAL_Pos (1U) 00913 #define BKP_CR_TPAL_Msk (0x1U << BKP_CR_TPAL_Pos) /*!< 0x00000002 */ 00914 #define BKP_CR_TPAL BKP_CR_TPAL_Msk /*!< TAMPER pin active level */ 00915 00916 /******************* Bit definition for BKP_CSR register ********************/ 00917 #define BKP_CSR_CTE_Pos (0U) 00918 #define BKP_CSR_CTE_Msk (0x1U << BKP_CSR_CTE_Pos) /*!< 0x00000001 */ 00919 #define BKP_CSR_CTE BKP_CSR_CTE_Msk /*!< Clear Tamper event */ 00920 #define BKP_CSR_CTI_Pos (1U) 00921 #define BKP_CSR_CTI_Msk (0x1U << BKP_CSR_CTI_Pos) /*!< 0x00000002 */ 00922 #define BKP_CSR_CTI BKP_CSR_CTI_Msk /*!< Clear Tamper Interrupt */ 00923 #define BKP_CSR_TPIE_Pos (2U) 00924 #define BKP_CSR_TPIE_Msk (0x1U << BKP_CSR_TPIE_Pos) /*!< 0x00000004 */ 00925 #define BKP_CSR_TPIE BKP_CSR_TPIE_Msk /*!< TAMPER Pin interrupt enable */ 00926 #define BKP_CSR_TEF_Pos (8U) 00927 #define BKP_CSR_TEF_Msk (0x1U << BKP_CSR_TEF_Pos) /*!< 0x00000100 */ 00928 #define BKP_CSR_TEF BKP_CSR_TEF_Msk /*!< Tamper Event Flag */ 00929 #define BKP_CSR_TIF_Pos (9U) 00930 #define BKP_CSR_TIF_Msk (0x1U << BKP_CSR_TIF_Pos) /*!< 0x00000200 */ 00931 #define BKP_CSR_TIF BKP_CSR_TIF_Msk /*!< Tamper Interrupt Flag */ 00932 00933 /******************************************************************************/ 00934 /* */ 00935 /* Reset and Clock Control */ 00936 /* */ 00937 /******************************************************************************/ 00938 00939 /******************** Bit definition for RCC_CR register ********************/ 00940 #define RCC_CR_HSION_Pos (0U) 00941 #define RCC_CR_HSION_Msk (0x1U << RCC_CR_HSION_Pos) /*!< 0x00000001 */ 00942 #define RCC_CR_HSION RCC_CR_HSION_Msk /*!< Internal High Speed clock enable */ 00943 #define RCC_CR_HSIRDY_Pos (1U) 00944 #define RCC_CR_HSIRDY_Msk (0x1U << RCC_CR_HSIRDY_Pos) /*!< 0x00000002 */ 00945 #define RCC_CR_HSIRDY RCC_CR_HSIRDY_Msk /*!< Internal High Speed clock ready flag */ 00946 #define RCC_CR_HSITRIM_Pos (3U) 00947 #define RCC_CR_HSITRIM_Msk (0x1FU << RCC_CR_HSITRIM_Pos) /*!< 0x000000F8 */ 00948 #define RCC_CR_HSITRIM RCC_CR_HSITRIM_Msk /*!< Internal High Speed clock trimming */ 00949 #define RCC_CR_HSICAL_Pos (8U) 00950 #define RCC_CR_HSICAL_Msk (0xFFU << RCC_CR_HSICAL_Pos) /*!< 0x0000FF00 */ 00951 #define RCC_CR_HSICAL RCC_CR_HSICAL_Msk /*!< Internal High Speed clock Calibration */ 00952 #define RCC_CR_HSEON_Pos (16U) 00953 #define RCC_CR_HSEON_Msk (0x1U << RCC_CR_HSEON_Pos) /*!< 0x00010000 */ 00954 #define RCC_CR_HSEON RCC_CR_HSEON_Msk /*!< External High Speed clock enable */ 00955 #define RCC_CR_HSERDY_Pos (17U) 00956 #define RCC_CR_HSERDY_Msk (0x1U << RCC_CR_HSERDY_Pos) /*!< 0x00020000 */ 00957 #define RCC_CR_HSERDY RCC_CR_HSERDY_Msk /*!< External High Speed clock ready flag */ 00958 #define RCC_CR_HSEBYP_Pos (18U) 00959 #define RCC_CR_HSEBYP_Msk (0x1U << RCC_CR_HSEBYP_Pos) /*!< 0x00040000 */ 00960 #define RCC_CR_HSEBYP RCC_CR_HSEBYP_Msk /*!< External High Speed clock Bypass */ 00961 #define RCC_CR_CSSON_Pos (19U) 00962 #define RCC_CR_CSSON_Msk (0x1U << RCC_CR_CSSON_Pos) /*!< 0x00080000 */ 00963 #define RCC_CR_CSSON RCC_CR_CSSON_Msk /*!< Clock Security System enable */ 00964 #define RCC_CR_PLLON_Pos (24U) 00965 #define RCC_CR_PLLON_Msk (0x1U << RCC_CR_PLLON_Pos) /*!< 0x01000000 */ 00966 #define RCC_CR_PLLON RCC_CR_PLLON_Msk /*!< PLL enable */ 00967 #define RCC_CR_PLLRDY_Pos (25U) 00968 #define RCC_CR_PLLRDY_Msk (0x1U << RCC_CR_PLLRDY_Pos) /*!< 0x02000000 */ 00969 #define RCC_CR_PLLRDY RCC_CR_PLLRDY_Msk /*!< PLL clock ready flag */ 00970 00971 00972 /******************* Bit definition for RCC_CFGR register *******************/ 00973 /*!< SW configuration */ 00974 #define RCC_CFGR_SW_Pos (0U) 00975 #define RCC_CFGR_SW_Msk (0x3U << RCC_CFGR_SW_Pos) /*!< 0x00000003 */ 00976 #define RCC_CFGR_SW RCC_CFGR_SW_Msk /*!< SW[1:0] bits (System clock Switch) */ 00977 #define RCC_CFGR_SW_0 (0x1U << RCC_CFGR_SW_Pos) /*!< 0x00000001 */ 00978 #define RCC_CFGR_SW_1 (0x2U << RCC_CFGR_SW_Pos) /*!< 0x00000002 */ 00979 00980 #define RCC_CFGR_SW_HSI ((uint32_t)0x00000000) /*!< HSI selected as system clock */ 00981 #define RCC_CFGR_SW_HSE ((uint32_t)0x00000001) /*!< HSE selected as system clock */ 00982 #define RCC_CFGR_SW_PLL ((uint32_t)0x00000002) /*!< PLL selected as system clock */ 00983 00984 /*!< SWS configuration */ 00985 #define RCC_CFGR_SWS_Pos (2U) 00986 #define RCC_CFGR_SWS_Msk (0x3U << RCC_CFGR_SWS_Pos) /*!< 0x0000000C */ 00987 #define RCC_CFGR_SWS RCC_CFGR_SWS_Msk /*!< SWS[1:0] bits (System Clock Switch Status) */ 00988 #define RCC_CFGR_SWS_0 (0x1U << RCC_CFGR_SWS_Pos) /*!< 0x00000004 */ 00989 #define RCC_CFGR_SWS_1 (0x2U << RCC_CFGR_SWS_Pos) /*!< 0x00000008 */ 00990 00991 #define RCC_CFGR_SWS_HSI ((uint32_t)0x00000000) /*!< HSI oscillator used as system clock */ 00992 #define RCC_CFGR_SWS_HSE ((uint32_t)0x00000004) /*!< HSE oscillator used as system clock */ 00993 #define RCC_CFGR_SWS_PLL ((uint32_t)0x00000008) /*!< PLL used as system clock */ 00994 00995 /*!< HPRE configuration */ 00996 #define RCC_CFGR_HPRE_Pos (4U) 00997 #define RCC_CFGR_HPRE_Msk (0xFU << RCC_CFGR_HPRE_Pos) /*!< 0x000000F0 */ 00998 #define RCC_CFGR_HPRE RCC_CFGR_HPRE_Msk /*!< HPRE[3:0] bits (AHB prescaler) */ 00999 #define RCC_CFGR_HPRE_0 (0x1U << RCC_CFGR_HPRE_Pos) /*!< 0x00000010 */ 01000 #define RCC_CFGR_HPRE_1 (0x2U << RCC_CFGR_HPRE_Pos) /*!< 0x00000020 */ 01001 #define RCC_CFGR_HPRE_2 (0x4U << RCC_CFGR_HPRE_Pos) /*!< 0x00000040 */ 01002 #define RCC_CFGR_HPRE_3 (0x8U << RCC_CFGR_HPRE_Pos) /*!< 0x00000080 */ 01003 01004 #define RCC_CFGR_HPRE_DIV1 ((uint32_t)0x00000000) /*!< SYSCLK not divided */ 01005 #define RCC_CFGR_HPRE_DIV2 ((uint32_t)0x00000080) /*!< SYSCLK divided by 2 */ 01006 #define RCC_CFGR_HPRE_DIV4 ((uint32_t)0x00000090) /*!< SYSCLK divided by 4 */ 01007 #define RCC_CFGR_HPRE_DIV8 ((uint32_t)0x000000A0) /*!< SYSCLK divided by 8 */ 01008 #define RCC_CFGR_HPRE_DIV16 ((uint32_t)0x000000B0) /*!< SYSCLK divided by 16 */ 01009 #define RCC_CFGR_HPRE_DIV64 ((uint32_t)0x000000C0) /*!< SYSCLK divided by 64 */ 01010 #define RCC_CFGR_HPRE_DIV128 ((uint32_t)0x000000D0) /*!< SYSCLK divided by 128 */ 01011 #define RCC_CFGR_HPRE_DIV256 ((uint32_t)0x000000E0) /*!< SYSCLK divided by 256 */ 01012 #define RCC_CFGR_HPRE_DIV512 ((uint32_t)0x000000F0) /*!< SYSCLK divided by 512 */ 01013 01014 /*!< PPRE1 configuration */ 01015 #define RCC_CFGR_PPRE1_Pos (8U) 01016 #define RCC_CFGR_PPRE1_Msk (0x7U << RCC_CFGR_PPRE1_Pos) /*!< 0x00000700 */ 01017 #define RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_Msk /*!< PRE1[2:0] bits (APB1 prescaler) */ 01018 #define RCC_CFGR_PPRE1_0 (0x1U << RCC_CFGR_PPRE1_Pos) /*!< 0x00000100 */ 01019 #define RCC_CFGR_PPRE1_1 (0x2U << RCC_CFGR_PPRE1_Pos) /*!< 0x00000200 */ 01020 #define RCC_CFGR_PPRE1_2 (0x4U << RCC_CFGR_PPRE1_Pos) /*!< 0x00000400 */ 01021 01022 #define RCC_CFGR_PPRE1_DIV1 ((uint32_t)0x00000000) /*!< HCLK not divided */ 01023 #define RCC_CFGR_PPRE1_DIV2 ((uint32_t)0x00000400) /*!< HCLK divided by 2 */ 01024 #define RCC_CFGR_PPRE1_DIV4 ((uint32_t)0x00000500) /*!< HCLK divided by 4 */ 01025 #define RCC_CFGR_PPRE1_DIV8 ((uint32_t)0x00000600) /*!< HCLK divided by 8 */ 01026 #define RCC_CFGR_PPRE1_DIV16 ((uint32_t)0x00000700) /*!< HCLK divided by 16 */ 01027 01028 /*!< PPRE2 configuration */ 01029 #define RCC_CFGR_PPRE2_Pos (11U) 01030 #define RCC_CFGR_PPRE2_Msk (0x7U << RCC_CFGR_PPRE2_Pos) /*!< 0x00003800 */ 01031 #define RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_Msk /*!< PRE2[2:0] bits (APB2 prescaler) */ 01032 #define RCC_CFGR_PPRE2_0 (0x1U << RCC_CFGR_PPRE2_Pos) /*!< 0x00000800 */ 01033 #define RCC_CFGR_PPRE2_1 (0x2U << RCC_CFGR_PPRE2_Pos) /*!< 0x00001000 */ 01034 #define RCC_CFGR_PPRE2_2 (0x4U << RCC_CFGR_PPRE2_Pos) /*!< 0x00002000 */ 01035 01036 #define RCC_CFGR_PPRE2_DIV1 ((uint32_t)0x00000000) /*!< HCLK not divided */ 01037 #define RCC_CFGR_PPRE2_DIV2 ((uint32_t)0x00002000) /*!< HCLK divided by 2 */ 01038 #define RCC_CFGR_PPRE2_DIV4 ((uint32_t)0x00002800) /*!< HCLK divided by 4 */ 01039 #define RCC_CFGR_PPRE2_DIV8 ((uint32_t)0x00003000) /*!< HCLK divided by 8 */ 01040 #define RCC_CFGR_PPRE2_DIV16 ((uint32_t)0x00003800) /*!< HCLK divided by 16 */ 01041 01042 /*!< ADCPPRE configuration */ 01043 #define RCC_CFGR_ADCPRE_Pos (14U) 01044 #define RCC_CFGR_ADCPRE_Msk (0x3U << RCC_CFGR_ADCPRE_Pos) /*!< 0x0000C000 */ 01045 #define RCC_CFGR_ADCPRE RCC_CFGR_ADCPRE_Msk /*!< ADCPRE[1:0] bits (ADC prescaler) */ 01046 #define RCC_CFGR_ADCPRE_0 (0x1U << RCC_CFGR_ADCPRE_Pos) /*!< 0x00004000 */ 01047 #define RCC_CFGR_ADCPRE_1 (0x2U << RCC_CFGR_ADCPRE_Pos) /*!< 0x00008000 */ 01048 01049 #define RCC_CFGR_ADCPRE_DIV2 ((uint32_t)0x00000000) /*!< PCLK2 divided by 2 */ 01050 #define RCC_CFGR_ADCPRE_DIV4 ((uint32_t)0x00004000) /*!< PCLK2 divided by 4 */ 01051 #define RCC_CFGR_ADCPRE_DIV6 ((uint32_t)0x00008000) /*!< PCLK2 divided by 6 */ 01052 #define RCC_CFGR_ADCPRE_DIV8 ((uint32_t)0x0000C000) /*!< PCLK2 divided by 8 */ 01053 01054 #define RCC_CFGR_PLLSRC_Pos (16U) 01055 #define RCC_CFGR_PLLSRC_Msk (0x1U << RCC_CFGR_PLLSRC_Pos) /*!< 0x00010000 */ 01056 #define RCC_CFGR_PLLSRC RCC_CFGR_PLLSRC_Msk /*!< PLL entry clock source */ 01057 01058 #define RCC_CFGR_PLLXTPRE_Pos (17U) 01059 #define RCC_CFGR_PLLXTPRE_Msk (0x1U << RCC_CFGR_PLLXTPRE_Pos) /*!< 0x00020000 */ 01060 #define RCC_CFGR_PLLXTPRE RCC_CFGR_PLLXTPRE_Msk /*!< HSE divider for PLL entry */ 01061 01062 /*!< PLLMUL configuration */ 01063 #define RCC_CFGR_PLLMULL_Pos (18U) 01064 #define RCC_CFGR_PLLMULL_Msk (0xFU << RCC_CFGR_PLLMULL_Pos) /*!< 0x003C0000 */ 01065 #define RCC_CFGR_PLLMULL RCC_CFGR_PLLMULL_Msk /*!< PLLMUL[3:0] bits (PLL multiplication factor) */ 01066 #define RCC_CFGR_PLLMULL_0 (0x1U << RCC_CFGR_PLLMULL_Pos) /*!< 0x00040000 */ 01067 #define RCC_CFGR_PLLMULL_1 (0x2U << RCC_CFGR_PLLMULL_Pos) /*!< 0x00080000 */ 01068 #define RCC_CFGR_PLLMULL_2 (0x4U << RCC_CFGR_PLLMULL_Pos) /*!< 0x00100000 */ 01069 #define RCC_CFGR_PLLMULL_3 (0x8U << RCC_CFGR_PLLMULL_Pos) /*!< 0x00200000 */ 01070 01071 #define RCC_CFGR_PLLXTPRE_HSE ((uint32_t)0x00000000) /*!< HSE clock not divided for PLL entry */ 01072 #define RCC_CFGR_PLLXTPRE_HSE_DIV2 ((uint32_t)0x00020000) /*!< HSE clock divided by 2 for PLL entry */ 01073 01074 #define RCC_CFGR_PLLMULL2 ((uint32_t)0x00000000) /*!< PLL input clock*2 */ 01075 #define RCC_CFGR_PLLMULL3_Pos (18U) 01076 #define RCC_CFGR_PLLMULL3_Msk (0x1U << RCC_CFGR_PLLMULL3_Pos) /*!< 0x00040000 */ 01077 #define RCC_CFGR_PLLMULL3 RCC_CFGR_PLLMULL3_Msk /*!< PLL input clock*3 */ 01078 #define RCC_CFGR_PLLMULL4_Pos (19U) 01079 #define RCC_CFGR_PLLMULL4_Msk (0x1U << RCC_CFGR_PLLMULL4_Pos) /*!< 0x00080000 */ 01080 #define RCC_CFGR_PLLMULL4 RCC_CFGR_PLLMULL4_Msk /*!< PLL input clock*4 */ 01081 #define RCC_CFGR_PLLMULL5_Pos (18U) 01082 #define RCC_CFGR_PLLMULL5_Msk (0x3U << RCC_CFGR_PLLMULL5_Pos) /*!< 0x000C0000 */ 01083 #define RCC_CFGR_PLLMULL5 RCC_CFGR_PLLMULL5_Msk /*!< PLL input clock*5 */ 01084 #define RCC_CFGR_PLLMULL6_Pos (20U) 01085 #define RCC_CFGR_PLLMULL6_Msk (0x1U << RCC_CFGR_PLLMULL6_Pos) /*!< 0x00100000 */ 01086 #define RCC_CFGR_PLLMULL6 RCC_CFGR_PLLMULL6_Msk /*!< PLL input clock*6 */ 01087 #define RCC_CFGR_PLLMULL7_Pos (18U) 01088 #define RCC_CFGR_PLLMULL7_Msk (0x5U << RCC_CFGR_PLLMULL7_Pos) /*!< 0x00140000 */ 01089 #define RCC_CFGR_PLLMULL7 RCC_CFGR_PLLMULL7_Msk /*!< PLL input clock*7 */ 01090 #define RCC_CFGR_PLLMULL8_Pos (19U) 01091 #define RCC_CFGR_PLLMULL8_Msk (0x3U << RCC_CFGR_PLLMULL8_Pos) /*!< 0x00180000 */ 01092 #define RCC_CFGR_PLLMULL8 RCC_CFGR_PLLMULL8_Msk /*!< PLL input clock*8 */ 01093 #define RCC_CFGR_PLLMULL9_Pos (18U) 01094 #define RCC_CFGR_PLLMULL9_Msk (0x7U << RCC_CFGR_PLLMULL9_Pos) /*!< 0x001C0000 */ 01095 #define RCC_CFGR_PLLMULL9 RCC_CFGR_PLLMULL9_Msk /*!< PLL input clock*9 */ 01096 #define RCC_CFGR_PLLMULL10_Pos (21U) 01097 #define RCC_CFGR_PLLMULL10_Msk (0x1U << RCC_CFGR_PLLMULL10_Pos) /*!< 0x00200000 */ 01098 #define RCC_CFGR_PLLMULL10 RCC_CFGR_PLLMULL10_Msk /*!< PLL input clock10 */ 01099 #define RCC_CFGR_PLLMULL11_Pos (18U) 01100 #define RCC_CFGR_PLLMULL11_Msk (0x9U << RCC_CFGR_PLLMULL11_Pos) /*!< 0x00240000 */ 01101 #define RCC_CFGR_PLLMULL11 RCC_CFGR_PLLMULL11_Msk /*!< PLL input clock*11 */ 01102 #define RCC_CFGR_PLLMULL12_Pos (19U) 01103 #define RCC_CFGR_PLLMULL12_Msk (0x5U << RCC_CFGR_PLLMULL12_Pos) /*!< 0x00280000 */ 01104 #define RCC_CFGR_PLLMULL12 RCC_CFGR_PLLMULL12_Msk /*!< PLL input clock*12 */ 01105 #define RCC_CFGR_PLLMULL13_Pos (18U) 01106 #define RCC_CFGR_PLLMULL13_Msk (0xBU << RCC_CFGR_PLLMULL13_Pos) /*!< 0x002C0000 */ 01107 #define RCC_CFGR_PLLMULL13 RCC_CFGR_PLLMULL13_Msk /*!< PLL input clock*13 */ 01108 #define RCC_CFGR_PLLMULL14_Pos (20U) 01109 #define RCC_CFGR_PLLMULL14_Msk (0x3U << RCC_CFGR_PLLMULL14_Pos) /*!< 0x00300000 */ 01110 #define RCC_CFGR_PLLMULL14 RCC_CFGR_PLLMULL14_Msk /*!< PLL input clock*14 */ 01111 #define RCC_CFGR_PLLMULL15_Pos (18U) 01112 #define RCC_CFGR_PLLMULL15_Msk (0xDU << RCC_CFGR_PLLMULL15_Pos) /*!< 0x00340000 */ 01113 #define RCC_CFGR_PLLMULL15 RCC_CFGR_PLLMULL15_Msk /*!< PLL input clock*15 */ 01114 #define RCC_CFGR_PLLMULL16_Pos (19U) 01115 #define RCC_CFGR_PLLMULL16_Msk (0x7U << RCC_CFGR_PLLMULL16_Pos) /*!< 0x00380000 */ 01116 #define RCC_CFGR_PLLMULL16 RCC_CFGR_PLLMULL16_Msk /*!< PLL input clock*16 */ 01117 #define RCC_CFGR_USBPRE_Pos (22U) 01118 #define RCC_CFGR_USBPRE_Msk (0x1U << RCC_CFGR_USBPRE_Pos) /*!< 0x00400000 */ 01119 #define RCC_CFGR_USBPRE RCC_CFGR_USBPRE_Msk /*!< USB Device prescaler */ 01120 01121 /*!< MCO configuration */ 01122 #define RCC_CFGR_MCO_Pos (24U) 01123 #define RCC_CFGR_MCO_Msk (0x7U << RCC_CFGR_MCO_Pos) /*!< 0x07000000 */ 01124 #define RCC_CFGR_MCO RCC_CFGR_MCO_Msk /*!< MCO[2:0] bits (Microcontroller Clock Output) */ 01125 #define RCC_CFGR_MCO_0 (0x1U << RCC_CFGR_MCO_Pos) /*!< 0x01000000 */ 01126 #define RCC_CFGR_MCO_1 (0x2U << RCC_CFGR_MCO_Pos) /*!< 0x02000000 */ 01127 #define RCC_CFGR_MCO_2 (0x4U << RCC_CFGR_MCO_Pos) /*!< 0x04000000 */ 01128 01129 #define RCC_CFGR_MCO_NOCLOCK ((uint32_t)0x00000000) /*!< No clock */ 01130 #define RCC_CFGR_MCO_SYSCLK ((uint32_t)0x04000000) /*!< System clock selected as MCO source */ 01131 #define RCC_CFGR_MCO_HSI ((uint32_t)0x05000000) /*!< HSI clock selected as MCO source */ 01132 #define RCC_CFGR_MCO_HSE ((uint32_t)0x06000000) /*!< HSE clock selected as MCO source */ 01133 #define RCC_CFGR_MCO_PLLCLK_DIV2 ((uint32_t)0x07000000) /*!< PLL clock divided by 2 selected as MCO source */ 01134 01135 /* Reference defines */ 01136 #define RCC_CFGR_MCOSEL RCC_CFGR_MCO 01137 #define RCC_CFGR_MCOSEL_0 RCC_CFGR_MCO_0 01138 #define RCC_CFGR_MCOSEL_1 RCC_CFGR_MCO_1 01139 #define RCC_CFGR_MCOSEL_2 RCC_CFGR_MCO_2 01140 #define RCC_CFGR_MCOSEL_NOCLOCK RCC_CFGR_MCO_NOCLOCK 01141 #define RCC_CFGR_MCOSEL_SYSCLK RCC_CFGR_MCO_SYSCLK 01142 #define RCC_CFGR_MCOSEL_HSI RCC_CFGR_MCO_HSI 01143 #define RCC_CFGR_MCOSEL_HSE RCC_CFGR_MCO_HSE 01144 #define RCC_CFGR_MCOSEL_PLL_DIV2 RCC_CFGR_MCO_PLLCLK_DIV2 01145 01146 /*!<****************** Bit definition for RCC_CIR register ********************/ 01147 #define RCC_CIR_LSIRDYF_Pos (0U) 01148 #define RCC_CIR_LSIRDYF_Msk (0x1U << RCC_CIR_LSIRDYF_Pos) /*!< 0x00000001 */ 01149 #define RCC_CIR_LSIRDYF RCC_CIR_LSIRDYF_Msk /*!< LSI Ready Interrupt flag */ 01150 #define RCC_CIR_LSERDYF_Pos (1U) 01151 #define RCC_CIR_LSERDYF_Msk (0x1U << RCC_CIR_LSERDYF_Pos) /*!< 0x00000002 */ 01152 #define RCC_CIR_LSERDYF RCC_CIR_LSERDYF_Msk /*!< LSE Ready Interrupt flag */ 01153 #define RCC_CIR_HSIRDYF_Pos (2U) 01154 #define RCC_CIR_HSIRDYF_Msk (0x1U << RCC_CIR_HSIRDYF_Pos) /*!< 0x00000004 */ 01155 #define RCC_CIR_HSIRDYF RCC_CIR_HSIRDYF_Msk /*!< HSI Ready Interrupt flag */ 01156 #define RCC_CIR_HSERDYF_Pos (3U) 01157 #define RCC_CIR_HSERDYF_Msk (0x1U << RCC_CIR_HSERDYF_Pos) /*!< 0x00000008 */ 01158 #define RCC_CIR_HSERDYF RCC_CIR_HSERDYF_Msk /*!< HSE Ready Interrupt flag */ 01159 #define RCC_CIR_PLLRDYF_Pos (4U) 01160 #define RCC_CIR_PLLRDYF_Msk (0x1U << RCC_CIR_PLLRDYF_Pos) /*!< 0x00000010 */ 01161 #define RCC_CIR_PLLRDYF RCC_CIR_PLLRDYF_Msk /*!< PLL Ready Interrupt flag */ 01162 #define RCC_CIR_CSSF_Pos (7U) 01163 #define RCC_CIR_CSSF_Msk (0x1U << RCC_CIR_CSSF_Pos) /*!< 0x00000080 */ 01164 #define RCC_CIR_CSSF RCC_CIR_CSSF_Msk /*!< Clock Security System Interrupt flag */ 01165 #define RCC_CIR_LSIRDYIE_Pos (8U) 01166 #define RCC_CIR_LSIRDYIE_Msk (0x1U << RCC_CIR_LSIRDYIE_Pos) /*!< 0x00000100 */ 01167 #define RCC_CIR_LSIRDYIE RCC_CIR_LSIRDYIE_Msk /*!< LSI Ready Interrupt Enable */ 01168 #define RCC_CIR_LSERDYIE_Pos (9U) 01169 #define RCC_CIR_LSERDYIE_Msk (0x1U << RCC_CIR_LSERDYIE_Pos) /*!< 0x00000200 */ 01170 #define RCC_CIR_LSERDYIE RCC_CIR_LSERDYIE_Msk /*!< LSE Ready Interrupt Enable */ 01171 #define RCC_CIR_HSIRDYIE_Pos (10U) 01172 #define RCC_CIR_HSIRDYIE_Msk (0x1U << RCC_CIR_HSIRDYIE_Pos) /*!< 0x00000400 */ 01173 #define RCC_CIR_HSIRDYIE RCC_CIR_HSIRDYIE_Msk /*!< HSI Ready Interrupt Enable */ 01174 #define RCC_CIR_HSERDYIE_Pos (11U) 01175 #define RCC_CIR_HSERDYIE_Msk (0x1U << RCC_CIR_HSERDYIE_Pos) /*!< 0x00000800 */ 01176 #define RCC_CIR_HSERDYIE RCC_CIR_HSERDYIE_Msk /*!< HSE Ready Interrupt Enable */ 01177 #define RCC_CIR_PLLRDYIE_Pos (12U) 01178 #define RCC_CIR_PLLRDYIE_Msk (0x1U << RCC_CIR_PLLRDYIE_Pos) /*!< 0x00001000 */ 01179 #define RCC_CIR_PLLRDYIE RCC_CIR_PLLRDYIE_Msk /*!< PLL Ready Interrupt Enable */ 01180 #define RCC_CIR_LSIRDYC_Pos (16U) 01181 #define RCC_CIR_LSIRDYC_Msk (0x1U << RCC_CIR_LSIRDYC_Pos) /*!< 0x00010000 */ 01182 #define RCC_CIR_LSIRDYC RCC_CIR_LSIRDYC_Msk /*!< LSI Ready Interrupt Clear */ 01183 #define RCC_CIR_LSERDYC_Pos (17U) 01184 #define RCC_CIR_LSERDYC_Msk (0x1U << RCC_CIR_LSERDYC_Pos) /*!< 0x00020000 */ 01185 #define RCC_CIR_LSERDYC RCC_CIR_LSERDYC_Msk /*!< LSE Ready Interrupt Clear */ 01186 #define RCC_CIR_HSIRDYC_Pos (18U) 01187 #define RCC_CIR_HSIRDYC_Msk (0x1U << RCC_CIR_HSIRDYC_Pos) /*!< 0x00040000 */ 01188 #define RCC_CIR_HSIRDYC RCC_CIR_HSIRDYC_Msk /*!< HSI Ready Interrupt Clear */ 01189 #define RCC_CIR_HSERDYC_Pos (19U) 01190 #define RCC_CIR_HSERDYC_Msk (0x1U << RCC_CIR_HSERDYC_Pos) /*!< 0x00080000 */ 01191 #define RCC_CIR_HSERDYC RCC_CIR_HSERDYC_Msk /*!< HSE Ready Interrupt Clear */ 01192 #define RCC_CIR_PLLRDYC_Pos (20U) 01193 #define RCC_CIR_PLLRDYC_Msk (0x1U << RCC_CIR_PLLRDYC_Pos) /*!< 0x00100000 */ 01194 #define RCC_CIR_PLLRDYC RCC_CIR_PLLRDYC_Msk /*!< PLL Ready Interrupt Clear */ 01195 #define RCC_CIR_CSSC_Pos (23U) 01196 #define RCC_CIR_CSSC_Msk (0x1U << RCC_CIR_CSSC_Pos) /*!< 0x00800000 */ 01197 #define RCC_CIR_CSSC RCC_CIR_CSSC_Msk /*!< Clock Security System Interrupt Clear */ 01198 01199 01200 /***************** Bit definition for RCC_APB2RSTR register *****************/ 01201 #define RCC_APB2RSTR_AFIORST_Pos (0U) 01202 #define RCC_APB2RSTR_AFIORST_Msk (0x1U << RCC_APB2RSTR_AFIORST_Pos) /*!< 0x00000001 */ 01203 #define RCC_APB2RSTR_AFIORST RCC_APB2RSTR_AFIORST_Msk /*!< Alternate Function I/O reset */ 01204 #define RCC_APB2RSTR_IOPARST_Pos (2U) 01205 #define RCC_APB2RSTR_IOPARST_Msk (0x1U << RCC_APB2RSTR_IOPARST_Pos) /*!< 0x00000004 */ 01206 #define RCC_APB2RSTR_IOPARST RCC_APB2RSTR_IOPARST_Msk /*!< I/O port A reset */ 01207 #define RCC_APB2RSTR_IOPBRST_Pos (3U) 01208 #define RCC_APB2RSTR_IOPBRST_Msk (0x1U << RCC_APB2RSTR_IOPBRST_Pos) /*!< 0x00000008 */ 01209 #define RCC_APB2RSTR_IOPBRST RCC_APB2RSTR_IOPBRST_Msk /*!< I/O port B reset */ 01210 #define RCC_APB2RSTR_IOPCRST_Pos (4U) 01211 #define RCC_APB2RSTR_IOPCRST_Msk (0x1U << RCC_APB2RSTR_IOPCRST_Pos) /*!< 0x00000010 */ 01212 #define RCC_APB2RSTR_IOPCRST RCC_APB2RSTR_IOPCRST_Msk /*!< I/O port C reset */ 01213 #define RCC_APB2RSTR_IOPDRST_Pos (5U) 01214 #define RCC_APB2RSTR_IOPDRST_Msk (0x1U << RCC_APB2RSTR_IOPDRST_Pos) /*!< 0x00000020 */ 01215 #define RCC_APB2RSTR_IOPDRST RCC_APB2RSTR_IOPDRST_Msk /*!< I/O port D reset */ 01216 #define RCC_APB2RSTR_ADC1RST_Pos (9U) 01217 #define RCC_APB2RSTR_ADC1RST_Msk (0x1U << RCC_APB2RSTR_ADC1RST_Pos) /*!< 0x00000200 */ 01218 #define RCC_APB2RSTR_ADC1RST RCC_APB2RSTR_ADC1RST_Msk /*!< ADC 1 interface reset */ 01219 01220 #define RCC_APB2RSTR_ADC2RST_Pos (10U) 01221 #define RCC_APB2RSTR_ADC2RST_Msk (0x1U << RCC_APB2RSTR_ADC2RST_Pos) /*!< 0x00000400 */ 01222 #define RCC_APB2RSTR_ADC2RST RCC_APB2RSTR_ADC2RST_Msk /*!< ADC 2 interface reset */ 01223 01224 #define RCC_APB2RSTR_TIM1RST_Pos (11U) 01225 #define RCC_APB2RSTR_TIM1RST_Msk (0x1U << RCC_APB2RSTR_TIM1RST_Pos) /*!< 0x00000800 */ 01226 #define RCC_APB2RSTR_TIM1RST RCC_APB2RSTR_TIM1RST_Msk /*!< TIM1 Timer reset */ 01227 #define RCC_APB2RSTR_SPI1RST_Pos (12U) 01228 #define RCC_APB2RSTR_SPI1RST_Msk (0x1U << RCC_APB2RSTR_SPI1RST_Pos) /*!< 0x00001000 */ 01229 #define RCC_APB2RSTR_SPI1RST RCC_APB2RSTR_SPI1RST_Msk /*!< SPI 1 reset */ 01230 #define RCC_APB2RSTR_USART1RST_Pos (14U) 01231 #define RCC_APB2RSTR_USART1RST_Msk (0x1U << RCC_APB2RSTR_USART1RST_Pos) /*!< 0x00004000 */ 01232 #define RCC_APB2RSTR_USART1RST RCC_APB2RSTR_USART1RST_Msk /*!< USART1 reset */ 01233 01234 01235 #define RCC_APB2RSTR_IOPERST_Pos (6U) 01236 #define RCC_APB2RSTR_IOPERST_Msk (0x1U << RCC_APB2RSTR_IOPERST_Pos) /*!< 0x00000040 */ 01237 #define RCC_APB2RSTR_IOPERST RCC_APB2RSTR_IOPERST_Msk /*!< I/O port E reset */ 01238 01239 01240 01241 01242 /***************** Bit definition for RCC_APB1RSTR register *****************/ 01243 #define RCC_APB1RSTR_TIM2RST_Pos (0U) 01244 #define RCC_APB1RSTR_TIM2RST_Msk (0x1U << RCC_APB1RSTR_TIM2RST_Pos) /*!< 0x00000001 */ 01245 #define RCC_APB1RSTR_TIM2RST RCC_APB1RSTR_TIM2RST_Msk /*!< Timer 2 reset */ 01246 #define RCC_APB1RSTR_TIM3RST_Pos (1U) 01247 #define RCC_APB1RSTR_TIM3RST_Msk (0x1U << RCC_APB1RSTR_TIM3RST_Pos) /*!< 0x00000002 */ 01248 #define RCC_APB1RSTR_TIM3RST RCC_APB1RSTR_TIM3RST_Msk /*!< Timer 3 reset */ 01249 #define RCC_APB1RSTR_WWDGRST_Pos (11U) 01250 #define RCC_APB1RSTR_WWDGRST_Msk (0x1U << RCC_APB1RSTR_WWDGRST_Pos) /*!< 0x00000800 */ 01251 #define RCC_APB1RSTR_WWDGRST RCC_APB1RSTR_WWDGRST_Msk /*!< Window Watchdog reset */ 01252 #define RCC_APB1RSTR_USART2RST_Pos (17U) 01253 #define RCC_APB1RSTR_USART2RST_Msk (0x1U << RCC_APB1RSTR_USART2RST_Pos) /*!< 0x00020000 */ 01254 #define RCC_APB1RSTR_USART2RST RCC_APB1RSTR_USART2RST_Msk /*!< USART 2 reset */ 01255 #define RCC_APB1RSTR_I2C1RST_Pos (21U) 01256 #define RCC_APB1RSTR_I2C1RST_Msk (0x1U << RCC_APB1RSTR_I2C1RST_Pos) /*!< 0x00200000 */ 01257 #define RCC_APB1RSTR_I2C1RST RCC_APB1RSTR_I2C1RST_Msk /*!< I2C 1 reset */ 01258 01259 #define RCC_APB1RSTR_CAN1RST_Pos (25U) 01260 #define RCC_APB1RSTR_CAN1RST_Msk (0x1U << RCC_APB1RSTR_CAN1RST_Pos) /*!< 0x02000000 */ 01261 #define RCC_APB1RSTR_CAN1RST RCC_APB1RSTR_CAN1RST_Msk /*!< CAN1 reset */ 01262 01263 #define RCC_APB1RSTR_BKPRST_Pos (27U) 01264 #define RCC_APB1RSTR_BKPRST_Msk (0x1U << RCC_APB1RSTR_BKPRST_Pos) /*!< 0x08000000 */ 01265 #define RCC_APB1RSTR_BKPRST RCC_APB1RSTR_BKPRST_Msk /*!< Backup interface reset */ 01266 #define RCC_APB1RSTR_PWRRST_Pos (28U) 01267 #define RCC_APB1RSTR_PWRRST_Msk (0x1U << RCC_APB1RSTR_PWRRST_Pos) /*!< 0x10000000 */ 01268 #define RCC_APB1RSTR_PWRRST RCC_APB1RSTR_PWRRST_Msk /*!< Power interface reset */ 01269 01270 #define RCC_APB1RSTR_TIM4RST_Pos (2U) 01271 #define RCC_APB1RSTR_TIM4RST_Msk (0x1U << RCC_APB1RSTR_TIM4RST_Pos) /*!< 0x00000004 */ 01272 #define RCC_APB1RSTR_TIM4RST RCC_APB1RSTR_TIM4RST_Msk /*!< Timer 4 reset */ 01273 #define RCC_APB1RSTR_SPI2RST_Pos (14U) 01274 #define RCC_APB1RSTR_SPI2RST_Msk (0x1U << RCC_APB1RSTR_SPI2RST_Pos) /*!< 0x00004000 */ 01275 #define RCC_APB1RSTR_SPI2RST RCC_APB1RSTR_SPI2RST_Msk /*!< SPI 2 reset */ 01276 #define RCC_APB1RSTR_USART3RST_Pos (18U) 01277 #define RCC_APB1RSTR_USART3RST_Msk (0x1U << RCC_APB1RSTR_USART3RST_Pos) /*!< 0x00040000 */ 01278 #define RCC_APB1RSTR_USART3RST RCC_APB1RSTR_USART3RST_Msk /*!< USART 3 reset */ 01279 #define RCC_APB1RSTR_I2C2RST_Pos (22U) 01280 #define RCC_APB1RSTR_I2C2RST_Msk (0x1U << RCC_APB1RSTR_I2C2RST_Pos) /*!< 0x00400000 */ 01281 #define RCC_APB1RSTR_I2C2RST RCC_APB1RSTR_I2C2RST_Msk /*!< I2C 2 reset */ 01282 01283 #define RCC_APB1RSTR_USBRST_Pos (23U) 01284 #define RCC_APB1RSTR_USBRST_Msk (0x1U << RCC_APB1RSTR_USBRST_Pos) /*!< 0x00800000 */ 01285 #define RCC_APB1RSTR_USBRST RCC_APB1RSTR_USBRST_Msk /*!< USB Device reset */ 01286 01287 01288 01289 01290 01291 01292 /****************** Bit definition for RCC_AHBENR register ******************/ 01293 #define RCC_AHBENR_DMA1EN_Pos (0U) 01294 #define RCC_AHBENR_DMA1EN_Msk (0x1U << RCC_AHBENR_DMA1EN_Pos) /*!< 0x00000001 */ 01295 #define RCC_AHBENR_DMA1EN RCC_AHBENR_DMA1EN_Msk /*!< DMA1 clock enable */ 01296 #define RCC_AHBENR_SRAMEN_Pos (2U) 01297 #define RCC_AHBENR_SRAMEN_Msk (0x1U << RCC_AHBENR_SRAMEN_Pos) /*!< 0x00000004 */ 01298 #define RCC_AHBENR_SRAMEN RCC_AHBENR_SRAMEN_Msk /*!< SRAM interface clock enable */ 01299 #define RCC_AHBENR_FLITFEN_Pos (4U) 01300 #define RCC_AHBENR_FLITFEN_Msk (0x1U << RCC_AHBENR_FLITFEN_Pos) /*!< 0x00000010 */ 01301 #define RCC_AHBENR_FLITFEN RCC_AHBENR_FLITFEN_Msk /*!< FLITF clock enable */ 01302 #define RCC_AHBENR_CRCEN_Pos (6U) 01303 #define RCC_AHBENR_CRCEN_Msk (0x1U << RCC_AHBENR_CRCEN_Pos) /*!< 0x00000040 */ 01304 #define RCC_AHBENR_CRCEN RCC_AHBENR_CRCEN_Msk /*!< CRC clock enable */ 01305 01306 01307 01308 01309 /****************** Bit definition for RCC_APB2ENR register *****************/ 01310 #define RCC_APB2ENR_AFIOEN_Pos (0U) 01311 #define RCC_APB2ENR_AFIOEN_Msk (0x1U << RCC_APB2ENR_AFIOEN_Pos) /*!< 0x00000001 */ 01312 #define RCC_APB2ENR_AFIOEN RCC_APB2ENR_AFIOEN_Msk /*!< Alternate Function I/O clock enable */ 01313 #define RCC_APB2ENR_IOPAEN_Pos (2U) 01314 #define RCC_APB2ENR_IOPAEN_Msk (0x1U << RCC_APB2ENR_IOPAEN_Pos) /*!< 0x00000004 */ 01315 #define RCC_APB2ENR_IOPAEN RCC_APB2ENR_IOPAEN_Msk /*!< I/O port A clock enable */ 01316 #define RCC_APB2ENR_IOPBEN_Pos (3U) 01317 #define RCC_APB2ENR_IOPBEN_Msk (0x1U << RCC_APB2ENR_IOPBEN_Pos) /*!< 0x00000008 */ 01318 #define RCC_APB2ENR_IOPBEN RCC_APB2ENR_IOPBEN_Msk /*!< I/O port B clock enable */ 01319 #define RCC_APB2ENR_IOPCEN_Pos (4U) 01320 #define RCC_APB2ENR_IOPCEN_Msk (0x1U << RCC_APB2ENR_IOPCEN_Pos) /*!< 0x00000010 */ 01321 #define RCC_APB2ENR_IOPCEN RCC_APB2ENR_IOPCEN_Msk /*!< I/O port C clock enable */ 01322 #define RCC_APB2ENR_IOPDEN_Pos (5U) 01323 #define RCC_APB2ENR_IOPDEN_Msk (0x1U << RCC_APB2ENR_IOPDEN_Pos) /*!< 0x00000020 */ 01324 #define RCC_APB2ENR_IOPDEN RCC_APB2ENR_IOPDEN_Msk /*!< I/O port D clock enable */ 01325 #define RCC_APB2ENR_ADC1EN_Pos (9U) 01326 #define RCC_APB2ENR_ADC1EN_Msk (0x1U << RCC_APB2ENR_ADC1EN_Pos) /*!< 0x00000200 */ 01327 #define RCC_APB2ENR_ADC1EN RCC_APB2ENR_ADC1EN_Msk /*!< ADC 1 interface clock enable */ 01328 01329 #define RCC_APB2ENR_ADC2EN_Pos (10U) 01330 #define RCC_APB2ENR_ADC2EN_Msk (0x1U << RCC_APB2ENR_ADC2EN_Pos) /*!< 0x00000400 */ 01331 #define RCC_APB2ENR_ADC2EN RCC_APB2ENR_ADC2EN_Msk /*!< ADC 2 interface clock enable */ 01332 01333 #define RCC_APB2ENR_TIM1EN_Pos (11U) 01334 #define RCC_APB2ENR_TIM1EN_Msk (0x1U << RCC_APB2ENR_TIM1EN_Pos) /*!< 0x00000800 */ 01335 #define RCC_APB2ENR_TIM1EN RCC_APB2ENR_TIM1EN_Msk /*!< TIM1 Timer clock enable */ 01336 #define RCC_APB2ENR_SPI1EN_Pos (12U) 01337 #define RCC_APB2ENR_SPI1EN_Msk (0x1U << RCC_APB2ENR_SPI1EN_Pos) /*!< 0x00001000 */ 01338 #define RCC_APB2ENR_SPI1EN RCC_APB2ENR_SPI1EN_Msk /*!< SPI 1 clock enable */ 01339 #define RCC_APB2ENR_USART1EN_Pos (14U) 01340 #define RCC_APB2ENR_USART1EN_Msk (0x1U << RCC_APB2ENR_USART1EN_Pos) /*!< 0x00004000 */ 01341 #define RCC_APB2ENR_USART1EN RCC_APB2ENR_USART1EN_Msk /*!< USART1 clock enable */ 01342 01343 01344 #define RCC_APB2ENR_IOPEEN_Pos (6U) 01345 #define RCC_APB2ENR_IOPEEN_Msk (0x1U << RCC_APB2ENR_IOPEEN_Pos) /*!< 0x00000040 */ 01346 #define RCC_APB2ENR_IOPEEN RCC_APB2ENR_IOPEEN_Msk /*!< I/O port E clock enable */ 01347 01348 01349 01350 01351 /***************** Bit definition for RCC_APB1ENR register ******************/ 01352 #define RCC_APB1ENR_TIM2EN_Pos (0U) 01353 #define RCC_APB1ENR_TIM2EN_Msk (0x1U << RCC_APB1ENR_TIM2EN_Pos) /*!< 0x00000001 */ 01354 #define RCC_APB1ENR_TIM2EN RCC_APB1ENR_TIM2EN_Msk /*!< Timer 2 clock enabled*/ 01355 #define RCC_APB1ENR_TIM3EN_Pos (1U) 01356 #define RCC_APB1ENR_TIM3EN_Msk (0x1U << RCC_APB1ENR_TIM3EN_Pos) /*!< 0x00000002 */ 01357 #define RCC_APB1ENR_TIM3EN RCC_APB1ENR_TIM3EN_Msk /*!< Timer 3 clock enable */ 01358 #define RCC_APB1ENR_WWDGEN_Pos (11U) 01359 #define RCC_APB1ENR_WWDGEN_Msk (0x1U << RCC_APB1ENR_WWDGEN_Pos) /*!< 0x00000800 */ 01360 #define RCC_APB1ENR_WWDGEN RCC_APB1ENR_WWDGEN_Msk /*!< Window Watchdog clock enable */ 01361 #define RCC_APB1ENR_USART2EN_Pos (17U) 01362 #define RCC_APB1ENR_USART2EN_Msk (0x1U << RCC_APB1ENR_USART2EN_Pos) /*!< 0x00020000 */ 01363 #define RCC_APB1ENR_USART2EN RCC_APB1ENR_USART2EN_Msk /*!< USART 2 clock enable */ 01364 #define RCC_APB1ENR_I2C1EN_Pos (21U) 01365 #define RCC_APB1ENR_I2C1EN_Msk (0x1U << RCC_APB1ENR_I2C1EN_Pos) /*!< 0x00200000 */ 01366 #define RCC_APB1ENR_I2C1EN RCC_APB1ENR_I2C1EN_Msk /*!< I2C 1 clock enable */ 01367 01368 #define RCC_APB1ENR_CAN1EN_Pos (25U) 01369 #define RCC_APB1ENR_CAN1EN_Msk (0x1U << RCC_APB1ENR_CAN1EN_Pos) /*!< 0x02000000 */ 01370 #define RCC_APB1ENR_CAN1EN RCC_APB1ENR_CAN1EN_Msk /*!< CAN1 clock enable */ 01371 01372 #define RCC_APB1ENR_BKPEN_Pos (27U) 01373 #define RCC_APB1ENR_BKPEN_Msk (0x1U << RCC_APB1ENR_BKPEN_Pos) /*!< 0x08000000 */ 01374 #define RCC_APB1ENR_BKPEN RCC_APB1ENR_BKPEN_Msk /*!< Backup interface clock enable */ 01375 #define RCC_APB1ENR_PWREN_Pos (28U) 01376 #define RCC_APB1ENR_PWREN_Msk (0x1U << RCC_APB1ENR_PWREN_Pos) /*!< 0x10000000 */ 01377 #define RCC_APB1ENR_PWREN RCC_APB1ENR_PWREN_Msk /*!< Power interface clock enable */ 01378 01379 #define RCC_APB1ENR_TIM4EN_Pos (2U) 01380 #define RCC_APB1ENR_TIM4EN_Msk (0x1U << RCC_APB1ENR_TIM4EN_Pos) /*!< 0x00000004 */ 01381 #define RCC_APB1ENR_TIM4EN RCC_APB1ENR_TIM4EN_Msk /*!< Timer 4 clock enable */ 01382 #define RCC_APB1ENR_SPI2EN_Pos (14U) 01383 #define RCC_APB1ENR_SPI2EN_Msk (0x1U << RCC_APB1ENR_SPI2EN_Pos) /*!< 0x00004000 */ 01384 #define RCC_APB1ENR_SPI2EN RCC_APB1ENR_SPI2EN_Msk /*!< SPI 2 clock enable */ 01385 #define RCC_APB1ENR_USART3EN_Pos (18U) 01386 #define RCC_APB1ENR_USART3EN_Msk (0x1U << RCC_APB1ENR_USART3EN_Pos) /*!< 0x00040000 */ 01387 #define RCC_APB1ENR_USART3EN RCC_APB1ENR_USART3EN_Msk /*!< USART 3 clock enable */ 01388 #define RCC_APB1ENR_I2C2EN_Pos (22U) 01389 #define RCC_APB1ENR_I2C2EN_Msk (0x1U << RCC_APB1ENR_I2C2EN_Pos) /*!< 0x00400000 */ 01390 #define RCC_APB1ENR_I2C2EN RCC_APB1ENR_I2C2EN_Msk /*!< I2C 2 clock enable */ 01391 01392 #define RCC_APB1ENR_USBEN_Pos (23U) 01393 #define RCC_APB1ENR_USBEN_Msk (0x1U << RCC_APB1ENR_USBEN_Pos) /*!< 0x00800000 */ 01394 #define RCC_APB1ENR_USBEN RCC_APB1ENR_USBEN_Msk /*!< USB Device clock enable */ 01395 01396 01397 01398 01399 01400 01401 /******************* Bit definition for RCC_BDCR register *******************/ 01402 #define RCC_BDCR_LSEON_Pos (0U) 01403 #define RCC_BDCR_LSEON_Msk (0x1U << RCC_BDCR_LSEON_Pos) /*!< 0x00000001 */ 01404 #define RCC_BDCR_LSEON RCC_BDCR_LSEON_Msk /*!< External Low Speed oscillator enable */ 01405 #define RCC_BDCR_LSERDY_Pos (1U) 01406 #define RCC_BDCR_LSERDY_Msk (0x1U << RCC_BDCR_LSERDY_Pos) /*!< 0x00000002 */ 01407 #define RCC_BDCR_LSERDY RCC_BDCR_LSERDY_Msk /*!< External Low Speed oscillator Ready */ 01408 #define RCC_BDCR_LSEBYP_Pos (2U) 01409 #define RCC_BDCR_LSEBYP_Msk (0x1U << RCC_BDCR_LSEBYP_Pos) /*!< 0x00000004 */ 01410 #define RCC_BDCR_LSEBYP RCC_BDCR_LSEBYP_Msk /*!< External Low Speed oscillator Bypass */ 01411 01412 #define RCC_BDCR_RTCSEL_Pos (8U) 01413 #define RCC_BDCR_RTCSEL_Msk (0x3U << RCC_BDCR_RTCSEL_Pos) /*!< 0x00000300 */ 01414 #define RCC_BDCR_RTCSEL RCC_BDCR_RTCSEL_Msk /*!< RTCSEL[1:0] bits (RTC clock source selection) */ 01415 #define RCC_BDCR_RTCSEL_0 (0x1U << RCC_BDCR_RTCSEL_Pos) /*!< 0x00000100 */ 01416 #define RCC_BDCR_RTCSEL_1 (0x2U << RCC_BDCR_RTCSEL_Pos) /*!< 0x00000200 */ 01417 01418 /*!< RTC congiguration */ 01419 #define RCC_BDCR_RTCSEL_NOCLOCK ((uint32_t)0x00000000) /*!< No clock */ 01420 #define RCC_BDCR_RTCSEL_LSE ((uint32_t)0x00000100) /*!< LSE oscillator clock used as RTC clock */ 01421 #define RCC_BDCR_RTCSEL_LSI ((uint32_t)0x00000200) /*!< LSI oscillator clock used as RTC clock */ 01422 #define RCC_BDCR_RTCSEL_HSE ((uint32_t)0x00000300) /*!< HSE oscillator clock divided by 128 used as RTC clock */ 01423 01424 #define RCC_BDCR_RTCEN_Pos (15U) 01425 #define RCC_BDCR_RTCEN_Msk (0x1U << RCC_BDCR_RTCEN_Pos) /*!< 0x00008000 */ 01426 #define RCC_BDCR_RTCEN RCC_BDCR_RTCEN_Msk /*!< RTC clock enable */ 01427 #define RCC_BDCR_BDRST_Pos (16U) 01428 #define RCC_BDCR_BDRST_Msk (0x1U << RCC_BDCR_BDRST_Pos) /*!< 0x00010000 */ 01429 #define RCC_BDCR_BDRST RCC_BDCR_BDRST_Msk /*!< Backup domain software reset */ 01430 01431 /******************* Bit definition for RCC_CSR register ********************/ 01432 #define RCC_CSR_LSION_Pos (0U) 01433 #define RCC_CSR_LSION_Msk (0x1U << RCC_CSR_LSION_Pos) /*!< 0x00000001 */ 01434 #define RCC_CSR_LSION RCC_CSR_LSION_Msk /*!< Internal Low Speed oscillator enable */ 01435 #define RCC_CSR_LSIRDY_Pos (1U) 01436 #define RCC_CSR_LSIRDY_Msk (0x1U << RCC_CSR_LSIRDY_Pos) /*!< 0x00000002 */ 01437 #define RCC_CSR_LSIRDY RCC_CSR_LSIRDY_Msk /*!< Internal Low Speed oscillator Ready */ 01438 #define RCC_CSR_RMVF_Pos (24U) 01439 #define RCC_CSR_RMVF_Msk (0x1U << RCC_CSR_RMVF_Pos) /*!< 0x01000000 */ 01440 #define RCC_CSR_RMVF RCC_CSR_RMVF_Msk /*!< Remove reset flag */ 01441 #define RCC_CSR_PINRSTF_Pos (26U) 01442 #define RCC_CSR_PINRSTF_Msk (0x1U << RCC_CSR_PINRSTF_Pos) /*!< 0x04000000 */ 01443 #define RCC_CSR_PINRSTF RCC_CSR_PINRSTF_Msk /*!< PIN reset flag */ 01444 #define RCC_CSR_PORRSTF_Pos (27U) 01445 #define RCC_CSR_PORRSTF_Msk (0x1U << RCC_CSR_PORRSTF_Pos) /*!< 0x08000000 */ 01446 #define RCC_CSR_PORRSTF RCC_CSR_PORRSTF_Msk /*!< POR/PDR reset flag */ 01447 #define RCC_CSR_SFTRSTF_Pos (28U) 01448 #define RCC_CSR_SFTRSTF_Msk (0x1U << RCC_CSR_SFTRSTF_Pos) /*!< 0x10000000 */ 01449 #define RCC_CSR_SFTRSTF RCC_CSR_SFTRSTF_Msk /*!< Software Reset flag */ 01450 #define RCC_CSR_IWDGRSTF_Pos (29U) 01451 #define RCC_CSR_IWDGRSTF_Msk (0x1U << RCC_CSR_IWDGRSTF_Pos) /*!< 0x20000000 */ 01452 #define RCC_CSR_IWDGRSTF RCC_CSR_IWDGRSTF_Msk /*!< Independent Watchdog reset flag */ 01453 #define RCC_CSR_WWDGRSTF_Pos (30U) 01454 #define RCC_CSR_WWDGRSTF_Msk (0x1U << RCC_CSR_WWDGRSTF_Pos) /*!< 0x40000000 */ 01455 #define RCC_CSR_WWDGRSTF RCC_CSR_WWDGRSTF_Msk /*!< Window watchdog reset flag */ 01456 #define RCC_CSR_LPWRRSTF_Pos (31U) 01457 #define RCC_CSR_LPWRRSTF_Msk (0x1U << RCC_CSR_LPWRRSTF_Pos) /*!< 0x80000000 */ 01458 #define RCC_CSR_LPWRRSTF RCC_CSR_LPWRRSTF_Msk /*!< Low-Power reset flag */ 01459 01460 01461 01462 /******************************************************************************/ 01463 /* */ 01464 /* General Purpose and Alternate Function I/O */ 01465 /* */ 01466 /******************************************************************************/ 01467 01468 /******************* Bit definition for GPIO_CRL register *******************/ 01469 #define GPIO_CRL_MODE_Pos (0U) 01470 #define GPIO_CRL_MODE_Msk (0x33333333U << GPIO_CRL_MODE_Pos) /*!< 0x33333333 */ 01471 #define GPIO_CRL_MODE GPIO_CRL_MODE_Msk /*!< Port x mode bits */ 01472 01473 #define GPIO_CRL_MODE0_Pos (0U) 01474 #define GPIO_CRL_MODE0_Msk (0x3U << GPIO_CRL_MODE0_Pos) /*!< 0x00000003 */ 01475 #define GPIO_CRL_MODE0 GPIO_CRL_MODE0_Msk /*!< MODE0[1:0] bits (Port x mode bits, pin 0) */ 01476 #define GPIO_CRL_MODE0_0 (0x1U << GPIO_CRL_MODE0_Pos) /*!< 0x00000001 */ 01477 #define GPIO_CRL_MODE0_1 (0x2U << GPIO_CRL_MODE0_Pos) /*!< 0x00000002 */ 01478 01479 #define GPIO_CRL_MODE1_Pos (4U) 01480 #define GPIO_CRL_MODE1_Msk (0x3U << GPIO_CRL_MODE1_Pos) /*!< 0x00000030 */ 01481 #define GPIO_CRL_MODE1 GPIO_CRL_MODE1_Msk /*!< MODE1[1:0] bits (Port x mode bits, pin 1) */ 01482 #define GPIO_CRL_MODE1_0 (0x1U << GPIO_CRL_MODE1_Pos) /*!< 0x00000010 */ 01483 #define GPIO_CRL_MODE1_1 (0x2U << GPIO_CRL_MODE1_Pos) /*!< 0x00000020 */ 01484 01485 #define GPIO_CRL_MODE2_Pos (8U) 01486 #define GPIO_CRL_MODE2_Msk (0x3U << GPIO_CRL_MODE2_Pos) /*!< 0x00000300 */ 01487 #define GPIO_CRL_MODE2 GPIO_CRL_MODE2_Msk /*!< MODE2[1:0] bits (Port x mode bits, pin 2) */ 01488 #define GPIO_CRL_MODE2_0 (0x1U << GPIO_CRL_MODE2_Pos) /*!< 0x00000100 */ 01489 #define GPIO_CRL_MODE2_1 (0x2U << GPIO_CRL_MODE2_Pos) /*!< 0x00000200 */ 01490 01491 #define GPIO_CRL_MODE3_Pos (12U) 01492 #define GPIO_CRL_MODE3_Msk (0x3U << GPIO_CRL_MODE3_Pos) /*!< 0x00003000 */ 01493 #define GPIO_CRL_MODE3 GPIO_CRL_MODE3_Msk /*!< MODE3[1:0] bits (Port x mode bits, pin 3) */ 01494 #define GPIO_CRL_MODE3_0 (0x1U << GPIO_CRL_MODE3_Pos) /*!< 0x00001000 */ 01495 #define GPIO_CRL_MODE3_1 (0x2U << GPIO_CRL_MODE3_Pos) /*!< 0x00002000 */ 01496 01497 #define GPIO_CRL_MODE4_Pos (16U) 01498 #define GPIO_CRL_MODE4_Msk (0x3U << GPIO_CRL_MODE4_Pos) /*!< 0x00030000 */ 01499 #define GPIO_CRL_MODE4 GPIO_CRL_MODE4_Msk /*!< MODE4[1:0] bits (Port x mode bits, pin 4) */ 01500 #define GPIO_CRL_MODE4_0 (0x1U << GPIO_CRL_MODE4_Pos) /*!< 0x00010000 */ 01501 #define GPIO_CRL_MODE4_1 (0x2U << GPIO_CRL_MODE4_Pos) /*!< 0x00020000 */ 01502 01503 #define GPIO_CRL_MODE5_Pos (20U) 01504 #define GPIO_CRL_MODE5_Msk (0x3U << GPIO_CRL_MODE5_Pos) /*!< 0x00300000 */ 01505 #define GPIO_CRL_MODE5 GPIO_CRL_MODE5_Msk /*!< MODE5[1:0] bits (Port x mode bits, pin 5) */ 01506 #define GPIO_CRL_MODE5_0 (0x1U << GPIO_CRL_MODE5_Pos) /*!< 0x00100000 */ 01507 #define GPIO_CRL_MODE5_1 (0x2U << GPIO_CRL_MODE5_Pos) /*!< 0x00200000 */ 01508 01509 #define GPIO_CRL_MODE6_Pos (24U) 01510 #define GPIO_CRL_MODE6_Msk (0x3U << GPIO_CRL_MODE6_Pos) /*!< 0x03000000 */ 01511 #define GPIO_CRL_MODE6 GPIO_CRL_MODE6_Msk /*!< MODE6[1:0] bits (Port x mode bits, pin 6) */ 01512 #define GPIO_CRL_MODE6_0 (0x1U << GPIO_CRL_MODE6_Pos) /*!< 0x01000000 */ 01513 #define GPIO_CRL_MODE6_1 (0x2U << GPIO_CRL_MODE6_Pos) /*!< 0x02000000 */ 01514 01515 #define GPIO_CRL_MODE7_Pos (28U) 01516 #define GPIO_CRL_MODE7_Msk (0x3U << GPIO_CRL_MODE7_Pos) /*!< 0x30000000 */ 01517 #define GPIO_CRL_MODE7 GPIO_CRL_MODE7_Msk /*!< MODE7[1:0] bits (Port x mode bits, pin 7) */ 01518 #define GPIO_CRL_MODE7_0 (0x1U << GPIO_CRL_MODE7_Pos) /*!< 0x10000000 */ 01519 #define GPIO_CRL_MODE7_1 (0x2U << GPIO_CRL_MODE7_Pos) /*!< 0x20000000 */ 01520 01521 #define GPIO_CRL_CNF_Pos (2U) 01522 #define GPIO_CRL_CNF_Msk (0x33333333U << GPIO_CRL_CNF_Pos) /*!< 0xCCCCCCCC */ 01523 #define GPIO_CRL_CNF GPIO_CRL_CNF_Msk /*!< Port x configuration bits */ 01524 01525 #define GPIO_CRL_CNF0_Pos (2U) 01526 #define GPIO_CRL_CNF0_Msk (0x3U << GPIO_CRL_CNF0_Pos) /*!< 0x0000000C */ 01527 #define GPIO_CRL_CNF0 GPIO_CRL_CNF0_Msk /*!< CNF0[1:0] bits (Port x configuration bits, pin 0) */ 01528 #define GPIO_CRL_CNF0_0 (0x1U << GPIO_CRL_CNF0_Pos) /*!< 0x00000004 */ 01529 #define GPIO_CRL_CNF0_1 (0x2U << GPIO_CRL_CNF0_Pos) /*!< 0x00000008 */ 01530 01531 #define GPIO_CRL_CNF1_Pos (6U) 01532 #define GPIO_CRL_CNF1_Msk (0x3U << GPIO_CRL_CNF1_Pos) /*!< 0x000000C0 */ 01533 #define GPIO_CRL_CNF1 GPIO_CRL_CNF1_Msk /*!< CNF1[1:0] bits (Port x configuration bits, pin 1) */ 01534 #define GPIO_CRL_CNF1_0 (0x1U << GPIO_CRL_CNF1_Pos) /*!< 0x00000040 */ 01535 #define GPIO_CRL_CNF1_1 (0x2U << GPIO_CRL_CNF1_Pos) /*!< 0x00000080 */ 01536 01537 #define GPIO_CRL_CNF2_Pos (10U) 01538 #define GPIO_CRL_CNF2_Msk (0x3U << GPIO_CRL_CNF2_Pos) /*!< 0x00000C00 */ 01539 #define GPIO_CRL_CNF2 GPIO_CRL_CNF2_Msk /*!< CNF2[1:0] bits (Port x configuration bits, pin 2) */ 01540 #define GPIO_CRL_CNF2_0 (0x1U << GPIO_CRL_CNF2_Pos) /*!< 0x00000400 */ 01541 #define GPIO_CRL_CNF2_1 (0x2U << GPIO_CRL_CNF2_Pos) /*!< 0x00000800 */ 01542 01543 #define GPIO_CRL_CNF3_Pos (14U) 01544 #define GPIO_CRL_CNF3_Msk (0x3U << GPIO_CRL_CNF3_Pos) /*!< 0x0000C000 */ 01545 #define GPIO_CRL_CNF3 GPIO_CRL_CNF3_Msk /*!< CNF3[1:0] bits (Port x configuration bits, pin 3) */ 01546 #define GPIO_CRL_CNF3_0 (0x1U << GPIO_CRL_CNF3_Pos) /*!< 0x00004000 */ 01547 #define GPIO_CRL_CNF3_1 (0x2U << GPIO_CRL_CNF3_Pos) /*!< 0x00008000 */ 01548 01549 #define GPIO_CRL_CNF4_Pos (18U) 01550 #define GPIO_CRL_CNF4_Msk (0x3U << GPIO_CRL_CNF4_Pos) /*!< 0x000C0000 */ 01551 #define GPIO_CRL_CNF4 GPIO_CRL_CNF4_Msk /*!< CNF4[1:0] bits (Port x configuration bits, pin 4) */ 01552 #define GPIO_CRL_CNF4_0 (0x1U << GPIO_CRL_CNF4_Pos) /*!< 0x00040000 */ 01553 #define GPIO_CRL_CNF4_1 (0x2U << GPIO_CRL_CNF4_Pos) /*!< 0x00080000 */ 01554 01555 #define GPIO_CRL_CNF5_Pos (22U) 01556 #define GPIO_CRL_CNF5_Msk (0x3U << GPIO_CRL_CNF5_Pos) /*!< 0x00C00000 */ 01557 #define GPIO_CRL_CNF5 GPIO_CRL_CNF5_Msk /*!< CNF5[1:0] bits (Port x configuration bits, pin 5) */ 01558 #define GPIO_CRL_CNF5_0 (0x1U << GPIO_CRL_CNF5_Pos) /*!< 0x00400000 */ 01559 #define GPIO_CRL_CNF5_1 (0x2U << GPIO_CRL_CNF5_Pos) /*!< 0x00800000 */ 01560 01561 #define GPIO_CRL_CNF6_Pos (26U) 01562 #define GPIO_CRL_CNF6_Msk (0x3U << GPIO_CRL_CNF6_Pos) /*!< 0x0C000000 */ 01563 #define GPIO_CRL_CNF6 GPIO_CRL_CNF6_Msk /*!< CNF6[1:0] bits (Port x configuration bits, pin 6) */ 01564 #define GPIO_CRL_CNF6_0 (0x1U << GPIO_CRL_CNF6_Pos) /*!< 0x04000000 */ 01565 #define GPIO_CRL_CNF6_1 (0x2U << GPIO_CRL_CNF6_Pos) /*!< 0x08000000 */ 01566 01567 #define GPIO_CRL_CNF7_Pos (30U) 01568 #define GPIO_CRL_CNF7_Msk (0x3U << GPIO_CRL_CNF7_Pos) /*!< 0xC0000000 */ 01569 #define GPIO_CRL_CNF7 GPIO_CRL_CNF7_Msk /*!< CNF7[1:0] bits (Port x configuration bits, pin 7) */ 01570 #define GPIO_CRL_CNF7_0 (0x1U << GPIO_CRL_CNF7_Pos) /*!< 0x40000000 */ 01571 #define GPIO_CRL_CNF7_1 (0x2U << GPIO_CRL_CNF7_Pos) /*!< 0x80000000 */ 01572 01573 /******************* Bit definition for GPIO_CRH register *******************/ 01574 #define GPIO_CRH_MODE_Pos (0U) 01575 #define GPIO_CRH_MODE_Msk (0x33333333U << GPIO_CRH_MODE_Pos) /*!< 0x33333333 */ 01576 #define GPIO_CRH_MODE GPIO_CRH_MODE_Msk /*!< Port x mode bits */ 01577 01578 #define GPIO_CRH_MODE8_Pos (0U) 01579 #define GPIO_CRH_MODE8_Msk (0x3U << GPIO_CRH_MODE8_Pos) /*!< 0x00000003 */ 01580 #define GPIO_CRH_MODE8 GPIO_CRH_MODE8_Msk /*!< MODE8[1:0] bits (Port x mode bits, pin 8) */ 01581 #define GPIO_CRH_MODE8_0 (0x1U << GPIO_CRH_MODE8_Pos) /*!< 0x00000001 */ 01582 #define GPIO_CRH_MODE8_1 (0x2U << GPIO_CRH_MODE8_Pos) /*!< 0x00000002 */ 01583 01584 #define GPIO_CRH_MODE9_Pos (4U) 01585 #define GPIO_CRH_MODE9_Msk (0x3U << GPIO_CRH_MODE9_Pos) /*!< 0x00000030 */ 01586 #define GPIO_CRH_MODE9 GPIO_CRH_MODE9_Msk /*!< MODE9[1:0] bits (Port x mode bits, pin 9) */ 01587 #define GPIO_CRH_MODE9_0 (0x1U << GPIO_CRH_MODE9_Pos) /*!< 0x00000010 */ 01588 #define GPIO_CRH_MODE9_1 (0x2U << GPIO_CRH_MODE9_Pos) /*!< 0x00000020 */ 01589 01590 #define GPIO_CRH_MODE10_Pos (8U) 01591 #define GPIO_CRH_MODE10_Msk (0x3U << GPIO_CRH_MODE10_Pos) /*!< 0x00000300 */ 01592 #define GPIO_CRH_MODE10 GPIO_CRH_MODE10_Msk /*!< MODE10[1:0] bits (Port x mode bits, pin 10) */ 01593 #define GPIO_CRH_MODE10_0 (0x1U << GPIO_CRH_MODE10_Pos) /*!< 0x00000100 */ 01594 #define GPIO_CRH_MODE10_1 (0x2U << GPIO_CRH_MODE10_Pos) /*!< 0x00000200 */ 01595 01596 #define GPIO_CRH_MODE11_Pos (12U) 01597 #define GPIO_CRH_MODE11_Msk (0x3U << GPIO_CRH_MODE11_Pos) /*!< 0x00003000 */ 01598 #define GPIO_CRH_MODE11 GPIO_CRH_MODE11_Msk /*!< MODE11[1:0] bits (Port x mode bits, pin 11) */ 01599 #define GPIO_CRH_MODE11_0 (0x1U << GPIO_CRH_MODE11_Pos) /*!< 0x00001000 */ 01600 #define GPIO_CRH_MODE11_1 (0x2U << GPIO_CRH_MODE11_Pos) /*!< 0x00002000 */ 01601 01602 #define GPIO_CRH_MODE12_Pos (16U) 01603 #define GPIO_CRH_MODE12_Msk (0x3U << GPIO_CRH_MODE12_Pos) /*!< 0x00030000 */ 01604 #define GPIO_CRH_MODE12 GPIO_CRH_MODE12_Msk /*!< MODE12[1:0] bits (Port x mode bits, pin 12) */ 01605 #define GPIO_CRH_MODE12_0 (0x1U << GPIO_CRH_MODE12_Pos) /*!< 0x00010000 */ 01606 #define GPIO_CRH_MODE12_1 (0x2U << GPIO_CRH_MODE12_Pos) /*!< 0x00020000 */ 01607 01608 #define GPIO_CRH_MODE13_Pos (20U) 01609 #define GPIO_CRH_MODE13_Msk (0x3U << GPIO_CRH_MODE13_Pos) /*!< 0x00300000 */ 01610 #define GPIO_CRH_MODE13 GPIO_CRH_MODE13_Msk /*!< MODE13[1:0] bits (Port x mode bits, pin 13) */ 01611 #define GPIO_CRH_MODE13_0 (0x1U << GPIO_CRH_MODE13_Pos) /*!< 0x00100000 */ 01612 #define GPIO_CRH_MODE13_1 (0x2U << GPIO_CRH_MODE13_Pos) /*!< 0x00200000 */ 01613 01614 #define GPIO_CRH_MODE14_Pos (24U) 01615 #define GPIO_CRH_MODE14_Msk (0x3U << GPIO_CRH_MODE14_Pos) /*!< 0x03000000 */ 01616 #define GPIO_CRH_MODE14 GPIO_CRH_MODE14_Msk /*!< MODE14[1:0] bits (Port x mode bits, pin 14) */ 01617 #define GPIO_CRH_MODE14_0 (0x1U << GPIO_CRH_MODE14_Pos) /*!< 0x01000000 */ 01618 #define GPIO_CRH_MODE14_1 (0x2U << GPIO_CRH_MODE14_Pos) /*!< 0x02000000 */ 01619 01620 #define GPIO_CRH_MODE15_Pos (28U) 01621 #define GPIO_CRH_MODE15_Msk (0x3U << GPIO_CRH_MODE15_Pos) /*!< 0x30000000 */ 01622 #define GPIO_CRH_MODE15 GPIO_CRH_MODE15_Msk /*!< MODE15[1:0] bits (Port x mode bits, pin 15) */ 01623 #define GPIO_CRH_MODE15_0 (0x1U << GPIO_CRH_MODE15_Pos) /*!< 0x10000000 */ 01624 #define GPIO_CRH_MODE15_1 (0x2U << GPIO_CRH_MODE15_Pos) /*!< 0x20000000 */ 01625 01626 #define GPIO_CRH_CNF_Pos (2U) 01627 #define GPIO_CRH_CNF_Msk (0x33333333U << GPIO_CRH_CNF_Pos) /*!< 0xCCCCCCCC */ 01628 #define GPIO_CRH_CNF GPIO_CRH_CNF_Msk /*!< Port x configuration bits */ 01629 01630 #define GPIO_CRH_CNF8_Pos (2U) 01631 #define GPIO_CRH_CNF8_Msk (0x3U << GPIO_CRH_CNF8_Pos) /*!< 0x0000000C */ 01632 #define GPIO_CRH_CNF8 GPIO_CRH_CNF8_Msk /*!< CNF8[1:0] bits (Port x configuration bits, pin 8) */ 01633 #define GPIO_CRH_CNF8_0 (0x1U << GPIO_CRH_CNF8_Pos) /*!< 0x00000004 */ 01634 #define GPIO_CRH_CNF8_1 (0x2U << GPIO_CRH_CNF8_Pos) /*!< 0x00000008 */ 01635 01636 #define GPIO_CRH_CNF9_Pos (6U) 01637 #define GPIO_CRH_CNF9_Msk (0x3U << GPIO_CRH_CNF9_Pos) /*!< 0x000000C0 */ 01638 #define GPIO_CRH_CNF9 GPIO_CRH_CNF9_Msk /*!< CNF9[1:0] bits (Port x configuration bits, pin 9) */ 01639 #define GPIO_CRH_CNF9_0 (0x1U << GPIO_CRH_CNF9_Pos) /*!< 0x00000040 */ 01640 #define GPIO_CRH_CNF9_1 (0x2U << GPIO_CRH_CNF9_Pos) /*!< 0x00000080 */ 01641 01642 #define GPIO_CRH_CNF10_Pos (10U) 01643 #define GPIO_CRH_CNF10_Msk (0x3U << GPIO_CRH_CNF10_Pos) /*!< 0x00000C00 */ 01644 #define GPIO_CRH_CNF10 GPIO_CRH_CNF10_Msk /*!< CNF10[1:0] bits (Port x configuration bits, pin 10) */ 01645 #define GPIO_CRH_CNF10_0 (0x1U << GPIO_CRH_CNF10_Pos) /*!< 0x00000400 */ 01646 #define GPIO_CRH_CNF10_1 (0x2U << GPIO_CRH_CNF10_Pos) /*!< 0x00000800 */ 01647 01648 #define GPIO_CRH_CNF11_Pos (14U) 01649 #define GPIO_CRH_CNF11_Msk (0x3U << GPIO_CRH_CNF11_Pos) /*!< 0x0000C000 */ 01650 #define GPIO_CRH_CNF11 GPIO_CRH_CNF11_Msk /*!< CNF11[1:0] bits (Port x configuration bits, pin 11) */ 01651 #define GPIO_CRH_CNF11_0 (0x1U << GPIO_CRH_CNF11_Pos) /*!< 0x00004000 */ 01652 #define GPIO_CRH_CNF11_1 (0x2U << GPIO_CRH_CNF11_Pos) /*!< 0x00008000 */ 01653 01654 #define GPIO_CRH_CNF12_Pos (18U) 01655 #define GPIO_CRH_CNF12_Msk (0x3U << GPIO_CRH_CNF12_Pos) /*!< 0x000C0000 */ 01656 #define GPIO_CRH_CNF12 GPIO_CRH_CNF12_Msk /*!< CNF12[1:0] bits (Port x configuration bits, pin 12) */ 01657 #define GPIO_CRH_CNF12_0 (0x1U << GPIO_CRH_CNF12_Pos) /*!< 0x00040000 */ 01658 #define GPIO_CRH_CNF12_1 (0x2U << GPIO_CRH_CNF12_Pos) /*!< 0x00080000 */ 01659 01660 #define GPIO_CRH_CNF13_Pos (22U) 01661 #define GPIO_CRH_CNF13_Msk (0x3U << GPIO_CRH_CNF13_Pos) /*!< 0x00C00000 */ 01662 #define GPIO_CRH_CNF13 GPIO_CRH_CNF13_Msk /*!< CNF13[1:0] bits (Port x configuration bits, pin 13) */ 01663 #define GPIO_CRH_CNF13_0 (0x1U << GPIO_CRH_CNF13_Pos) /*!< 0x00400000 */ 01664 #define GPIO_CRH_CNF13_1 (0x2U << GPIO_CRH_CNF13_Pos) /*!< 0x00800000 */ 01665 01666 #define GPIO_CRH_CNF14_Pos (26U) 01667 #define GPIO_CRH_CNF14_Msk (0x3U << GPIO_CRH_CNF14_Pos) /*!< 0x0C000000 */ 01668 #define GPIO_CRH_CNF14 GPIO_CRH_CNF14_Msk /*!< CNF14[1:0] bits (Port x configuration bits, pin 14) */ 01669 #define GPIO_CRH_CNF14_0 (0x1U << GPIO_CRH_CNF14_Pos) /*!< 0x04000000 */ 01670 #define GPIO_CRH_CNF14_1 (0x2U << GPIO_CRH_CNF14_Pos) /*!< 0x08000000 */ 01671 01672 #define GPIO_CRH_CNF15_Pos (30U) 01673 #define GPIO_CRH_CNF15_Msk (0x3U << GPIO_CRH_CNF15_Pos) /*!< 0xC0000000 */ 01674 #define GPIO_CRH_CNF15 GPIO_CRH_CNF15_Msk /*!< CNF15[1:0] bits (Port x configuration bits, pin 15) */ 01675 #define GPIO_CRH_CNF15_0 (0x1U << GPIO_CRH_CNF15_Pos) /*!< 0x40000000 */ 01676 #define GPIO_CRH_CNF15_1 (0x2U << GPIO_CRH_CNF15_Pos) /*!< 0x80000000 */ 01677 01678 /*!<****************** Bit definition for GPIO_IDR register *******************/ 01679 #define GPIO_IDR_IDR0_Pos (0U) 01680 #define GPIO_IDR_IDR0_Msk (0x1U << GPIO_IDR_IDR0_Pos) /*!< 0x00000001 */ 01681 #define GPIO_IDR_IDR0 GPIO_IDR_IDR0_Msk /*!< Port input data, bit 0 */ 01682 #define GPIO_IDR_IDR1_Pos (1U) 01683 #define GPIO_IDR_IDR1_Msk (0x1U << GPIO_IDR_IDR1_Pos) /*!< 0x00000002 */ 01684 #define GPIO_IDR_IDR1 GPIO_IDR_IDR1_Msk /*!< Port input data, bit 1 */ 01685 #define GPIO_IDR_IDR2_Pos (2U) 01686 #define GPIO_IDR_IDR2_Msk (0x1U << GPIO_IDR_IDR2_Pos) /*!< 0x00000004 */ 01687 #define GPIO_IDR_IDR2 GPIO_IDR_IDR2_Msk /*!< Port input data, bit 2 */ 01688 #define GPIO_IDR_IDR3_Pos (3U) 01689 #define GPIO_IDR_IDR3_Msk (0x1U << GPIO_IDR_IDR3_Pos) /*!< 0x00000008 */ 01690 #define GPIO_IDR_IDR3 GPIO_IDR_IDR3_Msk /*!< Port input data, bit 3 */ 01691 #define GPIO_IDR_IDR4_Pos (4U) 01692 #define GPIO_IDR_IDR4_Msk (0x1U << GPIO_IDR_IDR4_Pos) /*!< 0x00000010 */ 01693 #define GPIO_IDR_IDR4 GPIO_IDR_IDR4_Msk /*!< Port input data, bit 4 */ 01694 #define GPIO_IDR_IDR5_Pos (5U) 01695 #define GPIO_IDR_IDR5_Msk (0x1U << GPIO_IDR_IDR5_Pos) /*!< 0x00000020 */ 01696 #define GPIO_IDR_IDR5 GPIO_IDR_IDR5_Msk /*!< Port input data, bit 5 */ 01697 #define GPIO_IDR_IDR6_Pos (6U) 01698 #define GPIO_IDR_IDR6_Msk (0x1U << GPIO_IDR_IDR6_Pos) /*!< 0x00000040 */ 01699 #define GPIO_IDR_IDR6 GPIO_IDR_IDR6_Msk /*!< Port input data, bit 6 */ 01700 #define GPIO_IDR_IDR7_Pos (7U) 01701 #define GPIO_IDR_IDR7_Msk (0x1U << GPIO_IDR_IDR7_Pos) /*!< 0x00000080 */ 01702 #define GPIO_IDR_IDR7 GPIO_IDR_IDR7_Msk /*!< Port input data, bit 7 */ 01703 #define GPIO_IDR_IDR8_Pos (8U) 01704 #define GPIO_IDR_IDR8_Msk (0x1U << GPIO_IDR_IDR8_Pos) /*!< 0x00000100 */ 01705 #define GPIO_IDR_IDR8 GPIO_IDR_IDR8_Msk /*!< Port input data, bit 8 */ 01706 #define GPIO_IDR_IDR9_Pos (9U) 01707 #define GPIO_IDR_IDR9_Msk (0x1U << GPIO_IDR_IDR9_Pos) /*!< 0x00000200 */ 01708 #define GPIO_IDR_IDR9 GPIO_IDR_IDR9_Msk /*!< Port input data, bit 9 */ 01709 #define GPIO_IDR_IDR10_Pos (10U) 01710 #define GPIO_IDR_IDR10_Msk (0x1U << GPIO_IDR_IDR10_Pos) /*!< 0x00000400 */ 01711 #define GPIO_IDR_IDR10 GPIO_IDR_IDR10_Msk /*!< Port input data, bit 10 */ 01712 #define GPIO_IDR_IDR11_Pos (11U) 01713 #define GPIO_IDR_IDR11_Msk (0x1U << GPIO_IDR_IDR11_Pos) /*!< 0x00000800 */ 01714 #define GPIO_IDR_IDR11 GPIO_IDR_IDR11_Msk /*!< Port input data, bit 11 */ 01715 #define GPIO_IDR_IDR12_Pos (12U) 01716 #define GPIO_IDR_IDR12_Msk (0x1U << GPIO_IDR_IDR12_Pos) /*!< 0x00001000 */ 01717 #define GPIO_IDR_IDR12 GPIO_IDR_IDR12_Msk /*!< Port input data, bit 12 */ 01718 #define GPIO_IDR_IDR13_Pos (13U) 01719 #define GPIO_IDR_IDR13_Msk (0x1U << GPIO_IDR_IDR13_Pos) /*!< 0x00002000 */ 01720 #define GPIO_IDR_IDR13 GPIO_IDR_IDR13_Msk /*!< Port input data, bit 13 */ 01721 #define GPIO_IDR_IDR14_Pos (14U) 01722 #define GPIO_IDR_IDR14_Msk (0x1U << GPIO_IDR_IDR14_Pos) /*!< 0x00004000 */ 01723 #define GPIO_IDR_IDR14 GPIO_IDR_IDR14_Msk /*!< Port input data, bit 14 */ 01724 #define GPIO_IDR_IDR15_Pos (15U) 01725 #define GPIO_IDR_IDR15_Msk (0x1U << GPIO_IDR_IDR15_Pos) /*!< 0x00008000 */ 01726 #define GPIO_IDR_IDR15 GPIO_IDR_IDR15_Msk /*!< Port input data, bit 15 */ 01727 01728 /******************* Bit definition for GPIO_ODR register *******************/ 01729 #define GPIO_ODR_ODR0_Pos (0U) 01730 #define GPIO_ODR_ODR0_Msk (0x1U << GPIO_ODR_ODR0_Pos) /*!< 0x00000001 */ 01731 #define GPIO_ODR_ODR0 GPIO_ODR_ODR0_Msk /*!< Port output data, bit 0 */ 01732 #define GPIO_ODR_ODR1_Pos (1U) 01733 #define GPIO_ODR_ODR1_Msk (0x1U << GPIO_ODR_ODR1_Pos) /*!< 0x00000002 */ 01734 #define GPIO_ODR_ODR1 GPIO_ODR_ODR1_Msk /*!< Port output data, bit 1 */ 01735 #define GPIO_ODR_ODR2_Pos (2U) 01736 #define GPIO_ODR_ODR2_Msk (0x1U << GPIO_ODR_ODR2_Pos) /*!< 0x00000004 */ 01737 #define GPIO_ODR_ODR2 GPIO_ODR_ODR2_Msk /*!< Port output data, bit 2 */ 01738 #define GPIO_ODR_ODR3_Pos (3U) 01739 #define GPIO_ODR_ODR3_Msk (0x1U << GPIO_ODR_ODR3_Pos) /*!< 0x00000008 */ 01740 #define GPIO_ODR_ODR3 GPIO_ODR_ODR3_Msk /*!< Port output data, bit 3 */ 01741 #define GPIO_ODR_ODR4_Pos (4U) 01742 #define GPIO_ODR_ODR4_Msk (0x1U << GPIO_ODR_ODR4_Pos) /*!< 0x00000010 */ 01743 #define GPIO_ODR_ODR4 GPIO_ODR_ODR4_Msk /*!< Port output data, bit 4 */ 01744 #define GPIO_ODR_ODR5_Pos (5U) 01745 #define GPIO_ODR_ODR5_Msk (0x1U << GPIO_ODR_ODR5_Pos) /*!< 0x00000020 */ 01746 #define GPIO_ODR_ODR5 GPIO_ODR_ODR5_Msk /*!< Port output data, bit 5 */ 01747 #define GPIO_ODR_ODR6_Pos (6U) 01748 #define GPIO_ODR_ODR6_Msk (0x1U << GPIO_ODR_ODR6_Pos) /*!< 0x00000040 */ 01749 #define GPIO_ODR_ODR6 GPIO_ODR_ODR6_Msk /*!< Port output data, bit 6 */ 01750 #define GPIO_ODR_ODR7_Pos (7U) 01751 #define GPIO_ODR_ODR7_Msk (0x1U << GPIO_ODR_ODR7_Pos) /*!< 0x00000080 */ 01752 #define GPIO_ODR_ODR7 GPIO_ODR_ODR7_Msk /*!< Port output data, bit 7 */ 01753 #define GPIO_ODR_ODR8_Pos (8U) 01754 #define GPIO_ODR_ODR8_Msk (0x1U << GPIO_ODR_ODR8_Pos) /*!< 0x00000100 */ 01755 #define GPIO_ODR_ODR8 GPIO_ODR_ODR8_Msk /*!< Port output data, bit 8 */ 01756 #define GPIO_ODR_ODR9_Pos (9U) 01757 #define GPIO_ODR_ODR9_Msk (0x1U << GPIO_ODR_ODR9_Pos) /*!< 0x00000200 */ 01758 #define GPIO_ODR_ODR9 GPIO_ODR_ODR9_Msk /*!< Port output data, bit 9 */ 01759 #define GPIO_ODR_ODR10_Pos (10U) 01760 #define GPIO_ODR_ODR10_Msk (0x1U << GPIO_ODR_ODR10_Pos) /*!< 0x00000400 */ 01761 #define GPIO_ODR_ODR10 GPIO_ODR_ODR10_Msk /*!< Port output data, bit 10 */ 01762 #define GPIO_ODR_ODR11_Pos (11U) 01763 #define GPIO_ODR_ODR11_Msk (0x1U << GPIO_ODR_ODR11_Pos) /*!< 0x00000800 */ 01764 #define GPIO_ODR_ODR11 GPIO_ODR_ODR11_Msk /*!< Port output data, bit 11 */ 01765 #define GPIO_ODR_ODR12_Pos (12U) 01766 #define GPIO_ODR_ODR12_Msk (0x1U << GPIO_ODR_ODR12_Pos) /*!< 0x00001000 */ 01767 #define GPIO_ODR_ODR12 GPIO_ODR_ODR12_Msk /*!< Port output data, bit 12 */ 01768 #define GPIO_ODR_ODR13_Pos (13U) 01769 #define GPIO_ODR_ODR13_Msk (0x1U << GPIO_ODR_ODR13_Pos) /*!< 0x00002000 */ 01770 #define GPIO_ODR_ODR13 GPIO_ODR_ODR13_Msk /*!< Port output data, bit 13 */ 01771 #define GPIO_ODR_ODR14_Pos (14U) 01772 #define GPIO_ODR_ODR14_Msk (0x1U << GPIO_ODR_ODR14_Pos) /*!< 0x00004000 */ 01773 #define GPIO_ODR_ODR14 GPIO_ODR_ODR14_Msk /*!< Port output data, bit 14 */ 01774 #define GPIO_ODR_ODR15_Pos (15U) 01775 #define GPIO_ODR_ODR15_Msk (0x1U << GPIO_ODR_ODR15_Pos) /*!< 0x00008000 */ 01776 #define GPIO_ODR_ODR15 GPIO_ODR_ODR15_Msk /*!< Port output data, bit 15 */ 01777 01778 /****************** Bit definition for GPIO_BSRR register *******************/ 01779 #define GPIO_BSRR_BS0_Pos (0U) 01780 #define GPIO_BSRR_BS0_Msk (0x1U << GPIO_BSRR_BS0_Pos) /*!< 0x00000001 */ 01781 #define GPIO_BSRR_BS0 GPIO_BSRR_BS0_Msk /*!< Port x Set bit 0 */ 01782 #define GPIO_BSRR_BS1_Pos (1U) 01783 #define GPIO_BSRR_BS1_Msk (0x1U << GPIO_BSRR_BS1_Pos) /*!< 0x00000002 */ 01784 #define GPIO_BSRR_BS1 GPIO_BSRR_BS1_Msk /*!< Port x Set bit 1 */ 01785 #define GPIO_BSRR_BS2_Pos (2U) 01786 #define GPIO_BSRR_BS2_Msk (0x1U << GPIO_BSRR_BS2_Pos) /*!< 0x00000004 */ 01787 #define GPIO_BSRR_BS2 GPIO_BSRR_BS2_Msk /*!< Port x Set bit 2 */ 01788 #define GPIO_BSRR_BS3_Pos (3U) 01789 #define GPIO_BSRR_BS3_Msk (0x1U << GPIO_BSRR_BS3_Pos) /*!< 0x00000008 */ 01790 #define GPIO_BSRR_BS3 GPIO_BSRR_BS3_Msk /*!< Port x Set bit 3 */ 01791 #define GPIO_BSRR_BS4_Pos (4U) 01792 #define GPIO_BSRR_BS4_Msk (0x1U << GPIO_BSRR_BS4_Pos) /*!< 0x00000010 */ 01793 #define GPIO_BSRR_BS4 GPIO_BSRR_BS4_Msk /*!< Port x Set bit 4 */ 01794 #define GPIO_BSRR_BS5_Pos (5U) 01795 #define GPIO_BSRR_BS5_Msk (0x1U << GPIO_BSRR_BS5_Pos) /*!< 0x00000020 */ 01796 #define GPIO_BSRR_BS5 GPIO_BSRR_BS5_Msk /*!< Port x Set bit 5 */ 01797 #define GPIO_BSRR_BS6_Pos (6U) 01798 #define GPIO_BSRR_BS6_Msk (0x1U << GPIO_BSRR_BS6_Pos) /*!< 0x00000040 */ 01799 #define GPIO_BSRR_BS6 GPIO_BSRR_BS6_Msk /*!< Port x Set bit 6 */ 01800 #define GPIO_BSRR_BS7_Pos (7U) 01801 #define GPIO_BSRR_BS7_Msk (0x1U << GPIO_BSRR_BS7_Pos) /*!< 0x00000080 */ 01802 #define GPIO_BSRR_BS7 GPIO_BSRR_BS7_Msk /*!< Port x Set bit 7 */ 01803 #define GPIO_BSRR_BS8_Pos (8U) 01804 #define GPIO_BSRR_BS8_Msk (0x1U << GPIO_BSRR_BS8_Pos) /*!< 0x00000100 */ 01805 #define GPIO_BSRR_BS8 GPIO_BSRR_BS8_Msk /*!< Port x Set bit 8 */ 01806 #define GPIO_BSRR_BS9_Pos (9U) 01807 #define GPIO_BSRR_BS9_Msk (0x1U << GPIO_BSRR_BS9_Pos) /*!< 0x00000200 */ 01808 #define GPIO_BSRR_BS9 GPIO_BSRR_BS9_Msk /*!< Port x Set bit 9 */ 01809 #define GPIO_BSRR_BS10_Pos (10U) 01810 #define GPIO_BSRR_BS10_Msk (0x1U << GPIO_BSRR_BS10_Pos) /*!< 0x00000400 */ 01811 #define GPIO_BSRR_BS10 GPIO_BSRR_BS10_Msk /*!< Port x Set bit 10 */ 01812 #define GPIO_BSRR_BS11_Pos (11U) 01813 #define GPIO_BSRR_BS11_Msk (0x1U << GPIO_BSRR_BS11_Pos) /*!< 0x00000800 */ 01814 #define GPIO_BSRR_BS11 GPIO_BSRR_BS11_Msk /*!< Port x Set bit 11 */ 01815 #define GPIO_BSRR_BS12_Pos (12U) 01816 #define GPIO_BSRR_BS12_Msk (0x1U << GPIO_BSRR_BS12_Pos) /*!< 0x00001000 */ 01817 #define GPIO_BSRR_BS12 GPIO_BSRR_BS12_Msk /*!< Port x Set bit 12 */ 01818 #define GPIO_BSRR_BS13_Pos (13U) 01819 #define GPIO_BSRR_BS13_Msk (0x1U << GPIO_BSRR_BS13_Pos) /*!< 0x00002000 */ 01820 #define GPIO_BSRR_BS13 GPIO_BSRR_BS13_Msk /*!< Port x Set bit 13 */ 01821 #define GPIO_BSRR_BS14_Pos (14U) 01822 #define GPIO_BSRR_BS14_Msk (0x1U << GPIO_BSRR_BS14_Pos) /*!< 0x00004000 */ 01823 #define GPIO_BSRR_BS14 GPIO_BSRR_BS14_Msk /*!< Port x Set bit 14 */ 01824 #define GPIO_BSRR_BS15_Pos (15U) 01825 #define GPIO_BSRR_BS15_Msk (0x1U << GPIO_BSRR_BS15_Pos) /*!< 0x00008000 */ 01826 #define GPIO_BSRR_BS15 GPIO_BSRR_BS15_Msk /*!< Port x Set bit 15 */ 01827 01828 #define GPIO_BSRR_BR0_Pos (16U) 01829 #define GPIO_BSRR_BR0_Msk (0x1U << GPIO_BSRR_BR0_Pos) /*!< 0x00010000 */ 01830 #define GPIO_BSRR_BR0 GPIO_BSRR_BR0_Msk /*!< Port x Reset bit 0 */ 01831 #define GPIO_BSRR_BR1_Pos (17U) 01832 #define GPIO_BSRR_BR1_Msk (0x1U << GPIO_BSRR_BR1_Pos) /*!< 0x00020000 */ 01833 #define GPIO_BSRR_BR1 GPIO_BSRR_BR1_Msk /*!< Port x Reset bit 1 */ 01834 #define GPIO_BSRR_BR2_Pos (18U) 01835 #define GPIO_BSRR_BR2_Msk (0x1U << GPIO_BSRR_BR2_Pos) /*!< 0x00040000 */ 01836 #define GPIO_BSRR_BR2 GPIO_BSRR_BR2_Msk /*!< Port x Reset bit 2 */ 01837 #define GPIO_BSRR_BR3_Pos (19U) 01838 #define GPIO_BSRR_BR3_Msk (0x1U << GPIO_BSRR_BR3_Pos) /*!< 0x00080000 */ 01839 #define GPIO_BSRR_BR3 GPIO_BSRR_BR3_Msk /*!< Port x Reset bit 3 */ 01840 #define GPIO_BSRR_BR4_Pos (20U) 01841 #define GPIO_BSRR_BR4_Msk (0x1U << GPIO_BSRR_BR4_Pos) /*!< 0x00100000 */ 01842 #define GPIO_BSRR_BR4 GPIO_BSRR_BR4_Msk /*!< Port x Reset bit 4 */ 01843 #define GPIO_BSRR_BR5_Pos (21U) 01844 #define GPIO_BSRR_BR5_Msk (0x1U << GPIO_BSRR_BR5_Pos) /*!< 0x00200000 */ 01845 #define GPIO_BSRR_BR5 GPIO_BSRR_BR5_Msk /*!< Port x Reset bit 5 */ 01846 #define GPIO_BSRR_BR6_Pos (22U) 01847 #define GPIO_BSRR_BR6_Msk (0x1U << GPIO_BSRR_BR6_Pos) /*!< 0x00400000 */ 01848 #define GPIO_BSRR_BR6 GPIO_BSRR_BR6_Msk /*!< Port x Reset bit 6 */ 01849 #define GPIO_BSRR_BR7_Pos (23U) 01850 #define GPIO_BSRR_BR7_Msk (0x1U << GPIO_BSRR_BR7_Pos) /*!< 0x00800000 */ 01851 #define GPIO_BSRR_BR7 GPIO_BSRR_BR7_Msk /*!< Port x Reset bit 7 */ 01852 #define GPIO_BSRR_BR8_Pos (24U) 01853 #define GPIO_BSRR_BR8_Msk (0x1U << GPIO_BSRR_BR8_Pos) /*!< 0x01000000 */ 01854 #define GPIO_BSRR_BR8 GPIO_BSRR_BR8_Msk /*!< Port x Reset bit 8 */ 01855 #define GPIO_BSRR_BR9_Pos (25U) 01856 #define GPIO_BSRR_BR9_Msk (0x1U << GPIO_BSRR_BR9_Pos) /*!< 0x02000000 */ 01857 #define GPIO_BSRR_BR9 GPIO_BSRR_BR9_Msk /*!< Port x Reset bit 9 */ 01858 #define GPIO_BSRR_BR10_Pos (26U) 01859 #define GPIO_BSRR_BR10_Msk (0x1U << GPIO_BSRR_BR10_Pos) /*!< 0x04000000 */ 01860 #define GPIO_BSRR_BR10 GPIO_BSRR_BR10_Msk /*!< Port x Reset bit 10 */ 01861 #define GPIO_BSRR_BR11_Pos (27U) 01862 #define GPIO_BSRR_BR11_Msk (0x1U << GPIO_BSRR_BR11_Pos) /*!< 0x08000000 */ 01863 #define GPIO_BSRR_BR11 GPIO_BSRR_BR11_Msk /*!< Port x Reset bit 11 */ 01864 #define GPIO_BSRR_BR12_Pos (28U) 01865 #define GPIO_BSRR_BR12_Msk (0x1U << GPIO_BSRR_BR12_Pos) /*!< 0x10000000 */ 01866 #define GPIO_BSRR_BR12 GPIO_BSRR_BR12_Msk /*!< Port x Reset bit 12 */ 01867 #define GPIO_BSRR_BR13_Pos (29U) 01868 #define GPIO_BSRR_BR13_Msk (0x1U << GPIO_BSRR_BR13_Pos) /*!< 0x20000000 */ 01869 #define GPIO_BSRR_BR13 GPIO_BSRR_BR13_Msk /*!< Port x Reset bit 13 */ 01870 #define GPIO_BSRR_BR14_Pos (30U) 01871 #define GPIO_BSRR_BR14_Msk (0x1U << GPIO_BSRR_BR14_Pos) /*!< 0x40000000 */ 01872 #define GPIO_BSRR_BR14 GPIO_BSRR_BR14_Msk /*!< Port x Reset bit 14 */ 01873 #define GPIO_BSRR_BR15_Pos (31U) 01874 #define GPIO_BSRR_BR15_Msk (0x1U << GPIO_BSRR_BR15_Pos) /*!< 0x80000000 */ 01875 #define GPIO_BSRR_BR15 GPIO_BSRR_BR15_Msk /*!< Port x Reset bit 15 */ 01876 01877 /******************* Bit definition for GPIO_BRR register *******************/ 01878 #define GPIO_BRR_BR0_Pos (0U) 01879 #define GPIO_BRR_BR0_Msk (0x1U << GPIO_BRR_BR0_Pos) /*!< 0x00000001 */ 01880 #define GPIO_BRR_BR0 GPIO_BRR_BR0_Msk /*!< Port x Reset bit 0 */ 01881 #define GPIO_BRR_BR1_Pos (1U) 01882 #define GPIO_BRR_BR1_Msk (0x1U << GPIO_BRR_BR1_Pos) /*!< 0x00000002 */ 01883 #define GPIO_BRR_BR1 GPIO_BRR_BR1_Msk /*!< Port x Reset bit 1 */ 01884 #define GPIO_BRR_BR2_Pos (2U) 01885 #define GPIO_BRR_BR2_Msk (0x1U << GPIO_BRR_BR2_Pos) /*!< 0x00000004 */ 01886 #define GPIO_BRR_BR2 GPIO_BRR_BR2_Msk /*!< Port x Reset bit 2 */ 01887 #define GPIO_BRR_BR3_Pos (3U) 01888 #define GPIO_BRR_BR3_Msk (0x1U << GPIO_BRR_BR3_Pos) /*!< 0x00000008 */ 01889 #define GPIO_BRR_BR3 GPIO_BRR_BR3_Msk /*!< Port x Reset bit 3 */ 01890 #define GPIO_BRR_BR4_Pos (4U) 01891 #define GPIO_BRR_BR4_Msk (0x1U << GPIO_BRR_BR4_Pos) /*!< 0x00000010 */ 01892 #define GPIO_BRR_BR4 GPIO_BRR_BR4_Msk /*!< Port x Reset bit 4 */ 01893 #define GPIO_BRR_BR5_Pos (5U) 01894 #define GPIO_BRR_BR5_Msk (0x1U << GPIO_BRR_BR5_Pos) /*!< 0x00000020 */ 01895 #define GPIO_BRR_BR5 GPIO_BRR_BR5_Msk /*!< Port x Reset bit 5 */ 01896 #define GPIO_BRR_BR6_Pos (6U) 01897 #define GPIO_BRR_BR6_Msk (0x1U << GPIO_BRR_BR6_Pos) /*!< 0x00000040 */ 01898 #define GPIO_BRR_BR6 GPIO_BRR_BR6_Msk /*!< Port x Reset bit 6 */ 01899 #define GPIO_BRR_BR7_Pos (7U) 01900 #define GPIO_BRR_BR7_Msk (0x1U << GPIO_BRR_BR7_Pos) /*!< 0x00000080 */ 01901 #define GPIO_BRR_BR7 GPIO_BRR_BR7_Msk /*!< Port x Reset bit 7 */ 01902 #define GPIO_BRR_BR8_Pos (8U) 01903 #define GPIO_BRR_BR8_Msk (0x1U << GPIO_BRR_BR8_Pos) /*!< 0x00000100 */ 01904 #define GPIO_BRR_BR8 GPIO_BRR_BR8_Msk /*!< Port x Reset bit 8 */ 01905 #define GPIO_BRR_BR9_Pos (9U) 01906 #define GPIO_BRR_BR9_Msk (0x1U << GPIO_BRR_BR9_Pos) /*!< 0x00000200 */ 01907 #define GPIO_BRR_BR9 GPIO_BRR_BR9_Msk /*!< Port x Reset bit 9 */ 01908 #define GPIO_BRR_BR10_Pos (10U) 01909 #define GPIO_BRR_BR10_Msk (0x1U << GPIO_BRR_BR10_Pos) /*!< 0x00000400 */ 01910 #define GPIO_BRR_BR10 GPIO_BRR_BR10_Msk /*!< Port x Reset bit 10 */ 01911 #define GPIO_BRR_BR11_Pos (11U) 01912 #define GPIO_BRR_BR11_Msk (0x1U << GPIO_BRR_BR11_Pos) /*!< 0x00000800 */ 01913 #define GPIO_BRR_BR11 GPIO_BRR_BR11_Msk /*!< Port x Reset bit 11 */ 01914 #define GPIO_BRR_BR12_Pos (12U) 01915 #define GPIO_BRR_BR12_Msk (0x1U << GPIO_BRR_BR12_Pos) /*!< 0x00001000 */ 01916 #define GPIO_BRR_BR12 GPIO_BRR_BR12_Msk /*!< Port x Reset bit 12 */ 01917 #define GPIO_BRR_BR13_Pos (13U) 01918 #define GPIO_BRR_BR13_Msk (0x1U << GPIO_BRR_BR13_Pos) /*!< 0x00002000 */ 01919 #define GPIO_BRR_BR13 GPIO_BRR_BR13_Msk /*!< Port x Reset bit 13 */ 01920 #define GPIO_BRR_BR14_Pos (14U) 01921 #define GPIO_BRR_BR14_Msk (0x1U << GPIO_BRR_BR14_Pos) /*!< 0x00004000 */ 01922 #define GPIO_BRR_BR14 GPIO_BRR_BR14_Msk /*!< Port x Reset bit 14 */ 01923 #define GPIO_BRR_BR15_Pos (15U) 01924 #define GPIO_BRR_BR15_Msk (0x1U << GPIO_BRR_BR15_Pos) /*!< 0x00008000 */ 01925 #define GPIO_BRR_BR15 GPIO_BRR_BR15_Msk /*!< Port x Reset bit 15 */ 01926 01927 /****************** Bit definition for GPIO_LCKR register *******************/ 01928 #define GPIO_LCKR_LCK0_Pos (0U) 01929 #define GPIO_LCKR_LCK0_Msk (0x1U << GPIO_LCKR_LCK0_Pos) /*!< 0x00000001 */ 01930 #define GPIO_LCKR_LCK0 GPIO_LCKR_LCK0_Msk /*!< Port x Lock bit 0 */ 01931 #define GPIO_LCKR_LCK1_Pos (1U) 01932 #define GPIO_LCKR_LCK1_Msk (0x1U << GPIO_LCKR_LCK1_Pos) /*!< 0x00000002 */ 01933 #define GPIO_LCKR_LCK1 GPIO_LCKR_LCK1_Msk /*!< Port x Lock bit 1 */ 01934 #define GPIO_LCKR_LCK2_Pos (2U) 01935 #define GPIO_LCKR_LCK2_Msk (0x1U << GPIO_LCKR_LCK2_Pos) /*!< 0x00000004 */ 01936 #define GPIO_LCKR_LCK2 GPIO_LCKR_LCK2_Msk /*!< Port x Lock bit 2 */ 01937 #define GPIO_LCKR_LCK3_Pos (3U) 01938 #define GPIO_LCKR_LCK3_Msk (0x1U << GPIO_LCKR_LCK3_Pos) /*!< 0x00000008 */ 01939 #define GPIO_LCKR_LCK3 GPIO_LCKR_LCK3_Msk /*!< Port x Lock bit 3 */ 01940 #define GPIO_LCKR_LCK4_Pos (4U) 01941 #define GPIO_LCKR_LCK4_Msk (0x1U << GPIO_LCKR_LCK4_Pos) /*!< 0x00000010 */ 01942 #define GPIO_LCKR_LCK4 GPIO_LCKR_LCK4_Msk /*!< Port x Lock bit 4 */ 01943 #define GPIO_LCKR_LCK5_Pos (5U) 01944 #define GPIO_LCKR_LCK5_Msk (0x1U << GPIO_LCKR_LCK5_Pos) /*!< 0x00000020 */ 01945 #define GPIO_LCKR_LCK5 GPIO_LCKR_LCK5_Msk /*!< Port x Lock bit 5 */ 01946 #define GPIO_LCKR_LCK6_Pos (6U) 01947 #define GPIO_LCKR_LCK6_Msk (0x1U << GPIO_LCKR_LCK6_Pos) /*!< 0x00000040 */ 01948 #define GPIO_LCKR_LCK6 GPIO_LCKR_LCK6_Msk /*!< Port x Lock bit 6 */ 01949 #define GPIO_LCKR_LCK7_Pos (7U) 01950 #define GPIO_LCKR_LCK7_Msk (0x1U << GPIO_LCKR_LCK7_Pos) /*!< 0x00000080 */ 01951 #define GPIO_LCKR_LCK7 GPIO_LCKR_LCK7_Msk /*!< Port x Lock bit 7 */ 01952 #define GPIO_LCKR_LCK8_Pos (8U) 01953 #define GPIO_LCKR_LCK8_Msk (0x1U << GPIO_LCKR_LCK8_Pos) /*!< 0x00000100 */ 01954 #define GPIO_LCKR_LCK8 GPIO_LCKR_LCK8_Msk /*!< Port x Lock bit 8 */ 01955 #define GPIO_LCKR_LCK9_Pos (9U) 01956 #define GPIO_LCKR_LCK9_Msk (0x1U << GPIO_LCKR_LCK9_Pos) /*!< 0x00000200 */ 01957 #define GPIO_LCKR_LCK9 GPIO_LCKR_LCK9_Msk /*!< Port x Lock bit 9 */ 01958 #define GPIO_LCKR_LCK10_Pos (10U) 01959 #define GPIO_LCKR_LCK10_Msk (0x1U << GPIO_LCKR_LCK10_Pos) /*!< 0x00000400 */ 01960 #define GPIO_LCKR_LCK10 GPIO_LCKR_LCK10_Msk /*!< Port x Lock bit 10 */ 01961 #define GPIO_LCKR_LCK11_Pos (11U) 01962 #define GPIO_LCKR_LCK11_Msk (0x1U << GPIO_LCKR_LCK11_Pos) /*!< 0x00000800 */ 01963 #define GPIO_LCKR_LCK11 GPIO_LCKR_LCK11_Msk /*!< Port x Lock bit 11 */ 01964 #define GPIO_LCKR_LCK12_Pos (12U) 01965 #define GPIO_LCKR_LCK12_Msk (0x1U << GPIO_LCKR_LCK12_Pos) /*!< 0x00001000 */ 01966 #define GPIO_LCKR_LCK12 GPIO_LCKR_LCK12_Msk /*!< Port x Lock bit 12 */ 01967 #define GPIO_LCKR_LCK13_Pos (13U) 01968 #define GPIO_LCKR_LCK13_Msk (0x1U << GPIO_LCKR_LCK13_Pos) /*!< 0x00002000 */ 01969 #define GPIO_LCKR_LCK13 GPIO_LCKR_LCK13_Msk /*!< Port x Lock bit 13 */ 01970 #define GPIO_LCKR_LCK14_Pos (14U) 01971 #define GPIO_LCKR_LCK14_Msk (0x1U << GPIO_LCKR_LCK14_Pos) /*!< 0x00004000 */ 01972 #define GPIO_LCKR_LCK14 GPIO_LCKR_LCK14_Msk /*!< Port x Lock bit 14 */ 01973 #define GPIO_LCKR_LCK15_Pos (15U) 01974 #define GPIO_LCKR_LCK15_Msk (0x1U << GPIO_LCKR_LCK15_Pos) /*!< 0x00008000 */ 01975 #define GPIO_LCKR_LCK15 GPIO_LCKR_LCK15_Msk /*!< Port x Lock bit 15 */ 01976 #define GPIO_LCKR_LCKK_Pos (16U) 01977 #define GPIO_LCKR_LCKK_Msk (0x1U << GPIO_LCKR_LCKK_Pos) /*!< 0x00010000 */ 01978 #define GPIO_LCKR_LCKK GPIO_LCKR_LCKK_Msk /*!< Lock key */ 01979 01980 /*----------------------------------------------------------------------------*/ 01981 01982 /****************** Bit definition for AFIO_EVCR register *******************/ 01983 #define AFIO_EVCR_PIN_Pos (0U) 01984 #define AFIO_EVCR_PIN_Msk (0xFU << AFIO_EVCR_PIN_Pos) /*!< 0x0000000F */ 01985 #define AFIO_EVCR_PIN AFIO_EVCR_PIN_Msk /*!< PIN[3:0] bits (Pin selection) */ 01986 #define AFIO_EVCR_PIN_0 (0x1U << AFIO_EVCR_PIN_Pos) /*!< 0x00000001 */ 01987 #define AFIO_EVCR_PIN_1 (0x2U << AFIO_EVCR_PIN_Pos) /*!< 0x00000002 */ 01988 #define AFIO_EVCR_PIN_2 (0x4U << AFIO_EVCR_PIN_Pos) /*!< 0x00000004 */ 01989 #define AFIO_EVCR_PIN_3 (0x8U << AFIO_EVCR_PIN_Pos) /*!< 0x00000008 */ 01990 01991 /*!< PIN configuration */ 01992 #define AFIO_EVCR_PIN_PX0 ((uint32_t)0x00000000) /*!< Pin 0 selected */ 01993 #define AFIO_EVCR_PIN_PX1_Pos (0U) 01994 #define AFIO_EVCR_PIN_PX1_Msk (0x1U << AFIO_EVCR_PIN_PX1_Pos) /*!< 0x00000001 */ 01995 #define AFIO_EVCR_PIN_PX1 AFIO_EVCR_PIN_PX1_Msk /*!< Pin 1 selected */ 01996 #define AFIO_EVCR_PIN_PX2_Pos (1U) 01997 #define AFIO_EVCR_PIN_PX2_Msk (0x1U << AFIO_EVCR_PIN_PX2_Pos) /*!< 0x00000002 */ 01998 #define AFIO_EVCR_PIN_PX2 AFIO_EVCR_PIN_PX2_Msk /*!< Pin 2 selected */ 01999 #define AFIO_EVCR_PIN_PX3_Pos (0U) 02000 #define AFIO_EVCR_PIN_PX3_Msk (0x3U << AFIO_EVCR_PIN_PX3_Pos) /*!< 0x00000003 */ 02001 #define AFIO_EVCR_PIN_PX3 AFIO_EVCR_PIN_PX3_Msk /*!< Pin 3 selected */ 02002 #define AFIO_EVCR_PIN_PX4_Pos (2U) 02003 #define AFIO_EVCR_PIN_PX4_Msk (0x1U << AFIO_EVCR_PIN_PX4_Pos) /*!< 0x00000004 */ 02004 #define AFIO_EVCR_PIN_PX4 AFIO_EVCR_PIN_PX4_Msk /*!< Pin 4 selected */ 02005 #define AFIO_EVCR_PIN_PX5_Pos (0U) 02006 #define AFIO_EVCR_PIN_PX5_Msk (0x5U << AFIO_EVCR_PIN_PX5_Pos) /*!< 0x00000005 */ 02007 #define AFIO_EVCR_PIN_PX5 AFIO_EVCR_PIN_PX5_Msk /*!< Pin 5 selected */ 02008 #define AFIO_EVCR_PIN_PX6_Pos (1U) 02009 #define AFIO_EVCR_PIN_PX6_Msk (0x3U << AFIO_EVCR_PIN_PX6_Pos) /*!< 0x00000006 */ 02010 #define AFIO_EVCR_PIN_PX6 AFIO_EVCR_PIN_PX6_Msk /*!< Pin 6 selected */ 02011 #define AFIO_EVCR_PIN_PX7_Pos (0U) 02012 #define AFIO_EVCR_PIN_PX7_Msk (0x7U << AFIO_EVCR_PIN_PX7_Pos) /*!< 0x00000007 */ 02013 #define AFIO_EVCR_PIN_PX7 AFIO_EVCR_PIN_PX7_Msk /*!< Pin 7 selected */ 02014 #define AFIO_EVCR_PIN_PX8_Pos (3U) 02015 #define AFIO_EVCR_PIN_PX8_Msk (0x1U << AFIO_EVCR_PIN_PX8_Pos) /*!< 0x00000008 */ 02016 #define AFIO_EVCR_PIN_PX8 AFIO_EVCR_PIN_PX8_Msk /*!< Pin 8 selected */ 02017 #define AFIO_EVCR_PIN_PX9_Pos (0U) 02018 #define AFIO_EVCR_PIN_PX9_Msk (0x9U << AFIO_EVCR_PIN_PX9_Pos) /*!< 0x00000009 */ 02019 #define AFIO_EVCR_PIN_PX9 AFIO_EVCR_PIN_PX9_Msk /*!< Pin 9 selected */ 02020 #define AFIO_EVCR_PIN_PX10_Pos (1U) 02021 #define AFIO_EVCR_PIN_PX10_Msk (0x5U << AFIO_EVCR_PIN_PX10_Pos) /*!< 0x0000000A */ 02022 #define AFIO_EVCR_PIN_PX10 AFIO_EVCR_PIN_PX10_Msk /*!< Pin 10 selected */ 02023 #define AFIO_EVCR_PIN_PX11_Pos (0U) 02024 #define AFIO_EVCR_PIN_PX11_Msk (0xBU << AFIO_EVCR_PIN_PX11_Pos) /*!< 0x0000000B */ 02025 #define AFIO_EVCR_PIN_PX11 AFIO_EVCR_PIN_PX11_Msk /*!< Pin 11 selected */ 02026 #define AFIO_EVCR_PIN_PX12_Pos (2U) 02027 #define AFIO_EVCR_PIN_PX12_Msk (0x3U << AFIO_EVCR_PIN_PX12_Pos) /*!< 0x0000000C */ 02028 #define AFIO_EVCR_PIN_PX12 AFIO_EVCR_PIN_PX12_Msk /*!< Pin 12 selected */ 02029 #define AFIO_EVCR_PIN_PX13_Pos (0U) 02030 #define AFIO_EVCR_PIN_PX13_Msk (0xDU << AFIO_EVCR_PIN_PX13_Pos) /*!< 0x0000000D */ 02031 #define AFIO_EVCR_PIN_PX13 AFIO_EVCR_PIN_PX13_Msk /*!< Pin 13 selected */ 02032 #define AFIO_EVCR_PIN_PX14_Pos (1U) 02033 #define AFIO_EVCR_PIN_PX14_Msk (0x7U << AFIO_EVCR_PIN_PX14_Pos) /*!< 0x0000000E */ 02034 #define AFIO_EVCR_PIN_PX14 AFIO_EVCR_PIN_PX14_Msk /*!< Pin 14 selected */ 02035 #define AFIO_EVCR_PIN_PX15_Pos (0U) 02036 #define AFIO_EVCR_PIN_PX15_Msk (0xFU << AFIO_EVCR_PIN_PX15_Pos) /*!< 0x0000000F */ 02037 #define AFIO_EVCR_PIN_PX15 AFIO_EVCR_PIN_PX15_Msk /*!< Pin 15 selected */ 02038 02039 #define AFIO_EVCR_PORT_Pos (4U) 02040 #define AFIO_EVCR_PORT_Msk (0x7U << AFIO_EVCR_PORT_Pos) /*!< 0x00000070 */ 02041 #define AFIO_EVCR_PORT AFIO_EVCR_PORT_Msk /*!< PORT[2:0] bits (Port selection) */ 02042 #define AFIO_EVCR_PORT_0 (0x1U << AFIO_EVCR_PORT_Pos) /*!< 0x00000010 */ 02043 #define AFIO_EVCR_PORT_1 (0x2U << AFIO_EVCR_PORT_Pos) /*!< 0x00000020 */ 02044 #define AFIO_EVCR_PORT_2 (0x4U << AFIO_EVCR_PORT_Pos) /*!< 0x00000040 */ 02045 02046 /*!< PORT configuration */ 02047 #define AFIO_EVCR_PORT_PA ((uint32_t)0x00000000) /*!< Port A selected */ 02048 #define AFIO_EVCR_PORT_PB_Pos (4U) 02049 #define AFIO_EVCR_PORT_PB_Msk (0x1U << AFIO_EVCR_PORT_PB_Pos) /*!< 0x00000010 */ 02050 #define AFIO_EVCR_PORT_PB AFIO_EVCR_PORT_PB_Msk /*!< Port B selected */ 02051 #define AFIO_EVCR_PORT_PC_Pos (5U) 02052 #define AFIO_EVCR_PORT_PC_Msk (0x1U << AFIO_EVCR_PORT_PC_Pos) /*!< 0x00000020 */ 02053 #define AFIO_EVCR_PORT_PC AFIO_EVCR_PORT_PC_Msk /*!< Port C selected */ 02054 #define AFIO_EVCR_PORT_PD_Pos (4U) 02055 #define AFIO_EVCR_PORT_PD_Msk (0x3U << AFIO_EVCR_PORT_PD_Pos) /*!< 0x00000030 */ 02056 #define AFIO_EVCR_PORT_PD AFIO_EVCR_PORT_PD_Msk /*!< Port D selected */ 02057 #define AFIO_EVCR_PORT_PE_Pos (6U) 02058 #define AFIO_EVCR_PORT_PE_Msk (0x1U << AFIO_EVCR_PORT_PE_Pos) /*!< 0x00000040 */ 02059 #define AFIO_EVCR_PORT_PE AFIO_EVCR_PORT_PE_Msk /*!< Port E selected */ 02060 02061 #define AFIO_EVCR_EVOE_Pos (7U) 02062 #define AFIO_EVCR_EVOE_Msk (0x1U << AFIO_EVCR_EVOE_Pos) /*!< 0x00000080 */ 02063 #define AFIO_EVCR_EVOE AFIO_EVCR_EVOE_Msk /*!< Event Output Enable */ 02064 02065 /****************** Bit definition for AFIO_MAPR register *******************/ 02066 #define AFIO_MAPR_SPI1_REMAP_Pos (0U) 02067 #define AFIO_MAPR_SPI1_REMAP_Msk (0x1U << AFIO_MAPR_SPI1_REMAP_Pos) /*!< 0x00000001 */ 02068 #define AFIO_MAPR_SPI1_REMAP AFIO_MAPR_SPI1_REMAP_Msk /*!< SPI1 remapping */ 02069 #define AFIO_MAPR_I2C1_REMAP_Pos (1U) 02070 #define AFIO_MAPR_I2C1_REMAP_Msk (0x1U << AFIO_MAPR_I2C1_REMAP_Pos) /*!< 0x00000002 */ 02071 #define AFIO_MAPR_I2C1_REMAP AFIO_MAPR_I2C1_REMAP_Msk /*!< I2C1 remapping */ 02072 #define AFIO_MAPR_USART1_REMAP_Pos (2U) 02073 #define AFIO_MAPR_USART1_REMAP_Msk (0x1U << AFIO_MAPR_USART1_REMAP_Pos) /*!< 0x00000004 */ 02074 #define AFIO_MAPR_USART1_REMAP AFIO_MAPR_USART1_REMAP_Msk /*!< USART1 remapping */ 02075 #define AFIO_MAPR_USART2_REMAP_Pos (3U) 02076 #define AFIO_MAPR_USART2_REMAP_Msk (0x1U << AFIO_MAPR_USART2_REMAP_Pos) /*!< 0x00000008 */ 02077 #define AFIO_MAPR_USART2_REMAP AFIO_MAPR_USART2_REMAP_Msk /*!< USART2 remapping */ 02078 02079 #define AFIO_MAPR_USART3_REMAP_Pos (4U) 02080 #define AFIO_MAPR_USART3_REMAP_Msk (0x3U << AFIO_MAPR_USART3_REMAP_Pos) /*!< 0x00000030 */ 02081 #define AFIO_MAPR_USART3_REMAP AFIO_MAPR_USART3_REMAP_Msk /*!< USART3_REMAP[1:0] bits (USART3 remapping) */ 02082 #define AFIO_MAPR_USART3_REMAP_0 (0x1U << AFIO_MAPR_USART3_REMAP_Pos) /*!< 0x00000010 */ 02083 #define AFIO_MAPR_USART3_REMAP_1 (0x2U << AFIO_MAPR_USART3_REMAP_Pos) /*!< 0x00000020 */ 02084 02085 /* USART3_REMAP configuration */ 02086 #define AFIO_MAPR_USART3_REMAP_NOREMAP ((uint32_t)0x00000000) /*!< No remap (TX/PB10, RX/PB11, CK/PB12, CTS/PB13, RTS/PB14) */ 02087 #define AFIO_MAPR_USART3_REMAP_PARTIALREMAP_Pos (4U) 02088 #define AFIO_MAPR_USART3_REMAP_PARTIALREMAP_Msk (0x1U << AFIO_MAPR_USART3_REMAP_PARTIALREMAP_Pos) /*!< 0x00000010 */ 02089 #define AFIO_MAPR_USART3_REMAP_PARTIALREMAP AFIO_MAPR_USART3_REMAP_PARTIALREMAP_Msk /*!< Partial remap (TX/PC10, RX/PC11, CK/PC12, CTS/PB13, RTS/PB14) */ 02090 #define AFIO_MAPR_USART3_REMAP_FULLREMAP_Pos (4U) 02091 #define AFIO_MAPR_USART3_REMAP_FULLREMAP_Msk (0x3U << AFIO_MAPR_USART3_REMAP_FULLREMAP_Pos) /*!< 0x00000030 */ 02092 #define AFIO_MAPR_USART3_REMAP_FULLREMAP AFIO_MAPR_USART3_REMAP_FULLREMAP_Msk /*!< Full remap (TX/PD8, RX/PD9, CK/PD10, CTS/PD11, RTS/PD12) */ 02093 02094 #define AFIO_MAPR_TIM1_REMAP_Pos (6U) 02095 #define AFIO_MAPR_TIM1_REMAP_Msk (0x3U << AFIO_MAPR_TIM1_REMAP_Pos) /*!< 0x000000C0 */ 02096 #define AFIO_MAPR_TIM1_REMAP AFIO_MAPR_TIM1_REMAP_Msk /*!< TIM1_REMAP[1:0] bits (TIM1 remapping) */ 02097 #define AFIO_MAPR_TIM1_REMAP_0 (0x1U << AFIO_MAPR_TIM1_REMAP_Pos) /*!< 0x00000040 */ 02098 #define AFIO_MAPR_TIM1_REMAP_1 (0x2U << AFIO_MAPR_TIM1_REMAP_Pos) /*!< 0x00000080 */ 02099 02100 /*!< TIM1_REMAP configuration */ 02101 #define AFIO_MAPR_TIM1_REMAP_NOREMAP ((uint32_t)0x00000000) /*!< No remap (ETR/PA12, CH1/PA8, CH2/PA9, CH3/PA10, CH4/PA11, BKIN/PB12, CH1N/PB13, CH2N/PB14, CH3N/PB15) */ 02102 #define AFIO_MAPR_TIM1_REMAP_PARTIALREMAP_Pos (6U) 02103 #define AFIO_MAPR_TIM1_REMAP_PARTIALREMAP_Msk (0x1U << AFIO_MAPR_TIM1_REMAP_PARTIALREMAP_Pos) /*!< 0x00000040 */ 02104 #define AFIO_MAPR_TIM1_REMAP_PARTIALREMAP AFIO_MAPR_TIM1_REMAP_PARTIALREMAP_Msk /*!< Partial remap (ETR/PA12, CH1/PA8, CH2/PA9, CH3/PA10, CH4/PA11, BKIN/PA6, CH1N/PA7, CH2N/PB0, CH3N/PB1) */ 02105 #define AFIO_MAPR_TIM1_REMAP_FULLREMAP_Pos (6U) 02106 #define AFIO_MAPR_TIM1_REMAP_FULLREMAP_Msk (0x3U << AFIO_MAPR_TIM1_REMAP_FULLREMAP_Pos) /*!< 0x000000C0 */ 02107 #define AFIO_MAPR_TIM1_REMAP_FULLREMAP AFIO_MAPR_TIM1_REMAP_FULLREMAP_Msk /*!< Full remap (ETR/PE7, CH1/PE9, CH2/PE11, CH3/PE13, CH4/PE14, BKIN/PE15, CH1N/PE8, CH2N/PE10, CH3N/PE12) */ 02108 02109 #define AFIO_MAPR_TIM2_REMAP_Pos (8U) 02110 #define AFIO_MAPR_TIM2_REMAP_Msk (0x3U << AFIO_MAPR_TIM2_REMAP_Pos) /*!< 0x00000300 */ 02111 #define AFIO_MAPR_TIM2_REMAP AFIO_MAPR_TIM2_REMAP_Msk /*!< TIM2_REMAP[1:0] bits (TIM2 remapping) */ 02112 #define AFIO_MAPR_TIM2_REMAP_0 (0x1U << AFIO_MAPR_TIM2_REMAP_Pos) /*!< 0x00000100 */ 02113 #define AFIO_MAPR_TIM2_REMAP_1 (0x2U << AFIO_MAPR_TIM2_REMAP_Pos) /*!< 0x00000200 */ 02114 02115 /*!< TIM2_REMAP configuration */ 02116 #define AFIO_MAPR_TIM2_REMAP_NOREMAP ((uint32_t)0x00000000) /*!< No remap (CH1/ETR/PA0, CH2/PA1, CH3/PA2, CH4/PA3) */ 02117 #define AFIO_MAPR_TIM2_REMAP_PARTIALREMAP1_Pos (8U) 02118 #define AFIO_MAPR_TIM2_REMAP_PARTIALREMAP1_Msk (0x1U << AFIO_MAPR_TIM2_REMAP_PARTIALREMAP1_Pos) /*!< 0x00000100 */ 02119 #define AFIO_MAPR_TIM2_REMAP_PARTIALREMAP1 AFIO_MAPR_TIM2_REMAP_PARTIALREMAP1_Msk /*!< Partial remap (CH1/ETR/PA15, CH2/PB3, CH3/PA2, CH4/PA3) */ 02120 #define AFIO_MAPR_TIM2_REMAP_PARTIALREMAP2_Pos (9U) 02121 #define AFIO_MAPR_TIM2_REMAP_PARTIALREMAP2_Msk (0x1U << AFIO_MAPR_TIM2_REMAP_PARTIALREMAP2_Pos) /*!< 0x00000200 */ 02122 #define AFIO_MAPR_TIM2_REMAP_PARTIALREMAP2 AFIO_MAPR_TIM2_REMAP_PARTIALREMAP2_Msk /*!< Partial remap (CH1/ETR/PA0, CH2/PA1, CH3/PB10, CH4/PB11) */ 02123 #define AFIO_MAPR_TIM2_REMAP_FULLREMAP_Pos (8U) 02124 #define AFIO_MAPR_TIM2_REMAP_FULLREMAP_Msk (0x3U << AFIO_MAPR_TIM2_REMAP_FULLREMAP_Pos) /*!< 0x00000300 */ 02125 #define AFIO_MAPR_TIM2_REMAP_FULLREMAP AFIO_MAPR_TIM2_REMAP_FULLREMAP_Msk /*!< Full remap (CH1/ETR/PA15, CH2/PB3, CH3/PB10, CH4/PB11) */ 02126 02127 #define AFIO_MAPR_TIM3_REMAP_Pos (10U) 02128 #define AFIO_MAPR_TIM3_REMAP_Msk (0x3U << AFIO_MAPR_TIM3_REMAP_Pos) /*!< 0x00000C00 */ 02129 #define AFIO_MAPR_TIM3_REMAP AFIO_MAPR_TIM3_REMAP_Msk /*!< TIM3_REMAP[1:0] bits (TIM3 remapping) */ 02130 #define AFIO_MAPR_TIM3_REMAP_0 (0x1U << AFIO_MAPR_TIM3_REMAP_Pos) /*!< 0x00000400 */ 02131 #define AFIO_MAPR_TIM3_REMAP_1 (0x2U << AFIO_MAPR_TIM3_REMAP_Pos) /*!< 0x00000800 */ 02132 02133 /*!< TIM3_REMAP configuration */ 02134 #define AFIO_MAPR_TIM3_REMAP_NOREMAP ((uint32_t)0x00000000) /*!< No remap (CH1/PA6, CH2/PA7, CH3/PB0, CH4/PB1) */ 02135 #define AFIO_MAPR_TIM3_REMAP_PARTIALREMAP_Pos (11U) 02136 #define AFIO_MAPR_TIM3_REMAP_PARTIALREMAP_Msk (0x1U << AFIO_MAPR_TIM3_REMAP_PARTIALREMAP_Pos) /*!< 0x00000800 */ 02137 #define AFIO_MAPR_TIM3_REMAP_PARTIALREMAP AFIO_MAPR_TIM3_REMAP_PARTIALREMAP_Msk /*!< Partial remap (CH1/PB4, CH2/PB5, CH3/PB0, CH4/PB1) */ 02138 #define AFIO_MAPR_TIM3_REMAP_FULLREMAP_Pos (10U) 02139 #define AFIO_MAPR_TIM3_REMAP_FULLREMAP_Msk (0x3U << AFIO_MAPR_TIM3_REMAP_FULLREMAP_Pos) /*!< 0x00000C00 */ 02140 #define AFIO_MAPR_TIM3_REMAP_FULLREMAP AFIO_MAPR_TIM3_REMAP_FULLREMAP_Msk /*!< Full remap (CH1/PC6, CH2/PC7, CH3/PC8, CH4/PC9) */ 02141 02142 #define AFIO_MAPR_TIM4_REMAP_Pos (12U) 02143 #define AFIO_MAPR_TIM4_REMAP_Msk (0x1U << AFIO_MAPR_TIM4_REMAP_Pos) /*!< 0x00001000 */ 02144 #define AFIO_MAPR_TIM4_REMAP AFIO_MAPR_TIM4_REMAP_Msk /*!< TIM4_REMAP bit (TIM4 remapping) */ 02145 02146 #define AFIO_MAPR_CAN_REMAP_Pos (13U) 02147 #define AFIO_MAPR_CAN_REMAP_Msk (0x3U << AFIO_MAPR_CAN_REMAP_Pos) /*!< 0x00006000 */ 02148 #define AFIO_MAPR_CAN_REMAP AFIO_MAPR_CAN_REMAP_Msk /*!< CAN_REMAP[1:0] bits (CAN Alternate function remapping) */ 02149 #define AFIO_MAPR_CAN_REMAP_0 (0x1U << AFIO_MAPR_CAN_REMAP_Pos) /*!< 0x00002000 */ 02150 #define AFIO_MAPR_CAN_REMAP_1 (0x2U << AFIO_MAPR_CAN_REMAP_Pos) /*!< 0x00004000 */ 02151 02152 /*!< CAN_REMAP configuration */ 02153 #define AFIO_MAPR_CAN_REMAP_REMAP1 ((uint32_t)0x00000000) /*!< CANRX mapped to PA11, CANTX mapped to PA12 */ 02154 #define AFIO_MAPR_CAN_REMAP_REMAP2_Pos (14U) 02155 #define AFIO_MAPR_CAN_REMAP_REMAP2_Msk (0x1U << AFIO_MAPR_CAN_REMAP_REMAP2_Pos) /*!< 0x00004000 */ 02156 #define AFIO_MAPR_CAN_REMAP_REMAP2 AFIO_MAPR_CAN_REMAP_REMAP2_Msk /*!< CANRX mapped to PB8, CANTX mapped to PB9 */ 02157 #define AFIO_MAPR_CAN_REMAP_REMAP3_Pos (13U) 02158 #define AFIO_MAPR_CAN_REMAP_REMAP3_Msk (0x3U << AFIO_MAPR_CAN_REMAP_REMAP3_Pos) /*!< 0x00006000 */ 02159 #define AFIO_MAPR_CAN_REMAP_REMAP3 AFIO_MAPR_CAN_REMAP_REMAP3_Msk /*!< CANRX mapped to PD0, CANTX mapped to PD1 */ 02160 02161 #define AFIO_MAPR_PD01_REMAP_Pos (15U) 02162 #define AFIO_MAPR_PD01_REMAP_Msk (0x1U << AFIO_MAPR_PD01_REMAP_Pos) /*!< 0x00008000 */ 02163 #define AFIO_MAPR_PD01_REMAP AFIO_MAPR_PD01_REMAP_Msk /*!< Port D0/Port D1 mapping on OSC_IN/OSC_OUT */ 02164 02165 /*!< SWJ_CFG configuration */ 02166 #define AFIO_MAPR_SWJ_CFG_Pos (24U) 02167 #define AFIO_MAPR_SWJ_CFG_Msk (0x7U << AFIO_MAPR_SWJ_CFG_Pos) /*!< 0x07000000 */ 02168 #define AFIO_MAPR_SWJ_CFG AFIO_MAPR_SWJ_CFG_Msk /*!< SWJ_CFG[2:0] bits (Serial Wire JTAG configuration) */ 02169 #define AFIO_MAPR_SWJ_CFG_0 (0x1U << AFIO_MAPR_SWJ_CFG_Pos) /*!< 0x01000000 */ 02170 #define AFIO_MAPR_SWJ_CFG_1 (0x2U << AFIO_MAPR_SWJ_CFG_Pos) /*!< 0x02000000 */ 02171 #define AFIO_MAPR_SWJ_CFG_2 (0x4U << AFIO_MAPR_SWJ_CFG_Pos) /*!< 0x04000000 */ 02172 02173 #define AFIO_MAPR_SWJ_CFG_RESET ((uint32_t)0x00000000) /*!< Full SWJ (JTAG-DP + SW-DP) : Reset State */ 02174 #define AFIO_MAPR_SWJ_CFG_NOJNTRST_Pos (24U) 02175 #define AFIO_MAPR_SWJ_CFG_NOJNTRST_Msk (0x1U << AFIO_MAPR_SWJ_CFG_NOJNTRST_Pos) /*!< 0x01000000 */ 02176 #define AFIO_MAPR_SWJ_CFG_NOJNTRST AFIO_MAPR_SWJ_CFG_NOJNTRST_Msk /*!< Full SWJ (JTAG-DP + SW-DP) but without JNTRST */ 02177 #define AFIO_MAPR_SWJ_CFG_JTAGDISABLE_Pos (25U) 02178 #define AFIO_MAPR_SWJ_CFG_JTAGDISABLE_Msk (0x1U << AFIO_MAPR_SWJ_CFG_JTAGDISABLE_Pos) /*!< 0x02000000 */ 02179 #define AFIO_MAPR_SWJ_CFG_JTAGDISABLE AFIO_MAPR_SWJ_CFG_JTAGDISABLE_Msk /*!< JTAG-DP Disabled and SW-DP Enabled */ 02180 #define AFIO_MAPR_SWJ_CFG_DISABLE_Pos (26U) 02181 #define AFIO_MAPR_SWJ_CFG_DISABLE_Msk (0x1U << AFIO_MAPR_SWJ_CFG_DISABLE_Pos) /*!< 0x04000000 */ 02182 #define AFIO_MAPR_SWJ_CFG_DISABLE AFIO_MAPR_SWJ_CFG_DISABLE_Msk /*!< JTAG-DP Disabled and SW-DP Disabled */ 02183 02184 02185 /***************** Bit definition for AFIO_EXTICR1 register *****************/ 02186 #define AFIO_EXTICR1_EXTI0_Pos (0U) 02187 #define AFIO_EXTICR1_EXTI0_Msk (0xFU << AFIO_EXTICR1_EXTI0_Pos) /*!< 0x0000000F */ 02188 #define AFIO_EXTICR1_EXTI0 AFIO_EXTICR1_EXTI0_Msk /*!< EXTI 0 configuration */ 02189 #define AFIO_EXTICR1_EXTI1_Pos (4U) 02190 #define AFIO_EXTICR1_EXTI1_Msk (0xFU << AFIO_EXTICR1_EXTI1_Pos) /*!< 0x000000F0 */ 02191 #define AFIO_EXTICR1_EXTI1 AFIO_EXTICR1_EXTI1_Msk /*!< EXTI 1 configuration */ 02192 #define AFIO_EXTICR1_EXTI2_Pos (8U) 02193 #define AFIO_EXTICR1_EXTI2_Msk (0xFU << AFIO_EXTICR1_EXTI2_Pos) /*!< 0x00000F00 */ 02194 #define AFIO_EXTICR1_EXTI2 AFIO_EXTICR1_EXTI2_Msk /*!< EXTI 2 configuration */ 02195 #define AFIO_EXTICR1_EXTI3_Pos (12U) 02196 #define AFIO_EXTICR1_EXTI3_Msk (0xFU << AFIO_EXTICR1_EXTI3_Pos) /*!< 0x0000F000 */ 02197 #define AFIO_EXTICR1_EXTI3 AFIO_EXTICR1_EXTI3_Msk /*!< EXTI 3 configuration */ 02198 02199 /*!< EXTI0 configuration */ 02200 #define AFIO_EXTICR1_EXTI0_PA ((uint32_t)0x00000000) /*!< PA[0] pin */ 02201 #define AFIO_EXTICR1_EXTI0_PB_Pos (0U) 02202 #define AFIO_EXTICR1_EXTI0_PB_Msk (0x1U << AFIO_EXTICR1_EXTI0_PB_Pos) /*!< 0x00000001 */ 02203 #define AFIO_EXTICR1_EXTI0_PB AFIO_EXTICR1_EXTI0_PB_Msk /*!< PB[0] pin */ 02204 #define AFIO_EXTICR1_EXTI0_PC_Pos (1U) 02205 #define AFIO_EXTICR1_EXTI0_PC_Msk (0x1U << AFIO_EXTICR1_EXTI0_PC_Pos) /*!< 0x00000002 */ 02206 #define AFIO_EXTICR1_EXTI0_PC AFIO_EXTICR1_EXTI0_PC_Msk /*!< PC[0] pin */ 02207 #define AFIO_EXTICR1_EXTI0_PD_Pos (0U) 02208 #define AFIO_EXTICR1_EXTI0_PD_Msk (0x3U << AFIO_EXTICR1_EXTI0_PD_Pos) /*!< 0x00000003 */ 02209 #define AFIO_EXTICR1_EXTI0_PD AFIO_EXTICR1_EXTI0_PD_Msk /*!< PD[0] pin */ 02210 #define AFIO_EXTICR1_EXTI0_PE_Pos (2U) 02211 #define AFIO_EXTICR1_EXTI0_PE_Msk (0x1U << AFIO_EXTICR1_EXTI0_PE_Pos) /*!< 0x00000004 */ 02212 #define AFIO_EXTICR1_EXTI0_PE AFIO_EXTICR1_EXTI0_PE_Msk /*!< PE[0] pin */ 02213 #define AFIO_EXTICR1_EXTI0_PF_Pos (0U) 02214 #define AFIO_EXTICR1_EXTI0_PF_Msk (0x5U << AFIO_EXTICR1_EXTI0_PF_Pos) /*!< 0x00000005 */ 02215 #define AFIO_EXTICR1_EXTI0_PF AFIO_EXTICR1_EXTI0_PF_Msk /*!< PF[0] pin */ 02216 #define AFIO_EXTICR1_EXTI0_PG_Pos (1U) 02217 #define AFIO_EXTICR1_EXTI0_PG_Msk (0x3U << AFIO_EXTICR1_EXTI0_PG_Pos) /*!< 0x00000006 */ 02218 #define AFIO_EXTICR1_EXTI0_PG AFIO_EXTICR1_EXTI0_PG_Msk /*!< PG[0] pin */ 02219 02220 /*!< EXTI1 configuration */ 02221 #define AFIO_EXTICR1_EXTI1_PA ((uint32_t)0x00000000) /*!< PA[1] pin */ 02222 #define AFIO_EXTICR1_EXTI1_PB_Pos (4U) 02223 #define AFIO_EXTICR1_EXTI1_PB_Msk (0x1U << AFIO_EXTICR1_EXTI1_PB_Pos) /*!< 0x00000010 */ 02224 #define AFIO_EXTICR1_EXTI1_PB AFIO_EXTICR1_EXTI1_PB_Msk /*!< PB[1] pin */ 02225 #define AFIO_EXTICR1_EXTI1_PC_Pos (5U) 02226 #define AFIO_EXTICR1_EXTI1_PC_Msk (0x1U << AFIO_EXTICR1_EXTI1_PC_Pos) /*!< 0x00000020 */ 02227 #define AFIO_EXTICR1_EXTI1_PC AFIO_EXTICR1_EXTI1_PC_Msk /*!< PC[1] pin */ 02228 #define AFIO_EXTICR1_EXTI1_PD_Pos (4U) 02229 #define AFIO_EXTICR1_EXTI1_PD_Msk (0x3U << AFIO_EXTICR1_EXTI1_PD_Pos) /*!< 0x00000030 */ 02230 #define AFIO_EXTICR1_EXTI1_PD AFIO_EXTICR1_EXTI1_PD_Msk /*!< PD[1] pin */ 02231 #define AFIO_EXTICR1_EXTI1_PE_Pos (6U) 02232 #define AFIO_EXTICR1_EXTI1_PE_Msk (0x1U << AFIO_EXTICR1_EXTI1_PE_Pos) /*!< 0x00000040 */ 02233 #define AFIO_EXTICR1_EXTI1_PE AFIO_EXTICR1_EXTI1_PE_Msk /*!< PE[1] pin */ 02234 #define AFIO_EXTICR1_EXTI1_PF_Pos (4U) 02235 #define AFIO_EXTICR1_EXTI1_PF_Msk (0x5U << AFIO_EXTICR1_EXTI1_PF_Pos) /*!< 0x00000050 */ 02236 #define AFIO_EXTICR1_EXTI1_PF AFIO_EXTICR1_EXTI1_PF_Msk /*!< PF[1] pin */ 02237 #define AFIO_EXTICR1_EXTI1_PG_Pos (5U) 02238 #define AFIO_EXTICR1_EXTI1_PG_Msk (0x3U << AFIO_EXTICR1_EXTI1_PG_Pos) /*!< 0x00000060 */ 02239 #define AFIO_EXTICR1_EXTI1_PG AFIO_EXTICR1_EXTI1_PG_Msk /*!< PG[1] pin */ 02240 02241 /*!< EXTI2 configuration */ 02242 #define AFIO_EXTICR1_EXTI2_PA ((uint32_t)0x00000000) /*!< PA[2] pin */ 02243 #define AFIO_EXTICR1_EXTI2_PB_Pos (8U) 02244 #define AFIO_EXTICR1_EXTI2_PB_Msk (0x1U << AFIO_EXTICR1_EXTI2_PB_Pos) /*!< 0x00000100 */ 02245 #define AFIO_EXTICR1_EXTI2_PB AFIO_EXTICR1_EXTI2_PB_Msk /*!< PB[2] pin */ 02246 #define AFIO_EXTICR1_EXTI2_PC_Pos (9U) 02247 #define AFIO_EXTICR1_EXTI2_PC_Msk (0x1U << AFIO_EXTICR1_EXTI2_PC_Pos) /*!< 0x00000200 */ 02248 #define AFIO_EXTICR1_EXTI2_PC AFIO_EXTICR1_EXTI2_PC_Msk /*!< PC[2] pin */ 02249 #define AFIO_EXTICR1_EXTI2_PD_Pos (8U) 02250 #define AFIO_EXTICR1_EXTI2_PD_Msk (0x3U << AFIO_EXTICR1_EXTI2_PD_Pos) /*!< 0x00000300 */ 02251 #define AFIO_EXTICR1_EXTI2_PD AFIO_EXTICR1_EXTI2_PD_Msk /*!< PD[2] pin */ 02252 #define AFIO_EXTICR1_EXTI2_PE_Pos (10U) 02253 #define AFIO_EXTICR1_EXTI2_PE_Msk (0x1U << AFIO_EXTICR1_EXTI2_PE_Pos) /*!< 0x00000400 */ 02254 #define AFIO_EXTICR1_EXTI2_PE AFIO_EXTICR1_EXTI2_PE_Msk /*!< PE[2] pin */ 02255 #define AFIO_EXTICR1_EXTI2_PF_Pos (8U) 02256 #define AFIO_EXTICR1_EXTI2_PF_Msk (0x5U << AFIO_EXTICR1_EXTI2_PF_Pos) /*!< 0x00000500 */ 02257 #define AFIO_EXTICR1_EXTI2_PF AFIO_EXTICR1_EXTI2_PF_Msk /*!< PF[2] pin */ 02258 #define AFIO_EXTICR1_EXTI2_PG_Pos (9U) 02259 #define AFIO_EXTICR1_EXTI2_PG_Msk (0x3U << AFIO_EXTICR1_EXTI2_PG_Pos) /*!< 0x00000600 */ 02260 #define AFIO_EXTICR1_EXTI2_PG AFIO_EXTICR1_EXTI2_PG_Msk /*!< PG[2] pin */ 02261 02262 /*!< EXTI3 configuration */ 02263 #define AFIO_EXTICR1_EXTI3_PA ((uint32_t)0x00000000) /*!< PA[3] pin */ 02264 #define AFIO_EXTICR1_EXTI3_PB_Pos (12U) 02265 #define AFIO_EXTICR1_EXTI3_PB_Msk (0x1U << AFIO_EXTICR1_EXTI3_PB_Pos) /*!< 0x00001000 */ 02266 #define AFIO_EXTICR1_EXTI3_PB AFIO_EXTICR1_EXTI3_PB_Msk /*!< PB[3] pin */ 02267 #define AFIO_EXTICR1_EXTI3_PC_Pos (13U) 02268 #define AFIO_EXTICR1_EXTI3_PC_Msk (0x1U << AFIO_EXTICR1_EXTI3_PC_Pos) /*!< 0x00002000 */ 02269 #define AFIO_EXTICR1_EXTI3_PC AFIO_EXTICR1_EXTI3_PC_Msk /*!< PC[3] pin */ 02270 #define AFIO_EXTICR1_EXTI3_PD_Pos (12U) 02271 #define AFIO_EXTICR1_EXTI3_PD_Msk (0x3U << AFIO_EXTICR1_EXTI3_PD_Pos) /*!< 0x00003000 */ 02272 #define AFIO_EXTICR1_EXTI3_PD AFIO_EXTICR1_EXTI3_PD_Msk /*!< PD[3] pin */ 02273 #define AFIO_EXTICR1_EXTI3_PE_Pos (14U) 02274 #define AFIO_EXTICR1_EXTI3_PE_Msk (0x1U << AFIO_EXTICR1_EXTI3_PE_Pos) /*!< 0x00004000 */ 02275 #define AFIO_EXTICR1_EXTI3_PE AFIO_EXTICR1_EXTI3_PE_Msk /*!< PE[3] pin */ 02276 #define AFIO_EXTICR1_EXTI3_PF_Pos (12U) 02277 #define AFIO_EXTICR1_EXTI3_PF_Msk (0x5U << AFIO_EXTICR1_EXTI3_PF_Pos) /*!< 0x00005000 */ 02278 #define AFIO_EXTICR1_EXTI3_PF AFIO_EXTICR1_EXTI3_PF_Msk /*!< PF[3] pin */ 02279 #define AFIO_EXTICR1_EXTI3_PG_Pos (13U) 02280 #define AFIO_EXTICR1_EXTI3_PG_Msk (0x3U << AFIO_EXTICR1_EXTI3_PG_Pos) /*!< 0x00006000 */ 02281 #define AFIO_EXTICR1_EXTI3_PG AFIO_EXTICR1_EXTI3_PG_Msk /*!< PG[3] pin */ 02282 02283 /***************** Bit definition for AFIO_EXTICR2 register *****************/ 02284 #define AFIO_EXTICR2_EXTI4_Pos (0U) 02285 #define AFIO_EXTICR2_EXTI4_Msk (0xFU << AFIO_EXTICR2_EXTI4_Pos) /*!< 0x0000000F */ 02286 #define AFIO_EXTICR2_EXTI4 AFIO_EXTICR2_EXTI4_Msk /*!< EXTI 4 configuration */ 02287 #define AFIO_EXTICR2_EXTI5_Pos (4U) 02288 #define AFIO_EXTICR2_EXTI5_Msk (0xFU << AFIO_EXTICR2_EXTI5_Pos) /*!< 0x000000F0 */ 02289 #define AFIO_EXTICR2_EXTI5 AFIO_EXTICR2_EXTI5_Msk /*!< EXTI 5 configuration */ 02290 #define AFIO_EXTICR2_EXTI6_Pos (8U) 02291 #define AFIO_EXTICR2_EXTI6_Msk (0xFU << AFIO_EXTICR2_EXTI6_Pos) /*!< 0x00000F00 */ 02292 #define AFIO_EXTICR2_EXTI6 AFIO_EXTICR2_EXTI6_Msk /*!< EXTI 6 configuration */ 02293 #define AFIO_EXTICR2_EXTI7_Pos (12U) 02294 #define AFIO_EXTICR2_EXTI7_Msk (0xFU << AFIO_EXTICR2_EXTI7_Pos) /*!< 0x0000F000 */ 02295 #define AFIO_EXTICR2_EXTI7 AFIO_EXTICR2_EXTI7_Msk /*!< EXTI 7 configuration */ 02296 02297 /*!< EXTI4 configuration */ 02298 #define AFIO_EXTICR2_EXTI4_PA ((uint32_t)0x00000000) /*!< PA[4] pin */ 02299 #define AFIO_EXTICR2_EXTI4_PB_Pos (0U) 02300 #define AFIO_EXTICR2_EXTI4_PB_Msk (0x1U << AFIO_EXTICR2_EXTI4_PB_Pos) /*!< 0x00000001 */ 02301 #define AFIO_EXTICR2_EXTI4_PB AFIO_EXTICR2_EXTI4_PB_Msk /*!< PB[4] pin */ 02302 #define AFIO_EXTICR2_EXTI4_PC_Pos (1U) 02303 #define AFIO_EXTICR2_EXTI4_PC_Msk (0x1U << AFIO_EXTICR2_EXTI4_PC_Pos) /*!< 0x00000002 */ 02304 #define AFIO_EXTICR2_EXTI4_PC AFIO_EXTICR2_EXTI4_PC_Msk /*!< PC[4] pin */ 02305 #define AFIO_EXTICR2_EXTI4_PD_Pos (0U) 02306 #define AFIO_EXTICR2_EXTI4_PD_Msk (0x3U << AFIO_EXTICR2_EXTI4_PD_Pos) /*!< 0x00000003 */ 02307 #define AFIO_EXTICR2_EXTI4_PD AFIO_EXTICR2_EXTI4_PD_Msk /*!< PD[4] pin */ 02308 #define AFIO_EXTICR2_EXTI4_PE_Pos (2U) 02309 #define AFIO_EXTICR2_EXTI4_PE_Msk (0x1U << AFIO_EXTICR2_EXTI4_PE_Pos) /*!< 0x00000004 */ 02310 #define AFIO_EXTICR2_EXTI4_PE AFIO_EXTICR2_EXTI4_PE_Msk /*!< PE[4] pin */ 02311 #define AFIO_EXTICR2_EXTI4_PF_Pos (0U) 02312 #define AFIO_EXTICR2_EXTI4_PF_Msk (0x5U << AFIO_EXTICR2_EXTI4_PF_Pos) /*!< 0x00000005 */ 02313 #define AFIO_EXTICR2_EXTI4_PF AFIO_EXTICR2_EXTI4_PF_Msk /*!< PF[4] pin */ 02314 #define AFIO_EXTICR2_EXTI4_PG_Pos (1U) 02315 #define AFIO_EXTICR2_EXTI4_PG_Msk (0x3U << AFIO_EXTICR2_EXTI4_PG_Pos) /*!< 0x00000006 */ 02316 #define AFIO_EXTICR2_EXTI4_PG AFIO_EXTICR2_EXTI4_PG_Msk /*!< PG[4] pin */ 02317 02318 /* EXTI5 configuration */ 02319 #define AFIO_EXTICR2_EXTI5_PA ((uint32_t)0x00000000) /*!< PA[5] pin */ 02320 #define AFIO_EXTICR2_EXTI5_PB_Pos (4U) 02321 #define AFIO_EXTICR2_EXTI5_PB_Msk (0x1U << AFIO_EXTICR2_EXTI5_PB_Pos) /*!< 0x00000010 */ 02322 #define AFIO_EXTICR2_EXTI5_PB AFIO_EXTICR2_EXTI5_PB_Msk /*!< PB[5] pin */ 02323 #define AFIO_EXTICR2_EXTI5_PC_Pos (5U) 02324 #define AFIO_EXTICR2_EXTI5_PC_Msk (0x1U << AFIO_EXTICR2_EXTI5_PC_Pos) /*!< 0x00000020 */ 02325 #define AFIO_EXTICR2_EXTI5_PC AFIO_EXTICR2_EXTI5_PC_Msk /*!< PC[5] pin */ 02326 #define AFIO_EXTICR2_EXTI5_PD_Pos (4U) 02327 #define AFIO_EXTICR2_EXTI5_PD_Msk (0x3U << AFIO_EXTICR2_EXTI5_PD_Pos) /*!< 0x00000030 */ 02328 #define AFIO_EXTICR2_EXTI5_PD AFIO_EXTICR2_EXTI5_PD_Msk /*!< PD[5] pin */ 02329 #define AFIO_EXTICR2_EXTI5_PE_Pos (6U) 02330 #define AFIO_EXTICR2_EXTI5_PE_Msk (0x1U << AFIO_EXTICR2_EXTI5_PE_Pos) /*!< 0x00000040 */ 02331 #define AFIO_EXTICR2_EXTI5_PE AFIO_EXTICR2_EXTI5_PE_Msk /*!< PE[5] pin */ 02332 #define AFIO_EXTICR2_EXTI5_PF_Pos (4U) 02333 #define AFIO_EXTICR2_EXTI5_PF_Msk (0x5U << AFIO_EXTICR2_EXTI5_PF_Pos) /*!< 0x00000050 */ 02334 #define AFIO_EXTICR2_EXTI5_PF AFIO_EXTICR2_EXTI5_PF_Msk /*!< PF[5] pin */ 02335 #define AFIO_EXTICR2_EXTI5_PG_Pos (5U) 02336 #define AFIO_EXTICR2_EXTI5_PG_Msk (0x3U << AFIO_EXTICR2_EXTI5_PG_Pos) /*!< 0x00000060 */ 02337 #define AFIO_EXTICR2_EXTI5_PG AFIO_EXTICR2_EXTI5_PG_Msk /*!< PG[5] pin */ 02338 02339 /*!< EXTI6 configuration */ 02340 #define AFIO_EXTICR2_EXTI6_PA ((uint32_t)0x00000000) /*!< PA[6] pin */ 02341 #define AFIO_EXTICR2_EXTI6_PB_Pos (8U) 02342 #define AFIO_EXTICR2_EXTI6_PB_Msk (0x1U << AFIO_EXTICR2_EXTI6_PB_Pos) /*!< 0x00000100 */ 02343 #define AFIO_EXTICR2_EXTI6_PB AFIO_EXTICR2_EXTI6_PB_Msk /*!< PB[6] pin */ 02344 #define AFIO_EXTICR2_EXTI6_PC_Pos (9U) 02345 #define AFIO_EXTICR2_EXTI6_PC_Msk (0x1U << AFIO_EXTICR2_EXTI6_PC_Pos) /*!< 0x00000200 */ 02346 #define AFIO_EXTICR2_EXTI6_PC AFIO_EXTICR2_EXTI6_PC_Msk /*!< PC[6] pin */ 02347 #define AFIO_EXTICR2_EXTI6_PD_Pos (8U) 02348 #define AFIO_EXTICR2_EXTI6_PD_Msk (0x3U << AFIO_EXTICR2_EXTI6_PD_Pos) /*!< 0x00000300 */ 02349 #define AFIO_EXTICR2_EXTI6_PD AFIO_EXTICR2_EXTI6_PD_Msk /*!< PD[6] pin */ 02350 #define AFIO_EXTICR2_EXTI6_PE_Pos (10U) 02351 #define AFIO_EXTICR2_EXTI6_PE_Msk (0x1U << AFIO_EXTICR2_EXTI6_PE_Pos) /*!< 0x00000400 */ 02352 #define AFIO_EXTICR2_EXTI6_PE AFIO_EXTICR2_EXTI6_PE_Msk /*!< PE[6] pin */ 02353 #define AFIO_EXTICR2_EXTI6_PF_Pos (8U) 02354 #define AFIO_EXTICR2_EXTI6_PF_Msk (0x5U << AFIO_EXTICR2_EXTI6_PF_Pos) /*!< 0x00000500 */ 02355 #define AFIO_EXTICR2_EXTI6_PF AFIO_EXTICR2_EXTI6_PF_Msk /*!< PF[6] pin */ 02356 #define AFIO_EXTICR2_EXTI6_PG_Pos (9U) 02357 #define AFIO_EXTICR2_EXTI6_PG_Msk (0x3U << AFIO_EXTICR2_EXTI6_PG_Pos) /*!< 0x00000600 */ 02358 #define AFIO_EXTICR2_EXTI6_PG AFIO_EXTICR2_EXTI6_PG_Msk /*!< PG[6] pin */ 02359 02360 /*!< EXTI7 configuration */ 02361 #define AFIO_EXTICR2_EXTI7_PA ((uint32_t)0x00000000) /*!< PA[7] pin */ 02362 #define AFIO_EXTICR2_EXTI7_PB_Pos (12U) 02363 #define AFIO_EXTICR2_EXTI7_PB_Msk (0x1U << AFIO_EXTICR2_EXTI7_PB_Pos) /*!< 0x00001000 */ 02364 #define AFIO_EXTICR2_EXTI7_PB AFIO_EXTICR2_EXTI7_PB_Msk /*!< PB[7] pin */ 02365 #define AFIO_EXTICR2_EXTI7_PC_Pos (13U) 02366 #define AFIO_EXTICR2_EXTI7_PC_Msk (0x1U << AFIO_EXTICR2_EXTI7_PC_Pos) /*!< 0x00002000 */ 02367 #define AFIO_EXTICR2_EXTI7_PC AFIO_EXTICR2_EXTI7_PC_Msk /*!< PC[7] pin */ 02368 #define AFIO_EXTICR2_EXTI7_PD_Pos (12U) 02369 #define AFIO_EXTICR2_EXTI7_PD_Msk (0x3U << AFIO_EXTICR2_EXTI7_PD_Pos) /*!< 0x00003000 */ 02370 #define AFIO_EXTICR2_EXTI7_PD AFIO_EXTICR2_EXTI7_PD_Msk /*!< PD[7] pin */ 02371 #define AFIO_EXTICR2_EXTI7_PE_Pos (14U) 02372 #define AFIO_EXTICR2_EXTI7_PE_Msk (0x1U << AFIO_EXTICR2_EXTI7_PE_Pos) /*!< 0x00004000 */ 02373 #define AFIO_EXTICR2_EXTI7_PE AFIO_EXTICR2_EXTI7_PE_Msk /*!< PE[7] pin */ 02374 #define AFIO_EXTICR2_EXTI7_PF_Pos (12U) 02375 #define AFIO_EXTICR2_EXTI7_PF_Msk (0x5U << AFIO_EXTICR2_EXTI7_PF_Pos) /*!< 0x00005000 */ 02376 #define AFIO_EXTICR2_EXTI7_PF AFIO_EXTICR2_EXTI7_PF_Msk /*!< PF[7] pin */ 02377 #define AFIO_EXTICR2_EXTI7_PG_Pos (13U) 02378 #define AFIO_EXTICR2_EXTI7_PG_Msk (0x3U << AFIO_EXTICR2_EXTI7_PG_Pos) /*!< 0x00006000 */ 02379 #define AFIO_EXTICR2_EXTI7_PG AFIO_EXTICR2_EXTI7_PG_Msk /*!< PG[7] pin */ 02380 02381 /***************** Bit definition for AFIO_EXTICR3 register *****************/ 02382 #define AFIO_EXTICR3_EXTI8_Pos (0U) 02383 #define AFIO_EXTICR3_EXTI8_Msk (0xFU << AFIO_EXTICR3_EXTI8_Pos) /*!< 0x0000000F */ 02384 #define AFIO_EXTICR3_EXTI8 AFIO_EXTICR3_EXTI8_Msk /*!< EXTI 8 configuration */ 02385 #define AFIO_EXTICR3_EXTI9_Pos (4U) 02386 #define AFIO_EXTICR3_EXTI9_Msk (0xFU << AFIO_EXTICR3_EXTI9_Pos) /*!< 0x000000F0 */ 02387 #define AFIO_EXTICR3_EXTI9 AFIO_EXTICR3_EXTI9_Msk /*!< EXTI 9 configuration */ 02388 #define AFIO_EXTICR3_EXTI10_Pos (8U) 02389 #define AFIO_EXTICR3_EXTI10_Msk (0xFU << AFIO_EXTICR3_EXTI10_Pos) /*!< 0x00000F00 */ 02390 #define AFIO_EXTICR3_EXTI10 AFIO_EXTICR3_EXTI10_Msk /*!< EXTI 10 configuration */ 02391 #define AFIO_EXTICR3_EXTI11_Pos (12U) 02392 #define AFIO_EXTICR3_EXTI11_Msk (0xFU << AFIO_EXTICR3_EXTI11_Pos) /*!< 0x0000F000 */ 02393 #define AFIO_EXTICR3_EXTI11 AFIO_EXTICR3_EXTI11_Msk /*!< EXTI 11 configuration */ 02394 02395 /*!< EXTI8 configuration */ 02396 #define AFIO_EXTICR3_EXTI8_PA ((uint32_t)0x00000000) /*!< PA[8] pin */ 02397 #define AFIO_EXTICR3_EXTI8_PB_Pos (0U) 02398 #define AFIO_EXTICR3_EXTI8_PB_Msk (0x1U << AFIO_EXTICR3_EXTI8_PB_Pos) /*!< 0x00000001 */ 02399 #define AFIO_EXTICR3_EXTI8_PB AFIO_EXTICR3_EXTI8_PB_Msk /*!< PB[8] pin */ 02400 #define AFIO_EXTICR3_EXTI8_PC_Pos (1U) 02401 #define AFIO_EXTICR3_EXTI8_PC_Msk (0x1U << AFIO_EXTICR3_EXTI8_PC_Pos) /*!< 0x00000002 */ 02402 #define AFIO_EXTICR3_EXTI8_PC AFIO_EXTICR3_EXTI8_PC_Msk /*!< PC[8] pin */ 02403 #define AFIO_EXTICR3_EXTI8_PD_Pos (0U) 02404 #define AFIO_EXTICR3_EXTI8_PD_Msk (0x3U << AFIO_EXTICR3_EXTI8_PD_Pos) /*!< 0x00000003 */ 02405 #define AFIO_EXTICR3_EXTI8_PD AFIO_EXTICR3_EXTI8_PD_Msk /*!< PD[8] pin */ 02406 #define AFIO_EXTICR3_EXTI8_PE_Pos (2U) 02407 #define AFIO_EXTICR3_EXTI8_PE_Msk (0x1U << AFIO_EXTICR3_EXTI8_PE_Pos) /*!< 0x00000004 */ 02408 #define AFIO_EXTICR3_EXTI8_PE AFIO_EXTICR3_EXTI8_PE_Msk /*!< PE[8] pin */ 02409 #define AFIO_EXTICR3_EXTI8_PF_Pos (0U) 02410 #define AFIO_EXTICR3_EXTI8_PF_Msk (0x5U << AFIO_EXTICR3_EXTI8_PF_Pos) /*!< 0x00000005 */ 02411 #define AFIO_EXTICR3_EXTI8_PF AFIO_EXTICR3_EXTI8_PF_Msk /*!< PF[8] pin */ 02412 #define AFIO_EXTICR3_EXTI8_PG_Pos (1U) 02413 #define AFIO_EXTICR3_EXTI8_PG_Msk (0x3U << AFIO_EXTICR3_EXTI8_PG_Pos) /*!< 0x00000006 */ 02414 #define AFIO_EXTICR3_EXTI8_PG AFIO_EXTICR3_EXTI8_PG_Msk /*!< PG[8] pin */ 02415 02416 /*!< EXTI9 configuration */ 02417 #define AFIO_EXTICR3_EXTI9_PA ((uint32_t)0x00000000) /*!< PA[9] pin */ 02418 #define AFIO_EXTICR3_EXTI9_PB_Pos (4U) 02419 #define AFIO_EXTICR3_EXTI9_PB_Msk (0x1U << AFIO_EXTICR3_EXTI9_PB_Pos) /*!< 0x00000010 */ 02420 #define AFIO_EXTICR3_EXTI9_PB AFIO_EXTICR3_EXTI9_PB_Msk /*!< PB[9] pin */ 02421 #define AFIO_EXTICR3_EXTI9_PC_Pos (5U) 02422 #define AFIO_EXTICR3_EXTI9_PC_Msk (0x1U << AFIO_EXTICR3_EXTI9_PC_Pos) /*!< 0x00000020 */ 02423 #define AFIO_EXTICR3_EXTI9_PC AFIO_EXTICR3_EXTI9_PC_Msk /*!< PC[9] pin */ 02424 #define AFIO_EXTICR3_EXTI9_PD_Pos (4U) 02425 #define AFIO_EXTICR3_EXTI9_PD_Msk (0x3U << AFIO_EXTICR3_EXTI9_PD_Pos) /*!< 0x00000030 */ 02426 #define AFIO_EXTICR3_EXTI9_PD AFIO_EXTICR3_EXTI9_PD_Msk /*!< PD[9] pin */ 02427 #define AFIO_EXTICR3_EXTI9_PE_Pos (6U) 02428 #define AFIO_EXTICR3_EXTI9_PE_Msk (0x1U << AFIO_EXTICR3_EXTI9_PE_Pos) /*!< 0x00000040 */ 02429 #define AFIO_EXTICR3_EXTI9_PE AFIO_EXTICR3_EXTI9_PE_Msk /*!< PE[9] pin */ 02430 #define AFIO_EXTICR3_EXTI9_PF_Pos (4U) 02431 #define AFIO_EXTICR3_EXTI9_PF_Msk (0x5U << AFIO_EXTICR3_EXTI9_PF_Pos) /*!< 0x00000050 */ 02432 #define AFIO_EXTICR3_EXTI9_PF AFIO_EXTICR3_EXTI9_PF_Msk /*!< PF[9] pin */ 02433 #define AFIO_EXTICR3_EXTI9_PG_Pos (5U) 02434 #define AFIO_EXTICR3_EXTI9_PG_Msk (0x3U << AFIO_EXTICR3_EXTI9_PG_Pos) /*!< 0x00000060 */ 02435 #define AFIO_EXTICR3_EXTI9_PG AFIO_EXTICR3_EXTI9_PG_Msk /*!< PG[9] pin */ 02436 02437 /*!< EXTI10 configuration */ 02438 #define AFIO_EXTICR3_EXTI10_PA ((uint32_t)0x00000000) /*!< PA[10] pin */ 02439 #define AFIO_EXTICR3_EXTI10_PB_Pos (8U) 02440 #define AFIO_EXTICR3_EXTI10_PB_Msk (0x1U << AFIO_EXTICR3_EXTI10_PB_Pos) /*!< 0x00000100 */ 02441 #define AFIO_EXTICR3_EXTI10_PB AFIO_EXTICR3_EXTI10_PB_Msk /*!< PB[10] pin */ 02442 #define AFIO_EXTICR3_EXTI10_PC_Pos (9U) 02443 #define AFIO_EXTICR3_EXTI10_PC_Msk (0x1U << AFIO_EXTICR3_EXTI10_PC_Pos) /*!< 0x00000200 */ 02444 #define AFIO_EXTICR3_EXTI10_PC AFIO_EXTICR3_EXTI10_PC_Msk /*!< PC[10] pin */ 02445 #define AFIO_EXTICR3_EXTI10_PD_Pos (8U) 02446 #define AFIO_EXTICR3_EXTI10_PD_Msk (0x3U << AFIO_EXTICR3_EXTI10_PD_Pos) /*!< 0x00000300 */ 02447 #define AFIO_EXTICR3_EXTI10_PD AFIO_EXTICR3_EXTI10_PD_Msk /*!< PD[10] pin */ 02448 #define AFIO_EXTICR3_EXTI10_PE_Pos (10U) 02449 #define AFIO_EXTICR3_EXTI10_PE_Msk (0x1U << AFIO_EXTICR3_EXTI10_PE_Pos) /*!< 0x00000400 */ 02450 #define AFIO_EXTICR3_EXTI10_PE AFIO_EXTICR3_EXTI10_PE_Msk /*!< PE[10] pin */ 02451 #define AFIO_EXTICR3_EXTI10_PF_Pos (8U) 02452 #define AFIO_EXTICR3_EXTI10_PF_Msk (0x5U << AFIO_EXTICR3_EXTI10_PF_Pos) /*!< 0x00000500 */ 02453 #define AFIO_EXTICR3_EXTI10_PF AFIO_EXTICR3_EXTI10_PF_Msk /*!< PF[10] pin */ 02454 #define AFIO_EXTICR3_EXTI10_PG_Pos (9U) 02455 #define AFIO_EXTICR3_EXTI10_PG_Msk (0x3U << AFIO_EXTICR3_EXTI10_PG_Pos) /*!< 0x00000600 */ 02456 #define AFIO_EXTICR3_EXTI10_PG AFIO_EXTICR3_EXTI10_PG_Msk /*!< PG[10] pin */ 02457 02458 /*!< EXTI11 configuration */ 02459 #define AFIO_EXTICR3_EXTI11_PA ((uint32_t)0x00000000) /*!< PA[11] pin */ 02460 #define AFIO_EXTICR3_EXTI11_PB_Pos (12U) 02461 #define AFIO_EXTICR3_EXTI11_PB_Msk (0x1U << AFIO_EXTICR3_EXTI11_PB_Pos) /*!< 0x00001000 */ 02462 #define AFIO_EXTICR3_EXTI11_PB AFIO_EXTICR3_EXTI11_PB_Msk /*!< PB[11] pin */ 02463 #define AFIO_EXTICR3_EXTI11_PC_Pos (13U) 02464 #define AFIO_EXTICR3_EXTI11_PC_Msk (0x1U << AFIO_EXTICR3_EXTI11_PC_Pos) /*!< 0x00002000 */ 02465 #define AFIO_EXTICR3_EXTI11_PC AFIO_EXTICR3_EXTI11_PC_Msk /*!< PC[11] pin */ 02466 #define AFIO_EXTICR3_EXTI11_PD_Pos (12U) 02467 #define AFIO_EXTICR3_EXTI11_PD_Msk (0x3U << AFIO_EXTICR3_EXTI11_PD_Pos) /*!< 0x00003000 */ 02468 #define AFIO_EXTICR3_EXTI11_PD AFIO_EXTICR3_EXTI11_PD_Msk /*!< PD[11] pin */ 02469 #define AFIO_EXTICR3_EXTI11_PE_Pos (14U) 02470 #define AFIO_EXTICR3_EXTI11_PE_Msk (0x1U << AFIO_EXTICR3_EXTI11_PE_Pos) /*!< 0x00004000 */ 02471 #define AFIO_EXTICR3_EXTI11_PE AFIO_EXTICR3_EXTI11_PE_Msk /*!< PE[11] pin */ 02472 #define AFIO_EXTICR3_EXTI11_PF_Pos (12U) 02473 #define AFIO_EXTICR3_EXTI11_PF_Msk (0x5U << AFIO_EXTICR3_EXTI11_PF_Pos) /*!< 0x00005000 */ 02474 #define AFIO_EXTICR3_EXTI11_PF AFIO_EXTICR3_EXTI11_PF_Msk /*!< PF[11] pin */ 02475 #define AFIO_EXTICR3_EXTI11_PG_Pos (13U) 02476 #define AFIO_EXTICR3_EXTI11_PG_Msk (0x3U << AFIO_EXTICR3_EXTI11_PG_Pos) /*!< 0x00006000 */ 02477 #define AFIO_EXTICR3_EXTI11_PG AFIO_EXTICR3_EXTI11_PG_Msk /*!< PG[11] pin */ 02478 02479 /***************** Bit definition for AFIO_EXTICR4 register *****************/ 02480 #define AFIO_EXTICR4_EXTI12_Pos (0U) 02481 #define AFIO_EXTICR4_EXTI12_Msk (0xFU << AFIO_EXTICR4_EXTI12_Pos) /*!< 0x0000000F */ 02482 #define AFIO_EXTICR4_EXTI12 AFIO_EXTICR4_EXTI12_Msk /*!< EXTI 12 configuration */ 02483 #define AFIO_EXTICR4_EXTI13_Pos (4U) 02484 #define AFIO_EXTICR4_EXTI13_Msk (0xFU << AFIO_EXTICR4_EXTI13_Pos) /*!< 0x000000F0 */ 02485 #define AFIO_EXTICR4_EXTI13 AFIO_EXTICR4_EXTI13_Msk /*!< EXTI 13 configuration */ 02486 #define AFIO_EXTICR4_EXTI14_Pos (8U) 02487 #define AFIO_EXTICR4_EXTI14_Msk (0xFU << AFIO_EXTICR4_EXTI14_Pos) /*!< 0x00000F00 */ 02488 #define AFIO_EXTICR4_EXTI14 AFIO_EXTICR4_EXTI14_Msk /*!< EXTI 14 configuration */ 02489 #define AFIO_EXTICR4_EXTI15_Pos (12U) 02490 #define AFIO_EXTICR4_EXTI15_Msk (0xFU << AFIO_EXTICR4_EXTI15_Pos) /*!< 0x0000F000 */ 02491 #define AFIO_EXTICR4_EXTI15 AFIO_EXTICR4_EXTI15_Msk /*!< EXTI 15 configuration */ 02492 02493 /* EXTI12 configuration */ 02494 #define AFIO_EXTICR4_EXTI12_PA ((uint32_t)0x00000000) /*!< PA[12] pin */ 02495 #define AFIO_EXTICR4_EXTI12_PB_Pos (0U) 02496 #define AFIO_EXTICR4_EXTI12_PB_Msk (0x1U << AFIO_EXTICR4_EXTI12_PB_Pos) /*!< 0x00000001 */ 02497 #define AFIO_EXTICR4_EXTI12_PB AFIO_EXTICR4_EXTI12_PB_Msk /*!< PB[12] pin */ 02498 #define AFIO_EXTICR4_EXTI12_PC_Pos (1U) 02499 #define AFIO_EXTICR4_EXTI12_PC_Msk (0x1U << AFIO_EXTICR4_EXTI12_PC_Pos) /*!< 0x00000002 */ 02500 #define AFIO_EXTICR4_EXTI12_PC AFIO_EXTICR4_EXTI12_PC_Msk /*!< PC[12] pin */ 02501 #define AFIO_EXTICR4_EXTI12_PD_Pos (0U) 02502 #define AFIO_EXTICR4_EXTI12_PD_Msk (0x3U << AFIO_EXTICR4_EXTI12_PD_Pos) /*!< 0x00000003 */ 02503 #define AFIO_EXTICR4_EXTI12_PD AFIO_EXTICR4_EXTI12_PD_Msk /*!< PD[12] pin */ 02504 #define AFIO_EXTICR4_EXTI12_PE_Pos (2U) 02505 #define AFIO_EXTICR4_EXTI12_PE_Msk (0x1U << AFIO_EXTICR4_EXTI12_PE_Pos) /*!< 0x00000004 */ 02506 #define AFIO_EXTICR4_EXTI12_PE AFIO_EXTICR4_EXTI12_PE_Msk /*!< PE[12] pin */ 02507 #define AFIO_EXTICR4_EXTI12_PF_Pos (0U) 02508 #define AFIO_EXTICR4_EXTI12_PF_Msk (0x5U << AFIO_EXTICR4_EXTI12_PF_Pos) /*!< 0x00000005 */ 02509 #define AFIO_EXTICR4_EXTI12_PF AFIO_EXTICR4_EXTI12_PF_Msk /*!< PF[12] pin */ 02510 #define AFIO_EXTICR4_EXTI12_PG_Pos (1U) 02511 #define AFIO_EXTICR4_EXTI12_PG_Msk (0x3U << AFIO_EXTICR4_EXTI12_PG_Pos) /*!< 0x00000006 */ 02512 #define AFIO_EXTICR4_EXTI12_PG AFIO_EXTICR4_EXTI12_PG_Msk /*!< PG[12] pin */ 02513 02514 /* EXTI13 configuration */ 02515 #define AFIO_EXTICR4_EXTI13_PA ((uint32_t)0x00000000) /*!< PA[13] pin */ 02516 #define AFIO_EXTICR4_EXTI13_PB_Pos (4U) 02517 #define AFIO_EXTICR4_EXTI13_PB_Msk (0x1U << AFIO_EXTICR4_EXTI13_PB_Pos) /*!< 0x00000010 */ 02518 #define AFIO_EXTICR4_EXTI13_PB AFIO_EXTICR4_EXTI13_PB_Msk /*!< PB[13] pin */ 02519 #define AFIO_EXTICR4_EXTI13_PC_Pos (5U) 02520 #define AFIO_EXTICR4_EXTI13_PC_Msk (0x1U << AFIO_EXTICR4_EXTI13_PC_Pos) /*!< 0x00000020 */ 02521 #define AFIO_EXTICR4_EXTI13_PC AFIO_EXTICR4_EXTI13_PC_Msk /*!< PC[13] pin */ 02522 #define AFIO_EXTICR4_EXTI13_PD_Pos (4U) 02523 #define AFIO_EXTICR4_EXTI13_PD_Msk (0x3U << AFIO_EXTICR4_EXTI13_PD_Pos) /*!< 0x00000030 */ 02524 #define AFIO_EXTICR4_EXTI13_PD AFIO_EXTICR4_EXTI13_PD_Msk /*!< PD[13] pin */ 02525 #define AFIO_EXTICR4_EXTI13_PE_Pos (6U) 02526 #define AFIO_EXTICR4_EXTI13_PE_Msk (0x1U << AFIO_EXTICR4_EXTI13_PE_Pos) /*!< 0x00000040 */ 02527 #define AFIO_EXTICR4_EXTI13_PE AFIO_EXTICR4_EXTI13_PE_Msk /*!< PE[13] pin */ 02528 #define AFIO_EXTICR4_EXTI13_PF_Pos (4U) 02529 #define AFIO_EXTICR4_EXTI13_PF_Msk (0x5U << AFIO_EXTICR4_EXTI13_PF_Pos) /*!< 0x00000050 */ 02530 #define AFIO_EXTICR4_EXTI13_PF AFIO_EXTICR4_EXTI13_PF_Msk /*!< PF[13] pin */ 02531 #define AFIO_EXTICR4_EXTI13_PG_Pos (5U) 02532 #define AFIO_EXTICR4_EXTI13_PG_Msk (0x3U << AFIO_EXTICR4_EXTI13_PG_Pos) /*!< 0x00000060 */ 02533 #define AFIO_EXTICR4_EXTI13_PG AFIO_EXTICR4_EXTI13_PG_Msk /*!< PG[13] pin */ 02534 02535 /*!< EXTI14 configuration */ 02536 #define AFIO_EXTICR4_EXTI14_PA ((uint32_t)0x00000000) /*!< PA[14] pin */ 02537 #define AFIO_EXTICR4_EXTI14_PB_Pos (8U) 02538 #define AFIO_EXTICR4_EXTI14_PB_Msk (0x1U << AFIO_EXTICR4_EXTI14_PB_Pos) /*!< 0x00000100 */ 02539 #define AFIO_EXTICR4_EXTI14_PB AFIO_EXTICR4_EXTI14_PB_Msk /*!< PB[14] pin */ 02540 #define AFIO_EXTICR4_EXTI14_PC_Pos (9U) 02541 #define AFIO_EXTICR4_EXTI14_PC_Msk (0x1U << AFIO_EXTICR4_EXTI14_PC_Pos) /*!< 0x00000200 */ 02542 #define AFIO_EXTICR4_EXTI14_PC AFIO_EXTICR4_EXTI14_PC_Msk /*!< PC[14] pin */ 02543 #define AFIO_EXTICR4_EXTI14_PD_Pos (8U) 02544 #define AFIO_EXTICR4_EXTI14_PD_Msk (0x3U << AFIO_EXTICR4_EXTI14_PD_Pos) /*!< 0x00000300 */ 02545 #define AFIO_EXTICR4_EXTI14_PD AFIO_EXTICR4_EXTI14_PD_Msk /*!< PD[14] pin */ 02546 #define AFIO_EXTICR4_EXTI14_PE_Pos (10U) 02547 #define AFIO_EXTICR4_EXTI14_PE_Msk (0x1U << AFIO_EXTICR4_EXTI14_PE_Pos) /*!< 0x00000400 */ 02548 #define AFIO_EXTICR4_EXTI14_PE AFIO_EXTICR4_EXTI14_PE_Msk /*!< PE[14] pin */ 02549 #define AFIO_EXTICR4_EXTI14_PF_Pos (8U) 02550 #define AFIO_EXTICR4_EXTI14_PF_Msk (0x5U << AFIO_EXTICR4_EXTI14_PF_Pos) /*!< 0x00000500 */ 02551 #define AFIO_EXTICR4_EXTI14_PF AFIO_EXTICR4_EXTI14_PF_Msk /*!< PF[14] pin */ 02552 #define AFIO_EXTICR4_EXTI14_PG_Pos (9U) 02553 #define AFIO_EXTICR4_EXTI14_PG_Msk (0x3U << AFIO_EXTICR4_EXTI14_PG_Pos) /*!< 0x00000600 */ 02554 #define AFIO_EXTICR4_EXTI14_PG AFIO_EXTICR4_EXTI14_PG_Msk /*!< PG[14] pin */ 02555 02556 /*!< EXTI15 configuration */ 02557 #define AFIO_EXTICR4_EXTI15_PA ((uint32_t)0x00000000) /*!< PA[15] pin */ 02558 #define AFIO_EXTICR4_EXTI15_PB_Pos (12U) 02559 #define AFIO_EXTICR4_EXTI15_PB_Msk (0x1U << AFIO_EXTICR4_EXTI15_PB_Pos) /*!< 0x00001000 */ 02560 #define AFIO_EXTICR4_EXTI15_PB AFIO_EXTICR4_EXTI15_PB_Msk /*!< PB[15] pin */ 02561 #define AFIO_EXTICR4_EXTI15_PC_Pos (13U) 02562 #define AFIO_EXTICR4_EXTI15_PC_Msk (0x1U << AFIO_EXTICR4_EXTI15_PC_Pos) /*!< 0x00002000 */ 02563 #define AFIO_EXTICR4_EXTI15_PC AFIO_EXTICR4_EXTI15_PC_Msk /*!< PC[15] pin */ 02564 #define AFIO_EXTICR4_EXTI15_PD_Pos (12U) 02565 #define AFIO_EXTICR4_EXTI15_PD_Msk (0x3U << AFIO_EXTICR4_EXTI15_PD_Pos) /*!< 0x00003000 */ 02566 #define AFIO_EXTICR4_EXTI15_PD AFIO_EXTICR4_EXTI15_PD_Msk /*!< PD[15] pin */ 02567 #define AFIO_EXTICR4_EXTI15_PE_Pos (14U) 02568 #define AFIO_EXTICR4_EXTI15_PE_Msk (0x1U << AFIO_EXTICR4_EXTI15_PE_Pos) /*!< 0x00004000 */ 02569 #define AFIO_EXTICR4_EXTI15_PE AFIO_EXTICR4_EXTI15_PE_Msk /*!< PE[15] pin */ 02570 #define AFIO_EXTICR4_EXTI15_PF_Pos (12U) 02571 #define AFIO_EXTICR4_EXTI15_PF_Msk (0x5U << AFIO_EXTICR4_EXTI15_PF_Pos) /*!< 0x00005000 */ 02572 #define AFIO_EXTICR4_EXTI15_PF AFIO_EXTICR4_EXTI15_PF_Msk /*!< PF[15] pin */ 02573 #define AFIO_EXTICR4_EXTI15_PG_Pos (13U) 02574 #define AFIO_EXTICR4_EXTI15_PG_Msk (0x3U << AFIO_EXTICR4_EXTI15_PG_Pos) /*!< 0x00006000 */ 02575 #define AFIO_EXTICR4_EXTI15_PG AFIO_EXTICR4_EXTI15_PG_Msk /*!< PG[15] pin */ 02576 02577 /****************** Bit definition for AFIO_MAPR2 register ******************/ 02578 02579 02580 02581 /******************************************************************************/ 02582 /* */ 02583 /* External Interrupt/Event Controller */ 02584 /* */ 02585 /******************************************************************************/ 02586 02587 /******************* Bit definition for EXTI_IMR register *******************/ 02588 #define EXTI_IMR_MR0_Pos (0U) 02589 #define EXTI_IMR_MR0_Msk (0x1U << EXTI_IMR_MR0_Pos) /*!< 0x00000001 */ 02590 #define EXTI_IMR_MR0 EXTI_IMR_MR0_Msk /*!< Interrupt Mask on line 0 */ 02591 #define EXTI_IMR_MR1_Pos (1U) 02592 #define EXTI_IMR_MR1_Msk (0x1U << EXTI_IMR_MR1_Pos) /*!< 0x00000002 */ 02593 #define EXTI_IMR_MR1 EXTI_IMR_MR1_Msk /*!< Interrupt Mask on line 1 */ 02594 #define EXTI_IMR_MR2_Pos (2U) 02595 #define EXTI_IMR_MR2_Msk (0x1U << EXTI_IMR_MR2_Pos) /*!< 0x00000004 */ 02596 #define EXTI_IMR_MR2 EXTI_IMR_MR2_Msk /*!< Interrupt Mask on line 2 */ 02597 #define EXTI_IMR_MR3_Pos (3U) 02598 #define EXTI_IMR_MR3_Msk (0x1U << EXTI_IMR_MR3_Pos) /*!< 0x00000008 */ 02599 #define EXTI_IMR_MR3 EXTI_IMR_MR3_Msk /*!< Interrupt Mask on line 3 */ 02600 #define EXTI_IMR_MR4_Pos (4U) 02601 #define EXTI_IMR_MR4_Msk (0x1U << EXTI_IMR_MR4_Pos) /*!< 0x00000010 */ 02602 #define EXTI_IMR_MR4 EXTI_IMR_MR4_Msk /*!< Interrupt Mask on line 4 */ 02603 #define EXTI_IMR_MR5_Pos (5U) 02604 #define EXTI_IMR_MR5_Msk (0x1U << EXTI_IMR_MR5_Pos) /*!< 0x00000020 */ 02605 #define EXTI_IMR_MR5 EXTI_IMR_MR5_Msk /*!< Interrupt Mask on line 5 */ 02606 #define EXTI_IMR_MR6_Pos (6U) 02607 #define EXTI_IMR_MR6_Msk (0x1U << EXTI_IMR_MR6_Pos) /*!< 0x00000040 */ 02608 #define EXTI_IMR_MR6 EXTI_IMR_MR6_Msk /*!< Interrupt Mask on line 6 */ 02609 #define EXTI_IMR_MR7_Pos (7U) 02610 #define EXTI_IMR_MR7_Msk (0x1U << EXTI_IMR_MR7_Pos) /*!< 0x00000080 */ 02611 #define EXTI_IMR_MR7 EXTI_IMR_MR7_Msk /*!< Interrupt Mask on line 7 */ 02612 #define EXTI_IMR_MR8_Pos (8U) 02613 #define EXTI_IMR_MR8_Msk (0x1U << EXTI_IMR_MR8_Pos) /*!< 0x00000100 */ 02614 #define EXTI_IMR_MR8 EXTI_IMR_MR8_Msk /*!< Interrupt Mask on line 8 */ 02615 #define EXTI_IMR_MR9_Pos (9U) 02616 #define EXTI_IMR_MR9_Msk (0x1U << EXTI_IMR_MR9_Pos) /*!< 0x00000200 */ 02617 #define EXTI_IMR_MR9 EXTI_IMR_MR9_Msk /*!< Interrupt Mask on line 9 */ 02618 #define EXTI_IMR_MR10_Pos (10U) 02619 #define EXTI_IMR_MR10_Msk (0x1U << EXTI_IMR_MR10_Pos) /*!< 0x00000400 */ 02620 #define EXTI_IMR_MR10 EXTI_IMR_MR10_Msk /*!< Interrupt Mask on line 10 */ 02621 #define EXTI_IMR_MR11_Pos (11U) 02622 #define EXTI_IMR_MR11_Msk (0x1U << EXTI_IMR_MR11_Pos) /*!< 0x00000800 */ 02623 #define EXTI_IMR_MR11 EXTI_IMR_MR11_Msk /*!< Interrupt Mask on line 11 */ 02624 #define EXTI_IMR_MR12_Pos (12U) 02625 #define EXTI_IMR_MR12_Msk (0x1U << EXTI_IMR_MR12_Pos) /*!< 0x00001000 */ 02626 #define EXTI_IMR_MR12 EXTI_IMR_MR12_Msk /*!< Interrupt Mask on line 12 */ 02627 #define EXTI_IMR_MR13_Pos (13U) 02628 #define EXTI_IMR_MR13_Msk (0x1U << EXTI_IMR_MR13_Pos) /*!< 0x00002000 */ 02629 #define EXTI_IMR_MR13 EXTI_IMR_MR13_Msk /*!< Interrupt Mask on line 13 */ 02630 #define EXTI_IMR_MR14_Pos (14U) 02631 #define EXTI_IMR_MR14_Msk (0x1U << EXTI_IMR_MR14_Pos) /*!< 0x00004000 */ 02632 #define EXTI_IMR_MR14 EXTI_IMR_MR14_Msk /*!< Interrupt Mask on line 14 */ 02633 #define EXTI_IMR_MR15_Pos (15U) 02634 #define EXTI_IMR_MR15_Msk (0x1U << EXTI_IMR_MR15_Pos) /*!< 0x00008000 */ 02635 #define EXTI_IMR_MR15 EXTI_IMR_MR15_Msk /*!< Interrupt Mask on line 15 */ 02636 #define EXTI_IMR_MR16_Pos (16U) 02637 #define EXTI_IMR_MR16_Msk (0x1U << EXTI_IMR_MR16_Pos) /*!< 0x00010000 */ 02638 #define EXTI_IMR_MR16 EXTI_IMR_MR16_Msk /*!< Interrupt Mask on line 16 */ 02639 #define EXTI_IMR_MR17_Pos (17U) 02640 #define EXTI_IMR_MR17_Msk (0x1U << EXTI_IMR_MR17_Pos) /*!< 0x00020000 */ 02641 #define EXTI_IMR_MR17 EXTI_IMR_MR17_Msk /*!< Interrupt Mask on line 17 */ 02642 #define EXTI_IMR_MR18_Pos (18U) 02643 #define EXTI_IMR_MR18_Msk (0x1U << EXTI_IMR_MR18_Pos) /*!< 0x00040000 */ 02644 #define EXTI_IMR_MR18 EXTI_IMR_MR18_Msk /*!< Interrupt Mask on line 18 */ 02645 #define EXTI_IMR_MR19_Pos (19U) 02646 #define EXTI_IMR_MR19_Msk (0x1U << EXTI_IMR_MR19_Pos) /*!< 0x00080000 */ 02647 #define EXTI_IMR_MR19 EXTI_IMR_MR19_Msk /*!< Interrupt Mask on line 19 */ 02648 02649 /* References Defines */ 02650 #define EXTI_IMR_IM0 EXTI_IMR_MR0 02651 #define EXTI_IMR_IM1 EXTI_IMR_MR1 02652 #define EXTI_IMR_IM2 EXTI_IMR_MR2 02653 #define EXTI_IMR_IM3 EXTI_IMR_MR3 02654 #define EXTI_IMR_IM4 EXTI_IMR_MR4 02655 #define EXTI_IMR_IM5 EXTI_IMR_MR5 02656 #define EXTI_IMR_IM6 EXTI_IMR_MR6 02657 #define EXTI_IMR_IM7 EXTI_IMR_MR7 02658 #define EXTI_IMR_IM8 EXTI_IMR_MR8 02659 #define EXTI_IMR_IM9 EXTI_IMR_MR9 02660 #define EXTI_IMR_IM10 EXTI_IMR_MR10 02661 #define EXTI_IMR_IM11 EXTI_IMR_MR11 02662 #define EXTI_IMR_IM12 EXTI_IMR_MR12 02663 #define EXTI_IMR_IM13 EXTI_IMR_MR13 02664 #define EXTI_IMR_IM14 EXTI_IMR_MR14 02665 #define EXTI_IMR_IM15 EXTI_IMR_MR15 02666 #define EXTI_IMR_IM16 EXTI_IMR_MR16 02667 #define EXTI_IMR_IM17 EXTI_IMR_MR17 02668 #define EXTI_IMR_IM18 EXTI_IMR_MR18 02669 #define EXTI_IMR_IM19 EXTI_IMR_MR19 02670 02671 /******************* Bit definition for EXTI_EMR register *******************/ 02672 #define EXTI_EMR_MR0_Pos (0U) 02673 #define EXTI_EMR_MR0_Msk (0x1U << EXTI_EMR_MR0_Pos) /*!< 0x00000001 */ 02674 #define EXTI_EMR_MR0 EXTI_EMR_MR0_Msk /*!< Event Mask on line 0 */ 02675 #define EXTI_EMR_MR1_Pos (1U) 02676 #define EXTI_EMR_MR1_Msk (0x1U << EXTI_EMR_MR1_Pos) /*!< 0x00000002 */ 02677 #define EXTI_EMR_MR1 EXTI_EMR_MR1_Msk /*!< Event Mask on line 1 */ 02678 #define EXTI_EMR_MR2_Pos (2U) 02679 #define EXTI_EMR_MR2_Msk (0x1U << EXTI_EMR_MR2_Pos) /*!< 0x00000004 */ 02680 #define EXTI_EMR_MR2 EXTI_EMR_MR2_Msk /*!< Event Mask on line 2 */ 02681 #define EXTI_EMR_MR3_Pos (3U) 02682 #define EXTI_EMR_MR3_Msk (0x1U << EXTI_EMR_MR3_Pos) /*!< 0x00000008 */ 02683 #define EXTI_EMR_MR3 EXTI_EMR_MR3_Msk /*!< Event Mask on line 3 */ 02684 #define EXTI_EMR_MR4_Pos (4U) 02685 #define EXTI_EMR_MR4_Msk (0x1U << EXTI_EMR_MR4_Pos) /*!< 0x00000010 */ 02686 #define EXTI_EMR_MR4 EXTI_EMR_MR4_Msk /*!< Event Mask on line 4 */ 02687 #define EXTI_EMR_MR5_Pos (5U) 02688 #define EXTI_EMR_MR5_Msk (0x1U << EXTI_EMR_MR5_Pos) /*!< 0x00000020 */ 02689 #define EXTI_EMR_MR5 EXTI_EMR_MR5_Msk /*!< Event Mask on line 5 */ 02690 #define EXTI_EMR_MR6_Pos (6U) 02691 #define EXTI_EMR_MR6_Msk (0x1U << EXTI_EMR_MR6_Pos) /*!< 0x00000040 */ 02692 #define EXTI_EMR_MR6 EXTI_EMR_MR6_Msk /*!< Event Mask on line 6 */ 02693 #define EXTI_EMR_MR7_Pos (7U) 02694 #define EXTI_EMR_MR7_Msk (0x1U << EXTI_EMR_MR7_Pos) /*!< 0x00000080 */ 02695 #define EXTI_EMR_MR7 EXTI_EMR_MR7_Msk /*!< Event Mask on line 7 */ 02696 #define EXTI_EMR_MR8_Pos (8U) 02697 #define EXTI_EMR_MR8_Msk (0x1U << EXTI_EMR_MR8_Pos) /*!< 0x00000100 */ 02698 #define EXTI_EMR_MR8 EXTI_EMR_MR8_Msk /*!< Event Mask on line 8 */ 02699 #define EXTI_EMR_MR9_Pos (9U) 02700 #define EXTI_EMR_MR9_Msk (0x1U << EXTI_EMR_MR9_Pos) /*!< 0x00000200 */ 02701 #define EXTI_EMR_MR9 EXTI_EMR_MR9_Msk /*!< Event Mask on line 9 */ 02702 #define EXTI_EMR_MR10_Pos (10U) 02703 #define EXTI_EMR_MR10_Msk (0x1U << EXTI_EMR_MR10_Pos) /*!< 0x00000400 */ 02704 #define EXTI_EMR_MR10 EXTI_EMR_MR10_Msk /*!< Event Mask on line 10 */ 02705 #define EXTI_EMR_MR11_Pos (11U) 02706 #define EXTI_EMR_MR11_Msk (0x1U << EXTI_EMR_MR11_Pos) /*!< 0x00000800 */ 02707 #define EXTI_EMR_MR11 EXTI_EMR_MR11_Msk /*!< Event Mask on line 11 */ 02708 #define EXTI_EMR_MR12_Pos (12U) 02709 #define EXTI_EMR_MR12_Msk (0x1U << EXTI_EMR_MR12_Pos) /*!< 0x00001000 */ 02710 #define EXTI_EMR_MR12 EXTI_EMR_MR12_Msk /*!< Event Mask on line 12 */ 02711 #define EXTI_EMR_MR13_Pos (13U) 02712 #define EXTI_EMR_MR13_Msk (0x1U << EXTI_EMR_MR13_Pos) /*!< 0x00002000 */ 02713 #define EXTI_EMR_MR13 EXTI_EMR_MR13_Msk /*!< Event Mask on line 13 */ 02714 #define EXTI_EMR_MR14_Pos (14U) 02715 #define EXTI_EMR_MR14_Msk (0x1U << EXTI_EMR_MR14_Pos) /*!< 0x00004000 */ 02716 #define EXTI_EMR_MR14 EXTI_EMR_MR14_Msk /*!< Event Mask on line 14 */ 02717 #define EXTI_EMR_MR15_Pos (15U) 02718 #define EXTI_EMR_MR15_Msk (0x1U << EXTI_EMR_MR15_Pos) /*!< 0x00008000 */ 02719 #define EXTI_EMR_MR15 EXTI_EMR_MR15_Msk /*!< Event Mask on line 15 */ 02720 #define EXTI_EMR_MR16_Pos (16U) 02721 #define EXTI_EMR_MR16_Msk (0x1U << EXTI_EMR_MR16_Pos) /*!< 0x00010000 */ 02722 #define EXTI_EMR_MR16 EXTI_EMR_MR16_Msk /*!< Event Mask on line 16 */ 02723 #define EXTI_EMR_MR17_Pos (17U) 02724 #define EXTI_EMR_MR17_Msk (0x1U << EXTI_EMR_MR17_Pos) /*!< 0x00020000 */ 02725 #define EXTI_EMR_MR17 EXTI_EMR_MR17_Msk /*!< Event Mask on line 17 */ 02726 #define EXTI_EMR_MR18_Pos (18U) 02727 #define EXTI_EMR_MR18_Msk (0x1U << EXTI_EMR_MR18_Pos) /*!< 0x00040000 */ 02728 #define EXTI_EMR_MR18 EXTI_EMR_MR18_Msk /*!< Event Mask on line 18 */ 02729 #define EXTI_EMR_MR19_Pos (19U) 02730 #define EXTI_EMR_MR19_Msk (0x1U << EXTI_EMR_MR19_Pos) /*!< 0x00080000 */ 02731 #define EXTI_EMR_MR19 EXTI_EMR_MR19_Msk /*!< Event Mask on line 19 */ 02732 02733 /* References Defines */ 02734 #define EXTI_EMR_EM0 EXTI_EMR_MR0 02735 #define EXTI_EMR_EM1 EXTI_EMR_MR1 02736 #define EXTI_EMR_EM2 EXTI_EMR_MR2 02737 #define EXTI_EMR_EM3 EXTI_EMR_MR3 02738 #define EXTI_EMR_EM4 EXTI_EMR_MR4 02739 #define EXTI_EMR_EM5 EXTI_EMR_MR5 02740 #define EXTI_EMR_EM6 EXTI_EMR_MR6 02741 #define EXTI_EMR_EM7 EXTI_EMR_MR7 02742 #define EXTI_EMR_EM8 EXTI_EMR_MR8 02743 #define EXTI_EMR_EM9 EXTI_EMR_MR9 02744 #define EXTI_EMR_EM10 EXTI_EMR_MR10 02745 #define EXTI_EMR_EM11 EXTI_EMR_MR11 02746 #define EXTI_EMR_EM12 EXTI_EMR_MR12 02747 #define EXTI_EMR_EM13 EXTI_EMR_MR13 02748 #define EXTI_EMR_EM14 EXTI_EMR_MR14 02749 #define EXTI_EMR_EM15 EXTI_EMR_MR15 02750 #define EXTI_EMR_EM16 EXTI_EMR_MR16 02751 #define EXTI_EMR_EM17 EXTI_EMR_MR17 02752 #define EXTI_EMR_EM18 EXTI_EMR_MR18 02753 #define EXTI_EMR_EM19 EXTI_EMR_MR19 02754 02755 /****************** Bit definition for EXTI_RTSR register *******************/ 02756 #define EXTI_RTSR_TR0_Pos (0U) 02757 #define EXTI_RTSR_TR0_Msk (0x1U << EXTI_RTSR_TR0_Pos) /*!< 0x00000001 */ 02758 #define EXTI_RTSR_TR0 EXTI_RTSR_TR0_Msk /*!< Rising trigger event configuration bit of line 0 */ 02759 #define EXTI_RTSR_TR1_Pos (1U) 02760 #define EXTI_RTSR_TR1_Msk (0x1U << EXTI_RTSR_TR1_Pos) /*!< 0x00000002 */ 02761 #define EXTI_RTSR_TR1 EXTI_RTSR_TR1_Msk /*!< Rising trigger event configuration bit of line 1 */ 02762 #define EXTI_RTSR_TR2_Pos (2U) 02763 #define EXTI_RTSR_TR2_Msk (0x1U << EXTI_RTSR_TR2_Pos) /*!< 0x00000004 */ 02764 #define EXTI_RTSR_TR2 EXTI_RTSR_TR2_Msk /*!< Rising trigger event configuration bit of line 2 */ 02765 #define EXTI_RTSR_TR3_Pos (3U) 02766 #define EXTI_RTSR_TR3_Msk (0x1U << EXTI_RTSR_TR3_Pos) /*!< 0x00000008 */ 02767 #define EXTI_RTSR_TR3 EXTI_RTSR_TR3_Msk /*!< Rising trigger event configuration bit of line 3 */ 02768 #define EXTI_RTSR_TR4_Pos (4U) 02769 #define EXTI_RTSR_TR4_Msk (0x1U << EXTI_RTSR_TR4_Pos) /*!< 0x00000010 */ 02770 #define EXTI_RTSR_TR4 EXTI_RTSR_TR4_Msk /*!< Rising trigger event configuration bit of line 4 */ 02771 #define EXTI_RTSR_TR5_Pos (5U) 02772 #define EXTI_RTSR_TR5_Msk (0x1U << EXTI_RTSR_TR5_Pos) /*!< 0x00000020 */ 02773 #define EXTI_RTSR_TR5 EXTI_RTSR_TR5_Msk /*!< Rising trigger event configuration bit of line 5 */ 02774 #define EXTI_RTSR_TR6_Pos (6U) 02775 #define EXTI_RTSR_TR6_Msk (0x1U << EXTI_RTSR_TR6_Pos) /*!< 0x00000040 */ 02776 #define EXTI_RTSR_TR6 EXTI_RTSR_TR6_Msk /*!< Rising trigger event configuration bit of line 6 */ 02777 #define EXTI_RTSR_TR7_Pos (7U) 02778 #define EXTI_RTSR_TR7_Msk (0x1U << EXTI_RTSR_TR7_Pos) /*!< 0x00000080 */ 02779 #define EXTI_RTSR_TR7 EXTI_RTSR_TR7_Msk /*!< Rising trigger event configuration bit of line 7 */ 02780 #define EXTI_RTSR_TR8_Pos (8U) 02781 #define EXTI_RTSR_TR8_Msk (0x1U << EXTI_RTSR_TR8_Pos) /*!< 0x00000100 */ 02782 #define EXTI_RTSR_TR8 EXTI_RTSR_TR8_Msk /*!< Rising trigger event configuration bit of line 8 */ 02783 #define EXTI_RTSR_TR9_Pos (9U) 02784 #define EXTI_RTSR_TR9_Msk (0x1U << EXTI_RTSR_TR9_Pos) /*!< 0x00000200 */ 02785 #define EXTI_RTSR_TR9 EXTI_RTSR_TR9_Msk /*!< Rising trigger event configuration bit of line 9 */ 02786 #define EXTI_RTSR_TR10_Pos (10U) 02787 #define EXTI_RTSR_TR10_Msk (0x1U << EXTI_RTSR_TR10_Pos) /*!< 0x00000400 */ 02788 #define EXTI_RTSR_TR10 EXTI_RTSR_TR10_Msk /*!< Rising trigger event configuration bit of line 10 */ 02789 #define EXTI_RTSR_TR11_Pos (11U) 02790 #define EXTI_RTSR_TR11_Msk (0x1U << EXTI_RTSR_TR11_Pos) /*!< 0x00000800 */ 02791 #define EXTI_RTSR_TR11 EXTI_RTSR_TR11_Msk /*!< Rising trigger event configuration bit of line 11 */ 02792 #define EXTI_RTSR_TR12_Pos (12U) 02793 #define EXTI_RTSR_TR12_Msk (0x1U << EXTI_RTSR_TR12_Pos) /*!< 0x00001000 */ 02794 #define EXTI_RTSR_TR12 EXTI_RTSR_TR12_Msk /*!< Rising trigger event configuration bit of line 12 */ 02795 #define EXTI_RTSR_TR13_Pos (13U) 02796 #define EXTI_RTSR_TR13_Msk (0x1U << EXTI_RTSR_TR13_Pos) /*!< 0x00002000 */ 02797 #define EXTI_RTSR_TR13 EXTI_RTSR_TR13_Msk /*!< Rising trigger event configuration bit of line 13 */ 02798 #define EXTI_RTSR_TR14_Pos (14U) 02799 #define EXTI_RTSR_TR14_Msk (0x1U << EXTI_RTSR_TR14_Pos) /*!< 0x00004000 */ 02800 #define EXTI_RTSR_TR14 EXTI_RTSR_TR14_Msk /*!< Rising trigger event configuration bit of line 14 */ 02801 #define EXTI_RTSR_TR15_Pos (15U) 02802 #define EXTI_RTSR_TR15_Msk (0x1U << EXTI_RTSR_TR15_Pos) /*!< 0x00008000 */ 02803 #define EXTI_RTSR_TR15 EXTI_RTSR_TR15_Msk /*!< Rising trigger event configuration bit of line 15 */ 02804 #define EXTI_RTSR_TR16_Pos (16U) 02805 #define EXTI_RTSR_TR16_Msk (0x1U << EXTI_RTSR_TR16_Pos) /*!< 0x00010000 */ 02806 #define EXTI_RTSR_TR16 EXTI_RTSR_TR16_Msk /*!< Rising trigger event configuration bit of line 16 */ 02807 #define EXTI_RTSR_TR17_Pos (17U) 02808 #define EXTI_RTSR_TR17_Msk (0x1U << EXTI_RTSR_TR17_Pos) /*!< 0x00020000 */ 02809 #define EXTI_RTSR_TR17 EXTI_RTSR_TR17_Msk /*!< Rising trigger event configuration bit of line 17 */ 02810 #define EXTI_RTSR_TR18_Pos (18U) 02811 #define EXTI_RTSR_TR18_Msk (0x1U << EXTI_RTSR_TR18_Pos) /*!< 0x00040000 */ 02812 #define EXTI_RTSR_TR18 EXTI_RTSR_TR18_Msk /*!< Rising trigger event configuration bit of line 18 */ 02813 #define EXTI_RTSR_TR19_Pos (19U) 02814 #define EXTI_RTSR_TR19_Msk (0x1U << EXTI_RTSR_TR19_Pos) /*!< 0x00080000 */ 02815 #define EXTI_RTSR_TR19 EXTI_RTSR_TR19_Msk /*!< Rising trigger event configuration bit of line 19 */ 02816 02817 /* References Defines */ 02818 #define EXTI_RTSR_RT0 EXTI_RTSR_TR0 02819 #define EXTI_RTSR_RT1 EXTI_RTSR_TR1 02820 #define EXTI_RTSR_RT2 EXTI_RTSR_TR2 02821 #define EXTI_RTSR_RT3 EXTI_RTSR_TR3 02822 #define EXTI_RTSR_RT4 EXTI_RTSR_TR4 02823 #define EXTI_RTSR_RT5 EXTI_RTSR_TR5 02824 #define EXTI_RTSR_RT6 EXTI_RTSR_TR6 02825 #define EXTI_RTSR_RT7 EXTI_RTSR_TR7 02826 #define EXTI_RTSR_RT8 EXTI_RTSR_TR8 02827 #define EXTI_RTSR_RT9 EXTI_RTSR_TR9 02828 #define EXTI_RTSR_RT10 EXTI_RTSR_TR10 02829 #define EXTI_RTSR_RT11 EXTI_RTSR_TR11 02830 #define EXTI_RTSR_RT12 EXTI_RTSR_TR12 02831 #define EXTI_RTSR_RT13 EXTI_RTSR_TR13 02832 #define EXTI_RTSR_RT14 EXTI_RTSR_TR14 02833 #define EXTI_RTSR_RT15 EXTI_RTSR_TR15 02834 #define EXTI_RTSR_RT16 EXTI_RTSR_TR16 02835 #define EXTI_RTSR_RT17 EXTI_RTSR_TR17 02836 #define EXTI_RTSR_RT18 EXTI_RTSR_TR18 02837 #define EXTI_RTSR_RT19 EXTI_RTSR_TR19 02838 02839 /****************** Bit definition for EXTI_FTSR register *******************/ 02840 #define EXTI_FTSR_TR0_Pos (0U) 02841 #define EXTI_FTSR_TR0_Msk (0x1U << EXTI_FTSR_TR0_Pos) /*!< 0x00000001 */ 02842 #define EXTI_FTSR_TR0 EXTI_FTSR_TR0_Msk /*!< Falling trigger event configuration bit of line 0 */ 02843 #define EXTI_FTSR_TR1_Pos (1U) 02844 #define EXTI_FTSR_TR1_Msk (0x1U << EXTI_FTSR_TR1_Pos) /*!< 0x00000002 */ 02845 #define EXTI_FTSR_TR1 EXTI_FTSR_TR1_Msk /*!< Falling trigger event configuration bit of line 1 */ 02846 #define EXTI_FTSR_TR2_Pos (2U) 02847 #define EXTI_FTSR_TR2_Msk (0x1U << EXTI_FTSR_TR2_Pos) /*!< 0x00000004 */ 02848 #define EXTI_FTSR_TR2 EXTI_FTSR_TR2_Msk /*!< Falling trigger event configuration bit of line 2 */ 02849 #define EXTI_FTSR_TR3_Pos (3U) 02850 #define EXTI_FTSR_TR3_Msk (0x1U << EXTI_FTSR_TR3_Pos) /*!< 0x00000008 */ 02851 #define EXTI_FTSR_TR3 EXTI_FTSR_TR3_Msk /*!< Falling trigger event configuration bit of line 3 */ 02852 #define EXTI_FTSR_TR4_Pos (4U) 02853 #define EXTI_FTSR_TR4_Msk (0x1U << EXTI_FTSR_TR4_Pos) /*!< 0x00000010 */ 02854 #define EXTI_FTSR_TR4 EXTI_FTSR_TR4_Msk /*!< Falling trigger event configuration bit of line 4 */ 02855 #define EXTI_FTSR_TR5_Pos (5U) 02856 #define EXTI_FTSR_TR5_Msk (0x1U << EXTI_FTSR_TR5_Pos) /*!< 0x00000020 */ 02857 #define EXTI_FTSR_TR5 EXTI_FTSR_TR5_Msk /*!< Falling trigger event configuration bit of line 5 */ 02858 #define EXTI_FTSR_TR6_Pos (6U) 02859 #define EXTI_FTSR_TR6_Msk (0x1U << EXTI_FTSR_TR6_Pos) /*!< 0x00000040 */ 02860 #define EXTI_FTSR_TR6 EXTI_FTSR_TR6_Msk /*!< Falling trigger event configuration bit of line 6 */ 02861 #define EXTI_FTSR_TR7_Pos (7U) 02862 #define EXTI_FTSR_TR7_Msk (0x1U << EXTI_FTSR_TR7_Pos) /*!< 0x00000080 */ 02863 #define EXTI_FTSR_TR7 EXTI_FTSR_TR7_Msk /*!< Falling trigger event configuration bit of line 7 */ 02864 #define EXTI_FTSR_TR8_Pos (8U) 02865 #define EXTI_FTSR_TR8_Msk (0x1U << EXTI_FTSR_TR8_Pos) /*!< 0x00000100 */ 02866 #define EXTI_FTSR_TR8 EXTI_FTSR_TR8_Msk /*!< Falling trigger event configuration bit of line 8 */ 02867 #define EXTI_FTSR_TR9_Pos (9U) 02868 #define EXTI_FTSR_TR9_Msk (0x1U << EXTI_FTSR_TR9_Pos) /*!< 0x00000200 */ 02869 #define EXTI_FTSR_TR9 EXTI_FTSR_TR9_Msk /*!< Falling trigger event configuration bit of line 9 */ 02870 #define EXTI_FTSR_TR10_Pos (10U) 02871 #define EXTI_FTSR_TR10_Msk (0x1U << EXTI_FTSR_TR10_Pos) /*!< 0x00000400 */ 02872 #define EXTI_FTSR_TR10 EXTI_FTSR_TR10_Msk /*!< Falling trigger event configuration bit of line 10 */ 02873 #define EXTI_FTSR_TR11_Pos (11U) 02874 #define EXTI_FTSR_TR11_Msk (0x1U << EXTI_FTSR_TR11_Pos) /*!< 0x00000800 */ 02875 #define EXTI_FTSR_TR11 EXTI_FTSR_TR11_Msk /*!< Falling trigger event configuration bit of line 11 */ 02876 #define EXTI_FTSR_TR12_Pos (12U) 02877 #define EXTI_FTSR_TR12_Msk (0x1U << EXTI_FTSR_TR12_Pos) /*!< 0x00001000 */ 02878 #define EXTI_FTSR_TR12 EXTI_FTSR_TR12_Msk /*!< Falling trigger event configuration bit of line 12 */ 02879 #define EXTI_FTSR_TR13_Pos (13U) 02880 #define EXTI_FTSR_TR13_Msk (0x1U << EXTI_FTSR_TR13_Pos) /*!< 0x00002000 */ 02881 #define EXTI_FTSR_TR13 EXTI_FTSR_TR13_Msk /*!< Falling trigger event configuration bit of line 13 */ 02882 #define EXTI_FTSR_TR14_Pos (14U) 02883 #define EXTI_FTSR_TR14_Msk (0x1U << EXTI_FTSR_TR14_Pos) /*!< 0x00004000 */ 02884 #define EXTI_FTSR_TR14 EXTI_FTSR_TR14_Msk /*!< Falling trigger event configuration bit of line 14 */ 02885 #define EXTI_FTSR_TR15_Pos (15U) 02886 #define EXTI_FTSR_TR15_Msk (0x1U << EXTI_FTSR_TR15_Pos) /*!< 0x00008000 */ 02887 #define EXTI_FTSR_TR15 EXTI_FTSR_TR15_Msk /*!< Falling trigger event configuration bit of line 15 */ 02888 #define EXTI_FTSR_TR16_Pos (16U) 02889 #define EXTI_FTSR_TR16_Msk (0x1U << EXTI_FTSR_TR16_Pos) /*!< 0x00010000 */ 02890 #define EXTI_FTSR_TR16 EXTI_FTSR_TR16_Msk /*!< Falling trigger event configuration bit of line 16 */ 02891 #define EXTI_FTSR_TR17_Pos (17U) 02892 #define EXTI_FTSR_TR17_Msk (0x1U << EXTI_FTSR_TR17_Pos) /*!< 0x00020000 */ 02893 #define EXTI_FTSR_TR17 EXTI_FTSR_TR17_Msk /*!< Falling trigger event configuration bit of line 17 */ 02894 #define EXTI_FTSR_TR18_Pos (18U) 02895 #define EXTI_FTSR_TR18_Msk (0x1U << EXTI_FTSR_TR18_Pos) /*!< 0x00040000 */ 02896 #define EXTI_FTSR_TR18 EXTI_FTSR_TR18_Msk /*!< Falling trigger event configuration bit of line 18 */ 02897 #define EXTI_FTSR_TR19_Pos (19U) 02898 #define EXTI_FTSR_TR19_Msk (0x1U << EXTI_FTSR_TR19_Pos) /*!< 0x00080000 */ 02899 #define EXTI_FTSR_TR19 EXTI_FTSR_TR19_Msk /*!< Falling trigger event configuration bit of line 19 */ 02900 02901 /* References Defines */ 02902 #define EXTI_FTSR_FT0 EXTI_FTSR_TR0 02903 #define EXTI_FTSR_FT1 EXTI_FTSR_TR1 02904 #define EXTI_FTSR_FT2 EXTI_FTSR_TR2 02905 #define EXTI_FTSR_FT3 EXTI_FTSR_TR3 02906 #define EXTI_FTSR_FT4 EXTI_FTSR_TR4 02907 #define EXTI_FTSR_FT5 EXTI_FTSR_TR5 02908 #define EXTI_FTSR_FT6 EXTI_FTSR_TR6 02909 #define EXTI_FTSR_FT7 EXTI_FTSR_TR7 02910 #define EXTI_FTSR_FT8 EXTI_FTSR_TR8 02911 #define EXTI_FTSR_FT9 EXTI_FTSR_TR9 02912 #define EXTI_FTSR_FT10 EXTI_FTSR_TR10 02913 #define EXTI_FTSR_FT11 EXTI_FTSR_TR11 02914 #define EXTI_FTSR_FT12 EXTI_FTSR_TR12 02915 #define EXTI_FTSR_FT13 EXTI_FTSR_TR13 02916 #define EXTI_FTSR_FT14 EXTI_FTSR_TR14 02917 #define EXTI_FTSR_FT15 EXTI_FTSR_TR15 02918 #define EXTI_FTSR_FT16 EXTI_FTSR_TR16 02919 #define EXTI_FTSR_FT17 EXTI_FTSR_TR17 02920 #define EXTI_FTSR_FT18 EXTI_FTSR_TR18 02921 #define EXTI_FTSR_FT19 EXTI_FTSR_TR19 02922 02923 /****************** Bit definition for EXTI_SWIER register ******************/ 02924 #define EXTI_SWIER_SWIER0_Pos (0U) 02925 #define EXTI_SWIER_SWIER0_Msk (0x1U << EXTI_SWIER_SWIER0_Pos) /*!< 0x00000001 */ 02926 #define EXTI_SWIER_SWIER0 EXTI_SWIER_SWIER0_Msk /*!< Software Interrupt on line 0 */ 02927 #define EXTI_SWIER_SWIER1_Pos (1U) 02928 #define EXTI_SWIER_SWIER1_Msk (0x1U << EXTI_SWIER_SWIER1_Pos) /*!< 0x00000002 */ 02929 #define EXTI_SWIER_SWIER1 EXTI_SWIER_SWIER1_Msk /*!< Software Interrupt on line 1 */ 02930 #define EXTI_SWIER_SWIER2_Pos (2U) 02931 #define EXTI_SWIER_SWIER2_Msk (0x1U << EXTI_SWIER_SWIER2_Pos) /*!< 0x00000004 */ 02932 #define EXTI_SWIER_SWIER2 EXTI_SWIER_SWIER2_Msk /*!< Software Interrupt on line 2 */ 02933 #define EXTI_SWIER_SWIER3_Pos (3U) 02934 #define EXTI_SWIER_SWIER3_Msk (0x1U << EXTI_SWIER_SWIER3_Pos) /*!< 0x00000008 */ 02935 #define EXTI_SWIER_SWIER3 EXTI_SWIER_SWIER3_Msk /*!< Software Interrupt on line 3 */ 02936 #define EXTI_SWIER_SWIER4_Pos (4U) 02937 #define EXTI_SWIER_SWIER4_Msk (0x1U << EXTI_SWIER_SWIER4_Pos) /*!< 0x00000010 */ 02938 #define EXTI_SWIER_SWIER4 EXTI_SWIER_SWIER4_Msk /*!< Software Interrupt on line 4 */ 02939 #define EXTI_SWIER_SWIER5_Pos (5U) 02940 #define EXTI_SWIER_SWIER5_Msk (0x1U << EXTI_SWIER_SWIER5_Pos) /*!< 0x00000020 */ 02941 #define EXTI_SWIER_SWIER5 EXTI_SWIER_SWIER5_Msk /*!< Software Interrupt on line 5 */ 02942 #define EXTI_SWIER_SWIER6_Pos (6U) 02943 #define EXTI_SWIER_SWIER6_Msk (0x1U << EXTI_SWIER_SWIER6_Pos) /*!< 0x00000040 */ 02944 #define EXTI_SWIER_SWIER6 EXTI_SWIER_SWIER6_Msk /*!< Software Interrupt on line 6 */ 02945 #define EXTI_SWIER_SWIER7_Pos (7U) 02946 #define EXTI_SWIER_SWIER7_Msk (0x1U << EXTI_SWIER_SWIER7_Pos) /*!< 0x00000080 */ 02947 #define EXTI_SWIER_SWIER7 EXTI_SWIER_SWIER7_Msk /*!< Software Interrupt on line 7 */ 02948 #define EXTI_SWIER_SWIER8_Pos (8U) 02949 #define EXTI_SWIER_SWIER8_Msk (0x1U << EXTI_SWIER_SWIER8_Pos) /*!< 0x00000100 */ 02950 #define EXTI_SWIER_SWIER8 EXTI_SWIER_SWIER8_Msk /*!< Software Interrupt on line 8 */ 02951 #define EXTI_SWIER_SWIER9_Pos (9U) 02952 #define EXTI_SWIER_SWIER9_Msk (0x1U << EXTI_SWIER_SWIER9_Pos) /*!< 0x00000200 */ 02953 #define EXTI_SWIER_SWIER9 EXTI_SWIER_SWIER9_Msk /*!< Software Interrupt on line 9 */ 02954 #define EXTI_SWIER_SWIER10_Pos (10U) 02955 #define EXTI_SWIER_SWIER10_Msk (0x1U << EXTI_SWIER_SWIER10_Pos) /*!< 0x00000400 */ 02956 #define EXTI_SWIER_SWIER10 EXTI_SWIER_SWIER10_Msk /*!< Software Interrupt on line 10 */ 02957 #define EXTI_SWIER_SWIER11_Pos (11U) 02958 #define EXTI_SWIER_SWIER11_Msk (0x1U << EXTI_SWIER_SWIER11_Pos) /*!< 0x00000800 */ 02959 #define EXTI_SWIER_SWIER11 EXTI_SWIER_SWIER11_Msk /*!< Software Interrupt on line 11 */ 02960 #define EXTI_SWIER_SWIER12_Pos (12U) 02961 #define EXTI_SWIER_SWIER12_Msk (0x1U << EXTI_SWIER_SWIER12_Pos) /*!< 0x00001000 */ 02962 #define EXTI_SWIER_SWIER12 EXTI_SWIER_SWIER12_Msk /*!< Software Interrupt on line 12 */ 02963 #define EXTI_SWIER_SWIER13_Pos (13U) 02964 #define EXTI_SWIER_SWIER13_Msk (0x1U << EXTI_SWIER_SWIER13_Pos) /*!< 0x00002000 */ 02965 #define EXTI_SWIER_SWIER13 EXTI_SWIER_SWIER13_Msk /*!< Software Interrupt on line 13 */ 02966 #define EXTI_SWIER_SWIER14_Pos (14U) 02967 #define EXTI_SWIER_SWIER14_Msk (0x1U << EXTI_SWIER_SWIER14_Pos) /*!< 0x00004000 */ 02968 #define EXTI_SWIER_SWIER14 EXTI_SWIER_SWIER14_Msk /*!< Software Interrupt on line 14 */ 02969 #define EXTI_SWIER_SWIER15_Pos (15U) 02970 #define EXTI_SWIER_SWIER15_Msk (0x1U << EXTI_SWIER_SWIER15_Pos) /*!< 0x00008000 */ 02971 #define EXTI_SWIER_SWIER15 EXTI_SWIER_SWIER15_Msk /*!< Software Interrupt on line 15 */ 02972 #define EXTI_SWIER_SWIER16_Pos (16U) 02973 #define EXTI_SWIER_SWIER16_Msk (0x1U << EXTI_SWIER_SWIER16_Pos) /*!< 0x00010000 */ 02974 #define EXTI_SWIER_SWIER16 EXTI_SWIER_SWIER16_Msk /*!< Software Interrupt on line 16 */ 02975 #define EXTI_SWIER_SWIER17_Pos (17U) 02976 #define EXTI_SWIER_SWIER17_Msk (0x1U << EXTI_SWIER_SWIER17_Pos) /*!< 0x00020000 */ 02977 #define EXTI_SWIER_SWIER17 EXTI_SWIER_SWIER17_Msk /*!< Software Interrupt on line 17 */ 02978 #define EXTI_SWIER_SWIER18_Pos (18U) 02979 #define EXTI_SWIER_SWIER18_Msk (0x1U << EXTI_SWIER_SWIER18_Pos) /*!< 0x00040000 */ 02980 #define EXTI_SWIER_SWIER18 EXTI_SWIER_SWIER18_Msk /*!< Software Interrupt on line 18 */ 02981 #define EXTI_SWIER_SWIER19_Pos (19U) 02982 #define EXTI_SWIER_SWIER19_Msk (0x1U << EXTI_SWIER_SWIER19_Pos) /*!< 0x00080000 */ 02983 #define EXTI_SWIER_SWIER19 EXTI_SWIER_SWIER19_Msk /*!< Software Interrupt on line 19 */ 02984 02985 /* References Defines */ 02986 #define EXTI_SWIER_SWI0 EXTI_SWIER_SWIER0 02987 #define EXTI_SWIER_SWI1 EXTI_SWIER_SWIER1 02988 #define EXTI_SWIER_SWI2 EXTI_SWIER_SWIER2 02989 #define EXTI_SWIER_SWI3 EXTI_SWIER_SWIER3 02990 #define EXTI_SWIER_SWI4 EXTI_SWIER_SWIER4 02991 #define EXTI_SWIER_SWI5 EXTI_SWIER_SWIER5 02992 #define EXTI_SWIER_SWI6 EXTI_SWIER_SWIER6 02993 #define EXTI_SWIER_SWI7 EXTI_SWIER_SWIER7 02994 #define EXTI_SWIER_SWI8 EXTI_SWIER_SWIER8 02995 #define EXTI_SWIER_SWI9 EXTI_SWIER_SWIER9 02996 #define EXTI_SWIER_SWI10 EXTI_SWIER_SWIER10 02997 #define EXTI_SWIER_SWI11 EXTI_SWIER_SWIER11 02998 #define EXTI_SWIER_SWI12 EXTI_SWIER_SWIER12 02999 #define EXTI_SWIER_SWI13 EXTI_SWIER_SWIER13 03000 #define EXTI_SWIER_SWI14 EXTI_SWIER_SWIER14 03001 #define EXTI_SWIER_SWI15 EXTI_SWIER_SWIER15 03002 #define EXTI_SWIER_SWI16 EXTI_SWIER_SWIER16 03003 #define EXTI_SWIER_SWI17 EXTI_SWIER_SWIER17 03004 #define EXTI_SWIER_SWI18 EXTI_SWIER_SWIER18 03005 #define EXTI_SWIER_SWI19 EXTI_SWIER_SWIER19 03006 03007 /******************* Bit definition for EXTI_PR register ********************/ 03008 #define EXTI_PR_PR0_Pos (0U) 03009 #define EXTI_PR_PR0_Msk (0x1U << EXTI_PR_PR0_Pos) /*!< 0x00000001 */ 03010 #define EXTI_PR_PR0 EXTI_PR_PR0_Msk /*!< Pending bit for line 0 */ 03011 #define EXTI_PR_PR1_Pos (1U) 03012 #define EXTI_PR_PR1_Msk (0x1U << EXTI_PR_PR1_Pos) /*!< 0x00000002 */ 03013 #define EXTI_PR_PR1 EXTI_PR_PR1_Msk /*!< Pending bit for line 1 */ 03014 #define EXTI_PR_PR2_Pos (2U) 03015 #define EXTI_PR_PR2_Msk (0x1U << EXTI_PR_PR2_Pos) /*!< 0x00000004 */ 03016 #define EXTI_PR_PR2 EXTI_PR_PR2_Msk /*!< Pending bit for line 2 */ 03017 #define EXTI_PR_PR3_Pos (3U) 03018 #define EXTI_PR_PR3_Msk (0x1U << EXTI_PR_PR3_Pos) /*!< 0x00000008 */ 03019 #define EXTI_PR_PR3 EXTI_PR_PR3_Msk /*!< Pending bit for line 3 */ 03020 #define EXTI_PR_PR4_Pos (4U) 03021 #define EXTI_PR_PR4_Msk (0x1U << EXTI_PR_PR4_Pos) /*!< 0x00000010 */ 03022 #define EXTI_PR_PR4 EXTI_PR_PR4_Msk /*!< Pending bit for line 4 */ 03023 #define EXTI_PR_PR5_Pos (5U) 03024 #define EXTI_PR_PR5_Msk (0x1U << EXTI_PR_PR5_Pos) /*!< 0x00000020 */ 03025 #define EXTI_PR_PR5 EXTI_PR_PR5_Msk /*!< Pending bit for line 5 */ 03026 #define EXTI_PR_PR6_Pos (6U) 03027 #define EXTI_PR_PR6_Msk (0x1U << EXTI_PR_PR6_Pos) /*!< 0x00000040 */ 03028 #define EXTI_PR_PR6 EXTI_PR_PR6_Msk /*!< Pending bit for line 6 */ 03029 #define EXTI_PR_PR7_Pos (7U) 03030 #define EXTI_PR_PR7_Msk (0x1U << EXTI_PR_PR7_Pos) /*!< 0x00000080 */ 03031 #define EXTI_PR_PR7 EXTI_PR_PR7_Msk /*!< Pending bit for line 7 */ 03032 #define EXTI_PR_PR8_Pos (8U) 03033 #define EXTI_PR_PR8_Msk (0x1U << EXTI_PR_PR8_Pos) /*!< 0x00000100 */ 03034 #define EXTI_PR_PR8 EXTI_PR_PR8_Msk /*!< Pending bit for line 8 */ 03035 #define EXTI_PR_PR9_Pos (9U) 03036 #define EXTI_PR_PR9_Msk (0x1U << EXTI_PR_PR9_Pos) /*!< 0x00000200 */ 03037 #define EXTI_PR_PR9 EXTI_PR_PR9_Msk /*!< Pending bit for line 9 */ 03038 #define EXTI_PR_PR10_Pos (10U) 03039 #define EXTI_PR_PR10_Msk (0x1U << EXTI_PR_PR10_Pos) /*!< 0x00000400 */ 03040 #define EXTI_PR_PR10 EXTI_PR_PR10_Msk /*!< Pending bit for line 10 */ 03041 #define EXTI_PR_PR11_Pos (11U) 03042 #define EXTI_PR_PR11_Msk (0x1U << EXTI_PR_PR11_Pos) /*!< 0x00000800 */ 03043 #define EXTI_PR_PR11 EXTI_PR_PR11_Msk /*!< Pending bit for line 11 */ 03044 #define EXTI_PR_PR12_Pos (12U) 03045 #define EXTI_PR_PR12_Msk (0x1U << EXTI_PR_PR12_Pos) /*!< 0x00001000 */ 03046 #define EXTI_PR_PR12 EXTI_PR_PR12_Msk /*!< Pending bit for line 12 */ 03047 #define EXTI_PR_PR13_Pos (13U) 03048 #define EXTI_PR_PR13_Msk (0x1U << EXTI_PR_PR13_Pos) /*!< 0x00002000 */ 03049 #define EXTI_PR_PR13 EXTI_PR_PR13_Msk /*!< Pending bit for line 13 */ 03050 #define EXTI_PR_PR14_Pos (14U) 03051 #define EXTI_PR_PR14_Msk (0x1U << EXTI_PR_PR14_Pos) /*!< 0x00004000 */ 03052 #define EXTI_PR_PR14 EXTI_PR_PR14_Msk /*!< Pending bit for line 14 */ 03053 #define EXTI_PR_PR15_Pos (15U) 03054 #define EXTI_PR_PR15_Msk (0x1U << EXTI_PR_PR15_Pos) /*!< 0x00008000 */ 03055 #define EXTI_PR_PR15 EXTI_PR_PR15_Msk /*!< Pending bit for line 15 */ 03056 #define EXTI_PR_PR16_Pos (16U) 03057 #define EXTI_PR_PR16_Msk (0x1U << EXTI_PR_PR16_Pos) /*!< 0x00010000 */ 03058 #define EXTI_PR_PR16 EXTI_PR_PR16_Msk /*!< Pending bit for line 16 */ 03059 #define EXTI_PR_PR17_Pos (17U) 03060 #define EXTI_PR_PR17_Msk (0x1U << EXTI_PR_PR17_Pos) /*!< 0x00020000 */ 03061 #define EXTI_PR_PR17 EXTI_PR_PR17_Msk /*!< Pending bit for line 17 */ 03062 #define EXTI_PR_PR18_Pos (18U) 03063 #define EXTI_PR_PR18_Msk (0x1U << EXTI_PR_PR18_Pos) /*!< 0x00040000 */ 03064 #define EXTI_PR_PR18 EXTI_PR_PR18_Msk /*!< Pending bit for line 18 */ 03065 #define EXTI_PR_PR19_Pos (19U) 03066 #define EXTI_PR_PR19_Msk (0x1U << EXTI_PR_PR19_Pos) /*!< 0x00080000 */ 03067 #define EXTI_PR_PR19 EXTI_PR_PR19_Msk /*!< Pending bit for line 19 */ 03068 03069 /* References Defines */ 03070 #define EXTI_PR_PIF0 EXTI_PR_PR0 03071 #define EXTI_PR_PIF1 EXTI_PR_PR1 03072 #define EXTI_PR_PIF2 EXTI_PR_PR2 03073 #define EXTI_PR_PIF3 EXTI_PR_PR3 03074 #define EXTI_PR_PIF4 EXTI_PR_PR4 03075 #define EXTI_PR_PIF5 EXTI_PR_PR5 03076 #define EXTI_PR_PIF6 EXTI_PR_PR6 03077 #define EXTI_PR_PIF7 EXTI_PR_PR7 03078 #define EXTI_PR_PIF8 EXTI_PR_PR8 03079 #define EXTI_PR_PIF9 EXTI_PR_PR9 03080 #define EXTI_PR_PIF10 EXTI_PR_PR10 03081 #define EXTI_PR_PIF11 EXTI_PR_PR11 03082 #define EXTI_PR_PIF12 EXTI_PR_PR12 03083 #define EXTI_PR_PIF13 EXTI_PR_PR13 03084 #define EXTI_PR_PIF14 EXTI_PR_PR14 03085 #define EXTI_PR_PIF15 EXTI_PR_PR15 03086 #define EXTI_PR_PIF16 EXTI_PR_PR16 03087 #define EXTI_PR_PIF17 EXTI_PR_PR17 03088 #define EXTI_PR_PIF18 EXTI_PR_PR18 03089 #define EXTI_PR_PIF19 EXTI_PR_PR19 03090 03091 /******************************************************************************/ 03092 /* */ 03093 /* DMA Controller */ 03094 /* */ 03095 /******************************************************************************/ 03096 03097 /******************* Bit definition for DMA_ISR register ********************/ 03098 #define DMA_ISR_GIF1_Pos (0U) 03099 #define DMA_ISR_GIF1_Msk (0x1U << DMA_ISR_GIF1_Pos) /*!< 0x00000001 */ 03100 #define DMA_ISR_GIF1 DMA_ISR_GIF1_Msk /*!< Channel 1 Global interrupt flag */ 03101 #define DMA_ISR_TCIF1_Pos (1U) 03102 #define DMA_ISR_TCIF1_Msk (0x1U << DMA_ISR_TCIF1_Pos) /*!< 0x00000002 */ 03103 #define DMA_ISR_TCIF1 DMA_ISR_TCIF1_Msk /*!< Channel 1 Transfer Complete flag */ 03104 #define DMA_ISR_HTIF1_Pos (2U) 03105 #define DMA_ISR_HTIF1_Msk (0x1U << DMA_ISR_HTIF1_Pos) /*!< 0x00000004 */ 03106 #define DMA_ISR_HTIF1 DMA_ISR_HTIF1_Msk /*!< Channel 1 Half Transfer flag */ 03107 #define DMA_ISR_TEIF1_Pos (3U) 03108 #define DMA_ISR_TEIF1_Msk (0x1U << DMA_ISR_TEIF1_Pos) /*!< 0x00000008 */ 03109 #define DMA_ISR_TEIF1 DMA_ISR_TEIF1_Msk /*!< Channel 1 Transfer Error flag */ 03110 #define DMA_ISR_GIF2_Pos (4U) 03111 #define DMA_ISR_GIF2_Msk (0x1U << DMA_ISR_GIF2_Pos) /*!< 0x00000010 */ 03112 #define DMA_ISR_GIF2 DMA_ISR_GIF2_Msk /*!< Channel 2 Global interrupt flag */ 03113 #define DMA_ISR_TCIF2_Pos (5U) 03114 #define DMA_ISR_TCIF2_Msk (0x1U << DMA_ISR_TCIF2_Pos) /*!< 0x00000020 */ 03115 #define DMA_ISR_TCIF2 DMA_ISR_TCIF2_Msk /*!< Channel 2 Transfer Complete flag */ 03116 #define DMA_ISR_HTIF2_Pos (6U) 03117 #define DMA_ISR_HTIF2_Msk (0x1U << DMA_ISR_HTIF2_Pos) /*!< 0x00000040 */ 03118 #define DMA_ISR_HTIF2 DMA_ISR_HTIF2_Msk /*!< Channel 2 Half Transfer flag */ 03119 #define DMA_ISR_TEIF2_Pos (7U) 03120 #define DMA_ISR_TEIF2_Msk (0x1U << DMA_ISR_TEIF2_Pos) /*!< 0x00000080 */ 03121 #define DMA_ISR_TEIF2 DMA_ISR_TEIF2_Msk /*!< Channel 2 Transfer Error flag */ 03122 #define DMA_ISR_GIF3_Pos (8U) 03123 #define DMA_ISR_GIF3_Msk (0x1U << DMA_ISR_GIF3_Pos) /*!< 0x00000100 */ 03124 #define DMA_ISR_GIF3 DMA_ISR_GIF3_Msk /*!< Channel 3 Global interrupt flag */ 03125 #define DMA_ISR_TCIF3_Pos (9U) 03126 #define DMA_ISR_TCIF3_Msk (0x1U << DMA_ISR_TCIF3_Pos) /*!< 0x00000200 */ 03127 #define DMA_ISR_TCIF3 DMA_ISR_TCIF3_Msk /*!< Channel 3 Transfer Complete flag */ 03128 #define DMA_ISR_HTIF3_Pos (10U) 03129 #define DMA_ISR_HTIF3_Msk (0x1U << DMA_ISR_HTIF3_Pos) /*!< 0x00000400 */ 03130 #define DMA_ISR_HTIF3 DMA_ISR_HTIF3_Msk /*!< Channel 3 Half Transfer flag */ 03131 #define DMA_ISR_TEIF3_Pos (11U) 03132 #define DMA_ISR_TEIF3_Msk (0x1U << DMA_ISR_TEIF3_Pos) /*!< 0x00000800 */ 03133 #define DMA_ISR_TEIF3 DMA_ISR_TEIF3_Msk /*!< Channel 3 Transfer Error flag */ 03134 #define DMA_ISR_GIF4_Pos (12U) 03135 #define DMA_ISR_GIF4_Msk (0x1U << DMA_ISR_GIF4_Pos) /*!< 0x00001000 */ 03136 #define DMA_ISR_GIF4 DMA_ISR_GIF4_Msk /*!< Channel 4 Global interrupt flag */ 03137 #define DMA_ISR_TCIF4_Pos (13U) 03138 #define DMA_ISR_TCIF4_Msk (0x1U << DMA_ISR_TCIF4_Pos) /*!< 0x00002000 */ 03139 #define DMA_ISR_TCIF4 DMA_ISR_TCIF4_Msk /*!< Channel 4 Transfer Complete flag */ 03140 #define DMA_ISR_HTIF4_Pos (14U) 03141 #define DMA_ISR_HTIF4_Msk (0x1U << DMA_ISR_HTIF4_Pos) /*!< 0x00004000 */ 03142 #define DMA_ISR_HTIF4 DMA_ISR_HTIF4_Msk /*!< Channel 4 Half Transfer flag */ 03143 #define DMA_ISR_TEIF4_Pos (15U) 03144 #define DMA_ISR_TEIF4_Msk (0x1U << DMA_ISR_TEIF4_Pos) /*!< 0x00008000 */ 03145 #define DMA_ISR_TEIF4 DMA_ISR_TEIF4_Msk /*!< Channel 4 Transfer Error flag */ 03146 #define DMA_ISR_GIF5_Pos (16U) 03147 #define DMA_ISR_GIF5_Msk (0x1U << DMA_ISR_GIF5_Pos) /*!< 0x00010000 */ 03148 #define DMA_ISR_GIF5 DMA_ISR_GIF5_Msk /*!< Channel 5 Global interrupt flag */ 03149 #define DMA_ISR_TCIF5_Pos (17U) 03150 #define DMA_ISR_TCIF5_Msk (0x1U << DMA_ISR_TCIF5_Pos) /*!< 0x00020000 */ 03151 #define DMA_ISR_TCIF5 DMA_ISR_TCIF5_Msk /*!< Channel 5 Transfer Complete flag */ 03152 #define DMA_ISR_HTIF5_Pos (18U) 03153 #define DMA_ISR_HTIF5_Msk (0x1U << DMA_ISR_HTIF5_Pos) /*!< 0x00040000 */ 03154 #define DMA_ISR_HTIF5 DMA_ISR_HTIF5_Msk /*!< Channel 5 Half Transfer flag */ 03155 #define DMA_ISR_TEIF5_Pos (19U) 03156 #define DMA_ISR_TEIF5_Msk (0x1U << DMA_ISR_TEIF5_Pos) /*!< 0x00080000 */ 03157 #define DMA_ISR_TEIF5 DMA_ISR_TEIF5_Msk /*!< Channel 5 Transfer Error flag */ 03158 #define DMA_ISR_GIF6_Pos (20U) 03159 #define DMA_ISR_GIF6_Msk (0x1U << DMA_ISR_GIF6_Pos) /*!< 0x00100000 */ 03160 #define DMA_ISR_GIF6 DMA_ISR_GIF6_Msk /*!< Channel 6 Global interrupt flag */ 03161 #define DMA_ISR_TCIF6_Pos (21U) 03162 #define DMA_ISR_TCIF6_Msk (0x1U << DMA_ISR_TCIF6_Pos) /*!< 0x00200000 */ 03163 #define DMA_ISR_TCIF6 DMA_ISR_TCIF6_Msk /*!< Channel 6 Transfer Complete flag */ 03164 #define DMA_ISR_HTIF6_Pos (22U) 03165 #define DMA_ISR_HTIF6_Msk (0x1U << DMA_ISR_HTIF6_Pos) /*!< 0x00400000 */ 03166 #define DMA_ISR_HTIF6 DMA_ISR_HTIF6_Msk /*!< Channel 6 Half Transfer flag */ 03167 #define DMA_ISR_TEIF6_Pos (23U) 03168 #define DMA_ISR_TEIF6_Msk (0x1U << DMA_ISR_TEIF6_Pos) /*!< 0x00800000 */ 03169 #define DMA_ISR_TEIF6 DMA_ISR_TEIF6_Msk /*!< Channel 6 Transfer Error flag */ 03170 #define DMA_ISR_GIF7_Pos (24U) 03171 #define DMA_ISR_GIF7_Msk (0x1U << DMA_ISR_GIF7_Pos) /*!< 0x01000000 */ 03172 #define DMA_ISR_GIF7 DMA_ISR_GIF7_Msk /*!< Channel 7 Global interrupt flag */ 03173 #define DMA_ISR_TCIF7_Pos (25U) 03174 #define DMA_ISR_TCIF7_Msk (0x1U << DMA_ISR_TCIF7_Pos) /*!< 0x02000000 */ 03175 #define DMA_ISR_TCIF7 DMA_ISR_TCIF7_Msk /*!< Channel 7 Transfer Complete flag */ 03176 #define DMA_ISR_HTIF7_Pos (26U) 03177 #define DMA_ISR_HTIF7_Msk (0x1U << DMA_ISR_HTIF7_Pos) /*!< 0x04000000 */ 03178 #define DMA_ISR_HTIF7 DMA_ISR_HTIF7_Msk /*!< Channel 7 Half Transfer flag */ 03179 #define DMA_ISR_TEIF7_Pos (27U) 03180 #define DMA_ISR_TEIF7_Msk (0x1U << DMA_ISR_TEIF7_Pos) /*!< 0x08000000 */ 03181 #define DMA_ISR_TEIF7 DMA_ISR_TEIF7_Msk /*!< Channel 7 Transfer Error flag */ 03182 03183 /******************* Bit definition for DMA_IFCR register *******************/ 03184 #define DMA_IFCR_CGIF1_Pos (0U) 03185 #define DMA_IFCR_CGIF1_Msk (0x1U << DMA_IFCR_CGIF1_Pos) /*!< 0x00000001 */ 03186 #define DMA_IFCR_CGIF1 DMA_IFCR_CGIF1_Msk /*!< Channel 1 Global interrupt clear */ 03187 #define DMA_IFCR_CTCIF1_Pos (1U) 03188 #define DMA_IFCR_CTCIF1_Msk (0x1U << DMA_IFCR_CTCIF1_Pos) /*!< 0x00000002 */ 03189 #define DMA_IFCR_CTCIF1 DMA_IFCR_CTCIF1_Msk /*!< Channel 1 Transfer Complete clear */ 03190 #define DMA_IFCR_CHTIF1_Pos (2U) 03191 #define DMA_IFCR_CHTIF1_Msk (0x1U << DMA_IFCR_CHTIF1_Pos) /*!< 0x00000004 */ 03192 #define DMA_IFCR_CHTIF1 DMA_IFCR_CHTIF1_Msk /*!< Channel 1 Half Transfer clear */ 03193 #define DMA_IFCR_CTEIF1_Pos (3U) 03194 #define DMA_IFCR_CTEIF1_Msk (0x1U << DMA_IFCR_CTEIF1_Pos) /*!< 0x00000008 */ 03195 #define DMA_IFCR_CTEIF1 DMA_IFCR_CTEIF1_Msk /*!< Channel 1 Transfer Error clear */ 03196 #define DMA_IFCR_CGIF2_Pos (4U) 03197 #define DMA_IFCR_CGIF2_Msk (0x1U << DMA_IFCR_CGIF2_Pos) /*!< 0x00000010 */ 03198 #define DMA_IFCR_CGIF2 DMA_IFCR_CGIF2_Msk /*!< Channel 2 Global interrupt clear */ 03199 #define DMA_IFCR_CTCIF2_Pos (5U) 03200 #define DMA_IFCR_CTCIF2_Msk (0x1U << DMA_IFCR_CTCIF2_Pos) /*!< 0x00000020 */ 03201 #define DMA_IFCR_CTCIF2 DMA_IFCR_CTCIF2_Msk /*!< Channel 2 Transfer Complete clear */ 03202 #define DMA_IFCR_CHTIF2_Pos (6U) 03203 #define DMA_IFCR_CHTIF2_Msk (0x1U << DMA_IFCR_CHTIF2_Pos) /*!< 0x00000040 */ 03204 #define DMA_IFCR_CHTIF2 DMA_IFCR_CHTIF2_Msk /*!< Channel 2 Half Transfer clear */ 03205 #define DMA_IFCR_CTEIF2_Pos (7U) 03206 #define DMA_IFCR_CTEIF2_Msk (0x1U << DMA_IFCR_CTEIF2_Pos) /*!< 0x00000080 */ 03207 #define DMA_IFCR_CTEIF2 DMA_IFCR_CTEIF2_Msk /*!< Channel 2 Transfer Error clear */ 03208 #define DMA_IFCR_CGIF3_Pos (8U) 03209 #define DMA_IFCR_CGIF3_Msk (0x1U << DMA_IFCR_CGIF3_Pos) /*!< 0x00000100 */ 03210 #define DMA_IFCR_CGIF3 DMA_IFCR_CGIF3_Msk /*!< Channel 3 Global interrupt clear */ 03211 #define DMA_IFCR_CTCIF3_Pos (9U) 03212 #define DMA_IFCR_CTCIF3_Msk (0x1U << DMA_IFCR_CTCIF3_Pos) /*!< 0x00000200 */ 03213 #define DMA_IFCR_CTCIF3 DMA_IFCR_CTCIF3_Msk /*!< Channel 3 Transfer Complete clear */ 03214 #define DMA_IFCR_CHTIF3_Pos (10U) 03215 #define DMA_IFCR_CHTIF3_Msk (0x1U << DMA_IFCR_CHTIF3_Pos) /*!< 0x00000400 */ 03216 #define DMA_IFCR_CHTIF3 DMA_IFCR_CHTIF3_Msk /*!< Channel 3 Half Transfer clear */ 03217 #define DMA_IFCR_CTEIF3_Pos (11U) 03218 #define DMA_IFCR_CTEIF3_Msk (0x1U << DMA_IFCR_CTEIF3_Pos) /*!< 0x00000800 */ 03219 #define DMA_IFCR_CTEIF3 DMA_IFCR_CTEIF3_Msk /*!< Channel 3 Transfer Error clear */ 03220 #define DMA_IFCR_CGIF4_Pos (12U) 03221 #define DMA_IFCR_CGIF4_Msk (0x1U << DMA_IFCR_CGIF4_Pos) /*!< 0x00001000 */ 03222 #define DMA_IFCR_CGIF4 DMA_IFCR_CGIF4_Msk /*!< Channel 4 Global interrupt clear */ 03223 #define DMA_IFCR_CTCIF4_Pos (13U) 03224 #define DMA_IFCR_CTCIF4_Msk (0x1U << DMA_IFCR_CTCIF4_Pos) /*!< 0x00002000 */ 03225 #define DMA_IFCR_CTCIF4 DMA_IFCR_CTCIF4_Msk /*!< Channel 4 Transfer Complete clear */ 03226 #define DMA_IFCR_CHTIF4_Pos (14U) 03227 #define DMA_IFCR_CHTIF4_Msk (0x1U << DMA_IFCR_CHTIF4_Pos) /*!< 0x00004000 */ 03228 #define DMA_IFCR_CHTIF4 DMA_IFCR_CHTIF4_Msk /*!< Channel 4 Half Transfer clear */ 03229 #define DMA_IFCR_CTEIF4_Pos (15U) 03230 #define DMA_IFCR_CTEIF4_Msk (0x1U << DMA_IFCR_CTEIF4_Pos) /*!< 0x00008000 */ 03231 #define DMA_IFCR_CTEIF4 DMA_IFCR_CTEIF4_Msk /*!< Channel 4 Transfer Error clear */ 03232 #define DMA_IFCR_CGIF5_Pos (16U) 03233 #define DMA_IFCR_CGIF5_Msk (0x1U << DMA_IFCR_CGIF5_Pos) /*!< 0x00010000 */ 03234 #define DMA_IFCR_CGIF5 DMA_IFCR_CGIF5_Msk /*!< Channel 5 Global interrupt clear */ 03235 #define DMA_IFCR_CTCIF5_Pos (17U) 03236 #define DMA_IFCR_CTCIF5_Msk (0x1U << DMA_IFCR_CTCIF5_Pos) /*!< 0x00020000 */ 03237 #define DMA_IFCR_CTCIF5 DMA_IFCR_CTCIF5_Msk /*!< Channel 5 Transfer Complete clear */ 03238 #define DMA_IFCR_CHTIF5_Pos (18U) 03239 #define DMA_IFCR_CHTIF5_Msk (0x1U << DMA_IFCR_CHTIF5_Pos) /*!< 0x00040000 */ 03240 #define DMA_IFCR_CHTIF5 DMA_IFCR_CHTIF5_Msk /*!< Channel 5 Half Transfer clear */ 03241 #define DMA_IFCR_CTEIF5_Pos (19U) 03242 #define DMA_IFCR_CTEIF5_Msk (0x1U << DMA_IFCR_CTEIF5_Pos) /*!< 0x00080000 */ 03243 #define DMA_IFCR_CTEIF5 DMA_IFCR_CTEIF5_Msk /*!< Channel 5 Transfer Error clear */ 03244 #define DMA_IFCR_CGIF6_Pos (20U) 03245 #define DMA_IFCR_CGIF6_Msk (0x1U << DMA_IFCR_CGIF6_Pos) /*!< 0x00100000 */ 03246 #define DMA_IFCR_CGIF6 DMA_IFCR_CGIF6_Msk /*!< Channel 6 Global interrupt clear */ 03247 #define DMA_IFCR_CTCIF6_Pos (21U) 03248 #define DMA_IFCR_CTCIF6_Msk (0x1U << DMA_IFCR_CTCIF6_Pos) /*!< 0x00200000 */ 03249 #define DMA_IFCR_CTCIF6 DMA_IFCR_CTCIF6_Msk /*!< Channel 6 Transfer Complete clear */ 03250 #define DMA_IFCR_CHTIF6_Pos (22U) 03251 #define DMA_IFCR_CHTIF6_Msk (0x1U << DMA_IFCR_CHTIF6_Pos) /*!< 0x00400000 */ 03252 #define DMA_IFCR_CHTIF6 DMA_IFCR_CHTIF6_Msk /*!< Channel 6 Half Transfer clear */ 03253 #define DMA_IFCR_CTEIF6_Pos (23U) 03254 #define DMA_IFCR_CTEIF6_Msk (0x1U << DMA_IFCR_CTEIF6_Pos) /*!< 0x00800000 */ 03255 #define DMA_IFCR_CTEIF6 DMA_IFCR_CTEIF6_Msk /*!< Channel 6 Transfer Error clear */ 03256 #define DMA_IFCR_CGIF7_Pos (24U) 03257 #define DMA_IFCR_CGIF7_Msk (0x1U << DMA_IFCR_CGIF7_Pos) /*!< 0x01000000 */ 03258 #define DMA_IFCR_CGIF7 DMA_IFCR_CGIF7_Msk /*!< Channel 7 Global interrupt clear */ 03259 #define DMA_IFCR_CTCIF7_Pos (25U) 03260 #define DMA_IFCR_CTCIF7_Msk (0x1U << DMA_IFCR_CTCIF7_Pos) /*!< 0x02000000 */ 03261 #define DMA_IFCR_CTCIF7 DMA_IFCR_CTCIF7_Msk /*!< Channel 7 Transfer Complete clear */ 03262 #define DMA_IFCR_CHTIF7_Pos (26U) 03263 #define DMA_IFCR_CHTIF7_Msk (0x1U << DMA_IFCR_CHTIF7_Pos) /*!< 0x04000000 */ 03264 #define DMA_IFCR_CHTIF7 DMA_IFCR_CHTIF7_Msk /*!< Channel 7 Half Transfer clear */ 03265 #define DMA_IFCR_CTEIF7_Pos (27U) 03266 #define DMA_IFCR_CTEIF7_Msk (0x1U << DMA_IFCR_CTEIF7_Pos) /*!< 0x08000000 */ 03267 #define DMA_IFCR_CTEIF7 DMA_IFCR_CTEIF7_Msk /*!< Channel 7 Transfer Error clear */ 03268 03269 /******************* Bit definition for DMA_CCR register *******************/ 03270 #define DMA_CCR_EN_Pos (0U) 03271 #define DMA_CCR_EN_Msk (0x1U << DMA_CCR_EN_Pos) /*!< 0x00000001 */ 03272 #define DMA_CCR_EN DMA_CCR_EN_Msk /*!< Channel enable */ 03273 #define DMA_CCR_TCIE_Pos (1U) 03274 #define DMA_CCR_TCIE_Msk (0x1U << DMA_CCR_TCIE_Pos) /*!< 0x00000002 */ 03275 #define DMA_CCR_TCIE DMA_CCR_TCIE_Msk /*!< Transfer complete interrupt enable */ 03276 #define DMA_CCR_HTIE_Pos (2U) 03277 #define DMA_CCR_HTIE_Msk (0x1U << DMA_CCR_HTIE_Pos) /*!< 0x00000004 */ 03278 #define DMA_CCR_HTIE DMA_CCR_HTIE_Msk /*!< Half Transfer interrupt enable */ 03279 #define DMA_CCR_TEIE_Pos (3U) 03280 #define DMA_CCR_TEIE_Msk (0x1U << DMA_CCR_TEIE_Pos) /*!< 0x00000008 */ 03281 #define DMA_CCR_TEIE DMA_CCR_TEIE_Msk /*!< Transfer error interrupt enable */ 03282 #define DMA_CCR_DIR_Pos (4U) 03283 #define DMA_CCR_DIR_Msk (0x1U << DMA_CCR_DIR_Pos) /*!< 0x00000010 */ 03284 #define DMA_CCR_DIR DMA_CCR_DIR_Msk /*!< Data transfer direction */ 03285 #define DMA_CCR_CIRC_Pos (5U) 03286 #define DMA_CCR_CIRC_Msk (0x1U << DMA_CCR_CIRC_Pos) /*!< 0x00000020 */ 03287 #define DMA_CCR_CIRC DMA_CCR_CIRC_Msk /*!< Circular mode */ 03288 #define DMA_CCR_PINC_Pos (6U) 03289 #define DMA_CCR_PINC_Msk (0x1U << DMA_CCR_PINC_Pos) /*!< 0x00000040 */ 03290 #define DMA_CCR_PINC DMA_CCR_PINC_Msk /*!< Peripheral increment mode */ 03291 #define DMA_CCR_MINC_Pos (7U) 03292 #define DMA_CCR_MINC_Msk (0x1U << DMA_CCR_MINC_Pos) /*!< 0x00000080 */ 03293 #define DMA_CCR_MINC DMA_CCR_MINC_Msk /*!< Memory increment mode */ 03294 03295 #define DMA_CCR_PSIZE_Pos (8U) 03296 #define DMA_CCR_PSIZE_Msk (0x3U << DMA_CCR_PSIZE_Pos) /*!< 0x00000300 */ 03297 #define DMA_CCR_PSIZE DMA_CCR_PSIZE_Msk /*!< PSIZE[1:0] bits (Peripheral size) */ 03298 #define DMA_CCR_PSIZE_0 (0x1U << DMA_CCR_PSIZE_Pos) /*!< 0x00000100 */ 03299 #define DMA_CCR_PSIZE_1 (0x2U << DMA_CCR_PSIZE_Pos) /*!< 0x00000200 */ 03300 03301 #define DMA_CCR_MSIZE_Pos (10U) 03302 #define DMA_CCR_MSIZE_Msk (0x3U << DMA_CCR_MSIZE_Pos) /*!< 0x00000C00 */ 03303 #define DMA_CCR_MSIZE DMA_CCR_MSIZE_Msk /*!< MSIZE[1:0] bits (Memory size) */ 03304 #define DMA_CCR_MSIZE_0 (0x1U << DMA_CCR_MSIZE_Pos) /*!< 0x00000400 */ 03305 #define DMA_CCR_MSIZE_1 (0x2U << DMA_CCR_MSIZE_Pos) /*!< 0x00000800 */ 03306 03307 #define DMA_CCR_PL_Pos (12U) 03308 #define DMA_CCR_PL_Msk (0x3U << DMA_CCR_PL_Pos) /*!< 0x00003000 */ 03309 #define DMA_CCR_PL DMA_CCR_PL_Msk /*!< PL[1:0] bits(Channel Priority level) */ 03310 #define DMA_CCR_PL_0 (0x1U << DMA_CCR_PL_Pos) /*!< 0x00001000 */ 03311 #define DMA_CCR_PL_1 (0x2U << DMA_CCR_PL_Pos) /*!< 0x00002000 */ 03312 03313 #define DMA_CCR_MEM2MEM_Pos (14U) 03314 #define DMA_CCR_MEM2MEM_Msk (0x1U << DMA_CCR_MEM2MEM_Pos) /*!< 0x00004000 */ 03315 #define DMA_CCR_MEM2MEM DMA_CCR_MEM2MEM_Msk /*!< Memory to memory mode */ 03316 03317 /****************** Bit definition for DMA_CNDTR register ******************/ 03318 #define DMA_CNDTR_NDT_Pos (0U) 03319 #define DMA_CNDTR_NDT_Msk (0xFFFFU << DMA_CNDTR_NDT_Pos) /*!< 0x0000FFFF */ 03320 #define DMA_CNDTR_NDT DMA_CNDTR_NDT_Msk /*!< Number of data to Transfer */ 03321 03322 /****************** Bit definition for DMA_CPAR register *******************/ 03323 #define DMA_CPAR_PA_Pos (0U) 03324 #define DMA_CPAR_PA_Msk (0xFFFFFFFFU << DMA_CPAR_PA_Pos) /*!< 0xFFFFFFFF */ 03325 #define DMA_CPAR_PA DMA_CPAR_PA_Msk /*!< Peripheral Address */ 03326 03327 /****************** Bit definition for DMA_CMAR register *******************/ 03328 #define DMA_CMAR_MA_Pos (0U) 03329 #define DMA_CMAR_MA_Msk (0xFFFFFFFFU << DMA_CMAR_MA_Pos) /*!< 0xFFFFFFFF */ 03330 #define DMA_CMAR_MA DMA_CMAR_MA_Msk /*!< Memory Address */ 03331 03332 /******************************************************************************/ 03333 /* */ 03334 /* Analog to Digital Converter (ADC) */ 03335 /* */ 03336 /******************************************************************************/ 03337 03338 /* 03339 * @brief Specific device feature definitions (not present on all devices in the STM32F1 family) 03340 */ 03341 #define ADC_MULTIMODE_SUPPORT /*!< ADC feature available only on specific devices: multimode available on devices with several ADC instances */ 03342 03343 /******************** Bit definition for ADC_SR register ********************/ 03344 #define ADC_SR_AWD_Pos (0U) 03345 #define ADC_SR_AWD_Msk (0x1U << ADC_SR_AWD_Pos) /*!< 0x00000001 */ 03346 #define ADC_SR_AWD ADC_SR_AWD_Msk /*!< ADC analog watchdog 1 flag */ 03347 #define ADC_SR_EOS_Pos (1U) 03348 #define ADC_SR_EOS_Msk (0x1U << ADC_SR_EOS_Pos) /*!< 0x00000002 */ 03349 #define ADC_SR_EOS ADC_SR_EOS_Msk /*!< ADC group regular end of sequence conversions flag */ 03350 #define ADC_SR_JEOS_Pos (2U) 03351 #define ADC_SR_JEOS_Msk (0x1U << ADC_SR_JEOS_Pos) /*!< 0x00000004 */ 03352 #define ADC_SR_JEOS ADC_SR_JEOS_Msk /*!< ADC group injected end of sequence conversions flag */ 03353 #define ADC_SR_JSTRT_Pos (3U) 03354 #define ADC_SR_JSTRT_Msk (0x1U << ADC_SR_JSTRT_Pos) /*!< 0x00000008 */ 03355 #define ADC_SR_JSTRT ADC_SR_JSTRT_Msk /*!< ADC group injected conversion start flag */ 03356 #define ADC_SR_STRT_Pos (4U) 03357 #define ADC_SR_STRT_Msk (0x1U << ADC_SR_STRT_Pos) /*!< 0x00000010 */ 03358 #define ADC_SR_STRT ADC_SR_STRT_Msk /*!< ADC group regular conversion start flag */ 03359 03360 /* Legacy defines */ 03361 #define ADC_SR_EOC (ADC_SR_EOS) 03362 #define ADC_SR_JEOC (ADC_SR_JEOS) 03363 03364 /******************* Bit definition for ADC_CR1 register ********************/ 03365 #define ADC_CR1_AWDCH_Pos (0U) 03366 #define ADC_CR1_AWDCH_Msk (0x1FU << ADC_CR1_AWDCH_Pos) /*!< 0x0000001F */ 03367 #define ADC_CR1_AWDCH ADC_CR1_AWDCH_Msk /*!< ADC analog watchdog 1 monitored channel selection */ 03368 #define ADC_CR1_AWDCH_0 (0x01U << ADC_CR1_AWDCH_Pos) /*!< 0x00000001 */ 03369 #define ADC_CR1_AWDCH_1 (0x02U << ADC_CR1_AWDCH_Pos) /*!< 0x00000002 */ 03370 #define ADC_CR1_AWDCH_2 (0x04U << ADC_CR1_AWDCH_Pos) /*!< 0x00000004 */ 03371 #define ADC_CR1_AWDCH_3 (0x08U << ADC_CR1_AWDCH_Pos) /*!< 0x00000008 */ 03372 #define ADC_CR1_AWDCH_4 (0x10U << ADC_CR1_AWDCH_Pos) /*!< 0x00000010 */ 03373 03374 #define ADC_CR1_EOSIE_Pos (5U) 03375 #define ADC_CR1_EOSIE_Msk (0x1U << ADC_CR1_EOSIE_Pos) /*!< 0x00000020 */ 03376 #define ADC_CR1_EOSIE ADC_CR1_EOSIE_Msk /*!< ADC group regular end of sequence conversions interrupt */ 03377 #define ADC_CR1_AWDIE_Pos (6U) 03378 #define ADC_CR1_AWDIE_Msk (0x1U << ADC_CR1_AWDIE_Pos) /*!< 0x00000040 */ 03379 #define ADC_CR1_AWDIE ADC_CR1_AWDIE_Msk /*!< ADC analog watchdog 1 interrupt */ 03380 #define ADC_CR1_JEOSIE_Pos (7U) 03381 #define ADC_CR1_JEOSIE_Msk (0x1U << ADC_CR1_JEOSIE_Pos) /*!< 0x00000080 */ 03382 #define ADC_CR1_JEOSIE ADC_CR1_JEOSIE_Msk /*!< ADC group injected end of sequence conversions interrupt */ 03383 #define ADC_CR1_SCAN_Pos (8U) 03384 #define ADC_CR1_SCAN_Msk (0x1U << ADC_CR1_SCAN_Pos) /*!< 0x00000100 */ 03385 #define ADC_CR1_SCAN ADC_CR1_SCAN_Msk /*!< ADC scan mode */ 03386 #define ADC_CR1_AWDSGL_Pos (9U) 03387 #define ADC_CR1_AWDSGL_Msk (0x1U << ADC_CR1_AWDSGL_Pos) /*!< 0x00000200 */ 03388 #define ADC_CR1_AWDSGL ADC_CR1_AWDSGL_Msk /*!< ADC analog watchdog 1 monitoring a single channel or all channels */ 03389 #define ADC_CR1_JAUTO_Pos (10U) 03390 #define ADC_CR1_JAUTO_Msk (0x1U << ADC_CR1_JAUTO_Pos) /*!< 0x00000400 */ 03391 #define ADC_CR1_JAUTO ADC_CR1_JAUTO_Msk /*!< ADC group injected automatic trigger mode */ 03392 #define ADC_CR1_DISCEN_Pos (11U) 03393 #define ADC_CR1_DISCEN_Msk (0x1U << ADC_CR1_DISCEN_Pos) /*!< 0x00000800 */ 03394 #define ADC_CR1_DISCEN ADC_CR1_DISCEN_Msk /*!< ADC group regular sequencer discontinuous mode */ 03395 #define ADC_CR1_JDISCEN_Pos (12U) 03396 #define ADC_CR1_JDISCEN_Msk (0x1U << ADC_CR1_JDISCEN_Pos) /*!< 0x00001000 */ 03397 #define ADC_CR1_JDISCEN ADC_CR1_JDISCEN_Msk /*!< ADC group injected sequencer discontinuous mode */ 03398 03399 #define ADC_CR1_DISCNUM_Pos (13U) 03400 #define ADC_CR1_DISCNUM_Msk (0x7U << ADC_CR1_DISCNUM_Pos) /*!< 0x0000E000 */ 03401 #define ADC_CR1_DISCNUM ADC_CR1_DISCNUM_Msk /*!< ADC group regular sequencer discontinuous number of ranks */ 03402 #define ADC_CR1_DISCNUM_0 (0x1U << ADC_CR1_DISCNUM_Pos) /*!< 0x00002000 */ 03403 #define ADC_CR1_DISCNUM_1 (0x2U << ADC_CR1_DISCNUM_Pos) /*!< 0x00004000 */ 03404 #define ADC_CR1_DISCNUM_2 (0x4U << ADC_CR1_DISCNUM_Pos) /*!< 0x00008000 */ 03405 03406 #define ADC_CR1_DUALMOD_Pos (16U) 03407 #define ADC_CR1_DUALMOD_Msk (0xFU << ADC_CR1_DUALMOD_Pos) /*!< 0x000F0000 */ 03408 #define ADC_CR1_DUALMOD ADC_CR1_DUALMOD_Msk /*!< ADC multimode mode selection */ 03409 #define ADC_CR1_DUALMOD_0 (0x1U << ADC_CR1_DUALMOD_Pos) /*!< 0x00010000 */ 03410 #define ADC_CR1_DUALMOD_1 (0x2U << ADC_CR1_DUALMOD_Pos) /*!< 0x00020000 */ 03411 #define ADC_CR1_DUALMOD_2 (0x4U << ADC_CR1_DUALMOD_Pos) /*!< 0x00040000 */ 03412 #define ADC_CR1_DUALMOD_3 (0x8U << ADC_CR1_DUALMOD_Pos) /*!< 0x00080000 */ 03413 03414 #define ADC_CR1_JAWDEN_Pos (22U) 03415 #define ADC_CR1_JAWDEN_Msk (0x1U << ADC_CR1_JAWDEN_Pos) /*!< 0x00400000 */ 03416 #define ADC_CR1_JAWDEN ADC_CR1_JAWDEN_Msk /*!< ADC analog watchdog 1 enable on scope ADC group injected */ 03417 #define ADC_CR1_AWDEN_Pos (23U) 03418 #define ADC_CR1_AWDEN_Msk (0x1U << ADC_CR1_AWDEN_Pos) /*!< 0x00800000 */ 03419 #define ADC_CR1_AWDEN ADC_CR1_AWDEN_Msk /*!< ADC analog watchdog 1 enable on scope ADC group regular */ 03420 03421 /* Legacy defines */ 03422 #define ADC_CR1_EOCIE (ADC_CR1_EOSIE) 03423 #define ADC_CR1_JEOCIE (ADC_CR1_JEOSIE) 03424 03425 /******************* Bit definition for ADC_CR2 register ********************/ 03426 #define ADC_CR2_ADON_Pos (0U) 03427 #define ADC_CR2_ADON_Msk (0x1U << ADC_CR2_ADON_Pos) /*!< 0x00000001 */ 03428 #define ADC_CR2_ADON ADC_CR2_ADON_Msk /*!< ADC enable */ 03429 #define ADC_CR2_CONT_Pos (1U) 03430 #define ADC_CR2_CONT_Msk (0x1U << ADC_CR2_CONT_Pos) /*!< 0x00000002 */ 03431 #define ADC_CR2_CONT ADC_CR2_CONT_Msk /*!< ADC group regular continuous conversion mode */ 03432 #define ADC_CR2_CAL_Pos (2U) 03433 #define ADC_CR2_CAL_Msk (0x1U << ADC_CR2_CAL_Pos) /*!< 0x00000004 */ 03434 #define ADC_CR2_CAL ADC_CR2_CAL_Msk /*!< ADC calibration start */ 03435 #define ADC_CR2_RSTCAL_Pos (3U) 03436 #define ADC_CR2_RSTCAL_Msk (0x1U << ADC_CR2_RSTCAL_Pos) /*!< 0x00000008 */ 03437 #define ADC_CR2_RSTCAL ADC_CR2_RSTCAL_Msk /*!< ADC calibration reset */ 03438 #define ADC_CR2_DMA_Pos (8U) 03439 #define ADC_CR2_DMA_Msk (0x1U << ADC_CR2_DMA_Pos) /*!< 0x00000100 */ 03440 #define ADC_CR2_DMA ADC_CR2_DMA_Msk /*!< ADC DMA transfer enable */ 03441 #define ADC_CR2_ALIGN_Pos (11U) 03442 #define ADC_CR2_ALIGN_Msk (0x1U << ADC_CR2_ALIGN_Pos) /*!< 0x00000800 */ 03443 #define ADC_CR2_ALIGN ADC_CR2_ALIGN_Msk /*!< ADC data alignement */ 03444 03445 #define ADC_CR2_JEXTSEL_Pos (12U) 03446 #define ADC_CR2_JEXTSEL_Msk (0x7U << ADC_CR2_JEXTSEL_Pos) /*!< 0x00007000 */ 03447 #define ADC_CR2_JEXTSEL ADC_CR2_JEXTSEL_Msk /*!< ADC group injected external trigger source */ 03448 #define ADC_CR2_JEXTSEL_0 (0x1U << ADC_CR2_JEXTSEL_Pos) /*!< 0x00001000 */ 03449 #define ADC_CR2_JEXTSEL_1 (0x2U << ADC_CR2_JEXTSEL_Pos) /*!< 0x00002000 */ 03450 #define ADC_CR2_JEXTSEL_2 (0x4U << ADC_CR2_JEXTSEL_Pos) /*!< 0x00004000 */ 03451 03452 #define ADC_CR2_JEXTTRIG_Pos (15U) 03453 #define ADC_CR2_JEXTTRIG_Msk (0x1U << ADC_CR2_JEXTTRIG_Pos) /*!< 0x00008000 */ 03454 #define ADC_CR2_JEXTTRIG ADC_CR2_JEXTTRIG_Msk /*!< ADC group injected external trigger enable */ 03455 03456 #define ADC_CR2_EXTSEL_Pos (17U) 03457 #define ADC_CR2_EXTSEL_Msk (0x7U << ADC_CR2_EXTSEL_Pos) /*!< 0x000E0000 */ 03458 #define ADC_CR2_EXTSEL ADC_CR2_EXTSEL_Msk /*!< ADC group regular external trigger source */ 03459 #define ADC_CR2_EXTSEL_0 (0x1U << ADC_CR2_EXTSEL_Pos) /*!< 0x00020000 */ 03460 #define ADC_CR2_EXTSEL_1 (0x2U << ADC_CR2_EXTSEL_Pos) /*!< 0x00040000 */ 03461 #define ADC_CR2_EXTSEL_2 (0x4U << ADC_CR2_EXTSEL_Pos) /*!< 0x00080000 */ 03462 03463 #define ADC_CR2_EXTTRIG_Pos (20U) 03464 #define ADC_CR2_EXTTRIG_Msk (0x1U << ADC_CR2_EXTTRIG_Pos) /*!< 0x00100000 */ 03465 #define ADC_CR2_EXTTRIG ADC_CR2_EXTTRIG_Msk /*!< ADC group regular external trigger enable */ 03466 #define ADC_CR2_JSWSTART_Pos (21U) 03467 #define ADC_CR2_JSWSTART_Msk (0x1U << ADC_CR2_JSWSTART_Pos) /*!< 0x00200000 */ 03468 #define ADC_CR2_JSWSTART ADC_CR2_JSWSTART_Msk /*!< ADC group injected conversion start */ 03469 #define ADC_CR2_SWSTART_Pos (22U) 03470 #define ADC_CR2_SWSTART_Msk (0x1U << ADC_CR2_SWSTART_Pos) /*!< 0x00400000 */ 03471 #define ADC_CR2_SWSTART ADC_CR2_SWSTART_Msk /*!< ADC group regular conversion start */ 03472 #define ADC_CR2_TSVREFE_Pos (23U) 03473 #define ADC_CR2_TSVREFE_Msk (0x1U << ADC_CR2_TSVREFE_Pos) /*!< 0x00800000 */ 03474 #define ADC_CR2_TSVREFE ADC_CR2_TSVREFE_Msk /*!< ADC internal path to VrefInt and temperature sensor enable */ 03475 03476 /****************** Bit definition for ADC_SMPR1 register *******************/ 03477 #define ADC_SMPR1_SMP10_Pos (0U) 03478 #define ADC_SMPR1_SMP10_Msk (0x7U << ADC_SMPR1_SMP10_Pos) /*!< 0x00000007 */ 03479 #define ADC_SMPR1_SMP10 ADC_SMPR1_SMP10_Msk /*!< ADC channel 10 sampling time selection */ 03480 #define ADC_SMPR1_SMP10_0 (0x1U << ADC_SMPR1_SMP10_Pos) /*!< 0x00000001 */ 03481 #define ADC_SMPR1_SMP10_1 (0x2U << ADC_SMPR1_SMP10_Pos) /*!< 0x00000002 */ 03482 #define ADC_SMPR1_SMP10_2 (0x4U << ADC_SMPR1_SMP10_Pos) /*!< 0x00000004 */ 03483 03484 #define ADC_SMPR1_SMP11_Pos (3U) 03485 #define ADC_SMPR1_SMP11_Msk (0x7U << ADC_SMPR1_SMP11_Pos) /*!< 0x00000038 */ 03486 #define ADC_SMPR1_SMP11 ADC_SMPR1_SMP11_Msk /*!< ADC channel 11 sampling time selection */ 03487 #define ADC_SMPR1_SMP11_0 (0x1U << ADC_SMPR1_SMP11_Pos) /*!< 0x00000008 */ 03488 #define ADC_SMPR1_SMP11_1 (0x2U << ADC_SMPR1_SMP11_Pos) /*!< 0x00000010 */ 03489 #define ADC_SMPR1_SMP11_2 (0x4U << ADC_SMPR1_SMP11_Pos) /*!< 0x00000020 */ 03490 03491 #define ADC_SMPR1_SMP12_Pos (6U) 03492 #define ADC_SMPR1_SMP12_Msk (0x7U << ADC_SMPR1_SMP12_Pos) /*!< 0x000001C0 */ 03493 #define ADC_SMPR1_SMP12 ADC_SMPR1_SMP12_Msk /*!< ADC channel 12 sampling time selection */ 03494 #define ADC_SMPR1_SMP12_0 (0x1U << ADC_SMPR1_SMP12_Pos) /*!< 0x00000040 */ 03495 #define ADC_SMPR1_SMP12_1 (0x2U << ADC_SMPR1_SMP12_Pos) /*!< 0x00000080 */ 03496 #define ADC_SMPR1_SMP12_2 (0x4U << ADC_SMPR1_SMP12_Pos) /*!< 0x00000100 */ 03497 03498 #define ADC_SMPR1_SMP13_Pos (9U) 03499 #define ADC_SMPR1_SMP13_Msk (0x7U << ADC_SMPR1_SMP13_Pos) /*!< 0x00000E00 */ 03500 #define ADC_SMPR1_SMP13 ADC_SMPR1_SMP13_Msk /*!< ADC channel 13 sampling time selection */ 03501 #define ADC_SMPR1_SMP13_0 (0x1U << ADC_SMPR1_SMP13_Pos) /*!< 0x00000200 */ 03502 #define ADC_SMPR1_SMP13_1 (0x2U << ADC_SMPR1_SMP13_Pos) /*!< 0x00000400 */ 03503 #define ADC_SMPR1_SMP13_2 (0x4U << ADC_SMPR1_SMP13_Pos) /*!< 0x00000800 */ 03504 03505 #define ADC_SMPR1_SMP14_Pos (12U) 03506 #define ADC_SMPR1_SMP14_Msk (0x7U << ADC_SMPR1_SMP14_Pos) /*!< 0x00007000 */ 03507 #define ADC_SMPR1_SMP14 ADC_SMPR1_SMP14_Msk /*!< ADC channel 14 sampling time selection */ 03508 #define ADC_SMPR1_SMP14_0 (0x1U << ADC_SMPR1_SMP14_Pos) /*!< 0x00001000 */ 03509 #define ADC_SMPR1_SMP14_1 (0x2U << ADC_SMPR1_SMP14_Pos) /*!< 0x00002000 */ 03510 #define ADC_SMPR1_SMP14_2 (0x4U << ADC_SMPR1_SMP14_Pos) /*!< 0x00004000 */ 03511 03512 #define ADC_SMPR1_SMP15_Pos (15U) 03513 #define ADC_SMPR1_SMP15_Msk (0x7U << ADC_SMPR1_SMP15_Pos) /*!< 0x00038000 */ 03514 #define ADC_SMPR1_SMP15 ADC_SMPR1_SMP15_Msk /*!< ADC channel 15 sampling time selection */ 03515 #define ADC_SMPR1_SMP15_0 (0x1U << ADC_SMPR1_SMP15_Pos) /*!< 0x00008000 */ 03516 #define ADC_SMPR1_SMP15_1 (0x2U << ADC_SMPR1_SMP15_Pos) /*!< 0x00010000 */ 03517 #define ADC_SMPR1_SMP15_2 (0x4U << ADC_SMPR1_SMP15_Pos) /*!< 0x00020000 */ 03518 03519 #define ADC_SMPR1_SMP16_Pos (18U) 03520 #define ADC_SMPR1_SMP16_Msk (0x7U << ADC_SMPR1_SMP16_Pos) /*!< 0x001C0000 */ 03521 #define ADC_SMPR1_SMP16 ADC_SMPR1_SMP16_Msk /*!< ADC channel 16 sampling time selection */ 03522 #define ADC_SMPR1_SMP16_0 (0x1U << ADC_SMPR1_SMP16_Pos) /*!< 0x00040000 */ 03523 #define ADC_SMPR1_SMP16_1 (0x2U << ADC_SMPR1_SMP16_Pos) /*!< 0x00080000 */ 03524 #define ADC_SMPR1_SMP16_2 (0x4U << ADC_SMPR1_SMP16_Pos) /*!< 0x00100000 */ 03525 03526 #define ADC_SMPR1_SMP17_Pos (21U) 03527 #define ADC_SMPR1_SMP17_Msk (0x7U << ADC_SMPR1_SMP17_Pos) /*!< 0x00E00000 */ 03528 #define ADC_SMPR1_SMP17 ADC_SMPR1_SMP17_Msk /*!< ADC channel 17 sampling time selection */ 03529 #define ADC_SMPR1_SMP17_0 (0x1U << ADC_SMPR1_SMP17_Pos) /*!< 0x00200000 */ 03530 #define ADC_SMPR1_SMP17_1 (0x2U << ADC_SMPR1_SMP17_Pos) /*!< 0x00400000 */ 03531 #define ADC_SMPR1_SMP17_2 (0x4U << ADC_SMPR1_SMP17_Pos) /*!< 0x00800000 */ 03532 03533 /****************** Bit definition for ADC_SMPR2 register *******************/ 03534 #define ADC_SMPR2_SMP0_Pos (0U) 03535 #define ADC_SMPR2_SMP0_Msk (0x7U << ADC_SMPR2_SMP0_Pos) /*!< 0x00000007 */ 03536 #define ADC_SMPR2_SMP0 ADC_SMPR2_SMP0_Msk /*!< ADC channel 0 sampling time selection */ 03537 #define ADC_SMPR2_SMP0_0 (0x1U << ADC_SMPR2_SMP0_Pos) /*!< 0x00000001 */ 03538 #define ADC_SMPR2_SMP0_1 (0x2U << ADC_SMPR2_SMP0_Pos) /*!< 0x00000002 */ 03539 #define ADC_SMPR2_SMP0_2 (0x4U << ADC_SMPR2_SMP0_Pos) /*!< 0x00000004 */ 03540 03541 #define ADC_SMPR2_SMP1_Pos (3U) 03542 #define ADC_SMPR2_SMP1_Msk (0x7U << ADC_SMPR2_SMP1_Pos) /*!< 0x00000038 */ 03543 #define ADC_SMPR2_SMP1 ADC_SMPR2_SMP1_Msk /*!< ADC channel 1 sampling time selection */ 03544 #define ADC_SMPR2_SMP1_0 (0x1U << ADC_SMPR2_SMP1_Pos) /*!< 0x00000008 */ 03545 #define ADC_SMPR2_SMP1_1 (0x2U << ADC_SMPR2_SMP1_Pos) /*!< 0x00000010 */ 03546 #define ADC_SMPR2_SMP1_2 (0x4U << ADC_SMPR2_SMP1_Pos) /*!< 0x00000020 */ 03547 03548 #define ADC_SMPR2_SMP2_Pos (6U) 03549 #define ADC_SMPR2_SMP2_Msk (0x7U << ADC_SMPR2_SMP2_Pos) /*!< 0x000001C0 */ 03550 #define ADC_SMPR2_SMP2 ADC_SMPR2_SMP2_Msk /*!< ADC channel 2 sampling time selection */ 03551 #define ADC_SMPR2_SMP2_0 (0x1U << ADC_SMPR2_SMP2_Pos) /*!< 0x00000040 */ 03552 #define ADC_SMPR2_SMP2_1 (0x2U << ADC_SMPR2_SMP2_Pos) /*!< 0x00000080 */ 03553 #define ADC_SMPR2_SMP2_2 (0x4U << ADC_SMPR2_SMP2_Pos) /*!< 0x00000100 */ 03554 03555 #define ADC_SMPR2_SMP3_Pos (9U) 03556 #define ADC_SMPR2_SMP3_Msk (0x7U << ADC_SMPR2_SMP3_Pos) /*!< 0x00000E00 */ 03557 #define ADC_SMPR2_SMP3 ADC_SMPR2_SMP3_Msk /*!< ADC channel 3 sampling time selection */ 03558 #define ADC_SMPR2_SMP3_0 (0x1U << ADC_SMPR2_SMP3_Pos) /*!< 0x00000200 */ 03559 #define ADC_SMPR2_SMP3_1 (0x2U << ADC_SMPR2_SMP3_Pos) /*!< 0x00000400 */ 03560 #define ADC_SMPR2_SMP3_2 (0x4U << ADC_SMPR2_SMP3_Pos) /*!< 0x00000800 */ 03561 03562 #define ADC_SMPR2_SMP4_Pos (12U) 03563 #define ADC_SMPR2_SMP4_Msk (0x7U << ADC_SMPR2_SMP4_Pos) /*!< 0x00007000 */ 03564 #define ADC_SMPR2_SMP4 ADC_SMPR2_SMP4_Msk /*!< ADC channel 4 sampling time selection */ 03565 #define ADC_SMPR2_SMP4_0 (0x1U << ADC_SMPR2_SMP4_Pos) /*!< 0x00001000 */ 03566 #define ADC_SMPR2_SMP4_1 (0x2U << ADC_SMPR2_SMP4_Pos) /*!< 0x00002000 */ 03567 #define ADC_SMPR2_SMP4_2 (0x4U << ADC_SMPR2_SMP4_Pos) /*!< 0x00004000 */ 03568 03569 #define ADC_SMPR2_SMP5_Pos (15U) 03570 #define ADC_SMPR2_SMP5_Msk (0x7U << ADC_SMPR2_SMP5_Pos) /*!< 0x00038000 */ 03571 #define ADC_SMPR2_SMP5 ADC_SMPR2_SMP5_Msk /*!< ADC channel 5 sampling time selection */ 03572 #define ADC_SMPR2_SMP5_0 (0x1U << ADC_SMPR2_SMP5_Pos) /*!< 0x00008000 */ 03573 #define ADC_SMPR2_SMP5_1 (0x2U << ADC_SMPR2_SMP5_Pos) /*!< 0x00010000 */ 03574 #define ADC_SMPR2_SMP5_2 (0x4U << ADC_SMPR2_SMP5_Pos) /*!< 0x00020000 */ 03575 03576 #define ADC_SMPR2_SMP6_Pos (18U) 03577 #define ADC_SMPR2_SMP6_Msk (0x7U << ADC_SMPR2_SMP6_Pos) /*!< 0x001C0000 */ 03578 #define ADC_SMPR2_SMP6 ADC_SMPR2_SMP6_Msk /*!< ADC channel 6 sampling time selection */ 03579 #define ADC_SMPR2_SMP6_0 (0x1U << ADC_SMPR2_SMP6_Pos) /*!< 0x00040000 */ 03580 #define ADC_SMPR2_SMP6_1 (0x2U << ADC_SMPR2_SMP6_Pos) /*!< 0x00080000 */ 03581 #define ADC_SMPR2_SMP6_2 (0x4U << ADC_SMPR2_SMP6_Pos) /*!< 0x00100000 */ 03582 03583 #define ADC_SMPR2_SMP7_Pos (21U) 03584 #define ADC_SMPR2_SMP7_Msk (0x7U << ADC_SMPR2_SMP7_Pos) /*!< 0x00E00000 */ 03585 #define ADC_SMPR2_SMP7 ADC_SMPR2_SMP7_Msk /*!< ADC channel 7 sampling time selection */ 03586 #define ADC_SMPR2_SMP7_0 (0x1U << ADC_SMPR2_SMP7_Pos) /*!< 0x00200000 */ 03587 #define ADC_SMPR2_SMP7_1 (0x2U << ADC_SMPR2_SMP7_Pos) /*!< 0x00400000 */ 03588 #define ADC_SMPR2_SMP7_2 (0x4U << ADC_SMPR2_SMP7_Pos) /*!< 0x00800000 */ 03589 03590 #define ADC_SMPR2_SMP8_Pos (24U) 03591 #define ADC_SMPR2_SMP8_Msk (0x7U << ADC_SMPR2_SMP8_Pos) /*!< 0x07000000 */ 03592 #define ADC_SMPR2_SMP8 ADC_SMPR2_SMP8_Msk /*!< ADC channel 8 sampling time selection */ 03593 #define ADC_SMPR2_SMP8_0 (0x1U << ADC_SMPR2_SMP8_Pos) /*!< 0x01000000 */ 03594 #define ADC_SMPR2_SMP8_1 (0x2U << ADC_SMPR2_SMP8_Pos) /*!< 0x02000000 */ 03595 #define ADC_SMPR2_SMP8_2 (0x4U << ADC_SMPR2_SMP8_Pos) /*!< 0x04000000 */ 03596 03597 #define ADC_SMPR2_SMP9_Pos (27U) 03598 #define ADC_SMPR2_SMP9_Msk (0x7U << ADC_SMPR2_SMP9_Pos) /*!< 0x38000000 */ 03599 #define ADC_SMPR2_SMP9 ADC_SMPR2_SMP9_Msk /*!< ADC channel 9 sampling time selection */ 03600 #define ADC_SMPR2_SMP9_0 (0x1U << ADC_SMPR2_SMP9_Pos) /*!< 0x08000000 */ 03601 #define ADC_SMPR2_SMP9_1 (0x2U << ADC_SMPR2_SMP9_Pos) /*!< 0x10000000 */ 03602 #define ADC_SMPR2_SMP9_2 (0x4U << ADC_SMPR2_SMP9_Pos) /*!< 0x20000000 */ 03603 03604 /****************** Bit definition for ADC_JOFR1 register *******************/ 03605 #define ADC_JOFR1_JOFFSET1_Pos (0U) 03606 #define ADC_JOFR1_JOFFSET1_Msk (0xFFFU << ADC_JOFR1_JOFFSET1_Pos) /*!< 0x00000FFF */ 03607 #define ADC_JOFR1_JOFFSET1 ADC_JOFR1_JOFFSET1_Msk /*!< ADC group injected sequencer rank 1 offset value */ 03608 03609 /****************** Bit definition for ADC_JOFR2 register *******************/ 03610 #define ADC_JOFR2_JOFFSET2_Pos (0U) 03611 #define ADC_JOFR2_JOFFSET2_Msk (0xFFFU << ADC_JOFR2_JOFFSET2_Pos) /*!< 0x00000FFF */ 03612 #define ADC_JOFR2_JOFFSET2 ADC_JOFR2_JOFFSET2_Msk /*!< ADC group injected sequencer rank 2 offset value */ 03613 03614 /****************** Bit definition for ADC_JOFR3 register *******************/ 03615 #define ADC_JOFR3_JOFFSET3_Pos (0U) 03616 #define ADC_JOFR3_JOFFSET3_Msk (0xFFFU << ADC_JOFR3_JOFFSET3_Pos) /*!< 0x00000FFF */ 03617 #define ADC_JOFR3_JOFFSET3 ADC_JOFR3_JOFFSET3_Msk /*!< ADC group injected sequencer rank 3 offset value */ 03618 03619 /****************** Bit definition for ADC_JOFR4 register *******************/ 03620 #define ADC_JOFR4_JOFFSET4_Pos (0U) 03621 #define ADC_JOFR4_JOFFSET4_Msk (0xFFFU << ADC_JOFR4_JOFFSET4_Pos) /*!< 0x00000FFF */ 03622 #define ADC_JOFR4_JOFFSET4 ADC_JOFR4_JOFFSET4_Msk /*!< ADC group injected sequencer rank 4 offset value */ 03623 03624 /******************* Bit definition for ADC_HTR register ********************/ 03625 #define ADC_HTR_HT_Pos (0U) 03626 #define ADC_HTR_HT_Msk (0xFFFU << ADC_HTR_HT_Pos) /*!< 0x00000FFF */ 03627 #define ADC_HTR_HT ADC_HTR_HT_Msk /*!< ADC analog watchdog 1 threshold high */ 03628 03629 /******************* Bit definition for ADC_LTR register ********************/ 03630 #define ADC_LTR_LT_Pos (0U) 03631 #define ADC_LTR_LT_Msk (0xFFFU << ADC_LTR_LT_Pos) /*!< 0x00000FFF */ 03632 #define ADC_LTR_LT ADC_LTR_LT_Msk /*!< ADC analog watchdog 1 threshold low */ 03633 03634 /******************* Bit definition for ADC_SQR1 register *******************/ 03635 #define ADC_SQR1_SQ13_Pos (0U) 03636 #define ADC_SQR1_SQ13_Msk (0x1FU << ADC_SQR1_SQ13_Pos) /*!< 0x0000001F */ 03637 #define ADC_SQR1_SQ13 ADC_SQR1_SQ13_Msk /*!< ADC group regular sequencer rank 13 */ 03638 #define ADC_SQR1_SQ13_0 (0x01U << ADC_SQR1_SQ13_Pos) /*!< 0x00000001 */ 03639 #define ADC_SQR1_SQ13_1 (0x02U << ADC_SQR1_SQ13_Pos) /*!< 0x00000002 */ 03640 #define ADC_SQR1_SQ13_2 (0x04U << ADC_SQR1_SQ13_Pos) /*!< 0x00000004 */ 03641 #define ADC_SQR1_SQ13_3 (0x08U << ADC_SQR1_SQ13_Pos) /*!< 0x00000008 */ 03642 #define ADC_SQR1_SQ13_4 (0x10U << ADC_SQR1_SQ13_Pos) /*!< 0x00000010 */ 03643 03644 #define ADC_SQR1_SQ14_Pos (5U) 03645 #define ADC_SQR1_SQ14_Msk (0x1FU << ADC_SQR1_SQ14_Pos) /*!< 0x000003E0 */ 03646 #define ADC_SQR1_SQ14 ADC_SQR1_SQ14_Msk /*!< ADC group regular sequencer rank 14 */ 03647 #define ADC_SQR1_SQ14_0 (0x01U << ADC_SQR1_SQ14_Pos) /*!< 0x00000020 */ 03648 #define ADC_SQR1_SQ14_1 (0x02U << ADC_SQR1_SQ14_Pos) /*!< 0x00000040 */ 03649 #define ADC_SQR1_SQ14_2 (0x04U << ADC_SQR1_SQ14_Pos) /*!< 0x00000080 */ 03650 #define ADC_SQR1_SQ14_3 (0x08U << ADC_SQR1_SQ14_Pos) /*!< 0x00000100 */ 03651 #define ADC_SQR1_SQ14_4 (0x10U << ADC_SQR1_SQ14_Pos) /*!< 0x00000200 */ 03652 03653 #define ADC_SQR1_SQ15_Pos (10U) 03654 #define ADC_SQR1_SQ15_Msk (0x1FU << ADC_SQR1_SQ15_Pos) /*!< 0x00007C00 */ 03655 #define ADC_SQR1_SQ15 ADC_SQR1_SQ15_Msk /*!< ADC group regular sequencer rank 15 */ 03656 #define ADC_SQR1_SQ15_0 (0x01U << ADC_SQR1_SQ15_Pos) /*!< 0x00000400 */ 03657 #define ADC_SQR1_SQ15_1 (0x02U << ADC_SQR1_SQ15_Pos) /*!< 0x00000800 */ 03658 #define ADC_SQR1_SQ15_2 (0x04U << ADC_SQR1_SQ15_Pos) /*!< 0x00001000 */ 03659 #define ADC_SQR1_SQ15_3 (0x08U << ADC_SQR1_SQ15_Pos) /*!< 0x00002000 */ 03660 #define ADC_SQR1_SQ15_4 (0x10U << ADC_SQR1_SQ15_Pos) /*!< 0x00004000 */ 03661 03662 #define ADC_SQR1_SQ16_Pos (15U) 03663 #define ADC_SQR1_SQ16_Msk (0x1FU << ADC_SQR1_SQ16_Pos) /*!< 0x000F8000 */ 03664 #define ADC_SQR1_SQ16 ADC_SQR1_SQ16_Msk /*!< ADC group regular sequencer rank 16 */ 03665 #define ADC_SQR1_SQ16_0 (0x01U << ADC_SQR1_SQ16_Pos) /*!< 0x00008000 */ 03666 #define ADC_SQR1_SQ16_1 (0x02U << ADC_SQR1_SQ16_Pos) /*!< 0x00010000 */ 03667 #define ADC_SQR1_SQ16_2 (0x04U << ADC_SQR1_SQ16_Pos) /*!< 0x00020000 */ 03668 #define ADC_SQR1_SQ16_3 (0x08U << ADC_SQR1_SQ16_Pos) /*!< 0x00040000 */ 03669 #define ADC_SQR1_SQ16_4 (0x10U << ADC_SQR1_SQ16_Pos) /*!< 0x00080000 */ 03670 03671 #define ADC_SQR1_L_Pos (20U) 03672 #define ADC_SQR1_L_Msk (0xFU << ADC_SQR1_L_Pos) /*!< 0x00F00000 */ 03673 #define ADC_SQR1_L ADC_SQR1_L_Msk /*!< ADC group regular sequencer scan length */ 03674 #define ADC_SQR1_L_0 (0x1U << ADC_SQR1_L_Pos) /*!< 0x00100000 */ 03675 #define ADC_SQR1_L_1 (0x2U << ADC_SQR1_L_Pos) /*!< 0x00200000 */ 03676 #define ADC_SQR1_L_2 (0x4U << ADC_SQR1_L_Pos) /*!< 0x00400000 */ 03677 #define ADC_SQR1_L_3 (0x8U << ADC_SQR1_L_Pos) /*!< 0x00800000 */ 03678 03679 /******************* Bit definition for ADC_SQR2 register *******************/ 03680 #define ADC_SQR2_SQ7_Pos (0U) 03681 #define ADC_SQR2_SQ7_Msk (0x1FU << ADC_SQR2_SQ7_Pos) /*!< 0x0000001F */ 03682 #define ADC_SQR2_SQ7 ADC_SQR2_SQ7_Msk /*!< ADC group regular sequencer rank 7 */ 03683 #define ADC_SQR2_SQ7_0 (0x01U << ADC_SQR2_SQ7_Pos) /*!< 0x00000001 */ 03684 #define ADC_SQR2_SQ7_1 (0x02U << ADC_SQR2_SQ7_Pos) /*!< 0x00000002 */ 03685 #define ADC_SQR2_SQ7_2 (0x04U << ADC_SQR2_SQ7_Pos) /*!< 0x00000004 */ 03686 #define ADC_SQR2_SQ7_3 (0x08U << ADC_SQR2_SQ7_Pos) /*!< 0x00000008 */ 03687 #define ADC_SQR2_SQ7_4 (0x10U << ADC_SQR2_SQ7_Pos) /*!< 0x00000010 */ 03688 03689 #define ADC_SQR2_SQ8_Pos (5U) 03690 #define ADC_SQR2_SQ8_Msk (0x1FU << ADC_SQR2_SQ8_Pos) /*!< 0x000003E0 */ 03691 #define ADC_SQR2_SQ8 ADC_SQR2_SQ8_Msk /*!< ADC group regular sequencer rank 8 */ 03692 #define ADC_SQR2_SQ8_0 (0x01U << ADC_SQR2_SQ8_Pos) /*!< 0x00000020 */ 03693 #define ADC_SQR2_SQ8_1 (0x02U << ADC_SQR2_SQ8_Pos) /*!< 0x00000040 */ 03694 #define ADC_SQR2_SQ8_2 (0x04U << ADC_SQR2_SQ8_Pos) /*!< 0x00000080 */ 03695 #define ADC_SQR2_SQ8_3 (0x08U << ADC_SQR2_SQ8_Pos) /*!< 0x00000100 */ 03696 #define ADC_SQR2_SQ8_4 (0x10U << ADC_SQR2_SQ8_Pos) /*!< 0x00000200 */ 03697 03698 #define ADC_SQR2_SQ9_Pos (10U) 03699 #define ADC_SQR2_SQ9_Msk (0x1FU << ADC_SQR2_SQ9_Pos) /*!< 0x00007C00 */ 03700 #define ADC_SQR2_SQ9 ADC_SQR2_SQ9_Msk /*!< ADC group regular sequencer rank 9 */ 03701 #define ADC_SQR2_SQ9_0 (0x01U << ADC_SQR2_SQ9_Pos) /*!< 0x00000400 */ 03702 #define ADC_SQR2_SQ9_1 (0x02U << ADC_SQR2_SQ9_Pos) /*!< 0x00000800 */ 03703 #define ADC_SQR2_SQ9_2 (0x04U << ADC_SQR2_SQ9_Pos) /*!< 0x00001000 */ 03704 #define ADC_SQR2_SQ9_3 (0x08U << ADC_SQR2_SQ9_Pos) /*!< 0x00002000 */ 03705 #define ADC_SQR2_SQ9_4 (0x10U << ADC_SQR2_SQ9_Pos) /*!< 0x00004000 */ 03706 03707 #define ADC_SQR2_SQ10_Pos (15U) 03708 #define ADC_SQR2_SQ10_Msk (0x1FU << ADC_SQR2_SQ10_Pos) /*!< 0x000F8000 */ 03709 #define ADC_SQR2_SQ10 ADC_SQR2_SQ10_Msk /*!< ADC group regular sequencer rank 10 */ 03710 #define ADC_SQR2_SQ10_0 (0x01U << ADC_SQR2_SQ10_Pos) /*!< 0x00008000 */ 03711 #define ADC_SQR2_SQ10_1 (0x02U << ADC_SQR2_SQ10_Pos) /*!< 0x00010000 */ 03712 #define ADC_SQR2_SQ10_2 (0x04U << ADC_SQR2_SQ10_Pos) /*!< 0x00020000 */ 03713 #define ADC_SQR2_SQ10_3 (0x08U << ADC_SQR2_SQ10_Pos) /*!< 0x00040000 */ 03714 #define ADC_SQR2_SQ10_4 (0x10U << ADC_SQR2_SQ10_Pos) /*!< 0x00080000 */ 03715 03716 #define ADC_SQR2_SQ11_Pos (20U) 03717 #define ADC_SQR2_SQ11_Msk (0x1FU << ADC_SQR2_SQ11_Pos) /*!< 0x01F00000 */ 03718 #define ADC_SQR2_SQ11 ADC_SQR2_SQ11_Msk /*!< ADC group regular sequencer rank 1 */ 03719 #define ADC_SQR2_SQ11_0 (0x01U << ADC_SQR2_SQ11_Pos) /*!< 0x00100000 */ 03720 #define ADC_SQR2_SQ11_1 (0x02U << ADC_SQR2_SQ11_Pos) /*!< 0x00200000 */ 03721 #define ADC_SQR2_SQ11_2 (0x04U << ADC_SQR2_SQ11_Pos) /*!< 0x00400000 */ 03722 #define ADC_SQR2_SQ11_3 (0x08U << ADC_SQR2_SQ11_Pos) /*!< 0x00800000 */ 03723 #define ADC_SQR2_SQ11_4 (0x10U << ADC_SQR2_SQ11_Pos) /*!< 0x01000000 */ 03724 03725 #define ADC_SQR2_SQ12_Pos (25U) 03726 #define ADC_SQR2_SQ12_Msk (0x1FU << ADC_SQR2_SQ12_Pos) /*!< 0x3E000000 */ 03727 #define ADC_SQR2_SQ12 ADC_SQR2_SQ12_Msk /*!< ADC group regular sequencer rank 12 */ 03728 #define ADC_SQR2_SQ12_0 (0x01U << ADC_SQR2_SQ12_Pos) /*!< 0x02000000 */ 03729 #define ADC_SQR2_SQ12_1 (0x02U << ADC_SQR2_SQ12_Pos) /*!< 0x04000000 */ 03730 #define ADC_SQR2_SQ12_2 (0x04U << ADC_SQR2_SQ12_Pos) /*!< 0x08000000 */ 03731 #define ADC_SQR2_SQ12_3 (0x08U << ADC_SQR2_SQ12_Pos) /*!< 0x10000000 */ 03732 #define ADC_SQR2_SQ12_4 (0x10U << ADC_SQR2_SQ12_Pos) /*!< 0x20000000 */ 03733 03734 /******************* Bit definition for ADC_SQR3 register *******************/ 03735 #define ADC_SQR3_SQ1_Pos (0U) 03736 #define ADC_SQR3_SQ1_Msk (0x1FU << ADC_SQR3_SQ1_Pos) /*!< 0x0000001F */ 03737 #define ADC_SQR3_SQ1 ADC_SQR3_SQ1_Msk /*!< ADC group regular sequencer rank 1 */ 03738 #define ADC_SQR3_SQ1_0 (0x01U << ADC_SQR3_SQ1_Pos) /*!< 0x00000001 */ 03739 #define ADC_SQR3_SQ1_1 (0x02U << ADC_SQR3_SQ1_Pos) /*!< 0x00000002 */ 03740 #define ADC_SQR3_SQ1_2 (0x04U << ADC_SQR3_SQ1_Pos) /*!< 0x00000004 */ 03741 #define ADC_SQR3_SQ1_3 (0x08U << ADC_SQR3_SQ1_Pos) /*!< 0x00000008 */ 03742 #define ADC_SQR3_SQ1_4 (0x10U << ADC_SQR3_SQ1_Pos) /*!< 0x00000010 */ 03743 03744 #define ADC_SQR3_SQ2_Pos (5U) 03745 #define ADC_SQR3_SQ2_Msk (0x1FU << ADC_SQR3_SQ2_Pos) /*!< 0x000003E0 */ 03746 #define ADC_SQR3_SQ2 ADC_SQR3_SQ2_Msk /*!< ADC group regular sequencer rank 2 */ 03747 #define ADC_SQR3_SQ2_0 (0x01U << ADC_SQR3_SQ2_Pos) /*!< 0x00000020 */ 03748 #define ADC_SQR3_SQ2_1 (0x02U << ADC_SQR3_SQ2_Pos) /*!< 0x00000040 */ 03749 #define ADC_SQR3_SQ2_2 (0x04U << ADC_SQR3_SQ2_Pos) /*!< 0x00000080 */ 03750 #define ADC_SQR3_SQ2_3 (0x08U << ADC_SQR3_SQ2_Pos) /*!< 0x00000100 */ 03751 #define ADC_SQR3_SQ2_4 (0x10U << ADC_SQR3_SQ2_Pos) /*!< 0x00000200 */ 03752 03753 #define ADC_SQR3_SQ3_Pos (10U) 03754 #define ADC_SQR3_SQ3_Msk (0x1FU << ADC_SQR3_SQ3_Pos) /*!< 0x00007C00 */ 03755 #define ADC_SQR3_SQ3 ADC_SQR3_SQ3_Msk /*!< ADC group regular sequencer rank 3 */ 03756 #define ADC_SQR3_SQ3_0 (0x01U << ADC_SQR3_SQ3_Pos) /*!< 0x00000400 */ 03757 #define ADC_SQR3_SQ3_1 (0x02U << ADC_SQR3_SQ3_Pos) /*!< 0x00000800 */ 03758 #define ADC_SQR3_SQ3_2 (0x04U << ADC_SQR3_SQ3_Pos) /*!< 0x00001000 */ 03759 #define ADC_SQR3_SQ3_3 (0x08U << ADC_SQR3_SQ3_Pos) /*!< 0x00002000 */ 03760 #define ADC_SQR3_SQ3_4 (0x10U << ADC_SQR3_SQ3_Pos) /*!< 0x00004000 */ 03761 03762 #define ADC_SQR3_SQ4_Pos (15U) 03763 #define ADC_SQR3_SQ4_Msk (0x1FU << ADC_SQR3_SQ4_Pos) /*!< 0x000F8000 */ 03764 #define ADC_SQR3_SQ4 ADC_SQR3_SQ4_Msk /*!< ADC group regular sequencer rank 4 */ 03765 #define ADC_SQR3_SQ4_0 (0x01U << ADC_SQR3_SQ4_Pos) /*!< 0x00008000 */ 03766 #define ADC_SQR3_SQ4_1 (0x02U << ADC_SQR3_SQ4_Pos) /*!< 0x00010000 */ 03767 #define ADC_SQR3_SQ4_2 (0x04U << ADC_SQR3_SQ4_Pos) /*!< 0x00020000 */ 03768 #define ADC_SQR3_SQ4_3 (0x08U << ADC_SQR3_SQ4_Pos) /*!< 0x00040000 */ 03769 #define ADC_SQR3_SQ4_4 (0x10U << ADC_SQR3_SQ4_Pos) /*!< 0x00080000 */ 03770 03771 #define ADC_SQR3_SQ5_Pos (20U) 03772 #define ADC_SQR3_SQ5_Msk (0x1FU << ADC_SQR3_SQ5_Pos) /*!< 0x01F00000 */ 03773 #define ADC_SQR3_SQ5 ADC_SQR3_SQ5_Msk /*!< ADC group regular sequencer rank 5 */ 03774 #define ADC_SQR3_SQ5_0 (0x01U << ADC_SQR3_SQ5_Pos) /*!< 0x00100000 */ 03775 #define ADC_SQR3_SQ5_1 (0x02U << ADC_SQR3_SQ5_Pos) /*!< 0x00200000 */ 03776 #define ADC_SQR3_SQ5_2 (0x04U << ADC_SQR3_SQ5_Pos) /*!< 0x00400000 */ 03777 #define ADC_SQR3_SQ5_3 (0x08U << ADC_SQR3_SQ5_Pos) /*!< 0x00800000 */ 03778 #define ADC_SQR3_SQ5_4 (0x10U << ADC_SQR3_SQ5_Pos) /*!< 0x01000000 */ 03779 03780 #define ADC_SQR3_SQ6_Pos (25U) 03781 #define ADC_SQR3_SQ6_Msk (0x1FU << ADC_SQR3_SQ6_Pos) /*!< 0x3E000000 */ 03782 #define ADC_SQR3_SQ6 ADC_SQR3_SQ6_Msk /*!< ADC group regular sequencer rank 6 */ 03783 #define ADC_SQR3_SQ6_0 (0x01U << ADC_SQR3_SQ6_Pos) /*!< 0x02000000 */ 03784 #define ADC_SQR3_SQ6_1 (0x02U << ADC_SQR3_SQ6_Pos) /*!< 0x04000000 */ 03785 #define ADC_SQR3_SQ6_2 (0x04U << ADC_SQR3_SQ6_Pos) /*!< 0x08000000 */ 03786 #define ADC_SQR3_SQ6_3 (0x08U << ADC_SQR3_SQ6_Pos) /*!< 0x10000000 */ 03787 #define ADC_SQR3_SQ6_4 (0x10U << ADC_SQR3_SQ6_Pos) /*!< 0x20000000 */ 03788 03789 /******************* Bit definition for ADC_JSQR register *******************/ 03790 #define ADC_JSQR_JSQ1_Pos (0U) 03791 #define ADC_JSQR_JSQ1_Msk (0x1FU << ADC_JSQR_JSQ1_Pos) /*!< 0x0000001F */ 03792 #define ADC_JSQR_JSQ1 ADC_JSQR_JSQ1_Msk /*!< ADC group injected sequencer rank 1 */ 03793 #define ADC_JSQR_JSQ1_0 (0x01U << ADC_JSQR_JSQ1_Pos) /*!< 0x00000001 */ 03794 #define ADC_JSQR_JSQ1_1 (0x02U << ADC_JSQR_JSQ1_Pos) /*!< 0x00000002 */ 03795 #define ADC_JSQR_JSQ1_2 (0x04U << ADC_JSQR_JSQ1_Pos) /*!< 0x00000004 */ 03796 #define ADC_JSQR_JSQ1_3 (0x08U << ADC_JSQR_JSQ1_Pos) /*!< 0x00000008 */ 03797 #define ADC_JSQR_JSQ1_4 (0x10U << ADC_JSQR_JSQ1_Pos) /*!< 0x00000010 */ 03798 03799 #define ADC_JSQR_JSQ2_Pos (5U) 03800 #define ADC_JSQR_JSQ2_Msk (0x1FU << ADC_JSQR_JSQ2_Pos) /*!< 0x000003E0 */ 03801 #define ADC_JSQR_JSQ2 ADC_JSQR_JSQ2_Msk /*!< ADC group injected sequencer rank 2 */ 03802 #define ADC_JSQR_JSQ2_0 (0x01U << ADC_JSQR_JSQ2_Pos) /*!< 0x00000020 */ 03803 #define ADC_JSQR_JSQ2_1 (0x02U << ADC_JSQR_JSQ2_Pos) /*!< 0x00000040 */ 03804 #define ADC_JSQR_JSQ2_2 (0x04U << ADC_JSQR_JSQ2_Pos) /*!< 0x00000080 */ 03805 #define ADC_JSQR_JSQ2_3 (0x08U << ADC_JSQR_JSQ2_Pos) /*!< 0x00000100 */ 03806 #define ADC_JSQR_JSQ2_4 (0x10U << ADC_JSQR_JSQ2_Pos) /*!< 0x00000200 */ 03807 03808 #define ADC_JSQR_JSQ3_Pos (10U) 03809 #define ADC_JSQR_JSQ3_Msk (0x1FU << ADC_JSQR_JSQ3_Pos) /*!< 0x00007C00 */ 03810 #define ADC_JSQR_JSQ3 ADC_JSQR_JSQ3_Msk /*!< ADC group injected sequencer rank 3 */ 03811 #define ADC_JSQR_JSQ3_0 (0x01U << ADC_JSQR_JSQ3_Pos) /*!< 0x00000400 */ 03812 #define ADC_JSQR_JSQ3_1 (0x02U << ADC_JSQR_JSQ3_Pos) /*!< 0x00000800 */ 03813 #define ADC_JSQR_JSQ3_2 (0x04U << ADC_JSQR_JSQ3_Pos) /*!< 0x00001000 */ 03814 #define ADC_JSQR_JSQ3_3 (0x08U << ADC_JSQR_JSQ3_Pos) /*!< 0x00002000 */ 03815 #define ADC_JSQR_JSQ3_4 (0x10U << ADC_JSQR_JSQ3_Pos) /*!< 0x00004000 */ 03816 03817 #define ADC_JSQR_JSQ4_Pos (15U) 03818 #define ADC_JSQR_JSQ4_Msk (0x1FU << ADC_JSQR_JSQ4_Pos) /*!< 0x000F8000 */ 03819 #define ADC_JSQR_JSQ4 ADC_JSQR_JSQ4_Msk /*!< ADC group injected sequencer rank 4 */ 03820 #define ADC_JSQR_JSQ4_0 (0x01U << ADC_JSQR_JSQ4_Pos) /*!< 0x00008000 */ 03821 #define ADC_JSQR_JSQ4_1 (0x02U << ADC_JSQR_JSQ4_Pos) /*!< 0x00010000 */ 03822 #define ADC_JSQR_JSQ4_2 (0x04U << ADC_JSQR_JSQ4_Pos) /*!< 0x00020000 */ 03823 #define ADC_JSQR_JSQ4_3 (0x08U << ADC_JSQR_JSQ4_Pos) /*!< 0x00040000 */ 03824 #define ADC_JSQR_JSQ4_4 (0x10U << ADC_JSQR_JSQ4_Pos) /*!< 0x00080000 */ 03825 03826 #define ADC_JSQR_JL_Pos (20U) 03827 #define ADC_JSQR_JL_Msk (0x3U << ADC_JSQR_JL_Pos) /*!< 0x00300000 */ 03828 #define ADC_JSQR_JL ADC_JSQR_JL_Msk /*!< ADC group injected sequencer scan length */ 03829 #define ADC_JSQR_JL_0 (0x1U << ADC_JSQR_JL_Pos) /*!< 0x00100000 */ 03830 #define ADC_JSQR_JL_1 (0x2U << ADC_JSQR_JL_Pos) /*!< 0x00200000 */ 03831 03832 /******************* Bit definition for ADC_JDR1 register *******************/ 03833 #define ADC_JDR1_JDATA_Pos (0U) 03834 #define ADC_JDR1_JDATA_Msk (0xFFFFU << ADC_JDR1_JDATA_Pos) /*!< 0x0000FFFF */ 03835 #define ADC_JDR1_JDATA ADC_JDR1_JDATA_Msk /*!< ADC group injected sequencer rank 1 conversion data */ 03836 03837 /******************* Bit definition for ADC_JDR2 register *******************/ 03838 #define ADC_JDR2_JDATA_Pos (0U) 03839 #define ADC_JDR2_JDATA_Msk (0xFFFFU << ADC_JDR2_JDATA_Pos) /*!< 0x0000FFFF */ 03840 #define ADC_JDR2_JDATA ADC_JDR2_JDATA_Msk /*!< ADC group injected sequencer rank 2 conversion data */ 03841 03842 /******************* Bit definition for ADC_JDR3 register *******************/ 03843 #define ADC_JDR3_JDATA_Pos (0U) 03844 #define ADC_JDR3_JDATA_Msk (0xFFFFU << ADC_JDR3_JDATA_Pos) /*!< 0x0000FFFF */ 03845 #define ADC_JDR3_JDATA ADC_JDR3_JDATA_Msk /*!< ADC group injected sequencer rank 3 conversion data */ 03846 03847 /******************* Bit definition for ADC_JDR4 register *******************/ 03848 #define ADC_JDR4_JDATA_Pos (0U) 03849 #define ADC_JDR4_JDATA_Msk (0xFFFFU << ADC_JDR4_JDATA_Pos) /*!< 0x0000FFFF */ 03850 #define ADC_JDR4_JDATA ADC_JDR4_JDATA_Msk /*!< ADC group injected sequencer rank 4 conversion data */ 03851 03852 /******************** Bit definition for ADC_DR register ********************/ 03853 #define ADC_DR_DATA_Pos (0U) 03854 #define ADC_DR_DATA_Msk (0xFFFFU << ADC_DR_DATA_Pos) /*!< 0x0000FFFF */ 03855 #define ADC_DR_DATA ADC_DR_DATA_Msk /*!< ADC group regular conversion data */ 03856 #define ADC_DR_ADC2DATA_Pos (16U) 03857 #define ADC_DR_ADC2DATA_Msk (0xFFFFU << ADC_DR_ADC2DATA_Pos) /*!< 0xFFFF0000 */ 03858 #define ADC_DR_ADC2DATA ADC_DR_ADC2DATA_Msk /*!< ADC group regular conversion data for ADC slave, in multimode */ 03859 03860 03861 /*****************************************************************************/ 03862 /* */ 03863 /* Timers (TIM) */ 03864 /* */ 03865 /*****************************************************************************/ 03866 /******************* Bit definition for TIM_CR1 register *******************/ 03867 #define TIM_CR1_CEN_Pos (0U) 03868 #define TIM_CR1_CEN_Msk (0x1U << TIM_CR1_CEN_Pos) /*!< 0x00000001 */ 03869 #define TIM_CR1_CEN TIM_CR1_CEN_Msk /*!<Counter enable */ 03870 #define TIM_CR1_UDIS_Pos (1U) 03871 #define TIM_CR1_UDIS_Msk (0x1U << TIM_CR1_UDIS_Pos) /*!< 0x00000002 */ 03872 #define TIM_CR1_UDIS TIM_CR1_UDIS_Msk /*!<Update disable */ 03873 #define TIM_CR1_URS_Pos (2U) 03874 #define TIM_CR1_URS_Msk (0x1U << TIM_CR1_URS_Pos) /*!< 0x00000004 */ 03875 #define TIM_CR1_URS TIM_CR1_URS_Msk /*!<Update request source */ 03876 #define TIM_CR1_OPM_Pos (3U) 03877 #define TIM_CR1_OPM_Msk (0x1U << TIM_CR1_OPM_Pos) /*!< 0x00000008 */ 03878 #define TIM_CR1_OPM TIM_CR1_OPM_Msk /*!<One pulse mode */ 03879 #define TIM_CR1_DIR_Pos (4U) 03880 #define TIM_CR1_DIR_Msk (0x1U << TIM_CR1_DIR_Pos) /*!< 0x00000010 */ 03881 #define TIM_CR1_DIR TIM_CR1_DIR_Msk /*!<Direction */ 03882 03883 #define TIM_CR1_CMS_Pos (5U) 03884 #define TIM_CR1_CMS_Msk (0x3U << TIM_CR1_CMS_Pos) /*!< 0x00000060 */ 03885 #define TIM_CR1_CMS TIM_CR1_CMS_Msk /*!<CMS[1:0] bits (Center-aligned mode selection) */ 03886 #define TIM_CR1_CMS_0 (0x1U << TIM_CR1_CMS_Pos) /*!< 0x00000020 */ 03887 #define TIM_CR1_CMS_1 (0x2U << TIM_CR1_CMS_Pos) /*!< 0x00000040 */ 03888 03889 #define TIM_CR1_ARPE_Pos (7U) 03890 #define TIM_CR1_ARPE_Msk (0x1U << TIM_CR1_ARPE_Pos) /*!< 0x00000080 */ 03891 #define TIM_CR1_ARPE TIM_CR1_ARPE_Msk /*!<Auto-reload preload enable */ 03892 03893 #define TIM_CR1_CKD_Pos (8U) 03894 #define TIM_CR1_CKD_Msk (0x3U << TIM_CR1_CKD_Pos) /*!< 0x00000300 */ 03895 #define TIM_CR1_CKD TIM_CR1_CKD_Msk /*!<CKD[1:0] bits (clock division) */ 03896 #define TIM_CR1_CKD_0 (0x1U << TIM_CR1_CKD_Pos) /*!< 0x00000100 */ 03897 #define TIM_CR1_CKD_1 (0x2U << TIM_CR1_CKD_Pos) /*!< 0x00000200 */ 03898 03899 /******************* Bit definition for TIM_CR2 register *******************/ 03900 #define TIM_CR2_CCPC_Pos (0U) 03901 #define TIM_CR2_CCPC_Msk (0x1U << TIM_CR2_CCPC_Pos) /*!< 0x00000001 */ 03902 #define TIM_CR2_CCPC TIM_CR2_CCPC_Msk /*!<Capture/Compare Preloaded Control */ 03903 #define TIM_CR2_CCUS_Pos (2U) 03904 #define TIM_CR2_CCUS_Msk (0x1U << TIM_CR2_CCUS_Pos) /*!< 0x00000004 */ 03905 #define TIM_CR2_CCUS TIM_CR2_CCUS_Msk /*!<Capture/Compare Control Update Selection */ 03906 #define TIM_CR2_CCDS_Pos (3U) 03907 #define TIM_CR2_CCDS_Msk (0x1U << TIM_CR2_CCDS_Pos) /*!< 0x00000008 */ 03908 #define TIM_CR2_CCDS TIM_CR2_CCDS_Msk /*!<Capture/Compare DMA Selection */ 03909 03910 #define TIM_CR2_MMS_Pos (4U) 03911 #define TIM_CR2_MMS_Msk (0x7U << TIM_CR2_MMS_Pos) /*!< 0x00000070 */ 03912 #define TIM_CR2_MMS TIM_CR2_MMS_Msk /*!<MMS[2:0] bits (Master Mode Selection) */ 03913 #define TIM_CR2_MMS_0 (0x1U << TIM_CR2_MMS_Pos) /*!< 0x00000010 */ 03914 #define TIM_CR2_MMS_1 (0x2U << TIM_CR2_MMS_Pos) /*!< 0x00000020 */ 03915 #define TIM_CR2_MMS_2 (0x4U << TIM_CR2_MMS_Pos) /*!< 0x00000040 */ 03916 03917 #define TIM_CR2_TI1S_Pos (7U) 03918 #define TIM_CR2_TI1S_Msk (0x1U << TIM_CR2_TI1S_Pos) /*!< 0x00000080 */ 03919 #define TIM_CR2_TI1S TIM_CR2_TI1S_Msk /*!<TI1 Selection */ 03920 #define TIM_CR2_OIS1_Pos (8U) 03921 #define TIM_CR2_OIS1_Msk (0x1U << TIM_CR2_OIS1_Pos) /*!< 0x00000100 */ 03922 #define TIM_CR2_OIS1 TIM_CR2_OIS1_Msk /*!<Output Idle state 1 (OC1 output) */ 03923 #define TIM_CR2_OIS1N_Pos (9U) 03924 #define TIM_CR2_OIS1N_Msk (0x1U << TIM_CR2_OIS1N_Pos) /*!< 0x00000200 */ 03925 #define TIM_CR2_OIS1N TIM_CR2_OIS1N_Msk /*!<Output Idle state 1 (OC1N output) */ 03926 #define TIM_CR2_OIS2_Pos (10U) 03927 #define TIM_CR2_OIS2_Msk (0x1U << TIM_CR2_OIS2_Pos) /*!< 0x00000400 */ 03928 #define TIM_CR2_OIS2 TIM_CR2_OIS2_Msk /*!<Output Idle state 2 (OC2 output) */ 03929 #define TIM_CR2_OIS2N_Pos (11U) 03930 #define TIM_CR2_OIS2N_Msk (0x1U << TIM_CR2_OIS2N_Pos) /*!< 0x00000800 */ 03931 #define TIM_CR2_OIS2N TIM_CR2_OIS2N_Msk /*!<Output Idle state 2 (OC2N output) */ 03932 #define TIM_CR2_OIS3_Pos (12U) 03933 #define TIM_CR2_OIS3_Msk (0x1U << TIM_CR2_OIS3_Pos) /*!< 0x00001000 */ 03934 #define TIM_CR2_OIS3 TIM_CR2_OIS3_Msk /*!<Output Idle state 3 (OC3 output) */ 03935 #define TIM_CR2_OIS3N_Pos (13U) 03936 #define TIM_CR2_OIS3N_Msk (0x1U << TIM_CR2_OIS3N_Pos) /*!< 0x00002000 */ 03937 #define TIM_CR2_OIS3N TIM_CR2_OIS3N_Msk /*!<Output Idle state 3 (OC3N output) */ 03938 #define TIM_CR2_OIS4_Pos (14U) 03939 #define TIM_CR2_OIS4_Msk (0x1U << TIM_CR2_OIS4_Pos) /*!< 0x00004000 */ 03940 #define TIM_CR2_OIS4 TIM_CR2_OIS4_Msk /*!<Output Idle state 4 (OC4 output) */ 03941 03942 /******************* Bit definition for TIM_SMCR register ******************/ 03943 #define TIM_SMCR_SMS_Pos (0U) 03944 #define TIM_SMCR_SMS_Msk (0x7U << TIM_SMCR_SMS_Pos) /*!< 0x00000007 */ 03945 #define TIM_SMCR_SMS TIM_SMCR_SMS_Msk /*!<SMS[2:0] bits (Slave mode selection) */ 03946 #define TIM_SMCR_SMS_0 (0x1U << TIM_SMCR_SMS_Pos) /*!< 0x00000001 */ 03947 #define TIM_SMCR_SMS_1 (0x2U << TIM_SMCR_SMS_Pos) /*!< 0x00000002 */ 03948 #define TIM_SMCR_SMS_2 (0x4U << TIM_SMCR_SMS_Pos) /*!< 0x00000004 */ 03949 03950 #define TIM_SMCR_OCCS_Pos (3U) 03951 #define TIM_SMCR_OCCS_Msk (0x1U << TIM_SMCR_OCCS_Pos) /*!< 0x00000008 */ 03952 #define TIM_SMCR_OCCS TIM_SMCR_OCCS_Msk /*!< OCREF clear selection */ 03953 03954 #define TIM_SMCR_TS_Pos (4U) 03955 #define TIM_SMCR_TS_Msk (0x7U << TIM_SMCR_TS_Pos) /*!< 0x00000070 */ 03956 #define TIM_SMCR_TS TIM_SMCR_TS_Msk /*!<TS[2:0] bits (Trigger selection) */ 03957 #define TIM_SMCR_TS_0 (0x1U << TIM_SMCR_TS_Pos) /*!< 0x00000010 */ 03958 #define TIM_SMCR_TS_1 (0x2U << TIM_SMCR_TS_Pos) /*!< 0x00000020 */ 03959 #define TIM_SMCR_TS_2 (0x4U << TIM_SMCR_TS_Pos) /*!< 0x00000040 */ 03960 03961 #define TIM_SMCR_MSM_Pos (7U) 03962 #define TIM_SMCR_MSM_Msk (0x1U << TIM_SMCR_MSM_Pos) /*!< 0x00000080 */ 03963 #define TIM_SMCR_MSM TIM_SMCR_MSM_Msk /*!<Master/slave mode */ 03964 03965 #define TIM_SMCR_ETF_Pos (8U) 03966 #define TIM_SMCR_ETF_Msk (0xFU << TIM_SMCR_ETF_Pos) /*!< 0x00000F00 */ 03967 #define TIM_SMCR_ETF TIM_SMCR_ETF_Msk /*!<ETF[3:0] bits (External trigger filter) */ 03968 #define TIM_SMCR_ETF_0 (0x1U << TIM_SMCR_ETF_Pos) /*!< 0x00000100 */ 03969 #define TIM_SMCR_ETF_1 (0x2U << TIM_SMCR_ETF_Pos) /*!< 0x00000200 */ 03970 #define TIM_SMCR_ETF_2 (0x4U << TIM_SMCR_ETF_Pos) /*!< 0x00000400 */ 03971 #define TIM_SMCR_ETF_3 (0x8U << TIM_SMCR_ETF_Pos) /*!< 0x00000800 */ 03972 03973 #define TIM_SMCR_ETPS_Pos (12U) 03974 #define TIM_SMCR_ETPS_Msk (0x3U << TIM_SMCR_ETPS_Pos) /*!< 0x00003000 */ 03975 #define TIM_SMCR_ETPS TIM_SMCR_ETPS_Msk /*!<ETPS[1:0] bits (External trigger prescaler) */ 03976 #define TIM_SMCR_ETPS_0 (0x1U << TIM_SMCR_ETPS_Pos) /*!< 0x00001000 */ 03977 #define TIM_SMCR_ETPS_1 (0x2U << TIM_SMCR_ETPS_Pos) /*!< 0x00002000 */ 03978 03979 #define TIM_SMCR_ECE_Pos (14U) 03980 #define TIM_SMCR_ECE_Msk (0x1U << TIM_SMCR_ECE_Pos) /*!< 0x00004000 */ 03981 #define TIM_SMCR_ECE TIM_SMCR_ECE_Msk /*!<External clock enable */ 03982 #define TIM_SMCR_ETP_Pos (15U) 03983 #define TIM_SMCR_ETP_Msk (0x1U << TIM_SMCR_ETP_Pos) /*!< 0x00008000 */ 03984 #define TIM_SMCR_ETP TIM_SMCR_ETP_Msk /*!<External trigger polarity */ 03985 03986 /******************* Bit definition for TIM_DIER register ******************/ 03987 #define TIM_DIER_UIE_Pos (0U) 03988 #define TIM_DIER_UIE_Msk (0x1U << TIM_DIER_UIE_Pos) /*!< 0x00000001 */ 03989 #define TIM_DIER_UIE TIM_DIER_UIE_Msk /*!<Update interrupt enable */ 03990 #define TIM_DIER_CC1IE_Pos (1U) 03991 #define TIM_DIER_CC1IE_Msk (0x1U << TIM_DIER_CC1IE_Pos) /*!< 0x00000002 */ 03992 #define TIM_DIER_CC1IE TIM_DIER_CC1IE_Msk /*!<Capture/Compare 1 interrupt enable */ 03993 #define TIM_DIER_CC2IE_Pos (2U) 03994 #define TIM_DIER_CC2IE_Msk (0x1U << TIM_DIER_CC2IE_Pos) /*!< 0x00000004 */ 03995 #define TIM_DIER_CC2IE TIM_DIER_CC2IE_Msk /*!<Capture/Compare 2 interrupt enable */ 03996 #define TIM_DIER_CC3IE_Pos (3U) 03997 #define TIM_DIER_CC3IE_Msk (0x1U << TIM_DIER_CC3IE_Pos) /*!< 0x00000008 */ 03998 #define TIM_DIER_CC3IE TIM_DIER_CC3IE_Msk /*!<Capture/Compare 3 interrupt enable */ 03999 #define TIM_DIER_CC4IE_Pos (4U) 04000 #define TIM_DIER_CC4IE_Msk (0x1U << TIM_DIER_CC4IE_Pos) /*!< 0x00000010 */ 04001 #define TIM_DIER_CC4IE TIM_DIER_CC4IE_Msk /*!<Capture/Compare 4 interrupt enable */ 04002 #define TIM_DIER_COMIE_Pos (5U) 04003 #define TIM_DIER_COMIE_Msk (0x1U << TIM_DIER_COMIE_Pos) /*!< 0x00000020 */ 04004 #define TIM_DIER_COMIE TIM_DIER_COMIE_Msk /*!<COM interrupt enable */ 04005 #define TIM_DIER_TIE_Pos (6U) 04006 #define TIM_DIER_TIE_Msk (0x1U << TIM_DIER_TIE_Pos) /*!< 0x00000040 */ 04007 #define TIM_DIER_TIE TIM_DIER_TIE_Msk /*!<Trigger interrupt enable */ 04008 #define TIM_DIER_BIE_Pos (7U) 04009 #define TIM_DIER_BIE_Msk (0x1U << TIM_DIER_BIE_Pos) /*!< 0x00000080 */ 04010 #define TIM_DIER_BIE TIM_DIER_BIE_Msk /*!<Break interrupt enable */ 04011 #define TIM_DIER_UDE_Pos (8U) 04012 #define TIM_DIER_UDE_Msk (0x1U << TIM_DIER_UDE_Pos) /*!< 0x00000100 */ 04013 #define TIM_DIER_UDE TIM_DIER_UDE_Msk /*!<Update DMA request enable */ 04014 #define TIM_DIER_CC1DE_Pos (9U) 04015 #define TIM_DIER_CC1DE_Msk (0x1U << TIM_DIER_CC1DE_Pos) /*!< 0x00000200 */ 04016 #define TIM_DIER_CC1DE TIM_DIER_CC1DE_Msk /*!<Capture/Compare 1 DMA request enable */ 04017 #define TIM_DIER_CC2DE_Pos (10U) 04018 #define TIM_DIER_CC2DE_Msk (0x1U << TIM_DIER_CC2DE_Pos) /*!< 0x00000400 */ 04019 #define TIM_DIER_CC2DE TIM_DIER_CC2DE_Msk /*!<Capture/Compare 2 DMA request enable */ 04020 #define TIM_DIER_CC3DE_Pos (11U) 04021 #define TIM_DIER_CC3DE_Msk (0x1U << TIM_DIER_CC3DE_Pos) /*!< 0x00000800 */ 04022 #define TIM_DIER_CC3DE TIM_DIER_CC3DE_Msk /*!<Capture/Compare 3 DMA request enable */ 04023 #define TIM_DIER_CC4DE_Pos (12U) 04024 #define TIM_DIER_CC4DE_Msk (0x1U << TIM_DIER_CC4DE_Pos) /*!< 0x00001000 */ 04025 #define TIM_DIER_CC4DE TIM_DIER_CC4DE_Msk /*!<Capture/Compare 4 DMA request enable */ 04026 #define TIM_DIER_COMDE_Pos (13U) 04027 #define TIM_DIER_COMDE_Msk (0x1U << TIM_DIER_COMDE_Pos) /*!< 0x00002000 */ 04028 #define TIM_DIER_COMDE TIM_DIER_COMDE_Msk /*!<COM DMA request enable */ 04029 #define TIM_DIER_TDE_Pos (14U) 04030 #define TIM_DIER_TDE_Msk (0x1U << TIM_DIER_TDE_Pos) /*!< 0x00004000 */ 04031 #define TIM_DIER_TDE TIM_DIER_TDE_Msk /*!<Trigger DMA request enable */ 04032 04033 /******************** Bit definition for TIM_SR register *******************/ 04034 #define TIM_SR_UIF_Pos (0U) 04035 #define TIM_SR_UIF_Msk (0x1U << TIM_SR_UIF_Pos) /*!< 0x00000001 */ 04036 #define TIM_SR_UIF TIM_SR_UIF_Msk /*!<Update interrupt Flag */ 04037 #define TIM_SR_CC1IF_Pos (1U) 04038 #define TIM_SR_CC1IF_Msk (0x1U << TIM_SR_CC1IF_Pos) /*!< 0x00000002 */ 04039 #define TIM_SR_CC1IF TIM_SR_CC1IF_Msk /*!<Capture/Compare 1 interrupt Flag */ 04040 #define TIM_SR_CC2IF_Pos (2U) 04041 #define TIM_SR_CC2IF_Msk (0x1U << TIM_SR_CC2IF_Pos) /*!< 0x00000004 */ 04042 #define TIM_SR_CC2IF TIM_SR_CC2IF_Msk /*!<Capture/Compare 2 interrupt Flag */ 04043 #define TIM_SR_CC3IF_Pos (3U) 04044 #define TIM_SR_CC3IF_Msk (0x1U << TIM_SR_CC3IF_Pos) /*!< 0x00000008 */ 04045 #define TIM_SR_CC3IF TIM_SR_CC3IF_Msk /*!<Capture/Compare 3 interrupt Flag */ 04046 #define TIM_SR_CC4IF_Pos (4U) 04047 #define TIM_SR_CC4IF_Msk (0x1U << TIM_SR_CC4IF_Pos) /*!< 0x00000010 */ 04048 #define TIM_SR_CC4IF TIM_SR_CC4IF_Msk /*!<Capture/Compare 4 interrupt Flag */ 04049 #define TIM_SR_COMIF_Pos (5U) 04050 #define TIM_SR_COMIF_Msk (0x1U << TIM_SR_COMIF_Pos) /*!< 0x00000020 */ 04051 #define TIM_SR_COMIF TIM_SR_COMIF_Msk /*!<COM interrupt Flag */ 04052 #define TIM_SR_TIF_Pos (6U) 04053 #define TIM_SR_TIF_Msk (0x1U << TIM_SR_TIF_Pos) /*!< 0x00000040 */ 04054 #define TIM_SR_TIF TIM_SR_TIF_Msk /*!<Trigger interrupt Flag */ 04055 #define TIM_SR_BIF_Pos (7U) 04056 #define TIM_SR_BIF_Msk (0x1U << TIM_SR_BIF_Pos) /*!< 0x00000080 */ 04057 #define TIM_SR_BIF TIM_SR_BIF_Msk /*!<Break interrupt Flag */ 04058 #define TIM_SR_CC1OF_Pos (9U) 04059 #define TIM_SR_CC1OF_Msk (0x1U << TIM_SR_CC1OF_Pos) /*!< 0x00000200 */ 04060 #define TIM_SR_CC1OF TIM_SR_CC1OF_Msk /*!<Capture/Compare 1 Overcapture Flag */ 04061 #define TIM_SR_CC2OF_Pos (10U) 04062 #define TIM_SR_CC2OF_Msk (0x1U << TIM_SR_CC2OF_Pos) /*!< 0x00000400 */ 04063 #define TIM_SR_CC2OF TIM_SR_CC2OF_Msk /*!<Capture/Compare 2 Overcapture Flag */ 04064 #define TIM_SR_CC3OF_Pos (11U) 04065 #define TIM_SR_CC3OF_Msk (0x1U << TIM_SR_CC3OF_Pos) /*!< 0x00000800 */ 04066 #define TIM_SR_CC3OF TIM_SR_CC3OF_Msk /*!<Capture/Compare 3 Overcapture Flag */ 04067 #define TIM_SR_CC4OF_Pos (12U) 04068 #define TIM_SR_CC4OF_Msk (0x1U << TIM_SR_CC4OF_Pos) /*!< 0x00001000 */ 04069 #define TIM_SR_CC4OF TIM_SR_CC4OF_Msk /*!<Capture/Compare 4 Overcapture Flag */ 04070 04071 /******************* Bit definition for TIM_EGR register *******************/ 04072 #define TIM_EGR_UG_Pos (0U) 04073 #define TIM_EGR_UG_Msk (0x1U << TIM_EGR_UG_Pos) /*!< 0x00000001 */ 04074 #define TIM_EGR_UG TIM_EGR_UG_Msk /*!<Update Generation */ 04075 #define TIM_EGR_CC1G_Pos (1U) 04076 #define TIM_EGR_CC1G_Msk (0x1U << TIM_EGR_CC1G_Pos) /*!< 0x00000002 */ 04077 #define TIM_EGR_CC1G TIM_EGR_CC1G_Msk /*!<Capture/Compare 1 Generation */ 04078 #define TIM_EGR_CC2G_Pos (2U) 04079 #define TIM_EGR_CC2G_Msk (0x1U << TIM_EGR_CC2G_Pos) /*!< 0x00000004 */ 04080 #define TIM_EGR_CC2G TIM_EGR_CC2G_Msk /*!<Capture/Compare 2 Generation */ 04081 #define TIM_EGR_CC3G_Pos (3U) 04082 #define TIM_EGR_CC3G_Msk (0x1U << TIM_EGR_CC3G_Pos) /*!< 0x00000008 */ 04083 #define TIM_EGR_CC3G TIM_EGR_CC3G_Msk /*!<Capture/Compare 3 Generation */ 04084 #define TIM_EGR_CC4G_Pos (4U) 04085 #define TIM_EGR_CC4G_Msk (0x1U << TIM_EGR_CC4G_Pos) /*!< 0x00000010 */ 04086 #define TIM_EGR_CC4G TIM_EGR_CC4G_Msk /*!<Capture/Compare 4 Generation */ 04087 #define TIM_EGR_COMG_Pos (5U) 04088 #define TIM_EGR_COMG_Msk (0x1U << TIM_EGR_COMG_Pos) /*!< 0x00000020 */ 04089 #define TIM_EGR_COMG TIM_EGR_COMG_Msk /*!<Capture/Compare Control Update Generation */ 04090 #define TIM_EGR_TG_Pos (6U) 04091 #define TIM_EGR_TG_Msk (0x1U << TIM_EGR_TG_Pos) /*!< 0x00000040 */ 04092 #define TIM_EGR_TG TIM_EGR_TG_Msk /*!<Trigger Generation */ 04093 #define TIM_EGR_BG_Pos (7U) 04094 #define TIM_EGR_BG_Msk (0x1U << TIM_EGR_BG_Pos) /*!< 0x00000080 */ 04095 #define TIM_EGR_BG TIM_EGR_BG_Msk /*!<Break Generation */ 04096 04097 /****************** Bit definition for TIM_CCMR1 register ******************/ 04098 #define TIM_CCMR1_CC1S_Pos (0U) 04099 #define TIM_CCMR1_CC1S_Msk (0x3U << TIM_CCMR1_CC1S_Pos) /*!< 0x00000003 */ 04100 #define TIM_CCMR1_CC1S TIM_CCMR1_CC1S_Msk /*!<CC1S[1:0] bits (Capture/Compare 1 Selection) */ 04101 #define TIM_CCMR1_CC1S_0 (0x1U << TIM_CCMR1_CC1S_Pos) /*!< 0x00000001 */ 04102 #define TIM_CCMR1_CC1S_1 (0x2U << TIM_CCMR1_CC1S_Pos) /*!< 0x00000002 */ 04103 04104 #define TIM_CCMR1_OC1FE_Pos (2U) 04105 #define TIM_CCMR1_OC1FE_Msk (0x1U << TIM_CCMR1_OC1FE_Pos) /*!< 0x00000004 */ 04106 #define TIM_CCMR1_OC1FE TIM_CCMR1_OC1FE_Msk /*!<Output Compare 1 Fast enable */ 04107 #define TIM_CCMR1_OC1PE_Pos (3U) 04108 #define TIM_CCMR1_OC1PE_Msk (0x1U << TIM_CCMR1_OC1PE_Pos) /*!< 0x00000008 */ 04109 #define TIM_CCMR1_OC1PE TIM_CCMR1_OC1PE_Msk /*!<Output Compare 1 Preload enable */ 04110 04111 #define TIM_CCMR1_OC1M_Pos (4U) 04112 #define TIM_CCMR1_OC1M_Msk (0x7U << TIM_CCMR1_OC1M_Pos) /*!< 0x00000070 */ 04113 #define TIM_CCMR1_OC1M TIM_CCMR1_OC1M_Msk /*!<OC1M[2:0] bits (Output Compare 1 Mode) */ 04114 #define TIM_CCMR1_OC1M_0 (0x1U << TIM_CCMR1_OC1M_Pos) /*!< 0x00000010 */ 04115 #define TIM_CCMR1_OC1M_1 (0x2U << TIM_CCMR1_OC1M_Pos) /*!< 0x00000020 */ 04116 #define TIM_CCMR1_OC1M_2 (0x4U << TIM_CCMR1_OC1M_Pos) /*!< 0x00000040 */ 04117 04118 #define TIM_CCMR1_OC1CE_Pos (7U) 04119 #define TIM_CCMR1_OC1CE_Msk (0x1U << TIM_CCMR1_OC1CE_Pos) /*!< 0x00000080 */ 04120 #define TIM_CCMR1_OC1CE TIM_CCMR1_OC1CE_Msk /*!<Output Compare 1Clear Enable */ 04121 04122 #define TIM_CCMR1_CC2S_Pos (8U) 04123 #define TIM_CCMR1_CC2S_Msk (0x3U << TIM_CCMR1_CC2S_Pos) /*!< 0x00000300 */ 04124 #define TIM_CCMR1_CC2S TIM_CCMR1_CC2S_Msk /*!<CC2S[1:0] bits (Capture/Compare 2 Selection) */ 04125 #define TIM_CCMR1_CC2S_0 (0x1U << TIM_CCMR1_CC2S_Pos) /*!< 0x00000100 */ 04126 #define TIM_CCMR1_CC2S_1 (0x2U << TIM_CCMR1_CC2S_Pos) /*!< 0x00000200 */ 04127 04128 #define TIM_CCMR1_OC2FE_Pos (10U) 04129 #define TIM_CCMR1_OC2FE_Msk (0x1U << TIM_CCMR1_OC2FE_Pos) /*!< 0x00000400 */ 04130 #define TIM_CCMR1_OC2FE TIM_CCMR1_OC2FE_Msk /*!<Output Compare 2 Fast enable */ 04131 #define TIM_CCMR1_OC2PE_Pos (11U) 04132 #define TIM_CCMR1_OC2PE_Msk (0x1U << TIM_CCMR1_OC2PE_Pos) /*!< 0x00000800 */ 04133 #define TIM_CCMR1_OC2PE TIM_CCMR1_OC2PE_Msk /*!<Output Compare 2 Preload enable */ 04134 04135 #define TIM_CCMR1_OC2M_Pos (12U) 04136 #define TIM_CCMR1_OC2M_Msk (0x7U << TIM_CCMR1_OC2M_Pos) /*!< 0x00007000 */ 04137 #define TIM_CCMR1_OC2M TIM_CCMR1_OC2M_Msk /*!<OC2M[2:0] bits (Output Compare 2 Mode) */ 04138 #define TIM_CCMR1_OC2M_0 (0x1U << TIM_CCMR1_OC2M_Pos) /*!< 0x00001000 */ 04139 #define TIM_CCMR1_OC2M_1 (0x2U << TIM_CCMR1_OC2M_Pos) /*!< 0x00002000 */ 04140 #define TIM_CCMR1_OC2M_2 (0x4U << TIM_CCMR1_OC2M_Pos) /*!< 0x00004000 */ 04141 04142 #define TIM_CCMR1_OC2CE_Pos (15U) 04143 #define TIM_CCMR1_OC2CE_Msk (0x1U << TIM_CCMR1_OC2CE_Pos) /*!< 0x00008000 */ 04144 #define TIM_CCMR1_OC2CE TIM_CCMR1_OC2CE_Msk /*!<Output Compare 2 Clear Enable */ 04145 04146 /*---------------------------------------------------------------------------*/ 04147 04148 #define TIM_CCMR1_IC1PSC_Pos (2U) 04149 #define TIM_CCMR1_IC1PSC_Msk (0x3U << TIM_CCMR1_IC1PSC_Pos) /*!< 0x0000000C */ 04150 #define TIM_CCMR1_IC1PSC TIM_CCMR1_IC1PSC_Msk /*!<IC1PSC[1:0] bits (Input Capture 1 Prescaler) */ 04151 #define TIM_CCMR1_IC1PSC_0 (0x1U << TIM_CCMR1_IC1PSC_Pos) /*!< 0x00000004 */ 04152 #define TIM_CCMR1_IC1PSC_1 (0x2U << TIM_CCMR1_IC1PSC_Pos) /*!< 0x00000008 */ 04153 04154 #define TIM_CCMR1_IC1F_Pos (4U) 04155 #define TIM_CCMR1_IC1F_Msk (0xFU << TIM_CCMR1_IC1F_Pos) /*!< 0x000000F0 */ 04156 #define TIM_CCMR1_IC1F TIM_CCMR1_IC1F_Msk /*!<IC1F[3:0] bits (Input Capture 1 Filter) */ 04157 #define TIM_CCMR1_IC1F_0 (0x1U << TIM_CCMR1_IC1F_Pos) /*!< 0x00000010 */ 04158 #define TIM_CCMR1_IC1F_1 (0x2U << TIM_CCMR1_IC1F_Pos) /*!< 0x00000020 */ 04159 #define TIM_CCMR1_IC1F_2 (0x4U << TIM_CCMR1_IC1F_Pos) /*!< 0x00000040 */ 04160 #define TIM_CCMR1_IC1F_3 (0x8U << TIM_CCMR1_IC1F_Pos) /*!< 0x00000080 */ 04161 04162 #define TIM_CCMR1_IC2PSC_Pos (10U) 04163 #define TIM_CCMR1_IC2PSC_Msk (0x3U << TIM_CCMR1_IC2PSC_Pos) /*!< 0x00000C00 */ 04164 #define TIM_CCMR1_IC2PSC TIM_CCMR1_IC2PSC_Msk /*!<IC2PSC[1:0] bits (Input Capture 2 Prescaler) */ 04165 #define TIM_CCMR1_IC2PSC_0 (0x1U << TIM_CCMR1_IC2PSC_Pos) /*!< 0x00000400 */ 04166 #define TIM_CCMR1_IC2PSC_1 (0x2U << TIM_CCMR1_IC2PSC_Pos) /*!< 0x00000800 */ 04167 04168 #define TIM_CCMR1_IC2F_Pos (12U) 04169 #define TIM_CCMR1_IC2F_Msk (0xFU << TIM_CCMR1_IC2F_Pos) /*!< 0x0000F000 */ 04170 #define TIM_CCMR1_IC2F TIM_CCMR1_IC2F_Msk /*!<IC2F[3:0] bits (Input Capture 2 Filter) */ 04171 #define TIM_CCMR1_IC2F_0 (0x1U << TIM_CCMR1_IC2F_Pos) /*!< 0x00001000 */ 04172 #define TIM_CCMR1_IC2F_1 (0x2U << TIM_CCMR1_IC2F_Pos) /*!< 0x00002000 */ 04173 #define TIM_CCMR1_IC2F_2 (0x4U << TIM_CCMR1_IC2F_Pos) /*!< 0x00004000 */ 04174 #define TIM_CCMR1_IC2F_3 (0x8U << TIM_CCMR1_IC2F_Pos) /*!< 0x00008000 */ 04175 04176 /****************** Bit definition for TIM_CCMR2 register ******************/ 04177 #define TIM_CCMR2_CC3S_Pos (0U) 04178 #define TIM_CCMR2_CC3S_Msk (0x3U << TIM_CCMR2_CC3S_Pos) /*!< 0x00000003 */ 04179 #define TIM_CCMR2_CC3S TIM_CCMR2_CC3S_Msk /*!<CC3S[1:0] bits (Capture/Compare 3 Selection) */ 04180 #define TIM_CCMR2_CC3S_0 (0x1U << TIM_CCMR2_CC3S_Pos) /*!< 0x00000001 */ 04181 #define TIM_CCMR2_CC3S_1 (0x2U << TIM_CCMR2_CC3S_Pos) /*!< 0x00000002 */ 04182 04183 #define TIM_CCMR2_OC3FE_Pos (2U) 04184 #define TIM_CCMR2_OC3FE_Msk (0x1U << TIM_CCMR2_OC3FE_Pos) /*!< 0x00000004 */ 04185 #define TIM_CCMR2_OC3FE TIM_CCMR2_OC3FE_Msk /*!<Output Compare 3 Fast enable */ 04186 #define TIM_CCMR2_OC3PE_Pos (3U) 04187 #define TIM_CCMR2_OC3PE_Msk (0x1U << TIM_CCMR2_OC3PE_Pos) /*!< 0x00000008 */ 04188 #define TIM_CCMR2_OC3PE TIM_CCMR2_OC3PE_Msk /*!<Output Compare 3 Preload enable */ 04189 04190 #define TIM_CCMR2_OC3M_Pos (4U) 04191 #define TIM_CCMR2_OC3M_Msk (0x7U << TIM_CCMR2_OC3M_Pos) /*!< 0x00000070 */ 04192 #define TIM_CCMR2_OC3M TIM_CCMR2_OC3M_Msk /*!<OC3M[2:0] bits (Output Compare 3 Mode) */ 04193 #define TIM_CCMR2_OC3M_0 (0x1U << TIM_CCMR2_OC3M_Pos) /*!< 0x00000010 */ 04194 #define TIM_CCMR2_OC3M_1 (0x2U << TIM_CCMR2_OC3M_Pos) /*!< 0x00000020 */ 04195 #define TIM_CCMR2_OC3M_2 (0x4U << TIM_CCMR2_OC3M_Pos) /*!< 0x00000040 */ 04196 04197 #define TIM_CCMR2_OC3CE_Pos (7U) 04198 #define TIM_CCMR2_OC3CE_Msk (0x1U << TIM_CCMR2_OC3CE_Pos) /*!< 0x00000080 */ 04199 #define TIM_CCMR2_OC3CE TIM_CCMR2_OC3CE_Msk /*!<Output Compare 3 Clear Enable */ 04200 04201 #define TIM_CCMR2_CC4S_Pos (8U) 04202 #define TIM_CCMR2_CC4S_Msk (0x3U << TIM_CCMR2_CC4S_Pos) /*!< 0x00000300 */ 04203 #define TIM_CCMR2_CC4S TIM_CCMR2_CC4S_Msk /*!<CC4S[1:0] bits (Capture/Compare 4 Selection) */ 04204 #define TIM_CCMR2_CC4S_0 (0x1U << TIM_CCMR2_CC4S_Pos) /*!< 0x00000100 */ 04205 #define TIM_CCMR2_CC4S_1 (0x2U << TIM_CCMR2_CC4S_Pos) /*!< 0x00000200 */ 04206 04207 #define TIM_CCMR2_OC4FE_Pos (10U) 04208 #define TIM_CCMR2_OC4FE_Msk (0x1U << TIM_CCMR2_OC4FE_Pos) /*!< 0x00000400 */ 04209 #define TIM_CCMR2_OC4FE TIM_CCMR2_OC4FE_Msk /*!<Output Compare 4 Fast enable */ 04210 #define TIM_CCMR2_OC4PE_Pos (11U) 04211 #define TIM_CCMR2_OC4PE_Msk (0x1U << TIM_CCMR2_OC4PE_Pos) /*!< 0x00000800 */ 04212 #define TIM_CCMR2_OC4PE TIM_CCMR2_OC4PE_Msk /*!<Output Compare 4 Preload enable */ 04213 04214 #define TIM_CCMR2_OC4M_Pos (12U) 04215 #define TIM_CCMR2_OC4M_Msk (0x7U << TIM_CCMR2_OC4M_Pos) /*!< 0x00007000 */ 04216 #define TIM_CCMR2_OC4M TIM_CCMR2_OC4M_Msk /*!<OC4M[2:0] bits (Output Compare 4 Mode) */ 04217 #define TIM_CCMR2_OC4M_0 (0x1U << TIM_CCMR2_OC4M_Pos) /*!< 0x00001000 */ 04218 #define TIM_CCMR2_OC4M_1 (0x2U << TIM_CCMR2_OC4M_Pos) /*!< 0x00002000 */ 04219 #define TIM_CCMR2_OC4M_2 (0x4U << TIM_CCMR2_OC4M_Pos) /*!< 0x00004000 */ 04220 04221 #define TIM_CCMR2_OC4CE_Pos (15U) 04222 #define TIM_CCMR2_OC4CE_Msk (0x1U << TIM_CCMR2_OC4CE_Pos) /*!< 0x00008000 */ 04223 #define TIM_CCMR2_OC4CE TIM_CCMR2_OC4CE_Msk /*!<Output Compare 4 Clear Enable */ 04224 04225 /*---------------------------------------------------------------------------*/ 04226 04227 #define TIM_CCMR2_IC3PSC_Pos (2U) 04228 #define TIM_CCMR2_IC3PSC_Msk (0x3U << TIM_CCMR2_IC3PSC_Pos) /*!< 0x0000000C */ 04229 #define TIM_CCMR2_IC3PSC TIM_CCMR2_IC3PSC_Msk /*!<IC3PSC[1:0] bits (Input Capture 3 Prescaler) */ 04230 #define TIM_CCMR2_IC3PSC_0 (0x1U << TIM_CCMR2_IC3PSC_Pos) /*!< 0x00000004 */ 04231 #define TIM_CCMR2_IC3PSC_1 (0x2U << TIM_CCMR2_IC3PSC_Pos) /*!< 0x00000008 */ 04232 04233 #define TIM_CCMR2_IC3F_Pos (4U) 04234 #define TIM_CCMR2_IC3F_Msk (0xFU << TIM_CCMR2_IC3F_Pos) /*!< 0x000000F0 */ 04235 #define TIM_CCMR2_IC3F TIM_CCMR2_IC3F_Msk /*!<IC3F[3:0] bits (Input Capture 3 Filter) */ 04236 #define TIM_CCMR2_IC3F_0 (0x1U << TIM_CCMR2_IC3F_Pos) /*!< 0x00000010 */ 04237 #define TIM_CCMR2_IC3F_1 (0x2U << TIM_CCMR2_IC3F_Pos) /*!< 0x00000020 */ 04238 #define TIM_CCMR2_IC3F_2 (0x4U << TIM_CCMR2_IC3F_Pos) /*!< 0x00000040 */ 04239 #define TIM_CCMR2_IC3F_3 (0x8U << TIM_CCMR2_IC3F_Pos) /*!< 0x00000080 */ 04240 04241 #define TIM_CCMR2_IC4PSC_Pos (10U) 04242 #define TIM_CCMR2_IC4PSC_Msk (0x3U << TIM_CCMR2_IC4PSC_Pos) /*!< 0x00000C00 */ 04243 #define TIM_CCMR2_IC4PSC TIM_CCMR2_IC4PSC_Msk /*!<IC4PSC[1:0] bits (Input Capture 4 Prescaler) */ 04244 #define TIM_CCMR2_IC4PSC_0 (0x1U << TIM_CCMR2_IC4PSC_Pos) /*!< 0x00000400 */ 04245 #define TIM_CCMR2_IC4PSC_1 (0x2U << TIM_CCMR2_IC4PSC_Pos) /*!< 0x00000800 */ 04246 04247 #define TIM_CCMR2_IC4F_Pos (12U) 04248 #define TIM_CCMR2_IC4F_Msk (0xFU << TIM_CCMR2_IC4F_Pos) /*!< 0x0000F000 */ 04249 #define TIM_CCMR2_IC4F TIM_CCMR2_IC4F_Msk /*!<IC4F[3:0] bits (Input Capture 4 Filter) */ 04250 #define TIM_CCMR2_IC4F_0 (0x1U << TIM_CCMR2_IC4F_Pos) /*!< 0x00001000 */ 04251 #define TIM_CCMR2_IC4F_1 (0x2U << TIM_CCMR2_IC4F_Pos) /*!< 0x00002000 */ 04252 #define TIM_CCMR2_IC4F_2 (0x4U << TIM_CCMR2_IC4F_Pos) /*!< 0x00004000 */ 04253 #define TIM_CCMR2_IC4F_3 (0x8U << TIM_CCMR2_IC4F_Pos) /*!< 0x00008000 */ 04254 04255 /******************* Bit definition for TIM_CCER register ******************/ 04256 #define TIM_CCER_CC1E_Pos (0U) 04257 #define TIM_CCER_CC1E_Msk (0x1U << TIM_CCER_CC1E_Pos) /*!< 0x00000001 */ 04258 #define TIM_CCER_CC1E TIM_CCER_CC1E_Msk /*!<Capture/Compare 1 output enable */ 04259 #define TIM_CCER_CC1P_Pos (1U) 04260 #define TIM_CCER_CC1P_Msk (0x1U << TIM_CCER_CC1P_Pos) /*!< 0x00000002 */ 04261 #define TIM_CCER_CC1P TIM_CCER_CC1P_Msk /*!<Capture/Compare 1 output Polarity */ 04262 #define TIM_CCER_CC1NE_Pos (2U) 04263 #define TIM_CCER_CC1NE_Msk (0x1U << TIM_CCER_CC1NE_Pos) /*!< 0x00000004 */ 04264 #define TIM_CCER_CC1NE TIM_CCER_CC1NE_Msk /*!<Capture/Compare 1 Complementary output enable */ 04265 #define TIM_CCER_CC1NP_Pos (3U) 04266 #define TIM_CCER_CC1NP_Msk (0x1U << TIM_CCER_CC1NP_Pos) /*!< 0x00000008 */ 04267 #define TIM_CCER_CC1NP TIM_CCER_CC1NP_Msk /*!<Capture/Compare 1 Complementary output Polarity */ 04268 #define TIM_CCER_CC2E_Pos (4U) 04269 #define TIM_CCER_CC2E_Msk (0x1U << TIM_CCER_CC2E_Pos) /*!< 0x00000010 */ 04270 #define TIM_CCER_CC2E TIM_CCER_CC2E_Msk /*!<Capture/Compare 2 output enable */ 04271 #define TIM_CCER_CC2P_Pos (5U) 04272 #define TIM_CCER_CC2P_Msk (0x1U << TIM_CCER_CC2P_Pos) /*!< 0x00000020 */ 04273 #define TIM_CCER_CC2P TIM_CCER_CC2P_Msk /*!<Capture/Compare 2 output Polarity */ 04274 #define TIM_CCER_CC2NE_Pos (6U) 04275 #define TIM_CCER_CC2NE_Msk (0x1U << TIM_CCER_CC2NE_Pos) /*!< 0x00000040 */ 04276 #define TIM_CCER_CC2NE TIM_CCER_CC2NE_Msk /*!<Capture/Compare 2 Complementary output enable */ 04277 #define TIM_CCER_CC2NP_Pos (7U) 04278 #define TIM_CCER_CC2NP_Msk (0x1U << TIM_CCER_CC2NP_Pos) /*!< 0x00000080 */ 04279 #define TIM_CCER_CC2NP TIM_CCER_CC2NP_Msk /*!<Capture/Compare 2 Complementary output Polarity */ 04280 #define TIM_CCER_CC3E_Pos (8U) 04281 #define TIM_CCER_CC3E_Msk (0x1U << TIM_CCER_CC3E_Pos) /*!< 0x00000100 */ 04282 #define TIM_CCER_CC3E TIM_CCER_CC3E_Msk /*!<Capture/Compare 3 output enable */ 04283 #define TIM_CCER_CC3P_Pos (9U) 04284 #define TIM_CCER_CC3P_Msk (0x1U << TIM_CCER_CC3P_Pos) /*!< 0x00000200 */ 04285 #define TIM_CCER_CC3P TIM_CCER_CC3P_Msk /*!<Capture/Compare 3 output Polarity */ 04286 #define TIM_CCER_CC3NE_Pos (10U) 04287 #define TIM_CCER_CC3NE_Msk (0x1U << TIM_CCER_CC3NE_Pos) /*!< 0x00000400 */ 04288 #define TIM_CCER_CC3NE TIM_CCER_CC3NE_Msk /*!<Capture/Compare 3 Complementary output enable */ 04289 #define TIM_CCER_CC3NP_Pos (11U) 04290 #define TIM_CCER_CC3NP_Msk (0x1U << TIM_CCER_CC3NP_Pos) /*!< 0x00000800 */ 04291 #define TIM_CCER_CC3NP TIM_CCER_CC3NP_Msk /*!<Capture/Compare 3 Complementary output Polarity */ 04292 #define TIM_CCER_CC4E_Pos (12U) 04293 #define TIM_CCER_CC4E_Msk (0x1U << TIM_CCER_CC4E_Pos) /*!< 0x00001000 */ 04294 #define TIM_CCER_CC4E TIM_CCER_CC4E_Msk /*!<Capture/Compare 4 output enable */ 04295 #define TIM_CCER_CC4P_Pos (13U) 04296 #define TIM_CCER_CC4P_Msk (0x1U << TIM_CCER_CC4P_Pos) /*!< 0x00002000 */ 04297 #define TIM_CCER_CC4P TIM_CCER_CC4P_Msk /*!<Capture/Compare 4 output Polarity */ 04298 #define TIM_CCER_CC4NP_Pos (15U) 04299 #define TIM_CCER_CC4NP_Msk (0x1U << TIM_CCER_CC4NP_Pos) /*!< 0x00008000 */ 04300 #define TIM_CCER_CC4NP TIM_CCER_CC4NP_Msk /*!<Capture/Compare 4 Complementary output Polarity */ 04301 04302 /******************* Bit definition for TIM_CNT register *******************/ 04303 #define TIM_CNT_CNT_Pos (0U) 04304 #define TIM_CNT_CNT_Msk (0xFFFFFFFFU << TIM_CNT_CNT_Pos) /*!< 0xFFFFFFFF */ 04305 #define TIM_CNT_CNT TIM_CNT_CNT_Msk /*!<Counter Value */ 04306 04307 /******************* Bit definition for TIM_PSC register *******************/ 04308 #define TIM_PSC_PSC_Pos (0U) 04309 #define TIM_PSC_PSC_Msk (0xFFFFU << TIM_PSC_PSC_Pos) /*!< 0x0000FFFF */ 04310 #define TIM_PSC_PSC TIM_PSC_PSC_Msk /*!<Prescaler Value */ 04311 04312 /******************* Bit definition for TIM_ARR register *******************/ 04313 #define TIM_ARR_ARR_Pos (0U) 04314 #define TIM_ARR_ARR_Msk (0xFFFFFFFFU << TIM_ARR_ARR_Pos) /*!< 0xFFFFFFFF */ 04315 #define TIM_ARR_ARR TIM_ARR_ARR_Msk /*!<actual auto-reload Value */ 04316 04317 /******************* Bit definition for TIM_RCR register *******************/ 04318 #define TIM_RCR_REP_Pos (0U) 04319 #define TIM_RCR_REP_Msk (0xFFU << TIM_RCR_REP_Pos) /*!< 0x000000FF */ 04320 #define TIM_RCR_REP TIM_RCR_REP_Msk /*!<Repetition Counter Value */ 04321 04322 /******************* Bit definition for TIM_CCR1 register ******************/ 04323 #define TIM_CCR1_CCR1_Pos (0U) 04324 #define TIM_CCR1_CCR1_Msk (0xFFFFU << TIM_CCR1_CCR1_Pos) /*!< 0x0000FFFF */ 04325 #define TIM_CCR1_CCR1 TIM_CCR1_CCR1_Msk /*!<Capture/Compare 1 Value */ 04326 04327 /******************* Bit definition for TIM_CCR2 register ******************/ 04328 #define TIM_CCR2_CCR2_Pos (0U) 04329 #define TIM_CCR2_CCR2_Msk (0xFFFFU << TIM_CCR2_CCR2_Pos) /*!< 0x0000FFFF */ 04330 #define TIM_CCR2_CCR2 TIM_CCR2_CCR2_Msk /*!<Capture/Compare 2 Value */ 04331 04332 /******************* Bit definition for TIM_CCR3 register ******************/ 04333 #define TIM_CCR3_CCR3_Pos (0U) 04334 #define TIM_CCR3_CCR3_Msk (0xFFFFU << TIM_CCR3_CCR3_Pos) /*!< 0x0000FFFF */ 04335 #define TIM_CCR3_CCR3 TIM_CCR3_CCR3_Msk /*!<Capture/Compare 3 Value */ 04336 04337 /******************* Bit definition for TIM_CCR4 register ******************/ 04338 #define TIM_CCR4_CCR4_Pos (0U) 04339 #define TIM_CCR4_CCR4_Msk (0xFFFFU << TIM_CCR4_CCR4_Pos) /*!< 0x0000FFFF */ 04340 #define TIM_CCR4_CCR4 TIM_CCR4_CCR4_Msk /*!<Capture/Compare 4 Value */ 04341 04342 /******************* Bit definition for TIM_BDTR register ******************/ 04343 #define TIM_BDTR_DTG_Pos (0U) 04344 #define TIM_BDTR_DTG_Msk (0xFFU << TIM_BDTR_DTG_Pos) /*!< 0x000000FF */ 04345 #define TIM_BDTR_DTG TIM_BDTR_DTG_Msk /*!<DTG[0:7] bits (Dead-Time Generator set-up) */ 04346 #define TIM_BDTR_DTG_0 (0x01U << TIM_BDTR_DTG_Pos) /*!< 0x00000001 */ 04347 #define TIM_BDTR_DTG_1 (0x02U << TIM_BDTR_DTG_Pos) /*!< 0x00000002 */ 04348 #define TIM_BDTR_DTG_2 (0x04U << TIM_BDTR_DTG_Pos) /*!< 0x00000004 */ 04349 #define TIM_BDTR_DTG_3 (0x08U << TIM_BDTR_DTG_Pos) /*!< 0x00000008 */ 04350 #define TIM_BDTR_DTG_4 (0x10U << TIM_BDTR_DTG_Pos) /*!< 0x00000010 */ 04351 #define TIM_BDTR_DTG_5 (0x20U << TIM_BDTR_DTG_Pos) /*!< 0x00000020 */ 04352 #define TIM_BDTR_DTG_6 (0x40U << TIM_BDTR_DTG_Pos) /*!< 0x00000040 */ 04353 #define TIM_BDTR_DTG_7 (0x80U << TIM_BDTR_DTG_Pos) /*!< 0x00000080 */ 04354 04355 #define TIM_BDTR_LOCK_Pos (8U) 04356 #define TIM_BDTR_LOCK_Msk (0x3U << TIM_BDTR_LOCK_Pos) /*!< 0x00000300 */ 04357 #define TIM_BDTR_LOCK TIM_BDTR_LOCK_Msk /*!<LOCK[1:0] bits (Lock Configuration) */ 04358 #define TIM_BDTR_LOCK_0 (0x1U << TIM_BDTR_LOCK_Pos) /*!< 0x00000100 */ 04359 #define TIM_BDTR_LOCK_1 (0x2U << TIM_BDTR_LOCK_Pos) /*!< 0x00000200 */ 04360 04361 #define TIM_BDTR_OSSI_Pos (10U) 04362 #define TIM_BDTR_OSSI_Msk (0x1U << TIM_BDTR_OSSI_Pos) /*!< 0x00000400 */ 04363 #define TIM_BDTR_OSSI TIM_BDTR_OSSI_Msk /*!<Off-State Selection for Idle mode */ 04364 #define TIM_BDTR_OSSR_Pos (11U) 04365 #define TIM_BDTR_OSSR_Msk (0x1U << TIM_BDTR_OSSR_Pos) /*!< 0x00000800 */ 04366 #define TIM_BDTR_OSSR TIM_BDTR_OSSR_Msk /*!<Off-State Selection for Run mode */ 04367 #define TIM_BDTR_BKE_Pos (12U) 04368 #define TIM_BDTR_BKE_Msk (0x1U << TIM_BDTR_BKE_Pos) /*!< 0x00001000 */ 04369 #define TIM_BDTR_BKE TIM_BDTR_BKE_Msk /*!<Break enable */ 04370 #define TIM_BDTR_BKP_Pos (13U) 04371 #define TIM_BDTR_BKP_Msk (0x1U << TIM_BDTR_BKP_Pos) /*!< 0x00002000 */ 04372 #define TIM_BDTR_BKP TIM_BDTR_BKP_Msk /*!<Break Polarity */ 04373 #define TIM_BDTR_AOE_Pos (14U) 04374 #define TIM_BDTR_AOE_Msk (0x1U << TIM_BDTR_AOE_Pos) /*!< 0x00004000 */ 04375 #define TIM_BDTR_AOE TIM_BDTR_AOE_Msk /*!<Automatic Output enable */ 04376 #define TIM_BDTR_MOE_Pos (15U) 04377 #define TIM_BDTR_MOE_Msk (0x1U << TIM_BDTR_MOE_Pos) /*!< 0x00008000 */ 04378 #define TIM_BDTR_MOE TIM_BDTR_MOE_Msk /*!<Main Output enable */ 04379 04380 /******************* Bit definition for TIM_DCR register *******************/ 04381 #define TIM_DCR_DBA_Pos (0U) 04382 #define TIM_DCR_DBA_Msk (0x1FU << TIM_DCR_DBA_Pos) /*!< 0x0000001F */ 04383 #define TIM_DCR_DBA TIM_DCR_DBA_Msk /*!<DBA[4:0] bits (DMA Base Address) */ 04384 #define TIM_DCR_DBA_0 (0x01U << TIM_DCR_DBA_Pos) /*!< 0x00000001 */ 04385 #define TIM_DCR_DBA_1 (0x02U << TIM_DCR_DBA_Pos) /*!< 0x00000002 */ 04386 #define TIM_DCR_DBA_2 (0x04U << TIM_DCR_DBA_Pos) /*!< 0x00000004 */ 04387 #define TIM_DCR_DBA_3 (0x08U << TIM_DCR_DBA_Pos) /*!< 0x00000008 */ 04388 #define TIM_DCR_DBA_4 (0x10U << TIM_DCR_DBA_Pos) /*!< 0x00000010 */ 04389 04390 #define TIM_DCR_DBL_Pos (8U) 04391 #define TIM_DCR_DBL_Msk (0x1FU << TIM_DCR_DBL_Pos) /*!< 0x00001F00 */ 04392 #define TIM_DCR_DBL TIM_DCR_DBL_Msk /*!<DBL[4:0] bits (DMA Burst Length) */ 04393 #define TIM_DCR_DBL_0 (0x01U << TIM_DCR_DBL_Pos) /*!< 0x00000100 */ 04394 #define TIM_DCR_DBL_1 (0x02U << TIM_DCR_DBL_Pos) /*!< 0x00000200 */ 04395 #define TIM_DCR_DBL_2 (0x04U << TIM_DCR_DBL_Pos) /*!< 0x00000400 */ 04396 #define TIM_DCR_DBL_3 (0x08U << TIM_DCR_DBL_Pos) /*!< 0x00000800 */ 04397 #define TIM_DCR_DBL_4 (0x10U << TIM_DCR_DBL_Pos) /*!< 0x00001000 */ 04398 04399 /******************* Bit definition for TIM_DMAR register ******************/ 04400 #define TIM_DMAR_DMAB_Pos (0U) 04401 #define TIM_DMAR_DMAB_Msk (0xFFFFU << TIM_DMAR_DMAB_Pos) /*!< 0x0000FFFF */ 04402 #define TIM_DMAR_DMAB TIM_DMAR_DMAB_Msk /*!<DMA register for burst accesses */ 04403 04404 /******************* Bit definition for TIM_OR register ********************/ 04405 04406 /******************************************************************************/ 04407 /* */ 04408 /* Real-Time Clock */ 04409 /* */ 04410 /******************************************************************************/ 04411 04412 /******************* Bit definition for RTC_CRH register ********************/ 04413 #define RTC_CRH_SECIE_Pos (0U) 04414 #define RTC_CRH_SECIE_Msk (0x1U << RTC_CRH_SECIE_Pos) /*!< 0x00000001 */ 04415 #define RTC_CRH_SECIE RTC_CRH_SECIE_Msk /*!< Second Interrupt Enable */ 04416 #define RTC_CRH_ALRIE_Pos (1U) 04417 #define RTC_CRH_ALRIE_Msk (0x1U << RTC_CRH_ALRIE_Pos) /*!< 0x00000002 */ 04418 #define RTC_CRH_ALRIE RTC_CRH_ALRIE_Msk /*!< Alarm Interrupt Enable */ 04419 #define RTC_CRH_OWIE_Pos (2U) 04420 #define RTC_CRH_OWIE_Msk (0x1U << RTC_CRH_OWIE_Pos) /*!< 0x00000004 */ 04421 #define RTC_CRH_OWIE RTC_CRH_OWIE_Msk /*!< OverfloW Interrupt Enable */ 04422 04423 /******************* Bit definition for RTC_CRL register ********************/ 04424 #define RTC_CRL_SECF_Pos (0U) 04425 #define RTC_CRL_SECF_Msk (0x1U << RTC_CRL_SECF_Pos) /*!< 0x00000001 */ 04426 #define RTC_CRL_SECF RTC_CRL_SECF_Msk /*!< Second Flag */ 04427 #define RTC_CRL_ALRF_Pos (1U) 04428 #define RTC_CRL_ALRF_Msk (0x1U << RTC_CRL_ALRF_Pos) /*!< 0x00000002 */ 04429 #define RTC_CRL_ALRF RTC_CRL_ALRF_Msk /*!< Alarm Flag */ 04430 #define RTC_CRL_OWF_Pos (2U) 04431 #define RTC_CRL_OWF_Msk (0x1U << RTC_CRL_OWF_Pos) /*!< 0x00000004 */ 04432 #define RTC_CRL_OWF RTC_CRL_OWF_Msk /*!< OverfloW Flag */ 04433 #define RTC_CRL_RSF_Pos (3U) 04434 #define RTC_CRL_RSF_Msk (0x1U << RTC_CRL_RSF_Pos) /*!< 0x00000008 */ 04435 #define RTC_CRL_RSF RTC_CRL_RSF_Msk /*!< Registers Synchronized Flag */ 04436 #define RTC_CRL_CNF_Pos (4U) 04437 #define RTC_CRL_CNF_Msk (0x1U << RTC_CRL_CNF_Pos) /*!< 0x00000010 */ 04438 #define RTC_CRL_CNF RTC_CRL_CNF_Msk /*!< Configuration Flag */ 04439 #define RTC_CRL_RTOFF_Pos (5U) 04440 #define RTC_CRL_RTOFF_Msk (0x1U << RTC_CRL_RTOFF_Pos) /*!< 0x00000020 */ 04441 #define RTC_CRL_RTOFF RTC_CRL_RTOFF_Msk /*!< RTC operation OFF */ 04442 04443 /******************* Bit definition for RTC_PRLH register *******************/ 04444 #define RTC_PRLH_PRL_Pos (0U) 04445 #define RTC_PRLH_PRL_Msk (0xFU << RTC_PRLH_PRL_Pos) /*!< 0x0000000F */ 04446 #define RTC_PRLH_PRL RTC_PRLH_PRL_Msk /*!< RTC Prescaler Reload Value High */ 04447 04448 /******************* Bit definition for RTC_PRLL register *******************/ 04449 #define RTC_PRLL_PRL_Pos (0U) 04450 #define RTC_PRLL_PRL_Msk (0xFFFFU << RTC_PRLL_PRL_Pos) /*!< 0x0000FFFF */ 04451 #define RTC_PRLL_PRL RTC_PRLL_PRL_Msk /*!< RTC Prescaler Reload Value Low */ 04452 04453 /******************* Bit definition for RTC_DIVH register *******************/ 04454 #define RTC_DIVH_RTC_DIV_Pos (0U) 04455 #define RTC_DIVH_RTC_DIV_Msk (0xFU << RTC_DIVH_RTC_DIV_Pos) /*!< 0x0000000F */ 04456 #define RTC_DIVH_RTC_DIV RTC_DIVH_RTC_DIV_Msk /*!< RTC Clock Divider High */ 04457 04458 /******************* Bit definition for RTC_DIVL register *******************/ 04459 #define RTC_DIVL_RTC_DIV_Pos (0U) 04460 #define RTC_DIVL_RTC_DIV_Msk (0xFFFFU << RTC_DIVL_RTC_DIV_Pos) /*!< 0x0000FFFF */ 04461 #define RTC_DIVL_RTC_DIV RTC_DIVL_RTC_DIV_Msk /*!< RTC Clock Divider Low */ 04462 04463 /******************* Bit definition for RTC_CNTH register *******************/ 04464 #define RTC_CNTH_RTC_CNT_Pos (0U) 04465 #define RTC_CNTH_RTC_CNT_Msk (0xFFFFU << RTC_CNTH_RTC_CNT_Pos) /*!< 0x0000FFFF */ 04466 #define RTC_CNTH_RTC_CNT RTC_CNTH_RTC_CNT_Msk /*!< RTC Counter High */ 04467 04468 /******************* Bit definition for RTC_CNTL register *******************/ 04469 #define RTC_CNTL_RTC_CNT_Pos (0U) 04470 #define RTC_CNTL_RTC_CNT_Msk (0xFFFFU << RTC_CNTL_RTC_CNT_Pos) /*!< 0x0000FFFF */ 04471 #define RTC_CNTL_RTC_CNT RTC_CNTL_RTC_CNT_Msk /*!< RTC Counter Low */ 04472 04473 /******************* Bit definition for RTC_ALRH register *******************/ 04474 #define RTC_ALRH_RTC_ALR_Pos (0U) 04475 #define RTC_ALRH_RTC_ALR_Msk (0xFFFFU << RTC_ALRH_RTC_ALR_Pos) /*!< 0x0000FFFF */ 04476 #define RTC_ALRH_RTC_ALR RTC_ALRH_RTC_ALR_Msk /*!< RTC Alarm High */ 04477 04478 /******************* Bit definition for RTC_ALRL register *******************/ 04479 #define RTC_ALRL_RTC_ALR_Pos (0U) 04480 #define RTC_ALRL_RTC_ALR_Msk (0xFFFFU << RTC_ALRL_RTC_ALR_Pos) /*!< 0x0000FFFF */ 04481 #define RTC_ALRL_RTC_ALR RTC_ALRL_RTC_ALR_Msk /*!< RTC Alarm Low */ 04482 04483 /******************************************************************************/ 04484 /* */ 04485 /* Independent WATCHDOG (IWDG) */ 04486 /* */ 04487 /******************************************************************************/ 04488 04489 /******************* Bit definition for IWDG_KR register ********************/ 04490 #define IWDG_KR_KEY_Pos (0U) 04491 #define IWDG_KR_KEY_Msk (0xFFFFU << IWDG_KR_KEY_Pos) /*!< 0x0000FFFF */ 04492 #define IWDG_KR_KEY IWDG_KR_KEY_Msk /*!< Key value (write only, read 0000h) */ 04493 04494 /******************* Bit definition for IWDG_PR register ********************/ 04495 #define IWDG_PR_PR_Pos (0U) 04496 #define IWDG_PR_PR_Msk (0x7U << IWDG_PR_PR_Pos) /*!< 0x00000007 */ 04497 #define IWDG_PR_PR IWDG_PR_PR_Msk /*!< PR[2:0] (Prescaler divider) */ 04498 #define IWDG_PR_PR_0 (0x1U << IWDG_PR_PR_Pos) /*!< 0x00000001 */ 04499 #define IWDG_PR_PR_1 (0x2U << IWDG_PR_PR_Pos) /*!< 0x00000002 */ 04500 #define IWDG_PR_PR_2 (0x4U << IWDG_PR_PR_Pos) /*!< 0x00000004 */ 04501 04502 /******************* Bit definition for IWDG_RLR register *******************/ 04503 #define IWDG_RLR_RL_Pos (0U) 04504 #define IWDG_RLR_RL_Msk (0xFFFU << IWDG_RLR_RL_Pos) /*!< 0x00000FFF */ 04505 #define IWDG_RLR_RL IWDG_RLR_RL_Msk /*!< Watchdog counter reload value */ 04506 04507 /******************* Bit definition for IWDG_SR register ********************/ 04508 #define IWDG_SR_PVU_Pos (0U) 04509 #define IWDG_SR_PVU_Msk (0x1U << IWDG_SR_PVU_Pos) /*!< 0x00000001 */ 04510 #define IWDG_SR_PVU IWDG_SR_PVU_Msk /*!< Watchdog prescaler value update */ 04511 #define IWDG_SR_RVU_Pos (1U) 04512 #define IWDG_SR_RVU_Msk (0x1U << IWDG_SR_RVU_Pos) /*!< 0x00000002 */ 04513 #define IWDG_SR_RVU IWDG_SR_RVU_Msk /*!< Watchdog counter reload value update */ 04514 04515 /******************************************************************************/ 04516 /* */ 04517 /* Window WATCHDOG (WWDG) */ 04518 /* */ 04519 /******************************************************************************/ 04520 04521 /******************* Bit definition for WWDG_CR register ********************/ 04522 #define WWDG_CR_T_Pos (0U) 04523 #define WWDG_CR_T_Msk (0x7FU << WWDG_CR_T_Pos) /*!< 0x0000007F */ 04524 #define WWDG_CR_T WWDG_CR_T_Msk /*!< T[6:0] bits (7-Bit counter (MSB to LSB)) */ 04525 #define WWDG_CR_T_0 (0x01U << WWDG_CR_T_Pos) /*!< 0x00000001 */ 04526 #define WWDG_CR_T_1 (0x02U << WWDG_CR_T_Pos) /*!< 0x00000002 */ 04527 #define WWDG_CR_T_2 (0x04U << WWDG_CR_T_Pos) /*!< 0x00000004 */ 04528 #define WWDG_CR_T_3 (0x08U << WWDG_CR_T_Pos) /*!< 0x00000008 */ 04529 #define WWDG_CR_T_4 (0x10U << WWDG_CR_T_Pos) /*!< 0x00000010 */ 04530 #define WWDG_CR_T_5 (0x20U << WWDG_CR_T_Pos) /*!< 0x00000020 */ 04531 #define WWDG_CR_T_6 (0x40U << WWDG_CR_T_Pos) /*!< 0x00000040 */ 04532 04533 /* Legacy defines */ 04534 #define WWDG_CR_T0 WWDG_CR_T_0 04535 #define WWDG_CR_T1 WWDG_CR_T_1 04536 #define WWDG_CR_T2 WWDG_CR_T_2 04537 #define WWDG_CR_T3 WWDG_CR_T_3 04538 #define WWDG_CR_T4 WWDG_CR_T_4 04539 #define WWDG_CR_T5 WWDG_CR_T_5 04540 #define WWDG_CR_T6 WWDG_CR_T_6 04541 04542 #define WWDG_CR_WDGA_Pos (7U) 04543 #define WWDG_CR_WDGA_Msk (0x1U << WWDG_CR_WDGA_Pos) /*!< 0x00000080 */ 04544 #define WWDG_CR_WDGA WWDG_CR_WDGA_Msk /*!< Activation bit */ 04545 04546 /******************* Bit definition for WWDG_CFR register *******************/ 04547 #define WWDG_CFR_W_Pos (0U) 04548 #define WWDG_CFR_W_Msk (0x7FU << WWDG_CFR_W_Pos) /*!< 0x0000007F */ 04549 #define WWDG_CFR_W WWDG_CFR_W_Msk /*!< W[6:0] bits (7-bit window value) */ 04550 #define WWDG_CFR_W_0 (0x01U << WWDG_CFR_W_Pos) /*!< 0x00000001 */ 04551 #define WWDG_CFR_W_1 (0x02U << WWDG_CFR_W_Pos) /*!< 0x00000002 */ 04552 #define WWDG_CFR_W_2 (0x04U << WWDG_CFR_W_Pos) /*!< 0x00000004 */ 04553 #define WWDG_CFR_W_3 (0x08U << WWDG_CFR_W_Pos) /*!< 0x00000008 */ 04554 #define WWDG_CFR_W_4 (0x10U << WWDG_CFR_W_Pos) /*!< 0x00000010 */ 04555 #define WWDG_CFR_W_5 (0x20U << WWDG_CFR_W_Pos) /*!< 0x00000020 */ 04556 #define WWDG_CFR_W_6 (0x40U << WWDG_CFR_W_Pos) /*!< 0x00000040 */ 04557 04558 /* Legacy defines */ 04559 #define WWDG_CFR_W0 WWDG_CFR_W_0 04560 #define WWDG_CFR_W1 WWDG_CFR_W_1 04561 #define WWDG_CFR_W2 WWDG_CFR_W_2 04562 #define WWDG_CFR_W3 WWDG_CFR_W_3 04563 #define WWDG_CFR_W4 WWDG_CFR_W_4 04564 #define WWDG_CFR_W5 WWDG_CFR_W_5 04565 #define WWDG_CFR_W6 WWDG_CFR_W_6 04566 04567 #define WWDG_CFR_WDGTB_Pos (7U) 04568 #define WWDG_CFR_WDGTB_Msk (0x3U << WWDG_CFR_WDGTB_Pos) /*!< 0x00000180 */ 04569 #define WWDG_CFR_WDGTB WWDG_CFR_WDGTB_Msk /*!< WDGTB[1:0] bits (Timer Base) */ 04570 #define WWDG_CFR_WDGTB_0 (0x1U << WWDG_CFR_WDGTB_Pos) /*!< 0x00000080 */ 04571 #define WWDG_CFR_WDGTB_1 (0x2U << WWDG_CFR_WDGTB_Pos) /*!< 0x00000100 */ 04572 04573 /* Legacy defines */ 04574 #define WWDG_CFR_WDGTB0 WWDG_CFR_WDGTB_0 04575 #define WWDG_CFR_WDGTB1 WWDG_CFR_WDGTB_1 04576 04577 #define WWDG_CFR_EWI_Pos (9U) 04578 #define WWDG_CFR_EWI_Msk (0x1U << WWDG_CFR_EWI_Pos) /*!< 0x00000200 */ 04579 #define WWDG_CFR_EWI WWDG_CFR_EWI_Msk /*!< Early Wakeup Interrupt */ 04580 04581 /******************* Bit definition for WWDG_SR register ********************/ 04582 #define WWDG_SR_EWIF_Pos (0U) 04583 #define WWDG_SR_EWIF_Msk (0x1U << WWDG_SR_EWIF_Pos) /*!< 0x00000001 */ 04584 #define WWDG_SR_EWIF WWDG_SR_EWIF_Msk /*!< Early Wakeup Interrupt Flag */ 04585 04586 04587 /******************************************************************************/ 04588 /* */ 04589 /* SD host Interface */ 04590 /* */ 04591 /******************************************************************************/ 04592 04593 /****************** Bit definition for SDIO_POWER register ******************/ 04594 #define SDIO_POWER_PWRCTRL_Pos (0U) 04595 #define SDIO_POWER_PWRCTRL_Msk (0x3U << SDIO_POWER_PWRCTRL_Pos) /*!< 0x00000003 */ 04596 #define SDIO_POWER_PWRCTRL SDIO_POWER_PWRCTRL_Msk /*!< PWRCTRL[1:0] bits (Power supply control bits) */ 04597 #define SDIO_POWER_PWRCTRL_0 (0x1U << SDIO_POWER_PWRCTRL_Pos) /*!< 0x01 */ 04598 #define SDIO_POWER_PWRCTRL_1 (0x2U << SDIO_POWER_PWRCTRL_Pos) /*!< 0x02 */ 04599 04600 /****************** Bit definition for SDIO_CLKCR register ******************/ 04601 #define SDIO_CLKCR_CLKDIV_Pos (0U) 04602 #define SDIO_CLKCR_CLKDIV_Msk (0xFFU << SDIO_CLKCR_CLKDIV_Pos) /*!< 0x000000FF */ 04603 #define SDIO_CLKCR_CLKDIV SDIO_CLKCR_CLKDIV_Msk /*!< Clock divide factor */ 04604 #define SDIO_CLKCR_CLKEN_Pos (8U) 04605 #define SDIO_CLKCR_CLKEN_Msk (0x1U << SDIO_CLKCR_CLKEN_Pos) /*!< 0x00000100 */ 04606 #define SDIO_CLKCR_CLKEN SDIO_CLKCR_CLKEN_Msk /*!< Clock enable bit */ 04607 #define SDIO_CLKCR_PWRSAV_Pos (9U) 04608 #define SDIO_CLKCR_PWRSAV_Msk (0x1U << SDIO_CLKCR_PWRSAV_Pos) /*!< 0x00000200 */ 04609 #define SDIO_CLKCR_PWRSAV SDIO_CLKCR_PWRSAV_Msk /*!< Power saving configuration bit */ 04610 #define SDIO_CLKCR_BYPASS_Pos (10U) 04611 #define SDIO_CLKCR_BYPASS_Msk (0x1U << SDIO_CLKCR_BYPASS_Pos) /*!< 0x00000400 */ 04612 #define SDIO_CLKCR_BYPASS SDIO_CLKCR_BYPASS_Msk /*!< Clock divider bypass enable bit */ 04613 04614 #define SDIO_CLKCR_WIDBUS_Pos (11U) 04615 #define SDIO_CLKCR_WIDBUS_Msk (0x3U << SDIO_CLKCR_WIDBUS_Pos) /*!< 0x00001800 */ 04616 #define SDIO_CLKCR_WIDBUS SDIO_CLKCR_WIDBUS_Msk /*!< WIDBUS[1:0] bits (Wide bus mode enable bit) */ 04617 #define SDIO_CLKCR_WIDBUS_0 (0x1U << SDIO_CLKCR_WIDBUS_Pos) /*!< 0x0800 */ 04618 #define SDIO_CLKCR_WIDBUS_1 (0x2U << SDIO_CLKCR_WIDBUS_Pos) /*!< 0x1000 */ 04619 04620 #define SDIO_CLKCR_NEGEDGE_Pos (13U) 04621 #define SDIO_CLKCR_NEGEDGE_Msk (0x1U << SDIO_CLKCR_NEGEDGE_Pos) /*!< 0x00002000 */ 04622 #define SDIO_CLKCR_NEGEDGE SDIO_CLKCR_NEGEDGE_Msk /*!< SDIO_CK dephasing selection bit */ 04623 #define SDIO_CLKCR_HWFC_EN_Pos (14U) 04624 #define SDIO_CLKCR_HWFC_EN_Msk (0x1U << SDIO_CLKCR_HWFC_EN_Pos) /*!< 0x00004000 */ 04625 #define SDIO_CLKCR_HWFC_EN SDIO_CLKCR_HWFC_EN_Msk /*!< HW Flow Control enable */ 04626 04627 /******************* Bit definition for SDIO_ARG register *******************/ 04628 #define SDIO_ARG_CMDARG_Pos (0U) 04629 #define SDIO_ARG_CMDARG_Msk (0xFFFFFFFFU << SDIO_ARG_CMDARG_Pos) /*!< 0xFFFFFFFF */ 04630 #define SDIO_ARG_CMDARG SDIO_ARG_CMDARG_Msk /*!< Command argument */ 04631 04632 /******************* Bit definition for SDIO_CMD register *******************/ 04633 #define SDIO_CMD_CMDINDEX_Pos (0U) 04634 #define SDIO_CMD_CMDINDEX_Msk (0x3FU << SDIO_CMD_CMDINDEX_Pos) /*!< 0x0000003F */ 04635 #define SDIO_CMD_CMDINDEX SDIO_CMD_CMDINDEX_Msk /*!< Command Index */ 04636 04637 #define SDIO_CMD_WAITRESP_Pos (6U) 04638 #define SDIO_CMD_WAITRESP_Msk (0x3U << SDIO_CMD_WAITRESP_Pos) /*!< 0x000000C0 */ 04639 #define SDIO_CMD_WAITRESP SDIO_CMD_WAITRESP_Msk /*!< WAITRESP[1:0] bits (Wait for response bits) */ 04640 #define SDIO_CMD_WAITRESP_0 (0x1U << SDIO_CMD_WAITRESP_Pos) /*!< 0x0040 */ 04641 #define SDIO_CMD_WAITRESP_1 (0x2U << SDIO_CMD_WAITRESP_Pos) /*!< 0x0080 */ 04642 04643 #define SDIO_CMD_WAITINT_Pos (8U) 04644 #define SDIO_CMD_WAITINT_Msk (0x1U << SDIO_CMD_WAITINT_Pos) /*!< 0x00000100 */ 04645 #define SDIO_CMD_WAITINT SDIO_CMD_WAITINT_Msk /*!< CPSM Waits for Interrupt Request */ 04646 #define SDIO_CMD_WAITPEND_Pos (9U) 04647 #define SDIO_CMD_WAITPEND_Msk (0x1U << SDIO_CMD_WAITPEND_Pos) /*!< 0x00000200 */ 04648 #define SDIO_CMD_WAITPEND SDIO_CMD_WAITPEND_Msk /*!< CPSM Waits for ends of data transfer (CmdPend internal signal) */ 04649 #define SDIO_CMD_CPSMEN_Pos (10U) 04650 #define SDIO_CMD_CPSMEN_Msk (0x1U << SDIO_CMD_CPSMEN_Pos) /*!< 0x00000400 */ 04651 #define SDIO_CMD_CPSMEN SDIO_CMD_CPSMEN_Msk /*!< Command path state machine (CPSM) Enable bit */ 04652 #define SDIO_CMD_SDIOSUSPEND_Pos (11U) 04653 #define SDIO_CMD_SDIOSUSPEND_Msk (0x1U << SDIO_CMD_SDIOSUSPEND_Pos) /*!< 0x00000800 */ 04654 #define SDIO_CMD_SDIOSUSPEND SDIO_CMD_SDIOSUSPEND_Msk /*!< SD I/O suspend command */ 04655 #define SDIO_CMD_ENCMDCOMPL_Pos (12U) 04656 #define SDIO_CMD_ENCMDCOMPL_Msk (0x1U << SDIO_CMD_ENCMDCOMPL_Pos) /*!< 0x00001000 */ 04657 #define SDIO_CMD_ENCMDCOMPL SDIO_CMD_ENCMDCOMPL_Msk /*!< Enable CMD completion */ 04658 #define SDIO_CMD_NIEN_Pos (13U) 04659 #define SDIO_CMD_NIEN_Msk (0x1U << SDIO_CMD_NIEN_Pos) /*!< 0x00002000 */ 04660 #define SDIO_CMD_NIEN SDIO_CMD_NIEN_Msk /*!< Not Interrupt Enable */ 04661 #define SDIO_CMD_CEATACMD_Pos (14U) 04662 #define SDIO_CMD_CEATACMD_Msk (0x1U << SDIO_CMD_CEATACMD_Pos) /*!< 0x00004000 */ 04663 #define SDIO_CMD_CEATACMD SDIO_CMD_CEATACMD_Msk /*!< CE-ATA command */ 04664 04665 /***************** Bit definition for SDIO_RESPCMD register *****************/ 04666 #define SDIO_RESPCMD_RESPCMD_Pos (0U) 04667 #define SDIO_RESPCMD_RESPCMD_Msk (0x3FU << SDIO_RESPCMD_RESPCMD_Pos) /*!< 0x0000003F */ 04668 #define SDIO_RESPCMD_RESPCMD SDIO_RESPCMD_RESPCMD_Msk /*!< Response command index */ 04669 04670 /****************** Bit definition for SDIO_RESP0 register ******************/ 04671 #define SDIO_RESP0_CARDSTATUS0_Pos (0U) 04672 #define SDIO_RESP0_CARDSTATUS0_Msk (0xFFFFFFFFU << SDIO_RESP0_CARDSTATUS0_Pos) /*!< 0xFFFFFFFF */ 04673 #define SDIO_RESP0_CARDSTATUS0 SDIO_RESP0_CARDSTATUS0_Msk /*!< Card Status */ 04674 04675 /****************** Bit definition for SDIO_RESP1 register ******************/ 04676 #define SDIO_RESP1_CARDSTATUS1_Pos (0U) 04677 #define SDIO_RESP1_CARDSTATUS1_Msk (0xFFFFFFFFU << SDIO_RESP1_CARDSTATUS1_Pos) /*!< 0xFFFFFFFF */ 04678 #define SDIO_RESP1_CARDSTATUS1 SDIO_RESP1_CARDSTATUS1_Msk /*!< Card Status */ 04679 04680 /****************** Bit definition for SDIO_RESP2 register ******************/ 04681 #define SDIO_RESP2_CARDSTATUS2_Pos (0U) 04682 #define SDIO_RESP2_CARDSTATUS2_Msk (0xFFFFFFFFU << SDIO_RESP2_CARDSTATUS2_Pos) /*!< 0xFFFFFFFF */ 04683 #define SDIO_RESP2_CARDSTATUS2 SDIO_RESP2_CARDSTATUS2_Msk /*!< Card Status */ 04684 04685 /****************** Bit definition for SDIO_RESP3 register ******************/ 04686 #define SDIO_RESP3_CARDSTATUS3_Pos (0U) 04687 #define SDIO_RESP3_CARDSTATUS3_Msk (0xFFFFFFFFU << SDIO_RESP3_CARDSTATUS3_Pos) /*!< 0xFFFFFFFF */ 04688 #define SDIO_RESP3_CARDSTATUS3 SDIO_RESP3_CARDSTATUS3_Msk /*!< Card Status */ 04689 04690 /****************** Bit definition for SDIO_RESP4 register ******************/ 04691 #define SDIO_RESP4_CARDSTATUS4_Pos (0U) 04692 #define SDIO_RESP4_CARDSTATUS4_Msk (0xFFFFFFFFU << SDIO_RESP4_CARDSTATUS4_Pos) /*!< 0xFFFFFFFF */ 04693 #define SDIO_RESP4_CARDSTATUS4 SDIO_RESP4_CARDSTATUS4_Msk /*!< Card Status */ 04694 04695 /****************** Bit definition for SDIO_DTIMER register *****************/ 04696 #define SDIO_DTIMER_DATATIME_Pos (0U) 04697 #define SDIO_DTIMER_DATATIME_Msk (0xFFFFFFFFU << SDIO_DTIMER_DATATIME_Pos) /*!< 0xFFFFFFFF */ 04698 #define SDIO_DTIMER_DATATIME SDIO_DTIMER_DATATIME_Msk /*!< Data timeout period. */ 04699 04700 /****************** Bit definition for SDIO_DLEN register *******************/ 04701 #define SDIO_DLEN_DATALENGTH_Pos (0U) 04702 #define SDIO_DLEN_DATALENGTH_Msk (0x1FFFFFFU << SDIO_DLEN_DATALENGTH_Pos) /*!< 0x01FFFFFF */ 04703 #define SDIO_DLEN_DATALENGTH SDIO_DLEN_DATALENGTH_Msk /*!< Data length value */ 04704 04705 /****************** Bit definition for SDIO_DCTRL register ******************/ 04706 #define SDIO_DCTRL_DTEN_Pos (0U) 04707 #define SDIO_DCTRL_DTEN_Msk (0x1U << SDIO_DCTRL_DTEN_Pos) /*!< 0x00000001 */ 04708 #define SDIO_DCTRL_DTEN SDIO_DCTRL_DTEN_Msk /*!< Data transfer enabled bit */ 04709 #define SDIO_DCTRL_DTDIR_Pos (1U) 04710 #define SDIO_DCTRL_DTDIR_Msk (0x1U << SDIO_DCTRL_DTDIR_Pos) /*!< 0x00000002 */ 04711 #define SDIO_DCTRL_DTDIR SDIO_DCTRL_DTDIR_Msk /*!< Data transfer direction selection */ 04712 #define SDIO_DCTRL_DTMODE_Pos (2U) 04713 #define SDIO_DCTRL_DTMODE_Msk (0x1U << SDIO_DCTRL_DTMODE_Pos) /*!< 0x00000004 */ 04714 #define SDIO_DCTRL_DTMODE SDIO_DCTRL_DTMODE_Msk /*!< Data transfer mode selection */ 04715 #define SDIO_DCTRL_DMAEN_Pos (3U) 04716 #define SDIO_DCTRL_DMAEN_Msk (0x1U << SDIO_DCTRL_DMAEN_Pos) /*!< 0x00000008 */ 04717 #define SDIO_DCTRL_DMAEN SDIO_DCTRL_DMAEN_Msk /*!< DMA enabled bit */ 04718 04719 #define SDIO_DCTRL_DBLOCKSIZE_Pos (4U) 04720 #define SDIO_DCTRL_DBLOCKSIZE_Msk (0xFU << SDIO_DCTRL_DBLOCKSIZE_Pos) /*!< 0x000000F0 */ 04721 #define SDIO_DCTRL_DBLOCKSIZE SDIO_DCTRL_DBLOCKSIZE_Msk /*!< DBLOCKSIZE[3:0] bits (Data block size) */ 04722 #define SDIO_DCTRL_DBLOCKSIZE_0 (0x1U << SDIO_DCTRL_DBLOCKSIZE_Pos) /*!< 0x0010 */ 04723 #define SDIO_DCTRL_DBLOCKSIZE_1 (0x2U << SDIO_DCTRL_DBLOCKSIZE_Pos) /*!< 0x0020 */ 04724 #define SDIO_DCTRL_DBLOCKSIZE_2 (0x4U << SDIO_DCTRL_DBLOCKSIZE_Pos) /*!< 0x0040 */ 04725 #define SDIO_DCTRL_DBLOCKSIZE_3 (0x8U << SDIO_DCTRL_DBLOCKSIZE_Pos) /*!< 0x0080 */ 04726 04727 #define SDIO_DCTRL_RWSTART_Pos (8U) 04728 #define SDIO_DCTRL_RWSTART_Msk (0x1U << SDIO_DCTRL_RWSTART_Pos) /*!< 0x00000100 */ 04729 #define SDIO_DCTRL_RWSTART SDIO_DCTRL_RWSTART_Msk /*!< Read wait start */ 04730 #define SDIO_DCTRL_RWSTOP_Pos (9U) 04731 #define SDIO_DCTRL_RWSTOP_Msk (0x1U << SDIO_DCTRL_RWSTOP_Pos) /*!< 0x00000200 */ 04732 #define SDIO_DCTRL_RWSTOP SDIO_DCTRL_RWSTOP_Msk /*!< Read wait stop */ 04733 #define SDIO_DCTRL_RWMOD_Pos (10U) 04734 #define SDIO_DCTRL_RWMOD_Msk (0x1U << SDIO_DCTRL_RWMOD_Pos) /*!< 0x00000400 */ 04735 #define SDIO_DCTRL_RWMOD SDIO_DCTRL_RWMOD_Msk /*!< Read wait mode */ 04736 #define SDIO_DCTRL_SDIOEN_Pos (11U) 04737 #define SDIO_DCTRL_SDIOEN_Msk (0x1U << SDIO_DCTRL_SDIOEN_Pos) /*!< 0x00000800 */ 04738 #define SDIO_DCTRL_SDIOEN SDIO_DCTRL_SDIOEN_Msk /*!< SD I/O enable functions */ 04739 04740 /****************** Bit definition for SDIO_DCOUNT register *****************/ 04741 #define SDIO_DCOUNT_DATACOUNT_Pos (0U) 04742 #define SDIO_DCOUNT_DATACOUNT_Msk (0x1FFFFFFU << SDIO_DCOUNT_DATACOUNT_Pos) /*!< 0x01FFFFFF */ 04743 #define SDIO_DCOUNT_DATACOUNT SDIO_DCOUNT_DATACOUNT_Msk /*!< Data count value */ 04744 04745 /****************** Bit definition for SDIO_STA register ********************/ 04746 #define SDIO_STA_CCRCFAIL_Pos (0U) 04747 #define SDIO_STA_CCRCFAIL_Msk (0x1U << SDIO_STA_CCRCFAIL_Pos) /*!< 0x00000001 */ 04748 #define SDIO_STA_CCRCFAIL SDIO_STA_CCRCFAIL_Msk /*!< Command response received (CRC check failed) */ 04749 #define SDIO_STA_DCRCFAIL_Pos (1U) 04750 #define SDIO_STA_DCRCFAIL_Msk (0x1U << SDIO_STA_DCRCFAIL_Pos) /*!< 0x00000002 */ 04751 #define SDIO_STA_DCRCFAIL SDIO_STA_DCRCFAIL_Msk /*!< Data block sent/received (CRC check failed) */ 04752 #define SDIO_STA_CTIMEOUT_Pos (2U) 04753 #define SDIO_STA_CTIMEOUT_Msk (0x1U << SDIO_STA_CTIMEOUT_Pos) /*!< 0x00000004 */ 04754 #define SDIO_STA_CTIMEOUT SDIO_STA_CTIMEOUT_Msk /*!< Command response timeout */ 04755 #define SDIO_STA_DTIMEOUT_Pos (3U) 04756 #define SDIO_STA_DTIMEOUT_Msk (0x1U << SDIO_STA_DTIMEOUT_Pos) /*!< 0x00000008 */ 04757 #define SDIO_STA_DTIMEOUT SDIO_STA_DTIMEOUT_Msk /*!< Data timeout */ 04758 #define SDIO_STA_TXUNDERR_Pos (4U) 04759 #define SDIO_STA_TXUNDERR_Msk (0x1U << SDIO_STA_TXUNDERR_Pos) /*!< 0x00000010 */ 04760 #define SDIO_STA_TXUNDERR SDIO_STA_TXUNDERR_Msk /*!< Transmit FIFO underrun error */ 04761 #define SDIO_STA_RXOVERR_Pos (5U) 04762 #define SDIO_STA_RXOVERR_Msk (0x1U << SDIO_STA_RXOVERR_Pos) /*!< 0x00000020 */ 04763 #define SDIO_STA_RXOVERR SDIO_STA_RXOVERR_Msk /*!< Received FIFO overrun error */ 04764 #define SDIO_STA_CMDREND_Pos (6U) 04765 #define SDIO_STA_CMDREND_Msk (0x1U << SDIO_STA_CMDREND_Pos) /*!< 0x00000040 */ 04766 #define SDIO_STA_CMDREND SDIO_STA_CMDREND_Msk /*!< Command response received (CRC check passed) */ 04767 #define SDIO_STA_CMDSENT_Pos (7U) 04768 #define SDIO_STA_CMDSENT_Msk (0x1U << SDIO_STA_CMDSENT_Pos) /*!< 0x00000080 */ 04769 #define SDIO_STA_CMDSENT SDIO_STA_CMDSENT_Msk /*!< Command sent (no response required) */ 04770 #define SDIO_STA_DATAEND_Pos (8U) 04771 #define SDIO_STA_DATAEND_Msk (0x1U << SDIO_STA_DATAEND_Pos) /*!< 0x00000100 */ 04772 #define SDIO_STA_DATAEND SDIO_STA_DATAEND_Msk /*!< Data end (data counter, SDIDCOUNT, is zero) */ 04773 #define SDIO_STA_STBITERR_Pos (9U) 04774 #define SDIO_STA_STBITERR_Msk (0x1U << SDIO_STA_STBITERR_Pos) /*!< 0x00000200 */ 04775 #define SDIO_STA_STBITERR SDIO_STA_STBITERR_Msk /*!< Start bit not detected on all data signals in wide bus mode */ 04776 #define SDIO_STA_DBCKEND_Pos (10U) 04777 #define SDIO_STA_DBCKEND_Msk (0x1U << SDIO_STA_DBCKEND_Pos) /*!< 0x00000400 */ 04778 #define SDIO_STA_DBCKEND SDIO_STA_DBCKEND_Msk /*!< Data block sent/received (CRC check passed) */ 04779 #define SDIO_STA_CMDACT_Pos (11U) 04780 #define SDIO_STA_CMDACT_Msk (0x1U << SDIO_STA_CMDACT_Pos) /*!< 0x00000800 */ 04781 #define SDIO_STA_CMDACT SDIO_STA_CMDACT_Msk /*!< Command transfer in progress */ 04782 #define SDIO_STA_TXACT_Pos (12U) 04783 #define SDIO_STA_TXACT_Msk (0x1U << SDIO_STA_TXACT_Pos) /*!< 0x00001000 */ 04784 #define SDIO_STA_TXACT SDIO_STA_TXACT_Msk /*!< Data transmit in progress */ 04785 #define SDIO_STA_RXACT_Pos (13U) 04786 #define SDIO_STA_RXACT_Msk (0x1U << SDIO_STA_RXACT_Pos) /*!< 0x00002000 */ 04787 #define SDIO_STA_RXACT SDIO_STA_RXACT_Msk /*!< Data receive in progress */ 04788 #define SDIO_STA_TXFIFOHE_Pos (14U) 04789 #define SDIO_STA_TXFIFOHE_Msk (0x1U << SDIO_STA_TXFIFOHE_Pos) /*!< 0x00004000 */ 04790 #define SDIO_STA_TXFIFOHE SDIO_STA_TXFIFOHE_Msk /*!< Transmit FIFO Half Empty: at least 8 words can be written into the FIFO */ 04791 #define SDIO_STA_RXFIFOHF_Pos (15U) 04792 #define SDIO_STA_RXFIFOHF_Msk (0x1U << SDIO_STA_RXFIFOHF_Pos) /*!< 0x00008000 */ 04793 #define SDIO_STA_RXFIFOHF SDIO_STA_RXFIFOHF_Msk /*!< Receive FIFO Half Full: there are at least 8 words in the FIFO */ 04794 #define SDIO_STA_TXFIFOF_Pos (16U) 04795 #define SDIO_STA_TXFIFOF_Msk (0x1U << SDIO_STA_TXFIFOF_Pos) /*!< 0x00010000 */ 04796 #define SDIO_STA_TXFIFOF SDIO_STA_TXFIFOF_Msk /*!< Transmit FIFO full */ 04797 #define SDIO_STA_RXFIFOF_Pos (17U) 04798 #define SDIO_STA_RXFIFOF_Msk (0x1U << SDIO_STA_RXFIFOF_Pos) /*!< 0x00020000 */ 04799 #define SDIO_STA_RXFIFOF SDIO_STA_RXFIFOF_Msk /*!< Receive FIFO full */ 04800 #define SDIO_STA_TXFIFOE_Pos (18U) 04801 #define SDIO_STA_TXFIFOE_Msk (0x1U << SDIO_STA_TXFIFOE_Pos) /*!< 0x00040000 */ 04802 #define SDIO_STA_TXFIFOE SDIO_STA_TXFIFOE_Msk /*!< Transmit FIFO empty */ 04803 #define SDIO_STA_RXFIFOE_Pos (19U) 04804 #define SDIO_STA_RXFIFOE_Msk (0x1U << SDIO_STA_RXFIFOE_Pos) /*!< 0x00080000 */ 04805 #define SDIO_STA_RXFIFOE SDIO_STA_RXFIFOE_Msk /*!< Receive FIFO empty */ 04806 #define SDIO_STA_TXDAVL_Pos (20U) 04807 #define SDIO_STA_TXDAVL_Msk (0x1U << SDIO_STA_TXDAVL_Pos) /*!< 0x00100000 */ 04808 #define SDIO_STA_TXDAVL SDIO_STA_TXDAVL_Msk /*!< Data available in transmit FIFO */ 04809 #define SDIO_STA_RXDAVL_Pos (21U) 04810 #define SDIO_STA_RXDAVL_Msk (0x1U << SDIO_STA_RXDAVL_Pos) /*!< 0x00200000 */ 04811 #define SDIO_STA_RXDAVL SDIO_STA_RXDAVL_Msk /*!< Data available in receive FIFO */ 04812 #define SDIO_STA_SDIOIT_Pos (22U) 04813 #define SDIO_STA_SDIOIT_Msk (0x1U << SDIO_STA_SDIOIT_Pos) /*!< 0x00400000 */ 04814 #define SDIO_STA_SDIOIT SDIO_STA_SDIOIT_Msk /*!< SDIO interrupt received */ 04815 #define SDIO_STA_CEATAEND_Pos (23U) 04816 #define SDIO_STA_CEATAEND_Msk (0x1U << SDIO_STA_CEATAEND_Pos) /*!< 0x00800000 */ 04817 #define SDIO_STA_CEATAEND SDIO_STA_CEATAEND_Msk /*!< CE-ATA command completion signal received for CMD61 */ 04818 04819 /******************* Bit definition for SDIO_ICR register *******************/ 04820 #define SDIO_ICR_CCRCFAILC_Pos (0U) 04821 #define SDIO_ICR_CCRCFAILC_Msk (0x1U << SDIO_ICR_CCRCFAILC_Pos) /*!< 0x00000001 */ 04822 #define SDIO_ICR_CCRCFAILC SDIO_ICR_CCRCFAILC_Msk /*!< CCRCFAIL flag clear bit */ 04823 #define SDIO_ICR_DCRCFAILC_Pos (1U) 04824 #define SDIO_ICR_DCRCFAILC_Msk (0x1U << SDIO_ICR_DCRCFAILC_Pos) /*!< 0x00000002 */ 04825 #define SDIO_ICR_DCRCFAILC SDIO_ICR_DCRCFAILC_Msk /*!< DCRCFAIL flag clear bit */ 04826 #define SDIO_ICR_CTIMEOUTC_Pos (2U) 04827 #define SDIO_ICR_CTIMEOUTC_Msk (0x1U << SDIO_ICR_CTIMEOUTC_Pos) /*!< 0x00000004 */ 04828 #define SDIO_ICR_CTIMEOUTC SDIO_ICR_CTIMEOUTC_Msk /*!< CTIMEOUT flag clear bit */ 04829 #define SDIO_ICR_DTIMEOUTC_Pos (3U) 04830 #define SDIO_ICR_DTIMEOUTC_Msk (0x1U << SDIO_ICR_DTIMEOUTC_Pos) /*!< 0x00000008 */ 04831 #define SDIO_ICR_DTIMEOUTC SDIO_ICR_DTIMEOUTC_Msk /*!< DTIMEOUT flag clear bit */ 04832 #define SDIO_ICR_TXUNDERRC_Pos (4U) 04833 #define SDIO_ICR_TXUNDERRC_Msk (0x1U << SDIO_ICR_TXUNDERRC_Pos) /*!< 0x00000010 */ 04834 #define SDIO_ICR_TXUNDERRC SDIO_ICR_TXUNDERRC_Msk /*!< TXUNDERR flag clear bit */ 04835 #define SDIO_ICR_RXOVERRC_Pos (5U) 04836 #define SDIO_ICR_RXOVERRC_Msk (0x1U << SDIO_ICR_RXOVERRC_Pos) /*!< 0x00000020 */ 04837 #define SDIO_ICR_RXOVERRC SDIO_ICR_RXOVERRC_Msk /*!< RXOVERR flag clear bit */ 04838 #define SDIO_ICR_CMDRENDC_Pos (6U) 04839 #define SDIO_ICR_CMDRENDC_Msk (0x1U << SDIO_ICR_CMDRENDC_Pos) /*!< 0x00000040 */ 04840 #define SDIO_ICR_CMDRENDC SDIO_ICR_CMDRENDC_Msk /*!< CMDREND flag clear bit */ 04841 #define SDIO_ICR_CMDSENTC_Pos (7U) 04842 #define SDIO_ICR_CMDSENTC_Msk (0x1U << SDIO_ICR_CMDSENTC_Pos) /*!< 0x00000080 */ 04843 #define SDIO_ICR_CMDSENTC SDIO_ICR_CMDSENTC_Msk /*!< CMDSENT flag clear bit */ 04844 #define SDIO_ICR_DATAENDC_Pos (8U) 04845 #define SDIO_ICR_DATAENDC_Msk (0x1U << SDIO_ICR_DATAENDC_Pos) /*!< 0x00000100 */ 04846 #define SDIO_ICR_DATAENDC SDIO_ICR_DATAENDC_Msk /*!< DATAEND flag clear bit */ 04847 #define SDIO_ICR_STBITERRC_Pos (9U) 04848 #define SDIO_ICR_STBITERRC_Msk (0x1U << SDIO_ICR_STBITERRC_Pos) /*!< 0x00000200 */ 04849 #define SDIO_ICR_STBITERRC SDIO_ICR_STBITERRC_Msk /*!< STBITERR flag clear bit */ 04850 #define SDIO_ICR_DBCKENDC_Pos (10U) 04851 #define SDIO_ICR_DBCKENDC_Msk (0x1U << SDIO_ICR_DBCKENDC_Pos) /*!< 0x00000400 */ 04852 #define SDIO_ICR_DBCKENDC SDIO_ICR_DBCKENDC_Msk /*!< DBCKEND flag clear bit */ 04853 #define SDIO_ICR_SDIOITC_Pos (22U) 04854 #define SDIO_ICR_SDIOITC_Msk (0x1U << SDIO_ICR_SDIOITC_Pos) /*!< 0x00400000 */ 04855 #define SDIO_ICR_SDIOITC SDIO_ICR_SDIOITC_Msk /*!< SDIOIT flag clear bit */ 04856 #define SDIO_ICR_CEATAENDC_Pos (23U) 04857 #define SDIO_ICR_CEATAENDC_Msk (0x1U << SDIO_ICR_CEATAENDC_Pos) /*!< 0x00800000 */ 04858 #define SDIO_ICR_CEATAENDC SDIO_ICR_CEATAENDC_Msk /*!< CEATAEND flag clear bit */ 04859 04860 /****************** Bit definition for SDIO_MASK register *******************/ 04861 #define SDIO_MASK_CCRCFAILIE_Pos (0U) 04862 #define SDIO_MASK_CCRCFAILIE_Msk (0x1U << SDIO_MASK_CCRCFAILIE_Pos) /*!< 0x00000001 */ 04863 #define SDIO_MASK_CCRCFAILIE SDIO_MASK_CCRCFAILIE_Msk /*!< Command CRC Fail Interrupt Enable */ 04864 #define SDIO_MASK_DCRCFAILIE_Pos (1U) 04865 #define SDIO_MASK_DCRCFAILIE_Msk (0x1U << SDIO_MASK_DCRCFAILIE_Pos) /*!< 0x00000002 */ 04866 #define SDIO_MASK_DCRCFAILIE SDIO_MASK_DCRCFAILIE_Msk /*!< Data CRC Fail Interrupt Enable */ 04867 #define SDIO_MASK_CTIMEOUTIE_Pos (2U) 04868 #define SDIO_MASK_CTIMEOUTIE_Msk (0x1U << SDIO_MASK_CTIMEOUTIE_Pos) /*!< 0x00000004 */ 04869 #define SDIO_MASK_CTIMEOUTIE SDIO_MASK_CTIMEOUTIE_Msk /*!< Command TimeOut Interrupt Enable */ 04870 #define SDIO_MASK_DTIMEOUTIE_Pos (3U) 04871 #define SDIO_MASK_DTIMEOUTIE_Msk (0x1U << SDIO_MASK_DTIMEOUTIE_Pos) /*!< 0x00000008 */ 04872 #define SDIO_MASK_DTIMEOUTIE SDIO_MASK_DTIMEOUTIE_Msk /*!< Data TimeOut Interrupt Enable */ 04873 #define SDIO_MASK_TXUNDERRIE_Pos (4U) 04874 #define SDIO_MASK_TXUNDERRIE_Msk (0x1U << SDIO_MASK_TXUNDERRIE_Pos) /*!< 0x00000010 */ 04875 #define SDIO_MASK_TXUNDERRIE SDIO_MASK_TXUNDERRIE_Msk /*!< Tx FIFO UnderRun Error Interrupt Enable */ 04876 #define SDIO_MASK_RXOVERRIE_Pos (5U) 04877 #define SDIO_MASK_RXOVERRIE_Msk (0x1U << SDIO_MASK_RXOVERRIE_Pos) /*!< 0x00000020 */ 04878 #define SDIO_MASK_RXOVERRIE SDIO_MASK_RXOVERRIE_Msk /*!< Rx FIFO OverRun Error Interrupt Enable */ 04879 #define SDIO_MASK_CMDRENDIE_Pos (6U) 04880 #define SDIO_MASK_CMDRENDIE_Msk (0x1U << SDIO_MASK_CMDRENDIE_Pos) /*!< 0x00000040 */ 04881 #define SDIO_MASK_CMDRENDIE SDIO_MASK_CMDRENDIE_Msk /*!< Command Response Received Interrupt Enable */ 04882 #define SDIO_MASK_CMDSENTIE_Pos (7U) 04883 #define SDIO_MASK_CMDSENTIE_Msk (0x1U << SDIO_MASK_CMDSENTIE_Pos) /*!< 0x00000080 */ 04884 #define SDIO_MASK_CMDSENTIE SDIO_MASK_CMDSENTIE_Msk /*!< Command Sent Interrupt Enable */ 04885 #define SDIO_MASK_DATAENDIE_Pos (8U) 04886 #define SDIO_MASK_DATAENDIE_Msk (0x1U << SDIO_MASK_DATAENDIE_Pos) /*!< 0x00000100 */ 04887 #define SDIO_MASK_DATAENDIE SDIO_MASK_DATAENDIE_Msk /*!< Data End Interrupt Enable */ 04888 #define SDIO_MASK_STBITERRIE_Pos (9U) 04889 #define SDIO_MASK_STBITERRIE_Msk (0x1U << SDIO_MASK_STBITERRIE_Pos) /*!< 0x00000200 */ 04890 #define SDIO_MASK_STBITERRIE SDIO_MASK_STBITERRIE_Msk /*!< Start Bit Error Interrupt Enable */ 04891 #define SDIO_MASK_DBCKENDIE_Pos (10U) 04892 #define SDIO_MASK_DBCKENDIE_Msk (0x1U << SDIO_MASK_DBCKENDIE_Pos) /*!< 0x00000400 */ 04893 #define SDIO_MASK_DBCKENDIE SDIO_MASK_DBCKENDIE_Msk /*!< Data Block End Interrupt Enable */ 04894 #define SDIO_MASK_CMDACTIE_Pos (11U) 04895 #define SDIO_MASK_CMDACTIE_Msk (0x1U << SDIO_MASK_CMDACTIE_Pos) /*!< 0x00000800 */ 04896 #define SDIO_MASK_CMDACTIE SDIO_MASK_CMDACTIE_Msk /*!< Command Acting Interrupt Enable */ 04897 #define SDIO_MASK_TXACTIE_Pos (12U) 04898 #define SDIO_MASK_TXACTIE_Msk (0x1U << SDIO_MASK_TXACTIE_Pos) /*!< 0x00001000 */ 04899 #define SDIO_MASK_TXACTIE SDIO_MASK_TXACTIE_Msk /*!< Data Transmit Acting Interrupt Enable */ 04900 #define SDIO_MASK_RXACTIE_Pos (13U) 04901 #define SDIO_MASK_RXACTIE_Msk (0x1U << SDIO_MASK_RXACTIE_Pos) /*!< 0x00002000 */ 04902 #define SDIO_MASK_RXACTIE SDIO_MASK_RXACTIE_Msk /*!< Data receive acting interrupt enabled */ 04903 #define SDIO_MASK_TXFIFOHEIE_Pos (14U) 04904 #define SDIO_MASK_TXFIFOHEIE_Msk (0x1U << SDIO_MASK_TXFIFOHEIE_Pos) /*!< 0x00004000 */ 04905 #define SDIO_MASK_TXFIFOHEIE SDIO_MASK_TXFIFOHEIE_Msk /*!< Tx FIFO Half Empty interrupt Enable */ 04906 #define SDIO_MASK_RXFIFOHFIE_Pos (15U) 04907 #define SDIO_MASK_RXFIFOHFIE_Msk (0x1U << SDIO_MASK_RXFIFOHFIE_Pos) /*!< 0x00008000 */ 04908 #define SDIO_MASK_RXFIFOHFIE SDIO_MASK_RXFIFOHFIE_Msk /*!< Rx FIFO Half Full interrupt Enable */ 04909 #define SDIO_MASK_TXFIFOFIE_Pos (16U) 04910 #define SDIO_MASK_TXFIFOFIE_Msk (0x1U << SDIO_MASK_TXFIFOFIE_Pos) /*!< 0x00010000 */ 04911 #define SDIO_MASK_TXFIFOFIE SDIO_MASK_TXFIFOFIE_Msk /*!< Tx FIFO Full interrupt Enable */ 04912 #define SDIO_MASK_RXFIFOFIE_Pos (17U) 04913 #define SDIO_MASK_RXFIFOFIE_Msk (0x1U << SDIO_MASK_RXFIFOFIE_Pos) /*!< 0x00020000 */ 04914 #define SDIO_MASK_RXFIFOFIE SDIO_MASK_RXFIFOFIE_Msk /*!< Rx FIFO Full interrupt Enable */ 04915 #define SDIO_MASK_TXFIFOEIE_Pos (18U) 04916 #define SDIO_MASK_TXFIFOEIE_Msk (0x1U << SDIO_MASK_TXFIFOEIE_Pos) /*!< 0x00040000 */ 04917 #define SDIO_MASK_TXFIFOEIE SDIO_MASK_TXFIFOEIE_Msk /*!< Tx FIFO Empty interrupt Enable */ 04918 #define SDIO_MASK_RXFIFOEIE_Pos (19U) 04919 #define SDIO_MASK_RXFIFOEIE_Msk (0x1U << SDIO_MASK_RXFIFOEIE_Pos) /*!< 0x00080000 */ 04920 #define SDIO_MASK_RXFIFOEIE SDIO_MASK_RXFIFOEIE_Msk /*!< Rx FIFO Empty interrupt Enable */ 04921 #define SDIO_MASK_TXDAVLIE_Pos (20U) 04922 #define SDIO_MASK_TXDAVLIE_Msk (0x1U << SDIO_MASK_TXDAVLIE_Pos) /*!< 0x00100000 */ 04923 #define SDIO_MASK_TXDAVLIE SDIO_MASK_TXDAVLIE_Msk /*!< Data available in Tx FIFO interrupt Enable */ 04924 #define SDIO_MASK_RXDAVLIE_Pos (21U) 04925 #define SDIO_MASK_RXDAVLIE_Msk (0x1U << SDIO_MASK_RXDAVLIE_Pos) /*!< 0x00200000 */ 04926 #define SDIO_MASK_RXDAVLIE SDIO_MASK_RXDAVLIE_Msk /*!< Data available in Rx FIFO interrupt Enable */ 04927 #define SDIO_MASK_SDIOITIE_Pos (22U) 04928 #define SDIO_MASK_SDIOITIE_Msk (0x1U << SDIO_MASK_SDIOITIE_Pos) /*!< 0x00400000 */ 04929 #define SDIO_MASK_SDIOITIE SDIO_MASK_SDIOITIE_Msk /*!< SDIO Mode Interrupt Received interrupt Enable */ 04930 #define SDIO_MASK_CEATAENDIE_Pos (23U) 04931 #define SDIO_MASK_CEATAENDIE_Msk (0x1U << SDIO_MASK_CEATAENDIE_Pos) /*!< 0x00800000 */ 04932 #define SDIO_MASK_CEATAENDIE SDIO_MASK_CEATAENDIE_Msk /*!< CE-ATA command completion signal received Interrupt Enable */ 04933 04934 /***************** Bit definition for SDIO_FIFOCNT register *****************/ 04935 #define SDIO_FIFOCNT_FIFOCOUNT_Pos (0U) 04936 #define SDIO_FIFOCNT_FIFOCOUNT_Msk (0xFFFFFFU << SDIO_FIFOCNT_FIFOCOUNT_Pos) /*!< 0x00FFFFFF */ 04937 #define SDIO_FIFOCNT_FIFOCOUNT SDIO_FIFOCNT_FIFOCOUNT_Msk /*!< Remaining number of words to be written to or read from the FIFO */ 04938 04939 /****************** Bit definition for SDIO_FIFO register *******************/ 04940 #define SDIO_FIFO_FIFODATA_Pos (0U) 04941 #define SDIO_FIFO_FIFODATA_Msk (0xFFFFFFFFU << SDIO_FIFO_FIFODATA_Pos) /*!< 0xFFFFFFFF */ 04942 #define SDIO_FIFO_FIFODATA SDIO_FIFO_FIFODATA_Msk /*!< Receive and transmit FIFO data */ 04943 04944 /******************************************************************************/ 04945 /* */ 04946 /* USB Device FS */ 04947 /* */ 04948 /******************************************************************************/ 04949 04950 /*!< Endpoint-specific registers */ 04951 #define USB_EP0R USB_BASE /*!< Endpoint 0 register address */ 04952 #define USB_EP1R (USB_BASE + 0x00000004) /*!< Endpoint 1 register address */ 04953 #define USB_EP2R (USB_BASE + 0x00000008) /*!< Endpoint 2 register address */ 04954 #define USB_EP3R (USB_BASE + 0x0000000C) /*!< Endpoint 3 register address */ 04955 #define USB_EP4R (USB_BASE + 0x00000010) /*!< Endpoint 4 register address */ 04956 #define USB_EP5R (USB_BASE + 0x00000014) /*!< Endpoint 5 register address */ 04957 #define USB_EP6R (USB_BASE + 0x00000018) /*!< Endpoint 6 register address */ 04958 #define USB_EP7R (USB_BASE + 0x0000001C) /*!< Endpoint 7 register address */ 04959 04960 /* bit positions */ 04961 #define USB_EP_CTR_RX_Pos (15U) 04962 #define USB_EP_CTR_RX_Msk (0x1U << USB_EP_CTR_RX_Pos) /*!< 0x00008000 */ 04963 #define USB_EP_CTR_RX USB_EP_CTR_RX_Msk /*!< EndPoint Correct TRansfer RX */ 04964 #define USB_EP_DTOG_RX_Pos (14U) 04965 #define USB_EP_DTOG_RX_Msk (0x1U << USB_EP_DTOG_RX_Pos) /*!< 0x00004000 */ 04966 #define USB_EP_DTOG_RX USB_EP_DTOG_RX_Msk /*!< EndPoint Data TOGGLE RX */ 04967 #define USB_EPRX_STAT_Pos (12U) 04968 #define USB_EPRX_STAT_Msk (0x3U << USB_EPRX_STAT_Pos) /*!< 0x00003000 */ 04969 #define USB_EPRX_STAT USB_EPRX_STAT_Msk /*!< EndPoint RX STATus bit field */ 04970 #define USB_EP_SETUP_Pos (11U) 04971 #define USB_EP_SETUP_Msk (0x1U << USB_EP_SETUP_Pos) /*!< 0x00000800 */ 04972 #define USB_EP_SETUP USB_EP_SETUP_Msk /*!< EndPoint SETUP */ 04973 #define USB_EP_T_FIELD_Pos (9U) 04974 #define USB_EP_T_FIELD_Msk (0x3U << USB_EP_T_FIELD_Pos) /*!< 0x00000600 */ 04975 #define USB_EP_T_FIELD USB_EP_T_FIELD_Msk /*!< EndPoint TYPE */ 04976 #define USB_EP_KIND_Pos (8U) 04977 #define USB_EP_KIND_Msk (0x1U << USB_EP_KIND_Pos) /*!< 0x00000100 */ 04978 #define USB_EP_KIND USB_EP_KIND_Msk /*!< EndPoint KIND */ 04979 #define USB_EP_CTR_TX_Pos (7U) 04980 #define USB_EP_CTR_TX_Msk (0x1U << USB_EP_CTR_TX_Pos) /*!< 0x00000080 */ 04981 #define USB_EP_CTR_TX USB_EP_CTR_TX_Msk /*!< EndPoint Correct TRansfer TX */ 04982 #define USB_EP_DTOG_TX_Pos (6U) 04983 #define USB_EP_DTOG_TX_Msk (0x1U << USB_EP_DTOG_TX_Pos) /*!< 0x00000040 */ 04984 #define USB_EP_DTOG_TX USB_EP_DTOG_TX_Msk /*!< EndPoint Data TOGGLE TX */ 04985 #define USB_EPTX_STAT_Pos (4U) 04986 #define USB_EPTX_STAT_Msk (0x3U << USB_EPTX_STAT_Pos) /*!< 0x00000030 */ 04987 #define USB_EPTX_STAT USB_EPTX_STAT_Msk /*!< EndPoint TX STATus bit field */ 04988 #define USB_EPADDR_FIELD_Pos (0U) 04989 #define USB_EPADDR_FIELD_Msk (0xFU << USB_EPADDR_FIELD_Pos) /*!< 0x0000000F */ 04990 #define USB_EPADDR_FIELD USB_EPADDR_FIELD_Msk /*!< EndPoint ADDRess FIELD */ 04991 04992 /* EndPoint REGister MASK (no toggle fields) */ 04993 #define USB_EPREG_MASK (USB_EP_CTR_RX|USB_EP_SETUP|USB_EP_T_FIELD|USB_EP_KIND|USB_EP_CTR_TX|USB_EPADDR_FIELD) 04994 /*!< EP_TYPE[1:0] EndPoint TYPE */ 04995 #define USB_EP_TYPE_MASK_Pos (9U) 04996 #define USB_EP_TYPE_MASK_Msk (0x3U << USB_EP_TYPE_MASK_Pos) /*!< 0x00000600 */ 04997 #define USB_EP_TYPE_MASK USB_EP_TYPE_MASK_Msk /*!< EndPoint TYPE Mask */ 04998 #define USB_EP_BULK ((uint32_t)0x00000000) /*!< EndPoint BULK */ 04999 #define USB_EP_CONTROL ((uint32_t)0x00000200) /*!< EndPoint CONTROL */ 05000 #define USB_EP_ISOCHRONOUS ((uint32_t)0x00000400) /*!< EndPoint ISOCHRONOUS */ 05001 #define USB_EP_INTERRUPT ((uint32_t)0x00000600) /*!< EndPoint INTERRUPT */ 05002 #define USB_EP_T_MASK (~USB_EP_T_FIELD & USB_EPREG_MASK) 05003 05004 #define USB_EPKIND_MASK (~USB_EP_KIND & USB_EPREG_MASK) /*!< EP_KIND EndPoint KIND */ 05005 /*!< STAT_TX[1:0] STATus for TX transfer */ 05006 #define USB_EP_TX_DIS ((uint32_t)0x00000000) /*!< EndPoint TX DISabled */ 05007 #define USB_EP_TX_STALL ((uint32_t)0x00000010) /*!< EndPoint TX STALLed */ 05008 #define USB_EP_TX_NAK ((uint32_t)0x00000020) /*!< EndPoint TX NAKed */ 05009 #define USB_EP_TX_VALID ((uint32_t)0x00000030) /*!< EndPoint TX VALID */ 05010 #define USB_EPTX_DTOG1 ((uint32_t)0x00000010) /*!< EndPoint TX Data TOGgle bit1 */ 05011 #define USB_EPTX_DTOG2 ((uint32_t)0x00000020) /*!< EndPoint TX Data TOGgle bit2 */ 05012 #define USB_EPTX_DTOGMASK (USB_EPTX_STAT|USB_EPREG_MASK) 05013 /*!< STAT_RX[1:0] STATus for RX transfer */ 05014 #define USB_EP_RX_DIS ((uint32_t)0x00000000) /*!< EndPoint RX DISabled */ 05015 #define USB_EP_RX_STALL ((uint32_t)0x00001000) /*!< EndPoint RX STALLed */ 05016 #define USB_EP_RX_NAK ((uint32_t)0x00002000) /*!< EndPoint RX NAKed */ 05017 #define USB_EP_RX_VALID ((uint32_t)0x00003000) /*!< EndPoint RX VALID */ 05018 #define USB_EPRX_DTOG1 ((uint32_t)0x00001000) /*!< EndPoint RX Data TOGgle bit1 */ 05019 #define USB_EPRX_DTOG2 ((uint32_t)0x00002000) /*!< EndPoint RX Data TOGgle bit1 */ 05020 #define USB_EPRX_DTOGMASK (USB_EPRX_STAT|USB_EPREG_MASK) 05021 05022 /******************* Bit definition for USB_EP0R register *******************/ 05023 #define USB_EP0R_EA_Pos (0U) 05024 #define USB_EP0R_EA_Msk (0xFU << USB_EP0R_EA_Pos) /*!< 0x0000000F */ 05025 #define USB_EP0R_EA USB_EP0R_EA_Msk /*!< Endpoint Address */ 05026 05027 #define USB_EP0R_STAT_TX_Pos (4U) 05028 #define USB_EP0R_STAT_TX_Msk (0x3U << USB_EP0R_STAT_TX_Pos) /*!< 0x00000030 */ 05029 #define USB_EP0R_STAT_TX USB_EP0R_STAT_TX_Msk /*!< STAT_TX[1:0] bits (Status bits, for transmission transfers) */ 05030 #define USB_EP0R_STAT_TX_0 (0x1U << USB_EP0R_STAT_TX_Pos) /*!< 0x00000010 */ 05031 #define USB_EP0R_STAT_TX_1 (0x2U << USB_EP0R_STAT_TX_Pos) /*!< 0x00000020 */ 05032 05033 #define USB_EP0R_DTOG_TX_Pos (6U) 05034 #define USB_EP0R_DTOG_TX_Msk (0x1U << USB_EP0R_DTOG_TX_Pos) /*!< 0x00000040 */ 05035 #define USB_EP0R_DTOG_TX USB_EP0R_DTOG_TX_Msk /*!< Data Toggle, for transmission transfers */ 05036 #define USB_EP0R_CTR_TX_Pos (7U) 05037 #define USB_EP0R_CTR_TX_Msk (0x1U << USB_EP0R_CTR_TX_Pos) /*!< 0x00000080 */ 05038 #define USB_EP0R_CTR_TX USB_EP0R_CTR_TX_Msk /*!< Correct Transfer for transmission */ 05039 #define USB_EP0R_EP_KIND_Pos (8U) 05040 #define USB_EP0R_EP_KIND_Msk (0x1U << USB_EP0R_EP_KIND_Pos) /*!< 0x00000100 */ 05041 #define USB_EP0R_EP_KIND USB_EP0R_EP_KIND_Msk /*!< Endpoint Kind */ 05042 05043 #define USB_EP0R_EP_TYPE_Pos (9U) 05044 #define USB_EP0R_EP_TYPE_Msk (0x3U << USB_EP0R_EP_TYPE_Pos) /*!< 0x00000600 */ 05045 #define USB_EP0R_EP_TYPE USB_EP0R_EP_TYPE_Msk /*!< EP_TYPE[1:0] bits (Endpoint type) */ 05046 #define USB_EP0R_EP_TYPE_0 (0x1U << USB_EP0R_EP_TYPE_Pos) /*!< 0x00000200 */ 05047 #define USB_EP0R_EP_TYPE_1 (0x2U << USB_EP0R_EP_TYPE_Pos) /*!< 0x00000400 */ 05048 05049 #define USB_EP0R_SETUP_Pos (11U) 05050 #define USB_EP0R_SETUP_Msk (0x1U << USB_EP0R_SETUP_Pos) /*!< 0x00000800 */ 05051 #define USB_EP0R_SETUP USB_EP0R_SETUP_Msk /*!< Setup transaction completed */ 05052 05053 #define USB_EP0R_STAT_RX_Pos (12U) 05054 #define USB_EP0R_STAT_RX_Msk (0x3U << USB_EP0R_STAT_RX_Pos) /*!< 0x00003000 */ 05055 #define USB_EP0R_STAT_RX USB_EP0R_STAT_RX_Msk /*!< STAT_RX[1:0] bits (Status bits, for reception transfers) */ 05056 #define USB_EP0R_STAT_RX_0 (0x1U << USB_EP0R_STAT_RX_Pos) /*!< 0x00001000 */ 05057 #define USB_EP0R_STAT_RX_1 (0x2U << USB_EP0R_STAT_RX_Pos) /*!< 0x00002000 */ 05058 05059 #define USB_EP0R_DTOG_RX_Pos (14U) 05060 #define USB_EP0R_DTOG_RX_Msk (0x1U << USB_EP0R_DTOG_RX_Pos) /*!< 0x00004000 */ 05061 #define USB_EP0R_DTOG_RX USB_EP0R_DTOG_RX_Msk /*!< Data Toggle, for reception transfers */ 05062 #define USB_EP0R_CTR_RX_Pos (15U) 05063 #define USB_EP0R_CTR_RX_Msk (0x1U << USB_EP0R_CTR_RX_Pos) /*!< 0x00008000 */ 05064 #define USB_EP0R_CTR_RX USB_EP0R_CTR_RX_Msk /*!< Correct Transfer for reception */ 05065 05066 /******************* Bit definition for USB_EP1R register *******************/ 05067 #define USB_EP1R_EA_Pos (0U) 05068 #define USB_EP1R_EA_Msk (0xFU << USB_EP1R_EA_Pos) /*!< 0x0000000F */ 05069 #define USB_EP1R_EA USB_EP1R_EA_Msk /*!< Endpoint Address */ 05070 05071 #define USB_EP1R_STAT_TX_Pos (4U) 05072 #define USB_EP1R_STAT_TX_Msk (0x3U << USB_EP1R_STAT_TX_Pos) /*!< 0x00000030 */ 05073 #define USB_EP1R_STAT_TX USB_EP1R_STAT_TX_Msk /*!< STAT_TX[1:0] bits (Status bits, for transmission transfers) */ 05074 #define USB_EP1R_STAT_TX_0 (0x1U << USB_EP1R_STAT_TX_Pos) /*!< 0x00000010 */ 05075 #define USB_EP1R_STAT_TX_1 (0x2U << USB_EP1R_STAT_TX_Pos) /*!< 0x00000020 */ 05076 05077 #define USB_EP1R_DTOG_TX_Pos (6U) 05078 #define USB_EP1R_DTOG_TX_Msk (0x1U << USB_EP1R_DTOG_TX_Pos) /*!< 0x00000040 */ 05079 #define USB_EP1R_DTOG_TX USB_EP1R_DTOG_TX_Msk /*!< Data Toggle, for transmission transfers */ 05080 #define USB_EP1R_CTR_TX_Pos (7U) 05081 #define USB_EP1R_CTR_TX_Msk (0x1U << USB_EP1R_CTR_TX_Pos) /*!< 0x00000080 */ 05082 #define USB_EP1R_CTR_TX USB_EP1R_CTR_TX_Msk /*!< Correct Transfer for transmission */ 05083 #define USB_EP1R_EP_KIND_Pos (8U) 05084 #define USB_EP1R_EP_KIND_Msk (0x1U << USB_EP1R_EP_KIND_Pos) /*!< 0x00000100 */ 05085 #define USB_EP1R_EP_KIND USB_EP1R_EP_KIND_Msk /*!< Endpoint Kind */ 05086 05087 #define USB_EP1R_EP_TYPE_Pos (9U) 05088 #define USB_EP1R_EP_TYPE_Msk (0x3U << USB_EP1R_EP_TYPE_Pos) /*!< 0x00000600 */ 05089 #define USB_EP1R_EP_TYPE USB_EP1R_EP_TYPE_Msk /*!< EP_TYPE[1:0] bits (Endpoint type) */ 05090 #define USB_EP1R_EP_TYPE_0 (0x1U << USB_EP1R_EP_TYPE_Pos) /*!< 0x00000200 */ 05091 #define USB_EP1R_EP_TYPE_1 (0x2U << USB_EP1R_EP_TYPE_Pos) /*!< 0x00000400 */ 05092 05093 #define USB_EP1R_SETUP_Pos (11U) 05094 #define USB_EP1R_SETUP_Msk (0x1U << USB_EP1R_SETUP_Pos) /*!< 0x00000800 */ 05095 #define USB_EP1R_SETUP USB_EP1R_SETUP_Msk /*!< Setup transaction completed */ 05096 05097 #define USB_EP1R_STAT_RX_Pos (12U) 05098 #define USB_EP1R_STAT_RX_Msk (0x3U << USB_EP1R_STAT_RX_Pos) /*!< 0x00003000 */ 05099 #define USB_EP1R_STAT_RX USB_EP1R_STAT_RX_Msk /*!< STAT_RX[1:0] bits (Status bits, for reception transfers) */ 05100 #define USB_EP1R_STAT_RX_0 (0x1U << USB_EP1R_STAT_RX_Pos) /*!< 0x00001000 */ 05101 #define USB_EP1R_STAT_RX_1 (0x2U << USB_EP1R_STAT_RX_Pos) /*!< 0x00002000 */ 05102 05103 #define USB_EP1R_DTOG_RX_Pos (14U) 05104 #define USB_EP1R_DTOG_RX_Msk (0x1U << USB_EP1R_DTOG_RX_Pos) /*!< 0x00004000 */ 05105 #define USB_EP1R_DTOG_RX USB_EP1R_DTOG_RX_Msk /*!< Data Toggle, for reception transfers */ 05106 #define USB_EP1R_CTR_RX_Pos (15U) 05107 #define USB_EP1R_CTR_RX_Msk (0x1U << USB_EP1R_CTR_RX_Pos) /*!< 0x00008000 */ 05108 #define USB_EP1R_CTR_RX USB_EP1R_CTR_RX_Msk /*!< Correct Transfer for reception */ 05109 05110 /******************* Bit definition for USB_EP2R register *******************/ 05111 #define USB_EP2R_EA_Pos (0U) 05112 #define USB_EP2R_EA_Msk (0xFU << USB_EP2R_EA_Pos) /*!< 0x0000000F */ 05113 #define USB_EP2R_EA USB_EP2R_EA_Msk /*!< Endpoint Address */ 05114 05115 #define USB_EP2R_STAT_TX_Pos (4U) 05116 #define USB_EP2R_STAT_TX_Msk (0x3U << USB_EP2R_STAT_TX_Pos) /*!< 0x00000030 */ 05117 #define USB_EP2R_STAT_TX USB_EP2R_STAT_TX_Msk /*!< STAT_TX[1:0] bits (Status bits, for transmission transfers) */ 05118 #define USB_EP2R_STAT_TX_0 (0x1U << USB_EP2R_STAT_TX_Pos) /*!< 0x00000010 */ 05119 #define USB_EP2R_STAT_TX_1 (0x2U << USB_EP2R_STAT_TX_Pos) /*!< 0x00000020 */ 05120 05121 #define USB_EP2R_DTOG_TX_Pos (6U) 05122 #define USB_EP2R_DTOG_TX_Msk (0x1U << USB_EP2R_DTOG_TX_Pos) /*!< 0x00000040 */ 05123 #define USB_EP2R_DTOG_TX USB_EP2R_DTOG_TX_Msk /*!< Data Toggle, for transmission transfers */ 05124 #define USB_EP2R_CTR_TX_Pos (7U) 05125 #define USB_EP2R_CTR_TX_Msk (0x1U << USB_EP2R_CTR_TX_Pos) /*!< 0x00000080 */ 05126 #define USB_EP2R_CTR_TX USB_EP2R_CTR_TX_Msk /*!< Correct Transfer for transmission */ 05127 #define USB_EP2R_EP_KIND_Pos (8U) 05128 #define USB_EP2R_EP_KIND_Msk (0x1U << USB_EP2R_EP_KIND_Pos) /*!< 0x00000100 */ 05129 #define USB_EP2R_EP_KIND USB_EP2R_EP_KIND_Msk /*!< Endpoint Kind */ 05130 05131 #define USB_EP2R_EP_TYPE_Pos (9U) 05132 #define USB_EP2R_EP_TYPE_Msk (0x3U << USB_EP2R_EP_TYPE_Pos) /*!< 0x00000600 */ 05133 #define USB_EP2R_EP_TYPE USB_EP2R_EP_TYPE_Msk /*!< EP_TYPE[1:0] bits (Endpoint type) */ 05134 #define USB_EP2R_EP_TYPE_0 (0x1U << USB_EP2R_EP_TYPE_Pos) /*!< 0x00000200 */ 05135 #define USB_EP2R_EP_TYPE_1 (0x2U << USB_EP2R_EP_TYPE_Pos) /*!< 0x00000400 */ 05136 05137 #define USB_EP2R_SETUP_Pos (11U) 05138 #define USB_EP2R_SETUP_Msk (0x1U << USB_EP2R_SETUP_Pos) /*!< 0x00000800 */ 05139 #define USB_EP2R_SETUP USB_EP2R_SETUP_Msk /*!< Setup transaction completed */ 05140 05141 #define USB_EP2R_STAT_RX_Pos (12U) 05142 #define USB_EP2R_STAT_RX_Msk (0x3U << USB_EP2R_STAT_RX_Pos) /*!< 0x00003000 */ 05143 #define USB_EP2R_STAT_RX USB_EP2R_STAT_RX_Msk /*!< STAT_RX[1:0] bits (Status bits, for reception transfers) */ 05144 #define USB_EP2R_STAT_RX_0 (0x1U << USB_EP2R_STAT_RX_Pos) /*!< 0x00001000 */ 05145 #define USB_EP2R_STAT_RX_1 (0x2U << USB_EP2R_STAT_RX_Pos) /*!< 0x00002000 */ 05146 05147 #define USB_EP2R_DTOG_RX_Pos (14U) 05148 #define USB_EP2R_DTOG_RX_Msk (0x1U << USB_EP2R_DTOG_RX_Pos) /*!< 0x00004000 */ 05149 #define USB_EP2R_DTOG_RX USB_EP2R_DTOG_RX_Msk /*!< Data Toggle, for reception transfers */ 05150 #define USB_EP2R_CTR_RX_Pos (15U) 05151 #define USB_EP2R_CTR_RX_Msk (0x1U << USB_EP2R_CTR_RX_Pos) /*!< 0x00008000 */ 05152 #define USB_EP2R_CTR_RX USB_EP2R_CTR_RX_Msk /*!< Correct Transfer for reception */ 05153 05154 /******************* Bit definition for USB_EP3R register *******************/ 05155 #define USB_EP3R_EA_Pos (0U) 05156 #define USB_EP3R_EA_Msk (0xFU << USB_EP3R_EA_Pos) /*!< 0x0000000F */ 05157 #define USB_EP3R_EA USB_EP3R_EA_Msk /*!< Endpoint Address */ 05158 05159 #define USB_EP3R_STAT_TX_Pos (4U) 05160 #define USB_EP3R_STAT_TX_Msk (0x3U << USB_EP3R_STAT_TX_Pos) /*!< 0x00000030 */ 05161 #define USB_EP3R_STAT_TX USB_EP3R_STAT_TX_Msk /*!< STAT_TX[1:0] bits (Status bits, for transmission transfers) */ 05162 #define USB_EP3R_STAT_TX_0 (0x1U << USB_EP3R_STAT_TX_Pos) /*!< 0x00000010 */ 05163 #define USB_EP3R_STAT_TX_1 (0x2U << USB_EP3R_STAT_TX_Pos) /*!< 0x00000020 */ 05164 05165 #define USB_EP3R_DTOG_TX_Pos (6U) 05166 #define USB_EP3R_DTOG_TX_Msk (0x1U << USB_EP3R_DTOG_TX_Pos) /*!< 0x00000040 */ 05167 #define USB_EP3R_DTOG_TX USB_EP3R_DTOG_TX_Msk /*!< Data Toggle, for transmission transfers */ 05168 #define USB_EP3R_CTR_TX_Pos (7U) 05169 #define USB_EP3R_CTR_TX_Msk (0x1U << USB_EP3R_CTR_TX_Pos) /*!< 0x00000080 */ 05170 #define USB_EP3R_CTR_TX USB_EP3R_CTR_TX_Msk /*!< Correct Transfer for transmission */ 05171 #define USB_EP3R_EP_KIND_Pos (8U) 05172 #define USB_EP3R_EP_KIND_Msk (0x1U << USB_EP3R_EP_KIND_Pos) /*!< 0x00000100 */ 05173 #define USB_EP3R_EP_KIND USB_EP3R_EP_KIND_Msk /*!< Endpoint Kind */ 05174 05175 #define USB_EP3R_EP_TYPE_Pos (9U) 05176 #define USB_EP3R_EP_TYPE_Msk (0x3U << USB_EP3R_EP_TYPE_Pos) /*!< 0x00000600 */ 05177 #define USB_EP3R_EP_TYPE USB_EP3R_EP_TYPE_Msk /*!< EP_TYPE[1:0] bits (Endpoint type) */ 05178 #define USB_EP3R_EP_TYPE_0 (0x1U << USB_EP3R_EP_TYPE_Pos) /*!< 0x00000200 */ 05179 #define USB_EP3R_EP_TYPE_1 (0x2U << USB_EP3R_EP_TYPE_Pos) /*!< 0x00000400 */ 05180 05181 #define USB_EP3R_SETUP_Pos (11U) 05182 #define USB_EP3R_SETUP_Msk (0x1U << USB_EP3R_SETUP_Pos) /*!< 0x00000800 */ 05183 #define USB_EP3R_SETUP USB_EP3R_SETUP_Msk /*!< Setup transaction completed */ 05184 05185 #define USB_EP3R_STAT_RX_Pos (12U) 05186 #define USB_EP3R_STAT_RX_Msk (0x3U << USB_EP3R_STAT_RX_Pos) /*!< 0x00003000 */ 05187 #define USB_EP3R_STAT_RX USB_EP3R_STAT_RX_Msk /*!< STAT_RX[1:0] bits (Status bits, for reception transfers) */ 05188 #define USB_EP3R_STAT_RX_0 (0x1U << USB_EP3R_STAT_RX_Pos) /*!< 0x00001000 */ 05189 #define USB_EP3R_STAT_RX_1 (0x2U << USB_EP3R_STAT_RX_Pos) /*!< 0x00002000 */ 05190 05191 #define USB_EP3R_DTOG_RX_Pos (14U) 05192 #define USB_EP3R_DTOG_RX_Msk (0x1U << USB_EP3R_DTOG_RX_Pos) /*!< 0x00004000 */ 05193 #define USB_EP3R_DTOG_RX USB_EP3R_DTOG_RX_Msk /*!< Data Toggle, for reception transfers */ 05194 #define USB_EP3R_CTR_RX_Pos (15U) 05195 #define USB_EP3R_CTR_RX_Msk (0x1U << USB_EP3R_CTR_RX_Pos) /*!< 0x00008000 */ 05196 #define USB_EP3R_CTR_RX USB_EP3R_CTR_RX_Msk /*!< Correct Transfer for reception */ 05197 05198 /******************* Bit definition for USB_EP4R register *******************/ 05199 #define USB_EP4R_EA_Pos (0U) 05200 #define USB_EP4R_EA_Msk (0xFU << USB_EP4R_EA_Pos) /*!< 0x0000000F */ 05201 #define USB_EP4R_EA USB_EP4R_EA_Msk /*!< Endpoint Address */ 05202 05203 #define USB_EP4R_STAT_TX_Pos (4U) 05204 #define USB_EP4R_STAT_TX_Msk (0x3U << USB_EP4R_STAT_TX_Pos) /*!< 0x00000030 */ 05205 #define USB_EP4R_STAT_TX USB_EP4R_STAT_TX_Msk /*!< STAT_TX[1:0] bits (Status bits, for transmission transfers) */ 05206 #define USB_EP4R_STAT_TX_0 (0x1U << USB_EP4R_STAT_TX_Pos) /*!< 0x00000010 */ 05207 #define USB_EP4R_STAT_TX_1 (0x2U << USB_EP4R_STAT_TX_Pos) /*!< 0x00000020 */ 05208 05209 #define USB_EP4R_DTOG_TX_Pos (6U) 05210 #define USB_EP4R_DTOG_TX_Msk (0x1U << USB_EP4R_DTOG_TX_Pos) /*!< 0x00000040 */ 05211 #define USB_EP4R_DTOG_TX USB_EP4R_DTOG_TX_Msk /*!< Data Toggle, for transmission transfers */ 05212 #define USB_EP4R_CTR_TX_Pos (7U) 05213 #define USB_EP4R_CTR_TX_Msk (0x1U << USB_EP4R_CTR_TX_Pos) /*!< 0x00000080 */ 05214 #define USB_EP4R_CTR_TX USB_EP4R_CTR_TX_Msk /*!< Correct Transfer for transmission */ 05215 #define USB_EP4R_EP_KIND_Pos (8U) 05216 #define USB_EP4R_EP_KIND_Msk (0x1U << USB_EP4R_EP_KIND_Pos) /*!< 0x00000100 */ 05217 #define USB_EP4R_EP_KIND USB_EP4R_EP_KIND_Msk /*!< Endpoint Kind */ 05218 05219 #define USB_EP4R_EP_TYPE_Pos (9U) 05220 #define USB_EP4R_EP_TYPE_Msk (0x3U << USB_EP4R_EP_TYPE_Pos) /*!< 0x00000600 */ 05221 #define USB_EP4R_EP_TYPE USB_EP4R_EP_TYPE_Msk /*!< EP_TYPE[1:0] bits (Endpoint type) */ 05222 #define USB_EP4R_EP_TYPE_0 (0x1U << USB_EP4R_EP_TYPE_Pos) /*!< 0x00000200 */ 05223 #define USB_EP4R_EP_TYPE_1 (0x2U << USB_EP4R_EP_TYPE_Pos) /*!< 0x00000400 */ 05224 05225 #define USB_EP4R_SETUP_Pos (11U) 05226 #define USB_EP4R_SETUP_Msk (0x1U << USB_EP4R_SETUP_Pos) /*!< 0x00000800 */ 05227 #define USB_EP4R_SETUP USB_EP4R_SETUP_Msk /*!< Setup transaction completed */ 05228 05229 #define USB_EP4R_STAT_RX_Pos (12U) 05230 #define USB_EP4R_STAT_RX_Msk (0x3U << USB_EP4R_STAT_RX_Pos) /*!< 0x00003000 */ 05231 #define USB_EP4R_STAT_RX USB_EP4R_STAT_RX_Msk /*!< STAT_RX[1:0] bits (Status bits, for reception transfers) */ 05232 #define USB_EP4R_STAT_RX_0 (0x1U << USB_EP4R_STAT_RX_Pos) /*!< 0x00001000 */ 05233 #define USB_EP4R_STAT_RX_1 (0x2U << USB_EP4R_STAT_RX_Pos) /*!< 0x00002000 */ 05234 05235 #define USB_EP4R_DTOG_RX_Pos (14U) 05236 #define USB_EP4R_DTOG_RX_Msk (0x1U << USB_EP4R_DTOG_RX_Pos) /*!< 0x00004000 */ 05237 #define USB_EP4R_DTOG_RX USB_EP4R_DTOG_RX_Msk /*!< Data Toggle, for reception transfers */ 05238 #define USB_EP4R_CTR_RX_Pos (15U) 05239 #define USB_EP4R_CTR_RX_Msk (0x1U << USB_EP4R_CTR_RX_Pos) /*!< 0x00008000 */ 05240 #define USB_EP4R_CTR_RX USB_EP4R_CTR_RX_Msk /*!< Correct Transfer for reception */ 05241 05242 /******************* Bit definition for USB_EP5R register *******************/ 05243 #define USB_EP5R_EA_Pos (0U) 05244 #define USB_EP5R_EA_Msk (0xFU << USB_EP5R_EA_Pos) /*!< 0x0000000F */ 05245 #define USB_EP5R_EA USB_EP5R_EA_Msk /*!< Endpoint Address */ 05246 05247 #define USB_EP5R_STAT_TX_Pos (4U) 05248 #define USB_EP5R_STAT_TX_Msk (0x3U << USB_EP5R_STAT_TX_Pos) /*!< 0x00000030 */ 05249 #define USB_EP5R_STAT_TX USB_EP5R_STAT_TX_Msk /*!< STAT_TX[1:0] bits (Status bits, for transmission transfers) */ 05250 #define USB_EP5R_STAT_TX_0 (0x1U << USB_EP5R_STAT_TX_Pos) /*!< 0x00000010 */ 05251 #define USB_EP5R_STAT_TX_1 (0x2U << USB_EP5R_STAT_TX_Pos) /*!< 0x00000020 */ 05252 05253 #define USB_EP5R_DTOG_TX_Pos (6U) 05254 #define USB_EP5R_DTOG_TX_Msk (0x1U << USB_EP5R_DTOG_TX_Pos) /*!< 0x00000040 */ 05255 #define USB_EP5R_DTOG_TX USB_EP5R_DTOG_TX_Msk /*!< Data Toggle, for transmission transfers */ 05256 #define USB_EP5R_CTR_TX_Pos (7U) 05257 #define USB_EP5R_CTR_TX_Msk (0x1U << USB_EP5R_CTR_TX_Pos) /*!< 0x00000080 */ 05258 #define USB_EP5R_CTR_TX USB_EP5R_CTR_TX_Msk /*!< Correct Transfer for transmission */ 05259 #define USB_EP5R_EP_KIND_Pos (8U) 05260 #define USB_EP5R_EP_KIND_Msk (0x1U << USB_EP5R_EP_KIND_Pos) /*!< 0x00000100 */ 05261 #define USB_EP5R_EP_KIND USB_EP5R_EP_KIND_Msk /*!< Endpoint Kind */ 05262 05263 #define USB_EP5R_EP_TYPE_Pos (9U) 05264 #define USB_EP5R_EP_TYPE_Msk (0x3U << USB_EP5R_EP_TYPE_Pos) /*!< 0x00000600 */ 05265 #define USB_EP5R_EP_TYPE USB_EP5R_EP_TYPE_Msk /*!< EP_TYPE[1:0] bits (Endpoint type) */ 05266 #define USB_EP5R_EP_TYPE_0 (0x1U << USB_EP5R_EP_TYPE_Pos) /*!< 0x00000200 */ 05267 #define USB_EP5R_EP_TYPE_1 (0x2U << USB_EP5R_EP_TYPE_Pos) /*!< 0x00000400 */ 05268 05269 #define USB_EP5R_SETUP_Pos (11U) 05270 #define USB_EP5R_SETUP_Msk (0x1U << USB_EP5R_SETUP_Pos) /*!< 0x00000800 */ 05271 #define USB_EP5R_SETUP USB_EP5R_SETUP_Msk /*!< Setup transaction completed */ 05272 05273 #define USB_EP5R_STAT_RX_Pos (12U) 05274 #define USB_EP5R_STAT_RX_Msk (0x3U << USB_EP5R_STAT_RX_Pos) /*!< 0x00003000 */ 05275 #define USB_EP5R_STAT_RX USB_EP5R_STAT_RX_Msk /*!< STAT_RX[1:0] bits (Status bits, for reception transfers) */ 05276 #define USB_EP5R_STAT_RX_0 (0x1U << USB_EP5R_STAT_RX_Pos) /*!< 0x00001000 */ 05277 #define USB_EP5R_STAT_RX_1 (0x2U << USB_EP5R_STAT_RX_Pos) /*!< 0x00002000 */ 05278 05279 #define USB_EP5R_DTOG_RX_Pos (14U) 05280 #define USB_EP5R_DTOG_RX_Msk (0x1U << USB_EP5R_DTOG_RX_Pos) /*!< 0x00004000 */ 05281 #define USB_EP5R_DTOG_RX USB_EP5R_DTOG_RX_Msk /*!< Data Toggle, for reception transfers */ 05282 #define USB_EP5R_CTR_RX_Pos (15U) 05283 #define USB_EP5R_CTR_RX_Msk (0x1U << USB_EP5R_CTR_RX_Pos) /*!< 0x00008000 */ 05284 #define USB_EP5R_CTR_RX USB_EP5R_CTR_RX_Msk /*!< Correct Transfer for reception */ 05285 05286 /******************* Bit definition for USB_EP6R register *******************/ 05287 #define USB_EP6R_EA_Pos (0U) 05288 #define USB_EP6R_EA_Msk (0xFU << USB_EP6R_EA_Pos) /*!< 0x0000000F */ 05289 #define USB_EP6R_EA USB_EP6R_EA_Msk /*!< Endpoint Address */ 05290 05291 #define USB_EP6R_STAT_TX_Pos (4U) 05292 #define USB_EP6R_STAT_TX_Msk (0x3U << USB_EP6R_STAT_TX_Pos) /*!< 0x00000030 */ 05293 #define USB_EP6R_STAT_TX USB_EP6R_STAT_TX_Msk /*!< STAT_TX[1:0] bits (Status bits, for transmission transfers) */ 05294 #define USB_EP6R_STAT_TX_0 (0x1U << USB_EP6R_STAT_TX_Pos) /*!< 0x00000010 */ 05295 #define USB_EP6R_STAT_TX_1 (0x2U << USB_EP6R_STAT_TX_Pos) /*!< 0x00000020 */ 05296 05297 #define USB_EP6R_DTOG_TX_Pos (6U) 05298 #define USB_EP6R_DTOG_TX_Msk (0x1U << USB_EP6R_DTOG_TX_Pos) /*!< 0x00000040 */ 05299 #define USB_EP6R_DTOG_TX USB_EP6R_DTOG_TX_Msk /*!< Data Toggle, for transmission transfers */ 05300 #define USB_EP6R_CTR_TX_Pos (7U) 05301 #define USB_EP6R_CTR_TX_Msk (0x1U << USB_EP6R_CTR_TX_Pos) /*!< 0x00000080 */ 05302 #define USB_EP6R_CTR_TX USB_EP6R_CTR_TX_Msk /*!< Correct Transfer for transmission */ 05303 #define USB_EP6R_EP_KIND_Pos (8U) 05304 #define USB_EP6R_EP_KIND_Msk (0x1U << USB_EP6R_EP_KIND_Pos) /*!< 0x00000100 */ 05305 #define USB_EP6R_EP_KIND USB_EP6R_EP_KIND_Msk /*!< Endpoint Kind */ 05306 05307 #define USB_EP6R_EP_TYPE_Pos (9U) 05308 #define USB_EP6R_EP_TYPE_Msk (0x3U << USB_EP6R_EP_TYPE_Pos) /*!< 0x00000600 */ 05309 #define USB_EP6R_EP_TYPE USB_EP6R_EP_TYPE_Msk /*!< EP_TYPE[1:0] bits (Endpoint type) */ 05310 #define USB_EP6R_EP_TYPE_0 (0x1U << USB_EP6R_EP_TYPE_Pos) /*!< 0x00000200 */ 05311 #define USB_EP6R_EP_TYPE_1 (0x2U << USB_EP6R_EP_TYPE_Pos) /*!< 0x00000400 */ 05312 05313 #define USB_EP6R_SETUP_Pos (11U) 05314 #define USB_EP6R_SETUP_Msk (0x1U << USB_EP6R_SETUP_Pos) /*!< 0x00000800 */ 05315 #define USB_EP6R_SETUP USB_EP6R_SETUP_Msk /*!< Setup transaction completed */ 05316 05317 #define USB_EP6R_STAT_RX_Pos (12U) 05318 #define USB_EP6R_STAT_RX_Msk (0x3U << USB_EP6R_STAT_RX_Pos) /*!< 0x00003000 */ 05319 #define USB_EP6R_STAT_RX USB_EP6R_STAT_RX_Msk /*!< STAT_RX[1:0] bits (Status bits, for reception transfers) */ 05320 #define USB_EP6R_STAT_RX_0 (0x1U << USB_EP6R_STAT_RX_Pos) /*!< 0x00001000 */ 05321 #define USB_EP6R_STAT_RX_1 (0x2U << USB_EP6R_STAT_RX_Pos) /*!< 0x00002000 */ 05322 05323 #define USB_EP6R_DTOG_RX_Pos (14U) 05324 #define USB_EP6R_DTOG_RX_Msk (0x1U << USB_EP6R_DTOG_RX_Pos) /*!< 0x00004000 */ 05325 #define USB_EP6R_DTOG_RX USB_EP6R_DTOG_RX_Msk /*!< Data Toggle, for reception transfers */ 05326 #define USB_EP6R_CTR_RX_Pos (15U) 05327 #define USB_EP6R_CTR_RX_Msk (0x1U << USB_EP6R_CTR_RX_Pos) /*!< 0x00008000 */ 05328 #define USB_EP6R_CTR_RX USB_EP6R_CTR_RX_Msk /*!< Correct Transfer for reception */ 05329 05330 /******************* Bit definition for USB_EP7R register *******************/ 05331 #define USB_EP7R_EA_Pos (0U) 05332 #define USB_EP7R_EA_Msk (0xFU << USB_EP7R_EA_Pos) /*!< 0x0000000F */ 05333 #define USB_EP7R_EA USB_EP7R_EA_Msk /*!< Endpoint Address */ 05334 05335 #define USB_EP7R_STAT_TX_Pos (4U) 05336 #define USB_EP7R_STAT_TX_Msk (0x3U << USB_EP7R_STAT_TX_Pos) /*!< 0x00000030 */ 05337 #define USB_EP7R_STAT_TX USB_EP7R_STAT_TX_Msk /*!< STAT_TX[1:0] bits (Status bits, for transmission transfers) */ 05338 #define USB_EP7R_STAT_TX_0 (0x1U << USB_EP7R_STAT_TX_Pos) /*!< 0x00000010 */ 05339 #define USB_EP7R_STAT_TX_1 (0x2U << USB_EP7R_STAT_TX_Pos) /*!< 0x00000020 */ 05340 05341 #define USB_EP7R_DTOG_TX_Pos (6U) 05342 #define USB_EP7R_DTOG_TX_Msk (0x1U << USB_EP7R_DTOG_TX_Pos) /*!< 0x00000040 */ 05343 #define USB_EP7R_DTOG_TX USB_EP7R_DTOG_TX_Msk /*!< Data Toggle, for transmission transfers */ 05344 #define USB_EP7R_CTR_TX_Pos (7U) 05345 #define USB_EP7R_CTR_TX_Msk (0x1U << USB_EP7R_CTR_TX_Pos) /*!< 0x00000080 */ 05346 #define USB_EP7R_CTR_TX USB_EP7R_CTR_TX_Msk /*!< Correct Transfer for transmission */ 05347 #define USB_EP7R_EP_KIND_Pos (8U) 05348 #define USB_EP7R_EP_KIND_Msk (0x1U << USB_EP7R_EP_KIND_Pos) /*!< 0x00000100 */ 05349 #define USB_EP7R_EP_KIND USB_EP7R_EP_KIND_Msk /*!< Endpoint Kind */ 05350 05351 #define USB_EP7R_EP_TYPE_Pos (9U) 05352 #define USB_EP7R_EP_TYPE_Msk (0x3U << USB_EP7R_EP_TYPE_Pos) /*!< 0x00000600 */ 05353 #define USB_EP7R_EP_TYPE USB_EP7R_EP_TYPE_Msk /*!< EP_TYPE[1:0] bits (Endpoint type) */ 05354 #define USB_EP7R_EP_TYPE_0 (0x1U << USB_EP7R_EP_TYPE_Pos) /*!< 0x00000200 */ 05355 #define USB_EP7R_EP_TYPE_1 (0x2U << USB_EP7R_EP_TYPE_Pos) /*!< 0x00000400 */ 05356 05357 #define USB_EP7R_SETUP_Pos (11U) 05358 #define USB_EP7R_SETUP_Msk (0x1U << USB_EP7R_SETUP_Pos) /*!< 0x00000800 */ 05359 #define USB_EP7R_SETUP USB_EP7R_SETUP_Msk /*!< Setup transaction completed */ 05360 05361 #define USB_EP7R_STAT_RX_Pos (12U) 05362 #define USB_EP7R_STAT_RX_Msk (0x3U << USB_EP7R_STAT_RX_Pos) /*!< 0x00003000 */ 05363 #define USB_EP7R_STAT_RX USB_EP7R_STAT_RX_Msk /*!< STAT_RX[1:0] bits (Status bits, for reception transfers) */ 05364 #define USB_EP7R_STAT_RX_0 (0x1U << USB_EP7R_STAT_RX_Pos) /*!< 0x00001000 */ 05365 #define USB_EP7R_STAT_RX_1 (0x2U << USB_EP7R_STAT_RX_Pos) /*!< 0x00002000 */ 05366 05367 #define USB_EP7R_DTOG_RX_Pos (14U) 05368 #define USB_EP7R_DTOG_RX_Msk (0x1U << USB_EP7R_DTOG_RX_Pos) /*!< 0x00004000 */ 05369 #define USB_EP7R_DTOG_RX USB_EP7R_DTOG_RX_Msk /*!< Data Toggle, for reception transfers */ 05370 #define USB_EP7R_CTR_RX_Pos (15U) 05371 #define USB_EP7R_CTR_RX_Msk (0x1U << USB_EP7R_CTR_RX_Pos) /*!< 0x00008000 */ 05372 #define USB_EP7R_CTR_RX USB_EP7R_CTR_RX_Msk /*!< Correct Transfer for reception */ 05373 05374 /*!< Common registers */ 05375 /******************* Bit definition for USB_CNTR register *******************/ 05376 #define USB_CNTR_FRES_Pos (0U) 05377 #define USB_CNTR_FRES_Msk (0x1U << USB_CNTR_FRES_Pos) /*!< 0x00000001 */ 05378 #define USB_CNTR_FRES USB_CNTR_FRES_Msk /*!< Force USB Reset */ 05379 #define USB_CNTR_PDWN_Pos (1U) 05380 #define USB_CNTR_PDWN_Msk (0x1U << USB_CNTR_PDWN_Pos) /*!< 0x00000002 */ 05381 #define USB_CNTR_PDWN USB_CNTR_PDWN_Msk /*!< Power down */ 05382 #define USB_CNTR_LP_MODE_Pos (2U) 05383 #define USB_CNTR_LP_MODE_Msk (0x1U << USB_CNTR_LP_MODE_Pos) /*!< 0x00000004 */ 05384 #define USB_CNTR_LP_MODE USB_CNTR_LP_MODE_Msk /*!< Low-power mode */ 05385 #define USB_CNTR_FSUSP_Pos (3U) 05386 #define USB_CNTR_FSUSP_Msk (0x1U << USB_CNTR_FSUSP_Pos) /*!< 0x00000008 */ 05387 #define USB_CNTR_FSUSP USB_CNTR_FSUSP_Msk /*!< Force suspend */ 05388 #define USB_CNTR_RESUME_Pos (4U) 05389 #define USB_CNTR_RESUME_Msk (0x1U << USB_CNTR_RESUME_Pos) /*!< 0x00000010 */ 05390 #define USB_CNTR_RESUME USB_CNTR_RESUME_Msk /*!< Resume request */ 05391 #define USB_CNTR_ESOFM_Pos (8U) 05392 #define USB_CNTR_ESOFM_Msk (0x1U << USB_CNTR_ESOFM_Pos) /*!< 0x00000100 */ 05393 #define USB_CNTR_ESOFM USB_CNTR_ESOFM_Msk /*!< Expected Start Of Frame Interrupt Mask */ 05394 #define USB_CNTR_SOFM_Pos (9U) 05395 #define USB_CNTR_SOFM_Msk (0x1U << USB_CNTR_SOFM_Pos) /*!< 0x00000200 */ 05396 #define USB_CNTR_SOFM USB_CNTR_SOFM_Msk /*!< Start Of Frame Interrupt Mask */ 05397 #define USB_CNTR_RESETM_Pos (10U) 05398 #define USB_CNTR_RESETM_Msk (0x1U << USB_CNTR_RESETM_Pos) /*!< 0x00000400 */ 05399 #define USB_CNTR_RESETM USB_CNTR_RESETM_Msk /*!< RESET Interrupt Mask */ 05400 #define USB_CNTR_SUSPM_Pos (11U) 05401 #define USB_CNTR_SUSPM_Msk (0x1U << USB_CNTR_SUSPM_Pos) /*!< 0x00000800 */ 05402 #define USB_CNTR_SUSPM USB_CNTR_SUSPM_Msk /*!< Suspend mode Interrupt Mask */ 05403 #define USB_CNTR_WKUPM_Pos (12U) 05404 #define USB_CNTR_WKUPM_Msk (0x1U << USB_CNTR_WKUPM_Pos) /*!< 0x00001000 */ 05405 #define USB_CNTR_WKUPM USB_CNTR_WKUPM_Msk /*!< Wakeup Interrupt Mask */ 05406 #define USB_CNTR_ERRM_Pos (13U) 05407 #define USB_CNTR_ERRM_Msk (0x1U << USB_CNTR_ERRM_Pos) /*!< 0x00002000 */ 05408 #define USB_CNTR_ERRM USB_CNTR_ERRM_Msk /*!< Error Interrupt Mask */ 05409 #define USB_CNTR_PMAOVRM_Pos (14U) 05410 #define USB_CNTR_PMAOVRM_Msk (0x1U << USB_CNTR_PMAOVRM_Pos) /*!< 0x00004000 */ 05411 #define USB_CNTR_PMAOVRM USB_CNTR_PMAOVRM_Msk /*!< Packet Memory Area Over / Underrun Interrupt Mask */ 05412 #define USB_CNTR_CTRM_Pos (15U) 05413 #define USB_CNTR_CTRM_Msk (0x1U << USB_CNTR_CTRM_Pos) /*!< 0x00008000 */ 05414 #define USB_CNTR_CTRM USB_CNTR_CTRM_Msk /*!< Correct Transfer Interrupt Mask */ 05415 05416 /******************* Bit definition for USB_ISTR register *******************/ 05417 #define USB_ISTR_EP_ID_Pos (0U) 05418 #define USB_ISTR_EP_ID_Msk (0xFU << USB_ISTR_EP_ID_Pos) /*!< 0x0000000F */ 05419 #define USB_ISTR_EP_ID USB_ISTR_EP_ID_Msk /*!< Endpoint Identifier */ 05420 #define USB_ISTR_DIR_Pos (4U) 05421 #define USB_ISTR_DIR_Msk (0x1U << USB_ISTR_DIR_Pos) /*!< 0x00000010 */ 05422 #define USB_ISTR_DIR USB_ISTR_DIR_Msk /*!< Direction of transaction */ 05423 #define USB_ISTR_ESOF_Pos (8U) 05424 #define USB_ISTR_ESOF_Msk (0x1U << USB_ISTR_ESOF_Pos) /*!< 0x00000100 */ 05425 #define USB_ISTR_ESOF USB_ISTR_ESOF_Msk /*!< Expected Start Of Frame */ 05426 #define USB_ISTR_SOF_Pos (9U) 05427 #define USB_ISTR_SOF_Msk (0x1U << USB_ISTR_SOF_Pos) /*!< 0x00000200 */ 05428 #define USB_ISTR_SOF USB_ISTR_SOF_Msk /*!< Start Of Frame */ 05429 #define USB_ISTR_RESET_Pos (10U) 05430 #define USB_ISTR_RESET_Msk (0x1U << USB_ISTR_RESET_Pos) /*!< 0x00000400 */ 05431 #define USB_ISTR_RESET USB_ISTR_RESET_Msk /*!< USB RESET request */ 05432 #define USB_ISTR_SUSP_Pos (11U) 05433 #define USB_ISTR_SUSP_Msk (0x1U << USB_ISTR_SUSP_Pos) /*!< 0x00000800 */ 05434 #define USB_ISTR_SUSP USB_ISTR_SUSP_Msk /*!< Suspend mode request */ 05435 #define USB_ISTR_WKUP_Pos (12U) 05436 #define USB_ISTR_WKUP_Msk (0x1U << USB_ISTR_WKUP_Pos) /*!< 0x00001000 */ 05437 #define USB_ISTR_WKUP USB_ISTR_WKUP_Msk /*!< Wake up */ 05438 #define USB_ISTR_ERR_Pos (13U) 05439 #define USB_ISTR_ERR_Msk (0x1U << USB_ISTR_ERR_Pos) /*!< 0x00002000 */ 05440 #define USB_ISTR_ERR USB_ISTR_ERR_Msk /*!< Error */ 05441 #define USB_ISTR_PMAOVR_Pos (14U) 05442 #define USB_ISTR_PMAOVR_Msk (0x1U << USB_ISTR_PMAOVR_Pos) /*!< 0x00004000 */ 05443 #define USB_ISTR_PMAOVR USB_ISTR_PMAOVR_Msk /*!< Packet Memory Area Over / Underrun */ 05444 #define USB_ISTR_CTR_Pos (15U) 05445 #define USB_ISTR_CTR_Msk (0x1U << USB_ISTR_CTR_Pos) /*!< 0x00008000 */ 05446 #define USB_ISTR_CTR USB_ISTR_CTR_Msk /*!< Correct Transfer */ 05447 05448 /******************* Bit definition for USB_FNR register ********************/ 05449 #define USB_FNR_FN_Pos (0U) 05450 #define USB_FNR_FN_Msk (0x7FFU << USB_FNR_FN_Pos) /*!< 0x000007FF */ 05451 #define USB_FNR_FN USB_FNR_FN_Msk /*!< Frame Number */ 05452 #define USB_FNR_LSOF_Pos (11U) 05453 #define USB_FNR_LSOF_Msk (0x3U << USB_FNR_LSOF_Pos) /*!< 0x00001800 */ 05454 #define USB_FNR_LSOF USB_FNR_LSOF_Msk /*!< Lost SOF */ 05455 #define USB_FNR_LCK_Pos (13U) 05456 #define USB_FNR_LCK_Msk (0x1U << USB_FNR_LCK_Pos) /*!< 0x00002000 */ 05457 #define USB_FNR_LCK USB_FNR_LCK_Msk /*!< Locked */ 05458 #define USB_FNR_RXDM_Pos (14U) 05459 #define USB_FNR_RXDM_Msk (0x1U << USB_FNR_RXDM_Pos) /*!< 0x00004000 */ 05460 #define USB_FNR_RXDM USB_FNR_RXDM_Msk /*!< Receive Data - Line Status */ 05461 #define USB_FNR_RXDP_Pos (15U) 05462 #define USB_FNR_RXDP_Msk (0x1U << USB_FNR_RXDP_Pos) /*!< 0x00008000 */ 05463 #define USB_FNR_RXDP USB_FNR_RXDP_Msk /*!< Receive Data + Line Status */ 05464 05465 /****************** Bit definition for USB_DADDR register *******************/ 05466 #define USB_DADDR_ADD_Pos (0U) 05467 #define USB_DADDR_ADD_Msk (0x7FU << USB_DADDR_ADD_Pos) /*!< 0x0000007F */ 05468 #define USB_DADDR_ADD USB_DADDR_ADD_Msk /*!< ADD[6:0] bits (Device Address) */ 05469 #define USB_DADDR_ADD0_Pos (0U) 05470 #define USB_DADDR_ADD0_Msk (0x1U << USB_DADDR_ADD0_Pos) /*!< 0x00000001 */ 05471 #define USB_DADDR_ADD0 USB_DADDR_ADD0_Msk /*!< Bit 0 */ 05472 #define USB_DADDR_ADD1_Pos (1U) 05473 #define USB_DADDR_ADD1_Msk (0x1U << USB_DADDR_ADD1_Pos) /*!< 0x00000002 */ 05474 #define USB_DADDR_ADD1 USB_DADDR_ADD1_Msk /*!< Bit 1 */ 05475 #define USB_DADDR_ADD2_Pos (2U) 05476 #define USB_DADDR_ADD2_Msk (0x1U << USB_DADDR_ADD2_Pos) /*!< 0x00000004 */ 05477 #define USB_DADDR_ADD2 USB_DADDR_ADD2_Msk /*!< Bit 2 */ 05478 #define USB_DADDR_ADD3_Pos (3U) 05479 #define USB_DADDR_ADD3_Msk (0x1U << USB_DADDR_ADD3_Pos) /*!< 0x00000008 */ 05480 #define USB_DADDR_ADD3 USB_DADDR_ADD3_Msk /*!< Bit 3 */ 05481 #define USB_DADDR_ADD4_Pos (4U) 05482 #define USB_DADDR_ADD4_Msk (0x1U << USB_DADDR_ADD4_Pos) /*!< 0x00000010 */ 05483 #define USB_DADDR_ADD4 USB_DADDR_ADD4_Msk /*!< Bit 4 */ 05484 #define USB_DADDR_ADD5_Pos (5U) 05485 #define USB_DADDR_ADD5_Msk (0x1U << USB_DADDR_ADD5_Pos) /*!< 0x00000020 */ 05486 #define USB_DADDR_ADD5 USB_DADDR_ADD5_Msk /*!< Bit 5 */ 05487 #define USB_DADDR_ADD6_Pos (6U) 05488 #define USB_DADDR_ADD6_Msk (0x1U << USB_DADDR_ADD6_Pos) /*!< 0x00000040 */ 05489 #define USB_DADDR_ADD6 USB_DADDR_ADD6_Msk /*!< Bit 6 */ 05490 05491 #define USB_DADDR_EF_Pos (7U) 05492 #define USB_DADDR_EF_Msk (0x1U << USB_DADDR_EF_Pos) /*!< 0x00000080 */ 05493 #define USB_DADDR_EF USB_DADDR_EF_Msk /*!< Enable Function */ 05494 05495 /****************** Bit definition for USB_BTABLE register ******************/ 05496 #define USB_BTABLE_BTABLE_Pos (3U) 05497 #define USB_BTABLE_BTABLE_Msk (0x1FFFU << USB_BTABLE_BTABLE_Pos) /*!< 0x0000FFF8 */ 05498 #define USB_BTABLE_BTABLE USB_BTABLE_BTABLE_Msk /*!< Buffer Table */ 05499 05500 /*!< Buffer descriptor table */ 05501 /***************** Bit definition for USB_ADDR0_TX register *****************/ 05502 #define USB_ADDR0_TX_ADDR0_TX_Pos (1U) 05503 #define USB_ADDR0_TX_ADDR0_TX_Msk (0x7FFFU << USB_ADDR0_TX_ADDR0_TX_Pos) /*!< 0x0000FFFE */ 05504 #define USB_ADDR0_TX_ADDR0_TX USB_ADDR0_TX_ADDR0_TX_Msk /*!< Transmission Buffer Address 0 */ 05505 05506 /***************** Bit definition for USB_ADDR1_TX register *****************/ 05507 #define USB_ADDR1_TX_ADDR1_TX_Pos (1U) 05508 #define USB_ADDR1_TX_ADDR1_TX_Msk (0x7FFFU << USB_ADDR1_TX_ADDR1_TX_Pos) /*!< 0x0000FFFE */ 05509 #define USB_ADDR1_TX_ADDR1_TX USB_ADDR1_TX_ADDR1_TX_Msk /*!< Transmission Buffer Address 1 */ 05510 05511 /***************** Bit definition for USB_ADDR2_TX register *****************/ 05512 #define USB_ADDR2_TX_ADDR2_TX_Pos (1U) 05513 #define USB_ADDR2_TX_ADDR2_TX_Msk (0x7FFFU << USB_ADDR2_TX_ADDR2_TX_Pos) /*!< 0x0000FFFE */ 05514 #define USB_ADDR2_TX_ADDR2_TX USB_ADDR2_TX_ADDR2_TX_Msk /*!< Transmission Buffer Address 2 */ 05515 05516 /***************** Bit definition for USB_ADDR3_TX register *****************/ 05517 #define USB_ADDR3_TX_ADDR3_TX_Pos (1U) 05518 #define USB_ADDR3_TX_ADDR3_TX_Msk (0x7FFFU << USB_ADDR3_TX_ADDR3_TX_Pos) /*!< 0x0000FFFE */ 05519 #define USB_ADDR3_TX_ADDR3_TX USB_ADDR3_TX_ADDR3_TX_Msk /*!< Transmission Buffer Address 3 */ 05520 05521 /***************** Bit definition for USB_ADDR4_TX register *****************/ 05522 #define USB_ADDR4_TX_ADDR4_TX_Pos (1U) 05523 #define USB_ADDR4_TX_ADDR4_TX_Msk (0x7FFFU << USB_ADDR4_TX_ADDR4_TX_Pos) /*!< 0x0000FFFE */ 05524 #define USB_ADDR4_TX_ADDR4_TX USB_ADDR4_TX_ADDR4_TX_Msk /*!< Transmission Buffer Address 4 */ 05525 05526 /***************** Bit definition for USB_ADDR5_TX register *****************/ 05527 #define USB_ADDR5_TX_ADDR5_TX_Pos (1U) 05528 #define USB_ADDR5_TX_ADDR5_TX_Msk (0x7FFFU << USB_ADDR5_TX_ADDR5_TX_Pos) /*!< 0x0000FFFE */ 05529 #define USB_ADDR5_TX_ADDR5_TX USB_ADDR5_TX_ADDR5_TX_Msk /*!< Transmission Buffer Address 5 */ 05530 05531 /***************** Bit definition for USB_ADDR6_TX register *****************/ 05532 #define USB_ADDR6_TX_ADDR6_TX_Pos (1U) 05533 #define USB_ADDR6_TX_ADDR6_TX_Msk (0x7FFFU << USB_ADDR6_TX_ADDR6_TX_Pos) /*!< 0x0000FFFE */ 05534 #define USB_ADDR6_TX_ADDR6_TX USB_ADDR6_TX_ADDR6_TX_Msk /*!< Transmission Buffer Address 6 */ 05535 05536 /***************** Bit definition for USB_ADDR7_TX register *****************/ 05537 #define USB_ADDR7_TX_ADDR7_TX_Pos (1U) 05538 #define USB_ADDR7_TX_ADDR7_TX_Msk (0x7FFFU << USB_ADDR7_TX_ADDR7_TX_Pos) /*!< 0x0000FFFE */ 05539 #define USB_ADDR7_TX_ADDR7_TX USB_ADDR7_TX_ADDR7_TX_Msk /*!< Transmission Buffer Address 7 */ 05540 05541 /*----------------------------------------------------------------------------*/ 05542 05543 /***************** Bit definition for USB_COUNT0_TX register ****************/ 05544 #define USB_COUNT0_TX_COUNT0_TX_Pos (0U) 05545 #define USB_COUNT0_TX_COUNT0_TX_Msk (0x3FFU << USB_COUNT0_TX_COUNT0_TX_Pos) /*!< 0x000003FF */ 05546 #define USB_COUNT0_TX_COUNT0_TX USB_COUNT0_TX_COUNT0_TX_Msk /*!< Transmission Byte Count 0 */ 05547 05548 /***************** Bit definition for USB_COUNT1_TX register ****************/ 05549 #define USB_COUNT1_TX_COUNT1_TX_Pos (0U) 05550 #define USB_COUNT1_TX_COUNT1_TX_Msk (0x3FFU << USB_COUNT1_TX_COUNT1_TX_Pos) /*!< 0x000003FF */ 05551 #define USB_COUNT1_TX_COUNT1_TX USB_COUNT1_TX_COUNT1_TX_Msk /*!< Transmission Byte Count 1 */ 05552 05553 /***************** Bit definition for USB_COUNT2_TX register ****************/ 05554 #define USB_COUNT2_TX_COUNT2_TX_Pos (0U) 05555 #define USB_COUNT2_TX_COUNT2_TX_Msk (0x3FFU << USB_COUNT2_TX_COUNT2_TX_Pos) /*!< 0x000003FF */ 05556 #define USB_COUNT2_TX_COUNT2_TX USB_COUNT2_TX_COUNT2_TX_Msk /*!< Transmission Byte Count 2 */ 05557 05558 /***************** Bit definition for USB_COUNT3_TX register ****************/ 05559 #define USB_COUNT3_TX_COUNT3_TX_Pos (0U) 05560 #define USB_COUNT3_TX_COUNT3_TX_Msk (0x3FFU << USB_COUNT3_TX_COUNT3_TX_Pos) /*!< 0x000003FF */ 05561 #define USB_COUNT3_TX_COUNT3_TX USB_COUNT3_TX_COUNT3_TX_Msk /*!< Transmission Byte Count 3 */ 05562 05563 /***************** Bit definition for USB_COUNT4_TX register ****************/ 05564 #define USB_COUNT4_TX_COUNT4_TX_Pos (0U) 05565 #define USB_COUNT4_TX_COUNT4_TX_Msk (0x3FFU << USB_COUNT4_TX_COUNT4_TX_Pos) /*!< 0x000003FF */ 05566 #define USB_COUNT4_TX_COUNT4_TX USB_COUNT4_TX_COUNT4_TX_Msk /*!< Transmission Byte Count 4 */ 05567 05568 /***************** Bit definition for USB_COUNT5_TX register ****************/ 05569 #define USB_COUNT5_TX_COUNT5_TX_Pos (0U) 05570 #define USB_COUNT5_TX_COUNT5_TX_Msk (0x3FFU << USB_COUNT5_TX_COUNT5_TX_Pos) /*!< 0x000003FF */ 05571 #define USB_COUNT5_TX_COUNT5_TX USB_COUNT5_TX_COUNT5_TX_Msk /*!< Transmission Byte Count 5 */ 05572 05573 /***************** Bit definition for USB_COUNT6_TX register ****************/ 05574 #define USB_COUNT6_TX_COUNT6_TX_Pos (0U) 05575 #define USB_COUNT6_TX_COUNT6_TX_Msk (0x3FFU << USB_COUNT6_TX_COUNT6_TX_Pos) /*!< 0x000003FF */ 05576 #define USB_COUNT6_TX_COUNT6_TX USB_COUNT6_TX_COUNT6_TX_Msk /*!< Transmission Byte Count 6 */ 05577 05578 /***************** Bit definition for USB_COUNT7_TX register ****************/ 05579 #define USB_COUNT7_TX_COUNT7_TX_Pos (0U) 05580 #define USB_COUNT7_TX_COUNT7_TX_Msk (0x3FFU << USB_COUNT7_TX_COUNT7_TX_Pos) /*!< 0x000003FF */ 05581 #define USB_COUNT7_TX_COUNT7_TX USB_COUNT7_TX_COUNT7_TX_Msk /*!< Transmission Byte Count 7 */ 05582 05583 /*----------------------------------------------------------------------------*/ 05584 05585 /**************** Bit definition for USB_COUNT0_TX_0 register ***************/ 05586 #define USB_COUNT0_TX_0_COUNT0_TX_0 ((uint32_t)0x000003FF) /*!< Transmission Byte Count 0 (low) */ 05587 05588 /**************** Bit definition for USB_COUNT0_TX_1 register ***************/ 05589 #define USB_COUNT0_TX_1_COUNT0_TX_1 ((uint32_t)0x03FF0000) /*!< Transmission Byte Count 0 (high) */ 05590 05591 /**************** Bit definition for USB_COUNT1_TX_0 register ***************/ 05592 #define USB_COUNT1_TX_0_COUNT1_TX_0 ((uint32_t)0x000003FF) /*!< Transmission Byte Count 1 (low) */ 05593 05594 /**************** Bit definition for USB_COUNT1_TX_1 register ***************/ 05595 #define USB_COUNT1_TX_1_COUNT1_TX_1 ((uint32_t)0x03FF0000) /*!< Transmission Byte Count 1 (high) */ 05596 05597 /**************** Bit definition for USB_COUNT2_TX_0 register ***************/ 05598 #define USB_COUNT2_TX_0_COUNT2_TX_0 ((uint32_t)0x000003FF) /*!< Transmission Byte Count 2 (low) */ 05599 05600 /**************** Bit definition for USB_COUNT2_TX_1 register ***************/ 05601 #define USB_COUNT2_TX_1_COUNT2_TX_1 ((uint32_t)0x03FF0000) /*!< Transmission Byte Count 2 (high) */ 05602 05603 /**************** Bit definition for USB_COUNT3_TX_0 register ***************/ 05604 #define USB_COUNT3_TX_0_COUNT3_TX_0 ((uint32_t)0x000003FF) /*!< Transmission Byte Count 3 (low) */ 05605 05606 /**************** Bit definition for USB_COUNT3_TX_1 register ***************/ 05607 #define USB_COUNT3_TX_1_COUNT3_TX_1 ((uint32_t)0x03FF0000) /*!< Transmission Byte Count 3 (high) */ 05608 05609 /**************** Bit definition for USB_COUNT4_TX_0 register ***************/ 05610 #define USB_COUNT4_TX_0_COUNT4_TX_0 ((uint32_t)0x000003FF) /*!< Transmission Byte Count 4 (low) */ 05611 05612 /**************** Bit definition for USB_COUNT4_TX_1 register ***************/ 05613 #define USB_COUNT4_TX_1_COUNT4_TX_1 ((uint32_t)0x03FF0000) /*!< Transmission Byte Count 4 (high) */ 05614 05615 /**************** Bit definition for USB_COUNT5_TX_0 register ***************/ 05616 #define USB_COUNT5_TX_0_COUNT5_TX_0 ((uint32_t)0x000003FF) /*!< Transmission Byte Count 5 (low) */ 05617 05618 /**************** Bit definition for USB_COUNT5_TX_1 register ***************/ 05619 #define USB_COUNT5_TX_1_COUNT5_TX_1 ((uint32_t)0x03FF0000) /*!< Transmission Byte Count 5 (high) */ 05620 05621 /**************** Bit definition for USB_COUNT6_TX_0 register ***************/ 05622 #define USB_COUNT6_TX_0_COUNT6_TX_0 ((uint32_t)0x000003FF) /*!< Transmission Byte Count 6 (low) */ 05623 05624 /**************** Bit definition for USB_COUNT6_TX_1 register ***************/ 05625 #define USB_COUNT6_TX_1_COUNT6_TX_1 ((uint32_t)0x03FF0000) /*!< Transmission Byte Count 6 (high) */ 05626 05627 /**************** Bit definition for USB_COUNT7_TX_0 register ***************/ 05628 #define USB_COUNT7_TX_0_COUNT7_TX_0 ((uint32_t)0x000003FF) /*!< Transmission Byte Count 7 (low) */ 05629 05630 /**************** Bit definition for USB_COUNT7_TX_1 register ***************/ 05631 #define USB_COUNT7_TX_1_COUNT7_TX_1 ((uint32_t)0x03FF0000) /*!< Transmission Byte Count 7 (high) */ 05632 05633 /*----------------------------------------------------------------------------*/ 05634 05635 /***************** Bit definition for USB_ADDR0_RX register *****************/ 05636 #define USB_ADDR0_RX_ADDR0_RX_Pos (1U) 05637 #define USB_ADDR0_RX_ADDR0_RX_Msk (0x7FFFU << USB_ADDR0_RX_ADDR0_RX_Pos) /*!< 0x0000FFFE */ 05638 #define USB_ADDR0_RX_ADDR0_RX USB_ADDR0_RX_ADDR0_RX_Msk /*!< Reception Buffer Address 0 */ 05639 05640 /***************** Bit definition for USB_ADDR1_RX register *****************/ 05641 #define USB_ADDR1_RX_ADDR1_RX_Pos (1U) 05642 #define USB_ADDR1_RX_ADDR1_RX_Msk (0x7FFFU << USB_ADDR1_RX_ADDR1_RX_Pos) /*!< 0x0000FFFE */ 05643 #define USB_ADDR1_RX_ADDR1_RX USB_ADDR1_RX_ADDR1_RX_Msk /*!< Reception Buffer Address 1 */ 05644 05645 /***************** Bit definition for USB_ADDR2_RX register *****************/ 05646 #define USB_ADDR2_RX_ADDR2_RX_Pos (1U) 05647 #define USB_ADDR2_RX_ADDR2_RX_Msk (0x7FFFU << USB_ADDR2_RX_ADDR2_RX_Pos) /*!< 0x0000FFFE */ 05648 #define USB_ADDR2_RX_ADDR2_RX USB_ADDR2_RX_ADDR2_RX_Msk /*!< Reception Buffer Address 2 */ 05649 05650 /***************** Bit definition for USB_ADDR3_RX register *****************/ 05651 #define USB_ADDR3_RX_ADDR3_RX_Pos (1U) 05652 #define USB_ADDR3_RX_ADDR3_RX_Msk (0x7FFFU << USB_ADDR3_RX_ADDR3_RX_Pos) /*!< 0x0000FFFE */ 05653 #define USB_ADDR3_RX_ADDR3_RX USB_ADDR3_RX_ADDR3_RX_Msk /*!< Reception Buffer Address 3 */ 05654 05655 /***************** Bit definition for USB_ADDR4_RX register *****************/ 05656 #define USB_ADDR4_RX_ADDR4_RX_Pos (1U) 05657 #define USB_ADDR4_RX_ADDR4_RX_Msk (0x7FFFU << USB_ADDR4_RX_ADDR4_RX_Pos) /*!< 0x0000FFFE */ 05658 #define USB_ADDR4_RX_ADDR4_RX USB_ADDR4_RX_ADDR4_RX_Msk /*!< Reception Buffer Address 4 */ 05659 05660 /***************** Bit definition for USB_ADDR5_RX register *****************/ 05661 #define USB_ADDR5_RX_ADDR5_RX_Pos (1U) 05662 #define USB_ADDR5_RX_ADDR5_RX_Msk (0x7FFFU << USB_ADDR5_RX_ADDR5_RX_Pos) /*!< 0x0000FFFE */ 05663 #define USB_ADDR5_RX_ADDR5_RX USB_ADDR5_RX_ADDR5_RX_Msk /*!< Reception Buffer Address 5 */ 05664 05665 /***************** Bit definition for USB_ADDR6_RX register *****************/ 05666 #define USB_ADDR6_RX_ADDR6_RX_Pos (1U) 05667 #define USB_ADDR6_RX_ADDR6_RX_Msk (0x7FFFU << USB_ADDR6_RX_ADDR6_RX_Pos) /*!< 0x0000FFFE */ 05668 #define USB_ADDR6_RX_ADDR6_RX USB_ADDR6_RX_ADDR6_RX_Msk /*!< Reception Buffer Address 6 */ 05669 05670 /***************** Bit definition for USB_ADDR7_RX register *****************/ 05671 #define USB_ADDR7_RX_ADDR7_RX_Pos (1U) 05672 #define USB_ADDR7_RX_ADDR7_RX_Msk (0x7FFFU << USB_ADDR7_RX_ADDR7_RX_Pos) /*!< 0x0000FFFE */ 05673 #define USB_ADDR7_RX_ADDR7_RX USB_ADDR7_RX_ADDR7_RX_Msk /*!< Reception Buffer Address 7 */ 05674 05675 /*----------------------------------------------------------------------------*/ 05676 05677 /***************** Bit definition for USB_COUNT0_RX register ****************/ 05678 #define USB_COUNT0_RX_COUNT0_RX_Pos (0U) 05679 #define USB_COUNT0_RX_COUNT0_RX_Msk (0x3FFU << USB_COUNT0_RX_COUNT0_RX_Pos) /*!< 0x000003FF */ 05680 #define USB_COUNT0_RX_COUNT0_RX USB_COUNT0_RX_COUNT0_RX_Msk /*!< Reception Byte Count */ 05681 05682 #define USB_COUNT0_RX_NUM_BLOCK_Pos (10U) 05683 #define USB_COUNT0_RX_NUM_BLOCK_Msk (0x1FU << USB_COUNT0_RX_NUM_BLOCK_Pos) /*!< 0x00007C00 */ 05684 #define USB_COUNT0_RX_NUM_BLOCK USB_COUNT0_RX_NUM_BLOCK_Msk /*!< NUM_BLOCK[4:0] bits (Number of blocks) */ 05685 #define USB_COUNT0_RX_NUM_BLOCK_0 (0x01U << USB_COUNT0_RX_NUM_BLOCK_Pos) /*!< 0x00000400 */ 05686 #define USB_COUNT0_RX_NUM_BLOCK_1 (0x02U << USB_COUNT0_RX_NUM_BLOCK_Pos) /*!< 0x00000800 */ 05687 #define USB_COUNT0_RX_NUM_BLOCK_2 (0x04U << USB_COUNT0_RX_NUM_BLOCK_Pos) /*!< 0x00001000 */ 05688 #define USB_COUNT0_RX_NUM_BLOCK_3 (0x08U << USB_COUNT0_RX_NUM_BLOCK_Pos) /*!< 0x00002000 */ 05689 #define USB_COUNT0_RX_NUM_BLOCK_4 (0x10U << USB_COUNT0_RX_NUM_BLOCK_Pos) /*!< 0x00004000 */ 05690 05691 #define USB_COUNT0_RX_BLSIZE_Pos (15U) 05692 #define USB_COUNT0_RX_BLSIZE_Msk (0x1U << USB_COUNT0_RX_BLSIZE_Pos) /*!< 0x00008000 */ 05693 #define USB_COUNT0_RX_BLSIZE USB_COUNT0_RX_BLSIZE_Msk /*!< BLock SIZE */ 05694 05695 /***************** Bit definition for USB_COUNT1_RX register ****************/ 05696 #define USB_COUNT1_RX_COUNT1_RX_Pos (0U) 05697 #define USB_COUNT1_RX_COUNT1_RX_Msk (0x3FFU << USB_COUNT1_RX_COUNT1_RX_Pos) /*!< 0x000003FF */ 05698 #define USB_COUNT1_RX_COUNT1_RX USB_COUNT1_RX_COUNT1_RX_Msk /*!< Reception Byte Count */ 05699 05700 #define USB_COUNT1_RX_NUM_BLOCK_Pos (10U) 05701 #define USB_COUNT1_RX_NUM_BLOCK_Msk (0x1FU << USB_COUNT1_RX_NUM_BLOCK_Pos) /*!< 0x00007C00 */ 05702 #define USB_COUNT1_RX_NUM_BLOCK USB_COUNT1_RX_NUM_BLOCK_Msk /*!< NUM_BLOCK[4:0] bits (Number of blocks) */ 05703 #define USB_COUNT1_RX_NUM_BLOCK_0 (0x01U << USB_COUNT1_RX_NUM_BLOCK_Pos) /*!< 0x00000400 */ 05704 #define USB_COUNT1_RX_NUM_BLOCK_1 (0x02U << USB_COUNT1_RX_NUM_BLOCK_Pos) /*!< 0x00000800 */ 05705 #define USB_COUNT1_RX_NUM_BLOCK_2 (0x04U << USB_COUNT1_RX_NUM_BLOCK_Pos) /*!< 0x00001000 */ 05706 #define USB_COUNT1_RX_NUM_BLOCK_3 (0x08U << USB_COUNT1_RX_NUM_BLOCK_Pos) /*!< 0x00002000 */ 05707 #define USB_COUNT1_RX_NUM_BLOCK_4 (0x10U << USB_COUNT1_RX_NUM_BLOCK_Pos) /*!< 0x00004000 */ 05708 05709 #define USB_COUNT1_RX_BLSIZE_Pos (15U) 05710 #define USB_COUNT1_RX_BLSIZE_Msk (0x1U << USB_COUNT1_RX_BLSIZE_Pos) /*!< 0x00008000 */ 05711 #define USB_COUNT1_RX_BLSIZE USB_COUNT1_RX_BLSIZE_Msk /*!< BLock SIZE */ 05712 05713 /***************** Bit definition for USB_COUNT2_RX register ****************/ 05714 #define USB_COUNT2_RX_COUNT2_RX_Pos (0U) 05715 #define USB_COUNT2_RX_COUNT2_RX_Msk (0x3FFU << USB_COUNT2_RX_COUNT2_RX_Pos) /*!< 0x000003FF */ 05716 #define USB_COUNT2_RX_COUNT2_RX USB_COUNT2_RX_COUNT2_RX_Msk /*!< Reception Byte Count */ 05717 05718 #define USB_COUNT2_RX_NUM_BLOCK_Pos (10U) 05719 #define USB_COUNT2_RX_NUM_BLOCK_Msk (0x1FU << USB_COUNT2_RX_NUM_BLOCK_Pos) /*!< 0x00007C00 */ 05720 #define USB_COUNT2_RX_NUM_BLOCK USB_COUNT2_RX_NUM_BLOCK_Msk /*!< NUM_BLOCK[4:0] bits (Number of blocks) */ 05721 #define USB_COUNT2_RX_NUM_BLOCK_0 (0x01U << USB_COUNT2_RX_NUM_BLOCK_Pos) /*!< 0x00000400 */ 05722 #define USB_COUNT2_RX_NUM_BLOCK_1 (0x02U << USB_COUNT2_RX_NUM_BLOCK_Pos) /*!< 0x00000800 */ 05723 #define USB_COUNT2_RX_NUM_BLOCK_2 (0x04U << USB_COUNT2_RX_NUM_BLOCK_Pos) /*!< 0x00001000 */ 05724 #define USB_COUNT2_RX_NUM_BLOCK_3 (0x08U << USB_COUNT2_RX_NUM_BLOCK_Pos) /*!< 0x00002000 */ 05725 #define USB_COUNT2_RX_NUM_BLOCK_4 (0x10U << USB_COUNT2_RX_NUM_BLOCK_Pos) /*!< 0x00004000 */ 05726 05727 #define USB_COUNT2_RX_BLSIZE_Pos (15U) 05728 #define USB_COUNT2_RX_BLSIZE_Msk (0x1U << USB_COUNT2_RX_BLSIZE_Pos) /*!< 0x00008000 */ 05729 #define USB_COUNT2_RX_BLSIZE USB_COUNT2_RX_BLSIZE_Msk /*!< BLock SIZE */ 05730 05731 /***************** Bit definition for USB_COUNT3_RX register ****************/ 05732 #define USB_COUNT3_RX_COUNT3_RX_Pos (0U) 05733 #define USB_COUNT3_RX_COUNT3_RX_Msk (0x3FFU << USB_COUNT3_RX_COUNT3_RX_Pos) /*!< 0x000003FF */ 05734 #define USB_COUNT3_RX_COUNT3_RX USB_COUNT3_RX_COUNT3_RX_Msk /*!< Reception Byte Count */ 05735 05736 #define USB_COUNT3_RX_NUM_BLOCK_Pos (10U) 05737 #define USB_COUNT3_RX_NUM_BLOCK_Msk (0x1FU << USB_COUNT3_RX_NUM_BLOCK_Pos) /*!< 0x00007C00 */ 05738 #define USB_COUNT3_RX_NUM_BLOCK USB_COUNT3_RX_NUM_BLOCK_Msk /*!< NUM_BLOCK[4:0] bits (Number of blocks) */ 05739 #define USB_COUNT3_RX_NUM_BLOCK_0 (0x01U << USB_COUNT3_RX_NUM_BLOCK_Pos) /*!< 0x00000400 */ 05740 #define USB_COUNT3_RX_NUM_BLOCK_1 (0x02U << USB_COUNT3_RX_NUM_BLOCK_Pos) /*!< 0x00000800 */ 05741 #define USB_COUNT3_RX_NUM_BLOCK_2 (0x04U << USB_COUNT3_RX_NUM_BLOCK_Pos) /*!< 0x00001000 */ 05742 #define USB_COUNT3_RX_NUM_BLOCK_3 (0x08U << USB_COUNT3_RX_NUM_BLOCK_Pos) /*!< 0x00002000 */ 05743 #define USB_COUNT3_RX_NUM_BLOCK_4 (0x10U << USB_COUNT3_RX_NUM_BLOCK_Pos) /*!< 0x00004000 */ 05744 05745 #define USB_COUNT3_RX_BLSIZE_Pos (15U) 05746 #define USB_COUNT3_RX_BLSIZE_Msk (0x1U << USB_COUNT3_RX_BLSIZE_Pos) /*!< 0x00008000 */ 05747 #define USB_COUNT3_RX_BLSIZE USB_COUNT3_RX_BLSIZE_Msk /*!< BLock SIZE */ 05748 05749 /***************** Bit definition for USB_COUNT4_RX register ****************/ 05750 #define USB_COUNT4_RX_COUNT4_RX_Pos (0U) 05751 #define USB_COUNT4_RX_COUNT4_RX_Msk (0x3FFU << USB_COUNT4_RX_COUNT4_RX_Pos) /*!< 0x000003FF */ 05752 #define USB_COUNT4_RX_COUNT4_RX USB_COUNT4_RX_COUNT4_RX_Msk /*!< Reception Byte Count */ 05753 05754 #define USB_COUNT4_RX_NUM_BLOCK_Pos (10U) 05755 #define USB_COUNT4_RX_NUM_BLOCK_Msk (0x1FU << USB_COUNT4_RX_NUM_BLOCK_Pos) /*!< 0x00007C00 */ 05756 #define USB_COUNT4_RX_NUM_BLOCK USB_COUNT4_RX_NUM_BLOCK_Msk /*!< NUM_BLOCK[4:0] bits (Number of blocks) */ 05757 #define USB_COUNT4_RX_NUM_BLOCK_0 (0x01U << USB_COUNT4_RX_NUM_BLOCK_Pos) /*!< 0x00000400 */ 05758 #define USB_COUNT4_RX_NUM_BLOCK_1 (0x02U << USB_COUNT4_RX_NUM_BLOCK_Pos) /*!< 0x00000800 */ 05759 #define USB_COUNT4_RX_NUM_BLOCK_2 (0x04U << USB_COUNT4_RX_NUM_BLOCK_Pos) /*!< 0x00001000 */ 05760 #define USB_COUNT4_RX_NUM_BLOCK_3 (0x08U << USB_COUNT4_RX_NUM_BLOCK_Pos) /*!< 0x00002000 */ 05761 #define USB_COUNT4_RX_NUM_BLOCK_4 (0x10U << USB_COUNT4_RX_NUM_BLOCK_Pos) /*!< 0x00004000 */ 05762 05763 #define USB_COUNT4_RX_BLSIZE_Pos (15U) 05764 #define USB_COUNT4_RX_BLSIZE_Msk (0x1U << USB_COUNT4_RX_BLSIZE_Pos) /*!< 0x00008000 */ 05765 #define USB_COUNT4_RX_BLSIZE USB_COUNT4_RX_BLSIZE_Msk /*!< BLock SIZE */ 05766 05767 /***************** Bit definition for USB_COUNT5_RX register ****************/ 05768 #define USB_COUNT5_RX_COUNT5_RX_Pos (0U) 05769 #define USB_COUNT5_RX_COUNT5_RX_Msk (0x3FFU << USB_COUNT5_RX_COUNT5_RX_Pos) /*!< 0x000003FF */ 05770 #define USB_COUNT5_RX_COUNT5_RX USB_COUNT5_RX_COUNT5_RX_Msk /*!< Reception Byte Count */ 05771 05772 #define USB_COUNT5_RX_NUM_BLOCK_Pos (10U) 05773 #define USB_COUNT5_RX_NUM_BLOCK_Msk (0x1FU << USB_COUNT5_RX_NUM_BLOCK_Pos) /*!< 0x00007C00 */ 05774 #define USB_COUNT5_RX_NUM_BLOCK USB_COUNT5_RX_NUM_BLOCK_Msk /*!< NUM_BLOCK[4:0] bits (Number of blocks) */ 05775 #define USB_COUNT5_RX_NUM_BLOCK_0 (0x01U << USB_COUNT5_RX_NUM_BLOCK_Pos) /*!< 0x00000400 */ 05776 #define USB_COUNT5_RX_NUM_BLOCK_1 (0x02U << USB_COUNT5_RX_NUM_BLOCK_Pos) /*!< 0x00000800 */ 05777 #define USB_COUNT5_RX_NUM_BLOCK_2 (0x04U << USB_COUNT5_RX_NUM_BLOCK_Pos) /*!< 0x00001000 */ 05778 #define USB_COUNT5_RX_NUM_BLOCK_3 (0x08U << USB_COUNT5_RX_NUM_BLOCK_Pos) /*!< 0x00002000 */ 05779 #define USB_COUNT5_RX_NUM_BLOCK_4 (0x10U << USB_COUNT5_RX_NUM_BLOCK_Pos) /*!< 0x00004000 */ 05780 05781 #define USB_COUNT5_RX_BLSIZE_Pos (15U) 05782 #define USB_COUNT5_RX_BLSIZE_Msk (0x1U << USB_COUNT5_RX_BLSIZE_Pos) /*!< 0x00008000 */ 05783 #define USB_COUNT5_RX_BLSIZE USB_COUNT5_RX_BLSIZE_Msk /*!< BLock SIZE */ 05784 05785 /***************** Bit definition for USB_COUNT6_RX register ****************/ 05786 #define USB_COUNT6_RX_COUNT6_RX_Pos (0U) 05787 #define USB_COUNT6_RX_COUNT6_RX_Msk (0x3FFU << USB_COUNT6_RX_COUNT6_RX_Pos) /*!< 0x000003FF */ 05788 #define USB_COUNT6_RX_COUNT6_RX USB_COUNT6_RX_COUNT6_RX_Msk /*!< Reception Byte Count */ 05789 05790 #define USB_COUNT6_RX_NUM_BLOCK_Pos (10U) 05791 #define USB_COUNT6_RX_NUM_BLOCK_Msk (0x1FU << USB_COUNT6_RX_NUM_BLOCK_Pos) /*!< 0x00007C00 */ 05792 #define USB_COUNT6_RX_NUM_BLOCK USB_COUNT6_RX_NUM_BLOCK_Msk /*!< NUM_BLOCK[4:0] bits (Number of blocks) */ 05793 #define USB_COUNT6_RX_NUM_BLOCK_0 (0x01U << USB_COUNT6_RX_NUM_BLOCK_Pos) /*!< 0x00000400 */ 05794 #define USB_COUNT6_RX_NUM_BLOCK_1 (0x02U << USB_COUNT6_RX_NUM_BLOCK_Pos) /*!< 0x00000800 */ 05795 #define USB_COUNT6_RX_NUM_BLOCK_2 (0x04U << USB_COUNT6_RX_NUM_BLOCK_Pos) /*!< 0x00001000 */ 05796 #define USB_COUNT6_RX_NUM_BLOCK_3 (0x08U << USB_COUNT6_RX_NUM_BLOCK_Pos) /*!< 0x00002000 */ 05797 #define USB_COUNT6_RX_NUM_BLOCK_4 (0x10U << USB_COUNT6_RX_NUM_BLOCK_Pos) /*!< 0x00004000 */ 05798 05799 #define USB_COUNT6_RX_BLSIZE_Pos (15U) 05800 #define USB_COUNT6_RX_BLSIZE_Msk (0x1U << USB_COUNT6_RX_BLSIZE_Pos) /*!< 0x00008000 */ 05801 #define USB_COUNT6_RX_BLSIZE USB_COUNT6_RX_BLSIZE_Msk /*!< BLock SIZE */ 05802 05803 /***************** Bit definition for USB_COUNT7_RX register ****************/ 05804 #define USB_COUNT7_RX_COUNT7_RX_Pos (0U) 05805 #define USB_COUNT7_RX_COUNT7_RX_Msk (0x3FFU << USB_COUNT7_RX_COUNT7_RX_Pos) /*!< 0x000003FF */ 05806 #define USB_COUNT7_RX_COUNT7_RX USB_COUNT7_RX_COUNT7_RX_Msk /*!< Reception Byte Count */ 05807 05808 #define USB_COUNT7_RX_NUM_BLOCK_Pos (10U) 05809 #define USB_COUNT7_RX_NUM_BLOCK_Msk (0x1FU << USB_COUNT7_RX_NUM_BLOCK_Pos) /*!< 0x00007C00 */ 05810 #define USB_COUNT7_RX_NUM_BLOCK USB_COUNT7_RX_NUM_BLOCK_Msk /*!< NUM_BLOCK[4:0] bits (Number of blocks) */ 05811 #define USB_COUNT7_RX_NUM_BLOCK_0 (0x01U << USB_COUNT7_RX_NUM_BLOCK_Pos) /*!< 0x00000400 */ 05812 #define USB_COUNT7_RX_NUM_BLOCK_1 (0x02U << USB_COUNT7_RX_NUM_BLOCK_Pos) /*!< 0x00000800 */ 05813 #define USB_COUNT7_RX_NUM_BLOCK_2 (0x04U << USB_COUNT7_RX_NUM_BLOCK_Pos) /*!< 0x00001000 */ 05814 #define USB_COUNT7_RX_NUM_BLOCK_3 (0x08U << USB_COUNT7_RX_NUM_BLOCK_Pos) /*!< 0x00002000 */ 05815 #define USB_COUNT7_RX_NUM_BLOCK_4 (0x10U << USB_COUNT7_RX_NUM_BLOCK_Pos) /*!< 0x00004000 */ 05816 05817 #define USB_COUNT7_RX_BLSIZE_Pos (15U) 05818 #define USB_COUNT7_RX_BLSIZE_Msk (0x1U << USB_COUNT7_RX_BLSIZE_Pos) /*!< 0x00008000 */ 05819 #define USB_COUNT7_RX_BLSIZE USB_COUNT7_RX_BLSIZE_Msk /*!< BLock SIZE */ 05820 05821 /*----------------------------------------------------------------------------*/ 05822 05823 /**************** Bit definition for USB_COUNT0_RX_0 register ***************/ 05824 #define USB_COUNT0_RX_0_COUNT0_RX_0 ((uint32_t)0x000003FF) /*!< Reception Byte Count (low) */ 05825 05826 #define USB_COUNT0_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00) /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */ 05827 #define USB_COUNT0_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400) /*!< Bit 0 */ 05828 #define USB_COUNT0_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800) /*!< Bit 1 */ 05829 #define USB_COUNT0_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000) /*!< Bit 2 */ 05830 #define USB_COUNT0_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000) /*!< Bit 3 */ 05831 #define USB_COUNT0_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000) /*!< Bit 4 */ 05832 05833 #define USB_COUNT0_RX_0_BLSIZE_0 ((uint32_t)0x00008000) /*!< BLock SIZE (low) */ 05834 05835 /**************** Bit definition for USB_COUNT0_RX_1 register ***************/ 05836 #define USB_COUNT0_RX_1_COUNT0_RX_1 ((uint32_t)0x03FF0000) /*!< Reception Byte Count (high) */ 05837 05838 #define USB_COUNT0_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000) /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */ 05839 #define USB_COUNT0_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000) /*!< Bit 1 */ 05840 #define USB_COUNT0_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000) /*!< Bit 1 */ 05841 #define USB_COUNT0_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000) /*!< Bit 2 */ 05842 #define USB_COUNT0_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000) /*!< Bit 3 */ 05843 #define USB_COUNT0_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000) /*!< Bit 4 */ 05844 05845 #define USB_COUNT0_RX_1_BLSIZE_1 ((uint32_t)0x80000000) /*!< BLock SIZE (high) */ 05846 05847 /**************** Bit definition for USB_COUNT1_RX_0 register ***************/ 05848 #define USB_COUNT1_RX_0_COUNT1_RX_0 ((uint32_t)0x000003FF) /*!< Reception Byte Count (low) */ 05849 05850 #define USB_COUNT1_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00) /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */ 05851 #define USB_COUNT1_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400) /*!< Bit 0 */ 05852 #define USB_COUNT1_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800) /*!< Bit 1 */ 05853 #define USB_COUNT1_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000) /*!< Bit 2 */ 05854 #define USB_COUNT1_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000) /*!< Bit 3 */ 05855 #define USB_COUNT1_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000) /*!< Bit 4 */ 05856 05857 #define USB_COUNT1_RX_0_BLSIZE_0 ((uint32_t)0x00008000) /*!< BLock SIZE (low) */ 05858 05859 /**************** Bit definition for USB_COUNT1_RX_1 register ***************/ 05860 #define USB_COUNT1_RX_1_COUNT1_RX_1 ((uint32_t)0x03FF0000) /*!< Reception Byte Count (high) */ 05861 05862 #define USB_COUNT1_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000) /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */ 05863 #define USB_COUNT1_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000) /*!< Bit 0 */ 05864 #define USB_COUNT1_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000) /*!< Bit 1 */ 05865 #define USB_COUNT1_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000) /*!< Bit 2 */ 05866 #define USB_COUNT1_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000) /*!< Bit 3 */ 05867 #define USB_COUNT1_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000) /*!< Bit 4 */ 05868 05869 #define USB_COUNT1_RX_1_BLSIZE_1 ((uint32_t)0x80000000) /*!< BLock SIZE (high) */ 05870 05871 /**************** Bit definition for USB_COUNT2_RX_0 register ***************/ 05872 #define USB_COUNT2_RX_0_COUNT2_RX_0 ((uint32_t)0x000003FF) /*!< Reception Byte Count (low) */ 05873 05874 #define USB_COUNT2_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00) /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */ 05875 #define USB_COUNT2_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400) /*!< Bit 0 */ 05876 #define USB_COUNT2_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800) /*!< Bit 1 */ 05877 #define USB_COUNT2_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000) /*!< Bit 2 */ 05878 #define USB_COUNT2_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000) /*!< Bit 3 */ 05879 #define USB_COUNT2_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000) /*!< Bit 4 */ 05880 05881 #define USB_COUNT2_RX_0_BLSIZE_0 ((uint32_t)0x00008000) /*!< BLock SIZE (low) */ 05882 05883 /**************** Bit definition for USB_COUNT2_RX_1 register ***************/ 05884 #define USB_COUNT2_RX_1_COUNT2_RX_1 ((uint32_t)0x03FF0000) /*!< Reception Byte Count (high) */ 05885 05886 #define USB_COUNT2_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000) /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */ 05887 #define USB_COUNT2_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000) /*!< Bit 0 */ 05888 #define USB_COUNT2_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000) /*!< Bit 1 */ 05889 #define USB_COUNT2_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000) /*!< Bit 2 */ 05890 #define USB_COUNT2_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000) /*!< Bit 3 */ 05891 #define USB_COUNT2_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000) /*!< Bit 4 */ 05892 05893 #define USB_COUNT2_RX_1_BLSIZE_1 ((uint32_t)0x80000000) /*!< BLock SIZE (high) */ 05894 05895 /**************** Bit definition for USB_COUNT3_RX_0 register ***************/ 05896 #define USB_COUNT3_RX_0_COUNT3_RX_0 ((uint32_t)0x000003FF) /*!< Reception Byte Count (low) */ 05897 05898 #define USB_COUNT3_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00) /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */ 05899 #define USB_COUNT3_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400) /*!< Bit 0 */ 05900 #define USB_COUNT3_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800) /*!< Bit 1 */ 05901 #define USB_COUNT3_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000) /*!< Bit 2 */ 05902 #define USB_COUNT3_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000) /*!< Bit 3 */ 05903 #define USB_COUNT3_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000) /*!< Bit 4 */ 05904 05905 #define USB_COUNT3_RX_0_BLSIZE_0 ((uint32_t)0x00008000) /*!< BLock SIZE (low) */ 05906 05907 /**************** Bit definition for USB_COUNT3_RX_1 register ***************/ 05908 #define USB_COUNT3_RX_1_COUNT3_RX_1 ((uint32_t)0x03FF0000) /*!< Reception Byte Count (high) */ 05909 05910 #define USB_COUNT3_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000) /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */ 05911 #define USB_COUNT3_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000) /*!< Bit 0 */ 05912 #define USB_COUNT3_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000) /*!< Bit 1 */ 05913 #define USB_COUNT3_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000) /*!< Bit 2 */ 05914 #define USB_COUNT3_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000) /*!< Bit 3 */ 05915 #define USB_COUNT3_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000) /*!< Bit 4 */ 05916 05917 #define USB_COUNT3_RX_1_BLSIZE_1 ((uint32_t)0x80000000) /*!< BLock SIZE (high) */ 05918 05919 /**************** Bit definition for USB_COUNT4_RX_0 register ***************/ 05920 #define USB_COUNT4_RX_0_COUNT4_RX_0 ((uint32_t)0x000003FF) /*!< Reception Byte Count (low) */ 05921 05922 #define USB_COUNT4_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00) /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */ 05923 #define USB_COUNT4_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400) /*!< Bit 0 */ 05924 #define USB_COUNT4_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800) /*!< Bit 1 */ 05925 #define USB_COUNT4_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000) /*!< Bit 2 */ 05926 #define USB_COUNT4_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000) /*!< Bit 3 */ 05927 #define USB_COUNT4_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000) /*!< Bit 4 */ 05928 05929 #define USB_COUNT4_RX_0_BLSIZE_0 ((uint32_t)0x00008000) /*!< BLock SIZE (low) */ 05930 05931 /**************** Bit definition for USB_COUNT4_RX_1 register ***************/ 05932 #define USB_COUNT4_RX_1_COUNT4_RX_1 ((uint32_t)0x03FF0000) /*!< Reception Byte Count (high) */ 05933 05934 #define USB_COUNT4_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000) /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */ 05935 #define USB_COUNT4_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000) /*!< Bit 0 */ 05936 #define USB_COUNT4_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000) /*!< Bit 1 */ 05937 #define USB_COUNT4_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000) /*!< Bit 2 */ 05938 #define USB_COUNT4_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000) /*!< Bit 3 */ 05939 #define USB_COUNT4_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000) /*!< Bit 4 */ 05940 05941 #define USB_COUNT4_RX_1_BLSIZE_1 ((uint32_t)0x80000000) /*!< BLock SIZE (high) */ 05942 05943 /**************** Bit definition for USB_COUNT5_RX_0 register ***************/ 05944 #define USB_COUNT5_RX_0_COUNT5_RX_0 ((uint32_t)0x000003FF) /*!< Reception Byte Count (low) */ 05945 05946 #define USB_COUNT5_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00) /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */ 05947 #define USB_COUNT5_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400) /*!< Bit 0 */ 05948 #define USB_COUNT5_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800) /*!< Bit 1 */ 05949 #define USB_COUNT5_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000) /*!< Bit 2 */ 05950 #define USB_COUNT5_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000) /*!< Bit 3 */ 05951 #define USB_COUNT5_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000) /*!< Bit 4 */ 05952 05953 #define USB_COUNT5_RX_0_BLSIZE_0 ((uint32_t)0x00008000) /*!< BLock SIZE (low) */ 05954 05955 /**************** Bit definition for USB_COUNT5_RX_1 register ***************/ 05956 #define USB_COUNT5_RX_1_COUNT5_RX_1 ((uint32_t)0x03FF0000) /*!< Reception Byte Count (high) */ 05957 05958 #define USB_COUNT5_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000) /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */ 05959 #define USB_COUNT5_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000) /*!< Bit 0 */ 05960 #define USB_COUNT5_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000) /*!< Bit 1 */ 05961 #define USB_COUNT5_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000) /*!< Bit 2 */ 05962 #define USB_COUNT5_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000) /*!< Bit 3 */ 05963 #define USB_COUNT5_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000) /*!< Bit 4 */ 05964 05965 #define USB_COUNT5_RX_1_BLSIZE_1 ((uint32_t)0x80000000) /*!< BLock SIZE (high) */ 05966 05967 /*************** Bit definition for USB_COUNT6_RX_0 register ***************/ 05968 #define USB_COUNT6_RX_0_COUNT6_RX_0 ((uint32_t)0x000003FF) /*!< Reception Byte Count (low) */ 05969 05970 #define USB_COUNT6_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00) /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */ 05971 #define USB_COUNT6_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400) /*!< Bit 0 */ 05972 #define USB_COUNT6_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800) /*!< Bit 1 */ 05973 #define USB_COUNT6_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000) /*!< Bit 2 */ 05974 #define USB_COUNT6_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000) /*!< Bit 3 */ 05975 #define USB_COUNT6_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000) /*!< Bit 4 */ 05976 05977 #define USB_COUNT6_RX_0_BLSIZE_0 ((uint32_t)0x00008000) /*!< BLock SIZE (low) */ 05978 05979 /**************** Bit definition for USB_COUNT6_RX_1 register ***************/ 05980 #define USB_COUNT6_RX_1_COUNT6_RX_1 ((uint32_t)0x03FF0000) /*!< Reception Byte Count (high) */ 05981 05982 #define USB_COUNT6_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000) /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */ 05983 #define USB_COUNT6_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000) /*!< Bit 0 */ 05984 #define USB_COUNT6_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000) /*!< Bit 1 */ 05985 #define USB_COUNT6_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000) /*!< Bit 2 */ 05986 #define USB_COUNT6_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000) /*!< Bit 3 */ 05987 #define USB_COUNT6_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000) /*!< Bit 4 */ 05988 05989 #define USB_COUNT6_RX_1_BLSIZE_1 ((uint32_t)0x80000000) /*!< BLock SIZE (high) */ 05990 05991 /*************** Bit definition for USB_COUNT7_RX_0 register ****************/ 05992 #define USB_COUNT7_RX_0_COUNT7_RX_0 ((uint32_t)0x000003FF) /*!< Reception Byte Count (low) */ 05993 05994 #define USB_COUNT7_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00) /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */ 05995 #define USB_COUNT7_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400) /*!< Bit 0 */ 05996 #define USB_COUNT7_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800) /*!< Bit 1 */ 05997 #define USB_COUNT7_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000) /*!< Bit 2 */ 05998 #define USB_COUNT7_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000) /*!< Bit 3 */ 05999 #define USB_COUNT7_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000) /*!< Bit 4 */ 06000 06001 #define USB_COUNT7_RX_0_BLSIZE_0 ((uint32_t)0x00008000) /*!< BLock SIZE (low) */ 06002 06003 /*************** Bit definition for USB_COUNT7_RX_1 register ****************/ 06004 #define USB_COUNT7_RX_1_COUNT7_RX_1 ((uint32_t)0x03FF0000) /*!< Reception Byte Count (high) */ 06005 06006 #define USB_COUNT7_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000) /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */ 06007 #define USB_COUNT7_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000) /*!< Bit 0 */ 06008 #define USB_COUNT7_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000) /*!< Bit 1 */ 06009 #define USB_COUNT7_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000) /*!< Bit 2 */ 06010 #define USB_COUNT7_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000) /*!< Bit 3 */ 06011 #define USB_COUNT7_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000) /*!< Bit 4 */ 06012 06013 #define USB_COUNT7_RX_1_BLSIZE_1 ((uint32_t)0x80000000) /*!< BLock SIZE (high) */ 06014 06015 /******************************************************************************/ 06016 /* */ 06017 /* Controller Area Network */ 06018 /* */ 06019 /******************************************************************************/ 06020 06021 /*!< CAN control and status registers */ 06022 /******************* Bit definition for CAN_MCR register ********************/ 06023 #define CAN_MCR_INRQ_Pos (0U) 06024 #define CAN_MCR_INRQ_Msk (0x1U << CAN_MCR_INRQ_Pos) /*!< 0x00000001 */ 06025 #define CAN_MCR_INRQ CAN_MCR_INRQ_Msk /*!< Initialization Request */ 06026 #define CAN_MCR_SLEEP_Pos (1U) 06027 #define CAN_MCR_SLEEP_Msk (0x1U << CAN_MCR_SLEEP_Pos) /*!< 0x00000002 */ 06028 #define CAN_MCR_SLEEP CAN_MCR_SLEEP_Msk /*!< Sleep Mode Request */ 06029 #define CAN_MCR_TXFP_Pos (2U) 06030 #define CAN_MCR_TXFP_Msk (0x1U << CAN_MCR_TXFP_Pos) /*!< 0x00000004 */ 06031 #define CAN_MCR_TXFP CAN_MCR_TXFP_Msk /*!< Transmit FIFO Priority */ 06032 #define CAN_MCR_RFLM_Pos (3U) 06033 #define CAN_MCR_RFLM_Msk (0x1U << CAN_MCR_RFLM_Pos) /*!< 0x00000008 */ 06034 #define CAN_MCR_RFLM CAN_MCR_RFLM_Msk /*!< Receive FIFO Locked Mode */ 06035 #define CAN_MCR_NART_Pos (4U) 06036 #define CAN_MCR_NART_Msk (0x1U << CAN_MCR_NART_Pos) /*!< 0x00000010 */ 06037 #define CAN_MCR_NART CAN_MCR_NART_Msk /*!< No Automatic Retransmission */ 06038 #define CAN_MCR_AWUM_Pos (5U) 06039 #define CAN_MCR_AWUM_Msk (0x1U << CAN_MCR_AWUM_Pos) /*!< 0x00000020 */ 06040 #define CAN_MCR_AWUM CAN_MCR_AWUM_Msk /*!< Automatic Wakeup Mode */ 06041 #define CAN_MCR_ABOM_Pos (6U) 06042 #define CAN_MCR_ABOM_Msk (0x1U << CAN_MCR_ABOM_Pos) /*!< 0x00000040 */ 06043 #define CAN_MCR_ABOM CAN_MCR_ABOM_Msk /*!< Automatic Bus-Off Management */ 06044 #define CAN_MCR_TTCM_Pos (7U) 06045 #define CAN_MCR_TTCM_Msk (0x1U << CAN_MCR_TTCM_Pos) /*!< 0x00000080 */ 06046 #define CAN_MCR_TTCM CAN_MCR_TTCM_Msk /*!< Time Triggered Communication Mode */ 06047 #define CAN_MCR_RESET_Pos (15U) 06048 #define CAN_MCR_RESET_Msk (0x1U << CAN_MCR_RESET_Pos) /*!< 0x00008000 */ 06049 #define CAN_MCR_RESET CAN_MCR_RESET_Msk /*!< CAN software master reset */ 06050 #define CAN_MCR_DBF_Pos (16U) 06051 #define CAN_MCR_DBF_Msk (0x1U << CAN_MCR_DBF_Pos) /*!< 0x00010000 */ 06052 #define CAN_MCR_DBF CAN_MCR_DBF_Msk /*!< CAN Debug freeze */ 06053 06054 /******************* Bit definition for CAN_MSR register ********************/ 06055 #define CAN_MSR_INAK_Pos (0U) 06056 #define CAN_MSR_INAK_Msk (0x1U << CAN_MSR_INAK_Pos) /*!< 0x00000001 */ 06057 #define CAN_MSR_INAK CAN_MSR_INAK_Msk /*!< Initialization Acknowledge */ 06058 #define CAN_MSR_SLAK_Pos (1U) 06059 #define CAN_MSR_SLAK_Msk (0x1U << CAN_MSR_SLAK_Pos) /*!< 0x00000002 */ 06060 #define CAN_MSR_SLAK CAN_MSR_SLAK_Msk /*!< Sleep Acknowledge */ 06061 #define CAN_MSR_ERRI_Pos (2U) 06062 #define CAN_MSR_ERRI_Msk (0x1U << CAN_MSR_ERRI_Pos) /*!< 0x00000004 */ 06063 #define CAN_MSR_ERRI CAN_MSR_ERRI_Msk /*!< Error Interrupt */ 06064 #define CAN_MSR_WKUI_Pos (3U) 06065 #define CAN_MSR_WKUI_Msk (0x1U << CAN_MSR_WKUI_Pos) /*!< 0x00000008 */ 06066 #define CAN_MSR_WKUI CAN_MSR_WKUI_Msk /*!< Wakeup Interrupt */ 06067 #define CAN_MSR_SLAKI_Pos (4U) 06068 #define CAN_MSR_SLAKI_Msk (0x1U << CAN_MSR_SLAKI_Pos) /*!< 0x00000010 */ 06069 #define CAN_MSR_SLAKI CAN_MSR_SLAKI_Msk /*!< Sleep Acknowledge Interrupt */ 06070 #define CAN_MSR_TXM_Pos (8U) 06071 #define CAN_MSR_TXM_Msk (0x1U << CAN_MSR_TXM_Pos) /*!< 0x00000100 */ 06072 #define CAN_MSR_TXM CAN_MSR_TXM_Msk /*!< Transmit Mode */ 06073 #define CAN_MSR_RXM_Pos (9U) 06074 #define CAN_MSR_RXM_Msk (0x1U << CAN_MSR_RXM_Pos) /*!< 0x00000200 */ 06075 #define CAN_MSR_RXM CAN_MSR_RXM_Msk /*!< Receive Mode */ 06076 #define CAN_MSR_SAMP_Pos (10U) 06077 #define CAN_MSR_SAMP_Msk (0x1U << CAN_MSR_SAMP_Pos) /*!< 0x00000400 */ 06078 #define CAN_MSR_SAMP CAN_MSR_SAMP_Msk /*!< Last Sample Point */ 06079 #define CAN_MSR_RX_Pos (11U) 06080 #define CAN_MSR_RX_Msk (0x1U << CAN_MSR_RX_Pos) /*!< 0x00000800 */ 06081 #define CAN_MSR_RX CAN_MSR_RX_Msk /*!< CAN Rx Signal */ 06082 06083 /******************* Bit definition for CAN_TSR register ********************/ 06084 #define CAN_TSR_RQCP0_Pos (0U) 06085 #define CAN_TSR_RQCP0_Msk (0x1U << CAN_TSR_RQCP0_Pos) /*!< 0x00000001 */ 06086 #define CAN_TSR_RQCP0 CAN_TSR_RQCP0_Msk /*!< Request Completed Mailbox0 */ 06087 #define CAN_TSR_TXOK0_Pos (1U) 06088 #define CAN_TSR_TXOK0_Msk (0x1U << CAN_TSR_TXOK0_Pos) /*!< 0x00000002 */ 06089 #define CAN_TSR_TXOK0 CAN_TSR_TXOK0_Msk /*!< Transmission OK of Mailbox0 */ 06090 #define CAN_TSR_ALST0_Pos (2U) 06091 #define CAN_TSR_ALST0_Msk (0x1U << CAN_TSR_ALST0_Pos) /*!< 0x00000004 */ 06092 #define CAN_TSR_ALST0 CAN_TSR_ALST0_Msk /*!< Arbitration Lost for Mailbox0 */ 06093 #define CAN_TSR_TERR0_Pos (3U) 06094 #define CAN_TSR_TERR0_Msk (0x1U << CAN_TSR_TERR0_Pos) /*!< 0x00000008 */ 06095 #define CAN_TSR_TERR0 CAN_TSR_TERR0_Msk /*!< Transmission Error of Mailbox0 */ 06096 #define CAN_TSR_ABRQ0_Pos (7U) 06097 #define CAN_TSR_ABRQ0_Msk (0x1U << CAN_TSR_ABRQ0_Pos) /*!< 0x00000080 */ 06098 #define CAN_TSR_ABRQ0 CAN_TSR_ABRQ0_Msk /*!< Abort Request for Mailbox0 */ 06099 #define CAN_TSR_RQCP1_Pos (8U) 06100 #define CAN_TSR_RQCP1_Msk (0x1U << CAN_TSR_RQCP1_Pos) /*!< 0x00000100 */ 06101 #define CAN_TSR_RQCP1 CAN_TSR_RQCP1_Msk /*!< Request Completed Mailbox1 */ 06102 #define CAN_TSR_TXOK1_Pos (9U) 06103 #define CAN_TSR_TXOK1_Msk (0x1U << CAN_TSR_TXOK1_Pos) /*!< 0x00000200 */ 06104 #define CAN_TSR_TXOK1 CAN_TSR_TXOK1_Msk /*!< Transmission OK of Mailbox1 */ 06105 #define CAN_TSR_ALST1_Pos (10U) 06106 #define CAN_TSR_ALST1_Msk (0x1U << CAN_TSR_ALST1_Pos) /*!< 0x00000400 */ 06107 #define CAN_TSR_ALST1 CAN_TSR_ALST1_Msk /*!< Arbitration Lost for Mailbox1 */ 06108 #define CAN_TSR_TERR1_Pos (11U) 06109 #define CAN_TSR_TERR1_Msk (0x1U << CAN_TSR_TERR1_Pos) /*!< 0x00000800 */ 06110 #define CAN_TSR_TERR1 CAN_TSR_TERR1_Msk /*!< Transmission Error of Mailbox1 */ 06111 #define CAN_TSR_ABRQ1_Pos (15U) 06112 #define CAN_TSR_ABRQ1_Msk (0x1U << CAN_TSR_ABRQ1_Pos) /*!< 0x00008000 */ 06113 #define CAN_TSR_ABRQ1 CAN_TSR_ABRQ1_Msk /*!< Abort Request for Mailbox 1 */ 06114 #define CAN_TSR_RQCP2_Pos (16U) 06115 #define CAN_TSR_RQCP2_Msk (0x1U << CAN_TSR_RQCP2_Pos) /*!< 0x00010000 */ 06116 #define CAN_TSR_RQCP2 CAN_TSR_RQCP2_Msk /*!< Request Completed Mailbox2 */ 06117 #define CAN_TSR_TXOK2_Pos (17U) 06118 #define CAN_TSR_TXOK2_Msk (0x1U << CAN_TSR_TXOK2_Pos) /*!< 0x00020000 */ 06119 #define CAN_TSR_TXOK2 CAN_TSR_TXOK2_Msk /*!< Transmission OK of Mailbox 2 */ 06120 #define CAN_TSR_ALST2_Pos (18U) 06121 #define CAN_TSR_ALST2_Msk (0x1U << CAN_TSR_ALST2_Pos) /*!< 0x00040000 */ 06122 #define CAN_TSR_ALST2 CAN_TSR_ALST2_Msk /*!< Arbitration Lost for mailbox 2 */ 06123 #define CAN_TSR_TERR2_Pos (19U) 06124 #define CAN_TSR_TERR2_Msk (0x1U << CAN_TSR_TERR2_Pos) /*!< 0x00080000 */ 06125 #define CAN_TSR_TERR2 CAN_TSR_TERR2_Msk /*!< Transmission Error of Mailbox 2 */ 06126 #define CAN_TSR_ABRQ2_Pos (23U) 06127 #define CAN_TSR_ABRQ2_Msk (0x1U << CAN_TSR_ABRQ2_Pos) /*!< 0x00800000 */ 06128 #define CAN_TSR_ABRQ2 CAN_TSR_ABRQ2_Msk /*!< Abort Request for Mailbox 2 */ 06129 #define CAN_TSR_CODE_Pos (24U) 06130 #define CAN_TSR_CODE_Msk (0x3U << CAN_TSR_CODE_Pos) /*!< 0x03000000 */ 06131 #define CAN_TSR_CODE CAN_TSR_CODE_Msk /*!< Mailbox Code */ 06132 06133 #define CAN_TSR_TME_Pos (26U) 06134 #define CAN_TSR_TME_Msk (0x7U << CAN_TSR_TME_Pos) /*!< 0x1C000000 */ 06135 #define CAN_TSR_TME CAN_TSR_TME_Msk /*!< TME[2:0] bits */ 06136 #define CAN_TSR_TME0_Pos (26U) 06137 #define CAN_TSR_TME0_Msk (0x1U << CAN_TSR_TME0_Pos) /*!< 0x04000000 */ 06138 #define CAN_TSR_TME0 CAN_TSR_TME0_Msk /*!< Transmit Mailbox 0 Empty */ 06139 #define CAN_TSR_TME1_Pos (27U) 06140 #define CAN_TSR_TME1_Msk (0x1U << CAN_TSR_TME1_Pos) /*!< 0x08000000 */ 06141 #define CAN_TSR_TME1 CAN_TSR_TME1_Msk /*!< Transmit Mailbox 1 Empty */ 06142 #define CAN_TSR_TME2_Pos (28U) 06143 #define CAN_TSR_TME2_Msk (0x1U << CAN_TSR_TME2_Pos) /*!< 0x10000000 */ 06144 #define CAN_TSR_TME2 CAN_TSR_TME2_Msk /*!< Transmit Mailbox 2 Empty */ 06145 06146 #define CAN_TSR_LOW_Pos (29U) 06147 #define CAN_TSR_LOW_Msk (0x7U << CAN_TSR_LOW_Pos) /*!< 0xE0000000 */ 06148 #define CAN_TSR_LOW CAN_TSR_LOW_Msk /*!< LOW[2:0] bits */ 06149 #define CAN_TSR_LOW0_Pos (29U) 06150 #define CAN_TSR_LOW0_Msk (0x1U << CAN_TSR_LOW0_Pos) /*!< 0x20000000 */ 06151 #define CAN_TSR_LOW0 CAN_TSR_LOW0_Msk /*!< Lowest Priority Flag for Mailbox 0 */ 06152 #define CAN_TSR_LOW1_Pos (30U) 06153 #define CAN_TSR_LOW1_Msk (0x1U << CAN_TSR_LOW1_Pos) /*!< 0x40000000 */ 06154 #define CAN_TSR_LOW1 CAN_TSR_LOW1_Msk /*!< Lowest Priority Flag for Mailbox 1 */ 06155 #define CAN_TSR_LOW2_Pos (31U) 06156 #define CAN_TSR_LOW2_Msk (0x1U << CAN_TSR_LOW2_Pos) /*!< 0x80000000 */ 06157 #define CAN_TSR_LOW2 CAN_TSR_LOW2_Msk /*!< Lowest Priority Flag for Mailbox 2 */ 06158 06159 /******************* Bit definition for CAN_RF0R register *******************/ 06160 #define CAN_RF0R_FMP0_Pos (0U) 06161 #define CAN_RF0R_FMP0_Msk (0x3U << CAN_RF0R_FMP0_Pos) /*!< 0x00000003 */ 06162 #define CAN_RF0R_FMP0 CAN_RF0R_FMP0_Msk /*!< FIFO 0 Message Pending */ 06163 #define CAN_RF0R_FULL0_Pos (3U) 06164 #define CAN_RF0R_FULL0_Msk (0x1U << CAN_RF0R_FULL0_Pos) /*!< 0x00000008 */ 06165 #define CAN_RF0R_FULL0 CAN_RF0R_FULL0_Msk /*!< FIFO 0 Full */ 06166 #define CAN_RF0R_FOVR0_Pos (4U) 06167 #define CAN_RF0R_FOVR0_Msk (0x1U << CAN_RF0R_FOVR0_Pos) /*!< 0x00000010 */ 06168 #define CAN_RF0R_FOVR0 CAN_RF0R_FOVR0_Msk /*!< FIFO 0 Overrun */ 06169 #define CAN_RF0R_RFOM0_Pos (5U) 06170 #define CAN_RF0R_RFOM0_Msk (0x1U << CAN_RF0R_RFOM0_Pos) /*!< 0x00000020 */ 06171 #define CAN_RF0R_RFOM0 CAN_RF0R_RFOM0_Msk /*!< Release FIFO 0 Output Mailbox */ 06172 06173 /******************* Bit definition for CAN_RF1R register *******************/ 06174 #define CAN_RF1R_FMP1_Pos (0U) 06175 #define CAN_RF1R_FMP1_Msk (0x3U << CAN_RF1R_FMP1_Pos) /*!< 0x00000003 */ 06176 #define CAN_RF1R_FMP1 CAN_RF1R_FMP1_Msk /*!< FIFO 1 Message Pending */ 06177 #define CAN_RF1R_FULL1_Pos (3U) 06178 #define CAN_RF1R_FULL1_Msk (0x1U << CAN_RF1R_FULL1_Pos) /*!< 0x00000008 */ 06179 #define CAN_RF1R_FULL1 CAN_RF1R_FULL1_Msk /*!< FIFO 1 Full */ 06180 #define CAN_RF1R_FOVR1_Pos (4U) 06181 #define CAN_RF1R_FOVR1_Msk (0x1U << CAN_RF1R_FOVR1_Pos) /*!< 0x00000010 */ 06182 #define CAN_RF1R_FOVR1 CAN_RF1R_FOVR1_Msk /*!< FIFO 1 Overrun */ 06183 #define CAN_RF1R_RFOM1_Pos (5U) 06184 #define CAN_RF1R_RFOM1_Msk (0x1U << CAN_RF1R_RFOM1_Pos) /*!< 0x00000020 */ 06185 #define CAN_RF1R_RFOM1 CAN_RF1R_RFOM1_Msk /*!< Release FIFO 1 Output Mailbox */ 06186 06187 /******************** Bit definition for CAN_IER register *******************/ 06188 #define CAN_IER_TMEIE_Pos (0U) 06189 #define CAN_IER_TMEIE_Msk (0x1U << CAN_IER_TMEIE_Pos) /*!< 0x00000001 */ 06190 #define CAN_IER_TMEIE CAN_IER_TMEIE_Msk /*!< Transmit Mailbox Empty Interrupt Enable */ 06191 #define CAN_IER_FMPIE0_Pos (1U) 06192 #define CAN_IER_FMPIE0_Msk (0x1U << CAN_IER_FMPIE0_Pos) /*!< 0x00000002 */ 06193 #define CAN_IER_FMPIE0 CAN_IER_FMPIE0_Msk /*!< FIFO Message Pending Interrupt Enable */ 06194 #define CAN_IER_FFIE0_Pos (2U) 06195 #define CAN_IER_FFIE0_Msk (0x1U << CAN_IER_FFIE0_Pos) /*!< 0x00000004 */ 06196 #define CAN_IER_FFIE0 CAN_IER_FFIE0_Msk /*!< FIFO Full Interrupt Enable */ 06197 #define CAN_IER_FOVIE0_Pos (3U) 06198 #define CAN_IER_FOVIE0_Msk (0x1U << CAN_IER_FOVIE0_Pos) /*!< 0x00000008 */ 06199 #define CAN_IER_FOVIE0 CAN_IER_FOVIE0_Msk /*!< FIFO Overrun Interrupt Enable */ 06200 #define CAN_IER_FMPIE1_Pos (4U) 06201 #define CAN_IER_FMPIE1_Msk (0x1U << CAN_IER_FMPIE1_Pos) /*!< 0x00000010 */ 06202 #define CAN_IER_FMPIE1 CAN_IER_FMPIE1_Msk /*!< FIFO Message Pending Interrupt Enable */ 06203 #define CAN_IER_FFIE1_Pos (5U) 06204 #define CAN_IER_FFIE1_Msk (0x1U << CAN_IER_FFIE1_Pos) /*!< 0x00000020 */ 06205 #define CAN_IER_FFIE1 CAN_IER_FFIE1_Msk /*!< FIFO Full Interrupt Enable */ 06206 #define CAN_IER_FOVIE1_Pos (6U) 06207 #define CAN_IER_FOVIE1_Msk (0x1U << CAN_IER_FOVIE1_Pos) /*!< 0x00000040 */ 06208 #define CAN_IER_FOVIE1 CAN_IER_FOVIE1_Msk /*!< FIFO Overrun Interrupt Enable */ 06209 #define CAN_IER_EWGIE_Pos (8U) 06210 #define CAN_IER_EWGIE_Msk (0x1U << CAN_IER_EWGIE_Pos) /*!< 0x00000100 */ 06211 #define CAN_IER_EWGIE CAN_IER_EWGIE_Msk /*!< Error Warning Interrupt Enable */ 06212 #define CAN_IER_EPVIE_Pos (9U) 06213 #define CAN_IER_EPVIE_Msk (0x1U << CAN_IER_EPVIE_Pos) /*!< 0x00000200 */ 06214 #define CAN_IER_EPVIE CAN_IER_EPVIE_Msk /*!< Error Passive Interrupt Enable */ 06215 #define CAN_IER_BOFIE_Pos (10U) 06216 #define CAN_IER_BOFIE_Msk (0x1U << CAN_IER_BOFIE_Pos) /*!< 0x00000400 */ 06217 #define CAN_IER_BOFIE CAN_IER_BOFIE_Msk /*!< Bus-Off Interrupt Enable */ 06218 #define CAN_IER_LECIE_Pos (11U) 06219 #define CAN_IER_LECIE_Msk (0x1U << CAN_IER_LECIE_Pos) /*!< 0x00000800 */ 06220 #define CAN_IER_LECIE CAN_IER_LECIE_Msk /*!< Last Error Code Interrupt Enable */ 06221 #define CAN_IER_ERRIE_Pos (15U) 06222 #define CAN_IER_ERRIE_Msk (0x1U << CAN_IER_ERRIE_Pos) /*!< 0x00008000 */ 06223 #define CAN_IER_ERRIE CAN_IER_ERRIE_Msk /*!< Error Interrupt Enable */ 06224 #define CAN_IER_WKUIE_Pos (16U) 06225 #define CAN_IER_WKUIE_Msk (0x1U << CAN_IER_WKUIE_Pos) /*!< 0x00010000 */ 06226 #define CAN_IER_WKUIE CAN_IER_WKUIE_Msk /*!< Wakeup Interrupt Enable */ 06227 #define CAN_IER_SLKIE_Pos (17U) 06228 #define CAN_IER_SLKIE_Msk (0x1U << CAN_IER_SLKIE_Pos) /*!< 0x00020000 */ 06229 #define CAN_IER_SLKIE CAN_IER_SLKIE_Msk /*!< Sleep Interrupt Enable */ 06230 06231 /******************** Bit definition for CAN_ESR register *******************/ 06232 #define CAN_ESR_EWGF_Pos (0U) 06233 #define CAN_ESR_EWGF_Msk (0x1U << CAN_ESR_EWGF_Pos) /*!< 0x00000001 */ 06234 #define CAN_ESR_EWGF CAN_ESR_EWGF_Msk /*!< Error Warning Flag */ 06235 #define CAN_ESR_EPVF_Pos (1U) 06236 #define CAN_ESR_EPVF_Msk (0x1U << CAN_ESR_EPVF_Pos) /*!< 0x00000002 */ 06237 #define CAN_ESR_EPVF CAN_ESR_EPVF_Msk /*!< Error Passive Flag */ 06238 #define CAN_ESR_BOFF_Pos (2U) 06239 #define CAN_ESR_BOFF_Msk (0x1U << CAN_ESR_BOFF_Pos) /*!< 0x00000004 */ 06240 #define CAN_ESR_BOFF CAN_ESR_BOFF_Msk /*!< Bus-Off Flag */ 06241 06242 #define CAN_ESR_LEC_Pos (4U) 06243 #define CAN_ESR_LEC_Msk (0x7U << CAN_ESR_LEC_Pos) /*!< 0x00000070 */ 06244 #define CAN_ESR_LEC CAN_ESR_LEC_Msk /*!< LEC[2:0] bits (Last Error Code) */ 06245 #define CAN_ESR_LEC_0 (0x1U << CAN_ESR_LEC_Pos) /*!< 0x00000010 */ 06246 #define CAN_ESR_LEC_1 (0x2U << CAN_ESR_LEC_Pos) /*!< 0x00000020 */ 06247 #define CAN_ESR_LEC_2 (0x4U << CAN_ESR_LEC_Pos) /*!< 0x00000040 */ 06248 06249 #define CAN_ESR_TEC_Pos (16U) 06250 #define CAN_ESR_TEC_Msk (0xFFU << CAN_ESR_TEC_Pos) /*!< 0x00FF0000 */ 06251 #define CAN_ESR_TEC CAN_ESR_TEC_Msk /*!< Least significant byte of the 9-bit Transmit Error Counter */ 06252 #define CAN_ESR_REC_Pos (24U) 06253 #define CAN_ESR_REC_Msk (0xFFU << CAN_ESR_REC_Pos) /*!< 0xFF000000 */ 06254 #define CAN_ESR_REC CAN_ESR_REC_Msk /*!< Receive Error Counter */ 06255 06256 /******************* Bit definition for CAN_BTR register ********************/ 06257 #define CAN_BTR_BRP_Pos (0U) 06258 #define CAN_BTR_BRP_Msk (0x3FFU << CAN_BTR_BRP_Pos) /*!< 0x000003FF */ 06259 #define CAN_BTR_BRP CAN_BTR_BRP_Msk /*!<Baud Rate Prescaler */ 06260 #define CAN_BTR_TS1_Pos (16U) 06261 #define CAN_BTR_TS1_Msk (0xFU << CAN_BTR_TS1_Pos) /*!< 0x000F0000 */ 06262 #define CAN_BTR_TS1 CAN_BTR_TS1_Msk /*!<Time Segment 1 */ 06263 #define CAN_BTR_TS1_0 (0x1U << CAN_BTR_TS1_Pos) /*!< 0x00010000 */ 06264 #define CAN_BTR_TS1_1 (0x2U << CAN_BTR_TS1_Pos) /*!< 0x00020000 */ 06265 #define CAN_BTR_TS1_2 (0x4U << CAN_BTR_TS1_Pos) /*!< 0x00040000 */ 06266 #define CAN_BTR_TS1_3 (0x8U << CAN_BTR_TS1_Pos) /*!< 0x00080000 */ 06267 #define CAN_BTR_TS2_Pos (20U) 06268 #define CAN_BTR_TS2_Msk (0x7U << CAN_BTR_TS2_Pos) /*!< 0x00700000 */ 06269 #define CAN_BTR_TS2 CAN_BTR_TS2_Msk /*!<Time Segment 2 */ 06270 #define CAN_BTR_TS2_0 (0x1U << CAN_BTR_TS2_Pos) /*!< 0x00100000 */ 06271 #define CAN_BTR_TS2_1 (0x2U << CAN_BTR_TS2_Pos) /*!< 0x00200000 */ 06272 #define CAN_BTR_TS2_2 (0x4U << CAN_BTR_TS2_Pos) /*!< 0x00400000 */ 06273 #define CAN_BTR_SJW_Pos (24U) 06274 #define CAN_BTR_SJW_Msk (0x3U << CAN_BTR_SJW_Pos) /*!< 0x03000000 */ 06275 #define CAN_BTR_SJW CAN_BTR_SJW_Msk /*!<Resynchronization Jump Width */ 06276 #define CAN_BTR_SJW_0 (0x1U << CAN_BTR_SJW_Pos) /*!< 0x01000000 */ 06277 #define CAN_BTR_SJW_1 (0x2U << CAN_BTR_SJW_Pos) /*!< 0x02000000 */ 06278 #define CAN_BTR_LBKM_Pos (30U) 06279 #define CAN_BTR_LBKM_Msk (0x1U << CAN_BTR_LBKM_Pos) /*!< 0x40000000 */ 06280 #define CAN_BTR_LBKM CAN_BTR_LBKM_Msk /*!<Loop Back Mode (Debug) */ 06281 #define CAN_BTR_SILM_Pos (31U) 06282 #define CAN_BTR_SILM_Msk (0x1U << CAN_BTR_SILM_Pos) /*!< 0x80000000 */ 06283 #define CAN_BTR_SILM CAN_BTR_SILM_Msk /*!<Silent Mode */ 06284 06285 /*!< Mailbox registers */ 06286 /****************** Bit definition for CAN_TI0R register ********************/ 06287 #define CAN_TI0R_TXRQ_Pos (0U) 06288 #define CAN_TI0R_TXRQ_Msk (0x1U << CAN_TI0R_TXRQ_Pos) /*!< 0x00000001 */ 06289 #define CAN_TI0R_TXRQ CAN_TI0R_TXRQ_Msk /*!< Transmit Mailbox Request */ 06290 #define CAN_TI0R_RTR_Pos (1U) 06291 #define CAN_TI0R_RTR_Msk (0x1U << CAN_TI0R_RTR_Pos) /*!< 0x00000002 */ 06292 #define CAN_TI0R_RTR CAN_TI0R_RTR_Msk /*!< Remote Transmission Request */ 06293 #define CAN_TI0R_IDE_Pos (2U) 06294 #define CAN_TI0R_IDE_Msk (0x1U << CAN_TI0R_IDE_Pos) /*!< 0x00000004 */ 06295 #define CAN_TI0R_IDE CAN_TI0R_IDE_Msk /*!< Identifier Extension */ 06296 #define CAN_TI0R_EXID_Pos (3U) 06297 #define CAN_TI0R_EXID_Msk (0x3FFFFU << CAN_TI0R_EXID_Pos) /*!< 0x001FFFF8 */ 06298 #define CAN_TI0R_EXID CAN_TI0R_EXID_Msk /*!< Extended Identifier */ 06299 #define CAN_TI0R_STID_Pos (21U) 06300 #define CAN_TI0R_STID_Msk (0x7FFU << CAN_TI0R_STID_Pos) /*!< 0xFFE00000 */ 06301 #define CAN_TI0R_STID CAN_TI0R_STID_Msk /*!< Standard Identifier or Extended Identifier */ 06302 06303 /****************** Bit definition for CAN_TDT0R register *******************/ 06304 #define CAN_TDT0R_DLC_Pos (0U) 06305 #define CAN_TDT0R_DLC_Msk (0xFU << CAN_TDT0R_DLC_Pos) /*!< 0x0000000F */ 06306 #define CAN_TDT0R_DLC CAN_TDT0R_DLC_Msk /*!< Data Length Code */ 06307 #define CAN_TDT0R_TGT_Pos (8U) 06308 #define CAN_TDT0R_TGT_Msk (0x1U << CAN_TDT0R_TGT_Pos) /*!< 0x00000100 */ 06309 #define CAN_TDT0R_TGT CAN_TDT0R_TGT_Msk /*!< Transmit Global Time */ 06310 #define CAN_TDT0R_TIME_Pos (16U) 06311 #define CAN_TDT0R_TIME_Msk (0xFFFFU << CAN_TDT0R_TIME_Pos) /*!< 0xFFFF0000 */ 06312 #define CAN_TDT0R_TIME CAN_TDT0R_TIME_Msk /*!< Message Time Stamp */ 06313 06314 /****************** Bit definition for CAN_TDL0R register *******************/ 06315 #define CAN_TDL0R_DATA0_Pos (0U) 06316 #define CAN_TDL0R_DATA0_Msk (0xFFU << CAN_TDL0R_DATA0_Pos) /*!< 0x000000FF */ 06317 #define CAN_TDL0R_DATA0 CAN_TDL0R_DATA0_Msk /*!< Data byte 0 */ 06318 #define CAN_TDL0R_DATA1_Pos (8U) 06319 #define CAN_TDL0R_DATA1_Msk (0xFFU << CAN_TDL0R_DATA1_Pos) /*!< 0x0000FF00 */ 06320 #define CAN_TDL0R_DATA1 CAN_TDL0R_DATA1_Msk /*!< Data byte 1 */ 06321 #define CAN_TDL0R_DATA2_Pos (16U) 06322 #define CAN_TDL0R_DATA2_Msk (0xFFU << CAN_TDL0R_DATA2_Pos) /*!< 0x00FF0000 */ 06323 #define CAN_TDL0R_DATA2 CAN_TDL0R_DATA2_Msk /*!< Data byte 2 */ 06324 #define CAN_TDL0R_DATA3_Pos (24U) 06325 #define CAN_TDL0R_DATA3_Msk (0xFFU << CAN_TDL0R_DATA3_Pos) /*!< 0xFF000000 */ 06326 #define CAN_TDL0R_DATA3 CAN_TDL0R_DATA3_Msk /*!< Data byte 3 */ 06327 06328 /****************** Bit definition for CAN_TDH0R register *******************/ 06329 #define CAN_TDH0R_DATA4_Pos (0U) 06330 #define CAN_TDH0R_DATA4_Msk (0xFFU << CAN_TDH0R_DATA4_Pos) /*!< 0x000000FF */ 06331 #define CAN_TDH0R_DATA4 CAN_TDH0R_DATA4_Msk /*!< Data byte 4 */ 06332 #define CAN_TDH0R_DATA5_Pos (8U) 06333 #define CAN_TDH0R_DATA5_Msk (0xFFU << CAN_TDH0R_DATA5_Pos) /*!< 0x0000FF00 */ 06334 #define CAN_TDH0R_DATA5 CAN_TDH0R_DATA5_Msk /*!< Data byte 5 */ 06335 #define CAN_TDH0R_DATA6_Pos (16U) 06336 #define CAN_TDH0R_DATA6_Msk (0xFFU << CAN_TDH0R_DATA6_Pos) /*!< 0x00FF0000 */ 06337 #define CAN_TDH0R_DATA6 CAN_TDH0R_DATA6_Msk /*!< Data byte 6 */ 06338 #define CAN_TDH0R_DATA7_Pos (24U) 06339 #define CAN_TDH0R_DATA7_Msk (0xFFU << CAN_TDH0R_DATA7_Pos) /*!< 0xFF000000 */ 06340 #define CAN_TDH0R_DATA7 CAN_TDH0R_DATA7_Msk /*!< Data byte 7 */ 06341 06342 /******************* Bit definition for CAN_TI1R register *******************/ 06343 #define CAN_TI1R_TXRQ_Pos (0U) 06344 #define CAN_TI1R_TXRQ_Msk (0x1U << CAN_TI1R_TXRQ_Pos) /*!< 0x00000001 */ 06345 #define CAN_TI1R_TXRQ CAN_TI1R_TXRQ_Msk /*!< Transmit Mailbox Request */ 06346 #define CAN_TI1R_RTR_Pos (1U) 06347 #define CAN_TI1R_RTR_Msk (0x1U << CAN_TI1R_RTR_Pos) /*!< 0x00000002 */ 06348 #define CAN_TI1R_RTR CAN_TI1R_RTR_Msk /*!< Remote Transmission Request */ 06349 #define CAN_TI1R_IDE_Pos (2U) 06350 #define CAN_TI1R_IDE_Msk (0x1U << CAN_TI1R_IDE_Pos) /*!< 0x00000004 */ 06351 #define CAN_TI1R_IDE CAN_TI1R_IDE_Msk /*!< Identifier Extension */ 06352 #define CAN_TI1R_EXID_Pos (3U) 06353 #define CAN_TI1R_EXID_Msk (0x3FFFFU << CAN_TI1R_EXID_Pos) /*!< 0x001FFFF8 */ 06354 #define CAN_TI1R_EXID CAN_TI1R_EXID_Msk /*!< Extended Identifier */ 06355 #define CAN_TI1R_STID_Pos (21U) 06356 #define CAN_TI1R_STID_Msk (0x7FFU << CAN_TI1R_STID_Pos) /*!< 0xFFE00000 */ 06357 #define CAN_TI1R_STID CAN_TI1R_STID_Msk /*!< Standard Identifier or Extended Identifier */ 06358 06359 /******************* Bit definition for CAN_TDT1R register ******************/ 06360 #define CAN_TDT1R_DLC_Pos (0U) 06361 #define CAN_TDT1R_DLC_Msk (0xFU << CAN_TDT1R_DLC_Pos) /*!< 0x0000000F */ 06362 #define CAN_TDT1R_DLC CAN_TDT1R_DLC_Msk /*!< Data Length Code */ 06363 #define CAN_TDT1R_TGT_Pos (8U) 06364 #define CAN_TDT1R_TGT_Msk (0x1U << CAN_TDT1R_TGT_Pos) /*!< 0x00000100 */ 06365 #define CAN_TDT1R_TGT CAN_TDT1R_TGT_Msk /*!< Transmit Global Time */ 06366 #define CAN_TDT1R_TIME_Pos (16U) 06367 #define CAN_TDT1R_TIME_Msk (0xFFFFU << CAN_TDT1R_TIME_Pos) /*!< 0xFFFF0000 */ 06368 #define CAN_TDT1R_TIME CAN_TDT1R_TIME_Msk /*!< Message Time Stamp */ 06369 06370 /******************* Bit definition for CAN_TDL1R register ******************/ 06371 #define CAN_TDL1R_DATA0_Pos (0U) 06372 #define CAN_TDL1R_DATA0_Msk (0xFFU << CAN_TDL1R_DATA0_Pos) /*!< 0x000000FF */ 06373 #define CAN_TDL1R_DATA0 CAN_TDL1R_DATA0_Msk /*!< Data byte 0 */ 06374 #define CAN_TDL1R_DATA1_Pos (8U) 06375 #define CAN_TDL1R_DATA1_Msk (0xFFU << CAN_TDL1R_DATA1_Pos) /*!< 0x0000FF00 */ 06376 #define CAN_TDL1R_DATA1 CAN_TDL1R_DATA1_Msk /*!< Data byte 1 */ 06377 #define CAN_TDL1R_DATA2_Pos (16U) 06378 #define CAN_TDL1R_DATA2_Msk (0xFFU << CAN_TDL1R_DATA2_Pos) /*!< 0x00FF0000 */ 06379 #define CAN_TDL1R_DATA2 CAN_TDL1R_DATA2_Msk /*!< Data byte 2 */ 06380 #define CAN_TDL1R_DATA3_Pos (24U) 06381 #define CAN_TDL1R_DATA3_Msk (0xFFU << CAN_TDL1R_DATA3_Pos) /*!< 0xFF000000 */ 06382 #define CAN_TDL1R_DATA3 CAN_TDL1R_DATA3_Msk /*!< Data byte 3 */ 06383 06384 /******************* Bit definition for CAN_TDH1R register ******************/ 06385 #define CAN_TDH1R_DATA4_Pos (0U) 06386 #define CAN_TDH1R_DATA4_Msk (0xFFU << CAN_TDH1R_DATA4_Pos) /*!< 0x000000FF */ 06387 #define CAN_TDH1R_DATA4 CAN_TDH1R_DATA4_Msk /*!< Data byte 4 */ 06388 #define CAN_TDH1R_DATA5_Pos (8U) 06389 #define CAN_TDH1R_DATA5_Msk (0xFFU << CAN_TDH1R_DATA5_Pos) /*!< 0x0000FF00 */ 06390 #define CAN_TDH1R_DATA5 CAN_TDH1R_DATA5_Msk /*!< Data byte 5 */ 06391 #define CAN_TDH1R_DATA6_Pos (16U) 06392 #define CAN_TDH1R_DATA6_Msk (0xFFU << CAN_TDH1R_DATA6_Pos) /*!< 0x00FF0000 */ 06393 #define CAN_TDH1R_DATA6 CAN_TDH1R_DATA6_Msk /*!< Data byte 6 */ 06394 #define CAN_TDH1R_DATA7_Pos (24U) 06395 #define CAN_TDH1R_DATA7_Msk (0xFFU << CAN_TDH1R_DATA7_Pos) /*!< 0xFF000000 */ 06396 #define CAN_TDH1R_DATA7 CAN_TDH1R_DATA7_Msk /*!< Data byte 7 */ 06397 06398 /******************* Bit definition for CAN_TI2R register *******************/ 06399 #define CAN_TI2R_TXRQ_Pos (0U) 06400 #define CAN_TI2R_TXRQ_Msk (0x1U << CAN_TI2R_TXRQ_Pos) /*!< 0x00000001 */ 06401 #define CAN_TI2R_TXRQ CAN_TI2R_TXRQ_Msk /*!< Transmit Mailbox Request */ 06402 #define CAN_TI2R_RTR_Pos (1U) 06403 #define CAN_TI2R_RTR_Msk (0x1U << CAN_TI2R_RTR_Pos) /*!< 0x00000002 */ 06404 #define CAN_TI2R_RTR CAN_TI2R_RTR_Msk /*!< Remote Transmission Request */ 06405 #define CAN_TI2R_IDE_Pos (2U) 06406 #define CAN_TI2R_IDE_Msk (0x1U << CAN_TI2R_IDE_Pos) /*!< 0x00000004 */ 06407 #define CAN_TI2R_IDE CAN_TI2R_IDE_Msk /*!< Identifier Extension */ 06408 #define CAN_TI2R_EXID_Pos (3U) 06409 #define CAN_TI2R_EXID_Msk (0x3FFFFU << CAN_TI2R_EXID_Pos) /*!< 0x001FFFF8 */ 06410 #define CAN_TI2R_EXID CAN_TI2R_EXID_Msk /*!< Extended identifier */ 06411 #define CAN_TI2R_STID_Pos (21U) 06412 #define CAN_TI2R_STID_Msk (0x7FFU << CAN_TI2R_STID_Pos) /*!< 0xFFE00000 */ 06413 #define CAN_TI2R_STID CAN_TI2R_STID_Msk /*!< Standard Identifier or Extended Identifier */ 06414 06415 /******************* Bit definition for CAN_TDT2R register ******************/ 06416 #define CAN_TDT2R_DLC_Pos (0U) 06417 #define CAN_TDT2R_DLC_Msk (0xFU << CAN_TDT2R_DLC_Pos) /*!< 0x0000000F */ 06418 #define CAN_TDT2R_DLC CAN_TDT2R_DLC_Msk /*!< Data Length Code */ 06419 #define CAN_TDT2R_TGT_Pos (8U) 06420 #define CAN_TDT2R_TGT_Msk (0x1U << CAN_TDT2R_TGT_Pos) /*!< 0x00000100 */ 06421 #define CAN_TDT2R_TGT CAN_TDT2R_TGT_Msk /*!< Transmit Global Time */ 06422 #define CAN_TDT2R_TIME_Pos (16U) 06423 #define CAN_TDT2R_TIME_Msk (0xFFFFU << CAN_TDT2R_TIME_Pos) /*!< 0xFFFF0000 */ 06424 #define CAN_TDT2R_TIME CAN_TDT2R_TIME_Msk /*!< Message Time Stamp */ 06425 06426 /******************* Bit definition for CAN_TDL2R register ******************/ 06427 #define CAN_TDL2R_DATA0_Pos (0U) 06428 #define CAN_TDL2R_DATA0_Msk (0xFFU << CAN_TDL2R_DATA0_Pos) /*!< 0x000000FF */ 06429 #define CAN_TDL2R_DATA0 CAN_TDL2R_DATA0_Msk /*!< Data byte 0 */ 06430 #define CAN_TDL2R_DATA1_Pos (8U) 06431 #define CAN_TDL2R_DATA1_Msk (0xFFU << CAN_TDL2R_DATA1_Pos) /*!< 0x0000FF00 */ 06432 #define CAN_TDL2R_DATA1 CAN_TDL2R_DATA1_Msk /*!< Data byte 1 */ 06433 #define CAN_TDL2R_DATA2_Pos (16U) 06434 #define CAN_TDL2R_DATA2_Msk (0xFFU << CAN_TDL2R_DATA2_Pos) /*!< 0x00FF0000 */ 06435 #define CAN_TDL2R_DATA2 CAN_TDL2R_DATA2_Msk /*!< Data byte 2 */ 06436 #define CAN_TDL2R_DATA3_Pos (24U) 06437 #define CAN_TDL2R_DATA3_Msk (0xFFU << CAN_TDL2R_DATA3_Pos) /*!< 0xFF000000 */ 06438 #define CAN_TDL2R_DATA3 CAN_TDL2R_DATA3_Msk /*!< Data byte 3 */ 06439 06440 /******************* Bit definition for CAN_TDH2R register ******************/ 06441 #define CAN_TDH2R_DATA4_Pos (0U) 06442 #define CAN_TDH2R_DATA4_Msk (0xFFU << CAN_TDH2R_DATA4_Pos) /*!< 0x000000FF */ 06443 #define CAN_TDH2R_DATA4 CAN_TDH2R_DATA4_Msk /*!< Data byte 4 */ 06444 #define CAN_TDH2R_DATA5_Pos (8U) 06445 #define CAN_TDH2R_DATA5_Msk (0xFFU << CAN_TDH2R_DATA5_Pos) /*!< 0x0000FF00 */ 06446 #define CAN_TDH2R_DATA5 CAN_TDH2R_DATA5_Msk /*!< Data byte 5 */ 06447 #define CAN_TDH2R_DATA6_Pos (16U) 06448 #define CAN_TDH2R_DATA6_Msk (0xFFU << CAN_TDH2R_DATA6_Pos) /*!< 0x00FF0000 */ 06449 #define CAN_TDH2R_DATA6 CAN_TDH2R_DATA6_Msk /*!< Data byte 6 */ 06450 #define CAN_TDH2R_DATA7_Pos (24U) 06451 #define CAN_TDH2R_DATA7_Msk (0xFFU << CAN_TDH2R_DATA7_Pos) /*!< 0xFF000000 */ 06452 #define CAN_TDH2R_DATA7 CAN_TDH2R_DATA7_Msk /*!< Data byte 7 */ 06453 06454 /******************* Bit definition for CAN_RI0R register *******************/ 06455 #define CAN_RI0R_RTR_Pos (1U) 06456 #define CAN_RI0R_RTR_Msk (0x1U << CAN_RI0R_RTR_Pos) /*!< 0x00000002 */ 06457 #define CAN_RI0R_RTR CAN_RI0R_RTR_Msk /*!< Remote Transmission Request */ 06458 #define CAN_RI0R_IDE_Pos (2U) 06459 #define CAN_RI0R_IDE_Msk (0x1U << CAN_RI0R_IDE_Pos) /*!< 0x00000004 */ 06460 #define CAN_RI0R_IDE CAN_RI0R_IDE_Msk /*!< Identifier Extension */ 06461 #define CAN_RI0R_EXID_Pos (3U) 06462 #define CAN_RI0R_EXID_Msk (0x3FFFFU << CAN_RI0R_EXID_Pos) /*!< 0x001FFFF8 */ 06463 #define CAN_RI0R_EXID CAN_RI0R_EXID_Msk /*!< Extended Identifier */ 06464 #define CAN_RI0R_STID_Pos (21U) 06465 #define CAN_RI0R_STID_Msk (0x7FFU << CAN_RI0R_STID_Pos) /*!< 0xFFE00000 */ 06466 #define CAN_RI0R_STID CAN_RI0R_STID_Msk /*!< Standard Identifier or Extended Identifier */ 06467 06468 /******************* Bit definition for CAN_RDT0R register ******************/ 06469 #define CAN_RDT0R_DLC_Pos (0U) 06470 #define CAN_RDT0R_DLC_Msk (0xFU << CAN_RDT0R_DLC_Pos) /*!< 0x0000000F */ 06471 #define CAN_RDT0R_DLC CAN_RDT0R_DLC_Msk /*!< Data Length Code */ 06472 #define CAN_RDT0R_FMI_Pos (8U) 06473 #define CAN_RDT0R_FMI_Msk (0xFFU << CAN_RDT0R_FMI_Pos) /*!< 0x0000FF00 */ 06474 #define CAN_RDT0R_FMI CAN_RDT0R_FMI_Msk /*!< Filter Match Index */ 06475 #define CAN_RDT0R_TIME_Pos (16U) 06476 #define CAN_RDT0R_TIME_Msk (0xFFFFU << CAN_RDT0R_TIME_Pos) /*!< 0xFFFF0000 */ 06477 #define CAN_RDT0R_TIME CAN_RDT0R_TIME_Msk /*!< Message Time Stamp */ 06478 06479 /******************* Bit definition for CAN_RDL0R register ******************/ 06480 #define CAN_RDL0R_DATA0_Pos (0U) 06481 #define CAN_RDL0R_DATA0_Msk (0xFFU << CAN_RDL0R_DATA0_Pos) /*!< 0x000000FF */ 06482 #define CAN_RDL0R_DATA0 CAN_RDL0R_DATA0_Msk /*!< Data byte 0 */ 06483 #define CAN_RDL0R_DATA1_Pos (8U) 06484 #define CAN_RDL0R_DATA1_Msk (0xFFU << CAN_RDL0R_DATA1_Pos) /*!< 0x0000FF00 */ 06485 #define CAN_RDL0R_DATA1 CAN_RDL0R_DATA1_Msk /*!< Data byte 1 */ 06486 #define CAN_RDL0R_DATA2_Pos (16U) 06487 #define CAN_RDL0R_DATA2_Msk (0xFFU << CAN_RDL0R_DATA2_Pos) /*!< 0x00FF0000 */ 06488 #define CAN_RDL0R_DATA2 CAN_RDL0R_DATA2_Msk /*!< Data byte 2 */ 06489 #define CAN_RDL0R_DATA3_Pos (24U) 06490 #define CAN_RDL0R_DATA3_Msk (0xFFU << CAN_RDL0R_DATA3_Pos) /*!< 0xFF000000 */ 06491 #define CAN_RDL0R_DATA3 CAN_RDL0R_DATA3_Msk /*!< Data byte 3 */ 06492 06493 /******************* Bit definition for CAN_RDH0R register ******************/ 06494 #define CAN_RDH0R_DATA4_Pos (0U) 06495 #define CAN_RDH0R_DATA4_Msk (0xFFU << CAN_RDH0R_DATA4_Pos) /*!< 0x000000FF */ 06496 #define CAN_RDH0R_DATA4 CAN_RDH0R_DATA4_Msk /*!< Data byte 4 */ 06497 #define CAN_RDH0R_DATA5_Pos (8U) 06498 #define CAN_RDH0R_DATA5_Msk (0xFFU << CAN_RDH0R_DATA5_Pos) /*!< 0x0000FF00 */ 06499 #define CAN_RDH0R_DATA5 CAN_RDH0R_DATA5_Msk /*!< Data byte 5 */ 06500 #define CAN_RDH0R_DATA6_Pos (16U) 06501 #define CAN_RDH0R_DATA6_Msk (0xFFU << CAN_RDH0R_DATA6_Pos) /*!< 0x00FF0000 */ 06502 #define CAN_RDH0R_DATA6 CAN_RDH0R_DATA6_Msk /*!< Data byte 6 */ 06503 #define CAN_RDH0R_DATA7_Pos (24U) 06504 #define CAN_RDH0R_DATA7_Msk (0xFFU << CAN_RDH0R_DATA7_Pos) /*!< 0xFF000000 */ 06505 #define CAN_RDH0R_DATA7 CAN_RDH0R_DATA7_Msk /*!< Data byte 7 */ 06506 06507 /******************* Bit definition for CAN_RI1R register *******************/ 06508 #define CAN_RI1R_RTR_Pos (1U) 06509 #define CAN_RI1R_RTR_Msk (0x1U << CAN_RI1R_RTR_Pos) /*!< 0x00000002 */ 06510 #define CAN_RI1R_RTR CAN_RI1R_RTR_Msk /*!< Remote Transmission Request */ 06511 #define CAN_RI1R_IDE_Pos (2U) 06512 #define CAN_RI1R_IDE_Msk (0x1U << CAN_RI1R_IDE_Pos) /*!< 0x00000004 */ 06513 #define CAN_RI1R_IDE CAN_RI1R_IDE_Msk /*!< Identifier Extension */ 06514 #define CAN_RI1R_EXID_Pos (3U) 06515 #define CAN_RI1R_EXID_Msk (0x3FFFFU << CAN_RI1R_EXID_Pos) /*!< 0x001FFFF8 */ 06516 #define CAN_RI1R_EXID CAN_RI1R_EXID_Msk /*!< Extended identifier */ 06517 #define CAN_RI1R_STID_Pos (21U) 06518 #define CAN_RI1R_STID_Msk (0x7FFU << CAN_RI1R_STID_Pos) /*!< 0xFFE00000 */ 06519 #define CAN_RI1R_STID CAN_RI1R_STID_Msk /*!< Standard Identifier or Extended Identifier */ 06520 06521 /******************* Bit definition for CAN_RDT1R register ******************/ 06522 #define CAN_RDT1R_DLC_Pos (0U) 06523 #define CAN_RDT1R_DLC_Msk (0xFU << CAN_RDT1R_DLC_Pos) /*!< 0x0000000F */ 06524 #define CAN_RDT1R_DLC CAN_RDT1R_DLC_Msk /*!< Data Length Code */ 06525 #define CAN_RDT1R_FMI_Pos (8U) 06526 #define CAN_RDT1R_FMI_Msk (0xFFU << CAN_RDT1R_FMI_Pos) /*!< 0x0000FF00 */ 06527 #define CAN_RDT1R_FMI CAN_RDT1R_FMI_Msk /*!< Filter Match Index */ 06528 #define CAN_RDT1R_TIME_Pos (16U) 06529 #define CAN_RDT1R_TIME_Msk (0xFFFFU << CAN_RDT1R_TIME_Pos) /*!< 0xFFFF0000 */ 06530 #define CAN_RDT1R_TIME CAN_RDT1R_TIME_Msk /*!< Message Time Stamp */ 06531 06532 /******************* Bit definition for CAN_RDL1R register ******************/ 06533 #define CAN_RDL1R_DATA0_Pos (0U) 06534 #define CAN_RDL1R_DATA0_Msk (0xFFU << CAN_RDL1R_DATA0_Pos) /*!< 0x000000FF */ 06535 #define CAN_RDL1R_DATA0 CAN_RDL1R_DATA0_Msk /*!< Data byte 0 */ 06536 #define CAN_RDL1R_DATA1_Pos (8U) 06537 #define CAN_RDL1R_DATA1_Msk (0xFFU << CAN_RDL1R_DATA1_Pos) /*!< 0x0000FF00 */ 06538 #define CAN_RDL1R_DATA1 CAN_RDL1R_DATA1_Msk /*!< Data byte 1 */ 06539 #define CAN_RDL1R_DATA2_Pos (16U) 06540 #define CAN_RDL1R_DATA2_Msk (0xFFU << CAN_RDL1R_DATA2_Pos) /*!< 0x00FF0000 */ 06541 #define CAN_RDL1R_DATA2 CAN_RDL1R_DATA2_Msk /*!< Data byte 2 */ 06542 #define CAN_RDL1R_DATA3_Pos (24U) 06543 #define CAN_RDL1R_DATA3_Msk (0xFFU << CAN_RDL1R_DATA3_Pos) /*!< 0xFF000000 */ 06544 #define CAN_RDL1R_DATA3 CAN_RDL1R_DATA3_Msk /*!< Data byte 3 */ 06545 06546 /******************* Bit definition for CAN_RDH1R register ******************/ 06547 #define CAN_RDH1R_DATA4_Pos (0U) 06548 #define CAN_RDH1R_DATA4_Msk (0xFFU << CAN_RDH1R_DATA4_Pos) /*!< 0x000000FF */ 06549 #define CAN_RDH1R_DATA4 CAN_RDH1R_DATA4_Msk /*!< Data byte 4 */ 06550 #define CAN_RDH1R_DATA5_Pos (8U) 06551 #define CAN_RDH1R_DATA5_Msk (0xFFU << CAN_RDH1R_DATA5_Pos) /*!< 0x0000FF00 */ 06552 #define CAN_RDH1R_DATA5 CAN_RDH1R_DATA5_Msk /*!< Data byte 5 */ 06553 #define CAN_RDH1R_DATA6_Pos (16U) 06554 #define CAN_RDH1R_DATA6_Msk (0xFFU << CAN_RDH1R_DATA6_Pos) /*!< 0x00FF0000 */ 06555 #define CAN_RDH1R_DATA6 CAN_RDH1R_DATA6_Msk /*!< Data byte 6 */ 06556 #define CAN_RDH1R_DATA7_Pos (24U) 06557 #define CAN_RDH1R_DATA7_Msk (0xFFU << CAN_RDH1R_DATA7_Pos) /*!< 0xFF000000 */ 06558 #define CAN_RDH1R_DATA7 CAN_RDH1R_DATA7_Msk /*!< Data byte 7 */ 06559 06560 /*!< CAN filter registers */ 06561 /******************* Bit definition for CAN_FMR register ********************/ 06562 #define CAN_FMR_FINIT_Pos (0U) 06563 #define CAN_FMR_FINIT_Msk (0x1U << CAN_FMR_FINIT_Pos) /*!< 0x00000001 */ 06564 #define CAN_FMR_FINIT CAN_FMR_FINIT_Msk /*!< Filter Init Mode */ 06565 #define CAN_FMR_CAN2SB_Pos (8U) 06566 #define CAN_FMR_CAN2SB_Msk (0x3FU << CAN_FMR_CAN2SB_Pos) /*!< 0x00003F00 */ 06567 #define CAN_FMR_CAN2SB CAN_FMR_CAN2SB_Msk /*!< CAN2 start bank */ 06568 06569 /******************* Bit definition for CAN_FM1R register *******************/ 06570 #define CAN_FM1R_FBM_Pos (0U) 06571 #define CAN_FM1R_FBM_Msk (0x3FFFU << CAN_FM1R_FBM_Pos) /*!< 0x00003FFF */ 06572 #define CAN_FM1R_FBM CAN_FM1R_FBM_Msk /*!< Filter Mode */ 06573 #define CAN_FM1R_FBM0_Pos (0U) 06574 #define CAN_FM1R_FBM0_Msk (0x1U << CAN_FM1R_FBM0_Pos) /*!< 0x00000001 */ 06575 #define CAN_FM1R_FBM0 CAN_FM1R_FBM0_Msk /*!< Filter Init Mode for filter 0 */ 06576 #define CAN_FM1R_FBM1_Pos (1U) 06577 #define CAN_FM1R_FBM1_Msk (0x1U << CAN_FM1R_FBM1_Pos) /*!< 0x00000002 */ 06578 #define CAN_FM1R_FBM1 CAN_FM1R_FBM1_Msk /*!< Filter Init Mode for filter 1 */ 06579 #define CAN_FM1R_FBM2_Pos (2U) 06580 #define CAN_FM1R_FBM2_Msk (0x1U << CAN_FM1R_FBM2_Pos) /*!< 0x00000004 */ 06581 #define CAN_FM1R_FBM2 CAN_FM1R_FBM2_Msk /*!< Filter Init Mode for filter 2 */ 06582 #define CAN_FM1R_FBM3_Pos (3U) 06583 #define CAN_FM1R_FBM3_Msk (0x1U << CAN_FM1R_FBM3_Pos) /*!< 0x00000008 */ 06584 #define CAN_FM1R_FBM3 CAN_FM1R_FBM3_Msk /*!< Filter Init Mode for filter 3 */ 06585 #define CAN_FM1R_FBM4_Pos (4U) 06586 #define CAN_FM1R_FBM4_Msk (0x1U << CAN_FM1R_FBM4_Pos) /*!< 0x00000010 */ 06587 #define CAN_FM1R_FBM4 CAN_FM1R_FBM4_Msk /*!< Filter Init Mode for filter 4 */ 06588 #define CAN_FM1R_FBM5_Pos (5U) 06589 #define CAN_FM1R_FBM5_Msk (0x1U << CAN_FM1R_FBM5_Pos) /*!< 0x00000020 */ 06590 #define CAN_FM1R_FBM5 CAN_FM1R_FBM5_Msk /*!< Filter Init Mode for filter 5 */ 06591 #define CAN_FM1R_FBM6_Pos (6U) 06592 #define CAN_FM1R_FBM6_Msk (0x1U << CAN_FM1R_FBM6_Pos) /*!< 0x00000040 */ 06593 #define CAN_FM1R_FBM6 CAN_FM1R_FBM6_Msk /*!< Filter Init Mode for filter 6 */ 06594 #define CAN_FM1R_FBM7_Pos (7U) 06595 #define CAN_FM1R_FBM7_Msk (0x1U << CAN_FM1R_FBM7_Pos) /*!< 0x00000080 */ 06596 #define CAN_FM1R_FBM7 CAN_FM1R_FBM7_Msk /*!< Filter Init Mode for filter 7 */ 06597 #define CAN_FM1R_FBM8_Pos (8U) 06598 #define CAN_FM1R_FBM8_Msk (0x1U << CAN_FM1R_FBM8_Pos) /*!< 0x00000100 */ 06599 #define CAN_FM1R_FBM8 CAN_FM1R_FBM8_Msk /*!< Filter Init Mode for filter 8 */ 06600 #define CAN_FM1R_FBM9_Pos (9U) 06601 #define CAN_FM1R_FBM9_Msk (0x1U << CAN_FM1R_FBM9_Pos) /*!< 0x00000200 */ 06602 #define CAN_FM1R_FBM9 CAN_FM1R_FBM9_Msk /*!< Filter Init Mode for filter 9 */ 06603 #define CAN_FM1R_FBM10_Pos (10U) 06604 #define CAN_FM1R_FBM10_Msk (0x1U << CAN_FM1R_FBM10_Pos) /*!< 0x00000400 */ 06605 #define CAN_FM1R_FBM10 CAN_FM1R_FBM10_Msk /*!< Filter Init Mode for filter 10 */ 06606 #define CAN_FM1R_FBM11_Pos (11U) 06607 #define CAN_FM1R_FBM11_Msk (0x1U << CAN_FM1R_FBM11_Pos) /*!< 0x00000800 */ 06608 #define CAN_FM1R_FBM11 CAN_FM1R_FBM11_Msk /*!< Filter Init Mode for filter 11 */ 06609 #define CAN_FM1R_FBM12_Pos (12U) 06610 #define CAN_FM1R_FBM12_Msk (0x1U << CAN_FM1R_FBM12_Pos) /*!< 0x00001000 */ 06611 #define CAN_FM1R_FBM12 CAN_FM1R_FBM12_Msk /*!< Filter Init Mode for filter 12 */ 06612 #define CAN_FM1R_FBM13_Pos (13U) 06613 #define CAN_FM1R_FBM13_Msk (0x1U << CAN_FM1R_FBM13_Pos) /*!< 0x00002000 */ 06614 #define CAN_FM1R_FBM13 CAN_FM1R_FBM13_Msk /*!< Filter Init Mode for filter 13 */ 06615 06616 /******************* Bit definition for CAN_FS1R register *******************/ 06617 #define CAN_FS1R_FSC_Pos (0U) 06618 #define CAN_FS1R_FSC_Msk (0x3FFFU << CAN_FS1R_FSC_Pos) /*!< 0x00003FFF */ 06619 #define CAN_FS1R_FSC CAN_FS1R_FSC_Msk /*!< Filter Scale Configuration */ 06620 #define CAN_FS1R_FSC0_Pos (0U) 06621 #define CAN_FS1R_FSC0_Msk (0x1U << CAN_FS1R_FSC0_Pos) /*!< 0x00000001 */ 06622 #define CAN_FS1R_FSC0 CAN_FS1R_FSC0_Msk /*!< Filter Scale Configuration for filter 0 */ 06623 #define CAN_FS1R_FSC1_Pos (1U) 06624 #define CAN_FS1R_FSC1_Msk (0x1U << CAN_FS1R_FSC1_Pos) /*!< 0x00000002 */ 06625 #define CAN_FS1R_FSC1 CAN_FS1R_FSC1_Msk /*!< Filter Scale Configuration for filter 1 */ 06626 #define CAN_FS1R_FSC2_Pos (2U) 06627 #define CAN_FS1R_FSC2_Msk (0x1U << CAN_FS1R_FSC2_Pos) /*!< 0x00000004 */ 06628 #define CAN_FS1R_FSC2 CAN_FS1R_FSC2_Msk /*!< Filter Scale Configuration for filter 2 */ 06629 #define CAN_FS1R_FSC3_Pos (3U) 06630 #define CAN_FS1R_FSC3_Msk (0x1U << CAN_FS1R_FSC3_Pos) /*!< 0x00000008 */ 06631 #define CAN_FS1R_FSC3 CAN_FS1R_FSC3_Msk /*!< Filter Scale Configuration for filter 3 */ 06632 #define CAN_FS1R_FSC4_Pos (4U) 06633 #define CAN_FS1R_FSC4_Msk (0x1U << CAN_FS1R_FSC4_Pos) /*!< 0x00000010 */ 06634 #define CAN_FS1R_FSC4 CAN_FS1R_FSC4_Msk /*!< Filter Scale Configuration for filter 4 */ 06635 #define CAN_FS1R_FSC5_Pos (5U) 06636 #define CAN_FS1R_FSC5_Msk (0x1U << CAN_FS1R_FSC5_Pos) /*!< 0x00000020 */ 06637 #define CAN_FS1R_FSC5 CAN_FS1R_FSC5_Msk /*!< Filter Scale Configuration for filter 5 */ 06638 #define CAN_FS1R_FSC6_Pos (6U) 06639 #define CAN_FS1R_FSC6_Msk (0x1U << CAN_FS1R_FSC6_Pos) /*!< 0x00000040 */ 06640 #define CAN_FS1R_FSC6 CAN_FS1R_FSC6_Msk /*!< Filter Scale Configuration for filter 6 */ 06641 #define CAN_FS1R_FSC7_Pos (7U) 06642 #define CAN_FS1R_FSC7_Msk (0x1U << CAN_FS1R_FSC7_Pos) /*!< 0x00000080 */ 06643 #define CAN_FS1R_FSC7 CAN_FS1R_FSC7_Msk /*!< Filter Scale Configuration for filter 7 */ 06644 #define CAN_FS1R_FSC8_Pos (8U) 06645 #define CAN_FS1R_FSC8_Msk (0x1U << CAN_FS1R_FSC8_Pos) /*!< 0x00000100 */ 06646 #define CAN_FS1R_FSC8 CAN_FS1R_FSC8_Msk /*!< Filter Scale Configuration for filter 8 */ 06647 #define CAN_FS1R_FSC9_Pos (9U) 06648 #define CAN_FS1R_FSC9_Msk (0x1U << CAN_FS1R_FSC9_Pos) /*!< 0x00000200 */ 06649 #define CAN_FS1R_FSC9 CAN_FS1R_FSC9_Msk /*!< Filter Scale Configuration for filter 9 */ 06650 #define CAN_FS1R_FSC10_Pos (10U) 06651 #define CAN_FS1R_FSC10_Msk (0x1U << CAN_FS1R_FSC10_Pos) /*!< 0x00000400 */ 06652 #define CAN_FS1R_FSC10 CAN_FS1R_FSC10_Msk /*!< Filter Scale Configuration for filter 10 */ 06653 #define CAN_FS1R_FSC11_Pos (11U) 06654 #define CAN_FS1R_FSC11_Msk (0x1U << CAN_FS1R_FSC11_Pos) /*!< 0x00000800 */ 06655 #define CAN_FS1R_FSC11 CAN_FS1R_FSC11_Msk /*!< Filter Scale Configuration for filter 11 */ 06656 #define CAN_FS1R_FSC12_Pos (12U) 06657 #define CAN_FS1R_FSC12_Msk (0x1U << CAN_FS1R_FSC12_Pos) /*!< 0x00001000 */ 06658 #define CAN_FS1R_FSC12 CAN_FS1R_FSC12_Msk /*!< Filter Scale Configuration for filter 12 */ 06659 #define CAN_FS1R_FSC13_Pos (13U) 06660 #define CAN_FS1R_FSC13_Msk (0x1U << CAN_FS1R_FSC13_Pos) /*!< 0x00002000 */ 06661 #define CAN_FS1R_FSC13 CAN_FS1R_FSC13_Msk /*!< Filter Scale Configuration for filter 13 */ 06662 06663 /****************** Bit definition for CAN_FFA1R register *******************/ 06664 #define CAN_FFA1R_FFA_Pos (0U) 06665 #define CAN_FFA1R_FFA_Msk (0x3FFFU << CAN_FFA1R_FFA_Pos) /*!< 0x00003FFF */ 06666 #define CAN_FFA1R_FFA CAN_FFA1R_FFA_Msk /*!< Filter FIFO Assignment */ 06667 #define CAN_FFA1R_FFA0_Pos (0U) 06668 #define CAN_FFA1R_FFA0_Msk (0x1U << CAN_FFA1R_FFA0_Pos) /*!< 0x00000001 */ 06669 #define CAN_FFA1R_FFA0 CAN_FFA1R_FFA0_Msk /*!< Filter FIFO Assignment for filter 0 */ 06670 #define CAN_FFA1R_FFA1_Pos (1U) 06671 #define CAN_FFA1R_FFA1_Msk (0x1U << CAN_FFA1R_FFA1_Pos) /*!< 0x00000002 */ 06672 #define CAN_FFA1R_FFA1 CAN_FFA1R_FFA1_Msk /*!< Filter FIFO Assignment for filter 1 */ 06673 #define CAN_FFA1R_FFA2_Pos (2U) 06674 #define CAN_FFA1R_FFA2_Msk (0x1U << CAN_FFA1R_FFA2_Pos) /*!< 0x00000004 */ 06675 #define CAN_FFA1R_FFA2 CAN_FFA1R_FFA2_Msk /*!< Filter FIFO Assignment for filter 2 */ 06676 #define CAN_FFA1R_FFA3_Pos (3U) 06677 #define CAN_FFA1R_FFA3_Msk (0x1U << CAN_FFA1R_FFA3_Pos) /*!< 0x00000008 */ 06678 #define CAN_FFA1R_FFA3 CAN_FFA1R_FFA3_Msk /*!< Filter FIFO Assignment for filter 3 */ 06679 #define CAN_FFA1R_FFA4_Pos (4U) 06680 #define CAN_FFA1R_FFA4_Msk (0x1U << CAN_FFA1R_FFA4_Pos) /*!< 0x00000010 */ 06681 #define CAN_FFA1R_FFA4 CAN_FFA1R_FFA4_Msk /*!< Filter FIFO Assignment for filter 4 */ 06682 #define CAN_FFA1R_FFA5_Pos (5U) 06683 #define CAN_FFA1R_FFA5_Msk (0x1U << CAN_FFA1R_FFA5_Pos) /*!< 0x00000020 */ 06684 #define CAN_FFA1R_FFA5 CAN_FFA1R_FFA5_Msk /*!< Filter FIFO Assignment for filter 5 */ 06685 #define CAN_FFA1R_FFA6_Pos (6U) 06686 #define CAN_FFA1R_FFA6_Msk (0x1U << CAN_FFA1R_FFA6_Pos) /*!< 0x00000040 */ 06687 #define CAN_FFA1R_FFA6 CAN_FFA1R_FFA6_Msk /*!< Filter FIFO Assignment for filter 6 */ 06688 #define CAN_FFA1R_FFA7_Pos (7U) 06689 #define CAN_FFA1R_FFA7_Msk (0x1U << CAN_FFA1R_FFA7_Pos) /*!< 0x00000080 */ 06690 #define CAN_FFA1R_FFA7 CAN_FFA1R_FFA7_Msk /*!< Filter FIFO Assignment for filter 7 */ 06691 #define CAN_FFA1R_FFA8_Pos (8U) 06692 #define CAN_FFA1R_FFA8_Msk (0x1U << CAN_FFA1R_FFA8_Pos) /*!< 0x00000100 */ 06693 #define CAN_FFA1R_FFA8 CAN_FFA1R_FFA8_Msk /*!< Filter FIFO Assignment for filter 8 */ 06694 #define CAN_FFA1R_FFA9_Pos (9U) 06695 #define CAN_FFA1R_FFA9_Msk (0x1U << CAN_FFA1R_FFA9_Pos) /*!< 0x00000200 */ 06696 #define CAN_FFA1R_FFA9 CAN_FFA1R_FFA9_Msk /*!< Filter FIFO Assignment for filter 9 */ 06697 #define CAN_FFA1R_FFA10_Pos (10U) 06698 #define CAN_FFA1R_FFA10_Msk (0x1U << CAN_FFA1R_FFA10_Pos) /*!< 0x00000400 */ 06699 #define CAN_FFA1R_FFA10 CAN_FFA1R_FFA10_Msk /*!< Filter FIFO Assignment for filter 10 */ 06700 #define CAN_FFA1R_FFA11_Pos (11U) 06701 #define CAN_FFA1R_FFA11_Msk (0x1U << CAN_FFA1R_FFA11_Pos) /*!< 0x00000800 */ 06702 #define CAN_FFA1R_FFA11 CAN_FFA1R_FFA11_Msk /*!< Filter FIFO Assignment for filter 11 */ 06703 #define CAN_FFA1R_FFA12_Pos (12U) 06704 #define CAN_FFA1R_FFA12_Msk (0x1U << CAN_FFA1R_FFA12_Pos) /*!< 0x00001000 */ 06705 #define CAN_FFA1R_FFA12 CAN_FFA1R_FFA12_Msk /*!< Filter FIFO Assignment for filter 12 */ 06706 #define CAN_FFA1R_FFA13_Pos (13U) 06707 #define CAN_FFA1R_FFA13_Msk (0x1U << CAN_FFA1R_FFA13_Pos) /*!< 0x00002000 */ 06708 #define CAN_FFA1R_FFA13 CAN_FFA1R_FFA13_Msk /*!< Filter FIFO Assignment for filter 13 */ 06709 06710 /******************* Bit definition for CAN_FA1R register *******************/ 06711 #define CAN_FA1R_FACT_Pos (0U) 06712 #define CAN_FA1R_FACT_Msk (0x3FFFU << CAN_FA1R_FACT_Pos) /*!< 0x00003FFF */ 06713 #define CAN_FA1R_FACT CAN_FA1R_FACT_Msk /*!< Filter Active */ 06714 #define CAN_FA1R_FACT0_Pos (0U) 06715 #define CAN_FA1R_FACT0_Msk (0x1U << CAN_FA1R_FACT0_Pos) /*!< 0x00000001 */ 06716 #define CAN_FA1R_FACT0 CAN_FA1R_FACT0_Msk /*!< Filter 0 Active */ 06717 #define CAN_FA1R_FACT1_Pos (1U) 06718 #define CAN_FA1R_FACT1_Msk (0x1U << CAN_FA1R_FACT1_Pos) /*!< 0x00000002 */ 06719 #define CAN_FA1R_FACT1 CAN_FA1R_FACT1_Msk /*!< Filter 1 Active */ 06720 #define CAN_FA1R_FACT2_Pos (2U) 06721 #define CAN_FA1R_FACT2_Msk (0x1U << CAN_FA1R_FACT2_Pos) /*!< 0x00000004 */ 06722 #define CAN_FA1R_FACT2 CAN_FA1R_FACT2_Msk /*!< Filter 2 Active */ 06723 #define CAN_FA1R_FACT3_Pos (3U) 06724 #define CAN_FA1R_FACT3_Msk (0x1U << CAN_FA1R_FACT3_Pos) /*!< 0x00000008 */ 06725 #define CAN_FA1R_FACT3 CAN_FA1R_FACT3_Msk /*!< Filter 3 Active */ 06726 #define CAN_FA1R_FACT4_Pos (4U) 06727 #define CAN_FA1R_FACT4_Msk (0x1U << CAN_FA1R_FACT4_Pos) /*!< 0x00000010 */ 06728 #define CAN_FA1R_FACT4 CAN_FA1R_FACT4_Msk /*!< Filter 4 Active */ 06729 #define CAN_FA1R_FACT5_Pos (5U) 06730 #define CAN_FA1R_FACT5_Msk (0x1U << CAN_FA1R_FACT5_Pos) /*!< 0x00000020 */ 06731 #define CAN_FA1R_FACT5 CAN_FA1R_FACT5_Msk /*!< Filter 5 Active */ 06732 #define CAN_FA1R_FACT6_Pos (6U) 06733 #define CAN_FA1R_FACT6_Msk (0x1U << CAN_FA1R_FACT6_Pos) /*!< 0x00000040 */ 06734 #define CAN_FA1R_FACT6 CAN_FA1R_FACT6_Msk /*!< Filter 6 Active */ 06735 #define CAN_FA1R_FACT7_Pos (7U) 06736 #define CAN_FA1R_FACT7_Msk (0x1U << CAN_FA1R_FACT7_Pos) /*!< 0x00000080 */ 06737 #define CAN_FA1R_FACT7 CAN_FA1R_FACT7_Msk /*!< Filter 7 Active */ 06738 #define CAN_FA1R_FACT8_Pos (8U) 06739 #define CAN_FA1R_FACT8_Msk (0x1U << CAN_FA1R_FACT8_Pos) /*!< 0x00000100 */ 06740 #define CAN_FA1R_FACT8 CAN_FA1R_FACT8_Msk /*!< Filter 8 Active */ 06741 #define CAN_FA1R_FACT9_Pos (9U) 06742 #define CAN_FA1R_FACT9_Msk (0x1U << CAN_FA1R_FACT9_Pos) /*!< 0x00000200 */ 06743 #define CAN_FA1R_FACT9 CAN_FA1R_FACT9_Msk /*!< Filter 9 Active */ 06744 #define CAN_FA1R_FACT10_Pos (10U) 06745 #define CAN_FA1R_FACT10_Msk (0x1U << CAN_FA1R_FACT10_Pos) /*!< 0x00000400 */ 06746 #define CAN_FA1R_FACT10 CAN_FA1R_FACT10_Msk /*!< Filter 10 Active */ 06747 #define CAN_FA1R_FACT11_Pos (11U) 06748 #define CAN_FA1R_FACT11_Msk (0x1U << CAN_FA1R_FACT11_Pos) /*!< 0x00000800 */ 06749 #define CAN_FA1R_FACT11 CAN_FA1R_FACT11_Msk /*!< Filter 11 Active */ 06750 #define CAN_FA1R_FACT12_Pos (12U) 06751 #define CAN_FA1R_FACT12_Msk (0x1U << CAN_FA1R_FACT12_Pos) /*!< 0x00001000 */ 06752 #define CAN_FA1R_FACT12 CAN_FA1R_FACT12_Msk /*!< Filter 12 Active */ 06753 #define CAN_FA1R_FACT13_Pos (13U) 06754 #define CAN_FA1R_FACT13_Msk (0x1U << CAN_FA1R_FACT13_Pos) /*!< 0x00002000 */ 06755 #define CAN_FA1R_FACT13 CAN_FA1R_FACT13_Msk /*!< Filter 13 Active */ 06756 06757 /******************* Bit definition for CAN_F0R1 register *******************/ 06758 #define CAN_F0R1_FB0_Pos (0U) 06759 #define CAN_F0R1_FB0_Msk (0x1U << CAN_F0R1_FB0_Pos) /*!< 0x00000001 */ 06760 #define CAN_F0R1_FB0 CAN_F0R1_FB0_Msk /*!< Filter bit 0 */ 06761 #define CAN_F0R1_FB1_Pos (1U) 06762 #define CAN_F0R1_FB1_Msk (0x1U << CAN_F0R1_FB1_Pos) /*!< 0x00000002 */ 06763 #define CAN_F0R1_FB1 CAN_F0R1_FB1_Msk /*!< Filter bit 1 */ 06764 #define CAN_F0R1_FB2_Pos (2U) 06765 #define CAN_F0R1_FB2_Msk (0x1U << CAN_F0R1_FB2_Pos) /*!< 0x00000004 */ 06766 #define CAN_F0R1_FB2 CAN_F0R1_FB2_Msk /*!< Filter bit 2 */ 06767 #define CAN_F0R1_FB3_Pos (3U) 06768 #define CAN_F0R1_FB3_Msk (0x1U << CAN_F0R1_FB3_Pos) /*!< 0x00000008 */ 06769 #define CAN_F0R1_FB3 CAN_F0R1_FB3_Msk /*!< Filter bit 3 */ 06770 #define CAN_F0R1_FB4_Pos (4U) 06771 #define CAN_F0R1_FB4_Msk (0x1U << CAN_F0R1_FB4_Pos) /*!< 0x00000010 */ 06772 #define CAN_F0R1_FB4 CAN_F0R1_FB4_Msk /*!< Filter bit 4 */ 06773 #define CAN_F0R1_FB5_Pos (5U) 06774 #define CAN_F0R1_FB5_Msk (0x1U << CAN_F0R1_FB5_Pos) /*!< 0x00000020 */ 06775 #define CAN_F0R1_FB5 CAN_F0R1_FB5_Msk /*!< Filter bit 5 */ 06776 #define CAN_F0R1_FB6_Pos (6U) 06777 #define CAN_F0R1_FB6_Msk (0x1U << CAN_F0R1_FB6_Pos) /*!< 0x00000040 */ 06778 #define CAN_F0R1_FB6 CAN_F0R1_FB6_Msk /*!< Filter bit 6 */ 06779 #define CAN_F0R1_FB7_Pos (7U) 06780 #define CAN_F0R1_FB7_Msk (0x1U << CAN_F0R1_FB7_Pos) /*!< 0x00000080 */ 06781 #define CAN_F0R1_FB7 CAN_F0R1_FB7_Msk /*!< Filter bit 7 */ 06782 #define CAN_F0R1_FB8_Pos (8U) 06783 #define CAN_F0R1_FB8_Msk (0x1U << CAN_F0R1_FB8_Pos) /*!< 0x00000100 */ 06784 #define CAN_F0R1_FB8 CAN_F0R1_FB8_Msk /*!< Filter bit 8 */ 06785 #define CAN_F0R1_FB9_Pos (9U) 06786 #define CAN_F0R1_FB9_Msk (0x1U << CAN_F0R1_FB9_Pos) /*!< 0x00000200 */ 06787 #define CAN_F0R1_FB9 CAN_F0R1_FB9_Msk /*!< Filter bit 9 */ 06788 #define CAN_F0R1_FB10_Pos (10U) 06789 #define CAN_F0R1_FB10_Msk (0x1U << CAN_F0R1_FB10_Pos) /*!< 0x00000400 */ 06790 #define CAN_F0R1_FB10 CAN_F0R1_FB10_Msk /*!< Filter bit 10 */ 06791 #define CAN_F0R1_FB11_Pos (11U) 06792 #define CAN_F0R1_FB11_Msk (0x1U << CAN_F0R1_FB11_Pos) /*!< 0x00000800 */ 06793 #define CAN_F0R1_FB11 CAN_F0R1_FB11_Msk /*!< Filter bit 11 */ 06794 #define CAN_F0R1_FB12_Pos (12U) 06795 #define CAN_F0R1_FB12_Msk (0x1U << CAN_F0R1_FB12_Pos) /*!< 0x00001000 */ 06796 #define CAN_F0R1_FB12 CAN_F0R1_FB12_Msk /*!< Filter bit 12 */ 06797 #define CAN_F0R1_FB13_Pos (13U) 06798 #define CAN_F0R1_FB13_Msk (0x1U << CAN_F0R1_FB13_Pos) /*!< 0x00002000 */ 06799 #define CAN_F0R1_FB13 CAN_F0R1_FB13_Msk /*!< Filter bit 13 */ 06800 #define CAN_F0R1_FB14_Pos (14U) 06801 #define CAN_F0R1_FB14_Msk (0x1U << CAN_F0R1_FB14_Pos) /*!< 0x00004000 */ 06802 #define CAN_F0R1_FB14 CAN_F0R1_FB14_Msk /*!< Filter bit 14 */ 06803 #define CAN_F0R1_FB15_Pos (15U) 06804 #define CAN_F0R1_FB15_Msk (0x1U << CAN_F0R1_FB15_Pos) /*!< 0x00008000 */ 06805 #define CAN_F0R1_FB15 CAN_F0R1_FB15_Msk /*!< Filter bit 15 */ 06806 #define CAN_F0R1_FB16_Pos (16U) 06807 #define CAN_F0R1_FB16_Msk (0x1U << CAN_F0R1_FB16_Pos) /*!< 0x00010000 */ 06808 #define CAN_F0R1_FB16 CAN_F0R1_FB16_Msk /*!< Filter bit 16 */ 06809 #define CAN_F0R1_FB17_Pos (17U) 06810 #define CAN_F0R1_FB17_Msk (0x1U << CAN_F0R1_FB17_Pos) /*!< 0x00020000 */ 06811 #define CAN_F0R1_FB17 CAN_F0R1_FB17_Msk /*!< Filter bit 17 */ 06812 #define CAN_F0R1_FB18_Pos (18U) 06813 #define CAN_F0R1_FB18_Msk (0x1U << CAN_F0R1_FB18_Pos) /*!< 0x00040000 */ 06814 #define CAN_F0R1_FB18 CAN_F0R1_FB18_Msk /*!< Filter bit 18 */ 06815 #define CAN_F0R1_FB19_Pos (19U) 06816 #define CAN_F0R1_FB19_Msk (0x1U << CAN_F0R1_FB19_Pos) /*!< 0x00080000 */ 06817 #define CAN_F0R1_FB19 CAN_F0R1_FB19_Msk /*!< Filter bit 19 */ 06818 #define CAN_F0R1_FB20_Pos (20U) 06819 #define CAN_F0R1_FB20_Msk (0x1U << CAN_F0R1_FB20_Pos) /*!< 0x00100000 */ 06820 #define CAN_F0R1_FB20 CAN_F0R1_FB20_Msk /*!< Filter bit 20 */ 06821 #define CAN_F0R1_FB21_Pos (21U) 06822 #define CAN_F0R1_FB21_Msk (0x1U << CAN_F0R1_FB21_Pos) /*!< 0x00200000 */ 06823 #define CAN_F0R1_FB21 CAN_F0R1_FB21_Msk /*!< Filter bit 21 */ 06824 #define CAN_F0R1_FB22_Pos (22U) 06825 #define CAN_F0R1_FB22_Msk (0x1U << CAN_F0R1_FB22_Pos) /*!< 0x00400000 */ 06826 #define CAN_F0R1_FB22 CAN_F0R1_FB22_Msk /*!< Filter bit 22 */ 06827 #define CAN_F0R1_FB23_Pos (23U) 06828 #define CAN_F0R1_FB23_Msk (0x1U << CAN_F0R1_FB23_Pos) /*!< 0x00800000 */ 06829 #define CAN_F0R1_FB23 CAN_F0R1_FB23_Msk /*!< Filter bit 23 */ 06830 #define CAN_F0R1_FB24_Pos (24U) 06831 #define CAN_F0R1_FB24_Msk (0x1U << CAN_F0R1_FB24_Pos) /*!< 0x01000000 */ 06832 #define CAN_F0R1_FB24 CAN_F0R1_FB24_Msk /*!< Filter bit 24 */ 06833 #define CAN_F0R1_FB25_Pos (25U) 06834 #define CAN_F0R1_FB25_Msk (0x1U << CAN_F0R1_FB25_Pos) /*!< 0x02000000 */ 06835 #define CAN_F0R1_FB25 CAN_F0R1_FB25_Msk /*!< Filter bit 25 */ 06836 #define CAN_F0R1_FB26_Pos (26U) 06837 #define CAN_F0R1_FB26_Msk (0x1U << CAN_F0R1_FB26_Pos) /*!< 0x04000000 */ 06838 #define CAN_F0R1_FB26 CAN_F0R1_FB26_Msk /*!< Filter bit 26 */ 06839 #define CAN_F0R1_FB27_Pos (27U) 06840 #define CAN_F0R1_FB27_Msk (0x1U << CAN_F0R1_FB27_Pos) /*!< 0x08000000 */ 06841 #define CAN_F0R1_FB27 CAN_F0R1_FB27_Msk /*!< Filter bit 27 */ 06842 #define CAN_F0R1_FB28_Pos (28U) 06843 #define CAN_F0R1_FB28_Msk (0x1U << CAN_F0R1_FB28_Pos) /*!< 0x10000000 */ 06844 #define CAN_F0R1_FB28 CAN_F0R1_FB28_Msk /*!< Filter bit 28 */ 06845 #define CAN_F0R1_FB29_Pos (29U) 06846 #define CAN_F0R1_FB29_Msk (0x1U << CAN_F0R1_FB29_Pos) /*!< 0x20000000 */ 06847 #define CAN_F0R1_FB29 CAN_F0R1_FB29_Msk /*!< Filter bit 29 */ 06848 #define CAN_F0R1_FB30_Pos (30U) 06849 #define CAN_F0R1_FB30_Msk (0x1U << CAN_F0R1_FB30_Pos) /*!< 0x40000000 */ 06850 #define CAN_F0R1_FB30 CAN_F0R1_FB30_Msk /*!< Filter bit 30 */ 06851 #define CAN_F0R1_FB31_Pos (31U) 06852 #define CAN_F0R1_FB31_Msk (0x1U << CAN_F0R1_FB31_Pos) /*!< 0x80000000 */ 06853 #define CAN_F0R1_FB31 CAN_F0R1_FB31_Msk /*!< Filter bit 31 */ 06854 06855 /******************* Bit definition for CAN_F1R1 register *******************/ 06856 #define CAN_F1R1_FB0_Pos (0U) 06857 #define CAN_F1R1_FB0_Msk (0x1U << CAN_F1R1_FB0_Pos) /*!< 0x00000001 */ 06858 #define CAN_F1R1_FB0 CAN_F1R1_FB0_Msk /*!< Filter bit 0 */ 06859 #define CAN_F1R1_FB1_Pos (1U) 06860 #define CAN_F1R1_FB1_Msk (0x1U << CAN_F1R1_FB1_Pos) /*!< 0x00000002 */ 06861 #define CAN_F1R1_FB1 CAN_F1R1_FB1_Msk /*!< Filter bit 1 */ 06862 #define CAN_F1R1_FB2_Pos (2U) 06863 #define CAN_F1R1_FB2_Msk (0x1U << CAN_F1R1_FB2_Pos) /*!< 0x00000004 */ 06864 #define CAN_F1R1_FB2 CAN_F1R1_FB2_Msk /*!< Filter bit 2 */ 06865 #define CAN_F1R1_FB3_Pos (3U) 06866 #define CAN_F1R1_FB3_Msk (0x1U << CAN_F1R1_FB3_Pos) /*!< 0x00000008 */ 06867 #define CAN_F1R1_FB3 CAN_F1R1_FB3_Msk /*!< Filter bit 3 */ 06868 #define CAN_F1R1_FB4_Pos (4U) 06869 #define CAN_F1R1_FB4_Msk (0x1U << CAN_F1R1_FB4_Pos) /*!< 0x00000010 */ 06870 #define CAN_F1R1_FB4 CAN_F1R1_FB4_Msk /*!< Filter bit 4 */ 06871 #define CAN_F1R1_FB5_Pos (5U) 06872 #define CAN_F1R1_FB5_Msk (0x1U << CAN_F1R1_FB5_Pos) /*!< 0x00000020 */ 06873 #define CAN_F1R1_FB5 CAN_F1R1_FB5_Msk /*!< Filter bit 5 */ 06874 #define CAN_F1R1_FB6_Pos (6U) 06875 #define CAN_F1R1_FB6_Msk (0x1U << CAN_F1R1_FB6_Pos) /*!< 0x00000040 */ 06876 #define CAN_F1R1_FB6 CAN_F1R1_FB6_Msk /*!< Filter bit 6 */ 06877 #define CAN_F1R1_FB7_Pos (7U) 06878 #define CAN_F1R1_FB7_Msk (0x1U << CAN_F1R1_FB7_Pos) /*!< 0x00000080 */ 06879 #define CAN_F1R1_FB7 CAN_F1R1_FB7_Msk /*!< Filter bit 7 */ 06880 #define CAN_F1R1_FB8_Pos (8U) 06881 #define CAN_F1R1_FB8_Msk (0x1U << CAN_F1R1_FB8_Pos) /*!< 0x00000100 */ 06882 #define CAN_F1R1_FB8 CAN_F1R1_FB8_Msk /*!< Filter bit 8 */ 06883 #define CAN_F1R1_FB9_Pos (9U) 06884 #define CAN_F1R1_FB9_Msk (0x1U << CAN_F1R1_FB9_Pos) /*!< 0x00000200 */ 06885 #define CAN_F1R1_FB9 CAN_F1R1_FB9_Msk /*!< Filter bit 9 */ 06886 #define CAN_F1R1_FB10_Pos (10U) 06887 #define CAN_F1R1_FB10_Msk (0x1U << CAN_F1R1_FB10_Pos) /*!< 0x00000400 */ 06888 #define CAN_F1R1_FB10 CAN_F1R1_FB10_Msk /*!< Filter bit 10 */ 06889 #define CAN_F1R1_FB11_Pos (11U) 06890 #define CAN_F1R1_FB11_Msk (0x1U << CAN_F1R1_FB11_Pos) /*!< 0x00000800 */ 06891 #define CAN_F1R1_FB11 CAN_F1R1_FB11_Msk /*!< Filter bit 11 */ 06892 #define CAN_F1R1_FB12_Pos (12U) 06893 #define CAN_F1R1_FB12_Msk (0x1U << CAN_F1R1_FB12_Pos) /*!< 0x00001000 */ 06894 #define CAN_F1R1_FB12 CAN_F1R1_FB12_Msk /*!< Filter bit 12 */ 06895 #define CAN_F1R1_FB13_Pos (13U) 06896 #define CAN_F1R1_FB13_Msk (0x1U << CAN_F1R1_FB13_Pos) /*!< 0x00002000 */ 06897 #define CAN_F1R1_FB13 CAN_F1R1_FB13_Msk /*!< Filter bit 13 */ 06898 #define CAN_F1R1_FB14_Pos (14U) 06899 #define CAN_F1R1_FB14_Msk (0x1U << CAN_F1R1_FB14_Pos) /*!< 0x00004000 */ 06900 #define CAN_F1R1_FB14 CAN_F1R1_FB14_Msk /*!< Filter bit 14 */ 06901 #define CAN_F1R1_FB15_Pos (15U) 06902 #define CAN_F1R1_FB15_Msk (0x1U << CAN_F1R1_FB15_Pos) /*!< 0x00008000 */ 06903 #define CAN_F1R1_FB15 CAN_F1R1_FB15_Msk /*!< Filter bit 15 */ 06904 #define CAN_F1R1_FB16_Pos (16U) 06905 #define CAN_F1R1_FB16_Msk (0x1U << CAN_F1R1_FB16_Pos) /*!< 0x00010000 */ 06906 #define CAN_F1R1_FB16 CAN_F1R1_FB16_Msk /*!< Filter bit 16 */ 06907 #define CAN_F1R1_FB17_Pos (17U) 06908 #define CAN_F1R1_FB17_Msk (0x1U << CAN_F1R1_FB17_Pos) /*!< 0x00020000 */ 06909 #define CAN_F1R1_FB17 CAN_F1R1_FB17_Msk /*!< Filter bit 17 */ 06910 #define CAN_F1R1_FB18_Pos (18U) 06911 #define CAN_F1R1_FB18_Msk (0x1U << CAN_F1R1_FB18_Pos) /*!< 0x00040000 */ 06912 #define CAN_F1R1_FB18 CAN_F1R1_FB18_Msk /*!< Filter bit 18 */ 06913 #define CAN_F1R1_FB19_Pos (19U) 06914 #define CAN_F1R1_FB19_Msk (0x1U << CAN_F1R1_FB19_Pos) /*!< 0x00080000 */ 06915 #define CAN_F1R1_FB19 CAN_F1R1_FB19_Msk /*!< Filter bit 19 */ 06916 #define CAN_F1R1_FB20_Pos (20U) 06917 #define CAN_F1R1_FB20_Msk (0x1U << CAN_F1R1_FB20_Pos) /*!< 0x00100000 */ 06918 #define CAN_F1R1_FB20 CAN_F1R1_FB20_Msk /*!< Filter bit 20 */ 06919 #define CAN_F1R1_FB21_Pos (21U) 06920 #define CAN_F1R1_FB21_Msk (0x1U << CAN_F1R1_FB21_Pos) /*!< 0x00200000 */ 06921 #define CAN_F1R1_FB21 CAN_F1R1_FB21_Msk /*!< Filter bit 21 */ 06922 #define CAN_F1R1_FB22_Pos (22U) 06923 #define CAN_F1R1_FB22_Msk (0x1U << CAN_F1R1_FB22_Pos) /*!< 0x00400000 */ 06924 #define CAN_F1R1_FB22 CAN_F1R1_FB22_Msk /*!< Filter bit 22 */ 06925 #define CAN_F1R1_FB23_Pos (23U) 06926 #define CAN_F1R1_FB23_Msk (0x1U << CAN_F1R1_FB23_Pos) /*!< 0x00800000 */ 06927 #define CAN_F1R1_FB23 CAN_F1R1_FB23_Msk /*!< Filter bit 23 */ 06928 #define CAN_F1R1_FB24_Pos (24U) 06929 #define CAN_F1R1_FB24_Msk (0x1U << CAN_F1R1_FB24_Pos) /*!< 0x01000000 */ 06930 #define CAN_F1R1_FB24 CAN_F1R1_FB24_Msk /*!< Filter bit 24 */ 06931 #define CAN_F1R1_FB25_Pos (25U) 06932 #define CAN_F1R1_FB25_Msk (0x1U << CAN_F1R1_FB25_Pos) /*!< 0x02000000 */ 06933 #define CAN_F1R1_FB25 CAN_F1R1_FB25_Msk /*!< Filter bit 25 */ 06934 #define CAN_F1R1_FB26_Pos (26U) 06935 #define CAN_F1R1_FB26_Msk (0x1U << CAN_F1R1_FB26_Pos) /*!< 0x04000000 */ 06936 #define CAN_F1R1_FB26 CAN_F1R1_FB26_Msk /*!< Filter bit 26 */ 06937 #define CAN_F1R1_FB27_Pos (27U) 06938 #define CAN_F1R1_FB27_Msk (0x1U << CAN_F1R1_FB27_Pos) /*!< 0x08000000 */ 06939 #define CAN_F1R1_FB27 CAN_F1R1_FB27_Msk /*!< Filter bit 27 */ 06940 #define CAN_F1R1_FB28_Pos (28U) 06941 #define CAN_F1R1_FB28_Msk (0x1U << CAN_F1R1_FB28_Pos) /*!< 0x10000000 */ 06942 #define CAN_F1R1_FB28 CAN_F1R1_FB28_Msk /*!< Filter bit 28 */ 06943 #define CAN_F1R1_FB29_Pos (29U) 06944 #define CAN_F1R1_FB29_Msk (0x1U << CAN_F1R1_FB29_Pos) /*!< 0x20000000 */ 06945 #define CAN_F1R1_FB29 CAN_F1R1_FB29_Msk /*!< Filter bit 29 */ 06946 #define CAN_F1R1_FB30_Pos (30U) 06947 #define CAN_F1R1_FB30_Msk (0x1U << CAN_F1R1_FB30_Pos) /*!< 0x40000000 */ 06948 #define CAN_F1R1_FB30 CAN_F1R1_FB30_Msk /*!< Filter bit 30 */ 06949 #define CAN_F1R1_FB31_Pos (31U) 06950 #define CAN_F1R1_FB31_Msk (0x1U << CAN_F1R1_FB31_Pos) /*!< 0x80000000 */ 06951 #define CAN_F1R1_FB31 CAN_F1R1_FB31_Msk /*!< Filter bit 31 */ 06952 06953 /******************* Bit definition for CAN_F2R1 register *******************/ 06954 #define CAN_F2R1_FB0_Pos (0U) 06955 #define CAN_F2R1_FB0_Msk (0x1U << CAN_F2R1_FB0_Pos) /*!< 0x00000001 */ 06956 #define CAN_F2R1_FB0 CAN_F2R1_FB0_Msk /*!< Filter bit 0 */ 06957 #define CAN_F2R1_FB1_Pos (1U) 06958 #define CAN_F2R1_FB1_Msk (0x1U << CAN_F2R1_FB1_Pos) /*!< 0x00000002 */ 06959 #define CAN_F2R1_FB1 CAN_F2R1_FB1_Msk /*!< Filter bit 1 */ 06960 #define CAN_F2R1_FB2_Pos (2U) 06961 #define CAN_F2R1_FB2_Msk (0x1U << CAN_F2R1_FB2_Pos) /*!< 0x00000004 */ 06962 #define CAN_F2R1_FB2 CAN_F2R1_FB2_Msk /*!< Filter bit 2 */ 06963 #define CAN_F2R1_FB3_Pos (3U) 06964 #define CAN_F2R1_FB3_Msk (0x1U << CAN_F2R1_FB3_Pos) /*!< 0x00000008 */ 06965 #define CAN_F2R1_FB3 CAN_F2R1_FB3_Msk /*!< Filter bit 3 */ 06966 #define CAN_F2R1_FB4_Pos (4U) 06967 #define CAN_F2R1_FB4_Msk (0x1U << CAN_F2R1_FB4_Pos) /*!< 0x00000010 */ 06968 #define CAN_F2R1_FB4 CAN_F2R1_FB4_Msk /*!< Filter bit 4 */ 06969 #define CAN_F2R1_FB5_Pos (5U) 06970 #define CAN_F2R1_FB5_Msk (0x1U << CAN_F2R1_FB5_Pos) /*!< 0x00000020 */ 06971 #define CAN_F2R1_FB5 CAN_F2R1_FB5_Msk /*!< Filter bit 5 */ 06972 #define CAN_F2R1_FB6_Pos (6U) 06973 #define CAN_F2R1_FB6_Msk (0x1U << CAN_F2R1_FB6_Pos) /*!< 0x00000040 */ 06974 #define CAN_F2R1_FB6 CAN_F2R1_FB6_Msk /*!< Filter bit 6 */ 06975 #define CAN_F2R1_FB7_Pos (7U) 06976 #define CAN_F2R1_FB7_Msk (0x1U << CAN_F2R1_FB7_Pos) /*!< 0x00000080 */ 06977 #define CAN_F2R1_FB7 CAN_F2R1_FB7_Msk /*!< Filter bit 7 */ 06978 #define CAN_F2R1_FB8_Pos (8U) 06979 #define CAN_F2R1_FB8_Msk (0x1U << CAN_F2R1_FB8_Pos) /*!< 0x00000100 */ 06980 #define CAN_F2R1_FB8 CAN_F2R1_FB8_Msk /*!< Filter bit 8 */ 06981 #define CAN_F2R1_FB9_Pos (9U) 06982 #define CAN_F2R1_FB9_Msk (0x1U << CAN_F2R1_FB9_Pos) /*!< 0x00000200 */ 06983 #define CAN_F2R1_FB9 CAN_F2R1_FB9_Msk /*!< Filter bit 9 */ 06984 #define CAN_F2R1_FB10_Pos (10U) 06985 #define CAN_F2R1_FB10_Msk (0x1U << CAN_F2R1_FB10_Pos) /*!< 0x00000400 */ 06986 #define CAN_F2R1_FB10 CAN_F2R1_FB10_Msk /*!< Filter bit 10 */ 06987 #define CAN_F2R1_FB11_Pos (11U) 06988 #define CAN_F2R1_FB11_Msk (0x1U << CAN_F2R1_FB11_Pos) /*!< 0x00000800 */ 06989 #define CAN_F2R1_FB11 CAN_F2R1_FB11_Msk /*!< Filter bit 11 */ 06990 #define CAN_F2R1_FB12_Pos (12U) 06991 #define CAN_F2R1_FB12_Msk (0x1U << CAN_F2R1_FB12_Pos) /*!< 0x00001000 */ 06992 #define CAN_F2R1_FB12 CAN_F2R1_FB12_Msk /*!< Filter bit 12 */ 06993 #define CAN_F2R1_FB13_Pos (13U) 06994 #define CAN_F2R1_FB13_Msk (0x1U << CAN_F2R1_FB13_Pos) /*!< 0x00002000 */ 06995 #define CAN_F2R1_FB13 CAN_F2R1_FB13_Msk /*!< Filter bit 13 */ 06996 #define CAN_F2R1_FB14_Pos (14U) 06997 #define CAN_F2R1_FB14_Msk (0x1U << CAN_F2R1_FB14_Pos) /*!< 0x00004000 */ 06998 #define CAN_F2R1_FB14 CAN_F2R1_FB14_Msk /*!< Filter bit 14 */ 06999 #define CAN_F2R1_FB15_Pos (15U) 07000 #define CAN_F2R1_FB15_Msk (0x1U << CAN_F2R1_FB15_Pos) /*!< 0x00008000 */ 07001 #define CAN_F2R1_FB15 CAN_F2R1_FB15_Msk /*!< Filter bit 15 */ 07002 #define CAN_F2R1_FB16_Pos (16U) 07003 #define CAN_F2R1_FB16_Msk (0x1U << CAN_F2R1_FB16_Pos) /*!< 0x00010000 */ 07004 #define CAN_F2R1_FB16 CAN_F2R1_FB16_Msk /*!< Filter bit 16 */ 07005 #define CAN_F2R1_FB17_Pos (17U) 07006 #define CAN_F2R1_FB17_Msk (0x1U << CAN_F2R1_FB17_Pos) /*!< 0x00020000 */ 07007 #define CAN_F2R1_FB17 CAN_F2R1_FB17_Msk /*!< Filter bit 17 */ 07008 #define CAN_F2R1_FB18_Pos (18U) 07009 #define CAN_F2R1_FB18_Msk (0x1U << CAN_F2R1_FB18_Pos) /*!< 0x00040000 */ 07010 #define CAN_F2R1_FB18 CAN_F2R1_FB18_Msk /*!< Filter bit 18 */ 07011 #define CAN_F2R1_FB19_Pos (19U) 07012 #define CAN_F2R1_FB19_Msk (0x1U << CAN_F2R1_FB19_Pos) /*!< 0x00080000 */ 07013 #define CAN_F2R1_FB19 CAN_F2R1_FB19_Msk /*!< Filter bit 19 */ 07014 #define CAN_F2R1_FB20_Pos (20U) 07015 #define CAN_F2R1_FB20_Msk (0x1U << CAN_F2R1_FB20_Pos) /*!< 0x00100000 */ 07016 #define CAN_F2R1_FB20 CAN_F2R1_FB20_Msk /*!< Filter bit 20 */ 07017 #define CAN_F2R1_FB21_Pos (21U) 07018 #define CAN_F2R1_FB21_Msk (0x1U << CAN_F2R1_FB21_Pos) /*!< 0x00200000 */ 07019 #define CAN_F2R1_FB21 CAN_F2R1_FB21_Msk /*!< Filter bit 21 */ 07020 #define CAN_F2R1_FB22_Pos (22U) 07021 #define CAN_F2R1_FB22_Msk (0x1U << CAN_F2R1_FB22_Pos) /*!< 0x00400000 */ 07022 #define CAN_F2R1_FB22 CAN_F2R1_FB22_Msk /*!< Filter bit 22 */ 07023 #define CAN_F2R1_FB23_Pos (23U) 07024 #define CAN_F2R1_FB23_Msk (0x1U << CAN_F2R1_FB23_Pos) /*!< 0x00800000 */ 07025 #define CAN_F2R1_FB23 CAN_F2R1_FB23_Msk /*!< Filter bit 23 */ 07026 #define CAN_F2R1_FB24_Pos (24U) 07027 #define CAN_F2R1_FB24_Msk (0x1U << CAN_F2R1_FB24_Pos) /*!< 0x01000000 */ 07028 #define CAN_F2R1_FB24 CAN_F2R1_FB24_Msk /*!< Filter bit 24 */ 07029 #define CAN_F2R1_FB25_Pos (25U) 07030 #define CAN_F2R1_FB25_Msk (0x1U << CAN_F2R1_FB25_Pos) /*!< 0x02000000 */ 07031 #define CAN_F2R1_FB25 CAN_F2R1_FB25_Msk /*!< Filter bit 25 */ 07032 #define CAN_F2R1_FB26_Pos (26U) 07033 #define CAN_F2R1_FB26_Msk (0x1U << CAN_F2R1_FB26_Pos) /*!< 0x04000000 */ 07034 #define CAN_F2R1_FB26 CAN_F2R1_FB26_Msk /*!< Filter bit 26 */ 07035 #define CAN_F2R1_FB27_Pos (27U) 07036 #define CAN_F2R1_FB27_Msk (0x1U << CAN_F2R1_FB27_Pos) /*!< 0x08000000 */ 07037 #define CAN_F2R1_FB27 CAN_F2R1_FB27_Msk /*!< Filter bit 27 */ 07038 #define CAN_F2R1_FB28_Pos (28U) 07039 #define CAN_F2R1_FB28_Msk (0x1U << CAN_F2R1_FB28_Pos) /*!< 0x10000000 */ 07040 #define CAN_F2R1_FB28 CAN_F2R1_FB28_Msk /*!< Filter bit 28 */ 07041 #define CAN_F2R1_FB29_Pos (29U) 07042 #define CAN_F2R1_FB29_Msk (0x1U << CAN_F2R1_FB29_Pos) /*!< 0x20000000 */ 07043 #define CAN_F2R1_FB29 CAN_F2R1_FB29_Msk /*!< Filter bit 29 */ 07044 #define CAN_F2R1_FB30_Pos (30U) 07045 #define CAN_F2R1_FB30_Msk (0x1U << CAN_F2R1_FB30_Pos) /*!< 0x40000000 */ 07046 #define CAN_F2R1_FB30 CAN_F2R1_FB30_Msk /*!< Filter bit 30 */ 07047 #define CAN_F2R1_FB31_Pos (31U) 07048 #define CAN_F2R1_FB31_Msk (0x1U << CAN_F2R1_FB31_Pos) /*!< 0x80000000 */ 07049 #define CAN_F2R1_FB31 CAN_F2R1_FB31_Msk /*!< Filter bit 31 */ 07050 07051 /******************* Bit definition for CAN_F3R1 register *******************/ 07052 #define CAN_F3R1_FB0_Pos (0U) 07053 #define CAN_F3R1_FB0_Msk (0x1U << CAN_F3R1_FB0_Pos) /*!< 0x00000001 */ 07054 #define CAN_F3R1_FB0 CAN_F3R1_FB0_Msk /*!< Filter bit 0 */ 07055 #define CAN_F3R1_FB1_Pos (1U) 07056 #define CAN_F3R1_FB1_Msk (0x1U << CAN_F3R1_FB1_Pos) /*!< 0x00000002 */ 07057 #define CAN_F3R1_FB1 CAN_F3R1_FB1_Msk /*!< Filter bit 1 */ 07058 #define CAN_F3R1_FB2_Pos (2U) 07059 #define CAN_F3R1_FB2_Msk (0x1U << CAN_F3R1_FB2_Pos) /*!< 0x00000004 */ 07060 #define CAN_F3R1_FB2 CAN_F3R1_FB2_Msk /*!< Filter bit 2 */ 07061 #define CAN_F3R1_FB3_Pos (3U) 07062 #define CAN_F3R1_FB3_Msk (0x1U << CAN_F3R1_FB3_Pos) /*!< 0x00000008 */ 07063 #define CAN_F3R1_FB3 CAN_F3R1_FB3_Msk /*!< Filter bit 3 */ 07064 #define CAN_F3R1_FB4_Pos (4U) 07065 #define CAN_F3R1_FB4_Msk (0x1U << CAN_F3R1_FB4_Pos) /*!< 0x00000010 */ 07066 #define CAN_F3R1_FB4 CAN_F3R1_FB4_Msk /*!< Filter bit 4 */ 07067 #define CAN_F3R1_FB5_Pos (5U) 07068 #define CAN_F3R1_FB5_Msk (0x1U << CAN_F3R1_FB5_Pos) /*!< 0x00000020 */ 07069 #define CAN_F3R1_FB5 CAN_F3R1_FB5_Msk /*!< Filter bit 5 */ 07070 #define CAN_F3R1_FB6_Pos (6U) 07071 #define CAN_F3R1_FB6_Msk (0x1U << CAN_F3R1_FB6_Pos) /*!< 0x00000040 */ 07072 #define CAN_F3R1_FB6 CAN_F3R1_FB6_Msk /*!< Filter bit 6 */ 07073 #define CAN_F3R1_FB7_Pos (7U) 07074 #define CAN_F3R1_FB7_Msk (0x1U << CAN_F3R1_FB7_Pos) /*!< 0x00000080 */ 07075 #define CAN_F3R1_FB7 CAN_F3R1_FB7_Msk /*!< Filter bit 7 */ 07076 #define CAN_F3R1_FB8_Pos (8U) 07077 #define CAN_F3R1_FB8_Msk (0x1U << CAN_F3R1_FB8_Pos) /*!< 0x00000100 */ 07078 #define CAN_F3R1_FB8 CAN_F3R1_FB8_Msk /*!< Filter bit 8 */ 07079 #define CAN_F3R1_FB9_Pos (9U) 07080 #define CAN_F3R1_FB9_Msk (0x1U << CAN_F3R1_FB9_Pos) /*!< 0x00000200 */ 07081 #define CAN_F3R1_FB9 CAN_F3R1_FB9_Msk /*!< Filter bit 9 */ 07082 #define CAN_F3R1_FB10_Pos (10U) 07083 #define CAN_F3R1_FB10_Msk (0x1U << CAN_F3R1_FB10_Pos) /*!< 0x00000400 */ 07084 #define CAN_F3R1_FB10 CAN_F3R1_FB10_Msk /*!< Filter bit 10 */ 07085 #define CAN_F3R1_FB11_Pos (11U) 07086 #define CAN_F3R1_FB11_Msk (0x1U << CAN_F3R1_FB11_Pos) /*!< 0x00000800 */ 07087 #define CAN_F3R1_FB11 CAN_F3R1_FB11_Msk /*!< Filter bit 11 */ 07088 #define CAN_F3R1_FB12_Pos (12U) 07089 #define CAN_F3R1_FB12_Msk (0x1U << CAN_F3R1_FB12_Pos) /*!< 0x00001000 */ 07090 #define CAN_F3R1_FB12 CAN_F3R1_FB12_Msk /*!< Filter bit 12 */ 07091 #define CAN_F3R1_FB13_Pos (13U) 07092 #define CAN_F3R1_FB13_Msk (0x1U << CAN_F3R1_FB13_Pos) /*!< 0x00002000 */ 07093 #define CAN_F3R1_FB13 CAN_F3R1_FB13_Msk /*!< Filter bit 13 */ 07094 #define CAN_F3R1_FB14_Pos (14U) 07095 #define CAN_F3R1_FB14_Msk (0x1U << CAN_F3R1_FB14_Pos) /*!< 0x00004000 */ 07096 #define CAN_F3R1_FB14 CAN_F3R1_FB14_Msk /*!< Filter bit 14 */ 07097 #define CAN_F3R1_FB15_Pos (15U) 07098 #define CAN_F3R1_FB15_Msk (0x1U << CAN_F3R1_FB15_Pos) /*!< 0x00008000 */ 07099 #define CAN_F3R1_FB15 CAN_F3R1_FB15_Msk /*!< Filter bit 15 */ 07100 #define CAN_F3R1_FB16_Pos (16U) 07101 #define CAN_F3R1_FB16_Msk (0x1U << CAN_F3R1_FB16_Pos) /*!< 0x00010000 */ 07102 #define CAN_F3R1_FB16 CAN_F3R1_FB16_Msk /*!< Filter bit 16 */ 07103 #define CAN_F3R1_FB17_Pos (17U) 07104 #define CAN_F3R1_FB17_Msk (0x1U << CAN_F3R1_FB17_Pos) /*!< 0x00020000 */ 07105 #define CAN_F3R1_FB17 CAN_F3R1_FB17_Msk /*!< Filter bit 17 */ 07106 #define CAN_F3R1_FB18_Pos (18U) 07107 #define CAN_F3R1_FB18_Msk (0x1U << CAN_F3R1_FB18_Pos) /*!< 0x00040000 */ 07108 #define CAN_F3R1_FB18 CAN_F3R1_FB18_Msk /*!< Filter bit 18 */ 07109 #define CAN_F3R1_FB19_Pos (19U) 07110 #define CAN_F3R1_FB19_Msk (0x1U << CAN_F3R1_FB19_Pos) /*!< 0x00080000 */ 07111 #define CAN_F3R1_FB19 CAN_F3R1_FB19_Msk /*!< Filter bit 19 */ 07112 #define CAN_F3R1_FB20_Pos (20U) 07113 #define CAN_F3R1_FB20_Msk (0x1U << CAN_F3R1_FB20_Pos) /*!< 0x00100000 */ 07114 #define CAN_F3R1_FB20 CAN_F3R1_FB20_Msk /*!< Filter bit 20 */ 07115 #define CAN_F3R1_FB21_Pos (21U) 07116 #define CAN_F3R1_FB21_Msk (0x1U << CAN_F3R1_FB21_Pos) /*!< 0x00200000 */ 07117 #define CAN_F3R1_FB21 CAN_F3R1_FB21_Msk /*!< Filter bit 21 */ 07118 #define CAN_F3R1_FB22_Pos (22U) 07119 #define CAN_F3R1_FB22_Msk (0x1U << CAN_F3R1_FB22_Pos) /*!< 0x00400000 */ 07120 #define CAN_F3R1_FB22 CAN_F3R1_FB22_Msk /*!< Filter bit 22 */ 07121 #define CAN_F3R1_FB23_Pos (23U) 07122 #define CAN_F3R1_FB23_Msk (0x1U << CAN_F3R1_FB23_Pos) /*!< 0x00800000 */ 07123 #define CAN_F3R1_FB23 CAN_F3R1_FB23_Msk /*!< Filter bit 23 */ 07124 #define CAN_F3R1_FB24_Pos (24U) 07125 #define CAN_F3R1_FB24_Msk (0x1U << CAN_F3R1_FB24_Pos) /*!< 0x01000000 */ 07126 #define CAN_F3R1_FB24 CAN_F3R1_FB24_Msk /*!< Filter bit 24 */ 07127 #define CAN_F3R1_FB25_Pos (25U) 07128 #define CAN_F3R1_FB25_Msk (0x1U << CAN_F3R1_FB25_Pos) /*!< 0x02000000 */ 07129 #define CAN_F3R1_FB25 CAN_F3R1_FB25_Msk /*!< Filter bit 25 */ 07130 #define CAN_F3R1_FB26_Pos (26U) 07131 #define CAN_F3R1_FB26_Msk (0x1U << CAN_F3R1_FB26_Pos) /*!< 0x04000000 */ 07132 #define CAN_F3R1_FB26 CAN_F3R1_FB26_Msk /*!< Filter bit 26 */ 07133 #define CAN_F3R1_FB27_Pos (27U) 07134 #define CAN_F3R1_FB27_Msk (0x1U << CAN_F3R1_FB27_Pos) /*!< 0x08000000 */ 07135 #define CAN_F3R1_FB27 CAN_F3R1_FB27_Msk /*!< Filter bit 27 */ 07136 #define CAN_F3R1_FB28_Pos (28U) 07137 #define CAN_F3R1_FB28_Msk (0x1U << CAN_F3R1_FB28_Pos) /*!< 0x10000000 */ 07138 #define CAN_F3R1_FB28 CAN_F3R1_FB28_Msk /*!< Filter bit 28 */ 07139 #define CAN_F3R1_FB29_Pos (29U) 07140 #define CAN_F3R1_FB29_Msk (0x1U << CAN_F3R1_FB29_Pos) /*!< 0x20000000 */ 07141 #define CAN_F3R1_FB29 CAN_F3R1_FB29_Msk /*!< Filter bit 29 */ 07142 #define CAN_F3R1_FB30_Pos (30U) 07143 #define CAN_F3R1_FB30_Msk (0x1U << CAN_F3R1_FB30_Pos) /*!< 0x40000000 */ 07144 #define CAN_F3R1_FB30 CAN_F3R1_FB30_Msk /*!< Filter bit 30 */ 07145 #define CAN_F3R1_FB31_Pos (31U) 07146 #define CAN_F3R1_FB31_Msk (0x1U << CAN_F3R1_FB31_Pos) /*!< 0x80000000 */ 07147 #define CAN_F3R1_FB31 CAN_F3R1_FB31_Msk /*!< Filter bit 31 */ 07148 07149 /******************* Bit definition for CAN_F4R1 register *******************/ 07150 #define CAN_F4R1_FB0_Pos (0U) 07151 #define CAN_F4R1_FB0_Msk (0x1U << CAN_F4R1_FB0_Pos) /*!< 0x00000001 */ 07152 #define CAN_F4R1_FB0 CAN_F4R1_FB0_Msk /*!< Filter bit 0 */ 07153 #define CAN_F4R1_FB1_Pos (1U) 07154 #define CAN_F4R1_FB1_Msk (0x1U << CAN_F4R1_FB1_Pos) /*!< 0x00000002 */ 07155 #define CAN_F4R1_FB1 CAN_F4R1_FB1_Msk /*!< Filter bit 1 */ 07156 #define CAN_F4R1_FB2_Pos (2U) 07157 #define CAN_F4R1_FB2_Msk (0x1U << CAN_F4R1_FB2_Pos) /*!< 0x00000004 */ 07158 #define CAN_F4R1_FB2 CAN_F4R1_FB2_Msk /*!< Filter bit 2 */ 07159 #define CAN_F4R1_FB3_Pos (3U) 07160 #define CAN_F4R1_FB3_Msk (0x1U << CAN_F4R1_FB3_Pos) /*!< 0x00000008 */ 07161 #define CAN_F4R1_FB3 CAN_F4R1_FB3_Msk /*!< Filter bit 3 */ 07162 #define CAN_F4R1_FB4_Pos (4U) 07163 #define CAN_F4R1_FB4_Msk (0x1U << CAN_F4R1_FB4_Pos) /*!< 0x00000010 */ 07164 #define CAN_F4R1_FB4 CAN_F4R1_FB4_Msk /*!< Filter bit 4 */ 07165 #define CAN_F4R1_FB5_Pos (5U) 07166 #define CAN_F4R1_FB5_Msk (0x1U << CAN_F4R1_FB5_Pos) /*!< 0x00000020 */ 07167 #define CAN_F4R1_FB5 CAN_F4R1_FB5_Msk /*!< Filter bit 5 */ 07168 #define CAN_F4R1_FB6_Pos (6U) 07169 #define CAN_F4R1_FB6_Msk (0x1U << CAN_F4R1_FB6_Pos) /*!< 0x00000040 */ 07170 #define CAN_F4R1_FB6 CAN_F4R1_FB6_Msk /*!< Filter bit 6 */ 07171 #define CAN_F4R1_FB7_Pos (7U) 07172 #define CAN_F4R1_FB7_Msk (0x1U << CAN_F4R1_FB7_Pos) /*!< 0x00000080 */ 07173 #define CAN_F4R1_FB7 CAN_F4R1_FB7_Msk /*!< Filter bit 7 */ 07174 #define CAN_F4R1_FB8_Pos (8U) 07175 #define CAN_F4R1_FB8_Msk (0x1U << CAN_F4R1_FB8_Pos) /*!< 0x00000100 */ 07176 #define CAN_F4R1_FB8 CAN_F4R1_FB8_Msk /*!< Filter bit 8 */ 07177 #define CAN_F4R1_FB9_Pos (9U) 07178 #define CAN_F4R1_FB9_Msk (0x1U << CAN_F4R1_FB9_Pos) /*!< 0x00000200 */ 07179 #define CAN_F4R1_FB9 CAN_F4R1_FB9_Msk /*!< Filter bit 9 */ 07180 #define CAN_F4R1_FB10_Pos (10U) 07181 #define CAN_F4R1_FB10_Msk (0x1U << CAN_F4R1_FB10_Pos) /*!< 0x00000400 */ 07182 #define CAN_F4R1_FB10 CAN_F4R1_FB10_Msk /*!< Filter bit 10 */ 07183 #define CAN_F4R1_FB11_Pos (11U) 07184 #define CAN_F4R1_FB11_Msk (0x1U << CAN_F4R1_FB11_Pos) /*!< 0x00000800 */ 07185 #define CAN_F4R1_FB11 CAN_F4R1_FB11_Msk /*!< Filter bit 11 */ 07186 #define CAN_F4R1_FB12_Pos (12U) 07187 #define CAN_F4R1_FB12_Msk (0x1U << CAN_F4R1_FB12_Pos) /*!< 0x00001000 */ 07188 #define CAN_F4R1_FB12 CAN_F4R1_FB12_Msk /*!< Filter bit 12 */ 07189 #define CAN_F4R1_FB13_Pos (13U) 07190 #define CAN_F4R1_FB13_Msk (0x1U << CAN_F4R1_FB13_Pos) /*!< 0x00002000 */ 07191 #define CAN_F4R1_FB13 CAN_F4R1_FB13_Msk /*!< Filter bit 13 */ 07192 #define CAN_F4R1_FB14_Pos (14U) 07193 #define CAN_F4R1_FB14_Msk (0x1U << CAN_F4R1_FB14_Pos) /*!< 0x00004000 */ 07194 #define CAN_F4R1_FB14 CAN_F4R1_FB14_Msk /*!< Filter bit 14 */ 07195 #define CAN_F4R1_FB15_Pos (15U) 07196 #define CAN_F4R1_FB15_Msk (0x1U << CAN_F4R1_FB15_Pos) /*!< 0x00008000 */ 07197 #define CAN_F4R1_FB15 CAN_F4R1_FB15_Msk /*!< Filter bit 15 */ 07198 #define CAN_F4R1_FB16_Pos (16U) 07199 #define CAN_F4R1_FB16_Msk (0x1U << CAN_F4R1_FB16_Pos) /*!< 0x00010000 */ 07200 #define CAN_F4R1_FB16 CAN_F4R1_FB16_Msk /*!< Filter bit 16 */ 07201 #define CAN_F4R1_FB17_Pos (17U) 07202 #define CAN_F4R1_FB17_Msk (0x1U << CAN_F4R1_FB17_Pos) /*!< 0x00020000 */ 07203 #define CAN_F4R1_FB17 CAN_F4R1_FB17_Msk /*!< Filter bit 17 */ 07204 #define CAN_F4R1_FB18_Pos (18U) 07205 #define CAN_F4R1_FB18_Msk (0x1U << CAN_F4R1_FB18_Pos) /*!< 0x00040000 */ 07206 #define CAN_F4R1_FB18 CAN_F4R1_FB18_Msk /*!< Filter bit 18 */ 07207 #define CAN_F4R1_FB19_Pos (19U) 07208 #define CAN_F4R1_FB19_Msk (0x1U << CAN_F4R1_FB19_Pos) /*!< 0x00080000 */ 07209 #define CAN_F4R1_FB19 CAN_F4R1_FB19_Msk /*!< Filter bit 19 */ 07210 #define CAN_F4R1_FB20_Pos (20U) 07211 #define CAN_F4R1_FB20_Msk (0x1U << CAN_F4R1_FB20_Pos) /*!< 0x00100000 */ 07212 #define CAN_F4R1_FB20 CAN_F4R1_FB20_Msk /*!< Filter bit 20 */ 07213 #define CAN_F4R1_FB21_Pos (21U) 07214 #define CAN_F4R1_FB21_Msk (0x1U << CAN_F4R1_FB21_Pos) /*!< 0x00200000 */ 07215 #define CAN_F4R1_FB21 CAN_F4R1_FB21_Msk /*!< Filter bit 21 */ 07216 #define CAN_F4R1_FB22_Pos (22U) 07217 #define CAN_F4R1_FB22_Msk (0x1U << CAN_F4R1_FB22_Pos) /*!< 0x00400000 */ 07218 #define CAN_F4R1_FB22 CAN_F4R1_FB22_Msk /*!< Filter bit 22 */ 07219 #define CAN_F4R1_FB23_Pos (23U) 07220 #define CAN_F4R1_FB23_Msk (0x1U << CAN_F4R1_FB23_Pos) /*!< 0x00800000 */ 07221 #define CAN_F4R1_FB23 CAN_F4R1_FB23_Msk /*!< Filter bit 23 */ 07222 #define CAN_F4R1_FB24_Pos (24U) 07223 #define CAN_F4R1_FB24_Msk (0x1U << CAN_F4R1_FB24_Pos) /*!< 0x01000000 */ 07224 #define CAN_F4R1_FB24 CAN_F4R1_FB24_Msk /*!< Filter bit 24 */ 07225 #define CAN_F4R1_FB25_Pos (25U) 07226 #define CAN_F4R1_FB25_Msk (0x1U << CAN_F4R1_FB25_Pos) /*!< 0x02000000 */ 07227 #define CAN_F4R1_FB25 CAN_F4R1_FB25_Msk /*!< Filter bit 25 */ 07228 #define CAN_F4R1_FB26_Pos (26U) 07229 #define CAN_F4R1_FB26_Msk (0x1U << CAN_F4R1_FB26_Pos) /*!< 0x04000000 */ 07230 #define CAN_F4R1_FB26 CAN_F4R1_FB26_Msk /*!< Filter bit 26 */ 07231 #define CAN_F4R1_FB27_Pos (27U) 07232 #define CAN_F4R1_FB27_Msk (0x1U << CAN_F4R1_FB27_Pos) /*!< 0x08000000 */ 07233 #define CAN_F4R1_FB27 CAN_F4R1_FB27_Msk /*!< Filter bit 27 */ 07234 #define CAN_F4R1_FB28_Pos (28U) 07235 #define CAN_F4R1_FB28_Msk (0x1U << CAN_F4R1_FB28_Pos) /*!< 0x10000000 */ 07236 #define CAN_F4R1_FB28 CAN_F4R1_FB28_Msk /*!< Filter bit 28 */ 07237 #define CAN_F4R1_FB29_Pos (29U) 07238 #define CAN_F4R1_FB29_Msk (0x1U << CAN_F4R1_FB29_Pos) /*!< 0x20000000 */ 07239 #define CAN_F4R1_FB29 CAN_F4R1_FB29_Msk /*!< Filter bit 29 */ 07240 #define CAN_F4R1_FB30_Pos (30U) 07241 #define CAN_F4R1_FB30_Msk (0x1U << CAN_F4R1_FB30_Pos) /*!< 0x40000000 */ 07242 #define CAN_F4R1_FB30 CAN_F4R1_FB30_Msk /*!< Filter bit 30 */ 07243 #define CAN_F4R1_FB31_Pos (31U) 07244 #define CAN_F4R1_FB31_Msk (0x1U << CAN_F4R1_FB31_Pos) /*!< 0x80000000 */ 07245 #define CAN_F4R1_FB31 CAN_F4R1_FB31_Msk /*!< Filter bit 31 */ 07246 07247 /******************* Bit definition for CAN_F5R1 register *******************/ 07248 #define CAN_F5R1_FB0_Pos (0U) 07249 #define CAN_F5R1_FB0_Msk (0x1U << CAN_F5R1_FB0_Pos) /*!< 0x00000001 */ 07250 #define CAN_F5R1_FB0 CAN_F5R1_FB0_Msk /*!< Filter bit 0 */ 07251 #define CAN_F5R1_FB1_Pos (1U) 07252 #define CAN_F5R1_FB1_Msk (0x1U << CAN_F5R1_FB1_Pos) /*!< 0x00000002 */ 07253 #define CAN_F5R1_FB1 CAN_F5R1_FB1_Msk /*!< Filter bit 1 */ 07254 #define CAN_F5R1_FB2_Pos (2U) 07255 #define CAN_F5R1_FB2_Msk (0x1U << CAN_F5R1_FB2_Pos) /*!< 0x00000004 */ 07256 #define CAN_F5R1_FB2 CAN_F5R1_FB2_Msk /*!< Filter bit 2 */ 07257 #define CAN_F5R1_FB3_Pos (3U) 07258 #define CAN_F5R1_FB3_Msk (0x1U << CAN_F5R1_FB3_Pos) /*!< 0x00000008 */ 07259 #define CAN_F5R1_FB3 CAN_F5R1_FB3_Msk /*!< Filter bit 3 */ 07260 #define CAN_F5R1_FB4_Pos (4U) 07261 #define CAN_F5R1_FB4_Msk (0x1U << CAN_F5R1_FB4_Pos) /*!< 0x00000010 */ 07262 #define CAN_F5R1_FB4 CAN_F5R1_FB4_Msk /*!< Filter bit 4 */ 07263 #define CAN_F5R1_FB5_Pos (5U) 07264 #define CAN_F5R1_FB5_Msk (0x1U << CAN_F5R1_FB5_Pos) /*!< 0x00000020 */ 07265 #define CAN_F5R1_FB5 CAN_F5R1_FB5_Msk /*!< Filter bit 5 */ 07266 #define CAN_F5R1_FB6_Pos (6U) 07267 #define CAN_F5R1_FB6_Msk (0x1U << CAN_F5R1_FB6_Pos) /*!< 0x00000040 */ 07268 #define CAN_F5R1_FB6 CAN_F5R1_FB6_Msk /*!< Filter bit 6 */ 07269 #define CAN_F5R1_FB7_Pos (7U) 07270 #define CAN_F5R1_FB7_Msk (0x1U << CAN_F5R1_FB7_Pos) /*!< 0x00000080 */ 07271 #define CAN_F5R1_FB7 CAN_F5R1_FB7_Msk /*!< Filter bit 7 */ 07272 #define CAN_F5R1_FB8_Pos (8U) 07273 #define CAN_F5R1_FB8_Msk (0x1U << CAN_F5R1_FB8_Pos) /*!< 0x00000100 */ 07274 #define CAN_F5R1_FB8 CAN_F5R1_FB8_Msk /*!< Filter bit 8 */ 07275 #define CAN_F5R1_FB9_Pos (9U) 07276 #define CAN_F5R1_FB9_Msk (0x1U << CAN_F5R1_FB9_Pos) /*!< 0x00000200 */ 07277 #define CAN_F5R1_FB9 CAN_F5R1_FB9_Msk /*!< Filter bit 9 */ 07278 #define CAN_F5R1_FB10_Pos (10U) 07279 #define CAN_F5R1_FB10_Msk (0x1U << CAN_F5R1_FB10_Pos) /*!< 0x00000400 */ 07280 #define CAN_F5R1_FB10 CAN_F5R1_FB10_Msk /*!< Filter bit 10 */ 07281 #define CAN_F5R1_FB11_Pos (11U) 07282 #define CAN_F5R1_FB11_Msk (0x1U << CAN_F5R1_FB11_Pos) /*!< 0x00000800 */ 07283 #define CAN_F5R1_FB11 CAN_F5R1_FB11_Msk /*!< Filter bit 11 */ 07284 #define CAN_F5R1_FB12_Pos (12U) 07285 #define CAN_F5R1_FB12_Msk (0x1U << CAN_F5R1_FB12_Pos) /*!< 0x00001000 */ 07286 #define CAN_F5R1_FB12 CAN_F5R1_FB12_Msk /*!< Filter bit 12 */ 07287 #define CAN_F5R1_FB13_Pos (13U) 07288 #define CAN_F5R1_FB13_Msk (0x1U << CAN_F5R1_FB13_Pos) /*!< 0x00002000 */ 07289 #define CAN_F5R1_FB13 CAN_F5R1_FB13_Msk /*!< Filter bit 13 */ 07290 #define CAN_F5R1_FB14_Pos (14U) 07291 #define CAN_F5R1_FB14_Msk (0x1U << CAN_F5R1_FB14_Pos) /*!< 0x00004000 */ 07292 #define CAN_F5R1_FB14 CAN_F5R1_FB14_Msk /*!< Filter bit 14 */ 07293 #define CAN_F5R1_FB15_Pos (15U) 07294 #define CAN_F5R1_FB15_Msk (0x1U << CAN_F5R1_FB15_Pos) /*!< 0x00008000 */ 07295 #define CAN_F5R1_FB15 CAN_F5R1_FB15_Msk /*!< Filter bit 15 */ 07296 #define CAN_F5R1_FB16_Pos (16U) 07297 #define CAN_F5R1_FB16_Msk (0x1U << CAN_F5R1_FB16_Pos) /*!< 0x00010000 */ 07298 #define CAN_F5R1_FB16 CAN_F5R1_FB16_Msk /*!< Filter bit 16 */ 07299 #define CAN_F5R1_FB17_Pos (17U) 07300 #define CAN_F5R1_FB17_Msk (0x1U << CAN_F5R1_FB17_Pos) /*!< 0x00020000 */ 07301 #define CAN_F5R1_FB17 CAN_F5R1_FB17_Msk /*!< Filter bit 17 */ 07302 #define CAN_F5R1_FB18_Pos (18U) 07303 #define CAN_F5R1_FB18_Msk (0x1U << CAN_F5R1_FB18_Pos) /*!< 0x00040000 */ 07304 #define CAN_F5R1_FB18 CAN_F5R1_FB18_Msk /*!< Filter bit 18 */ 07305 #define CAN_F5R1_FB19_Pos (19U) 07306 #define CAN_F5R1_FB19_Msk (0x1U << CAN_F5R1_FB19_Pos) /*!< 0x00080000 */ 07307 #define CAN_F5R1_FB19 CAN_F5R1_FB19_Msk /*!< Filter bit 19 */ 07308 #define CAN_F5R1_FB20_Pos (20U) 07309 #define CAN_F5R1_FB20_Msk (0x1U << CAN_F5R1_FB20_Pos) /*!< 0x00100000 */ 07310 #define CAN_F5R1_FB20 CAN_F5R1_FB20_Msk /*!< Filter bit 20 */ 07311 #define CAN_F5R1_FB21_Pos (21U) 07312 #define CAN_F5R1_FB21_Msk (0x1U << CAN_F5R1_FB21_Pos) /*!< 0x00200000 */ 07313 #define CAN_F5R1_FB21 CAN_F5R1_FB21_Msk /*!< Filter bit 21 */ 07314 #define CAN_F5R1_FB22_Pos (22U) 07315 #define CAN_F5R1_FB22_Msk (0x1U << CAN_F5R1_FB22_Pos) /*!< 0x00400000 */ 07316 #define CAN_F5R1_FB22 CAN_F5R1_FB22_Msk /*!< Filter bit 22 */ 07317 #define CAN_F5R1_FB23_Pos (23U) 07318 #define CAN_F5R1_FB23_Msk (0x1U << CAN_F5R1_FB23_Pos) /*!< 0x00800000 */ 07319 #define CAN_F5R1_FB23 CAN_F5R1_FB23_Msk /*!< Filter bit 23 */ 07320 #define CAN_F5R1_FB24_Pos (24U) 07321 #define CAN_F5R1_FB24_Msk (0x1U << CAN_F5R1_FB24_Pos) /*!< 0x01000000 */ 07322 #define CAN_F5R1_FB24 CAN_F5R1_FB24_Msk /*!< Filter bit 24 */ 07323 #define CAN_F5R1_FB25_Pos (25U) 07324 #define CAN_F5R1_FB25_Msk (0x1U << CAN_F5R1_FB25_Pos) /*!< 0x02000000 */ 07325 #define CAN_F5R1_FB25 CAN_F5R1_FB25_Msk /*!< Filter bit 25 */ 07326 #define CAN_F5R1_FB26_Pos (26U) 07327 #define CAN_F5R1_FB26_Msk (0x1U << CAN_F5R1_FB26_Pos) /*!< 0x04000000 */ 07328 #define CAN_F5R1_FB26 CAN_F5R1_FB26_Msk /*!< Filter bit 26 */ 07329 #define CAN_F5R1_FB27_Pos (27U) 07330 #define CAN_F5R1_FB27_Msk (0x1U << CAN_F5R1_FB27_Pos) /*!< 0x08000000 */ 07331 #define CAN_F5R1_FB27 CAN_F5R1_FB27_Msk /*!< Filter bit 27 */ 07332 #define CAN_F5R1_FB28_Pos (28U) 07333 #define CAN_F5R1_FB28_Msk (0x1U << CAN_F5R1_FB28_Pos) /*!< 0x10000000 */ 07334 #define CAN_F5R1_FB28 CAN_F5R1_FB28_Msk /*!< Filter bit 28 */ 07335 #define CAN_F5R1_FB29_Pos (29U) 07336 #define CAN_F5R1_FB29_Msk (0x1U << CAN_F5R1_FB29_Pos) /*!< 0x20000000 */ 07337 #define CAN_F5R1_FB29 CAN_F5R1_FB29_Msk /*!< Filter bit 29 */ 07338 #define CAN_F5R1_FB30_Pos (30U) 07339 #define CAN_F5R1_FB30_Msk (0x1U << CAN_F5R1_FB30_Pos) /*!< 0x40000000 */ 07340 #define CAN_F5R1_FB30 CAN_F5R1_FB30_Msk /*!< Filter bit 30 */ 07341 #define CAN_F5R1_FB31_Pos (31U) 07342 #define CAN_F5R1_FB31_Msk (0x1U << CAN_F5R1_FB31_Pos) /*!< 0x80000000 */ 07343 #define CAN_F5R1_FB31 CAN_F5R1_FB31_Msk /*!< Filter bit 31 */ 07344 07345 /******************* Bit definition for CAN_F6R1 register *******************/ 07346 #define CAN_F6R1_FB0_Pos (0U) 07347 #define CAN_F6R1_FB0_Msk (0x1U << CAN_F6R1_FB0_Pos) /*!< 0x00000001 */ 07348 #define CAN_F6R1_FB0 CAN_F6R1_FB0_Msk /*!< Filter bit 0 */ 07349 #define CAN_F6R1_FB1_Pos (1U) 07350 #define CAN_F6R1_FB1_Msk (0x1U << CAN_F6R1_FB1_Pos) /*!< 0x00000002 */ 07351 #define CAN_F6R1_FB1 CAN_F6R1_FB1_Msk /*!< Filter bit 1 */ 07352 #define CAN_F6R1_FB2_Pos (2U) 07353 #define CAN_F6R1_FB2_Msk (0x1U << CAN_F6R1_FB2_Pos) /*!< 0x00000004 */ 07354 #define CAN_F6R1_FB2 CAN_F6R1_FB2_Msk /*!< Filter bit 2 */ 07355 #define CAN_F6R1_FB3_Pos (3U) 07356 #define CAN_F6R1_FB3_Msk (0x1U << CAN_F6R1_FB3_Pos) /*!< 0x00000008 */ 07357 #define CAN_F6R1_FB3 CAN_F6R1_FB3_Msk /*!< Filter bit 3 */ 07358 #define CAN_F6R1_FB4_Pos (4U) 07359 #define CAN_F6R1_FB4_Msk (0x1U << CAN_F6R1_FB4_Pos) /*!< 0x00000010 */ 07360 #define CAN_F6R1_FB4 CAN_F6R1_FB4_Msk /*!< Filter bit 4 */ 07361 #define CAN_F6R1_FB5_Pos (5U) 07362 #define CAN_F6R1_FB5_Msk (0x1U << CAN_F6R1_FB5_Pos) /*!< 0x00000020 */ 07363 #define CAN_F6R1_FB5 CAN_F6R1_FB5_Msk /*!< Filter bit 5 */ 07364 #define CAN_F6R1_FB6_Pos (6U) 07365 #define CAN_F6R1_FB6_Msk (0x1U << CAN_F6R1_FB6_Pos) /*!< 0x00000040 */ 07366 #define CAN_F6R1_FB6 CAN_F6R1_FB6_Msk /*!< Filter bit 6 */ 07367 #define CAN_F6R1_FB7_Pos (7U) 07368 #define CAN_F6R1_FB7_Msk (0x1U << CAN_F6R1_FB7_Pos) /*!< 0x00000080 */ 07369 #define CAN_F6R1_FB7 CAN_F6R1_FB7_Msk /*!< Filter bit 7 */ 07370 #define CAN_F6R1_FB8_Pos (8U) 07371 #define CAN_F6R1_FB8_Msk (0x1U << CAN_F6R1_FB8_Pos) /*!< 0x00000100 */ 07372 #define CAN_F6R1_FB8 CAN_F6R1_FB8_Msk /*!< Filter bit 8 */ 07373 #define CAN_F6R1_FB9_Pos (9U) 07374 #define CAN_F6R1_FB9_Msk (0x1U << CAN_F6R1_FB9_Pos) /*!< 0x00000200 */ 07375 #define CAN_F6R1_FB9 CAN_F6R1_FB9_Msk /*!< Filter bit 9 */ 07376 #define CAN_F6R1_FB10_Pos (10U) 07377 #define CAN_F6R1_FB10_Msk (0x1U << CAN_F6R1_FB10_Pos) /*!< 0x00000400 */ 07378 #define CAN_F6R1_FB10 CAN_F6R1_FB10_Msk /*!< Filter bit 10 */ 07379 #define CAN_F6R1_FB11_Pos (11U) 07380 #define CAN_F6R1_FB11_Msk (0x1U << CAN_F6R1_FB11_Pos) /*!< 0x00000800 */ 07381 #define CAN_F6R1_FB11 CAN_F6R1_FB11_Msk /*!< Filter bit 11 */ 07382 #define CAN_F6R1_FB12_Pos (12U) 07383 #define CAN_F6R1_FB12_Msk (0x1U << CAN_F6R1_FB12_Pos) /*!< 0x00001000 */ 07384 #define CAN_F6R1_FB12 CAN_F6R1_FB12_Msk /*!< Filter bit 12 */ 07385 #define CAN_F6R1_FB13_Pos (13U) 07386 #define CAN_F6R1_FB13_Msk (0x1U << CAN_F6R1_FB13_Pos) /*!< 0x00002000 */ 07387 #define CAN_F6R1_FB13 CAN_F6R1_FB13_Msk /*!< Filter bit 13 */ 07388 #define CAN_F6R1_FB14_Pos (14U) 07389 #define CAN_F6R1_FB14_Msk (0x1U << CAN_F6R1_FB14_Pos) /*!< 0x00004000 */ 07390 #define CAN_F6R1_FB14 CAN_F6R1_FB14_Msk /*!< Filter bit 14 */ 07391 #define CAN_F6R1_FB15_Pos (15U) 07392 #define CAN_F6R1_FB15_Msk (0x1U << CAN_F6R1_FB15_Pos) /*!< 0x00008000 */ 07393 #define CAN_F6R1_FB15 CAN_F6R1_FB15_Msk /*!< Filter bit 15 */ 07394 #define CAN_F6R1_FB16_Pos (16U) 07395 #define CAN_F6R1_FB16_Msk (0x1U << CAN_F6R1_FB16_Pos) /*!< 0x00010000 */ 07396 #define CAN_F6R1_FB16 CAN_F6R1_FB16_Msk /*!< Filter bit 16 */ 07397 #define CAN_F6R1_FB17_Pos (17U) 07398 #define CAN_F6R1_FB17_Msk (0x1U << CAN_F6R1_FB17_Pos) /*!< 0x00020000 */ 07399 #define CAN_F6R1_FB17 CAN_F6R1_FB17_Msk /*!< Filter bit 17 */ 07400 #define CAN_F6R1_FB18_Pos (18U) 07401 #define CAN_F6R1_FB18_Msk (0x1U << CAN_F6R1_FB18_Pos) /*!< 0x00040000 */ 07402 #define CAN_F6R1_FB18 CAN_F6R1_FB18_Msk /*!< Filter bit 18 */ 07403 #define CAN_F6R1_FB19_Pos (19U) 07404 #define CAN_F6R1_FB19_Msk (0x1U << CAN_F6R1_FB19_Pos) /*!< 0x00080000 */ 07405 #define CAN_F6R1_FB19 CAN_F6R1_FB19_Msk /*!< Filter bit 19 */ 07406 #define CAN_F6R1_FB20_Pos (20U) 07407 #define CAN_F6R1_FB20_Msk (0x1U << CAN_F6R1_FB20_Pos) /*!< 0x00100000 */ 07408 #define CAN_F6R1_FB20 CAN_F6R1_FB20_Msk /*!< Filter bit 20 */ 07409 #define CAN_F6R1_FB21_Pos (21U) 07410 #define CAN_F6R1_FB21_Msk (0x1U << CAN_F6R1_FB21_Pos) /*!< 0x00200000 */ 07411 #define CAN_F6R1_FB21 CAN_F6R1_FB21_Msk /*!< Filter bit 21 */ 07412 #define CAN_F6R1_FB22_Pos (22U) 07413 #define CAN_F6R1_FB22_Msk (0x1U << CAN_F6R1_FB22_Pos) /*!< 0x00400000 */ 07414 #define CAN_F6R1_FB22 CAN_F6R1_FB22_Msk /*!< Filter bit 22 */ 07415 #define CAN_F6R1_FB23_Pos (23U) 07416 #define CAN_F6R1_FB23_Msk (0x1U << CAN_F6R1_FB23_Pos) /*!< 0x00800000 */ 07417 #define CAN_F6R1_FB23 CAN_F6R1_FB23_Msk /*!< Filter bit 23 */ 07418 #define CAN_F6R1_FB24_Pos (24U) 07419 #define CAN_F6R1_FB24_Msk (0x1U << CAN_F6R1_FB24_Pos) /*!< 0x01000000 */ 07420 #define CAN_F6R1_FB24 CAN_F6R1_FB24_Msk /*!< Filter bit 24 */ 07421 #define CAN_F6R1_FB25_Pos (25U) 07422 #define CAN_F6R1_FB25_Msk (0x1U << CAN_F6R1_FB25_Pos) /*!< 0x02000000 */ 07423 #define CAN_F6R1_FB25 CAN_F6R1_FB25_Msk /*!< Filter bit 25 */ 07424 #define CAN_F6R1_FB26_Pos (26U) 07425 #define CAN_F6R1_FB26_Msk (0x1U << CAN_F6R1_FB26_Pos) /*!< 0x04000000 */ 07426 #define CAN_F6R1_FB26 CAN_F6R1_FB26_Msk /*!< Filter bit 26 */ 07427 #define CAN_F6R1_FB27_Pos (27U) 07428 #define CAN_F6R1_FB27_Msk (0x1U << CAN_F6R1_FB27_Pos) /*!< 0x08000000 */ 07429 #define CAN_F6R1_FB27 CAN_F6R1_FB27_Msk /*!< Filter bit 27 */ 07430 #define CAN_F6R1_FB28_Pos (28U) 07431 #define CAN_F6R1_FB28_Msk (0x1U << CAN_F6R1_FB28_Pos) /*!< 0x10000000 */ 07432 #define CAN_F6R1_FB28 CAN_F6R1_FB28_Msk /*!< Filter bit 28 */ 07433 #define CAN_F6R1_FB29_Pos (29U) 07434 #define CAN_F6R1_FB29_Msk (0x1U << CAN_F6R1_FB29_Pos) /*!< 0x20000000 */ 07435 #define CAN_F6R1_FB29 CAN_F6R1_FB29_Msk /*!< Filter bit 29 */ 07436 #define CAN_F6R1_FB30_Pos (30U) 07437 #define CAN_F6R1_FB30_Msk (0x1U << CAN_F6R1_FB30_Pos) /*!< 0x40000000 */ 07438 #define CAN_F6R1_FB30 CAN_F6R1_FB30_Msk /*!< Filter bit 30 */ 07439 #define CAN_F6R1_FB31_Pos (31U) 07440 #define CAN_F6R1_FB31_Msk (0x1U << CAN_F6R1_FB31_Pos) /*!< 0x80000000 */ 07441 #define CAN_F6R1_FB31 CAN_F6R1_FB31_Msk /*!< Filter bit 31 */ 07442 07443 /******************* Bit definition for CAN_F7R1 register *******************/ 07444 #define CAN_F7R1_FB0_Pos (0U) 07445 #define CAN_F7R1_FB0_Msk (0x1U << CAN_F7R1_FB0_Pos) /*!< 0x00000001 */ 07446 #define CAN_F7R1_FB0 CAN_F7R1_FB0_Msk /*!< Filter bit 0 */ 07447 #define CAN_F7R1_FB1_Pos (1U) 07448 #define CAN_F7R1_FB1_Msk (0x1U << CAN_F7R1_FB1_Pos) /*!< 0x00000002 */ 07449 #define CAN_F7R1_FB1 CAN_F7R1_FB1_Msk /*!< Filter bit 1 */ 07450 #define CAN_F7R1_FB2_Pos (2U) 07451 #define CAN_F7R1_FB2_Msk (0x1U << CAN_F7R1_FB2_Pos) /*!< 0x00000004 */ 07452 #define CAN_F7R1_FB2 CAN_F7R1_FB2_Msk /*!< Filter bit 2 */ 07453 #define CAN_F7R1_FB3_Pos (3U) 07454 #define CAN_F7R1_FB3_Msk (0x1U << CAN_F7R1_FB3_Pos) /*!< 0x00000008 */ 07455 #define CAN_F7R1_FB3 CAN_F7R1_FB3_Msk /*!< Filter bit 3 */ 07456 #define CAN_F7R1_FB4_Pos (4U) 07457 #define CAN_F7R1_FB4_Msk (0x1U << CAN_F7R1_FB4_Pos) /*!< 0x00000010 */ 07458 #define CAN_F7R1_FB4 CAN_F7R1_FB4_Msk /*!< Filter bit 4 */ 07459 #define CAN_F7R1_FB5_Pos (5U) 07460 #define CAN_F7R1_FB5_Msk (0x1U << CAN_F7R1_FB5_Pos) /*!< 0x00000020 */ 07461 #define CAN_F7R1_FB5 CAN_F7R1_FB5_Msk /*!< Filter bit 5 */ 07462 #define CAN_F7R1_FB6_Pos (6U) 07463 #define CAN_F7R1_FB6_Msk (0x1U << CAN_F7R1_FB6_Pos) /*!< 0x00000040 */ 07464 #define CAN_F7R1_FB6 CAN_F7R1_FB6_Msk /*!< Filter bit 6 */ 07465 #define CAN_F7R1_FB7_Pos (7U) 07466 #define CAN_F7R1_FB7_Msk (0x1U << CAN_F7R1_FB7_Pos) /*!< 0x00000080 */ 07467 #define CAN_F7R1_FB7 CAN_F7R1_FB7_Msk /*!< Filter bit 7 */ 07468 #define CAN_F7R1_FB8_Pos (8U) 07469 #define CAN_F7R1_FB8_Msk (0x1U << CAN_F7R1_FB8_Pos) /*!< 0x00000100 */ 07470 #define CAN_F7R1_FB8 CAN_F7R1_FB8_Msk /*!< Filter bit 8 */ 07471 #define CAN_F7R1_FB9_Pos (9U) 07472 #define CAN_F7R1_FB9_Msk (0x1U << CAN_F7R1_FB9_Pos) /*!< 0x00000200 */ 07473 #define CAN_F7R1_FB9 CAN_F7R1_FB9_Msk /*!< Filter bit 9 */ 07474 #define CAN_F7R1_FB10_Pos (10U) 07475 #define CAN_F7R1_FB10_Msk (0x1U << CAN_F7R1_FB10_Pos) /*!< 0x00000400 */ 07476 #define CAN_F7R1_FB10 CAN_F7R1_FB10_Msk /*!< Filter bit 10 */ 07477 #define CAN_F7R1_FB11_Pos (11U) 07478 #define CAN_F7R1_FB11_Msk (0x1U << CAN_F7R1_FB11_Pos) /*!< 0x00000800 */ 07479 #define CAN_F7R1_FB11 CAN_F7R1_FB11_Msk /*!< Filter bit 11 */ 07480 #define CAN_F7R1_FB12_Pos (12U) 07481 #define CAN_F7R1_FB12_Msk (0x1U << CAN_F7R1_FB12_Pos) /*!< 0x00001000 */ 07482 #define CAN_F7R1_FB12 CAN_F7R1_FB12_Msk /*!< Filter bit 12 */ 07483 #define CAN_F7R1_FB13_Pos (13U) 07484 #define CAN_F7R1_FB13_Msk (0x1U << CAN_F7R1_FB13_Pos) /*!< 0x00002000 */ 07485 #define CAN_F7R1_FB13 CAN_F7R1_FB13_Msk /*!< Filter bit 13 */ 07486 #define CAN_F7R1_FB14_Pos (14U) 07487 #define CAN_F7R1_FB14_Msk (0x1U << CAN_F7R1_FB14_Pos) /*!< 0x00004000 */ 07488 #define CAN_F7R1_FB14 CAN_F7R1_FB14_Msk /*!< Filter bit 14 */ 07489 #define CAN_F7R1_FB15_Pos (15U) 07490 #define CAN_F7R1_FB15_Msk (0x1U << CAN_F7R1_FB15_Pos) /*!< 0x00008000 */ 07491 #define CAN_F7R1_FB15 CAN_F7R1_FB15_Msk /*!< Filter bit 15 */ 07492 #define CAN_F7R1_FB16_Pos (16U) 07493 #define CAN_F7R1_FB16_Msk (0x1U << CAN_F7R1_FB16_Pos) /*!< 0x00010000 */ 07494 #define CAN_F7R1_FB16 CAN_F7R1_FB16_Msk /*!< Filter bit 16 */ 07495 #define CAN_F7R1_FB17_Pos (17U) 07496 #define CAN_F7R1_FB17_Msk (0x1U << CAN_F7R1_FB17_Pos) /*!< 0x00020000 */ 07497 #define CAN_F7R1_FB17 CAN_F7R1_FB17_Msk /*!< Filter bit 17 */ 07498 #define CAN_F7R1_FB18_Pos (18U) 07499 #define CAN_F7R1_FB18_Msk (0x1U << CAN_F7R1_FB18_Pos) /*!< 0x00040000 */ 07500 #define CAN_F7R1_FB18 CAN_F7R1_FB18_Msk /*!< Filter bit 18 */ 07501 #define CAN_F7R1_FB19_Pos (19U) 07502 #define CAN_F7R1_FB19_Msk (0x1U << CAN_F7R1_FB19_Pos) /*!< 0x00080000 */ 07503 #define CAN_F7R1_FB19 CAN_F7R1_FB19_Msk /*!< Filter bit 19 */ 07504 #define CAN_F7R1_FB20_Pos (20U) 07505 #define CAN_F7R1_FB20_Msk (0x1U << CAN_F7R1_FB20_Pos) /*!< 0x00100000 */ 07506 #define CAN_F7R1_FB20 CAN_F7R1_FB20_Msk /*!< Filter bit 20 */ 07507 #define CAN_F7R1_FB21_Pos (21U) 07508 #define CAN_F7R1_FB21_Msk (0x1U << CAN_F7R1_FB21_Pos) /*!< 0x00200000 */ 07509 #define CAN_F7R1_FB21 CAN_F7R1_FB21_Msk /*!< Filter bit 21 */ 07510 #define CAN_F7R1_FB22_Pos (22U) 07511 #define CAN_F7R1_FB22_Msk (0x1U << CAN_F7R1_FB22_Pos) /*!< 0x00400000 */ 07512 #define CAN_F7R1_FB22 CAN_F7R1_FB22_Msk /*!< Filter bit 22 */ 07513 #define CAN_F7R1_FB23_Pos (23U) 07514 #define CAN_F7R1_FB23_Msk (0x1U << CAN_F7R1_FB23_Pos) /*!< 0x00800000 */ 07515 #define CAN_F7R1_FB23 CAN_F7R1_FB23_Msk /*!< Filter bit 23 */ 07516 #define CAN_F7R1_FB24_Pos (24U) 07517 #define CAN_F7R1_FB24_Msk (0x1U << CAN_F7R1_FB24_Pos) /*!< 0x01000000 */ 07518 #define CAN_F7R1_FB24 CAN_F7R1_FB24_Msk /*!< Filter bit 24 */ 07519 #define CAN_F7R1_FB25_Pos (25U) 07520 #define CAN_F7R1_FB25_Msk (0x1U << CAN_F7R1_FB25_Pos) /*!< 0x02000000 */ 07521 #define CAN_F7R1_FB25 CAN_F7R1_FB25_Msk /*!< Filter bit 25 */ 07522 #define CAN_F7R1_FB26_Pos (26U) 07523 #define CAN_F7R1_FB26_Msk (0x1U << CAN_F7R1_FB26_Pos) /*!< 0x04000000 */ 07524 #define CAN_F7R1_FB26 CAN_F7R1_FB26_Msk /*!< Filter bit 26 */ 07525 #define CAN_F7R1_FB27_Pos (27U) 07526 #define CAN_F7R1_FB27_Msk (0x1U << CAN_F7R1_FB27_Pos) /*!< 0x08000000 */ 07527 #define CAN_F7R1_FB27 CAN_F7R1_FB27_Msk /*!< Filter bit 27 */ 07528 #define CAN_F7R1_FB28_Pos (28U) 07529 #define CAN_F7R1_FB28_Msk (0x1U << CAN_F7R1_FB28_Pos) /*!< 0x10000000 */ 07530 #define CAN_F7R1_FB28 CAN_F7R1_FB28_Msk /*!< Filter bit 28 */ 07531 #define CAN_F7R1_FB29_Pos (29U) 07532 #define CAN_F7R1_FB29_Msk (0x1U << CAN_F7R1_FB29_Pos) /*!< 0x20000000 */ 07533 #define CAN_F7R1_FB29 CAN_F7R1_FB29_Msk /*!< Filter bit 29 */ 07534 #define CAN_F7R1_FB30_Pos (30U) 07535 #define CAN_F7R1_FB30_Msk (0x1U << CAN_F7R1_FB30_Pos) /*!< 0x40000000 */ 07536 #define CAN_F7R1_FB30 CAN_F7R1_FB30_Msk /*!< Filter bit 30 */ 07537 #define CAN_F7R1_FB31_Pos (31U) 07538 #define CAN_F7R1_FB31_Msk (0x1U << CAN_F7R1_FB31_Pos) /*!< 0x80000000 */ 07539 #define CAN_F7R1_FB31 CAN_F7R1_FB31_Msk /*!< Filter bit 31 */ 07540 07541 /******************* Bit definition for CAN_F8R1 register *******************/ 07542 #define CAN_F8R1_FB0_Pos (0U) 07543 #define CAN_F8R1_FB0_Msk (0x1U << CAN_F8R1_FB0_Pos) /*!< 0x00000001 */ 07544 #define CAN_F8R1_FB0 CAN_F8R1_FB0_Msk /*!< Filter bit 0 */ 07545 #define CAN_F8R1_FB1_Pos (1U) 07546 #define CAN_F8R1_FB1_Msk (0x1U << CAN_F8R1_FB1_Pos) /*!< 0x00000002 */ 07547 #define CAN_F8R1_FB1 CAN_F8R1_FB1_Msk /*!< Filter bit 1 */ 07548 #define CAN_F8R1_FB2_Pos (2U) 07549 #define CAN_F8R1_FB2_Msk (0x1U << CAN_F8R1_FB2_Pos) /*!< 0x00000004 */ 07550 #define CAN_F8R1_FB2 CAN_F8R1_FB2_Msk /*!< Filter bit 2 */ 07551 #define CAN_F8R1_FB3_Pos (3U) 07552 #define CAN_F8R1_FB3_Msk (0x1U << CAN_F8R1_FB3_Pos) /*!< 0x00000008 */ 07553 #define CAN_F8R1_FB3 CAN_F8R1_FB3_Msk /*!< Filter bit 3 */ 07554 #define CAN_F8R1_FB4_Pos (4U) 07555 #define CAN_F8R1_FB4_Msk (0x1U << CAN_F8R1_FB4_Pos) /*!< 0x00000010 */ 07556 #define CAN_F8R1_FB4 CAN_F8R1_FB4_Msk /*!< Filter bit 4 */ 07557 #define CAN_F8R1_FB5_Pos (5U) 07558 #define CAN_F8R1_FB5_Msk (0x1U << CAN_F8R1_FB5_Pos) /*!< 0x00000020 */ 07559 #define CAN_F8R1_FB5 CAN_F8R1_FB5_Msk /*!< Filter bit 5 */ 07560 #define CAN_F8R1_FB6_Pos (6U) 07561 #define CAN_F8R1_FB6_Msk (0x1U << CAN_F8R1_FB6_Pos) /*!< 0x00000040 */ 07562 #define CAN_F8R1_FB6 CAN_F8R1_FB6_Msk /*!< Filter bit 6 */ 07563 #define CAN_F8R1_FB7_Pos (7U) 07564 #define CAN_F8R1_FB7_Msk (0x1U << CAN_F8R1_FB7_Pos) /*!< 0x00000080 */ 07565 #define CAN_F8R1_FB7 CAN_F8R1_FB7_Msk /*!< Filter bit 7 */ 07566 #define CAN_F8R1_FB8_Pos (8U) 07567 #define CAN_F8R1_FB8_Msk (0x1U << CAN_F8R1_FB8_Pos) /*!< 0x00000100 */ 07568 #define CAN_F8R1_FB8 CAN_F8R1_FB8_Msk /*!< Filter bit 8 */ 07569 #define CAN_F8R1_FB9_Pos (9U) 07570 #define CAN_F8R1_FB9_Msk (0x1U << CAN_F8R1_FB9_Pos) /*!< 0x00000200 */ 07571 #define CAN_F8R1_FB9 CAN_F8R1_FB9_Msk /*!< Filter bit 9 */ 07572 #define CAN_F8R1_FB10_Pos (10U) 07573 #define CAN_F8R1_FB10_Msk (0x1U << CAN_F8R1_FB10_Pos) /*!< 0x00000400 */ 07574 #define CAN_F8R1_FB10 CAN_F8R1_FB10_Msk /*!< Filter bit 10 */ 07575 #define CAN_F8R1_FB11_Pos (11U) 07576 #define CAN_F8R1_FB11_Msk (0x1U << CAN_F8R1_FB11_Pos) /*!< 0x00000800 */ 07577 #define CAN_F8R1_FB11 CAN_F8R1_FB11_Msk /*!< Filter bit 11 */ 07578 #define CAN_F8R1_FB12_Pos (12U) 07579 #define CAN_F8R1_FB12_Msk (0x1U << CAN_F8R1_FB12_Pos) /*!< 0x00001000 */ 07580 #define CAN_F8R1_FB12 CAN_F8R1_FB12_Msk /*!< Filter bit 12 */ 07581 #define CAN_F8R1_FB13_Pos (13U) 07582 #define CAN_F8R1_FB13_Msk (0x1U << CAN_F8R1_FB13_Pos) /*!< 0x00002000 */ 07583 #define CAN_F8R1_FB13 CAN_F8R1_FB13_Msk /*!< Filter bit 13 */ 07584 #define CAN_F8R1_FB14_Pos (14U) 07585 #define CAN_F8R1_FB14_Msk (0x1U << CAN_F8R1_FB14_Pos) /*!< 0x00004000 */ 07586 #define CAN_F8R1_FB14 CAN_F8R1_FB14_Msk /*!< Filter bit 14 */ 07587 #define CAN_F8R1_FB15_Pos (15U) 07588 #define CAN_F8R1_FB15_Msk (0x1U << CAN_F8R1_FB15_Pos) /*!< 0x00008000 */ 07589 #define CAN_F8R1_FB15 CAN_F8R1_FB15_Msk /*!< Filter bit 15 */ 07590 #define CAN_F8R1_FB16_Pos (16U) 07591 #define CAN_F8R1_FB16_Msk (0x1U << CAN_F8R1_FB16_Pos) /*!< 0x00010000 */ 07592 #define CAN_F8R1_FB16 CAN_F8R1_FB16_Msk /*!< Filter bit 16 */ 07593 #define CAN_F8R1_FB17_Pos (17U) 07594 #define CAN_F8R1_FB17_Msk (0x1U << CAN_F8R1_FB17_Pos) /*!< 0x00020000 */ 07595 #define CAN_F8R1_FB17 CAN_F8R1_FB17_Msk /*!< Filter bit 17 */ 07596 #define CAN_F8R1_FB18_Pos (18U) 07597 #define CAN_F8R1_FB18_Msk (0x1U << CAN_F8R1_FB18_Pos) /*!< 0x00040000 */ 07598 #define CAN_F8R1_FB18 CAN_F8R1_FB18_Msk /*!< Filter bit 18 */ 07599 #define CAN_F8R1_FB19_Pos (19U) 07600 #define CAN_F8R1_FB19_Msk (0x1U << CAN_F8R1_FB19_Pos) /*!< 0x00080000 */ 07601 #define CAN_F8R1_FB19 CAN_F8R1_FB19_Msk /*!< Filter bit 19 */ 07602 #define CAN_F8R1_FB20_Pos (20U) 07603 #define CAN_F8R1_FB20_Msk (0x1U << CAN_F8R1_FB20_Pos) /*!< 0x00100000 */ 07604 #define CAN_F8R1_FB20 CAN_F8R1_FB20_Msk /*!< Filter bit 20 */ 07605 #define CAN_F8R1_FB21_Pos (21U) 07606 #define CAN_F8R1_FB21_Msk (0x1U << CAN_F8R1_FB21_Pos) /*!< 0x00200000 */ 07607 #define CAN_F8R1_FB21 CAN_F8R1_FB21_Msk /*!< Filter bit 21 */ 07608 #define CAN_F8R1_FB22_Pos (22U) 07609 #define CAN_F8R1_FB22_Msk (0x1U << CAN_F8R1_FB22_Pos) /*!< 0x00400000 */ 07610 #define CAN_F8R1_FB22 CAN_F8R1_FB22_Msk /*!< Filter bit 22 */ 07611 #define CAN_F8R1_FB23_Pos (23U) 07612 #define CAN_F8R1_FB23_Msk (0x1U << CAN_F8R1_FB23_Pos) /*!< 0x00800000 */ 07613 #define CAN_F8R1_FB23 CAN_F8R1_FB23_Msk /*!< Filter bit 23 */ 07614 #define CAN_F8R1_FB24_Pos (24U) 07615 #define CAN_F8R1_FB24_Msk (0x1U << CAN_F8R1_FB24_Pos) /*!< 0x01000000 */ 07616 #define CAN_F8R1_FB24 CAN_F8R1_FB24_Msk /*!< Filter bit 24 */ 07617 #define CAN_F8R1_FB25_Pos (25U) 07618 #define CAN_F8R1_FB25_Msk (0x1U << CAN_F8R1_FB25_Pos) /*!< 0x02000000 */ 07619 #define CAN_F8R1_FB25 CAN_F8R1_FB25_Msk /*!< Filter bit 25 */ 07620 #define CAN_F8R1_FB26_Pos (26U) 07621 #define CAN_F8R1_FB26_Msk (0x1U << CAN_F8R1_FB26_Pos) /*!< 0x04000000 */ 07622 #define CAN_F8R1_FB26 CAN_F8R1_FB26_Msk /*!< Filter bit 26 */ 07623 #define CAN_F8R1_FB27_Pos (27U) 07624 #define CAN_F8R1_FB27_Msk (0x1U << CAN_F8R1_FB27_Pos) /*!< 0x08000000 */ 07625 #define CAN_F8R1_FB27 CAN_F8R1_FB27_Msk /*!< Filter bit 27 */ 07626 #define CAN_F8R1_FB28_Pos (28U) 07627 #define CAN_F8R1_FB28_Msk (0x1U << CAN_F8R1_FB28_Pos) /*!< 0x10000000 */ 07628 #define CAN_F8R1_FB28 CAN_F8R1_FB28_Msk /*!< Filter bit 28 */ 07629 #define CAN_F8R1_FB29_Pos (29U) 07630 #define CAN_F8R1_FB29_Msk (0x1U << CAN_F8R1_FB29_Pos) /*!< 0x20000000 */ 07631 #define CAN_F8R1_FB29 CAN_F8R1_FB29_Msk /*!< Filter bit 29 */ 07632 #define CAN_F8R1_FB30_Pos (30U) 07633 #define CAN_F8R1_FB30_Msk (0x1U << CAN_F8R1_FB30_Pos) /*!< 0x40000000 */ 07634 #define CAN_F8R1_FB30 CAN_F8R1_FB30_Msk /*!< Filter bit 30 */ 07635 #define CAN_F8R1_FB31_Pos (31U) 07636 #define CAN_F8R1_FB31_Msk (0x1U << CAN_F8R1_FB31_Pos) /*!< 0x80000000 */ 07637 #define CAN_F8R1_FB31 CAN_F8R1_FB31_Msk /*!< Filter bit 31 */ 07638 07639 /******************* Bit definition for CAN_F9R1 register *******************/ 07640 #define CAN_F9R1_FB0_Pos (0U) 07641 #define CAN_F9R1_FB0_Msk (0x1U << CAN_F9R1_FB0_Pos) /*!< 0x00000001 */ 07642 #define CAN_F9R1_FB0 CAN_F9R1_FB0_Msk /*!< Filter bit 0 */ 07643 #define CAN_F9R1_FB1_Pos (1U) 07644 #define CAN_F9R1_FB1_Msk (0x1U << CAN_F9R1_FB1_Pos) /*!< 0x00000002 */ 07645 #define CAN_F9R1_FB1 CAN_F9R1_FB1_Msk /*!< Filter bit 1 */ 07646 #define CAN_F9R1_FB2_Pos (2U) 07647 #define CAN_F9R1_FB2_Msk (0x1U << CAN_F9R1_FB2_Pos) /*!< 0x00000004 */ 07648 #define CAN_F9R1_FB2 CAN_F9R1_FB2_Msk /*!< Filter bit 2 */ 07649 #define CAN_F9R1_FB3_Pos (3U) 07650 #define CAN_F9R1_FB3_Msk (0x1U << CAN_F9R1_FB3_Pos) /*!< 0x00000008 */ 07651 #define CAN_F9R1_FB3 CAN_F9R1_FB3_Msk /*!< Filter bit 3 */ 07652 #define CAN_F9R1_FB4_Pos (4U) 07653 #define CAN_F9R1_FB4_Msk (0x1U << CAN_F9R1_FB4_Pos) /*!< 0x00000010 */ 07654 #define CAN_F9R1_FB4 CAN_F9R1_FB4_Msk /*!< Filter bit 4 */ 07655 #define CAN_F9R1_FB5_Pos (5U) 07656 #define CAN_F9R1_FB5_Msk (0x1U << CAN_F9R1_FB5_Pos) /*!< 0x00000020 */ 07657 #define CAN_F9R1_FB5 CAN_F9R1_FB5_Msk /*!< Filter bit 5 */ 07658 #define CAN_F9R1_FB6_Pos (6U) 07659 #define CAN_F9R1_FB6_Msk (0x1U << CAN_F9R1_FB6_Pos) /*!< 0x00000040 */ 07660 #define CAN_F9R1_FB6 CAN_F9R1_FB6_Msk /*!< Filter bit 6 */ 07661 #define CAN_F9R1_FB7_Pos (7U) 07662 #define CAN_F9R1_FB7_Msk (0x1U << CAN_F9R1_FB7_Pos) /*!< 0x00000080 */ 07663 #define CAN_F9R1_FB7 CAN_F9R1_FB7_Msk /*!< Filter bit 7 */ 07664 #define CAN_F9R1_FB8_Pos (8U) 07665 #define CAN_F9R1_FB8_Msk (0x1U << CAN_F9R1_FB8_Pos) /*!< 0x00000100 */ 07666 #define CAN_F9R1_FB8 CAN_F9R1_FB8_Msk /*!< Filter bit 8 */ 07667 #define CAN_F9R1_FB9_Pos (9U) 07668 #define CAN_F9R1_FB9_Msk (0x1U << CAN_F9R1_FB9_Pos) /*!< 0x00000200 */ 07669 #define CAN_F9R1_FB9 CAN_F9R1_FB9_Msk /*!< Filter bit 9 */ 07670 #define CAN_F9R1_FB10_Pos (10U) 07671 #define CAN_F9R1_FB10_Msk (0x1U << CAN_F9R1_FB10_Pos) /*!< 0x00000400 */ 07672 #define CAN_F9R1_FB10 CAN_F9R1_FB10_Msk /*!< Filter bit 10 */ 07673 #define CAN_F9R1_FB11_Pos (11U) 07674 #define CAN_F9R1_FB11_Msk (0x1U << CAN_F9R1_FB11_Pos) /*!< 0x00000800 */ 07675 #define CAN_F9R1_FB11 CAN_F9R1_FB11_Msk /*!< Filter bit 11 */ 07676 #define CAN_F9R1_FB12_Pos (12U) 07677 #define CAN_F9R1_FB12_Msk (0x1U << CAN_F9R1_FB12_Pos) /*!< 0x00001000 */ 07678 #define CAN_F9R1_FB12 CAN_F9R1_FB12_Msk /*!< Filter bit 12 */ 07679 #define CAN_F9R1_FB13_Pos (13U) 07680 #define CAN_F9R1_FB13_Msk (0x1U << CAN_F9R1_FB13_Pos) /*!< 0x00002000 */ 07681 #define CAN_F9R1_FB13 CAN_F9R1_FB13_Msk /*!< Filter bit 13 */ 07682 #define CAN_F9R1_FB14_Pos (14U) 07683 #define CAN_F9R1_FB14_Msk (0x1U << CAN_F9R1_FB14_Pos) /*!< 0x00004000 */ 07684 #define CAN_F9R1_FB14 CAN_F9R1_FB14_Msk /*!< Filter bit 14 */ 07685 #define CAN_F9R1_FB15_Pos (15U) 07686 #define CAN_F9R1_FB15_Msk (0x1U << CAN_F9R1_FB15_Pos) /*!< 0x00008000 */ 07687 #define CAN_F9R1_FB15 CAN_F9R1_FB15_Msk /*!< Filter bit 15 */ 07688 #define CAN_F9R1_FB16_Pos (16U) 07689 #define CAN_F9R1_FB16_Msk (0x1U << CAN_F9R1_FB16_Pos) /*!< 0x00010000 */ 07690 #define CAN_F9R1_FB16 CAN_F9R1_FB16_Msk /*!< Filter bit 16 */ 07691 #define CAN_F9R1_FB17_Pos (17U) 07692 #define CAN_F9R1_FB17_Msk (0x1U << CAN_F9R1_FB17_Pos) /*!< 0x00020000 */ 07693 #define CAN_F9R1_FB17 CAN_F9R1_FB17_Msk /*!< Filter bit 17 */ 07694 #define CAN_F9R1_FB18_Pos (18U) 07695 #define CAN_F9R1_FB18_Msk (0x1U << CAN_F9R1_FB18_Pos) /*!< 0x00040000 */ 07696 #define CAN_F9R1_FB18 CAN_F9R1_FB18_Msk /*!< Filter bit 18 */ 07697 #define CAN_F9R1_FB19_Pos (19U) 07698 #define CAN_F9R1_FB19_Msk (0x1U << CAN_F9R1_FB19_Pos) /*!< 0x00080000 */ 07699 #define CAN_F9R1_FB19 CAN_F9R1_FB19_Msk /*!< Filter bit 19 */ 07700 #define CAN_F9R1_FB20_Pos (20U) 07701 #define CAN_F9R1_FB20_Msk (0x1U << CAN_F9R1_FB20_Pos) /*!< 0x00100000 */ 07702 #define CAN_F9R1_FB20 CAN_F9R1_FB20_Msk /*!< Filter bit 20 */ 07703 #define CAN_F9R1_FB21_Pos (21U) 07704 #define CAN_F9R1_FB21_Msk (0x1U << CAN_F9R1_FB21_Pos) /*!< 0x00200000 */ 07705 #define CAN_F9R1_FB21 CAN_F9R1_FB21_Msk /*!< Filter bit 21 */ 07706 #define CAN_F9R1_FB22_Pos (22U) 07707 #define CAN_F9R1_FB22_Msk (0x1U << CAN_F9R1_FB22_Pos) /*!< 0x00400000 */ 07708 #define CAN_F9R1_FB22 CAN_F9R1_FB22_Msk /*!< Filter bit 22 */ 07709 #define CAN_F9R1_FB23_Pos (23U) 07710 #define CAN_F9R1_FB23_Msk (0x1U << CAN_F9R1_FB23_Pos) /*!< 0x00800000 */ 07711 #define CAN_F9R1_FB23 CAN_F9R1_FB23_Msk /*!< Filter bit 23 */ 07712 #define CAN_F9R1_FB24_Pos (24U) 07713 #define CAN_F9R1_FB24_Msk (0x1U << CAN_F9R1_FB24_Pos) /*!< 0x01000000 */ 07714 #define CAN_F9R1_FB24 CAN_F9R1_FB24_Msk /*!< Filter bit 24 */ 07715 #define CAN_F9R1_FB25_Pos (25U) 07716 #define CAN_F9R1_FB25_Msk (0x1U << CAN_F9R1_FB25_Pos) /*!< 0x02000000 */ 07717 #define CAN_F9R1_FB25 CAN_F9R1_FB25_Msk /*!< Filter bit 25 */ 07718 #define CAN_F9R1_FB26_Pos (26U) 07719 #define CAN_F9R1_FB26_Msk (0x1U << CAN_F9R1_FB26_Pos) /*!< 0x04000000 */ 07720 #define CAN_F9R1_FB26 CAN_F9R1_FB26_Msk /*!< Filter bit 26 */ 07721 #define CAN_F9R1_FB27_Pos (27U) 07722 #define CAN_F9R1_FB27_Msk (0x1U << CAN_F9R1_FB27_Pos) /*!< 0x08000000 */ 07723 #define CAN_F9R1_FB27 CAN_F9R1_FB27_Msk /*!< Filter bit 27 */ 07724 #define CAN_F9R1_FB28_Pos (28U) 07725 #define CAN_F9R1_FB28_Msk (0x1U << CAN_F9R1_FB28_Pos) /*!< 0x10000000 */ 07726 #define CAN_F9R1_FB28 CAN_F9R1_FB28_Msk /*!< Filter bit 28 */ 07727 #define CAN_F9R1_FB29_Pos (29U) 07728 #define CAN_F9R1_FB29_Msk (0x1U << CAN_F9R1_FB29_Pos) /*!< 0x20000000 */ 07729 #define CAN_F9R1_FB29 CAN_F9R1_FB29_Msk /*!< Filter bit 29 */ 07730 #define CAN_F9R1_FB30_Pos (30U) 07731 #define CAN_F9R1_FB30_Msk (0x1U << CAN_F9R1_FB30_Pos) /*!< 0x40000000 */ 07732 #define CAN_F9R1_FB30 CAN_F9R1_FB30_Msk /*!< Filter bit 30 */ 07733 #define CAN_F9R1_FB31_Pos (31U) 07734 #define CAN_F9R1_FB31_Msk (0x1U << CAN_F9R1_FB31_Pos) /*!< 0x80000000 */ 07735 #define CAN_F9R1_FB31 CAN_F9R1_FB31_Msk /*!< Filter bit 31 */ 07736 07737 /******************* Bit definition for CAN_F10R1 register ******************/ 07738 #define CAN_F10R1_FB0_Pos (0U) 07739 #define CAN_F10R1_FB0_Msk (0x1U << CAN_F10R1_FB0_Pos) /*!< 0x00000001 */ 07740 #define CAN_F10R1_FB0 CAN_F10R1_FB0_Msk /*!< Filter bit 0 */ 07741 #define CAN_F10R1_FB1_Pos (1U) 07742 #define CAN_F10R1_FB1_Msk (0x1U << CAN_F10R1_FB1_Pos) /*!< 0x00000002 */ 07743 #define CAN_F10R1_FB1 CAN_F10R1_FB1_Msk /*!< Filter bit 1 */ 07744 #define CAN_F10R1_FB2_Pos (2U) 07745 #define CAN_F10R1_FB2_Msk (0x1U << CAN_F10R1_FB2_Pos) /*!< 0x00000004 */ 07746 #define CAN_F10R1_FB2 CAN_F10R1_FB2_Msk /*!< Filter bit 2 */ 07747 #define CAN_F10R1_FB3_Pos (3U) 07748 #define CAN_F10R1_FB3_Msk (0x1U << CAN_F10R1_FB3_Pos) /*!< 0x00000008 */ 07749 #define CAN_F10R1_FB3 CAN_F10R1_FB3_Msk /*!< Filter bit 3 */ 07750 #define CAN_F10R1_FB4_Pos (4U) 07751 #define CAN_F10R1_FB4_Msk (0x1U << CAN_F10R1_FB4_Pos) /*!< 0x00000010 */ 07752 #define CAN_F10R1_FB4 CAN_F10R1_FB4_Msk /*!< Filter bit 4 */ 07753 #define CAN_F10R1_FB5_Pos (5U) 07754 #define CAN_F10R1_FB5_Msk (0x1U << CAN_F10R1_FB5_Pos) /*!< 0x00000020 */ 07755 #define CAN_F10R1_FB5 CAN_F10R1_FB5_Msk /*!< Filter bit 5 */ 07756 #define CAN_F10R1_FB6_Pos (6U) 07757 #define CAN_F10R1_FB6_Msk (0x1U << CAN_F10R1_FB6_Pos) /*!< 0x00000040 */ 07758 #define CAN_F10R1_FB6 CAN_F10R1_FB6_Msk /*!< Filter bit 6 */ 07759 #define CAN_F10R1_FB7_Pos (7U) 07760 #define CAN_F10R1_FB7_Msk (0x1U << CAN_F10R1_FB7_Pos) /*!< 0x00000080 */ 07761 #define CAN_F10R1_FB7 CAN_F10R1_FB7_Msk /*!< Filter bit 7 */ 07762 #define CAN_F10R1_FB8_Pos (8U) 07763 #define CAN_F10R1_FB8_Msk (0x1U << CAN_F10R1_FB8_Pos) /*!< 0x00000100 */ 07764 #define CAN_F10R1_FB8 CAN_F10R1_FB8_Msk /*!< Filter bit 8 */ 07765 #define CAN_F10R1_FB9_Pos (9U) 07766 #define CAN_F10R1_FB9_Msk (0x1U << CAN_F10R1_FB9_Pos) /*!< 0x00000200 */ 07767 #define CAN_F10R1_FB9 CAN_F10R1_FB9_Msk /*!< Filter bit 9 */ 07768 #define CAN_F10R1_FB10_Pos (10U) 07769 #define CAN_F10R1_FB10_Msk (0x1U << CAN_F10R1_FB10_Pos) /*!< 0x00000400 */ 07770 #define CAN_F10R1_FB10 CAN_F10R1_FB10_Msk /*!< Filter bit 10 */ 07771 #define CAN_F10R1_FB11_Pos (11U) 07772 #define CAN_F10R1_FB11_Msk (0x1U << CAN_F10R1_FB11_Pos) /*!< 0x00000800 */ 07773 #define CAN_F10R1_FB11 CAN_F10R1_FB11_Msk /*!< Filter bit 11 */ 07774 #define CAN_F10R1_FB12_Pos (12U) 07775 #define CAN_F10R1_FB12_Msk (0x1U << CAN_F10R1_FB12_Pos) /*!< 0x00001000 */ 07776 #define CAN_F10R1_FB12 CAN_F10R1_FB12_Msk /*!< Filter bit 12 */ 07777 #define CAN_F10R1_FB13_Pos (13U) 07778 #define CAN_F10R1_FB13_Msk (0x1U << CAN_F10R1_FB13_Pos) /*!< 0x00002000 */ 07779 #define CAN_F10R1_FB13 CAN_F10R1_FB13_Msk /*!< Filter bit 13 */ 07780 #define CAN_F10R1_FB14_Pos (14U) 07781 #define CAN_F10R1_FB14_Msk (0x1U << CAN_F10R1_FB14_Pos) /*!< 0x00004000 */ 07782 #define CAN_F10R1_FB14 CAN_F10R1_FB14_Msk /*!< Filter bit 14 */ 07783 #define CAN_F10R1_FB15_Pos (15U) 07784 #define CAN_F10R1_FB15_Msk (0x1U << CAN_F10R1_FB15_Pos) /*!< 0x00008000 */ 07785 #define CAN_F10R1_FB15 CAN_F10R1_FB15_Msk /*!< Filter bit 15 */ 07786 #define CAN_F10R1_FB16_Pos (16U) 07787 #define CAN_F10R1_FB16_Msk (0x1U << CAN_F10R1_FB16_Pos) /*!< 0x00010000 */ 07788 #define CAN_F10R1_FB16 CAN_F10R1_FB16_Msk /*!< Filter bit 16 */ 07789 #define CAN_F10R1_FB17_Pos (17U) 07790 #define CAN_F10R1_FB17_Msk (0x1U << CAN_F10R1_FB17_Pos) /*!< 0x00020000 */ 07791 #define CAN_F10R1_FB17 CAN_F10R1_FB17_Msk /*!< Filter bit 17 */ 07792 #define CAN_F10R1_FB18_Pos (18U) 07793 #define CAN_F10R1_FB18_Msk (0x1U << CAN_F10R1_FB18_Pos) /*!< 0x00040000 */ 07794 #define CAN_F10R1_FB18 CAN_F10R1_FB18_Msk /*!< Filter bit 18 */ 07795 #define CAN_F10R1_FB19_Pos (19U) 07796 #define CAN_F10R1_FB19_Msk (0x1U << CAN_F10R1_FB19_Pos) /*!< 0x00080000 */ 07797 #define CAN_F10R1_FB19 CAN_F10R1_FB19_Msk /*!< Filter bit 19 */ 07798 #define CAN_F10R1_FB20_Pos (20U) 07799 #define CAN_F10R1_FB20_Msk (0x1U << CAN_F10R1_FB20_Pos) /*!< 0x00100000 */ 07800 #define CAN_F10R1_FB20 CAN_F10R1_FB20_Msk /*!< Filter bit 20 */ 07801 #define CAN_F10R1_FB21_Pos (21U) 07802 #define CAN_F10R1_FB21_Msk (0x1U << CAN_F10R1_FB21_Pos) /*!< 0x00200000 */ 07803 #define CAN_F10R1_FB21 CAN_F10R1_FB21_Msk /*!< Filter bit 21 */ 07804 #define CAN_F10R1_FB22_Pos (22U) 07805 #define CAN_F10R1_FB22_Msk (0x1U << CAN_F10R1_FB22_Pos) /*!< 0x00400000 */ 07806 #define CAN_F10R1_FB22 CAN_F10R1_FB22_Msk /*!< Filter bit 22 */ 07807 #define CAN_F10R1_FB23_Pos (23U) 07808 #define CAN_F10R1_FB23_Msk (0x1U << CAN_F10R1_FB23_Pos) /*!< 0x00800000 */ 07809 #define CAN_F10R1_FB23 CAN_F10R1_FB23_Msk /*!< Filter bit 23 */ 07810 #define CAN_F10R1_FB24_Pos (24U) 07811 #define CAN_F10R1_FB24_Msk (0x1U << CAN_F10R1_FB24_Pos) /*!< 0x01000000 */ 07812 #define CAN_F10R1_FB24 CAN_F10R1_FB24_Msk /*!< Filter bit 24 */ 07813 #define CAN_F10R1_FB25_Pos (25U) 07814 #define CAN_F10R1_FB25_Msk (0x1U << CAN_F10R1_FB25_Pos) /*!< 0x02000000 */ 07815 #define CAN_F10R1_FB25 CAN_F10R1_FB25_Msk /*!< Filter bit 25 */ 07816 #define CAN_F10R1_FB26_Pos (26U) 07817 #define CAN_F10R1_FB26_Msk (0x1U << CAN_F10R1_FB26_Pos) /*!< 0x04000000 */ 07818 #define CAN_F10R1_FB26 CAN_F10R1_FB26_Msk /*!< Filter bit 26 */ 07819 #define CAN_F10R1_FB27_Pos (27U) 07820 #define CAN_F10R1_FB27_Msk (0x1U << CAN_F10R1_FB27_Pos) /*!< 0x08000000 */ 07821 #define CAN_F10R1_FB27 CAN_F10R1_FB27_Msk /*!< Filter bit 27 */ 07822 #define CAN_F10R1_FB28_Pos (28U) 07823 #define CAN_F10R1_FB28_Msk (0x1U << CAN_F10R1_FB28_Pos) /*!< 0x10000000 */ 07824 #define CAN_F10R1_FB28 CAN_F10R1_FB28_Msk /*!< Filter bit 28 */ 07825 #define CAN_F10R1_FB29_Pos (29U) 07826 #define CAN_F10R1_FB29_Msk (0x1U << CAN_F10R1_FB29_Pos) /*!< 0x20000000 */ 07827 #define CAN_F10R1_FB29 CAN_F10R1_FB29_Msk /*!< Filter bit 29 */ 07828 #define CAN_F10R1_FB30_Pos (30U) 07829 #define CAN_F10R1_FB30_Msk (0x1U << CAN_F10R1_FB30_Pos) /*!< 0x40000000 */ 07830 #define CAN_F10R1_FB30 CAN_F10R1_FB30_Msk /*!< Filter bit 30 */ 07831 #define CAN_F10R1_FB31_Pos (31U) 07832 #define CAN_F10R1_FB31_Msk (0x1U << CAN_F10R1_FB31_Pos) /*!< 0x80000000 */ 07833 #define CAN_F10R1_FB31 CAN_F10R1_FB31_Msk /*!< Filter bit 31 */ 07834 07835 /******************* Bit definition for CAN_F11R1 register ******************/ 07836 #define CAN_F11R1_FB0_Pos (0U) 07837 #define CAN_F11R1_FB0_Msk (0x1U << CAN_F11R1_FB0_Pos) /*!< 0x00000001 */ 07838 #define CAN_F11R1_FB0 CAN_F11R1_FB0_Msk /*!< Filter bit 0 */ 07839 #define CAN_F11R1_FB1_Pos (1U) 07840 #define CAN_F11R1_FB1_Msk (0x1U << CAN_F11R1_FB1_Pos) /*!< 0x00000002 */ 07841 #define CAN_F11R1_FB1 CAN_F11R1_FB1_Msk /*!< Filter bit 1 */ 07842 #define CAN_F11R1_FB2_Pos (2U) 07843 #define CAN_F11R1_FB2_Msk (0x1U << CAN_F11R1_FB2_Pos) /*!< 0x00000004 */ 07844 #define CAN_F11R1_FB2 CAN_F11R1_FB2_Msk /*!< Filter bit 2 */ 07845 #define CAN_F11R1_FB3_Pos (3U) 07846 #define CAN_F11R1_FB3_Msk (0x1U << CAN_F11R1_FB3_Pos) /*!< 0x00000008 */ 07847 #define CAN_F11R1_FB3 CAN_F11R1_FB3_Msk /*!< Filter bit 3 */ 07848 #define CAN_F11R1_FB4_Pos (4U) 07849 #define CAN_F11R1_FB4_Msk (0x1U << CAN_F11R1_FB4_Pos) /*!< 0x00000010 */ 07850 #define CAN_F11R1_FB4 CAN_F11R1_FB4_Msk /*!< Filter bit 4 */ 07851 #define CAN_F11R1_FB5_Pos (5U) 07852 #define CAN_F11R1_FB5_Msk (0x1U << CAN_F11R1_FB5_Pos) /*!< 0x00000020 */ 07853 #define CAN_F11R1_FB5 CAN_F11R1_FB5_Msk /*!< Filter bit 5 */ 07854 #define CAN_F11R1_FB6_Pos (6U) 07855 #define CAN_F11R1_FB6_Msk (0x1U << CAN_F11R1_FB6_Pos) /*!< 0x00000040 */ 07856 #define CAN_F11R1_FB6 CAN_F11R1_FB6_Msk /*!< Filter bit 6 */ 07857 #define CAN_F11R1_FB7_Pos (7U) 07858 #define CAN_F11R1_FB7_Msk (0x1U << CAN_F11R1_FB7_Pos) /*!< 0x00000080 */ 07859 #define CAN_F11R1_FB7 CAN_F11R1_FB7_Msk /*!< Filter bit 7 */ 07860 #define CAN_F11R1_FB8_Pos (8U) 07861 #define CAN_F11R1_FB8_Msk (0x1U << CAN_F11R1_FB8_Pos) /*!< 0x00000100 */ 07862 #define CAN_F11R1_FB8 CAN_F11R1_FB8_Msk /*!< Filter bit 8 */ 07863 #define CAN_F11R1_FB9_Pos (9U) 07864 #define CAN_F11R1_FB9_Msk (0x1U << CAN_F11R1_FB9_Pos) /*!< 0x00000200 */ 07865 #define CAN_F11R1_FB9 CAN_F11R1_FB9_Msk /*!< Filter bit 9 */ 07866 #define CAN_F11R1_FB10_Pos (10U) 07867 #define CAN_F11R1_FB10_Msk (0x1U << CAN_F11R1_FB10_Pos) /*!< 0x00000400 */ 07868 #define CAN_F11R1_FB10 CAN_F11R1_FB10_Msk /*!< Filter bit 10 */ 07869 #define CAN_F11R1_FB11_Pos (11U) 07870 #define CAN_F11R1_FB11_Msk (0x1U << CAN_F11R1_FB11_Pos) /*!< 0x00000800 */ 07871 #define CAN_F11R1_FB11 CAN_F11R1_FB11_Msk /*!< Filter bit 11 */ 07872 #define CAN_F11R1_FB12_Pos (12U) 07873 #define CAN_F11R1_FB12_Msk (0x1U << CAN_F11R1_FB12_Pos) /*!< 0x00001000 */ 07874 #define CAN_F11R1_FB12 CAN_F11R1_FB12_Msk /*!< Filter bit 12 */ 07875 #define CAN_F11R1_FB13_Pos (13U) 07876 #define CAN_F11R1_FB13_Msk (0x1U << CAN_F11R1_FB13_Pos) /*!< 0x00002000 */ 07877 #define CAN_F11R1_FB13 CAN_F11R1_FB13_Msk /*!< Filter bit 13 */ 07878 #define CAN_F11R1_FB14_Pos (14U) 07879 #define CAN_F11R1_FB14_Msk (0x1U << CAN_F11R1_FB14_Pos) /*!< 0x00004000 */ 07880 #define CAN_F11R1_FB14 CAN_F11R1_FB14_Msk /*!< Filter bit 14 */ 07881 #define CAN_F11R1_FB15_Pos (15U) 07882 #define CAN_F11R1_FB15_Msk (0x1U << CAN_F11R1_FB15_Pos) /*!< 0x00008000 */ 07883 #define CAN_F11R1_FB15 CAN_F11R1_FB15_Msk /*!< Filter bit 15 */ 07884 #define CAN_F11R1_FB16_Pos (16U) 07885 #define CAN_F11R1_FB16_Msk (0x1U << CAN_F11R1_FB16_Pos) /*!< 0x00010000 */ 07886 #define CAN_F11R1_FB16 CAN_F11R1_FB16_Msk /*!< Filter bit 16 */ 07887 #define CAN_F11R1_FB17_Pos (17U) 07888 #define CAN_F11R1_FB17_Msk (0x1U << CAN_F11R1_FB17_Pos) /*!< 0x00020000 */ 07889 #define CAN_F11R1_FB17 CAN_F11R1_FB17_Msk /*!< Filter bit 17 */ 07890 #define CAN_F11R1_FB18_Pos (18U) 07891 #define CAN_F11R1_FB18_Msk (0x1U << CAN_F11R1_FB18_Pos) /*!< 0x00040000 */ 07892 #define CAN_F11R1_FB18 CAN_F11R1_FB18_Msk /*!< Filter bit 18 */ 07893 #define CAN_F11R1_FB19_Pos (19U) 07894 #define CAN_F11R1_FB19_Msk (0x1U << CAN_F11R1_FB19_Pos) /*!< 0x00080000 */ 07895 #define CAN_F11R1_FB19 CAN_F11R1_FB19_Msk /*!< Filter bit 19 */ 07896 #define CAN_F11R1_FB20_Pos (20U) 07897 #define CAN_F11R1_FB20_Msk (0x1U << CAN_F11R1_FB20_Pos) /*!< 0x00100000 */ 07898 #define CAN_F11R1_FB20 CAN_F11R1_FB20_Msk /*!< Filter bit 20 */ 07899 #define CAN_F11R1_FB21_Pos (21U) 07900 #define CAN_F11R1_FB21_Msk (0x1U << CAN_F11R1_FB21_Pos) /*!< 0x00200000 */ 07901 #define CAN_F11R1_FB21 CAN_F11R1_FB21_Msk /*!< Filter bit 21 */ 07902 #define CAN_F11R1_FB22_Pos (22U) 07903 #define CAN_F11R1_FB22_Msk (0x1U << CAN_F11R1_FB22_Pos) /*!< 0x00400000 */ 07904 #define CAN_F11R1_FB22 CAN_F11R1_FB22_Msk /*!< Filter bit 22 */ 07905 #define CAN_F11R1_FB23_Pos (23U) 07906 #define CAN_F11R1_FB23_Msk (0x1U << CAN_F11R1_FB23_Pos) /*!< 0x00800000 */ 07907 #define CAN_F11R1_FB23 CAN_F11R1_FB23_Msk /*!< Filter bit 23 */ 07908 #define CAN_F11R1_FB24_Pos (24U) 07909 #define CAN_F11R1_FB24_Msk (0x1U << CAN_F11R1_FB24_Pos) /*!< 0x01000000 */ 07910 #define CAN_F11R1_FB24 CAN_F11R1_FB24_Msk /*!< Filter bit 24 */ 07911 #define CAN_F11R1_FB25_Pos (25U) 07912 #define CAN_F11R1_FB25_Msk (0x1U << CAN_F11R1_FB25_Pos) /*!< 0x02000000 */ 07913 #define CAN_F11R1_FB25 CAN_F11R1_FB25_Msk /*!< Filter bit 25 */ 07914 #define CAN_F11R1_FB26_Pos (26U) 07915 #define CAN_F11R1_FB26_Msk (0x1U << CAN_F11R1_FB26_Pos) /*!< 0x04000000 */ 07916 #define CAN_F11R1_FB26 CAN_F11R1_FB26_Msk /*!< Filter bit 26 */ 07917 #define CAN_F11R1_FB27_Pos (27U) 07918 #define CAN_F11R1_FB27_Msk (0x1U << CAN_F11R1_FB27_Pos) /*!< 0x08000000 */ 07919 #define CAN_F11R1_FB27 CAN_F11R1_FB27_Msk /*!< Filter bit 27 */ 07920 #define CAN_F11R1_FB28_Pos (28U) 07921 #define CAN_F11R1_FB28_Msk (0x1U << CAN_F11R1_FB28_Pos) /*!< 0x10000000 */ 07922 #define CAN_F11R1_FB28 CAN_F11R1_FB28_Msk /*!< Filter bit 28 */ 07923 #define CAN_F11R1_FB29_Pos (29U) 07924 #define CAN_F11R1_FB29_Msk (0x1U << CAN_F11R1_FB29_Pos) /*!< 0x20000000 */ 07925 #define CAN_F11R1_FB29 CAN_F11R1_FB29_Msk /*!< Filter bit 29 */ 07926 #define CAN_F11R1_FB30_Pos (30U) 07927 #define CAN_F11R1_FB30_Msk (0x1U << CAN_F11R1_FB30_Pos) /*!< 0x40000000 */ 07928 #define CAN_F11R1_FB30 CAN_F11R1_FB30_Msk /*!< Filter bit 30 */ 07929 #define CAN_F11R1_FB31_Pos (31U) 07930 #define CAN_F11R1_FB31_Msk (0x1U << CAN_F11R1_FB31_Pos) /*!< 0x80000000 */ 07931 #define CAN_F11R1_FB31 CAN_F11R1_FB31_Msk /*!< Filter bit 31 */ 07932 07933 /******************* Bit definition for CAN_F12R1 register ******************/ 07934 #define CAN_F12R1_FB0_Pos (0U) 07935 #define CAN_F12R1_FB0_Msk (0x1U << CAN_F12R1_FB0_Pos) /*!< 0x00000001 */ 07936 #define CAN_F12R1_FB0 CAN_F12R1_FB0_Msk /*!< Filter bit 0 */ 07937 #define CAN_F12R1_FB1_Pos (1U) 07938 #define CAN_F12R1_FB1_Msk (0x1U << CAN_F12R1_FB1_Pos) /*!< 0x00000002 */ 07939 #define CAN_F12R1_FB1 CAN_F12R1_FB1_Msk /*!< Filter bit 1 */ 07940 #define CAN_F12R1_FB2_Pos (2U) 07941 #define CAN_F12R1_FB2_Msk (0x1U << CAN_F12R1_FB2_Pos) /*!< 0x00000004 */ 07942 #define CAN_F12R1_FB2 CAN_F12R1_FB2_Msk /*!< Filter bit 2 */ 07943 #define CAN_F12R1_FB3_Pos (3U) 07944 #define CAN_F12R1_FB3_Msk (0x1U << CAN_F12R1_FB3_Pos) /*!< 0x00000008 */ 07945 #define CAN_F12R1_FB3 CAN_F12R1_FB3_Msk /*!< Filter bit 3 */ 07946 #define CAN_F12R1_FB4_Pos (4U) 07947 #define CAN_F12R1_FB4_Msk (0x1U << CAN_F12R1_FB4_Pos) /*!< 0x00000010 */ 07948 #define CAN_F12R1_FB4 CAN_F12R1_FB4_Msk /*!< Filter bit 4 */ 07949 #define CAN_F12R1_FB5_Pos (5U) 07950 #define CAN_F12R1_FB5_Msk (0x1U << CAN_F12R1_FB5_Pos) /*!< 0x00000020 */ 07951 #define CAN_F12R1_FB5 CAN_F12R1_FB5_Msk /*!< Filter bit 5 */ 07952 #define CAN_F12R1_FB6_Pos (6U) 07953 #define CAN_F12R1_FB6_Msk (0x1U << CAN_F12R1_FB6_Pos) /*!< 0x00000040 */ 07954 #define CAN_F12R1_FB6 CAN_F12R1_FB6_Msk /*!< Filter bit 6 */ 07955 #define CAN_F12R1_FB7_Pos (7U) 07956 #define CAN_F12R1_FB7_Msk (0x1U << CAN_F12R1_FB7_Pos) /*!< 0x00000080 */ 07957 #define CAN_F12R1_FB7 CAN_F12R1_FB7_Msk /*!< Filter bit 7 */ 07958 #define CAN_F12R1_FB8_Pos (8U) 07959 #define CAN_F12R1_FB8_Msk (0x1U << CAN_F12R1_FB8_Pos) /*!< 0x00000100 */ 07960 #define CAN_F12R1_FB8 CAN_F12R1_FB8_Msk /*!< Filter bit 8 */ 07961 #define CAN_F12R1_FB9_Pos (9U) 07962 #define CAN_F12R1_FB9_Msk (0x1U << CAN_F12R1_FB9_Pos) /*!< 0x00000200 */ 07963 #define CAN_F12R1_FB9 CAN_F12R1_FB9_Msk /*!< Filter bit 9 */ 07964 #define CAN_F12R1_FB10_Pos (10U) 07965 #define CAN_F12R1_FB10_Msk (0x1U << CAN_F12R1_FB10_Pos) /*!< 0x00000400 */ 07966 #define CAN_F12R1_FB10 CAN_F12R1_FB10_Msk /*!< Filter bit 10 */ 07967 #define CAN_F12R1_FB11_Pos (11U) 07968 #define CAN_F12R1_FB11_Msk (0x1U << CAN_F12R1_FB11_Pos) /*!< 0x00000800 */ 07969 #define CAN_F12R1_FB11 CAN_F12R1_FB11_Msk /*!< Filter bit 11 */ 07970 #define CAN_F12R1_FB12_Pos (12U) 07971 #define CAN_F12R1_FB12_Msk (0x1U << CAN_F12R1_FB12_Pos) /*!< 0x00001000 */ 07972 #define CAN_F12R1_FB12 CAN_F12R1_FB12_Msk /*!< Filter bit 12 */ 07973 #define CAN_F12R1_FB13_Pos (13U) 07974 #define CAN_F12R1_FB13_Msk (0x1U << CAN_F12R1_FB13_Pos) /*!< 0x00002000 */ 07975 #define CAN_F12R1_FB13 CAN_F12R1_FB13_Msk /*!< Filter bit 13 */ 07976 #define CAN_F12R1_FB14_Pos (14U) 07977 #define CAN_F12R1_FB14_Msk (0x1U << CAN_F12R1_FB14_Pos) /*!< 0x00004000 */ 07978 #define CAN_F12R1_FB14 CAN_F12R1_FB14_Msk /*!< Filter bit 14 */ 07979 #define CAN_F12R1_FB15_Pos (15U) 07980 #define CAN_F12R1_FB15_Msk (0x1U << CAN_F12R1_FB15_Pos) /*!< 0x00008000 */ 07981 #define CAN_F12R1_FB15 CAN_F12R1_FB15_Msk /*!< Filter bit 15 */ 07982 #define CAN_F12R1_FB16_Pos (16U) 07983 #define CAN_F12R1_FB16_Msk (0x1U << CAN_F12R1_FB16_Pos) /*!< 0x00010000 */ 07984 #define CAN_F12R1_FB16 CAN_F12R1_FB16_Msk /*!< Filter bit 16 */ 07985 #define CAN_F12R1_FB17_Pos (17U) 07986 #define CAN_F12R1_FB17_Msk (0x1U << CAN_F12R1_FB17_Pos) /*!< 0x00020000 */ 07987 #define CAN_F12R1_FB17 CAN_F12R1_FB17_Msk /*!< Filter bit 17 */ 07988 #define CAN_F12R1_FB18_Pos (18U) 07989 #define CAN_F12R1_FB18_Msk (0x1U << CAN_F12R1_FB18_Pos) /*!< 0x00040000 */ 07990 #define CAN_F12R1_FB18 CAN_F12R1_FB18_Msk /*!< Filter bit 18 */ 07991 #define CAN_F12R1_FB19_Pos (19U) 07992 #define CAN_F12R1_FB19_Msk (0x1U << CAN_F12R1_FB19_Pos) /*!< 0x00080000 */ 07993 #define CAN_F12R1_FB19 CAN_F12R1_FB19_Msk /*!< Filter bit 19 */ 07994 #define CAN_F12R1_FB20_Pos (20U) 07995 #define CAN_F12R1_FB20_Msk (0x1U << CAN_F12R1_FB20_Pos) /*!< 0x00100000 */ 07996 #define CAN_F12R1_FB20 CAN_F12R1_FB20_Msk /*!< Filter bit 20 */ 07997 #define CAN_F12R1_FB21_Pos (21U) 07998 #define CAN_F12R1_FB21_Msk (0x1U << CAN_F12R1_FB21_Pos) /*!< 0x00200000 */ 07999 #define CAN_F12R1_FB21 CAN_F12R1_FB21_Msk /*!< Filter bit 21 */ 08000 #define CAN_F12R1_FB22_Pos (22U) 08001 #define CAN_F12R1_FB22_Msk (0x1U << CAN_F12R1_FB22_Pos) /*!< 0x00400000 */ 08002 #define CAN_F12R1_FB22 CAN_F12R1_FB22_Msk /*!< Filter bit 22 */ 08003 #define CAN_F12R1_FB23_Pos (23U) 08004 #define CAN_F12R1_FB23_Msk (0x1U << CAN_F12R1_FB23_Pos) /*!< 0x00800000 */ 08005 #define CAN_F12R1_FB23 CAN_F12R1_FB23_Msk /*!< Filter bit 23 */ 08006 #define CAN_F12R1_FB24_Pos (24U) 08007 #define CAN_F12R1_FB24_Msk (0x1U << CAN_F12R1_FB24_Pos) /*!< 0x01000000 */ 08008 #define CAN_F12R1_FB24 CAN_F12R1_FB24_Msk /*!< Filter bit 24 */ 08009 #define CAN_F12R1_FB25_Pos (25U) 08010 #define CAN_F12R1_FB25_Msk (0x1U << CAN_F12R1_FB25_Pos) /*!< 0x02000000 */ 08011 #define CAN_F12R1_FB25 CAN_F12R1_FB25_Msk /*!< Filter bit 25 */ 08012 #define CAN_F12R1_FB26_Pos (26U) 08013 #define CAN_F12R1_FB26_Msk (0x1U << CAN_F12R1_FB26_Pos) /*!< 0x04000000 */ 08014 #define CAN_F12R1_FB26 CAN_F12R1_FB26_Msk /*!< Filter bit 26 */ 08015 #define CAN_F12R1_FB27_Pos (27U) 08016 #define CAN_F12R1_FB27_Msk (0x1U << CAN_F12R1_FB27_Pos) /*!< 0x08000000 */ 08017 #define CAN_F12R1_FB27 CAN_F12R1_FB27_Msk /*!< Filter bit 27 */ 08018 #define CAN_F12R1_FB28_Pos (28U) 08019 #define CAN_F12R1_FB28_Msk (0x1U << CAN_F12R1_FB28_Pos) /*!< 0x10000000 */ 08020 #define CAN_F12R1_FB28 CAN_F12R1_FB28_Msk /*!< Filter bit 28 */ 08021 #define CAN_F12R1_FB29_Pos (29U) 08022 #define CAN_F12R1_FB29_Msk (0x1U << CAN_F12R1_FB29_Pos) /*!< 0x20000000 */ 08023 #define CAN_F12R1_FB29 CAN_F12R1_FB29_Msk /*!< Filter bit 29 */ 08024 #define CAN_F12R1_FB30_Pos (30U) 08025 #define CAN_F12R1_FB30_Msk (0x1U << CAN_F12R1_FB30_Pos) /*!< 0x40000000 */ 08026 #define CAN_F12R1_FB30 CAN_F12R1_FB30_Msk /*!< Filter bit 30 */ 08027 #define CAN_F12R1_FB31_Pos (31U) 08028 #define CAN_F12R1_FB31_Msk (0x1U << CAN_F12R1_FB31_Pos) /*!< 0x80000000 */ 08029 #define CAN_F12R1_FB31 CAN_F12R1_FB31_Msk /*!< Filter bit 31 */ 08030 08031 /******************* Bit definition for CAN_F13R1 register ******************/ 08032 #define CAN_F13R1_FB0_Pos (0U) 08033 #define CAN_F13R1_FB0_Msk (0x1U << CAN_F13R1_FB0_Pos) /*!< 0x00000001 */ 08034 #define CAN_F13R1_FB0 CAN_F13R1_FB0_Msk /*!< Filter bit 0 */ 08035 #define CAN_F13R1_FB1_Pos (1U) 08036 #define CAN_F13R1_FB1_Msk (0x1U << CAN_F13R1_FB1_Pos) /*!< 0x00000002 */ 08037 #define CAN_F13R1_FB1 CAN_F13R1_FB1_Msk /*!< Filter bit 1 */ 08038 #define CAN_F13R1_FB2_Pos (2U) 08039 #define CAN_F13R1_FB2_Msk (0x1U << CAN_F13R1_FB2_Pos) /*!< 0x00000004 */ 08040 #define CAN_F13R1_FB2 CAN_F13R1_FB2_Msk /*!< Filter bit 2 */ 08041 #define CAN_F13R1_FB3_Pos (3U) 08042 #define CAN_F13R1_FB3_Msk (0x1U << CAN_F13R1_FB3_Pos) /*!< 0x00000008 */ 08043 #define CAN_F13R1_FB3 CAN_F13R1_FB3_Msk /*!< Filter bit 3 */ 08044 #define CAN_F13R1_FB4_Pos (4U) 08045 #define CAN_F13R1_FB4_Msk (0x1U << CAN_F13R1_FB4_Pos) /*!< 0x00000010 */ 08046 #define CAN_F13R1_FB4 CAN_F13R1_FB4_Msk /*!< Filter bit 4 */ 08047 #define CAN_F13R1_FB5_Pos (5U) 08048 #define CAN_F13R1_FB5_Msk (0x1U << CAN_F13R1_FB5_Pos) /*!< 0x00000020 */ 08049 #define CAN_F13R1_FB5 CAN_F13R1_FB5_Msk /*!< Filter bit 5 */ 08050 #define CAN_F13R1_FB6_Pos (6U) 08051 #define CAN_F13R1_FB6_Msk (0x1U << CAN_F13R1_FB6_Pos) /*!< 0x00000040 */ 08052 #define CAN_F13R1_FB6 CAN_F13R1_FB6_Msk /*!< Filter bit 6 */ 08053 #define CAN_F13R1_FB7_Pos (7U) 08054 #define CAN_F13R1_FB7_Msk (0x1U << CAN_F13R1_FB7_Pos) /*!< 0x00000080 */ 08055 #define CAN_F13R1_FB7 CAN_F13R1_FB7_Msk /*!< Filter bit 7 */ 08056 #define CAN_F13R1_FB8_Pos (8U) 08057 #define CAN_F13R1_FB8_Msk (0x1U << CAN_F13R1_FB8_Pos) /*!< 0x00000100 */ 08058 #define CAN_F13R1_FB8 CAN_F13R1_FB8_Msk /*!< Filter bit 8 */ 08059 #define CAN_F13R1_FB9_Pos (9U) 08060 #define CAN_F13R1_FB9_Msk (0x1U << CAN_F13R1_FB9_Pos) /*!< 0x00000200 */ 08061 #define CAN_F13R1_FB9 CAN_F13R1_FB9_Msk /*!< Filter bit 9 */ 08062 #define CAN_F13R1_FB10_Pos (10U) 08063 #define CAN_F13R1_FB10_Msk (0x1U << CAN_F13R1_FB10_Pos) /*!< 0x00000400 */ 08064 #define CAN_F13R1_FB10 CAN_F13R1_FB10_Msk /*!< Filter bit 10 */ 08065 #define CAN_F13R1_FB11_Pos (11U) 08066 #define CAN_F13R1_FB11_Msk (0x1U << CAN_F13R1_FB11_Pos) /*!< 0x00000800 */ 08067 #define CAN_F13R1_FB11 CAN_F13R1_FB11_Msk /*!< Filter bit 11 */ 08068 #define CAN_F13R1_FB12_Pos (12U) 08069 #define CAN_F13R1_FB12_Msk (0x1U << CAN_F13R1_FB12_Pos) /*!< 0x00001000 */ 08070 #define CAN_F13R1_FB12 CAN_F13R1_FB12_Msk /*!< Filter bit 12 */ 08071 #define CAN_F13R1_FB13_Pos (13U) 08072 #define CAN_F13R1_FB13_Msk (0x1U << CAN_F13R1_FB13_Pos) /*!< 0x00002000 */ 08073 #define CAN_F13R1_FB13 CAN_F13R1_FB13_Msk /*!< Filter bit 13 */ 08074 #define CAN_F13R1_FB14_Pos (14U) 08075 #define CAN_F13R1_FB14_Msk (0x1U << CAN_F13R1_FB14_Pos) /*!< 0x00004000 */ 08076 #define CAN_F13R1_FB14 CAN_F13R1_FB14_Msk /*!< Filter bit 14 */ 08077 #define CAN_F13R1_FB15_Pos (15U) 08078 #define CAN_F13R1_FB15_Msk (0x1U << CAN_F13R1_FB15_Pos) /*!< 0x00008000 */ 08079 #define CAN_F13R1_FB15 CAN_F13R1_FB15_Msk /*!< Filter bit 15 */ 08080 #define CAN_F13R1_FB16_Pos (16U) 08081 #define CAN_F13R1_FB16_Msk (0x1U << CAN_F13R1_FB16_Pos) /*!< 0x00010000 */ 08082 #define CAN_F13R1_FB16 CAN_F13R1_FB16_Msk /*!< Filter bit 16 */ 08083 #define CAN_F13R1_FB17_Pos (17U) 08084 #define CAN_F13R1_FB17_Msk (0x1U << CAN_F13R1_FB17_Pos) /*!< 0x00020000 */ 08085 #define CAN_F13R1_FB17 CAN_F13R1_FB17_Msk /*!< Filter bit 17 */ 08086 #define CAN_F13R1_FB18_Pos (18U) 08087 #define CAN_F13R1_FB18_Msk (0x1U << CAN_F13R1_FB18_Pos) /*!< 0x00040000 */ 08088 #define CAN_F13R1_FB18 CAN_F13R1_FB18_Msk /*!< Filter bit 18 */ 08089 #define CAN_F13R1_FB19_Pos (19U) 08090 #define CAN_F13R1_FB19_Msk (0x1U << CAN_F13R1_FB19_Pos) /*!< 0x00080000 */ 08091 #define CAN_F13R1_FB19 CAN_F13R1_FB19_Msk /*!< Filter bit 19 */ 08092 #define CAN_F13R1_FB20_Pos (20U) 08093 #define CAN_F13R1_FB20_Msk (0x1U << CAN_F13R1_FB20_Pos) /*!< 0x00100000 */ 08094 #define CAN_F13R1_FB20 CAN_F13R1_FB20_Msk /*!< Filter bit 20 */ 08095 #define CAN_F13R1_FB21_Pos (21U) 08096 #define CAN_F13R1_FB21_Msk (0x1U << CAN_F13R1_FB21_Pos) /*!< 0x00200000 */ 08097 #define CAN_F13R1_FB21 CAN_F13R1_FB21_Msk /*!< Filter bit 21 */ 08098 #define CAN_F13R1_FB22_Pos (22U) 08099 #define CAN_F13R1_FB22_Msk (0x1U << CAN_F13R1_FB22_Pos) /*!< 0x00400000 */ 08100 #define CAN_F13R1_FB22 CAN_F13R1_FB22_Msk /*!< Filter bit 22 */ 08101 #define CAN_F13R1_FB23_Pos (23U) 08102 #define CAN_F13R1_FB23_Msk (0x1U << CAN_F13R1_FB23_Pos) /*!< 0x00800000 */ 08103 #define CAN_F13R1_FB23 CAN_F13R1_FB23_Msk /*!< Filter bit 23 */ 08104 #define CAN_F13R1_FB24_Pos (24U) 08105 #define CAN_F13R1_FB24_Msk (0x1U << CAN_F13R1_FB24_Pos) /*!< 0x01000000 */ 08106 #define CAN_F13R1_FB24 CAN_F13R1_FB24_Msk /*!< Filter bit 24 */ 08107 #define CAN_F13R1_FB25_Pos (25U) 08108 #define CAN_F13R1_FB25_Msk (0x1U << CAN_F13R1_FB25_Pos) /*!< 0x02000000 */ 08109 #define CAN_F13R1_FB25 CAN_F13R1_FB25_Msk /*!< Filter bit 25 */ 08110 #define CAN_F13R1_FB26_Pos (26U) 08111 #define CAN_F13R1_FB26_Msk (0x1U << CAN_F13R1_FB26_Pos) /*!< 0x04000000 */ 08112 #define CAN_F13R1_FB26 CAN_F13R1_FB26_Msk /*!< Filter bit 26 */ 08113 #define CAN_F13R1_FB27_Pos (27U) 08114 #define CAN_F13R1_FB27_Msk (0x1U << CAN_F13R1_FB27_Pos) /*!< 0x08000000 */ 08115 #define CAN_F13R1_FB27 CAN_F13R1_FB27_Msk /*!< Filter bit 27 */ 08116 #define CAN_F13R1_FB28_Pos (28U) 08117 #define CAN_F13R1_FB28_Msk (0x1U << CAN_F13R1_FB28_Pos) /*!< 0x10000000 */ 08118 #define CAN_F13R1_FB28 CAN_F13R1_FB28_Msk /*!< Filter bit 28 */ 08119 #define CAN_F13R1_FB29_Pos (29U) 08120 #define CAN_F13R1_FB29_Msk (0x1U << CAN_F13R1_FB29_Pos) /*!< 0x20000000 */ 08121 #define CAN_F13R1_FB29 CAN_F13R1_FB29_Msk /*!< Filter bit 29 */ 08122 #define CAN_F13R1_FB30_Pos (30U) 08123 #define CAN_F13R1_FB30_Msk (0x1U << CAN_F13R1_FB30_Pos) /*!< 0x40000000 */ 08124 #define CAN_F13R1_FB30 CAN_F13R1_FB30_Msk /*!< Filter bit 30 */ 08125 #define CAN_F13R1_FB31_Pos (31U) 08126 #define CAN_F13R1_FB31_Msk (0x1U << CAN_F13R1_FB31_Pos) /*!< 0x80000000 */ 08127 #define CAN_F13R1_FB31 CAN_F13R1_FB31_Msk /*!< Filter bit 31 */ 08128 08129 /******************* Bit definition for CAN_F0R2 register *******************/ 08130 #define CAN_F0R2_FB0_Pos (0U) 08131 #define CAN_F0R2_FB0_Msk (0x1U << CAN_F0R2_FB0_Pos) /*!< 0x00000001 */ 08132 #define CAN_F0R2_FB0 CAN_F0R2_FB0_Msk /*!< Filter bit 0 */ 08133 #define CAN_F0R2_FB1_Pos (1U) 08134 #define CAN_F0R2_FB1_Msk (0x1U << CAN_F0R2_FB1_Pos) /*!< 0x00000002 */ 08135 #define CAN_F0R2_FB1 CAN_F0R2_FB1_Msk /*!< Filter bit 1 */ 08136 #define CAN_F0R2_FB2_Pos (2U) 08137 #define CAN_F0R2_FB2_Msk (0x1U << CAN_F0R2_FB2_Pos) /*!< 0x00000004 */ 08138 #define CAN_F0R2_FB2 CAN_F0R2_FB2_Msk /*!< Filter bit 2 */ 08139 #define CAN_F0R2_FB3_Pos (3U) 08140 #define CAN_F0R2_FB3_Msk (0x1U << CAN_F0R2_FB3_Pos) /*!< 0x00000008 */ 08141 #define CAN_F0R2_FB3 CAN_F0R2_FB3_Msk /*!< Filter bit 3 */ 08142 #define CAN_F0R2_FB4_Pos (4U) 08143 #define CAN_F0R2_FB4_Msk (0x1U << CAN_F0R2_FB4_Pos) /*!< 0x00000010 */ 08144 #define CAN_F0R2_FB4 CAN_F0R2_FB4_Msk /*!< Filter bit 4 */ 08145 #define CAN_F0R2_FB5_Pos (5U) 08146 #define CAN_F0R2_FB5_Msk (0x1U << CAN_F0R2_FB5_Pos) /*!< 0x00000020 */ 08147 #define CAN_F0R2_FB5 CAN_F0R2_FB5_Msk /*!< Filter bit 5 */ 08148 #define CAN_F0R2_FB6_Pos (6U) 08149 #define CAN_F0R2_FB6_Msk (0x1U << CAN_F0R2_FB6_Pos) /*!< 0x00000040 */ 08150 #define CAN_F0R2_FB6 CAN_F0R2_FB6_Msk /*!< Filter bit 6 */ 08151 #define CAN_F0R2_FB7_Pos (7U) 08152 #define CAN_F0R2_FB7_Msk (0x1U << CAN_F0R2_FB7_Pos) /*!< 0x00000080 */ 08153 #define CAN_F0R2_FB7 CAN_F0R2_FB7_Msk /*!< Filter bit 7 */ 08154 #define CAN_F0R2_FB8_Pos (8U) 08155 #define CAN_F0R2_FB8_Msk (0x1U << CAN_F0R2_FB8_Pos) /*!< 0x00000100 */ 08156 #define CAN_F0R2_FB8 CAN_F0R2_FB8_Msk /*!< Filter bit 8 */ 08157 #define CAN_F0R2_FB9_Pos (9U) 08158 #define CAN_F0R2_FB9_Msk (0x1U << CAN_F0R2_FB9_Pos) /*!< 0x00000200 */ 08159 #define CAN_F0R2_FB9 CAN_F0R2_FB9_Msk /*!< Filter bit 9 */ 08160 #define CAN_F0R2_FB10_Pos (10U) 08161 #define CAN_F0R2_FB10_Msk (0x1U << CAN_F0R2_FB10_Pos) /*!< 0x00000400 */ 08162 #define CAN_F0R2_FB10 CAN_F0R2_FB10_Msk /*!< Filter bit 10 */ 08163 #define CAN_F0R2_FB11_Pos (11U) 08164 #define CAN_F0R2_FB11_Msk (0x1U << CAN_F0R2_FB11_Pos) /*!< 0x00000800 */ 08165 #define CAN_F0R2_FB11 CAN_F0R2_FB11_Msk /*!< Filter bit 11 */ 08166 #define CAN_F0R2_FB12_Pos (12U) 08167 #define CAN_F0R2_FB12_Msk (0x1U << CAN_F0R2_FB12_Pos) /*!< 0x00001000 */ 08168 #define CAN_F0R2_FB12 CAN_F0R2_FB12_Msk /*!< Filter bit 12 */ 08169 #define CAN_F0R2_FB13_Pos (13U) 08170 #define CAN_F0R2_FB13_Msk (0x1U << CAN_F0R2_FB13_Pos) /*!< 0x00002000 */ 08171 #define CAN_F0R2_FB13 CAN_F0R2_FB13_Msk /*!< Filter bit 13 */ 08172 #define CAN_F0R2_FB14_Pos (14U) 08173 #define CAN_F0R2_FB14_Msk (0x1U << CAN_F0R2_FB14_Pos) /*!< 0x00004000 */ 08174 #define CAN_F0R2_FB14 CAN_F0R2_FB14_Msk /*!< Filter bit 14 */ 08175 #define CAN_F0R2_FB15_Pos (15U) 08176 #define CAN_F0R2_FB15_Msk (0x1U << CAN_F0R2_FB15_Pos) /*!< 0x00008000 */ 08177 #define CAN_F0R2_FB15 CAN_F0R2_FB15_Msk /*!< Filter bit 15 */ 08178 #define CAN_F0R2_FB16_Pos (16U) 08179 #define CAN_F0R2_FB16_Msk (0x1U << CAN_F0R2_FB16_Pos) /*!< 0x00010000 */ 08180 #define CAN_F0R2_FB16 CAN_F0R2_FB16_Msk /*!< Filter bit 16 */ 08181 #define CAN_F0R2_FB17_Pos (17U) 08182 #define CAN_F0R2_FB17_Msk (0x1U << CAN_F0R2_FB17_Pos) /*!< 0x00020000 */ 08183 #define CAN_F0R2_FB17 CAN_F0R2_FB17_Msk /*!< Filter bit 17 */ 08184 #define CAN_F0R2_FB18_Pos (18U) 08185 #define CAN_F0R2_FB18_Msk (0x1U << CAN_F0R2_FB18_Pos) /*!< 0x00040000 */ 08186 #define CAN_F0R2_FB18 CAN_F0R2_FB18_Msk /*!< Filter bit 18 */ 08187 #define CAN_F0R2_FB19_Pos (19U) 08188 #define CAN_F0R2_FB19_Msk (0x1U << CAN_F0R2_FB19_Pos) /*!< 0x00080000 */ 08189 #define CAN_F0R2_FB19 CAN_F0R2_FB19_Msk /*!< Filter bit 19 */ 08190 #define CAN_F0R2_FB20_Pos (20U) 08191 #define CAN_F0R2_FB20_Msk (0x1U << CAN_F0R2_FB20_Pos) /*!< 0x00100000 */ 08192 #define CAN_F0R2_FB20 CAN_F0R2_FB20_Msk /*!< Filter bit 20 */ 08193 #define CAN_F0R2_FB21_Pos (21U) 08194 #define CAN_F0R2_FB21_Msk (0x1U << CAN_F0R2_FB21_Pos) /*!< 0x00200000 */ 08195 #define CAN_F0R2_FB21 CAN_F0R2_FB21_Msk /*!< Filter bit 21 */ 08196 #define CAN_F0R2_FB22_Pos (22U) 08197 #define CAN_F0R2_FB22_Msk (0x1U << CAN_F0R2_FB22_Pos) /*!< 0x00400000 */ 08198 #define CAN_F0R2_FB22 CAN_F0R2_FB22_Msk /*!< Filter bit 22 */ 08199 #define CAN_F0R2_FB23_Pos (23U) 08200 #define CAN_F0R2_FB23_Msk (0x1U << CAN_F0R2_FB23_Pos) /*!< 0x00800000 */ 08201 #define CAN_F0R2_FB23 CAN_F0R2_FB23_Msk /*!< Filter bit 23 */ 08202 #define CAN_F0R2_FB24_Pos (24U) 08203 #define CAN_F0R2_FB24_Msk (0x1U << CAN_F0R2_FB24_Pos) /*!< 0x01000000 */ 08204 #define CAN_F0R2_FB24 CAN_F0R2_FB24_Msk /*!< Filter bit 24 */ 08205 #define CAN_F0R2_FB25_Pos (25U) 08206 #define CAN_F0R2_FB25_Msk (0x1U << CAN_F0R2_FB25_Pos) /*!< 0x02000000 */ 08207 #define CAN_F0R2_FB25 CAN_F0R2_FB25_Msk /*!< Filter bit 25 */ 08208 #define CAN_F0R2_FB26_Pos (26U) 08209 #define CAN_F0R2_FB26_Msk (0x1U << CAN_F0R2_FB26_Pos) /*!< 0x04000000 */ 08210 #define CAN_F0R2_FB26 CAN_F0R2_FB26_Msk /*!< Filter bit 26 */ 08211 #define CAN_F0R2_FB27_Pos (27U) 08212 #define CAN_F0R2_FB27_Msk (0x1U << CAN_F0R2_FB27_Pos) /*!< 0x08000000 */ 08213 #define CAN_F0R2_FB27 CAN_F0R2_FB27_Msk /*!< Filter bit 27 */ 08214 #define CAN_F0R2_FB28_Pos (28U) 08215 #define CAN_F0R2_FB28_Msk (0x1U << CAN_F0R2_FB28_Pos) /*!< 0x10000000 */ 08216 #define CAN_F0R2_FB28 CAN_F0R2_FB28_Msk /*!< Filter bit 28 */ 08217 #define CAN_F0R2_FB29_Pos (29U) 08218 #define CAN_F0R2_FB29_Msk (0x1U << CAN_F0R2_FB29_Pos) /*!< 0x20000000 */ 08219 #define CAN_F0R2_FB29 CAN_F0R2_FB29_Msk /*!< Filter bit 29 */ 08220 #define CAN_F0R2_FB30_Pos (30U) 08221 #define CAN_F0R2_FB30_Msk (0x1U << CAN_F0R2_FB30_Pos) /*!< 0x40000000 */ 08222 #define CAN_F0R2_FB30 CAN_F0R2_FB30_Msk /*!< Filter bit 30 */ 08223 #define CAN_F0R2_FB31_Pos (31U) 08224 #define CAN_F0R2_FB31_Msk (0x1U << CAN_F0R2_FB31_Pos) /*!< 0x80000000 */ 08225 #define CAN_F0R2_FB31 CAN_F0R2_FB31_Msk /*!< Filter bit 31 */ 08226 08227 /******************* Bit definition for CAN_F1R2 register *******************/ 08228 #define CAN_F1R2_FB0_Pos (0U) 08229 #define CAN_F1R2_FB0_Msk (0x1U << CAN_F1R2_FB0_Pos) /*!< 0x00000001 */ 08230 #define CAN_F1R2_FB0 CAN_F1R2_FB0_Msk /*!< Filter bit 0 */ 08231 #define CAN_F1R2_FB1_Pos (1U) 08232 #define CAN_F1R2_FB1_Msk (0x1U << CAN_F1R2_FB1_Pos) /*!< 0x00000002 */ 08233 #define CAN_F1R2_FB1 CAN_F1R2_FB1_Msk /*!< Filter bit 1 */ 08234 #define CAN_F1R2_FB2_Pos (2U) 08235 #define CAN_F1R2_FB2_Msk (0x1U << CAN_F1R2_FB2_Pos) /*!< 0x00000004 */ 08236 #define CAN_F1R2_FB2 CAN_F1R2_FB2_Msk /*!< Filter bit 2 */ 08237 #define CAN_F1R2_FB3_Pos (3U) 08238 #define CAN_F1R2_FB3_Msk (0x1U << CAN_F1R2_FB3_Pos) /*!< 0x00000008 */ 08239 #define CAN_F1R2_FB3 CAN_F1R2_FB3_Msk /*!< Filter bit 3 */ 08240 #define CAN_F1R2_FB4_Pos (4U) 08241 #define CAN_F1R2_FB4_Msk (0x1U << CAN_F1R2_FB4_Pos) /*!< 0x00000010 */ 08242 #define CAN_F1R2_FB4 CAN_F1R2_FB4_Msk /*!< Filter bit 4 */ 08243 #define CAN_F1R2_FB5_Pos (5U) 08244 #define CAN_F1R2_FB5_Msk (0x1U << CAN_F1R2_FB5_Pos) /*!< 0x00000020 */ 08245 #define CAN_F1R2_FB5 CAN_F1R2_FB5_Msk /*!< Filter bit 5 */ 08246 #define CAN_F1R2_FB6_Pos (6U) 08247 #define CAN_F1R2_FB6_Msk (0x1U << CAN_F1R2_FB6_Pos) /*!< 0x00000040 */ 08248 #define CAN_F1R2_FB6 CAN_F1R2_FB6_Msk /*!< Filter bit 6 */ 08249 #define CAN_F1R2_FB7_Pos (7U) 08250 #define CAN_F1R2_FB7_Msk (0x1U << CAN_F1R2_FB7_Pos) /*!< 0x00000080 */ 08251 #define CAN_F1R2_FB7 CAN_F1R2_FB7_Msk /*!< Filter bit 7 */ 08252 #define CAN_F1R2_FB8_Pos (8U) 08253 #define CAN_F1R2_FB8_Msk (0x1U << CAN_F1R2_FB8_Pos) /*!< 0x00000100 */ 08254 #define CAN_F1R2_FB8 CAN_F1R2_FB8_Msk /*!< Filter bit 8 */ 08255 #define CAN_F1R2_FB9_Pos (9U) 08256 #define CAN_F1R2_FB9_Msk (0x1U << CAN_F1R2_FB9_Pos) /*!< 0x00000200 */ 08257 #define CAN_F1R2_FB9 CAN_F1R2_FB9_Msk /*!< Filter bit 9 */ 08258 #define CAN_F1R2_FB10_Pos (10U) 08259 #define CAN_F1R2_FB10_Msk (0x1U << CAN_F1R2_FB10_Pos) /*!< 0x00000400 */ 08260 #define CAN_F1R2_FB10 CAN_F1R2_FB10_Msk /*!< Filter bit 10 */ 08261 #define CAN_F1R2_FB11_Pos (11U) 08262 #define CAN_F1R2_FB11_Msk (0x1U << CAN_F1R2_FB11_Pos) /*!< 0x00000800 */ 08263 #define CAN_F1R2_FB11 CAN_F1R2_FB11_Msk /*!< Filter bit 11 */ 08264 #define CAN_F1R2_FB12_Pos (12U) 08265 #define CAN_F1R2_FB12_Msk (0x1U << CAN_F1R2_FB12_Pos) /*!< 0x00001000 */ 08266 #define CAN_F1R2_FB12 CAN_F1R2_FB12_Msk /*!< Filter bit 12 */ 08267 #define CAN_F1R2_FB13_Pos (13U) 08268 #define CAN_F1R2_FB13_Msk (0x1U << CAN_F1R2_FB13_Pos) /*!< 0x00002000 */ 08269 #define CAN_F1R2_FB13 CAN_F1R2_FB13_Msk /*!< Filter bit 13 */ 08270 #define CAN_F1R2_FB14_Pos (14U) 08271 #define CAN_F1R2_FB14_Msk (0x1U << CAN_F1R2_FB14_Pos) /*!< 0x00004000 */ 08272 #define CAN_F1R2_FB14 CAN_F1R2_FB14_Msk /*!< Filter bit 14 */ 08273 #define CAN_F1R2_FB15_Pos (15U) 08274 #define CAN_F1R2_FB15_Msk (0x1U << CAN_F1R2_FB15_Pos) /*!< 0x00008000 */ 08275 #define CAN_F1R2_FB15 CAN_F1R2_FB15_Msk /*!< Filter bit 15 */ 08276 #define CAN_F1R2_FB16_Pos (16U) 08277 #define CAN_F1R2_FB16_Msk (0x1U << CAN_F1R2_FB16_Pos) /*!< 0x00010000 */ 08278 #define CAN_F1R2_FB16 CAN_F1R2_FB16_Msk /*!< Filter bit 16 */ 08279 #define CAN_F1R2_FB17_Pos (17U) 08280 #define CAN_F1R2_FB17_Msk (0x1U << CAN_F1R2_FB17_Pos) /*!< 0x00020000 */ 08281 #define CAN_F1R2_FB17 CAN_F1R2_FB17_Msk /*!< Filter bit 17 */ 08282 #define CAN_F1R2_FB18_Pos (18U) 08283 #define CAN_F1R2_FB18_Msk (0x1U << CAN_F1R2_FB18_Pos) /*!< 0x00040000 */ 08284 #define CAN_F1R2_FB18 CAN_F1R2_FB18_Msk /*!< Filter bit 18 */ 08285 #define CAN_F1R2_FB19_Pos (19U) 08286 #define CAN_F1R2_FB19_Msk (0x1U << CAN_F1R2_FB19_Pos) /*!< 0x00080000 */ 08287 #define CAN_F1R2_FB19 CAN_F1R2_FB19_Msk /*!< Filter bit 19 */ 08288 #define CAN_F1R2_FB20_Pos (20U) 08289 #define CAN_F1R2_FB20_Msk (0x1U << CAN_F1R2_FB20_Pos) /*!< 0x00100000 */ 08290 #define CAN_F1R2_FB20 CAN_F1R2_FB20_Msk /*!< Filter bit 20 */ 08291 #define CAN_F1R2_FB21_Pos (21U) 08292 #define CAN_F1R2_FB21_Msk (0x1U << CAN_F1R2_FB21_Pos) /*!< 0x00200000 */ 08293 #define CAN_F1R2_FB21 CAN_F1R2_FB21_Msk /*!< Filter bit 21 */ 08294 #define CAN_F1R2_FB22_Pos (22U) 08295 #define CAN_F1R2_FB22_Msk (0x1U << CAN_F1R2_FB22_Pos) /*!< 0x00400000 */ 08296 #define CAN_F1R2_FB22 CAN_F1R2_FB22_Msk /*!< Filter bit 22 */ 08297 #define CAN_F1R2_FB23_Pos (23U) 08298 #define CAN_F1R2_FB23_Msk (0x1U << CAN_F1R2_FB23_Pos) /*!< 0x00800000 */ 08299 #define CAN_F1R2_FB23 CAN_F1R2_FB23_Msk /*!< Filter bit 23 */ 08300 #define CAN_F1R2_FB24_Pos (24U) 08301 #define CAN_F1R2_FB24_Msk (0x1U << CAN_F1R2_FB24_Pos) /*!< 0x01000000 */ 08302 #define CAN_F1R2_FB24 CAN_F1R2_FB24_Msk /*!< Filter bit 24 */ 08303 #define CAN_F1R2_FB25_Pos (25U) 08304 #define CAN_F1R2_FB25_Msk (0x1U << CAN_F1R2_FB25_Pos) /*!< 0x02000000 */ 08305 #define CAN_F1R2_FB25 CAN_F1R2_FB25_Msk /*!< Filter bit 25 */ 08306 #define CAN_F1R2_FB26_Pos (26U) 08307 #define CAN_F1R2_FB26_Msk (0x1U << CAN_F1R2_FB26_Pos) /*!< 0x04000000 */ 08308 #define CAN_F1R2_FB26 CAN_F1R2_FB26_Msk /*!< Filter bit 26 */ 08309 #define CAN_F1R2_FB27_Pos (27U) 08310 #define CAN_F1R2_FB27_Msk (0x1U << CAN_F1R2_FB27_Pos) /*!< 0x08000000 */ 08311 #define CAN_F1R2_FB27 CAN_F1R2_FB27_Msk /*!< Filter bit 27 */ 08312 #define CAN_F1R2_FB28_Pos (28U) 08313 #define CAN_F1R2_FB28_Msk (0x1U << CAN_F1R2_FB28_Pos) /*!< 0x10000000 */ 08314 #define CAN_F1R2_FB28 CAN_F1R2_FB28_Msk /*!< Filter bit 28 */ 08315 #define CAN_F1R2_FB29_Pos (29U) 08316 #define CAN_F1R2_FB29_Msk (0x1U << CAN_F1R2_FB29_Pos) /*!< 0x20000000 */ 08317 #define CAN_F1R2_FB29 CAN_F1R2_FB29_Msk /*!< Filter bit 29 */ 08318 #define CAN_F1R2_FB30_Pos (30U) 08319 #define CAN_F1R2_FB30_Msk (0x1U << CAN_F1R2_FB30_Pos) /*!< 0x40000000 */ 08320 #define CAN_F1R2_FB30 CAN_F1R2_FB30_Msk /*!< Filter bit 30 */ 08321 #define CAN_F1R2_FB31_Pos (31U) 08322 #define CAN_F1R2_FB31_Msk (0x1U << CAN_F1R2_FB31_Pos) /*!< 0x80000000 */ 08323 #define CAN_F1R2_FB31 CAN_F1R2_FB31_Msk /*!< Filter bit 31 */ 08324 08325 /******************* Bit definition for CAN_F2R2 register *******************/ 08326 #define CAN_F2R2_FB0_Pos (0U) 08327 #define CAN_F2R2_FB0_Msk (0x1U << CAN_F2R2_FB0_Pos) /*!< 0x00000001 */ 08328 #define CAN_F2R2_FB0 CAN_F2R2_FB0_Msk /*!< Filter bit 0 */ 08329 #define CAN_F2R2_FB1_Pos (1U) 08330 #define CAN_F2R2_FB1_Msk (0x1U << CAN_F2R2_FB1_Pos) /*!< 0x00000002 */ 08331 #define CAN_F2R2_FB1 CAN_F2R2_FB1_Msk /*!< Filter bit 1 */ 08332 #define CAN_F2R2_FB2_Pos (2U) 08333 #define CAN_F2R2_FB2_Msk (0x1U << CAN_F2R2_FB2_Pos) /*!< 0x00000004 */ 08334 #define CAN_F2R2_FB2 CAN_F2R2_FB2_Msk /*!< Filter bit 2 */ 08335 #define CAN_F2R2_FB3_Pos (3U) 08336 #define CAN_F2R2_FB3_Msk (0x1U << CAN_F2R2_FB3_Pos) /*!< 0x00000008 */ 08337 #define CAN_F2R2_FB3 CAN_F2R2_FB3_Msk /*!< Filter bit 3 */ 08338 #define CAN_F2R2_FB4_Pos (4U) 08339 #define CAN_F2R2_FB4_Msk (0x1U << CAN_F2R2_FB4_Pos) /*!< 0x00000010 */ 08340 #define CAN_F2R2_FB4 CAN_F2R2_FB4_Msk /*!< Filter bit 4 */ 08341 #define CAN_F2R2_FB5_Pos (5U) 08342 #define CAN_F2R2_FB5_Msk (0x1U << CAN_F2R2_FB5_Pos) /*!< 0x00000020 */ 08343 #define CAN_F2R2_FB5 CAN_F2R2_FB5_Msk /*!< Filter bit 5 */ 08344 #define CAN_F2R2_FB6_Pos (6U) 08345 #define CAN_F2R2_FB6_Msk (0x1U << CAN_F2R2_FB6_Pos) /*!< 0x00000040 */ 08346 #define CAN_F2R2_FB6 CAN_F2R2_FB6_Msk /*!< Filter bit 6 */ 08347 #define CAN_F2R2_FB7_Pos (7U) 08348 #define CAN_F2R2_FB7_Msk (0x1U << CAN_F2R2_FB7_Pos) /*!< 0x00000080 */ 08349 #define CAN_F2R2_FB7 CAN_F2R2_FB7_Msk /*!< Filter bit 7 */ 08350 #define CAN_F2R2_FB8_Pos (8U) 08351 #define CAN_F2R2_FB8_Msk (0x1U << CAN_F2R2_FB8_Pos) /*!< 0x00000100 */ 08352 #define CAN_F2R2_FB8 CAN_F2R2_FB8_Msk /*!< Filter bit 8 */ 08353 #define CAN_F2R2_FB9_Pos (9U) 08354 #define CAN_F2R2_FB9_Msk (0x1U << CAN_F2R2_FB9_Pos) /*!< 0x00000200 */ 08355 #define CAN_F2R2_FB9 CAN_F2R2_FB9_Msk /*!< Filter bit 9 */ 08356 #define CAN_F2R2_FB10_Pos (10U) 08357 #define CAN_F2R2_FB10_Msk (0x1U << CAN_F2R2_FB10_Pos) /*!< 0x00000400 */ 08358 #define CAN_F2R2_FB10 CAN_F2R2_FB10_Msk /*!< Filter bit 10 */ 08359 #define CAN_F2R2_FB11_Pos (11U) 08360 #define CAN_F2R2_FB11_Msk (0x1U << CAN_F2R2_FB11_Pos) /*!< 0x00000800 */ 08361 #define CAN_F2R2_FB11 CAN_F2R2_FB11_Msk /*!< Filter bit 11 */ 08362 #define CAN_F2R2_FB12_Pos (12U) 08363 #define CAN_F2R2_FB12_Msk (0x1U << CAN_F2R2_FB12_Pos) /*!< 0x00001000 */ 08364 #define CAN_F2R2_FB12 CAN_F2R2_FB12_Msk /*!< Filter bit 12 */ 08365 #define CAN_F2R2_FB13_Pos (13U) 08366 #define CAN_F2R2_FB13_Msk (0x1U << CAN_F2R2_FB13_Pos) /*!< 0x00002000 */ 08367 #define CAN_F2R2_FB13 CAN_F2R2_FB13_Msk /*!< Filter bit 13 */ 08368 #define CAN_F2R2_FB14_Pos (14U) 08369 #define CAN_F2R2_FB14_Msk (0x1U << CAN_F2R2_FB14_Pos) /*!< 0x00004000 */ 08370 #define CAN_F2R2_FB14 CAN_F2R2_FB14_Msk /*!< Filter bit 14 */ 08371 #define CAN_F2R2_FB15_Pos (15U) 08372 #define CAN_F2R2_FB15_Msk (0x1U << CAN_F2R2_FB15_Pos) /*!< 0x00008000 */ 08373 #define CAN_F2R2_FB15 CAN_F2R2_FB15_Msk /*!< Filter bit 15 */ 08374 #define CAN_F2R2_FB16_Pos (16U) 08375 #define CAN_F2R2_FB16_Msk (0x1U << CAN_F2R2_FB16_Pos) /*!< 0x00010000 */ 08376 #define CAN_F2R2_FB16 CAN_F2R2_FB16_Msk /*!< Filter bit 16 */ 08377 #define CAN_F2R2_FB17_Pos (17U) 08378 #define CAN_F2R2_FB17_Msk (0x1U << CAN_F2R2_FB17_Pos) /*!< 0x00020000 */ 08379 #define CAN_F2R2_FB17 CAN_F2R2_FB17_Msk /*!< Filter bit 17 */ 08380 #define CAN_F2R2_FB18_Pos (18U) 08381 #define CAN_F2R2_FB18_Msk (0x1U << CAN_F2R2_FB18_Pos) /*!< 0x00040000 */ 08382 #define CAN_F2R2_FB18 CAN_F2R2_FB18_Msk /*!< Filter bit 18 */ 08383 #define CAN_F2R2_FB19_Pos (19U) 08384 #define CAN_F2R2_FB19_Msk (0x1U << CAN_F2R2_FB19_Pos) /*!< 0x00080000 */ 08385 #define CAN_F2R2_FB19 CAN_F2R2_FB19_Msk /*!< Filter bit 19 */ 08386 #define CAN_F2R2_FB20_Pos (20U) 08387 #define CAN_F2R2_FB20_Msk (0x1U << CAN_F2R2_FB20_Pos) /*!< 0x00100000 */ 08388 #define CAN_F2R2_FB20 CAN_F2R2_FB20_Msk /*!< Filter bit 20 */ 08389 #define CAN_F2R2_FB21_Pos (21U) 08390 #define CAN_F2R2_FB21_Msk (0x1U << CAN_F2R2_FB21_Pos) /*!< 0x00200000 */ 08391 #define CAN_F2R2_FB21 CAN_F2R2_FB21_Msk /*!< Filter bit 21 */ 08392 #define CAN_F2R2_FB22_Pos (22U) 08393 #define CAN_F2R2_FB22_Msk (0x1U << CAN_F2R2_FB22_Pos) /*!< 0x00400000 */ 08394 #define CAN_F2R2_FB22 CAN_F2R2_FB22_Msk /*!< Filter bit 22 */ 08395 #define CAN_F2R2_FB23_Pos (23U) 08396 #define CAN_F2R2_FB23_Msk (0x1U << CAN_F2R2_FB23_Pos) /*!< 0x00800000 */ 08397 #define CAN_F2R2_FB23 CAN_F2R2_FB23_Msk /*!< Filter bit 23 */ 08398 #define CAN_F2R2_FB24_Pos (24U) 08399 #define CAN_F2R2_FB24_Msk (0x1U << CAN_F2R2_FB24_Pos) /*!< 0x01000000 */ 08400 #define CAN_F2R2_FB24 CAN_F2R2_FB24_Msk /*!< Filter bit 24 */ 08401 #define CAN_F2R2_FB25_Pos (25U) 08402 #define CAN_F2R2_FB25_Msk (0x1U << CAN_F2R2_FB25_Pos) /*!< 0x02000000 */ 08403 #define CAN_F2R2_FB25 CAN_F2R2_FB25_Msk /*!< Filter bit 25 */ 08404 #define CAN_F2R2_FB26_Pos (26U) 08405 #define CAN_F2R2_FB26_Msk (0x1U << CAN_F2R2_FB26_Pos) /*!< 0x04000000 */ 08406 #define CAN_F2R2_FB26 CAN_F2R2_FB26_Msk /*!< Filter bit 26 */ 08407 #define CAN_F2R2_FB27_Pos (27U) 08408 #define CAN_F2R2_FB27_Msk (0x1U << CAN_F2R2_FB27_Pos) /*!< 0x08000000 */ 08409 #define CAN_F2R2_FB27 CAN_F2R2_FB27_Msk /*!< Filter bit 27 */ 08410 #define CAN_F2R2_FB28_Pos (28U) 08411 #define CAN_F2R2_FB28_Msk (0x1U << CAN_F2R2_FB28_Pos) /*!< 0x10000000 */ 08412 #define CAN_F2R2_FB28 CAN_F2R2_FB28_Msk /*!< Filter bit 28 */ 08413 #define CAN_F2R2_FB29_Pos (29U) 08414 #define CAN_F2R2_FB29_Msk (0x1U << CAN_F2R2_FB29_Pos) /*!< 0x20000000 */ 08415 #define CAN_F2R2_FB29 CAN_F2R2_FB29_Msk /*!< Filter bit 29 */ 08416 #define CAN_F2R2_FB30_Pos (30U) 08417 #define CAN_F2R2_FB30_Msk (0x1U << CAN_F2R2_FB30_Pos) /*!< 0x40000000 */ 08418 #define CAN_F2R2_FB30 CAN_F2R2_FB30_Msk /*!< Filter bit 30 */ 08419 #define CAN_F2R2_FB31_Pos (31U) 08420 #define CAN_F2R2_FB31_Msk (0x1U << CAN_F2R2_FB31_Pos) /*!< 0x80000000 */ 08421 #define CAN_F2R2_FB31 CAN_F2R2_FB31_Msk /*!< Filter bit 31 */ 08422 08423 /******************* Bit definition for CAN_F3R2 register *******************/ 08424 #define CAN_F3R2_FB0_Pos (0U) 08425 #define CAN_F3R2_FB0_Msk (0x1U << CAN_F3R2_FB0_Pos) /*!< 0x00000001 */ 08426 #define CAN_F3R2_FB0 CAN_F3R2_FB0_Msk /*!< Filter bit 0 */ 08427 #define CAN_F3R2_FB1_Pos (1U) 08428 #define CAN_F3R2_FB1_Msk (0x1U << CAN_F3R2_FB1_Pos) /*!< 0x00000002 */ 08429 #define CAN_F3R2_FB1 CAN_F3R2_FB1_Msk /*!< Filter bit 1 */ 08430 #define CAN_F3R2_FB2_Pos (2U) 08431 #define CAN_F3R2_FB2_Msk (0x1U << CAN_F3R2_FB2_Pos) /*!< 0x00000004 */ 08432 #define CAN_F3R2_FB2 CAN_F3R2_FB2_Msk /*!< Filter bit 2 */ 08433 #define CAN_F3R2_FB3_Pos (3U) 08434 #define CAN_F3R2_FB3_Msk (0x1U << CAN_F3R2_FB3_Pos) /*!< 0x00000008 */ 08435 #define CAN_F3R2_FB3 CAN_F3R2_FB3_Msk /*!< Filter bit 3 */ 08436 #define CAN_F3R2_FB4_Pos (4U) 08437 #define CAN_F3R2_FB4_Msk (0x1U << CAN_F3R2_FB4_Pos) /*!< 0x00000010 */ 08438 #define CAN_F3R2_FB4 CAN_F3R2_FB4_Msk /*!< Filter bit 4 */ 08439 #define CAN_F3R2_FB5_Pos (5U) 08440 #define CAN_F3R2_FB5_Msk (0x1U << CAN_F3R2_FB5_Pos) /*!< 0x00000020 */ 08441 #define CAN_F3R2_FB5 CAN_F3R2_FB5_Msk /*!< Filter bit 5 */ 08442 #define CAN_F3R2_FB6_Pos (6U) 08443 #define CAN_F3R2_FB6_Msk (0x1U << CAN_F3R2_FB6_Pos) /*!< 0x00000040 */ 08444 #define CAN_F3R2_FB6 CAN_F3R2_FB6_Msk /*!< Filter bit 6 */ 08445 #define CAN_F3R2_FB7_Pos (7U) 08446 #define CAN_F3R2_FB7_Msk (0x1U << CAN_F3R2_FB7_Pos) /*!< 0x00000080 */ 08447 #define CAN_F3R2_FB7 CAN_F3R2_FB7_Msk /*!< Filter bit 7 */ 08448 #define CAN_F3R2_FB8_Pos (8U) 08449 #define CAN_F3R2_FB8_Msk (0x1U << CAN_F3R2_FB8_Pos) /*!< 0x00000100 */ 08450 #define CAN_F3R2_FB8 CAN_F3R2_FB8_Msk /*!< Filter bit 8 */ 08451 #define CAN_F3R2_FB9_Pos (9U) 08452 #define CAN_F3R2_FB9_Msk (0x1U << CAN_F3R2_FB9_Pos) /*!< 0x00000200 */ 08453 #define CAN_F3R2_FB9 CAN_F3R2_FB9_Msk /*!< Filter bit 9 */ 08454 #define CAN_F3R2_FB10_Pos (10U) 08455 #define CAN_F3R2_FB10_Msk (0x1U << CAN_F3R2_FB10_Pos) /*!< 0x00000400 */ 08456 #define CAN_F3R2_FB10 CAN_F3R2_FB10_Msk /*!< Filter bit 10 */ 08457 #define CAN_F3R2_FB11_Pos (11U) 08458 #define CAN_F3R2_FB11_Msk (0x1U << CAN_F3R2_FB11_Pos) /*!< 0x00000800 */ 08459 #define CAN_F3R2_FB11 CAN_F3R2_FB11_Msk /*!< Filter bit 11 */ 08460 #define CAN_F3R2_FB12_Pos (12U) 08461 #define CAN_F3R2_FB12_Msk (0x1U << CAN_F3R2_FB12_Pos) /*!< 0x00001000 */ 08462 #define CAN_F3R2_FB12 CAN_F3R2_FB12_Msk /*!< Filter bit 12 */ 08463 #define CAN_F3R2_FB13_Pos (13U) 08464 #define CAN_F3R2_FB13_Msk (0x1U << CAN_F3R2_FB13_Pos) /*!< 0x00002000 */ 08465 #define CAN_F3R2_FB13 CAN_F3R2_FB13_Msk /*!< Filter bit 13 */ 08466 #define CAN_F3R2_FB14_Pos (14U) 08467 #define CAN_F3R2_FB14_Msk (0x1U << CAN_F3R2_FB14_Pos) /*!< 0x00004000 */ 08468 #define CAN_F3R2_FB14 CAN_F3R2_FB14_Msk /*!< Filter bit 14 */ 08469 #define CAN_F3R2_FB15_Pos (15U) 08470 #define CAN_F3R2_FB15_Msk (0x1U << CAN_F3R2_FB15_Pos) /*!< 0x00008000 */ 08471 #define CAN_F3R2_FB15 CAN_F3R2_FB15_Msk /*!< Filter bit 15 */ 08472 #define CAN_F3R2_FB16_Pos (16U) 08473 #define CAN_F3R2_FB16_Msk (0x1U << CAN_F3R2_FB16_Pos) /*!< 0x00010000 */ 08474 #define CAN_F3R2_FB16 CAN_F3R2_FB16_Msk /*!< Filter bit 16 */ 08475 #define CAN_F3R2_FB17_Pos (17U) 08476 #define CAN_F3R2_FB17_Msk (0x1U << CAN_F3R2_FB17_Pos) /*!< 0x00020000 */ 08477 #define CAN_F3R2_FB17 CAN_F3R2_FB17_Msk /*!< Filter bit 17 */ 08478 #define CAN_F3R2_FB18_Pos (18U) 08479 #define CAN_F3R2_FB18_Msk (0x1U << CAN_F3R2_FB18_Pos) /*!< 0x00040000 */ 08480 #define CAN_F3R2_FB18 CAN_F3R2_FB18_Msk /*!< Filter bit 18 */ 08481 #define CAN_F3R2_FB19_Pos (19U) 08482 #define CAN_F3R2_FB19_Msk (0x1U << CAN_F3R2_FB19_Pos) /*!< 0x00080000 */ 08483 #define CAN_F3R2_FB19 CAN_F3R2_FB19_Msk /*!< Filter bit 19 */ 08484 #define CAN_F3R2_FB20_Pos (20U) 08485 #define CAN_F3R2_FB20_Msk (0x1U << CAN_F3R2_FB20_Pos) /*!< 0x00100000 */ 08486 #define CAN_F3R2_FB20 CAN_F3R2_FB20_Msk /*!< Filter bit 20 */ 08487 #define CAN_F3R2_FB21_Pos (21U) 08488 #define CAN_F3R2_FB21_Msk (0x1U << CAN_F3R2_FB21_Pos) /*!< 0x00200000 */ 08489 #define CAN_F3R2_FB21 CAN_F3R2_FB21_Msk /*!< Filter bit 21 */ 08490 #define CAN_F3R2_FB22_Pos (22U) 08491 #define CAN_F3R2_FB22_Msk (0x1U << CAN_F3R2_FB22_Pos) /*!< 0x00400000 */ 08492 #define CAN_F3R2_FB22 CAN_F3R2_FB22_Msk /*!< Filter bit 22 */ 08493 #define CAN_F3R2_FB23_Pos (23U) 08494 #define CAN_F3R2_FB23_Msk (0x1U << CAN_F3R2_FB23_Pos) /*!< 0x00800000 */ 08495 #define CAN_F3R2_FB23 CAN_F3R2_FB23_Msk /*!< Filter bit 23 */ 08496 #define CAN_F3R2_FB24_Pos (24U) 08497 #define CAN_F3R2_FB24_Msk (0x1U << CAN_F3R2_FB24_Pos) /*!< 0x01000000 */ 08498 #define CAN_F3R2_FB24 CAN_F3R2_FB24_Msk /*!< Filter bit 24 */ 08499 #define CAN_F3R2_FB25_Pos (25U) 08500 #define CAN_F3R2_FB25_Msk (0x1U << CAN_F3R2_FB25_Pos) /*!< 0x02000000 */ 08501 #define CAN_F3R2_FB25 CAN_F3R2_FB25_Msk /*!< Filter bit 25 */ 08502 #define CAN_F3R2_FB26_Pos (26U) 08503 #define CAN_F3R2_FB26_Msk (0x1U << CAN_F3R2_FB26_Pos) /*!< 0x04000000 */ 08504 #define CAN_F3R2_FB26 CAN_F3R2_FB26_Msk /*!< Filter bit 26 */ 08505 #define CAN_F3R2_FB27_Pos (27U) 08506 #define CAN_F3R2_FB27_Msk (0x1U << CAN_F3R2_FB27_Pos) /*!< 0x08000000 */ 08507 #define CAN_F3R2_FB27 CAN_F3R2_FB27_Msk /*!< Filter bit 27 */ 08508 #define CAN_F3R2_FB28_Pos (28U) 08509 #define CAN_F3R2_FB28_Msk (0x1U << CAN_F3R2_FB28_Pos) /*!< 0x10000000 */ 08510 #define CAN_F3R2_FB28 CAN_F3R2_FB28_Msk /*!< Filter bit 28 */ 08511 #define CAN_F3R2_FB29_Pos (29U) 08512 #define CAN_F3R2_FB29_Msk (0x1U << CAN_F3R2_FB29_Pos) /*!< 0x20000000 */ 08513 #define CAN_F3R2_FB29 CAN_F3R2_FB29_Msk /*!< Filter bit 29 */ 08514 #define CAN_F3R2_FB30_Pos (30U) 08515 #define CAN_F3R2_FB30_Msk (0x1U << CAN_F3R2_FB30_Pos) /*!< 0x40000000 */ 08516 #define CAN_F3R2_FB30 CAN_F3R2_FB30_Msk /*!< Filter bit 30 */ 08517 #define CAN_F3R2_FB31_Pos (31U) 08518 #define CAN_F3R2_FB31_Msk (0x1U << CAN_F3R2_FB31_Pos) /*!< 0x80000000 */ 08519 #define CAN_F3R2_FB31 CAN_F3R2_FB31_Msk /*!< Filter bit 31 */ 08520 08521 /******************* Bit definition for CAN_F4R2 register *******************/ 08522 #define CAN_F4R2_FB0_Pos (0U) 08523 #define CAN_F4R2_FB0_Msk (0x1U << CAN_F4R2_FB0_Pos) /*!< 0x00000001 */ 08524 #define CAN_F4R2_FB0 CAN_F4R2_FB0_Msk /*!< Filter bit 0 */ 08525 #define CAN_F4R2_FB1_Pos (1U) 08526 #define CAN_F4R2_FB1_Msk (0x1U << CAN_F4R2_FB1_Pos) /*!< 0x00000002 */ 08527 #define CAN_F4R2_FB1 CAN_F4R2_FB1_Msk /*!< Filter bit 1 */ 08528 #define CAN_F4R2_FB2_Pos (2U) 08529 #define CAN_F4R2_FB2_Msk (0x1U << CAN_F4R2_FB2_Pos) /*!< 0x00000004 */ 08530 #define CAN_F4R2_FB2 CAN_F4R2_FB2_Msk /*!< Filter bit 2 */ 08531 #define CAN_F4R2_FB3_Pos (3U) 08532 #define CAN_F4R2_FB3_Msk (0x1U << CAN_F4R2_FB3_Pos) /*!< 0x00000008 */ 08533 #define CAN_F4R2_FB3 CAN_F4R2_FB3_Msk /*!< Filter bit 3 */ 08534 #define CAN_F4R2_FB4_Pos (4U) 08535 #define CAN_F4R2_FB4_Msk (0x1U << CAN_F4R2_FB4_Pos) /*!< 0x00000010 */ 08536 #define CAN_F4R2_FB4 CAN_F4R2_FB4_Msk /*!< Filter bit 4 */ 08537 #define CAN_F4R2_FB5_Pos (5U) 08538 #define CAN_F4R2_FB5_Msk (0x1U << CAN_F4R2_FB5_Pos) /*!< 0x00000020 */ 08539 #define CAN_F4R2_FB5 CAN_F4R2_FB5_Msk /*!< Filter bit 5 */ 08540 #define CAN_F4R2_FB6_Pos (6U) 08541 #define CAN_F4R2_FB6_Msk (0x1U << CAN_F4R2_FB6_Pos) /*!< 0x00000040 */ 08542 #define CAN_F4R2_FB6 CAN_F4R2_FB6_Msk /*!< Filter bit 6 */ 08543 #define CAN_F4R2_FB7_Pos (7U) 08544 #define CAN_F4R2_FB7_Msk (0x1U << CAN_F4R2_FB7_Pos) /*!< 0x00000080 */ 08545 #define CAN_F4R2_FB7 CAN_F4R2_FB7_Msk /*!< Filter bit 7 */ 08546 #define CAN_F4R2_FB8_Pos (8U) 08547 #define CAN_F4R2_FB8_Msk (0x1U << CAN_F4R2_FB8_Pos) /*!< 0x00000100 */ 08548 #define CAN_F4R2_FB8 CAN_F4R2_FB8_Msk /*!< Filter bit 8 */ 08549 #define CAN_F4R2_FB9_Pos (9U) 08550 #define CAN_F4R2_FB9_Msk (0x1U << CAN_F4R2_FB9_Pos) /*!< 0x00000200 */ 08551 #define CAN_F4R2_FB9 CAN_F4R2_FB9_Msk /*!< Filter bit 9 */ 08552 #define CAN_F4R2_FB10_Pos (10U) 08553 #define CAN_F4R2_FB10_Msk (0x1U << CAN_F4R2_FB10_Pos) /*!< 0x00000400 */ 08554 #define CAN_F4R2_FB10 CAN_F4R2_FB10_Msk /*!< Filter bit 10 */ 08555 #define CAN_F4R2_FB11_Pos (11U) 08556 #define CAN_F4R2_FB11_Msk (0x1U << CAN_F4R2_FB11_Pos) /*!< 0x00000800 */ 08557 #define CAN_F4R2_FB11 CAN_F4R2_FB11_Msk /*!< Filter bit 11 */ 08558 #define CAN_F4R2_FB12_Pos (12U) 08559 #define CAN_F4R2_FB12_Msk (0x1U << CAN_F4R2_FB12_Pos) /*!< 0x00001000 */ 08560 #define CAN_F4R2_FB12 CAN_F4R2_FB12_Msk /*!< Filter bit 12 */ 08561 #define CAN_F4R2_FB13_Pos (13U) 08562 #define CAN_F4R2_FB13_Msk (0x1U << CAN_F4R2_FB13_Pos) /*!< 0x00002000 */ 08563 #define CAN_F4R2_FB13 CAN_F4R2_FB13_Msk /*!< Filter bit 13 */ 08564 #define CAN_F4R2_FB14_Pos (14U) 08565 #define CAN_F4R2_FB14_Msk (0x1U << CAN_F4R2_FB14_Pos) /*!< 0x00004000 */ 08566 #define CAN_F4R2_FB14 CAN_F4R2_FB14_Msk /*!< Filter bit 14 */ 08567 #define CAN_F4R2_FB15_Pos (15U) 08568 #define CAN_F4R2_FB15_Msk (0x1U << CAN_F4R2_FB15_Pos) /*!< 0x00008000 */ 08569 #define CAN_F4R2_FB15 CAN_F4R2_FB15_Msk /*!< Filter bit 15 */ 08570 #define CAN_F4R2_FB16_Pos (16U) 08571 #define CAN_F4R2_FB16_Msk (0x1U << CAN_F4R2_FB16_Pos) /*!< 0x00010000 */ 08572 #define CAN_F4R2_FB16 CAN_F4R2_FB16_Msk /*!< Filter bit 16 */ 08573 #define CAN_F4R2_FB17_Pos (17U) 08574 #define CAN_F4R2_FB17_Msk (0x1U << CAN_F4R2_FB17_Pos) /*!< 0x00020000 */ 08575 #define CAN_F4R2_FB17 CAN_F4R2_FB17_Msk /*!< Filter bit 17 */ 08576 #define CAN_F4R2_FB18_Pos (18U) 08577 #define CAN_F4R2_FB18_Msk (0x1U << CAN_F4R2_FB18_Pos) /*!< 0x00040000 */ 08578 #define CAN_F4R2_FB18 CAN_F4R2_FB18_Msk /*!< Filter bit 18 */ 08579 #define CAN_F4R2_FB19_Pos (19U) 08580 #define CAN_F4R2_FB19_Msk (0x1U << CAN_F4R2_FB19_Pos) /*!< 0x00080000 */ 08581 #define CAN_F4R2_FB19 CAN_F4R2_FB19_Msk /*!< Filter bit 19 */ 08582 #define CAN_F4R2_FB20_Pos (20U) 08583 #define CAN_F4R2_FB20_Msk (0x1U << CAN_F4R2_FB20_Pos) /*!< 0x00100000 */ 08584 #define CAN_F4R2_FB20 CAN_F4R2_FB20_Msk /*!< Filter bit 20 */ 08585 #define CAN_F4R2_FB21_Pos (21U) 08586 #define CAN_F4R2_FB21_Msk (0x1U << CAN_F4R2_FB21_Pos) /*!< 0x00200000 */ 08587 #define CAN_F4R2_FB21 CAN_F4R2_FB21_Msk /*!< Filter bit 21 */ 08588 #define CAN_F4R2_FB22_Pos (22U) 08589 #define CAN_F4R2_FB22_Msk (0x1U << CAN_F4R2_FB22_Pos) /*!< 0x00400000 */ 08590 #define CAN_F4R2_FB22 CAN_F4R2_FB22_Msk /*!< Filter bit 22 */ 08591 #define CAN_F4R2_FB23_Pos (23U) 08592 #define CAN_F4R2_FB23_Msk (0x1U << CAN_F4R2_FB23_Pos) /*!< 0x00800000 */ 08593 #define CAN_F4R2_FB23 CAN_F4R2_FB23_Msk /*!< Filter bit 23 */ 08594 #define CAN_F4R2_FB24_Pos (24U) 08595 #define CAN_F4R2_FB24_Msk (0x1U << CAN_F4R2_FB24_Pos) /*!< 0x01000000 */ 08596 #define CAN_F4R2_FB24 CAN_F4R2_FB24_Msk /*!< Filter bit 24 */ 08597 #define CAN_F4R2_FB25_Pos (25U) 08598 #define CAN_F4R2_FB25_Msk (0x1U << CAN_F4R2_FB25_Pos) /*!< 0x02000000 */ 08599 #define CAN_F4R2_FB25 CAN_F4R2_FB25_Msk /*!< Filter bit 25 */ 08600 #define CAN_F4R2_FB26_Pos (26U) 08601 #define CAN_F4R2_FB26_Msk (0x1U << CAN_F4R2_FB26_Pos) /*!< 0x04000000 */ 08602 #define CAN_F4R2_FB26 CAN_F4R2_FB26_Msk /*!< Filter bit 26 */ 08603 #define CAN_F4R2_FB27_Pos (27U) 08604 #define CAN_F4R2_FB27_Msk (0x1U << CAN_F4R2_FB27_Pos) /*!< 0x08000000 */ 08605 #define CAN_F4R2_FB27 CAN_F4R2_FB27_Msk /*!< Filter bit 27 */ 08606 #define CAN_F4R2_FB28_Pos (28U) 08607 #define CAN_F4R2_FB28_Msk (0x1U << CAN_F4R2_FB28_Pos) /*!< 0x10000000 */ 08608 #define CAN_F4R2_FB28 CAN_F4R2_FB28_Msk /*!< Filter bit 28 */ 08609 #define CAN_F4R2_FB29_Pos (29U) 08610 #define CAN_F4R2_FB29_Msk (0x1U << CAN_F4R2_FB29_Pos) /*!< 0x20000000 */ 08611 #define CAN_F4R2_FB29 CAN_F4R2_FB29_Msk /*!< Filter bit 29 */ 08612 #define CAN_F4R2_FB30_Pos (30U) 08613 #define CAN_F4R2_FB30_Msk (0x1U << CAN_F4R2_FB30_Pos) /*!< 0x40000000 */ 08614 #define CAN_F4R2_FB30 CAN_F4R2_FB30_Msk /*!< Filter bit 30 */ 08615 #define CAN_F4R2_FB31_Pos (31U) 08616 #define CAN_F4R2_FB31_Msk (0x1U << CAN_F4R2_FB31_Pos) /*!< 0x80000000 */ 08617 #define CAN_F4R2_FB31 CAN_F4R2_FB31_Msk /*!< Filter bit 31 */ 08618 08619 /******************* Bit definition for CAN_F5R2 register *******************/ 08620 #define CAN_F5R2_FB0_Pos (0U) 08621 #define CAN_F5R2_FB0_Msk (0x1U << CAN_F5R2_FB0_Pos) /*!< 0x00000001 */ 08622 #define CAN_F5R2_FB0 CAN_F5R2_FB0_Msk /*!< Filter bit 0 */ 08623 #define CAN_F5R2_FB1_Pos (1U) 08624 #define CAN_F5R2_FB1_Msk (0x1U << CAN_F5R2_FB1_Pos) /*!< 0x00000002 */ 08625 #define CAN_F5R2_FB1 CAN_F5R2_FB1_Msk /*!< Filter bit 1 */ 08626 #define CAN_F5R2_FB2_Pos (2U) 08627 #define CAN_F5R2_FB2_Msk (0x1U << CAN_F5R2_FB2_Pos) /*!< 0x00000004 */ 08628 #define CAN_F5R2_FB2 CAN_F5R2_FB2_Msk /*!< Filter bit 2 */ 08629 #define CAN_F5R2_FB3_Pos (3U) 08630 #define CAN_F5R2_FB3_Msk (0x1U << CAN_F5R2_FB3_Pos) /*!< 0x00000008 */ 08631 #define CAN_F5R2_FB3 CAN_F5R2_FB3_Msk /*!< Filter bit 3 */ 08632 #define CAN_F5R2_FB4_Pos (4U) 08633 #define CAN_F5R2_FB4_Msk (0x1U << CAN_F5R2_FB4_Pos) /*!< 0x00000010 */ 08634 #define CAN_F5R2_FB4 CAN_F5R2_FB4_Msk /*!< Filter bit 4 */ 08635 #define CAN_F5R2_FB5_Pos (5U) 08636 #define CAN_F5R2_FB5_Msk (0x1U << CAN_F5R2_FB5_Pos) /*!< 0x00000020 */ 08637 #define CAN_F5R2_FB5 CAN_F5R2_FB5_Msk /*!< Filter bit 5 */ 08638 #define CAN_F5R2_FB6_Pos (6U) 08639 #define CAN_F5R2_FB6_Msk (0x1U << CAN_F5R2_FB6_Pos) /*!< 0x00000040 */ 08640 #define CAN_F5R2_FB6 CAN_F5R2_FB6_Msk /*!< Filter bit 6 */ 08641 #define CAN_F5R2_FB7_Pos (7U) 08642 #define CAN_F5R2_FB7_Msk (0x1U << CAN_F5R2_FB7_Pos) /*!< 0x00000080 */ 08643 #define CAN_F5R2_FB7 CAN_F5R2_FB7_Msk /*!< Filter bit 7 */ 08644 #define CAN_F5R2_FB8_Pos (8U) 08645 #define CAN_F5R2_FB8_Msk (0x1U << CAN_F5R2_FB8_Pos) /*!< 0x00000100 */ 08646 #define CAN_F5R2_FB8 CAN_F5R2_FB8_Msk /*!< Filter bit 8 */ 08647 #define CAN_F5R2_FB9_Pos (9U) 08648 #define CAN_F5R2_FB9_Msk (0x1U << CAN_F5R2_FB9_Pos) /*!< 0x00000200 */ 08649 #define CAN_F5R2_FB9 CAN_F5R2_FB9_Msk /*!< Filter bit 9 */ 08650 #define CAN_F5R2_FB10_Pos (10U) 08651 #define CAN_F5R2_FB10_Msk (0x1U << CAN_F5R2_FB10_Pos) /*!< 0x00000400 */ 08652 #define CAN_F5R2_FB10 CAN_F5R2_FB10_Msk /*!< Filter bit 10 */ 08653 #define CAN_F5R2_FB11_Pos (11U) 08654 #define CAN_F5R2_FB11_Msk (0x1U << CAN_F5R2_FB11_Pos) /*!< 0x00000800 */ 08655 #define CAN_F5R2_FB11 CAN_F5R2_FB11_Msk /*!< Filter bit 11 */ 08656 #define CAN_F5R2_FB12_Pos (12U) 08657 #define CAN_F5R2_FB12_Msk (0x1U << CAN_F5R2_FB12_Pos) /*!< 0x00001000 */ 08658 #define CAN_F5R2_FB12 CAN_F5R2_FB12_Msk /*!< Filter bit 12 */ 08659 #define CAN_F5R2_FB13_Pos (13U) 08660 #define CAN_F5R2_FB13_Msk (0x1U << CAN_F5R2_FB13_Pos) /*!< 0x00002000 */ 08661 #define CAN_F5R2_FB13 CAN_F5R2_FB13_Msk /*!< Filter bit 13 */ 08662 #define CAN_F5R2_FB14_Pos (14U) 08663 #define CAN_F5R2_FB14_Msk (0x1U << CAN_F5R2_FB14_Pos) /*!< 0x00004000 */ 08664 #define CAN_F5R2_FB14 CAN_F5R2_FB14_Msk /*!< Filter bit 14 */ 08665 #define CAN_F5R2_FB15_Pos (15U) 08666 #define CAN_F5R2_FB15_Msk (0x1U << CAN_F5R2_FB15_Pos) /*!< 0x00008000 */ 08667 #define CAN_F5R2_FB15 CAN_F5R2_FB15_Msk /*!< Filter bit 15 */ 08668 #define CAN_F5R2_FB16_Pos (16U) 08669 #define CAN_F5R2_FB16_Msk (0x1U << CAN_F5R2_FB16_Pos) /*!< 0x00010000 */ 08670 #define CAN_F5R2_FB16 CAN_F5R2_FB16_Msk /*!< Filter bit 16 */ 08671 #define CAN_F5R2_FB17_Pos (17U) 08672 #define CAN_F5R2_FB17_Msk (0x1U << CAN_F5R2_FB17_Pos) /*!< 0x00020000 */ 08673 #define CAN_F5R2_FB17 CAN_F5R2_FB17_Msk /*!< Filter bit 17 */ 08674 #define CAN_F5R2_FB18_Pos (18U) 08675 #define CAN_F5R2_FB18_Msk (0x1U << CAN_F5R2_FB18_Pos) /*!< 0x00040000 */ 08676 #define CAN_F5R2_FB18 CAN_F5R2_FB18_Msk /*!< Filter bit 18 */ 08677 #define CAN_F5R2_FB19_Pos (19U) 08678 #define CAN_F5R2_FB19_Msk (0x1U << CAN_F5R2_FB19_Pos) /*!< 0x00080000 */ 08679 #define CAN_F5R2_FB19 CAN_F5R2_FB19_Msk /*!< Filter bit 19 */ 08680 #define CAN_F5R2_FB20_Pos (20U) 08681 #define CAN_F5R2_FB20_Msk (0x1U << CAN_F5R2_FB20_Pos) /*!< 0x00100000 */ 08682 #define CAN_F5R2_FB20 CAN_F5R2_FB20_Msk /*!< Filter bit 20 */ 08683 #define CAN_F5R2_FB21_Pos (21U) 08684 #define CAN_F5R2_FB21_Msk (0x1U << CAN_F5R2_FB21_Pos) /*!< 0x00200000 */ 08685 #define CAN_F5R2_FB21 CAN_F5R2_FB21_Msk /*!< Filter bit 21 */ 08686 #define CAN_F5R2_FB22_Pos (22U) 08687 #define CAN_F5R2_FB22_Msk (0x1U << CAN_F5R2_FB22_Pos) /*!< 0x00400000 */ 08688 #define CAN_F5R2_FB22 CAN_F5R2_FB22_Msk /*!< Filter bit 22 */ 08689 #define CAN_F5R2_FB23_Pos (23U) 08690 #define CAN_F5R2_FB23_Msk (0x1U << CAN_F5R2_FB23_Pos) /*!< 0x00800000 */ 08691 #define CAN_F5R2_FB23 CAN_F5R2_FB23_Msk /*!< Filter bit 23 */ 08692 #define CAN_F5R2_FB24_Pos (24U) 08693 #define CAN_F5R2_FB24_Msk (0x1U << CAN_F5R2_FB24_Pos) /*!< 0x01000000 */ 08694 #define CAN_F5R2_FB24 CAN_F5R2_FB24_Msk /*!< Filter bit 24 */ 08695 #define CAN_F5R2_FB25_Pos (25U) 08696 #define CAN_F5R2_FB25_Msk (0x1U << CAN_F5R2_FB25_Pos) /*!< 0x02000000 */ 08697 #define CAN_F5R2_FB25 CAN_F5R2_FB25_Msk /*!< Filter bit 25 */ 08698 #define CAN_F5R2_FB26_Pos (26U) 08699 #define CAN_F5R2_FB26_Msk (0x1U << CAN_F5R2_FB26_Pos) /*!< 0x04000000 */ 08700 #define CAN_F5R2_FB26 CAN_F5R2_FB26_Msk /*!< Filter bit 26 */ 08701 #define CAN_F5R2_FB27_Pos (27U) 08702 #define CAN_F5R2_FB27_Msk (0x1U << CAN_F5R2_FB27_Pos) /*!< 0x08000000 */ 08703 #define CAN_F5R2_FB27 CAN_F5R2_FB27_Msk /*!< Filter bit 27 */ 08704 #define CAN_F5R2_FB28_Pos (28U) 08705 #define CAN_F5R2_FB28_Msk (0x1U << CAN_F5R2_FB28_Pos) /*!< 0x10000000 */ 08706 #define CAN_F5R2_FB28 CAN_F5R2_FB28_Msk /*!< Filter bit 28 */ 08707 #define CAN_F5R2_FB29_Pos (29U) 08708 #define CAN_F5R2_FB29_Msk (0x1U << CAN_F5R2_FB29_Pos) /*!< 0x20000000 */ 08709 #define CAN_F5R2_FB29 CAN_F5R2_FB29_Msk /*!< Filter bit 29 */ 08710 #define CAN_F5R2_FB30_Pos (30U) 08711 #define CAN_F5R2_FB30_Msk (0x1U << CAN_F5R2_FB30_Pos) /*!< 0x40000000 */ 08712 #define CAN_F5R2_FB30 CAN_F5R2_FB30_Msk /*!< Filter bit 30 */ 08713 #define CAN_F5R2_FB31_Pos (31U) 08714 #define CAN_F5R2_FB31_Msk (0x1U << CAN_F5R2_FB31_Pos) /*!< 0x80000000 */ 08715 #define CAN_F5R2_FB31 CAN_F5R2_FB31_Msk /*!< Filter bit 31 */ 08716 08717 /******************* Bit definition for CAN_F6R2 register *******************/ 08718 #define CAN_F6R2_FB0_Pos (0U) 08719 #define CAN_F6R2_FB0_Msk (0x1U << CAN_F6R2_FB0_Pos) /*!< 0x00000001 */ 08720 #define CAN_F6R2_FB0 CAN_F6R2_FB0_Msk /*!< Filter bit 0 */ 08721 #define CAN_F6R2_FB1_Pos (1U) 08722 #define CAN_F6R2_FB1_Msk (0x1U << CAN_F6R2_FB1_Pos) /*!< 0x00000002 */ 08723 #define CAN_F6R2_FB1 CAN_F6R2_FB1_Msk /*!< Filter bit 1 */ 08724 #define CAN_F6R2_FB2_Pos (2U) 08725 #define CAN_F6R2_FB2_Msk (0x1U << CAN_F6R2_FB2_Pos) /*!< 0x00000004 */ 08726 #define CAN_F6R2_FB2 CAN_F6R2_FB2_Msk /*!< Filter bit 2 */ 08727 #define CAN_F6R2_FB3_Pos (3U) 08728 #define CAN_F6R2_FB3_Msk (0x1U << CAN_F6R2_FB3_Pos) /*!< 0x00000008 */ 08729 #define CAN_F6R2_FB3 CAN_F6R2_FB3_Msk /*!< Filter bit 3 */ 08730 #define CAN_F6R2_FB4_Pos (4U) 08731 #define CAN_F6R2_FB4_Msk (0x1U << CAN_F6R2_FB4_Pos) /*!< 0x00000010 */ 08732 #define CAN_F6R2_FB4 CAN_F6R2_FB4_Msk /*!< Filter bit 4 */ 08733 #define CAN_F6R2_FB5_Pos (5U) 08734 #define CAN_F6R2_FB5_Msk (0x1U << CAN_F6R2_FB5_Pos) /*!< 0x00000020 */ 08735 #define CAN_F6R2_FB5 CAN_F6R2_FB5_Msk /*!< Filter bit 5 */ 08736 #define CAN_F6R2_FB6_Pos (6U) 08737 #define CAN_F6R2_FB6_Msk (0x1U << CAN_F6R2_FB6_Pos) /*!< 0x00000040 */ 08738 #define CAN_F6R2_FB6 CAN_F6R2_FB6_Msk /*!< Filter bit 6 */ 08739 #define CAN_F6R2_FB7_Pos (7U) 08740 #define CAN_F6R2_FB7_Msk (0x1U << CAN_F6R2_FB7_Pos) /*!< 0x00000080 */ 08741 #define CAN_F6R2_FB7 CAN_F6R2_FB7_Msk /*!< Filter bit 7 */ 08742 #define CAN_F6R2_FB8_Pos (8U) 08743 #define CAN_F6R2_FB8_Msk (0x1U << CAN_F6R2_FB8_Pos) /*!< 0x00000100 */ 08744 #define CAN_F6R2_FB8 CAN_F6R2_FB8_Msk /*!< Filter bit 8 */ 08745 #define CAN_F6R2_FB9_Pos (9U) 08746 #define CAN_F6R2_FB9_Msk (0x1U << CAN_F6R2_FB9_Pos) /*!< 0x00000200 */ 08747 #define CAN_F6R2_FB9 CAN_F6R2_FB9_Msk /*!< Filter bit 9 */ 08748 #define CAN_F6R2_FB10_Pos (10U) 08749 #define CAN_F6R2_FB10_Msk (0x1U << CAN_F6R2_FB10_Pos) /*!< 0x00000400 */ 08750 #define CAN_F6R2_FB10 CAN_F6R2_FB10_Msk /*!< Filter bit 10 */ 08751 #define CAN_F6R2_FB11_Pos (11U) 08752 #define CAN_F6R2_FB11_Msk (0x1U << CAN_F6R2_FB11_Pos) /*!< 0x00000800 */ 08753 #define CAN_F6R2_FB11 CAN_F6R2_FB11_Msk /*!< Filter bit 11 */ 08754 #define CAN_F6R2_FB12_Pos (12U) 08755 #define CAN_F6R2_FB12_Msk (0x1U << CAN_F6R2_FB12_Pos) /*!< 0x00001000 */ 08756 #define CAN_F6R2_FB12 CAN_F6R2_FB12_Msk /*!< Filter bit 12 */ 08757 #define CAN_F6R2_FB13_Pos (13U) 08758 #define CAN_F6R2_FB13_Msk (0x1U << CAN_F6R2_FB13_Pos) /*!< 0x00002000 */ 08759 #define CAN_F6R2_FB13 CAN_F6R2_FB13_Msk /*!< Filter bit 13 */ 08760 #define CAN_F6R2_FB14_Pos (14U) 08761 #define CAN_F6R2_FB14_Msk (0x1U << CAN_F6R2_FB14_Pos) /*!< 0x00004000 */ 08762 #define CAN_F6R2_FB14 CAN_F6R2_FB14_Msk /*!< Filter bit 14 */ 08763 #define CAN_F6R2_FB15_Pos (15U) 08764 #define CAN_F6R2_FB15_Msk (0x1U << CAN_F6R2_FB15_Pos) /*!< 0x00008000 */ 08765 #define CAN_F6R2_FB15 CAN_F6R2_FB15_Msk /*!< Filter bit 15 */ 08766 #define CAN_F6R2_FB16_Pos (16U) 08767 #define CAN_F6R2_FB16_Msk (0x1U << CAN_F6R2_FB16_Pos) /*!< 0x00010000 */ 08768 #define CAN_F6R2_FB16 CAN_F6R2_FB16_Msk /*!< Filter bit 16 */ 08769 #define CAN_F6R2_FB17_Pos (17U) 08770 #define CAN_F6R2_FB17_Msk (0x1U << CAN_F6R2_FB17_Pos) /*!< 0x00020000 */ 08771 #define CAN_F6R2_FB17 CAN_F6R2_FB17_Msk /*!< Filter bit 17 */ 08772 #define CAN_F6R2_FB18_Pos (18U) 08773 #define CAN_F6R2_FB18_Msk (0x1U << CAN_F6R2_FB18_Pos) /*!< 0x00040000 */ 08774 #define CAN_F6R2_FB18 CAN_F6R2_FB18_Msk /*!< Filter bit 18 */ 08775 #define CAN_F6R2_FB19_Pos (19U) 08776 #define CAN_F6R2_FB19_Msk (0x1U << CAN_F6R2_FB19_Pos) /*!< 0x00080000 */ 08777 #define CAN_F6R2_FB19 CAN_F6R2_FB19_Msk /*!< Filter bit 19 */ 08778 #define CAN_F6R2_FB20_Pos (20U) 08779 #define CAN_F6R2_FB20_Msk (0x1U << CAN_F6R2_FB20_Pos) /*!< 0x00100000 */ 08780 #define CAN_F6R2_FB20 CAN_F6R2_FB20_Msk /*!< Filter bit 20 */ 08781 #define CAN_F6R2_FB21_Pos (21U) 08782 #define CAN_F6R2_FB21_Msk (0x1U << CAN_F6R2_FB21_Pos) /*!< 0x00200000 */ 08783 #define CAN_F6R2_FB21 CAN_F6R2_FB21_Msk /*!< Filter bit 21 */ 08784 #define CAN_F6R2_FB22_Pos (22U) 08785 #define CAN_F6R2_FB22_Msk (0x1U << CAN_F6R2_FB22_Pos) /*!< 0x00400000 */ 08786 #define CAN_F6R2_FB22 CAN_F6R2_FB22_Msk /*!< Filter bit 22 */ 08787 #define CAN_F6R2_FB23_Pos (23U) 08788 #define CAN_F6R2_FB23_Msk (0x1U << CAN_F6R2_FB23_Pos) /*!< 0x00800000 */ 08789 #define CAN_F6R2_FB23 CAN_F6R2_FB23_Msk /*!< Filter bit 23 */ 08790 #define CAN_F6R2_FB24_Pos (24U) 08791 #define CAN_F6R2_FB24_Msk (0x1U << CAN_F6R2_FB24_Pos) /*!< 0x01000000 */ 08792 #define CAN_F6R2_FB24 CAN_F6R2_FB24_Msk /*!< Filter bit 24 */ 08793 #define CAN_F6R2_FB25_Pos (25U) 08794 #define CAN_F6R2_FB25_Msk (0x1U << CAN_F6R2_FB25_Pos) /*!< 0x02000000 */ 08795 #define CAN_F6R2_FB25 CAN_F6R2_FB25_Msk /*!< Filter bit 25 */ 08796 #define CAN_F6R2_FB26_Pos (26U) 08797 #define CAN_F6R2_FB26_Msk (0x1U << CAN_F6R2_FB26_Pos) /*!< 0x04000000 */ 08798 #define CAN_F6R2_FB26 CAN_F6R2_FB26_Msk /*!< Filter bit 26 */ 08799 #define CAN_F6R2_FB27_Pos (27U) 08800 #define CAN_F6R2_FB27_Msk (0x1U << CAN_F6R2_FB27_Pos) /*!< 0x08000000 */ 08801 #define CAN_F6R2_FB27 CAN_F6R2_FB27_Msk /*!< Filter bit 27 */ 08802 #define CAN_F6R2_FB28_Pos (28U) 08803 #define CAN_F6R2_FB28_Msk (0x1U << CAN_F6R2_FB28_Pos) /*!< 0x10000000 */ 08804 #define CAN_F6R2_FB28 CAN_F6R2_FB28_Msk /*!< Filter bit 28 */ 08805 #define CAN_F6R2_FB29_Pos (29U) 08806 #define CAN_F6R2_FB29_Msk (0x1U << CAN_F6R2_FB29_Pos) /*!< 0x20000000 */ 08807 #define CAN_F6R2_FB29 CAN_F6R2_FB29_Msk /*!< Filter bit 29 */ 08808 #define CAN_F6R2_FB30_Pos (30U) 08809 #define CAN_F6R2_FB30_Msk (0x1U << CAN_F6R2_FB30_Pos) /*!< 0x40000000 */ 08810 #define CAN_F6R2_FB30 CAN_F6R2_FB30_Msk /*!< Filter bit 30 */ 08811 #define CAN_F6R2_FB31_Pos (31U) 08812 #define CAN_F6R2_FB31_Msk (0x1U << CAN_F6R2_FB31_Pos) /*!< 0x80000000 */ 08813 #define CAN_F6R2_FB31 CAN_F6R2_FB31_Msk /*!< Filter bit 31 */ 08814 08815 /******************* Bit definition for CAN_F7R2 register *******************/ 08816 #define CAN_F7R2_FB0_Pos (0U) 08817 #define CAN_F7R2_FB0_Msk (0x1U << CAN_F7R2_FB0_Pos) /*!< 0x00000001 */ 08818 #define CAN_F7R2_FB0 CAN_F7R2_FB0_Msk /*!< Filter bit 0 */ 08819 #define CAN_F7R2_FB1_Pos (1U) 08820 #define CAN_F7R2_FB1_Msk (0x1U << CAN_F7R2_FB1_Pos) /*!< 0x00000002 */ 08821 #define CAN_F7R2_FB1 CAN_F7R2_FB1_Msk /*!< Filter bit 1 */ 08822 #define CAN_F7R2_FB2_Pos (2U) 08823 #define CAN_F7R2_FB2_Msk (0x1U << CAN_F7R2_FB2_Pos) /*!< 0x00000004 */ 08824 #define CAN_F7R2_FB2 CAN_F7R2_FB2_Msk /*!< Filter bit 2 */ 08825 #define CAN_F7R2_FB3_Pos (3U) 08826 #define CAN_F7R2_FB3_Msk (0x1U << CAN_F7R2_FB3_Pos) /*!< 0x00000008 */ 08827 #define CAN_F7R2_FB3 CAN_F7R2_FB3_Msk /*!< Filter bit 3 */ 08828 #define CAN_F7R2_FB4_Pos (4U) 08829 #define CAN_F7R2_FB4_Msk (0x1U << CAN_F7R2_FB4_Pos) /*!< 0x00000010 */ 08830 #define CAN_F7R2_FB4 CAN_F7R2_FB4_Msk /*!< Filter bit 4 */ 08831 #define CAN_F7R2_FB5_Pos (5U) 08832 #define CAN_F7R2_FB5_Msk (0x1U << CAN_F7R2_FB5_Pos) /*!< 0x00000020 */ 08833 #define CAN_F7R2_FB5 CAN_F7R2_FB5_Msk /*!< Filter bit 5 */ 08834 #define CAN_F7R2_FB6_Pos (6U) 08835 #define CAN_F7R2_FB6_Msk (0x1U << CAN_F7R2_FB6_Pos) /*!< 0x00000040 */ 08836 #define CAN_F7R2_FB6 CAN_F7R2_FB6_Msk /*!< Filter bit 6 */ 08837 #define CAN_F7R2_FB7_Pos (7U) 08838 #define CAN_F7R2_FB7_Msk (0x1U << CAN_F7R2_FB7_Pos) /*!< 0x00000080 */ 08839 #define CAN_F7R2_FB7 CAN_F7R2_FB7_Msk /*!< Filter bit 7 */ 08840 #define CAN_F7R2_FB8_Pos (8U) 08841 #define CAN_F7R2_FB8_Msk (0x1U << CAN_F7R2_FB8_Pos) /*!< 0x00000100 */ 08842 #define CAN_F7R2_FB8 CAN_F7R2_FB8_Msk /*!< Filter bit 8 */ 08843 #define CAN_F7R2_FB9_Pos (9U) 08844 #define CAN_F7R2_FB9_Msk (0x1U << CAN_F7R2_FB9_Pos) /*!< 0x00000200 */ 08845 #define CAN_F7R2_FB9 CAN_F7R2_FB9_Msk /*!< Filter bit 9 */ 08846 #define CAN_F7R2_FB10_Pos (10U) 08847 #define CAN_F7R2_FB10_Msk (0x1U << CAN_F7R2_FB10_Pos) /*!< 0x00000400 */ 08848 #define CAN_F7R2_FB10 CAN_F7R2_FB10_Msk /*!< Filter bit 10 */ 08849 #define CAN_F7R2_FB11_Pos (11U) 08850 #define CAN_F7R2_FB11_Msk (0x1U << CAN_F7R2_FB11_Pos) /*!< 0x00000800 */ 08851 #define CAN_F7R2_FB11 CAN_F7R2_FB11_Msk /*!< Filter bit 11 */ 08852 #define CAN_F7R2_FB12_Pos (12U) 08853 #define CAN_F7R2_FB12_Msk (0x1U << CAN_F7R2_FB12_Pos) /*!< 0x00001000 */ 08854 #define CAN_F7R2_FB12 CAN_F7R2_FB12_Msk /*!< Filter bit 12 */ 08855 #define CAN_F7R2_FB13_Pos (13U) 08856 #define CAN_F7R2_FB13_Msk (0x1U << CAN_F7R2_FB13_Pos) /*!< 0x00002000 */ 08857 #define CAN_F7R2_FB13 CAN_F7R2_FB13_Msk /*!< Filter bit 13 */ 08858 #define CAN_F7R2_FB14_Pos (14U) 08859 #define CAN_F7R2_FB14_Msk (0x1U << CAN_F7R2_FB14_Pos) /*!< 0x00004000 */ 08860 #define CAN_F7R2_FB14 CAN_F7R2_FB14_Msk /*!< Filter bit 14 */ 08861 #define CAN_F7R2_FB15_Pos (15U) 08862 #define CAN_F7R2_FB15_Msk (0x1U << CAN_F7R2_FB15_Pos) /*!< 0x00008000 */ 08863 #define CAN_F7R2_FB15 CAN_F7R2_FB15_Msk /*!< Filter bit 15 */ 08864 #define CAN_F7R2_FB16_Pos (16U) 08865 #define CAN_F7R2_FB16_Msk (0x1U << CAN_F7R2_FB16_Pos) /*!< 0x00010000 */ 08866 #define CAN_F7R2_FB16 CAN_F7R2_FB16_Msk /*!< Filter bit 16 */ 08867 #define CAN_F7R2_FB17_Pos (17U) 08868 #define CAN_F7R2_FB17_Msk (0x1U << CAN_F7R2_FB17_Pos) /*!< 0x00020000 */ 08869 #define CAN_F7R2_FB17 CAN_F7R2_FB17_Msk /*!< Filter bit 17 */ 08870 #define CAN_F7R2_FB18_Pos (18U) 08871 #define CAN_F7R2_FB18_Msk (0x1U << CAN_F7R2_FB18_Pos) /*!< 0x00040000 */ 08872 #define CAN_F7R2_FB18 CAN_F7R2_FB18_Msk /*!< Filter bit 18 */ 08873 #define CAN_F7R2_FB19_Pos (19U) 08874 #define CAN_F7R2_FB19_Msk (0x1U << CAN_F7R2_FB19_Pos) /*!< 0x00080000 */ 08875 #define CAN_F7R2_FB19 CAN_F7R2_FB19_Msk /*!< Filter bit 19 */ 08876 #define CAN_F7R2_FB20_Pos (20U) 08877 #define CAN_F7R2_FB20_Msk (0x1U << CAN_F7R2_FB20_Pos) /*!< 0x00100000 */ 08878 #define CAN_F7R2_FB20 CAN_F7R2_FB20_Msk /*!< Filter bit 20 */ 08879 #define CAN_F7R2_FB21_Pos (21U) 08880 #define CAN_F7R2_FB21_Msk (0x1U << CAN_F7R2_FB21_Pos) /*!< 0x00200000 */ 08881 #define CAN_F7R2_FB21 CAN_F7R2_FB21_Msk /*!< Filter bit 21 */ 08882 #define CAN_F7R2_FB22_Pos (22U) 08883 #define CAN_F7R2_FB22_Msk (0x1U << CAN_F7R2_FB22_Pos) /*!< 0x00400000 */ 08884 #define CAN_F7R2_FB22 CAN_F7R2_FB22_Msk /*!< Filter bit 22 */ 08885 #define CAN_F7R2_FB23_Pos (23U) 08886 #define CAN_F7R2_FB23_Msk (0x1U << CAN_F7R2_FB23_Pos) /*!< 0x00800000 */ 08887 #define CAN_F7R2_FB23 CAN_F7R2_FB23_Msk /*!< Filter bit 23 */ 08888 #define CAN_F7R2_FB24_Pos (24U) 08889 #define CAN_F7R2_FB24_Msk (0x1U << CAN_F7R2_FB24_Pos) /*!< 0x01000000 */ 08890 #define CAN_F7R2_FB24 CAN_F7R2_FB24_Msk /*!< Filter bit 24 */ 08891 #define CAN_F7R2_FB25_Pos (25U) 08892 #define CAN_F7R2_FB25_Msk (0x1U << CAN_F7R2_FB25_Pos) /*!< 0x02000000 */ 08893 #define CAN_F7R2_FB25 CAN_F7R2_FB25_Msk /*!< Filter bit 25 */ 08894 #define CAN_F7R2_FB26_Pos (26U) 08895 #define CAN_F7R2_FB26_Msk (0x1U << CAN_F7R2_FB26_Pos) /*!< 0x04000000 */ 08896 #define CAN_F7R2_FB26 CAN_F7R2_FB26_Msk /*!< Filter bit 26 */ 08897 #define CAN_F7R2_FB27_Pos (27U) 08898 #define CAN_F7R2_FB27_Msk (0x1U << CAN_F7R2_FB27_Pos) /*!< 0x08000000 */ 08899 #define CAN_F7R2_FB27 CAN_F7R2_FB27_Msk /*!< Filter bit 27 */ 08900 #define CAN_F7R2_FB28_Pos (28U) 08901 #define CAN_F7R2_FB28_Msk (0x1U << CAN_F7R2_FB28_Pos) /*!< 0x10000000 */ 08902 #define CAN_F7R2_FB28 CAN_F7R2_FB28_Msk /*!< Filter bit 28 */ 08903 #define CAN_F7R2_FB29_Pos (29U) 08904 #define CAN_F7R2_FB29_Msk (0x1U << CAN_F7R2_FB29_Pos) /*!< 0x20000000 */ 08905 #define CAN_F7R2_FB29 CAN_F7R2_FB29_Msk /*!< Filter bit 29 */ 08906 #define CAN_F7R2_FB30_Pos (30U) 08907 #define CAN_F7R2_FB30_Msk (0x1U << CAN_F7R2_FB30_Pos) /*!< 0x40000000 */ 08908 #define CAN_F7R2_FB30 CAN_F7R2_FB30_Msk /*!< Filter bit 30 */ 08909 #define CAN_F7R2_FB31_Pos (31U) 08910 #define CAN_F7R2_FB31_Msk (0x1U << CAN_F7R2_FB31_Pos) /*!< 0x80000000 */ 08911 #define CAN_F7R2_FB31 CAN_F7R2_FB31_Msk /*!< Filter bit 31 */ 08912 08913 /******************* Bit definition for CAN_F8R2 register *******************/ 08914 #define CAN_F8R2_FB0_Pos (0U) 08915 #define CAN_F8R2_FB0_Msk (0x1U << CAN_F8R2_FB0_Pos) /*!< 0x00000001 */ 08916 #define CAN_F8R2_FB0 CAN_F8R2_FB0_Msk /*!< Filter bit 0 */ 08917 #define CAN_F8R2_FB1_Pos (1U) 08918 #define CAN_F8R2_FB1_Msk (0x1U << CAN_F8R2_FB1_Pos) /*!< 0x00000002 */ 08919 #define CAN_F8R2_FB1 CAN_F8R2_FB1_Msk /*!< Filter bit 1 */ 08920 #define CAN_F8R2_FB2_Pos (2U) 08921 #define CAN_F8R2_FB2_Msk (0x1U << CAN_F8R2_FB2_Pos) /*!< 0x00000004 */ 08922 #define CAN_F8R2_FB2 CAN_F8R2_FB2_Msk /*!< Filter bit 2 */ 08923 #define CAN_F8R2_FB3_Pos (3U) 08924 #define CAN_F8R2_FB3_Msk (0x1U << CAN_F8R2_FB3_Pos) /*!< 0x00000008 */ 08925 #define CAN_F8R2_FB3 CAN_F8R2_FB3_Msk /*!< Filter bit 3 */ 08926 #define CAN_F8R2_FB4_Pos (4U) 08927 #define CAN_F8R2_FB4_Msk (0x1U << CAN_F8R2_FB4_Pos) /*!< 0x00000010 */ 08928 #define CAN_F8R2_FB4 CAN_F8R2_FB4_Msk /*!< Filter bit 4 */ 08929 #define CAN_F8R2_FB5_Pos (5U) 08930 #define CAN_F8R2_FB5_Msk (0x1U << CAN_F8R2_FB5_Pos) /*!< 0x00000020 */ 08931 #define CAN_F8R2_FB5 CAN_F8R2_FB5_Msk /*!< Filter bit 5 */ 08932 #define CAN_F8R2_FB6_Pos (6U) 08933 #define CAN_F8R2_FB6_Msk (0x1U << CAN_F8R2_FB6_Pos) /*!< 0x00000040 */ 08934 #define CAN_F8R2_FB6 CAN_F8R2_FB6_Msk /*!< Filter bit 6 */ 08935 #define CAN_F8R2_FB7_Pos (7U) 08936 #define CAN_F8R2_FB7_Msk (0x1U << CAN_F8R2_FB7_Pos) /*!< 0x00000080 */ 08937 #define CAN_F8R2_FB7 CAN_F8R2_FB7_Msk /*!< Filter bit 7 */ 08938 #define CAN_F8R2_FB8_Pos (8U) 08939 #define CAN_F8R2_FB8_Msk (0x1U << CAN_F8R2_FB8_Pos) /*!< 0x00000100 */ 08940 #define CAN_F8R2_FB8 CAN_F8R2_FB8_Msk /*!< Filter bit 8 */ 08941 #define CAN_F8R2_FB9_Pos (9U) 08942 #define CAN_F8R2_FB9_Msk (0x1U << CAN_F8R2_FB9_Pos) /*!< 0x00000200 */ 08943 #define CAN_F8R2_FB9 CAN_F8R2_FB9_Msk /*!< Filter bit 9 */ 08944 #define CAN_F8R2_FB10_Pos (10U) 08945 #define CAN_F8R2_FB10_Msk (0x1U << CAN_F8R2_FB10_Pos) /*!< 0x00000400 */ 08946 #define CAN_F8R2_FB10 CAN_F8R2_FB10_Msk /*!< Filter bit 10 */ 08947 #define CAN_F8R2_FB11_Pos (11U) 08948 #define CAN_F8R2_FB11_Msk (0x1U << CAN_F8R2_FB11_Pos) /*!< 0x00000800 */ 08949 #define CAN_F8R2_FB11 CAN_F8R2_FB11_Msk /*!< Filter bit 11 */ 08950 #define CAN_F8R2_FB12_Pos (12U) 08951 #define CAN_F8R2_FB12_Msk (0x1U << CAN_F8R2_FB12_Pos) /*!< 0x00001000 */ 08952 #define CAN_F8R2_FB12 CAN_F8R2_FB12_Msk /*!< Filter bit 12 */ 08953 #define CAN_F8R2_FB13_Pos (13U) 08954 #define CAN_F8R2_FB13_Msk (0x1U << CAN_F8R2_FB13_Pos) /*!< 0x00002000 */ 08955 #define CAN_F8R2_FB13 CAN_F8R2_FB13_Msk /*!< Filter bit 13 */ 08956 #define CAN_F8R2_FB14_Pos (14U) 08957 #define CAN_F8R2_FB14_Msk (0x1U << CAN_F8R2_FB14_Pos) /*!< 0x00004000 */ 08958 #define CAN_F8R2_FB14 CAN_F8R2_FB14_Msk /*!< Filter bit 14 */ 08959 #define CAN_F8R2_FB15_Pos (15U) 08960 #define CAN_F8R2_FB15_Msk (0x1U << CAN_F8R2_FB15_Pos) /*!< 0x00008000 */ 08961 #define CAN_F8R2_FB15 CAN_F8R2_FB15_Msk /*!< Filter bit 15 */ 08962 #define CAN_F8R2_FB16_Pos (16U) 08963 #define CAN_F8R2_FB16_Msk (0x1U << CAN_F8R2_FB16_Pos) /*!< 0x00010000 */ 08964 #define CAN_F8R2_FB16 CAN_F8R2_FB16_Msk /*!< Filter bit 16 */ 08965 #define CAN_F8R2_FB17_Pos (17U) 08966 #define CAN_F8R2_FB17_Msk (0x1U << CAN_F8R2_FB17_Pos) /*!< 0x00020000 */ 08967 #define CAN_F8R2_FB17 CAN_F8R2_FB17_Msk /*!< Filter bit 17 */ 08968 #define CAN_F8R2_FB18_Pos (18U) 08969 #define CAN_F8R2_FB18_Msk (0x1U << CAN_F8R2_FB18_Pos) /*!< 0x00040000 */ 08970 #define CAN_F8R2_FB18 CAN_F8R2_FB18_Msk /*!< Filter bit 18 */ 08971 #define CAN_F8R2_FB19_Pos (19U) 08972 #define CAN_F8R2_FB19_Msk (0x1U << CAN_F8R2_FB19_Pos) /*!< 0x00080000 */ 08973 #define CAN_F8R2_FB19 CAN_F8R2_FB19_Msk /*!< Filter bit 19 */ 08974 #define CAN_F8R2_FB20_Pos (20U) 08975 #define CAN_F8R2_FB20_Msk (0x1U << CAN_F8R2_FB20_Pos) /*!< 0x00100000 */ 08976 #define CAN_F8R2_FB20 CAN_F8R2_FB20_Msk /*!< Filter bit 20 */ 08977 #define CAN_F8R2_FB21_Pos (21U) 08978 #define CAN_F8R2_FB21_Msk (0x1U << CAN_F8R2_FB21_Pos) /*!< 0x00200000 */ 08979 #define CAN_F8R2_FB21 CAN_F8R2_FB21_Msk /*!< Filter bit 21 */ 08980 #define CAN_F8R2_FB22_Pos (22U) 08981 #define CAN_F8R2_FB22_Msk (0x1U << CAN_F8R2_FB22_Pos) /*!< 0x00400000 */ 08982 #define CAN_F8R2_FB22 CAN_F8R2_FB22_Msk /*!< Filter bit 22 */ 08983 #define CAN_F8R2_FB23_Pos (23U) 08984 #define CAN_F8R2_FB23_Msk (0x1U << CAN_F8R2_FB23_Pos) /*!< 0x00800000 */ 08985 #define CAN_F8R2_FB23 CAN_F8R2_FB23_Msk /*!< Filter bit 23 */ 08986 #define CAN_F8R2_FB24_Pos (24U) 08987 #define CAN_F8R2_FB24_Msk (0x1U << CAN_F8R2_FB24_Pos) /*!< 0x01000000 */ 08988 #define CAN_F8R2_FB24 CAN_F8R2_FB24_Msk /*!< Filter bit 24 */ 08989 #define CAN_F8R2_FB25_Pos (25U) 08990 #define CAN_F8R2_FB25_Msk (0x1U << CAN_F8R2_FB25_Pos) /*!< 0x02000000 */ 08991 #define CAN_F8R2_FB25 CAN_F8R2_FB25_Msk /*!< Filter bit 25 */ 08992 #define CAN_F8R2_FB26_Pos (26U) 08993 #define CAN_F8R2_FB26_Msk (0x1U << CAN_F8R2_FB26_Pos) /*!< 0x04000000 */ 08994 #define CAN_F8R2_FB26 CAN_F8R2_FB26_Msk /*!< Filter bit 26 */ 08995 #define CAN_F8R2_FB27_Pos (27U) 08996 #define CAN_F8R2_FB27_Msk (0x1U << CAN_F8R2_FB27_Pos) /*!< 0x08000000 */ 08997 #define CAN_F8R2_FB27 CAN_F8R2_FB27_Msk /*!< Filter bit 27 */ 08998 #define CAN_F8R2_FB28_Pos (28U) 08999 #define CAN_F8R2_FB28_Msk (0x1U << CAN_F8R2_FB28_Pos) /*!< 0x10000000 */ 09000 #define CAN_F8R2_FB28 CAN_F8R2_FB28_Msk /*!< Filter bit 28 */ 09001 #define CAN_F8R2_FB29_Pos (29U) 09002 #define CAN_F8R2_FB29_Msk (0x1U << CAN_F8R2_FB29_Pos) /*!< 0x20000000 */ 09003 #define CAN_F8R2_FB29 CAN_F8R2_FB29_Msk /*!< Filter bit 29 */ 09004 #define CAN_F8R2_FB30_Pos (30U) 09005 #define CAN_F8R2_FB30_Msk (0x1U << CAN_F8R2_FB30_Pos) /*!< 0x40000000 */ 09006 #define CAN_F8R2_FB30 CAN_F8R2_FB30_Msk /*!< Filter bit 30 */ 09007 #define CAN_F8R2_FB31_Pos (31U) 09008 #define CAN_F8R2_FB31_Msk (0x1U << CAN_F8R2_FB31_Pos) /*!< 0x80000000 */ 09009 #define CAN_F8R2_FB31 CAN_F8R2_FB31_Msk /*!< Filter bit 31 */ 09010 09011 /******************* Bit definition for CAN_F9R2 register *******************/ 09012 #define CAN_F9R2_FB0_Pos (0U) 09013 #define CAN_F9R2_FB0_Msk (0x1U << CAN_F9R2_FB0_Pos) /*!< 0x00000001 */ 09014 #define CAN_F9R2_FB0 CAN_F9R2_FB0_Msk /*!< Filter bit 0 */ 09015 #define CAN_F9R2_FB1_Pos (1U) 09016 #define CAN_F9R2_FB1_Msk (0x1U << CAN_F9R2_FB1_Pos) /*!< 0x00000002 */ 09017 #define CAN_F9R2_FB1 CAN_F9R2_FB1_Msk /*!< Filter bit 1 */ 09018 #define CAN_F9R2_FB2_Pos (2U) 09019 #define CAN_F9R2_FB2_Msk (0x1U << CAN_F9R2_FB2_Pos) /*!< 0x00000004 */ 09020 #define CAN_F9R2_FB2 CAN_F9R2_FB2_Msk /*!< Filter bit 2 */ 09021 #define CAN_F9R2_FB3_Pos (3U) 09022 #define CAN_F9R2_FB3_Msk (0x1U << CAN_F9R2_FB3_Pos) /*!< 0x00000008 */ 09023 #define CAN_F9R2_FB3 CAN_F9R2_FB3_Msk /*!< Filter bit 3 */ 09024 #define CAN_F9R2_FB4_Pos (4U) 09025 #define CAN_F9R2_FB4_Msk (0x1U << CAN_F9R2_FB4_Pos) /*!< 0x00000010 */ 09026 #define CAN_F9R2_FB4 CAN_F9R2_FB4_Msk /*!< Filter bit 4 */ 09027 #define CAN_F9R2_FB5_Pos (5U) 09028 #define CAN_F9R2_FB5_Msk (0x1U << CAN_F9R2_FB5_Pos) /*!< 0x00000020 */ 09029 #define CAN_F9R2_FB5 CAN_F9R2_FB5_Msk /*!< Filter bit 5 */ 09030 #define CAN_F9R2_FB6_Pos (6U) 09031 #define CAN_F9R2_FB6_Msk (0x1U << CAN_F9R2_FB6_Pos) /*!< 0x00000040 */ 09032 #define CAN_F9R2_FB6 CAN_F9R2_FB6_Msk /*!< Filter bit 6 */ 09033 #define CAN_F9R2_FB7_Pos (7U) 09034 #define CAN_F9R2_FB7_Msk (0x1U << CAN_F9R2_FB7_Pos) /*!< 0x00000080 */ 09035 #define CAN_F9R2_FB7 CAN_F9R2_FB7_Msk /*!< Filter bit 7 */ 09036 #define CAN_F9R2_FB8_Pos (8U) 09037 #define CAN_F9R2_FB8_Msk (0x1U << CAN_F9R2_FB8_Pos) /*!< 0x00000100 */ 09038 #define CAN_F9R2_FB8 CAN_F9R2_FB8_Msk /*!< Filter bit 8 */ 09039 #define CAN_F9R2_FB9_Pos (9U) 09040 #define CAN_F9R2_FB9_Msk (0x1U << CAN_F9R2_FB9_Pos) /*!< 0x00000200 */ 09041 #define CAN_F9R2_FB9 CAN_F9R2_FB9_Msk /*!< Filter bit 9 */ 09042 #define CAN_F9R2_FB10_Pos (10U) 09043 #define CAN_F9R2_FB10_Msk (0x1U << CAN_F9R2_FB10_Pos) /*!< 0x00000400 */ 09044 #define CAN_F9R2_FB10 CAN_F9R2_FB10_Msk /*!< Filter bit 10 */ 09045 #define CAN_F9R2_FB11_Pos (11U) 09046 #define CAN_F9R2_FB11_Msk (0x1U << CAN_F9R2_FB11_Pos) /*!< 0x00000800 */ 09047 #define CAN_F9R2_FB11 CAN_F9R2_FB11_Msk /*!< Filter bit 11 */ 09048 #define CAN_F9R2_FB12_Pos (12U) 09049 #define CAN_F9R2_FB12_Msk (0x1U << CAN_F9R2_FB12_Pos) /*!< 0x00001000 */ 09050 #define CAN_F9R2_FB12 CAN_F9R2_FB12_Msk /*!< Filter bit 12 */ 09051 #define CAN_F9R2_FB13_Pos (13U) 09052 #define CAN_F9R2_FB13_Msk (0x1U << CAN_F9R2_FB13_Pos) /*!< 0x00002000 */ 09053 #define CAN_F9R2_FB13 CAN_F9R2_FB13_Msk /*!< Filter bit 13 */ 09054 #define CAN_F9R2_FB14_Pos (14U) 09055 #define CAN_F9R2_FB14_Msk (0x1U << CAN_F9R2_FB14_Pos) /*!< 0x00004000 */ 09056 #define CAN_F9R2_FB14 CAN_F9R2_FB14_Msk /*!< Filter bit 14 */ 09057 #define CAN_F9R2_FB15_Pos (15U) 09058 #define CAN_F9R2_FB15_Msk (0x1U << CAN_F9R2_FB15_Pos) /*!< 0x00008000 */ 09059 #define CAN_F9R2_FB15 CAN_F9R2_FB15_Msk /*!< Filter bit 15 */ 09060 #define CAN_F9R2_FB16_Pos (16U) 09061 #define CAN_F9R2_FB16_Msk (0x1U << CAN_F9R2_FB16_Pos) /*!< 0x00010000 */ 09062 #define CAN_F9R2_FB16 CAN_F9R2_FB16_Msk /*!< Filter bit 16 */ 09063 #define CAN_F9R2_FB17_Pos (17U) 09064 #define CAN_F9R2_FB17_Msk (0x1U << CAN_F9R2_FB17_Pos) /*!< 0x00020000 */ 09065 #define CAN_F9R2_FB17 CAN_F9R2_FB17_Msk /*!< Filter bit 17 */ 09066 #define CAN_F9R2_FB18_Pos (18U) 09067 #define CAN_F9R2_FB18_Msk (0x1U << CAN_F9R2_FB18_Pos) /*!< 0x00040000 */ 09068 #define CAN_F9R2_FB18 CAN_F9R2_FB18_Msk /*!< Filter bit 18 */ 09069 #define CAN_F9R2_FB19_Pos (19U) 09070 #define CAN_F9R2_FB19_Msk (0x1U << CAN_F9R2_FB19_Pos) /*!< 0x00080000 */ 09071 #define CAN_F9R2_FB19 CAN_F9R2_FB19_Msk /*!< Filter bit 19 */ 09072 #define CAN_F9R2_FB20_Pos (20U) 09073 #define CAN_F9R2_FB20_Msk (0x1U << CAN_F9R2_FB20_Pos) /*!< 0x00100000 */ 09074 #define CAN_F9R2_FB20 CAN_F9R2_FB20_Msk /*!< Filter bit 20 */ 09075 #define CAN_F9R2_FB21_Pos (21U) 09076 #define CAN_F9R2_FB21_Msk (0x1U << CAN_F9R2_FB21_Pos) /*!< 0x00200000 */ 09077 #define CAN_F9R2_FB21 CAN_F9R2_FB21_Msk /*!< Filter bit 21 */ 09078 #define CAN_F9R2_FB22_Pos (22U) 09079 #define CAN_F9R2_FB22_Msk (0x1U << CAN_F9R2_FB22_Pos) /*!< 0x00400000 */ 09080 #define CAN_F9R2_FB22 CAN_F9R2_FB22_Msk /*!< Filter bit 22 */ 09081 #define CAN_F9R2_FB23_Pos (23U) 09082 #define CAN_F9R2_FB23_Msk (0x1U << CAN_F9R2_FB23_Pos) /*!< 0x00800000 */ 09083 #define CAN_F9R2_FB23 CAN_F9R2_FB23_Msk /*!< Filter bit 23 */ 09084 #define CAN_F9R2_FB24_Pos (24U) 09085 #define CAN_F9R2_FB24_Msk (0x1U << CAN_F9R2_FB24_Pos) /*!< 0x01000000 */ 09086 #define CAN_F9R2_FB24 CAN_F9R2_FB24_Msk /*!< Filter bit 24 */ 09087 #define CAN_F9R2_FB25_Pos (25U) 09088 #define CAN_F9R2_FB25_Msk (0x1U << CAN_F9R2_FB25_Pos) /*!< 0x02000000 */ 09089 #define CAN_F9R2_FB25 CAN_F9R2_FB25_Msk /*!< Filter bit 25 */ 09090 #define CAN_F9R2_FB26_Pos (26U) 09091 #define CAN_F9R2_FB26_Msk (0x1U << CAN_F9R2_FB26_Pos) /*!< 0x04000000 */ 09092 #define CAN_F9R2_FB26 CAN_F9R2_FB26_Msk /*!< Filter bit 26 */ 09093 #define CAN_F9R2_FB27_Pos (27U) 09094 #define CAN_F9R2_FB27_Msk (0x1U << CAN_F9R2_FB27_Pos) /*!< 0x08000000 */ 09095 #define CAN_F9R2_FB27 CAN_F9R2_FB27_Msk /*!< Filter bit 27 */ 09096 #define CAN_F9R2_FB28_Pos (28U) 09097 #define CAN_F9R2_FB28_Msk (0x1U << CAN_F9R2_FB28_Pos) /*!< 0x10000000 */ 09098 #define CAN_F9R2_FB28 CAN_F9R2_FB28_Msk /*!< Filter bit 28 */ 09099 #define CAN_F9R2_FB29_Pos (29U) 09100 #define CAN_F9R2_FB29_Msk (0x1U << CAN_F9R2_FB29_Pos) /*!< 0x20000000 */ 09101 #define CAN_F9R2_FB29 CAN_F9R2_FB29_Msk /*!< Filter bit 29 */ 09102 #define CAN_F9R2_FB30_Pos (30U) 09103 #define CAN_F9R2_FB30_Msk (0x1U << CAN_F9R2_FB30_Pos) /*!< 0x40000000 */ 09104 #define CAN_F9R2_FB30 CAN_F9R2_FB30_Msk /*!< Filter bit 30 */ 09105 #define CAN_F9R2_FB31_Pos (31U) 09106 #define CAN_F9R2_FB31_Msk (0x1U << CAN_F9R2_FB31_Pos) /*!< 0x80000000 */ 09107 #define CAN_F9R2_FB31 CAN_F9R2_FB31_Msk /*!< Filter bit 31 */ 09108 09109 /******************* Bit definition for CAN_F10R2 register ******************/ 09110 #define CAN_F10R2_FB0_Pos (0U) 09111 #define CAN_F10R2_FB0_Msk (0x1U << CAN_F10R2_FB0_Pos) /*!< 0x00000001 */ 09112 #define CAN_F10R2_FB0 CAN_F10R2_FB0_Msk /*!< Filter bit 0 */ 09113 #define CAN_F10R2_FB1_Pos (1U) 09114 #define CAN_F10R2_FB1_Msk (0x1U << CAN_F10R2_FB1_Pos) /*!< 0x00000002 */ 09115 #define CAN_F10R2_FB1 CAN_F10R2_FB1_Msk /*!< Filter bit 1 */ 09116 #define CAN_F10R2_FB2_Pos (2U) 09117 #define CAN_F10R2_FB2_Msk (0x1U << CAN_F10R2_FB2_Pos) /*!< 0x00000004 */ 09118 #define CAN_F10R2_FB2 CAN_F10R2_FB2_Msk /*!< Filter bit 2 */ 09119 #define CAN_F10R2_FB3_Pos (3U) 09120 #define CAN_F10R2_FB3_Msk (0x1U << CAN_F10R2_FB3_Pos) /*!< 0x00000008 */ 09121 #define CAN_F10R2_FB3 CAN_F10R2_FB3_Msk /*!< Filter bit 3 */ 09122 #define CAN_F10R2_FB4_Pos (4U) 09123 #define CAN_F10R2_FB4_Msk (0x1U << CAN_F10R2_FB4_Pos) /*!< 0x00000010 */ 09124 #define CAN_F10R2_FB4 CAN_F10R2_FB4_Msk /*!< Filter bit 4 */ 09125 #define CAN_F10R2_FB5_Pos (5U) 09126 #define CAN_F10R2_FB5_Msk (0x1U << CAN_F10R2_FB5_Pos) /*!< 0x00000020 */ 09127 #define CAN_F10R2_FB5 CAN_F10R2_FB5_Msk /*!< Filter bit 5 */ 09128 #define CAN_F10R2_FB6_Pos (6U) 09129 #define CAN_F10R2_FB6_Msk (0x1U << CAN_F10R2_FB6_Pos) /*!< 0x00000040 */ 09130 #define CAN_F10R2_FB6 CAN_F10R2_FB6_Msk /*!< Filter bit 6 */ 09131 #define CAN_F10R2_FB7_Pos (7U) 09132 #define CAN_F10R2_FB7_Msk (0x1U << CAN_F10R2_FB7_Pos) /*!< 0x00000080 */ 09133 #define CAN_F10R2_FB7 CAN_F10R2_FB7_Msk /*!< Filter bit 7 */ 09134 #define CAN_F10R2_FB8_Pos (8U) 09135 #define CAN_F10R2_FB8_Msk (0x1U << CAN_F10R2_FB8_Pos) /*!< 0x00000100 */ 09136 #define CAN_F10R2_FB8 CAN_F10R2_FB8_Msk /*!< Filter bit 8 */ 09137 #define CAN_F10R2_FB9_Pos (9U) 09138 #define CAN_F10R2_FB9_Msk (0x1U << CAN_F10R2_FB9_Pos) /*!< 0x00000200 */ 09139 #define CAN_F10R2_FB9 CAN_F10R2_FB9_Msk /*!< Filter bit 9 */ 09140 #define CAN_F10R2_FB10_Pos (10U) 09141 #define CAN_F10R2_FB10_Msk (0x1U << CAN_F10R2_FB10_Pos) /*!< 0x00000400 */ 09142 #define CAN_F10R2_FB10 CAN_F10R2_FB10_Msk /*!< Filter bit 10 */ 09143 #define CAN_F10R2_FB11_Pos (11U) 09144 #define CAN_F10R2_FB11_Msk (0x1U << CAN_F10R2_FB11_Pos) /*!< 0x00000800 */ 09145 #define CAN_F10R2_FB11 CAN_F10R2_FB11_Msk /*!< Filter bit 11 */ 09146 #define CAN_F10R2_FB12_Pos (12U) 09147 #define CAN_F10R2_FB12_Msk (0x1U << CAN_F10R2_FB12_Pos) /*!< 0x00001000 */ 09148 #define CAN_F10R2_FB12 CAN_F10R2_FB12_Msk /*!< Filter bit 12 */ 09149 #define CAN_F10R2_FB13_Pos (13U) 09150 #define CAN_F10R2_FB13_Msk (0x1U << CAN_F10R2_FB13_Pos) /*!< 0x00002000 */ 09151 #define CAN_F10R2_FB13 CAN_F10R2_FB13_Msk /*!< Filter bit 13 */ 09152 #define CAN_F10R2_FB14_Pos (14U) 09153 #define CAN_F10R2_FB14_Msk (0x1U << CAN_F10R2_FB14_Pos) /*!< 0x00004000 */ 09154 #define CAN_F10R2_FB14 CAN_F10R2_FB14_Msk /*!< Filter bit 14 */ 09155 #define CAN_F10R2_FB15_Pos (15U) 09156 #define CAN_F10R2_FB15_Msk (0x1U << CAN_F10R2_FB15_Pos) /*!< 0x00008000 */ 09157 #define CAN_F10R2_FB15 CAN_F10R2_FB15_Msk /*!< Filter bit 15 */ 09158 #define CAN_F10R2_FB16_Pos (16U) 09159 #define CAN_F10R2_FB16_Msk (0x1U << CAN_F10R2_FB16_Pos) /*!< 0x00010000 */ 09160 #define CAN_F10R2_FB16 CAN_F10R2_FB16_Msk /*!< Filter bit 16 */ 09161 #define CAN_F10R2_FB17_Pos (17U) 09162 #define CAN_F10R2_FB17_Msk (0x1U << CAN_F10R2_FB17_Pos) /*!< 0x00020000 */ 09163 #define CAN_F10R2_FB17 CAN_F10R2_FB17_Msk /*!< Filter bit 17 */ 09164 #define CAN_F10R2_FB18_Pos (18U) 09165 #define CAN_F10R2_FB18_Msk (0x1U << CAN_F10R2_FB18_Pos) /*!< 0x00040000 */ 09166 #define CAN_F10R2_FB18 CAN_F10R2_FB18_Msk /*!< Filter bit 18 */ 09167 #define CAN_F10R2_FB19_Pos (19U) 09168 #define CAN_F10R2_FB19_Msk (0x1U << CAN_F10R2_FB19_Pos) /*!< 0x00080000 */ 09169 #define CAN_F10R2_FB19 CAN_F10R2_FB19_Msk /*!< Filter bit 19 */ 09170 #define CAN_F10R2_FB20_Pos (20U) 09171 #define CAN_F10R2_FB20_Msk (0x1U << CAN_F10R2_FB20_Pos) /*!< 0x00100000 */ 09172 #define CAN_F10R2_FB20 CAN_F10R2_FB20_Msk /*!< Filter bit 20 */ 09173 #define CAN_F10R2_FB21_Pos (21U) 09174 #define CAN_F10R2_FB21_Msk (0x1U << CAN_F10R2_FB21_Pos) /*!< 0x00200000 */ 09175 #define CAN_F10R2_FB21 CAN_F10R2_FB21_Msk /*!< Filter bit 21 */ 09176 #define CAN_F10R2_FB22_Pos (22U) 09177 #define CAN_F10R2_FB22_Msk (0x1U << CAN_F10R2_FB22_Pos) /*!< 0x00400000 */ 09178 #define CAN_F10R2_FB22 CAN_F10R2_FB22_Msk /*!< Filter bit 22 */ 09179 #define CAN_F10R2_FB23_Pos (23U) 09180 #define CAN_F10R2_FB23_Msk (0x1U << CAN_F10R2_FB23_Pos) /*!< 0x00800000 */ 09181 #define CAN_F10R2_FB23 CAN_F10R2_FB23_Msk /*!< Filter bit 23 */ 09182 #define CAN_F10R2_FB24_Pos (24U) 09183 #define CAN_F10R2_FB24_Msk (0x1U << CAN_F10R2_FB24_Pos) /*!< 0x01000000 */ 09184 #define CAN_F10R2_FB24 CAN_F10R2_FB24_Msk /*!< Filter bit 24 */ 09185 #define CAN_F10R2_FB25_Pos (25U) 09186 #define CAN_F10R2_FB25_Msk (0x1U << CAN_F10R2_FB25_Pos) /*!< 0x02000000 */ 09187 #define CAN_F10R2_FB25 CAN_F10R2_FB25_Msk /*!< Filter bit 25 */ 09188 #define CAN_F10R2_FB26_Pos (26U) 09189 #define CAN_F10R2_FB26_Msk (0x1U << CAN_F10R2_FB26_Pos) /*!< 0x04000000 */ 09190 #define CAN_F10R2_FB26 CAN_F10R2_FB26_Msk /*!< Filter bit 26 */ 09191 #define CAN_F10R2_FB27_Pos (27U) 09192 #define CAN_F10R2_FB27_Msk (0x1U << CAN_F10R2_FB27_Pos) /*!< 0x08000000 */ 09193 #define CAN_F10R2_FB27 CAN_F10R2_FB27_Msk /*!< Filter bit 27 */ 09194 #define CAN_F10R2_FB28_Pos (28U) 09195 #define CAN_F10R2_FB28_Msk (0x1U << CAN_F10R2_FB28_Pos) /*!< 0x10000000 */ 09196 #define CAN_F10R2_FB28 CAN_F10R2_FB28_Msk /*!< Filter bit 28 */ 09197 #define CAN_F10R2_FB29_Pos (29U) 09198 #define CAN_F10R2_FB29_Msk (0x1U << CAN_F10R2_FB29_Pos) /*!< 0x20000000 */ 09199 #define CAN_F10R2_FB29 CAN_F10R2_FB29_Msk /*!< Filter bit 29 */ 09200 #define CAN_F10R2_FB30_Pos (30U) 09201 #define CAN_F10R2_FB30_Msk (0x1U << CAN_F10R2_FB30_Pos) /*!< 0x40000000 */ 09202 #define CAN_F10R2_FB30 CAN_F10R2_FB30_Msk /*!< Filter bit 30 */ 09203 #define CAN_F10R2_FB31_Pos (31U) 09204 #define CAN_F10R2_FB31_Msk (0x1U << CAN_F10R2_FB31_Pos) /*!< 0x80000000 */ 09205 #define CAN_F10R2_FB31 CAN_F10R2_FB31_Msk /*!< Filter bit 31 */ 09206 09207 /******************* Bit definition for CAN_F11R2 register ******************/ 09208 #define CAN_F11R2_FB0_Pos (0U) 09209 #define CAN_F11R2_FB0_Msk (0x1U << CAN_F11R2_FB0_Pos) /*!< 0x00000001 */ 09210 #define CAN_F11R2_FB0 CAN_F11R2_FB0_Msk /*!< Filter bit 0 */ 09211 #define CAN_F11R2_FB1_Pos (1U) 09212 #define CAN_F11R2_FB1_Msk (0x1U << CAN_F11R2_FB1_Pos) /*!< 0x00000002 */ 09213 #define CAN_F11R2_FB1 CAN_F11R2_FB1_Msk /*!< Filter bit 1 */ 09214 #define CAN_F11R2_FB2_Pos (2U) 09215 #define CAN_F11R2_FB2_Msk (0x1U << CAN_F11R2_FB2_Pos) /*!< 0x00000004 */ 09216 #define CAN_F11R2_FB2 CAN_F11R2_FB2_Msk /*!< Filter bit 2 */ 09217 #define CAN_F11R2_FB3_Pos (3U) 09218 #define CAN_F11R2_FB3_Msk (0x1U << CAN_F11R2_FB3_Pos) /*!< 0x00000008 */ 09219 #define CAN_F11R2_FB3 CAN_F11R2_FB3_Msk /*!< Filter bit 3 */ 09220 #define CAN_F11R2_FB4_Pos (4U) 09221 #define CAN_F11R2_FB4_Msk (0x1U << CAN_F11R2_FB4_Pos) /*!< 0x00000010 */ 09222 #define CAN_F11R2_FB4 CAN_F11R2_FB4_Msk /*!< Filter bit 4 */ 09223 #define CAN_F11R2_FB5_Pos (5U) 09224 #define CAN_F11R2_FB5_Msk (0x1U << CAN_F11R2_FB5_Pos) /*!< 0x00000020 */ 09225 #define CAN_F11R2_FB5 CAN_F11R2_FB5_Msk /*!< Filter bit 5 */ 09226 #define CAN_F11R2_FB6_Pos (6U) 09227 #define CAN_F11R2_FB6_Msk (0x1U << CAN_F11R2_FB6_Pos) /*!< 0x00000040 */ 09228 #define CAN_F11R2_FB6 CAN_F11R2_FB6_Msk /*!< Filter bit 6 */ 09229 #define CAN_F11R2_FB7_Pos (7U) 09230 #define CAN_F11R2_FB7_Msk (0x1U << CAN_F11R2_FB7_Pos) /*!< 0x00000080 */ 09231 #define CAN_F11R2_FB7 CAN_F11R2_FB7_Msk /*!< Filter bit 7 */ 09232 #define CAN_F11R2_FB8_Pos (8U) 09233 #define CAN_F11R2_FB8_Msk (0x1U << CAN_F11R2_FB8_Pos) /*!< 0x00000100 */ 09234 #define CAN_F11R2_FB8 CAN_F11R2_FB8_Msk /*!< Filter bit 8 */ 09235 #define CAN_F11R2_FB9_Pos (9U) 09236 #define CAN_F11R2_FB9_Msk (0x1U << CAN_F11R2_FB9_Pos) /*!< 0x00000200 */ 09237 #define CAN_F11R2_FB9 CAN_F11R2_FB9_Msk /*!< Filter bit 9 */ 09238 #define CAN_F11R2_FB10_Pos (10U) 09239 #define CAN_F11R2_FB10_Msk (0x1U << CAN_F11R2_FB10_Pos) /*!< 0x00000400 */ 09240 #define CAN_F11R2_FB10 CAN_F11R2_FB10_Msk /*!< Filter bit 10 */ 09241 #define CAN_F11R2_FB11_Pos (11U) 09242 #define CAN_F11R2_FB11_Msk (0x1U << CAN_F11R2_FB11_Pos) /*!< 0x00000800 */ 09243 #define CAN_F11R2_FB11 CAN_F11R2_FB11_Msk /*!< Filter bit 11 */ 09244 #define CAN_F11R2_FB12_Pos (12U) 09245 #define CAN_F11R2_FB12_Msk (0x1U << CAN_F11R2_FB12_Pos) /*!< 0x00001000 */ 09246 #define CAN_F11R2_FB12 CAN_F11R2_FB12_Msk /*!< Filter bit 12 */ 09247 #define CAN_F11R2_FB13_Pos (13U) 09248 #define CAN_F11R2_FB13_Msk (0x1U << CAN_F11R2_FB13_Pos) /*!< 0x00002000 */ 09249 #define CAN_F11R2_FB13 CAN_F11R2_FB13_Msk /*!< Filter bit 13 */ 09250 #define CAN_F11R2_FB14_Pos (14U) 09251 #define CAN_F11R2_FB14_Msk (0x1U << CAN_F11R2_FB14_Pos) /*!< 0x00004000 */ 09252 #define CAN_F11R2_FB14 CAN_F11R2_FB14_Msk /*!< Filter bit 14 */ 09253 #define CAN_F11R2_FB15_Pos (15U) 09254 #define CAN_F11R2_FB15_Msk (0x1U << CAN_F11R2_FB15_Pos) /*!< 0x00008000 */ 09255 #define CAN_F11R2_FB15 CAN_F11R2_FB15_Msk /*!< Filter bit 15 */ 09256 #define CAN_F11R2_FB16_Pos (16U) 09257 #define CAN_F11R2_FB16_Msk (0x1U << CAN_F11R2_FB16_Pos) /*!< 0x00010000 */ 09258 #define CAN_F11R2_FB16 CAN_F11R2_FB16_Msk /*!< Filter bit 16 */ 09259 #define CAN_F11R2_FB17_Pos (17U) 09260 #define CAN_F11R2_FB17_Msk (0x1U << CAN_F11R2_FB17_Pos) /*!< 0x00020000 */ 09261 #define CAN_F11R2_FB17 CAN_F11R2_FB17_Msk /*!< Filter bit 17 */ 09262 #define CAN_F11R2_FB18_Pos (18U) 09263 #define CAN_F11R2_FB18_Msk (0x1U << CAN_F11R2_FB18_Pos) /*!< 0x00040000 */ 09264 #define CAN_F11R2_FB18 CAN_F11R2_FB18_Msk /*!< Filter bit 18 */ 09265 #define CAN_F11R2_FB19_Pos (19U) 09266 #define CAN_F11R2_FB19_Msk (0x1U << CAN_F11R2_FB19_Pos) /*!< 0x00080000 */ 09267 #define CAN_F11R2_FB19 CAN_F11R2_FB19_Msk /*!< Filter bit 19 */ 09268 #define CAN_F11R2_FB20_Pos (20U) 09269 #define CAN_F11R2_FB20_Msk (0x1U << CAN_F11R2_FB20_Pos) /*!< 0x00100000 */ 09270 #define CAN_F11R2_FB20 CAN_F11R2_FB20_Msk /*!< Filter bit 20 */ 09271 #define CAN_F11R2_FB21_Pos (21U) 09272 #define CAN_F11R2_FB21_Msk (0x1U << CAN_F11R2_FB21_Pos) /*!< 0x00200000 */ 09273 #define CAN_F11R2_FB21 CAN_F11R2_FB21_Msk /*!< Filter bit 21 */ 09274 #define CAN_F11R2_FB22_Pos (22U) 09275 #define CAN_F11R2_FB22_Msk (0x1U << CAN_F11R2_FB22_Pos) /*!< 0x00400000 */ 09276 #define CAN_F11R2_FB22 CAN_F11R2_FB22_Msk /*!< Filter bit 22 */ 09277 #define CAN_F11R2_FB23_Pos (23U) 09278 #define CAN_F11R2_FB23_Msk (0x1U << CAN_F11R2_FB23_Pos) /*!< 0x00800000 */ 09279 #define CAN_F11R2_FB23 CAN_F11R2_FB23_Msk /*!< Filter bit 23 */ 09280 #define CAN_F11R2_FB24_Pos (24U) 09281 #define CAN_F11R2_FB24_Msk (0x1U << CAN_F11R2_FB24_Pos) /*!< 0x01000000 */ 09282 #define CAN_F11R2_FB24 CAN_F11R2_FB24_Msk /*!< Filter bit 24 */ 09283 #define CAN_F11R2_FB25_Pos (25U) 09284 #define CAN_F11R2_FB25_Msk (0x1U << CAN_F11R2_FB25_Pos) /*!< 0x02000000 */ 09285 #define CAN_F11R2_FB25 CAN_F11R2_FB25_Msk /*!< Filter bit 25 */ 09286 #define CAN_F11R2_FB26_Pos (26U) 09287 #define CAN_F11R2_FB26_Msk (0x1U << CAN_F11R2_FB26_Pos) /*!< 0x04000000 */ 09288 #define CAN_F11R2_FB26 CAN_F11R2_FB26_Msk /*!< Filter bit 26 */ 09289 #define CAN_F11R2_FB27_Pos (27U) 09290 #define CAN_F11R2_FB27_Msk (0x1U << CAN_F11R2_FB27_Pos) /*!< 0x08000000 */ 09291 #define CAN_F11R2_FB27 CAN_F11R2_FB27_Msk /*!< Filter bit 27 */ 09292 #define CAN_F11R2_FB28_Pos (28U) 09293 #define CAN_F11R2_FB28_Msk (0x1U << CAN_F11R2_FB28_Pos) /*!< 0x10000000 */ 09294 #define CAN_F11R2_FB28 CAN_F11R2_FB28_Msk /*!< Filter bit 28 */ 09295 #define CAN_F11R2_FB29_Pos (29U) 09296 #define CAN_F11R2_FB29_Msk (0x1U << CAN_F11R2_FB29_Pos) /*!< 0x20000000 */ 09297 #define CAN_F11R2_FB29 CAN_F11R2_FB29_Msk /*!< Filter bit 29 */ 09298 #define CAN_F11R2_FB30_Pos (30U) 09299 #define CAN_F11R2_FB30_Msk (0x1U << CAN_F11R2_FB30_Pos) /*!< 0x40000000 */ 09300 #define CAN_F11R2_FB30 CAN_F11R2_FB30_Msk /*!< Filter bit 30 */ 09301 #define CAN_F11R2_FB31_Pos (31U) 09302 #define CAN_F11R2_FB31_Msk (0x1U << CAN_F11R2_FB31_Pos) /*!< 0x80000000 */ 09303 #define CAN_F11R2_FB31 CAN_F11R2_FB31_Msk /*!< Filter bit 31 */ 09304 09305 /******************* Bit definition for CAN_F12R2 register ******************/ 09306 #define CAN_F12R2_FB0_Pos (0U) 09307 #define CAN_F12R2_FB0_Msk (0x1U << CAN_F12R2_FB0_Pos) /*!< 0x00000001 */ 09308 #define CAN_F12R2_FB0 CAN_F12R2_FB0_Msk /*!< Filter bit 0 */ 09309 #define CAN_F12R2_FB1_Pos (1U) 09310 #define CAN_F12R2_FB1_Msk (0x1U << CAN_F12R2_FB1_Pos) /*!< 0x00000002 */ 09311 #define CAN_F12R2_FB1 CAN_F12R2_FB1_Msk /*!< Filter bit 1 */ 09312 #define CAN_F12R2_FB2_Pos (2U) 09313 #define CAN_F12R2_FB2_Msk (0x1U << CAN_F12R2_FB2_Pos) /*!< 0x00000004 */ 09314 #define CAN_F12R2_FB2 CAN_F12R2_FB2_Msk /*!< Filter bit 2 */ 09315 #define CAN_F12R2_FB3_Pos (3U) 09316 #define CAN_F12R2_FB3_Msk (0x1U << CAN_F12R2_FB3_Pos) /*!< 0x00000008 */ 09317 #define CAN_F12R2_FB3 CAN_F12R2_FB3_Msk /*!< Filter bit 3 */ 09318 #define CAN_F12R2_FB4_Pos (4U) 09319 #define CAN_F12R2_FB4_Msk (0x1U << CAN_F12R2_FB4_Pos) /*!< 0x00000010 */ 09320 #define CAN_F12R2_FB4 CAN_F12R2_FB4_Msk /*!< Filter bit 4 */ 09321 #define CAN_F12R2_FB5_Pos (5U) 09322 #define CAN_F12R2_FB5_Msk (0x1U << CAN_F12R2_FB5_Pos) /*!< 0x00000020 */ 09323 #define CAN_F12R2_FB5 CAN_F12R2_FB5_Msk /*!< Filter bit 5 */ 09324 #define CAN_F12R2_FB6_Pos (6U) 09325 #define CAN_F12R2_FB6_Msk (0x1U << CAN_F12R2_FB6_Pos) /*!< 0x00000040 */ 09326 #define CAN_F12R2_FB6 CAN_F12R2_FB6_Msk /*!< Filter bit 6 */ 09327 #define CAN_F12R2_FB7_Pos (7U) 09328 #define CAN_F12R2_FB7_Msk (0x1U << CAN_F12R2_FB7_Pos) /*!< 0x00000080 */ 09329 #define CAN_F12R2_FB7 CAN_F12R2_FB7_Msk /*!< Filter bit 7 */ 09330 #define CAN_F12R2_FB8_Pos (8U) 09331 #define CAN_F12R2_FB8_Msk (0x1U << CAN_F12R2_FB8_Pos) /*!< 0x00000100 */ 09332 #define CAN_F12R2_FB8 CAN_F12R2_FB8_Msk /*!< Filter bit 8 */ 09333 #define CAN_F12R2_FB9_Pos (9U) 09334 #define CAN_F12R2_FB9_Msk (0x1U << CAN_F12R2_FB9_Pos) /*!< 0x00000200 */ 09335 #define CAN_F12R2_FB9 CAN_F12R2_FB9_Msk /*!< Filter bit 9 */ 09336 #define CAN_F12R2_FB10_Pos (10U) 09337 #define CAN_F12R2_FB10_Msk (0x1U << CAN_F12R2_FB10_Pos) /*!< 0x00000400 */ 09338 #define CAN_F12R2_FB10 CAN_F12R2_FB10_Msk /*!< Filter bit 10 */ 09339 #define CAN_F12R2_FB11_Pos (11U) 09340 #define CAN_F12R2_FB11_Msk (0x1U << CAN_F12R2_FB11_Pos) /*!< 0x00000800 */ 09341 #define CAN_F12R2_FB11 CAN_F12R2_FB11_Msk /*!< Filter bit 11 */ 09342 #define CAN_F12R2_FB12_Pos (12U) 09343 #define CAN_F12R2_FB12_Msk (0x1U << CAN_F12R2_FB12_Pos) /*!< 0x00001000 */ 09344 #define CAN_F12R2_FB12 CAN_F12R2_FB12_Msk /*!< Filter bit 12 */ 09345 #define CAN_F12R2_FB13_Pos (13U) 09346 #define CAN_F12R2_FB13_Msk (0x1U << CAN_F12R2_FB13_Pos) /*!< 0x00002000 */ 09347 #define CAN_F12R2_FB13 CAN_F12R2_FB13_Msk /*!< Filter bit 13 */ 09348 #define CAN_F12R2_FB14_Pos (14U) 09349 #define CAN_F12R2_FB14_Msk (0x1U << CAN_F12R2_FB14_Pos) /*!< 0x00004000 */ 09350 #define CAN_F12R2_FB14 CAN_F12R2_FB14_Msk /*!< Filter bit 14 */ 09351 #define CAN_F12R2_FB15_Pos (15U) 09352 #define CAN_F12R2_FB15_Msk (0x1U << CAN_F12R2_FB15_Pos) /*!< 0x00008000 */ 09353 #define CAN_F12R2_FB15 CAN_F12R2_FB15_Msk /*!< Filter bit 15 */ 09354 #define CAN_F12R2_FB16_Pos (16U) 09355 #define CAN_F12R2_FB16_Msk (0x1U << CAN_F12R2_FB16_Pos) /*!< 0x00010000 */ 09356 #define CAN_F12R2_FB16 CAN_F12R2_FB16_Msk /*!< Filter bit 16 */ 09357 #define CAN_F12R2_FB17_Pos (17U) 09358 #define CAN_F12R2_FB17_Msk (0x1U << CAN_F12R2_FB17_Pos) /*!< 0x00020000 */ 09359 #define CAN_F12R2_FB17 CAN_F12R2_FB17_Msk /*!< Filter bit 17 */ 09360 #define CAN_F12R2_FB18_Pos (18U) 09361 #define CAN_F12R2_FB18_Msk (0x1U << CAN_F12R2_FB18_Pos) /*!< 0x00040000 */ 09362 #define CAN_F12R2_FB18 CAN_F12R2_FB18_Msk /*!< Filter bit 18 */ 09363 #define CAN_F12R2_FB19_Pos (19U) 09364 #define CAN_F12R2_FB19_Msk (0x1U << CAN_F12R2_FB19_Pos) /*!< 0x00080000 */ 09365 #define CAN_F12R2_FB19 CAN_F12R2_FB19_Msk /*!< Filter bit 19 */ 09366 #define CAN_F12R2_FB20_Pos (20U) 09367 #define CAN_F12R2_FB20_Msk (0x1U << CAN_F12R2_FB20_Pos) /*!< 0x00100000 */ 09368 #define CAN_F12R2_FB20 CAN_F12R2_FB20_Msk /*!< Filter bit 20 */ 09369 #define CAN_F12R2_FB21_Pos (21U) 09370 #define CAN_F12R2_FB21_Msk (0x1U << CAN_F12R2_FB21_Pos) /*!< 0x00200000 */ 09371 #define CAN_F12R2_FB21 CAN_F12R2_FB21_Msk /*!< Filter bit 21 */ 09372 #define CAN_F12R2_FB22_Pos (22U) 09373 #define CAN_F12R2_FB22_Msk (0x1U << CAN_F12R2_FB22_Pos) /*!< 0x00400000 */ 09374 #define CAN_F12R2_FB22 CAN_F12R2_FB22_Msk /*!< Filter bit 22 */ 09375 #define CAN_F12R2_FB23_Pos (23U) 09376 #define CAN_F12R2_FB23_Msk (0x1U << CAN_F12R2_FB23_Pos) /*!< 0x00800000 */ 09377 #define CAN_F12R2_FB23 CAN_F12R2_FB23_Msk /*!< Filter bit 23 */ 09378 #define CAN_F12R2_FB24_Pos (24U) 09379 #define CAN_F12R2_FB24_Msk (0x1U << CAN_F12R2_FB24_Pos) /*!< 0x01000000 */ 09380 #define CAN_F12R2_FB24 CAN_F12R2_FB24_Msk /*!< Filter bit 24 */ 09381 #define CAN_F12R2_FB25_Pos (25U) 09382 #define CAN_F12R2_FB25_Msk (0x1U << CAN_F12R2_FB25_Pos) /*!< 0x02000000 */ 09383 #define CAN_F12R2_FB25 CAN_F12R2_FB25_Msk /*!< Filter bit 25 */ 09384 #define CAN_F12R2_FB26_Pos (26U) 09385 #define CAN_F12R2_FB26_Msk (0x1U << CAN_F12R2_FB26_Pos) /*!< 0x04000000 */ 09386 #define CAN_F12R2_FB26 CAN_F12R2_FB26_Msk /*!< Filter bit 26 */ 09387 #define CAN_F12R2_FB27_Pos (27U) 09388 #define CAN_F12R2_FB27_Msk (0x1U << CAN_F12R2_FB27_Pos) /*!< 0x08000000 */ 09389 #define CAN_F12R2_FB27 CAN_F12R2_FB27_Msk /*!< Filter bit 27 */ 09390 #define CAN_F12R2_FB28_Pos (28U) 09391 #define CAN_F12R2_FB28_Msk (0x1U << CAN_F12R2_FB28_Pos) /*!< 0x10000000 */ 09392 #define CAN_F12R2_FB28 CAN_F12R2_FB28_Msk /*!< Filter bit 28 */ 09393 #define CAN_F12R2_FB29_Pos (29U) 09394 #define CAN_F12R2_FB29_Msk (0x1U << CAN_F12R2_FB29_Pos) /*!< 0x20000000 */ 09395 #define CAN_F12R2_FB29 CAN_F12R2_FB29_Msk /*!< Filter bit 29 */ 09396 #define CAN_F12R2_FB30_Pos (30U) 09397 #define CAN_F12R2_FB30_Msk (0x1U << CAN_F12R2_FB30_Pos) /*!< 0x40000000 */ 09398 #define CAN_F12R2_FB30 CAN_F12R2_FB30_Msk /*!< Filter bit 30 */ 09399 #define CAN_F12R2_FB31_Pos (31U) 09400 #define CAN_F12R2_FB31_Msk (0x1U << CAN_F12R2_FB31_Pos) /*!< 0x80000000 */ 09401 #define CAN_F12R2_FB31 CAN_F12R2_FB31_Msk /*!< Filter bit 31 */ 09402 09403 /******************* Bit definition for CAN_F13R2 register ******************/ 09404 #define CAN_F13R2_FB0_Pos (0U) 09405 #define CAN_F13R2_FB0_Msk (0x1U << CAN_F13R2_FB0_Pos) /*!< 0x00000001 */ 09406 #define CAN_F13R2_FB0 CAN_F13R2_FB0_Msk /*!< Filter bit 0 */ 09407 #define CAN_F13R2_FB1_Pos (1U) 09408 #define CAN_F13R2_FB1_Msk (0x1U << CAN_F13R2_FB1_Pos) /*!< 0x00000002 */ 09409 #define CAN_F13R2_FB1 CAN_F13R2_FB1_Msk /*!< Filter bit 1 */ 09410 #define CAN_F13R2_FB2_Pos (2U) 09411 #define CAN_F13R2_FB2_Msk (0x1U << CAN_F13R2_FB2_Pos) /*!< 0x00000004 */ 09412 #define CAN_F13R2_FB2 CAN_F13R2_FB2_Msk /*!< Filter bit 2 */ 09413 #define CAN_F13R2_FB3_Pos (3U) 09414 #define CAN_F13R2_FB3_Msk (0x1U << CAN_F13R2_FB3_Pos) /*!< 0x00000008 */ 09415 #define CAN_F13R2_FB3 CAN_F13R2_FB3_Msk /*!< Filter bit 3 */ 09416 #define CAN_F13R2_FB4_Pos (4U) 09417 #define CAN_F13R2_FB4_Msk (0x1U << CAN_F13R2_FB4_Pos) /*!< 0x00000010 */ 09418 #define CAN_F13R2_FB4 CAN_F13R2_FB4_Msk /*!< Filter bit 4 */ 09419 #define CAN_F13R2_FB5_Pos (5U) 09420 #define CAN_F13R2_FB5_Msk (0x1U << CAN_F13R2_FB5_Pos) /*!< 0x00000020 */ 09421 #define CAN_F13R2_FB5 CAN_F13R2_FB5_Msk /*!< Filter bit 5 */ 09422 #define CAN_F13R2_FB6_Pos (6U) 09423 #define CAN_F13R2_FB6_Msk (0x1U << CAN_F13R2_FB6_Pos) /*!< 0x00000040 */ 09424 #define CAN_F13R2_FB6 CAN_F13R2_FB6_Msk /*!< Filter bit 6 */ 09425 #define CAN_F13R2_FB7_Pos (7U) 09426 #define CAN_F13R2_FB7_Msk (0x1U << CAN_F13R2_FB7_Pos) /*!< 0x00000080 */ 09427 #define CAN_F13R2_FB7 CAN_F13R2_FB7_Msk /*!< Filter bit 7 */ 09428 #define CAN_F13R2_FB8_Pos (8U) 09429 #define CAN_F13R2_FB8_Msk (0x1U << CAN_F13R2_FB8_Pos) /*!< 0x00000100 */ 09430 #define CAN_F13R2_FB8 CAN_F13R2_FB8_Msk /*!< Filter bit 8 */ 09431 #define CAN_F13R2_FB9_Pos (9U) 09432 #define CAN_F13R2_FB9_Msk (0x1U << CAN_F13R2_FB9_Pos) /*!< 0x00000200 */ 09433 #define CAN_F13R2_FB9 CAN_F13R2_FB9_Msk /*!< Filter bit 9 */ 09434 #define CAN_F13R2_FB10_Pos (10U) 09435 #define CAN_F13R2_FB10_Msk (0x1U << CAN_F13R2_FB10_Pos) /*!< 0x00000400 */ 09436 #define CAN_F13R2_FB10 CAN_F13R2_FB10_Msk /*!< Filter bit 10 */ 09437 #define CAN_F13R2_FB11_Pos (11U) 09438 #define CAN_F13R2_FB11_Msk (0x1U << CAN_F13R2_FB11_Pos) /*!< 0x00000800 */ 09439 #define CAN_F13R2_FB11 CAN_F13R2_FB11_Msk /*!< Filter bit 11 */ 09440 #define CAN_F13R2_FB12_Pos (12U) 09441 #define CAN_F13R2_FB12_Msk (0x1U << CAN_F13R2_FB12_Pos) /*!< 0x00001000 */ 09442 #define CAN_F13R2_FB12 CAN_F13R2_FB12_Msk /*!< Filter bit 12 */ 09443 #define CAN_F13R2_FB13_Pos (13U) 09444 #define CAN_F13R2_FB13_Msk (0x1U << CAN_F13R2_FB13_Pos) /*!< 0x00002000 */ 09445 #define CAN_F13R2_FB13 CAN_F13R2_FB13_Msk /*!< Filter bit 13 */ 09446 #define CAN_F13R2_FB14_Pos (14U) 09447 #define CAN_F13R2_FB14_Msk (0x1U << CAN_F13R2_FB14_Pos) /*!< 0x00004000 */ 09448 #define CAN_F13R2_FB14 CAN_F13R2_FB14_Msk /*!< Filter bit 14 */ 09449 #define CAN_F13R2_FB15_Pos (15U) 09450 #define CAN_F13R2_FB15_Msk (0x1U << CAN_F13R2_FB15_Pos) /*!< 0x00008000 */ 09451 #define CAN_F13R2_FB15 CAN_F13R2_FB15_Msk /*!< Filter bit 15 */ 09452 #define CAN_F13R2_FB16_Pos (16U) 09453 #define CAN_F13R2_FB16_Msk (0x1U << CAN_F13R2_FB16_Pos) /*!< 0x00010000 */ 09454 #define CAN_F13R2_FB16 CAN_F13R2_FB16_Msk /*!< Filter bit 16 */ 09455 #define CAN_F13R2_FB17_Pos (17U) 09456 #define CAN_F13R2_FB17_Msk (0x1U << CAN_F13R2_FB17_Pos) /*!< 0x00020000 */ 09457 #define CAN_F13R2_FB17 CAN_F13R2_FB17_Msk /*!< Filter bit 17 */ 09458 #define CAN_F13R2_FB18_Pos (18U) 09459 #define CAN_F13R2_FB18_Msk (0x1U << CAN_F13R2_FB18_Pos) /*!< 0x00040000 */ 09460 #define CAN_F13R2_FB18 CAN_F13R2_FB18_Msk /*!< Filter bit 18 */ 09461 #define CAN_F13R2_FB19_Pos (19U) 09462 #define CAN_F13R2_FB19_Msk (0x1U << CAN_F13R2_FB19_Pos) /*!< 0x00080000 */ 09463 #define CAN_F13R2_FB19 CAN_F13R2_FB19_Msk /*!< Filter bit 19 */ 09464 #define CAN_F13R2_FB20_Pos (20U) 09465 #define CAN_F13R2_FB20_Msk (0x1U << CAN_F13R2_FB20_Pos) /*!< 0x00100000 */ 09466 #define CAN_F13R2_FB20 CAN_F13R2_FB20_Msk /*!< Filter bit 20 */ 09467 #define CAN_F13R2_FB21_Pos (21U) 09468 #define CAN_F13R2_FB21_Msk (0x1U << CAN_F13R2_FB21_Pos) /*!< 0x00200000 */ 09469 #define CAN_F13R2_FB21 CAN_F13R2_FB21_Msk /*!< Filter bit 21 */ 09470 #define CAN_F13R2_FB22_Pos (22U) 09471 #define CAN_F13R2_FB22_Msk (0x1U << CAN_F13R2_FB22_Pos) /*!< 0x00400000 */ 09472 #define CAN_F13R2_FB22 CAN_F13R2_FB22_Msk /*!< Filter bit 22 */ 09473 #define CAN_F13R2_FB23_Pos (23U) 09474 #define CAN_F13R2_FB23_Msk (0x1U << CAN_F13R2_FB23_Pos) /*!< 0x00800000 */ 09475 #define CAN_F13R2_FB23 CAN_F13R2_FB23_Msk /*!< Filter bit 23 */ 09476 #define CAN_F13R2_FB24_Pos (24U) 09477 #define CAN_F13R2_FB24_Msk (0x1U << CAN_F13R2_FB24_Pos) /*!< 0x01000000 */ 09478 #define CAN_F13R2_FB24 CAN_F13R2_FB24_Msk /*!< Filter bit 24 */ 09479 #define CAN_F13R2_FB25_Pos (25U) 09480 #define CAN_F13R2_FB25_Msk (0x1U << CAN_F13R2_FB25_Pos) /*!< 0x02000000 */ 09481 #define CAN_F13R2_FB25 CAN_F13R2_FB25_Msk /*!< Filter bit 25 */ 09482 #define CAN_F13R2_FB26_Pos (26U) 09483 #define CAN_F13R2_FB26_Msk (0x1U << CAN_F13R2_FB26_Pos) /*!< 0x04000000 */ 09484 #define CAN_F13R2_FB26 CAN_F13R2_FB26_Msk /*!< Filter bit 26 */ 09485 #define CAN_F13R2_FB27_Pos (27U) 09486 #define CAN_F13R2_FB27_Msk (0x1U << CAN_F13R2_FB27_Pos) /*!< 0x08000000 */ 09487 #define CAN_F13R2_FB27 CAN_F13R2_FB27_Msk /*!< Filter bit 27 */ 09488 #define CAN_F13R2_FB28_Pos (28U) 09489 #define CAN_F13R2_FB28_Msk (0x1U << CAN_F13R2_FB28_Pos) /*!< 0x10000000 */ 09490 #define CAN_F13R2_FB28 CAN_F13R2_FB28_Msk /*!< Filter bit 28 */ 09491 #define CAN_F13R2_FB29_Pos (29U) 09492 #define CAN_F13R2_FB29_Msk (0x1U << CAN_F13R2_FB29_Pos) /*!< 0x20000000 */ 09493 #define CAN_F13R2_FB29 CAN_F13R2_FB29_Msk /*!< Filter bit 29 */ 09494 #define CAN_F13R2_FB30_Pos (30U) 09495 #define CAN_F13R2_FB30_Msk (0x1U << CAN_F13R2_FB30_Pos) /*!< 0x40000000 */ 09496 #define CAN_F13R2_FB30 CAN_F13R2_FB30_Msk /*!< Filter bit 30 */ 09497 #define CAN_F13R2_FB31_Pos (31U) 09498 #define CAN_F13R2_FB31_Msk (0x1U << CAN_F13R2_FB31_Pos) /*!< 0x80000000 */ 09499 #define CAN_F13R2_FB31 CAN_F13R2_FB31_Msk /*!< Filter bit 31 */ 09500 09501 /******************************************************************************/ 09502 /* */ 09503 /* Serial Peripheral Interface */ 09504 /* */ 09505 /******************************************************************************/ 09506 09507 /******************* Bit definition for SPI_CR1 register ********************/ 09508 #define SPI_CR1_CPHA_Pos (0U) 09509 #define SPI_CR1_CPHA_Msk (0x1U << SPI_CR1_CPHA_Pos) /*!< 0x00000001 */ 09510 #define SPI_CR1_CPHA SPI_CR1_CPHA_Msk /*!< Clock Phase */ 09511 #define SPI_CR1_CPOL_Pos (1U) 09512 #define SPI_CR1_CPOL_Msk (0x1U << SPI_CR1_CPOL_Pos) /*!< 0x00000002 */ 09513 #define SPI_CR1_CPOL SPI_CR1_CPOL_Msk /*!< Clock Polarity */ 09514 #define SPI_CR1_MSTR_Pos (2U) 09515 #define SPI_CR1_MSTR_Msk (0x1U << SPI_CR1_MSTR_Pos) /*!< 0x00000004 */ 09516 #define SPI_CR1_MSTR SPI_CR1_MSTR_Msk /*!< Master Selection */ 09517 09518 #define SPI_CR1_BR_Pos (3U) 09519 #define SPI_CR1_BR_Msk (0x7U << SPI_CR1_BR_Pos) /*!< 0x00000038 */ 09520 #define SPI_CR1_BR SPI_CR1_BR_Msk /*!< BR[2:0] bits (Baud Rate Control) */ 09521 #define SPI_CR1_BR_0 (0x1U << SPI_CR1_BR_Pos) /*!< 0x00000008 */ 09522 #define SPI_CR1_BR_1 (0x2U << SPI_CR1_BR_Pos) /*!< 0x00000010 */ 09523 #define SPI_CR1_BR_2 (0x4U << SPI_CR1_BR_Pos) /*!< 0x00000020 */ 09524 09525 #define SPI_CR1_SPE_Pos (6U) 09526 #define SPI_CR1_SPE_Msk (0x1U << SPI_CR1_SPE_Pos) /*!< 0x00000040 */ 09527 #define SPI_CR1_SPE SPI_CR1_SPE_Msk /*!< SPI Enable */ 09528 #define SPI_CR1_LSBFIRST_Pos (7U) 09529 #define SPI_CR1_LSBFIRST_Msk (0x1U << SPI_CR1_LSBFIRST_Pos) /*!< 0x00000080 */ 09530 #define SPI_CR1_LSBFIRST SPI_CR1_LSBFIRST_Msk /*!< Frame Format */ 09531 #define SPI_CR1_SSI_Pos (8U) 09532 #define SPI_CR1_SSI_Msk (0x1U << SPI_CR1_SSI_Pos) /*!< 0x00000100 */ 09533 #define SPI_CR1_SSI SPI_CR1_SSI_Msk /*!< Internal slave select */ 09534 #define SPI_CR1_SSM_Pos (9U) 09535 #define SPI_CR1_SSM_Msk (0x1U << SPI_CR1_SSM_Pos) /*!< 0x00000200 */ 09536 #define SPI_CR1_SSM SPI_CR1_SSM_Msk /*!< Software slave management */ 09537 #define SPI_CR1_RXONLY_Pos (10U) 09538 #define SPI_CR1_RXONLY_Msk (0x1U << SPI_CR1_RXONLY_Pos) /*!< 0x00000400 */ 09539 #define SPI_CR1_RXONLY SPI_CR1_RXONLY_Msk /*!< Receive only */ 09540 #define SPI_CR1_DFF_Pos (11U) 09541 #define SPI_CR1_DFF_Msk (0x1U << SPI_CR1_DFF_Pos) /*!< 0x00000800 */ 09542 #define SPI_CR1_DFF SPI_CR1_DFF_Msk /*!< Data Frame Format */ 09543 #define SPI_CR1_CRCNEXT_Pos (12U) 09544 #define SPI_CR1_CRCNEXT_Msk (0x1U << SPI_CR1_CRCNEXT_Pos) /*!< 0x00001000 */ 09545 #define SPI_CR1_CRCNEXT SPI_CR1_CRCNEXT_Msk /*!< Transmit CRC next */ 09546 #define SPI_CR1_CRCEN_Pos (13U) 09547 #define SPI_CR1_CRCEN_Msk (0x1U << SPI_CR1_CRCEN_Pos) /*!< 0x00002000 */ 09548 #define SPI_CR1_CRCEN SPI_CR1_CRCEN_Msk /*!< Hardware CRC calculation enable */ 09549 #define SPI_CR1_BIDIOE_Pos (14U) 09550 #define SPI_CR1_BIDIOE_Msk (0x1U << SPI_CR1_BIDIOE_Pos) /*!< 0x00004000 */ 09551 #define SPI_CR1_BIDIOE SPI_CR1_BIDIOE_Msk /*!< Output enable in bidirectional mode */ 09552 #define SPI_CR1_BIDIMODE_Pos (15U) 09553 #define SPI_CR1_BIDIMODE_Msk (0x1U << SPI_CR1_BIDIMODE_Pos) /*!< 0x00008000 */ 09554 #define SPI_CR1_BIDIMODE SPI_CR1_BIDIMODE_Msk /*!< Bidirectional data mode enable */ 09555 09556 /******************* Bit definition for SPI_CR2 register ********************/ 09557 #define SPI_CR2_RXDMAEN_Pos (0U) 09558 #define SPI_CR2_RXDMAEN_Msk (0x1U << SPI_CR2_RXDMAEN_Pos) /*!< 0x00000001 */ 09559 #define SPI_CR2_RXDMAEN SPI_CR2_RXDMAEN_Msk /*!< Rx Buffer DMA Enable */ 09560 #define SPI_CR2_TXDMAEN_Pos (1U) 09561 #define SPI_CR2_TXDMAEN_Msk (0x1U << SPI_CR2_TXDMAEN_Pos) /*!< 0x00000002 */ 09562 #define SPI_CR2_TXDMAEN SPI_CR2_TXDMAEN_Msk /*!< Tx Buffer DMA Enable */ 09563 #define SPI_CR2_SSOE_Pos (2U) 09564 #define SPI_CR2_SSOE_Msk (0x1U << SPI_CR2_SSOE_Pos) /*!< 0x00000004 */ 09565 #define SPI_CR2_SSOE SPI_CR2_SSOE_Msk /*!< SS Output Enable */ 09566 #define SPI_CR2_ERRIE_Pos (5U) 09567 #define SPI_CR2_ERRIE_Msk (0x1U << SPI_CR2_ERRIE_Pos) /*!< 0x00000020 */ 09568 #define SPI_CR2_ERRIE SPI_CR2_ERRIE_Msk /*!< Error Interrupt Enable */ 09569 #define SPI_CR2_RXNEIE_Pos (6U) 09570 #define SPI_CR2_RXNEIE_Msk (0x1U << SPI_CR2_RXNEIE_Pos) /*!< 0x00000040 */ 09571 #define SPI_CR2_RXNEIE SPI_CR2_RXNEIE_Msk /*!< RX buffer Not Empty Interrupt Enable */ 09572 #define SPI_CR2_TXEIE_Pos (7U) 09573 #define SPI_CR2_TXEIE_Msk (0x1U << SPI_CR2_TXEIE_Pos) /*!< 0x00000080 */ 09574 #define SPI_CR2_TXEIE SPI_CR2_TXEIE_Msk /*!< Tx buffer Empty Interrupt Enable */ 09575 09576 /******************** Bit definition for SPI_SR register ********************/ 09577 #define SPI_SR_RXNE_Pos (0U) 09578 #define SPI_SR_RXNE_Msk (0x1U << SPI_SR_RXNE_Pos) /*!< 0x00000001 */ 09579 #define SPI_SR_RXNE SPI_SR_RXNE_Msk /*!< Receive buffer Not Empty */ 09580 #define SPI_SR_TXE_Pos (1U) 09581 #define SPI_SR_TXE_Msk (0x1U << SPI_SR_TXE_Pos) /*!< 0x00000002 */ 09582 #define SPI_SR_TXE SPI_SR_TXE_Msk /*!< Transmit buffer Empty */ 09583 #define SPI_SR_CHSIDE_Pos (2U) 09584 #define SPI_SR_CHSIDE_Msk (0x1U << SPI_SR_CHSIDE_Pos) /*!< 0x00000004 */ 09585 #define SPI_SR_CHSIDE SPI_SR_CHSIDE_Msk /*!< Channel side */ 09586 #define SPI_SR_UDR_Pos (3U) 09587 #define SPI_SR_UDR_Msk (0x1U << SPI_SR_UDR_Pos) /*!< 0x00000008 */ 09588 #define SPI_SR_UDR SPI_SR_UDR_Msk /*!< Underrun flag */ 09589 #define SPI_SR_CRCERR_Pos (4U) 09590 #define SPI_SR_CRCERR_Msk (0x1U << SPI_SR_CRCERR_Pos) /*!< 0x00000010 */ 09591 #define SPI_SR_CRCERR SPI_SR_CRCERR_Msk /*!< CRC Error flag */ 09592 #define SPI_SR_MODF_Pos (5U) 09593 #define SPI_SR_MODF_Msk (0x1U << SPI_SR_MODF_Pos) /*!< 0x00000020 */ 09594 #define SPI_SR_MODF SPI_SR_MODF_Msk /*!< Mode fault */ 09595 #define SPI_SR_OVR_Pos (6U) 09596 #define SPI_SR_OVR_Msk (0x1U << SPI_SR_OVR_Pos) /*!< 0x00000040 */ 09597 #define SPI_SR_OVR SPI_SR_OVR_Msk /*!< Overrun flag */ 09598 #define SPI_SR_BSY_Pos (7U) 09599 #define SPI_SR_BSY_Msk (0x1U << SPI_SR_BSY_Pos) /*!< 0x00000080 */ 09600 #define SPI_SR_BSY SPI_SR_BSY_Msk /*!< Busy flag */ 09601 09602 /******************** Bit definition for SPI_DR register ********************/ 09603 #define SPI_DR_DR_Pos (0U) 09604 #define SPI_DR_DR_Msk (0xFFFFU << SPI_DR_DR_Pos) /*!< 0x0000FFFF */ 09605 #define SPI_DR_DR SPI_DR_DR_Msk /*!< Data Register */ 09606 09607 /******************* Bit definition for SPI_CRCPR register ******************/ 09608 #define SPI_CRCPR_CRCPOLY_Pos (0U) 09609 #define SPI_CRCPR_CRCPOLY_Msk (0xFFFFU << SPI_CRCPR_CRCPOLY_Pos) /*!< 0x0000FFFF */ 09610 #define SPI_CRCPR_CRCPOLY SPI_CRCPR_CRCPOLY_Msk /*!< CRC polynomial register */ 09611 09612 /****************** Bit definition for SPI_RXCRCR register ******************/ 09613 #define SPI_RXCRCR_RXCRC_Pos (0U) 09614 #define SPI_RXCRCR_RXCRC_Msk (0xFFFFU << SPI_RXCRCR_RXCRC_Pos) /*!< 0x0000FFFF */ 09615 #define SPI_RXCRCR_RXCRC SPI_RXCRCR_RXCRC_Msk /*!< Rx CRC Register */ 09616 09617 /****************** Bit definition for SPI_TXCRCR register ******************/ 09618 #define SPI_TXCRCR_TXCRC_Pos (0U) 09619 #define SPI_TXCRCR_TXCRC_Msk (0xFFFFU << SPI_TXCRCR_TXCRC_Pos) /*!< 0x0000FFFF */ 09620 #define SPI_TXCRCR_TXCRC SPI_TXCRCR_TXCRC_Msk /*!< Tx CRC Register */ 09621 09622 /****************** Bit definition for SPI_I2SCFGR register *****************/ 09623 #define SPI_I2SCFGR_I2SMOD_Pos (11U) 09624 #define SPI_I2SCFGR_I2SMOD_Msk (0x1U << SPI_I2SCFGR_I2SMOD_Pos) /*!< 0x00000800 */ 09625 #define SPI_I2SCFGR_I2SMOD SPI_I2SCFGR_I2SMOD_Msk /*!< I2S mode selection */ 09626 09627 09628 /******************************************************************************/ 09629 /* */ 09630 /* Inter-integrated Circuit Interface */ 09631 /* */ 09632 /******************************************************************************/ 09633 09634 /******************* Bit definition for I2C_CR1 register ********************/ 09635 #define I2C_CR1_PE_Pos (0U) 09636 #define I2C_CR1_PE_Msk (0x1U << I2C_CR1_PE_Pos) /*!< 0x00000001 */ 09637 #define I2C_CR1_PE I2C_CR1_PE_Msk /*!< Peripheral Enable */ 09638 #define I2C_CR1_SMBUS_Pos (1U) 09639 #define I2C_CR1_SMBUS_Msk (0x1U << I2C_CR1_SMBUS_Pos) /*!< 0x00000002 */ 09640 #define I2C_CR1_SMBUS I2C_CR1_SMBUS_Msk /*!< SMBus Mode */ 09641 #define I2C_CR1_SMBTYPE_Pos (3U) 09642 #define I2C_CR1_SMBTYPE_Msk (0x1U << I2C_CR1_SMBTYPE_Pos) /*!< 0x00000008 */ 09643 #define I2C_CR1_SMBTYPE I2C_CR1_SMBTYPE_Msk /*!< SMBus Type */ 09644 #define I2C_CR1_ENARP_Pos (4U) 09645 #define I2C_CR1_ENARP_Msk (0x1U << I2C_CR1_ENARP_Pos) /*!< 0x00000010 */ 09646 #define I2C_CR1_ENARP I2C_CR1_ENARP_Msk /*!< ARP Enable */ 09647 #define I2C_CR1_ENPEC_Pos (5U) 09648 #define I2C_CR1_ENPEC_Msk (0x1U << I2C_CR1_ENPEC_Pos) /*!< 0x00000020 */ 09649 #define I2C_CR1_ENPEC I2C_CR1_ENPEC_Msk /*!< PEC Enable */ 09650 #define I2C_CR1_ENGC_Pos (6U) 09651 #define I2C_CR1_ENGC_Msk (0x1U << I2C_CR1_ENGC_Pos) /*!< 0x00000040 */ 09652 #define I2C_CR1_ENGC I2C_CR1_ENGC_Msk /*!< General Call Enable */ 09653 #define I2C_CR1_NOSTRETCH_Pos (7U) 09654 #define I2C_CR1_NOSTRETCH_Msk (0x1U << I2C_CR1_NOSTRETCH_Pos) /*!< 0x00000080 */ 09655 #define I2C_CR1_NOSTRETCH I2C_CR1_NOSTRETCH_Msk /*!< Clock Stretching Disable (Slave mode) */ 09656 #define I2C_CR1_START_Pos (8U) 09657 #define I2C_CR1_START_Msk (0x1U << I2C_CR1_START_Pos) /*!< 0x00000100 */ 09658 #define I2C_CR1_START I2C_CR1_START_Msk /*!< Start Generation */ 09659 #define I2C_CR1_STOP_Pos (9U) 09660 #define I2C_CR1_STOP_Msk (0x1U << I2C_CR1_STOP_Pos) /*!< 0x00000200 */ 09661 #define I2C_CR1_STOP I2C_CR1_STOP_Msk /*!< Stop Generation */ 09662 #define I2C_CR1_ACK_Pos (10U) 09663 #define I2C_CR1_ACK_Msk (0x1U << I2C_CR1_ACK_Pos) /*!< 0x00000400 */ 09664 #define I2C_CR1_ACK I2C_CR1_ACK_Msk /*!< Acknowledge Enable */ 09665 #define I2C_CR1_POS_Pos (11U) 09666 #define I2C_CR1_POS_Msk (0x1U << I2C_CR1_POS_Pos) /*!< 0x00000800 */ 09667 #define I2C_CR1_POS I2C_CR1_POS_Msk /*!< Acknowledge/PEC Position (for data reception) */ 09668 #define I2C_CR1_PEC_Pos (12U) 09669 #define I2C_CR1_PEC_Msk (0x1U << I2C_CR1_PEC_Pos) /*!< 0x00001000 */ 09670 #define I2C_CR1_PEC I2C_CR1_PEC_Msk /*!< Packet Error Checking */ 09671 #define I2C_CR1_ALERT_Pos (13U) 09672 #define I2C_CR1_ALERT_Msk (0x1U << I2C_CR1_ALERT_Pos) /*!< 0x00002000 */ 09673 #define I2C_CR1_ALERT I2C_CR1_ALERT_Msk /*!< SMBus Alert */ 09674 #define I2C_CR1_SWRST_Pos (15U) 09675 #define I2C_CR1_SWRST_Msk (0x1U << I2C_CR1_SWRST_Pos) /*!< 0x00008000 */ 09676 #define I2C_CR1_SWRST I2C_CR1_SWRST_Msk /*!< Software Reset */ 09677 09678 /******************* Bit definition for I2C_CR2 register ********************/ 09679 #define I2C_CR2_FREQ_Pos (0U) 09680 #define I2C_CR2_FREQ_Msk (0x3FU << I2C_CR2_FREQ_Pos) /*!< 0x0000003F */ 09681 #define I2C_CR2_FREQ I2C_CR2_FREQ_Msk /*!< FREQ[5:0] bits (Peripheral Clock Frequency) */ 09682 #define I2C_CR2_FREQ_0 (0x01U << I2C_CR2_FREQ_Pos) /*!< 0x00000001 */ 09683 #define I2C_CR2_FREQ_1 (0x02U << I2C_CR2_FREQ_Pos) /*!< 0x00000002 */ 09684 #define I2C_CR2_FREQ_2 (0x04U << I2C_CR2_FREQ_Pos) /*!< 0x00000004 */ 09685 #define I2C_CR2_FREQ_3 (0x08U << I2C_CR2_FREQ_Pos) /*!< 0x00000008 */ 09686 #define I2C_CR2_FREQ_4 (0x10U << I2C_CR2_FREQ_Pos) /*!< 0x00000010 */ 09687 #define I2C_CR2_FREQ_5 (0x20U << I2C_CR2_FREQ_Pos) /*!< 0x00000020 */ 09688 09689 #define I2C_CR2_ITERREN_Pos (8U) 09690 #define I2C_CR2_ITERREN_Msk (0x1U << I2C_CR2_ITERREN_Pos) /*!< 0x00000100 */ 09691 #define I2C_CR2_ITERREN I2C_CR2_ITERREN_Msk /*!< Error Interrupt Enable */ 09692 #define I2C_CR2_ITEVTEN_Pos (9U) 09693 #define I2C_CR2_ITEVTEN_Msk (0x1U << I2C_CR2_ITEVTEN_Pos) /*!< 0x00000200 */ 09694 #define I2C_CR2_ITEVTEN I2C_CR2_ITEVTEN_Msk /*!< Event Interrupt Enable */ 09695 #define I2C_CR2_ITBUFEN_Pos (10U) 09696 #define I2C_CR2_ITBUFEN_Msk (0x1U << I2C_CR2_ITBUFEN_Pos) /*!< 0x00000400 */ 09697 #define I2C_CR2_ITBUFEN I2C_CR2_ITBUFEN_Msk /*!< Buffer Interrupt Enable */ 09698 #define I2C_CR2_DMAEN_Pos (11U) 09699 #define I2C_CR2_DMAEN_Msk (0x1U << I2C_CR2_DMAEN_Pos) /*!< 0x00000800 */ 09700 #define I2C_CR2_DMAEN I2C_CR2_DMAEN_Msk /*!< DMA Requests Enable */ 09701 #define I2C_CR2_LAST_Pos (12U) 09702 #define I2C_CR2_LAST_Msk (0x1U << I2C_CR2_LAST_Pos) /*!< 0x00001000 */ 09703 #define I2C_CR2_LAST I2C_CR2_LAST_Msk /*!< DMA Last Transfer */ 09704 09705 /******************* Bit definition for I2C_OAR1 register *******************/ 09706 #define I2C_OAR1_ADD1_7 ((uint32_t)0x000000FE) /*!< Interface Address */ 09707 #define I2C_OAR1_ADD8_9 ((uint32_t)0x00000300) /*!< Interface Address */ 09708 09709 #define I2C_OAR1_ADD0_Pos (0U) 09710 #define I2C_OAR1_ADD0_Msk (0x1U << I2C_OAR1_ADD0_Pos) /*!< 0x00000001 */ 09711 #define I2C_OAR1_ADD0 I2C_OAR1_ADD0_Msk /*!< Bit 0 */ 09712 #define I2C_OAR1_ADD1_Pos (1U) 09713 #define I2C_OAR1_ADD1_Msk (0x1U << I2C_OAR1_ADD1_Pos) /*!< 0x00000002 */ 09714 #define I2C_OAR1_ADD1 I2C_OAR1_ADD1_Msk /*!< Bit 1 */ 09715 #define I2C_OAR1_ADD2_Pos (2U) 09716 #define I2C_OAR1_ADD2_Msk (0x1U << I2C_OAR1_ADD2_Pos) /*!< 0x00000004 */ 09717 #define I2C_OAR1_ADD2 I2C_OAR1_ADD2_Msk /*!< Bit 2 */ 09718 #define I2C_OAR1_ADD3_Pos (3U) 09719 #define I2C_OAR1_ADD3_Msk (0x1U << I2C_OAR1_ADD3_Pos) /*!< 0x00000008 */ 09720 #define I2C_OAR1_ADD3 I2C_OAR1_ADD3_Msk /*!< Bit 3 */ 09721 #define I2C_OAR1_ADD4_Pos (4U) 09722 #define I2C_OAR1_ADD4_Msk (0x1U << I2C_OAR1_ADD4_Pos) /*!< 0x00000010 */ 09723 #define I2C_OAR1_ADD4 I2C_OAR1_ADD4_Msk /*!< Bit 4 */ 09724 #define I2C_OAR1_ADD5_Pos (5U) 09725 #define I2C_OAR1_ADD5_Msk (0x1U << I2C_OAR1_ADD5_Pos) /*!< 0x00000020 */ 09726 #define I2C_OAR1_ADD5 I2C_OAR1_ADD5_Msk /*!< Bit 5 */ 09727 #define I2C_OAR1_ADD6_Pos (6U) 09728 #define I2C_OAR1_ADD6_Msk (0x1U << I2C_OAR1_ADD6_Pos) /*!< 0x00000040 */ 09729 #define I2C_OAR1_ADD6 I2C_OAR1_ADD6_Msk /*!< Bit 6 */ 09730 #define I2C_OAR1_ADD7_Pos (7U) 09731 #define I2C_OAR1_ADD7_Msk (0x1U << I2C_OAR1_ADD7_Pos) /*!< 0x00000080 */ 09732 #define I2C_OAR1_ADD7 I2C_OAR1_ADD7_Msk /*!< Bit 7 */ 09733 #define I2C_OAR1_ADD8_Pos (8U) 09734 #define I2C_OAR1_ADD8_Msk (0x1U << I2C_OAR1_ADD8_Pos) /*!< 0x00000100 */ 09735 #define I2C_OAR1_ADD8 I2C_OAR1_ADD8_Msk /*!< Bit 8 */ 09736 #define I2C_OAR1_ADD9_Pos (9U) 09737 #define I2C_OAR1_ADD9_Msk (0x1U << I2C_OAR1_ADD9_Pos) /*!< 0x00000200 */ 09738 #define I2C_OAR1_ADD9 I2C_OAR1_ADD9_Msk /*!< Bit 9 */ 09739 09740 #define I2C_OAR1_ADDMODE_Pos (15U) 09741 #define I2C_OAR1_ADDMODE_Msk (0x1U << I2C_OAR1_ADDMODE_Pos) /*!< 0x00008000 */ 09742 #define I2C_OAR1_ADDMODE I2C_OAR1_ADDMODE_Msk /*!< Addressing Mode (Slave mode) */ 09743 09744 /******************* Bit definition for I2C_OAR2 register *******************/ 09745 #define I2C_OAR2_ENDUAL_Pos (0U) 09746 #define I2C_OAR2_ENDUAL_Msk (0x1U << I2C_OAR2_ENDUAL_Pos) /*!< 0x00000001 */ 09747 #define I2C_OAR2_ENDUAL I2C_OAR2_ENDUAL_Msk /*!< Dual addressing mode enable */ 09748 #define I2C_OAR2_ADD2_Pos (1U) 09749 #define I2C_OAR2_ADD2_Msk (0x7FU << I2C_OAR2_ADD2_Pos) /*!< 0x000000FE */ 09750 #define I2C_OAR2_ADD2 I2C_OAR2_ADD2_Msk /*!< Interface address */ 09751 09752 /******************* Bit definition for I2C_SR1 register ********************/ 09753 #define I2C_SR1_SB_Pos (0U) 09754 #define I2C_SR1_SB_Msk (0x1U << I2C_SR1_SB_Pos) /*!< 0x00000001 */ 09755 #define I2C_SR1_SB I2C_SR1_SB_Msk /*!< Start Bit (Master mode) */ 09756 #define I2C_SR1_ADDR_Pos (1U) 09757 #define I2C_SR1_ADDR_Msk (0x1U << I2C_SR1_ADDR_Pos) /*!< 0x00000002 */ 09758 #define I2C_SR1_ADDR I2C_SR1_ADDR_Msk /*!< Address sent (master mode)/matched (slave mode) */ 09759 #define I2C_SR1_BTF_Pos (2U) 09760 #define I2C_SR1_BTF_Msk (0x1U << I2C_SR1_BTF_Pos) /*!< 0x00000004 */ 09761 #define I2C_SR1_BTF I2C_SR1_BTF_Msk /*!< Byte Transfer Finished */ 09762 #define I2C_SR1_ADD10_Pos (3U) 09763 #define I2C_SR1_ADD10_Msk (0x1U << I2C_SR1_ADD10_Pos) /*!< 0x00000008 */ 09764 #define I2C_SR1_ADD10 I2C_SR1_ADD10_Msk /*!< 10-bit header sent (Master mode) */ 09765 #define I2C_SR1_STOPF_Pos (4U) 09766 #define I2C_SR1_STOPF_Msk (0x1U << I2C_SR1_STOPF_Pos) /*!< 0x00000010 */ 09767 #define I2C_SR1_STOPF I2C_SR1_STOPF_Msk /*!< Stop detection (Slave mode) */ 09768 #define I2C_SR1_RXNE_Pos (6U) 09769 #define I2C_SR1_RXNE_Msk (0x1U << I2C_SR1_RXNE_Pos) /*!< 0x00000040 */ 09770 #define I2C_SR1_RXNE I2C_SR1_RXNE_Msk /*!< Data Register not Empty (receivers) */ 09771 #define I2C_SR1_TXE_Pos (7U) 09772 #define I2C_SR1_TXE_Msk (0x1U << I2C_SR1_TXE_Pos) /*!< 0x00000080 */ 09773 #define I2C_SR1_TXE I2C_SR1_TXE_Msk /*!< Data Register Empty (transmitters) */ 09774 #define I2C_SR1_BERR_Pos (8U) 09775 #define I2C_SR1_BERR_Msk (0x1U << I2C_SR1_BERR_Pos) /*!< 0x00000100 */ 09776 #define I2C_SR1_BERR I2C_SR1_BERR_Msk /*!< Bus Error */ 09777 #define I2C_SR1_ARLO_Pos (9U) 09778 #define I2C_SR1_ARLO_Msk (0x1U << I2C_SR1_ARLO_Pos) /*!< 0x00000200 */ 09779 #define I2C_SR1_ARLO I2C_SR1_ARLO_Msk /*!< Arbitration Lost (master mode) */ 09780 #define I2C_SR1_AF_Pos (10U) 09781 #define I2C_SR1_AF_Msk (0x1U << I2C_SR1_AF_Pos) /*!< 0x00000400 */ 09782 #define I2C_SR1_AF I2C_SR1_AF_Msk /*!< Acknowledge Failure */ 09783 #define I2C_SR1_OVR_Pos (11U) 09784 #define I2C_SR1_OVR_Msk (0x1U << I2C_SR1_OVR_Pos) /*!< 0x00000800 */ 09785 #define I2C_SR1_OVR I2C_SR1_OVR_Msk /*!< Overrun/Underrun */ 09786 #define I2C_SR1_PECERR_Pos (12U) 09787 #define I2C_SR1_PECERR_Msk (0x1U << I2C_SR1_PECERR_Pos) /*!< 0x00001000 */ 09788 #define I2C_SR1_PECERR I2C_SR1_PECERR_Msk /*!< PEC Error in reception */ 09789 #define I2C_SR1_TIMEOUT_Pos (14U) 09790 #define I2C_SR1_TIMEOUT_Msk (0x1U << I2C_SR1_TIMEOUT_Pos) /*!< 0x00004000 */ 09791 #define I2C_SR1_TIMEOUT I2C_SR1_TIMEOUT_Msk /*!< Timeout or Tlow Error */ 09792 #define I2C_SR1_SMBALERT_Pos (15U) 09793 #define I2C_SR1_SMBALERT_Msk (0x1U << I2C_SR1_SMBALERT_Pos) /*!< 0x00008000 */ 09794 #define I2C_SR1_SMBALERT I2C_SR1_SMBALERT_Msk /*!< SMBus Alert */ 09795 09796 /******************* Bit definition for I2C_SR2 register ********************/ 09797 #define I2C_SR2_MSL_Pos (0U) 09798 #define I2C_SR2_MSL_Msk (0x1U << I2C_SR2_MSL_Pos) /*!< 0x00000001 */ 09799 #define I2C_SR2_MSL I2C_SR2_MSL_Msk /*!< Master/Slave */ 09800 #define I2C_SR2_BUSY_Pos (1U) 09801 #define I2C_SR2_BUSY_Msk (0x1U << I2C_SR2_BUSY_Pos) /*!< 0x00000002 */ 09802 #define I2C_SR2_BUSY I2C_SR2_BUSY_Msk /*!< Bus Busy */ 09803 #define I2C_SR2_TRA_Pos (2U) 09804 #define I2C_SR2_TRA_Msk (0x1U << I2C_SR2_TRA_Pos) /*!< 0x00000004 */ 09805 #define I2C_SR2_TRA I2C_SR2_TRA_Msk /*!< Transmitter/Receiver */ 09806 #define I2C_SR2_GENCALL_Pos (4U) 09807 #define I2C_SR2_GENCALL_Msk (0x1U << I2C_SR2_GENCALL_Pos) /*!< 0x00000010 */ 09808 #define I2C_SR2_GENCALL I2C_SR2_GENCALL_Msk /*!< General Call Address (Slave mode) */ 09809 #define I2C_SR2_SMBDEFAULT_Pos (5U) 09810 #define I2C_SR2_SMBDEFAULT_Msk (0x1U << I2C_SR2_SMBDEFAULT_Pos) /*!< 0x00000020 */ 09811 #define I2C_SR2_SMBDEFAULT I2C_SR2_SMBDEFAULT_Msk /*!< SMBus Device Default Address (Slave mode) */ 09812 #define I2C_SR2_SMBHOST_Pos (6U) 09813 #define I2C_SR2_SMBHOST_Msk (0x1U << I2C_SR2_SMBHOST_Pos) /*!< 0x00000040 */ 09814 #define I2C_SR2_SMBHOST I2C_SR2_SMBHOST_Msk /*!< SMBus Host Header (Slave mode) */ 09815 #define I2C_SR2_DUALF_Pos (7U) 09816 #define I2C_SR2_DUALF_Msk (0x1U << I2C_SR2_DUALF_Pos) /*!< 0x00000080 */ 09817 #define I2C_SR2_DUALF I2C_SR2_DUALF_Msk /*!< Dual Flag (Slave mode) */ 09818 #define I2C_SR2_PEC_Pos (8U) 09819 #define I2C_SR2_PEC_Msk (0xFFU << I2C_SR2_PEC_Pos) /*!< 0x0000FF00 */ 09820 #define I2C_SR2_PEC I2C_SR2_PEC_Msk /*!< Packet Error Checking Register */ 09821 09822 /******************* Bit definition for I2C_CCR register ********************/ 09823 #define I2C_CCR_CCR_Pos (0U) 09824 #define I2C_CCR_CCR_Msk (0xFFFU << I2C_CCR_CCR_Pos) /*!< 0x00000FFF */ 09825 #define I2C_CCR_CCR I2C_CCR_CCR_Msk /*!< Clock Control Register in Fast/Standard mode (Master mode) */ 09826 #define I2C_CCR_DUTY_Pos (14U) 09827 #define I2C_CCR_DUTY_Msk (0x1U << I2C_CCR_DUTY_Pos) /*!< 0x00004000 */ 09828 #define I2C_CCR_DUTY I2C_CCR_DUTY_Msk /*!< Fast Mode Duty Cycle */ 09829 #define I2C_CCR_FS_Pos (15U) 09830 #define I2C_CCR_FS_Msk (0x1U << I2C_CCR_FS_Pos) /*!< 0x00008000 */ 09831 #define I2C_CCR_FS I2C_CCR_FS_Msk /*!< I2C Master Mode Selection */ 09832 09833 /****************** Bit definition for I2C_TRISE register *******************/ 09834 #define I2C_TRISE_TRISE_Pos (0U) 09835 #define I2C_TRISE_TRISE_Msk (0x3FU << I2C_TRISE_TRISE_Pos) /*!< 0x0000003F */ 09836 #define I2C_TRISE_TRISE I2C_TRISE_TRISE_Msk /*!< Maximum Rise Time in Fast/Standard mode (Master mode) */ 09837 09838 /******************************************************************************/ 09839 /* */ 09840 /* Universal Synchronous Asynchronous Receiver Transmitter */ 09841 /* */ 09842 /******************************************************************************/ 09843 09844 /******************* Bit definition for USART_SR register *******************/ 09845 #define USART_SR_PE_Pos (0U) 09846 #define USART_SR_PE_Msk (0x1U << USART_SR_PE_Pos) /*!< 0x00000001 */ 09847 #define USART_SR_PE USART_SR_PE_Msk /*!< Parity Error */ 09848 #define USART_SR_FE_Pos (1U) 09849 #define USART_SR_FE_Msk (0x1U << USART_SR_FE_Pos) /*!< 0x00000002 */ 09850 #define USART_SR_FE USART_SR_FE_Msk /*!< Framing Error */ 09851 #define USART_SR_NE_Pos (2U) 09852 #define USART_SR_NE_Msk (0x1U << USART_SR_NE_Pos) /*!< 0x00000004 */ 09853 #define USART_SR_NE USART_SR_NE_Msk /*!< Noise Error Flag */ 09854 #define USART_SR_ORE_Pos (3U) 09855 #define USART_SR_ORE_Msk (0x1U << USART_SR_ORE_Pos) /*!< 0x00000008 */ 09856 #define USART_SR_ORE USART_SR_ORE_Msk /*!< OverRun Error */ 09857 #define USART_SR_IDLE_Pos (4U) 09858 #define USART_SR_IDLE_Msk (0x1U << USART_SR_IDLE_Pos) /*!< 0x00000010 */ 09859 #define USART_SR_IDLE USART_SR_IDLE_Msk /*!< IDLE line detected */ 09860 #define USART_SR_RXNE_Pos (5U) 09861 #define USART_SR_RXNE_Msk (0x1U << USART_SR_RXNE_Pos) /*!< 0x00000020 */ 09862 #define USART_SR_RXNE USART_SR_RXNE_Msk /*!< Read Data Register Not Empty */ 09863 #define USART_SR_TC_Pos (6U) 09864 #define USART_SR_TC_Msk (0x1U << USART_SR_TC_Pos) /*!< 0x00000040 */ 09865 #define USART_SR_TC USART_SR_TC_Msk /*!< Transmission Complete */ 09866 #define USART_SR_TXE_Pos (7U) 09867 #define USART_SR_TXE_Msk (0x1U << USART_SR_TXE_Pos) /*!< 0x00000080 */ 09868 #define USART_SR_TXE USART_SR_TXE_Msk /*!< Transmit Data Register Empty */ 09869 #define USART_SR_LBD_Pos (8U) 09870 #define USART_SR_LBD_Msk (0x1U << USART_SR_LBD_Pos) /*!< 0x00000100 */ 09871 #define USART_SR_LBD USART_SR_LBD_Msk /*!< LIN Break Detection Flag */ 09872 #define USART_SR_CTS_Pos (9U) 09873 #define USART_SR_CTS_Msk (0x1U << USART_SR_CTS_Pos) /*!< 0x00000200 */ 09874 #define USART_SR_CTS USART_SR_CTS_Msk /*!< CTS Flag */ 09875 09876 /******************* Bit definition for USART_DR register *******************/ 09877 #define USART_DR_DR_Pos (0U) 09878 #define USART_DR_DR_Msk (0x1FFU << USART_DR_DR_Pos) /*!< 0x000001FF */ 09879 #define USART_DR_DR USART_DR_DR_Msk /*!< Data value */ 09880 09881 /****************** Bit definition for USART_BRR register *******************/ 09882 #define USART_BRR_DIV_Fraction_Pos (0U) 09883 #define USART_BRR_DIV_Fraction_Msk (0xFU << USART_BRR_DIV_Fraction_Pos) /*!< 0x0000000F */ 09884 #define USART_BRR_DIV_Fraction USART_BRR_DIV_Fraction_Msk /*!< Fraction of USARTDIV */ 09885 #define USART_BRR_DIV_Mantissa_Pos (4U) 09886 #define USART_BRR_DIV_Mantissa_Msk (0xFFFU << USART_BRR_DIV_Mantissa_Pos) /*!< 0x0000FFF0 */ 09887 #define USART_BRR_DIV_Mantissa USART_BRR_DIV_Mantissa_Msk /*!< Mantissa of USARTDIV */ 09888 09889 /****************** Bit definition for USART_CR1 register *******************/ 09890 #define USART_CR1_SBK_Pos (0U) 09891 #define USART_CR1_SBK_Msk (0x1U << USART_CR1_SBK_Pos) /*!< 0x00000001 */ 09892 #define USART_CR1_SBK USART_CR1_SBK_Msk /*!< Send Break */ 09893 #define USART_CR1_RWU_Pos (1U) 09894 #define USART_CR1_RWU_Msk (0x1U << USART_CR1_RWU_Pos) /*!< 0x00000002 */ 09895 #define USART_CR1_RWU USART_CR1_RWU_Msk /*!< Receiver wakeup */ 09896 #define USART_CR1_RE_Pos (2U) 09897 #define USART_CR1_RE_Msk (0x1U << USART_CR1_RE_Pos) /*!< 0x00000004 */ 09898 #define USART_CR1_RE USART_CR1_RE_Msk /*!< Receiver Enable */ 09899 #define USART_CR1_TE_Pos (3U) 09900 #define USART_CR1_TE_Msk (0x1U << USART_CR1_TE_Pos) /*!< 0x00000008 */ 09901 #define USART_CR1_TE USART_CR1_TE_Msk /*!< Transmitter Enable */ 09902 #define USART_CR1_IDLEIE_Pos (4U) 09903 #define USART_CR1_IDLEIE_Msk (0x1U << USART_CR1_IDLEIE_Pos) /*!< 0x00000010 */ 09904 #define USART_CR1_IDLEIE USART_CR1_IDLEIE_Msk /*!< IDLE Interrupt Enable */ 09905 #define USART_CR1_RXNEIE_Pos (5U) 09906 #define USART_CR1_RXNEIE_Msk (0x1U << USART_CR1_RXNEIE_Pos) /*!< 0x00000020 */ 09907 #define USART_CR1_RXNEIE USART_CR1_RXNEIE_Msk /*!< RXNE Interrupt Enable */ 09908 #define USART_CR1_TCIE_Pos (6U) 09909 #define USART_CR1_TCIE_Msk (0x1U << USART_CR1_TCIE_Pos) /*!< 0x00000040 */ 09910 #define USART_CR1_TCIE USART_CR1_TCIE_Msk /*!< Transmission Complete Interrupt Enable */ 09911 #define USART_CR1_TXEIE_Pos (7U) 09912 #define USART_CR1_TXEIE_Msk (0x1U << USART_CR1_TXEIE_Pos) /*!< 0x00000080 */ 09913 #define USART_CR1_TXEIE USART_CR1_TXEIE_Msk /*!< PE Interrupt Enable */ 09914 #define USART_CR1_PEIE_Pos (8U) 09915 #define USART_CR1_PEIE_Msk (0x1U << USART_CR1_PEIE_Pos) /*!< 0x00000100 */ 09916 #define USART_CR1_PEIE USART_CR1_PEIE_Msk /*!< PE Interrupt Enable */ 09917 #define USART_CR1_PS_Pos (9U) 09918 #define USART_CR1_PS_Msk (0x1U << USART_CR1_PS_Pos) /*!< 0x00000200 */ 09919 #define USART_CR1_PS USART_CR1_PS_Msk /*!< Parity Selection */ 09920 #define USART_CR1_PCE_Pos (10U) 09921 #define USART_CR1_PCE_Msk (0x1U << USART_CR1_PCE_Pos) /*!< 0x00000400 */ 09922 #define USART_CR1_PCE USART_CR1_PCE_Msk /*!< Parity Control Enable */ 09923 #define USART_CR1_WAKE_Pos (11U) 09924 #define USART_CR1_WAKE_Msk (0x1U << USART_CR1_WAKE_Pos) /*!< 0x00000800 */ 09925 #define USART_CR1_WAKE USART_CR1_WAKE_Msk /*!< Wakeup method */ 09926 #define USART_CR1_M_Pos (12U) 09927 #define USART_CR1_M_Msk (0x1U << USART_CR1_M_Pos) /*!< 0x00001000 */ 09928 #define USART_CR1_M USART_CR1_M_Msk /*!< Word length */ 09929 #define USART_CR1_UE_Pos (13U) 09930 #define USART_CR1_UE_Msk (0x1U << USART_CR1_UE_Pos) /*!< 0x00002000 */ 09931 #define USART_CR1_UE USART_CR1_UE_Msk /*!< USART Enable */ 09932 09933 /****************** Bit definition for USART_CR2 register *******************/ 09934 #define USART_CR2_ADD_Pos (0U) 09935 #define USART_CR2_ADD_Msk (0xFU << USART_CR2_ADD_Pos) /*!< 0x0000000F */ 09936 #define USART_CR2_ADD USART_CR2_ADD_Msk /*!< Address of the USART node */ 09937 #define USART_CR2_LBDL_Pos (5U) 09938 #define USART_CR2_LBDL_Msk (0x1U << USART_CR2_LBDL_Pos) /*!< 0x00000020 */ 09939 #define USART_CR2_LBDL USART_CR2_LBDL_Msk /*!< LIN Break Detection Length */ 09940 #define USART_CR2_LBDIE_Pos (6U) 09941 #define USART_CR2_LBDIE_Msk (0x1U << USART_CR2_LBDIE_Pos) /*!< 0x00000040 */ 09942 #define USART_CR2_LBDIE USART_CR2_LBDIE_Msk /*!< LIN Break Detection Interrupt Enable */ 09943 #define USART_CR2_LBCL_Pos (8U) 09944 #define USART_CR2_LBCL_Msk (0x1U << USART_CR2_LBCL_Pos) /*!< 0x00000100 */ 09945 #define USART_CR2_LBCL USART_CR2_LBCL_Msk /*!< Last Bit Clock pulse */ 09946 #define USART_CR2_CPHA_Pos (9U) 09947 #define USART_CR2_CPHA_Msk (0x1U << USART_CR2_CPHA_Pos) /*!< 0x00000200 */ 09948 #define USART_CR2_CPHA USART_CR2_CPHA_Msk /*!< Clock Phase */ 09949 #define USART_CR2_CPOL_Pos (10U) 09950 #define USART_CR2_CPOL_Msk (0x1U << USART_CR2_CPOL_Pos) /*!< 0x00000400 */ 09951 #define USART_CR2_CPOL USART_CR2_CPOL_Msk /*!< Clock Polarity */ 09952 #define USART_CR2_CLKEN_Pos (11U) 09953 #define USART_CR2_CLKEN_Msk (0x1U << USART_CR2_CLKEN_Pos) /*!< 0x00000800 */ 09954 #define USART_CR2_CLKEN USART_CR2_CLKEN_Msk /*!< Clock Enable */ 09955 09956 #define USART_CR2_STOP_Pos (12U) 09957 #define USART_CR2_STOP_Msk (0x3U << USART_CR2_STOP_Pos) /*!< 0x00003000 */ 09958 #define USART_CR2_STOP USART_CR2_STOP_Msk /*!< STOP[1:0] bits (STOP bits) */ 09959 #define USART_CR2_STOP_0 (0x1U << USART_CR2_STOP_Pos) /*!< 0x00001000 */ 09960 #define USART_CR2_STOP_1 (0x2U << USART_CR2_STOP_Pos) /*!< 0x00002000 */ 09961 09962 #define USART_CR2_LINEN_Pos (14U) 09963 #define USART_CR2_LINEN_Msk (0x1U << USART_CR2_LINEN_Pos) /*!< 0x00004000 */ 09964 #define USART_CR2_LINEN USART_CR2_LINEN_Msk /*!< LIN mode enable */ 09965 09966 /****************** Bit definition for USART_CR3 register *******************/ 09967 #define USART_CR3_EIE_Pos (0U) 09968 #define USART_CR3_EIE_Msk (0x1U << USART_CR3_EIE_Pos) /*!< 0x00000001 */ 09969 #define USART_CR3_EIE USART_CR3_EIE_Msk /*!< Error Interrupt Enable */ 09970 #define USART_CR3_IREN_Pos (1U) 09971 #define USART_CR3_IREN_Msk (0x1U << USART_CR3_IREN_Pos) /*!< 0x00000002 */ 09972 #define USART_CR3_IREN USART_CR3_IREN_Msk /*!< IrDA mode Enable */ 09973 #define USART_CR3_IRLP_Pos (2U) 09974 #define USART_CR3_IRLP_Msk (0x1U << USART_CR3_IRLP_Pos) /*!< 0x00000004 */ 09975 #define USART_CR3_IRLP USART_CR3_IRLP_Msk /*!< IrDA Low-Power */ 09976 #define USART_CR3_HDSEL_Pos (3U) 09977 #define USART_CR3_HDSEL_Msk (0x1U << USART_CR3_HDSEL_Pos) /*!< 0x00000008 */ 09978 #define USART_CR3_HDSEL USART_CR3_HDSEL_Msk /*!< Half-Duplex Selection */ 09979 #define USART_CR3_NACK_Pos (4U) 09980 #define USART_CR3_NACK_Msk (0x1U << USART_CR3_NACK_Pos) /*!< 0x00000010 */ 09981 #define USART_CR3_NACK USART_CR3_NACK_Msk /*!< Smartcard NACK enable */ 09982 #define USART_CR3_SCEN_Pos (5U) 09983 #define USART_CR3_SCEN_Msk (0x1U << USART_CR3_SCEN_Pos) /*!< 0x00000020 */ 09984 #define USART_CR3_SCEN USART_CR3_SCEN_Msk /*!< Smartcard mode enable */ 09985 #define USART_CR3_DMAR_Pos (6U) 09986 #define USART_CR3_DMAR_Msk (0x1U << USART_CR3_DMAR_Pos) /*!< 0x00000040 */ 09987 #define USART_CR3_DMAR USART_CR3_DMAR_Msk /*!< DMA Enable Receiver */ 09988 #define USART_CR3_DMAT_Pos (7U) 09989 #define USART_CR3_DMAT_Msk (0x1U << USART_CR3_DMAT_Pos) /*!< 0x00000080 */ 09990 #define USART_CR3_DMAT USART_CR3_DMAT_Msk /*!< DMA Enable Transmitter */ 09991 #define USART_CR3_RTSE_Pos (8U) 09992 #define USART_CR3_RTSE_Msk (0x1U << USART_CR3_RTSE_Pos) /*!< 0x00000100 */ 09993 #define USART_CR3_RTSE USART_CR3_RTSE_Msk /*!< RTS Enable */ 09994 #define USART_CR3_CTSE_Pos (9U) 09995 #define USART_CR3_CTSE_Msk (0x1U << USART_CR3_CTSE_Pos) /*!< 0x00000200 */ 09996 #define USART_CR3_CTSE USART_CR3_CTSE_Msk /*!< CTS Enable */ 09997 #define USART_CR3_CTSIE_Pos (10U) 09998 #define USART_CR3_CTSIE_Msk (0x1U << USART_CR3_CTSIE_Pos) /*!< 0x00000400 */ 09999 #define USART_CR3_CTSIE USART_CR3_CTSIE_Msk /*!< CTS Interrupt Enable */ 10000 10001 /****************** Bit definition for USART_GTPR register ******************/ 10002 #define USART_GTPR_PSC_Pos (0U) 10003 #define USART_GTPR_PSC_Msk (0xFFU << USART_GTPR_PSC_Pos) /*!< 0x000000FF */ 10004 #define USART_GTPR_PSC USART_GTPR_PSC_Msk /*!< PSC[7:0] bits (Prescaler value) */ 10005 #define USART_GTPR_PSC_0 (0x01U << USART_GTPR_PSC_Pos) /*!< 0x00000001 */ 10006 #define USART_GTPR_PSC_1 (0x02U << USART_GTPR_PSC_Pos) /*!< 0x00000002 */ 10007 #define USART_GTPR_PSC_2 (0x04U << USART_GTPR_PSC_Pos) /*!< 0x00000004 */ 10008 #define USART_GTPR_PSC_3 (0x08U << USART_GTPR_PSC_Pos) /*!< 0x00000008 */ 10009 #define USART_GTPR_PSC_4 (0x10U << USART_GTPR_PSC_Pos) /*!< 0x00000010 */ 10010 #define USART_GTPR_PSC_5 (0x20U << USART_GTPR_PSC_Pos) /*!< 0x00000020 */ 10011 #define USART_GTPR_PSC_6 (0x40U << USART_GTPR_PSC_Pos) /*!< 0x00000040 */ 10012 #define USART_GTPR_PSC_7 (0x80U << USART_GTPR_PSC_Pos) /*!< 0x00000080 */ 10013 10014 #define USART_GTPR_GT_Pos (8U) 10015 #define USART_GTPR_GT_Msk (0xFFU << USART_GTPR_GT_Pos) /*!< 0x0000FF00 */ 10016 #define USART_GTPR_GT USART_GTPR_GT_Msk /*!< Guard time value */ 10017 10018 /******************************************************************************/ 10019 /* */ 10020 /* Debug MCU */ 10021 /* */ 10022 /******************************************************************************/ 10023 10024 /**************** Bit definition for DBGMCU_IDCODE register *****************/ 10025 #define DBGMCU_IDCODE_DEV_ID_Pos (0U) 10026 #define DBGMCU_IDCODE_DEV_ID_Msk (0xFFFU << DBGMCU_IDCODE_DEV_ID_Pos) /*!< 0x00000FFF */ 10027 #define DBGMCU_IDCODE_DEV_ID DBGMCU_IDCODE_DEV_ID_Msk /*!< Device Identifier */ 10028 10029 #define DBGMCU_IDCODE_REV_ID_Pos (16U) 10030 #define DBGMCU_IDCODE_REV_ID_Msk (0xFFFFU << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0xFFFF0000 */ 10031 #define DBGMCU_IDCODE_REV_ID DBGMCU_IDCODE_REV_ID_Msk /*!< REV_ID[15:0] bits (Revision Identifier) */ 10032 #define DBGMCU_IDCODE_REV_ID_0 (0x0001U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00010000 */ 10033 #define DBGMCU_IDCODE_REV_ID_1 (0x0002U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00020000 */ 10034 #define DBGMCU_IDCODE_REV_ID_2 (0x0004U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00040000 */ 10035 #define DBGMCU_IDCODE_REV_ID_3 (0x0008U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00080000 */ 10036 #define DBGMCU_IDCODE_REV_ID_4 (0x0010U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00100000 */ 10037 #define DBGMCU_IDCODE_REV_ID_5 (0x0020U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00200000 */ 10038 #define DBGMCU_IDCODE_REV_ID_6 (0x0040U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00400000 */ 10039 #define DBGMCU_IDCODE_REV_ID_7 (0x0080U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00800000 */ 10040 #define DBGMCU_IDCODE_REV_ID_8 (0x0100U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x01000000 */ 10041 #define DBGMCU_IDCODE_REV_ID_9 (0x0200U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x02000000 */ 10042 #define DBGMCU_IDCODE_REV_ID_10 (0x0400U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x04000000 */ 10043 #define DBGMCU_IDCODE_REV_ID_11 (0x0800U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x08000000 */ 10044 #define DBGMCU_IDCODE_REV_ID_12 (0x1000U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x10000000 */ 10045 #define DBGMCU_IDCODE_REV_ID_13 (0x2000U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x20000000 */ 10046 #define DBGMCU_IDCODE_REV_ID_14 (0x4000U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x40000000 */ 10047 #define DBGMCU_IDCODE_REV_ID_15 (0x8000U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x80000000 */ 10048 10049 /****************** Bit definition for DBGMCU_CR register *******************/ 10050 #define DBGMCU_CR_DBG_SLEEP_Pos (0U) 10051 #define DBGMCU_CR_DBG_SLEEP_Msk (0x1U << DBGMCU_CR_DBG_SLEEP_Pos) /*!< 0x00000001 */ 10052 #define DBGMCU_CR_DBG_SLEEP DBGMCU_CR_DBG_SLEEP_Msk /*!< Debug Sleep Mode */ 10053 #define DBGMCU_CR_DBG_STOP_Pos (1U) 10054 #define DBGMCU_CR_DBG_STOP_Msk (0x1U << DBGMCU_CR_DBG_STOP_Pos) /*!< 0x00000002 */ 10055 #define DBGMCU_CR_DBG_STOP DBGMCU_CR_DBG_STOP_Msk /*!< Debug Stop Mode */ 10056 #define DBGMCU_CR_DBG_STANDBY_Pos (2U) 10057 #define DBGMCU_CR_DBG_STANDBY_Msk (0x1U << DBGMCU_CR_DBG_STANDBY_Pos) /*!< 0x00000004 */ 10058 #define DBGMCU_CR_DBG_STANDBY DBGMCU_CR_DBG_STANDBY_Msk /*!< Debug Standby mode */ 10059 #define DBGMCU_CR_TRACE_IOEN_Pos (5U) 10060 #define DBGMCU_CR_TRACE_IOEN_Msk (0x1U << DBGMCU_CR_TRACE_IOEN_Pos) /*!< 0x00000020 */ 10061 #define DBGMCU_CR_TRACE_IOEN DBGMCU_CR_TRACE_IOEN_Msk /*!< Trace Pin Assignment Control */ 10062 10063 #define DBGMCU_CR_TRACE_MODE_Pos (6U) 10064 #define DBGMCU_CR_TRACE_MODE_Msk (0x3U << DBGMCU_CR_TRACE_MODE_Pos) /*!< 0x000000C0 */ 10065 #define DBGMCU_CR_TRACE_MODE DBGMCU_CR_TRACE_MODE_Msk /*!< TRACE_MODE[1:0] bits (Trace Pin Assignment Control) */ 10066 #define DBGMCU_CR_TRACE_MODE_0 (0x1U << DBGMCU_CR_TRACE_MODE_Pos) /*!< 0x00000040 */ 10067 #define DBGMCU_CR_TRACE_MODE_1 (0x2U << DBGMCU_CR_TRACE_MODE_Pos) /*!< 0x00000080 */ 10068 10069 #define DBGMCU_CR_DBG_IWDG_STOP_Pos (8U) 10070 #define DBGMCU_CR_DBG_IWDG_STOP_Msk (0x1U << DBGMCU_CR_DBG_IWDG_STOP_Pos) /*!< 0x00000100 */ 10071 #define DBGMCU_CR_DBG_IWDG_STOP DBGMCU_CR_DBG_IWDG_STOP_Msk /*!< Debug Independent Watchdog stopped when Core is halted */ 10072 #define DBGMCU_CR_DBG_WWDG_STOP_Pos (9U) 10073 #define DBGMCU_CR_DBG_WWDG_STOP_Msk (0x1U << DBGMCU_CR_DBG_WWDG_STOP_Pos) /*!< 0x00000200 */ 10074 #define DBGMCU_CR_DBG_WWDG_STOP DBGMCU_CR_DBG_WWDG_STOP_Msk /*!< Debug Window Watchdog stopped when Core is halted */ 10075 #define DBGMCU_CR_DBG_TIM1_STOP_Pos (10U) 10076 #define DBGMCU_CR_DBG_TIM1_STOP_Msk (0x1U << DBGMCU_CR_DBG_TIM1_STOP_Pos) /*!< 0x00000400 */ 10077 #define DBGMCU_CR_DBG_TIM1_STOP DBGMCU_CR_DBG_TIM1_STOP_Msk /*!< TIM1 counter stopped when core is halted */ 10078 #define DBGMCU_CR_DBG_TIM2_STOP_Pos (11U) 10079 #define DBGMCU_CR_DBG_TIM2_STOP_Msk (0x1U << DBGMCU_CR_DBG_TIM2_STOP_Pos) /*!< 0x00000800 */ 10080 #define DBGMCU_CR_DBG_TIM2_STOP DBGMCU_CR_DBG_TIM2_STOP_Msk /*!< TIM2 counter stopped when core is halted */ 10081 #define DBGMCU_CR_DBG_TIM3_STOP_Pos (12U) 10082 #define DBGMCU_CR_DBG_TIM3_STOP_Msk (0x1U << DBGMCU_CR_DBG_TIM3_STOP_Pos) /*!< 0x00001000 */ 10083 #define DBGMCU_CR_DBG_TIM3_STOP DBGMCU_CR_DBG_TIM3_STOP_Msk /*!< TIM3 counter stopped when core is halted */ 10084 #define DBGMCU_CR_DBG_TIM4_STOP_Pos (13U) 10085 #define DBGMCU_CR_DBG_TIM4_STOP_Msk (0x1U << DBGMCU_CR_DBG_TIM4_STOP_Pos) /*!< 0x00002000 */ 10086 #define DBGMCU_CR_DBG_TIM4_STOP DBGMCU_CR_DBG_TIM4_STOP_Msk /*!< TIM4 counter stopped when core is halted */ 10087 #define DBGMCU_CR_DBG_CAN1_STOP_Pos (14U) 10088 #define DBGMCU_CR_DBG_CAN1_STOP_Msk (0x1U << DBGMCU_CR_DBG_CAN1_STOP_Pos) /*!< 0x00004000 */ 10089 #define DBGMCU_CR_DBG_CAN1_STOP DBGMCU_CR_DBG_CAN1_STOP_Msk /*!< Debug CAN1 stopped when Core is halted */ 10090 #define DBGMCU_CR_DBG_I2C1_SMBUS_TIMEOUT_Pos (15U) 10091 #define DBGMCU_CR_DBG_I2C1_SMBUS_TIMEOUT_Msk (0x1U << DBGMCU_CR_DBG_I2C1_SMBUS_TIMEOUT_Pos) /*!< 0x00008000 */ 10092 #define DBGMCU_CR_DBG_I2C1_SMBUS_TIMEOUT DBGMCU_CR_DBG_I2C1_SMBUS_TIMEOUT_Msk /*!< SMBUS timeout mode stopped when Core is halted */ 10093 #define DBGMCU_CR_DBG_I2C2_SMBUS_TIMEOUT_Pos (16U) 10094 #define DBGMCU_CR_DBG_I2C2_SMBUS_TIMEOUT_Msk (0x1U << DBGMCU_CR_DBG_I2C2_SMBUS_TIMEOUT_Pos) /*!< 0x00010000 */ 10095 #define DBGMCU_CR_DBG_I2C2_SMBUS_TIMEOUT DBGMCU_CR_DBG_I2C2_SMBUS_TIMEOUT_Msk /*!< SMBUS timeout mode stopped when Core is halted */ 10096 10097 /******************************************************************************/ 10098 /* */ 10099 /* FLASH and Option Bytes Registers */ 10100 /* */ 10101 /******************************************************************************/ 10102 /******************* Bit definition for FLASH_ACR register ******************/ 10103 #define FLASH_ACR_LATENCY_Pos (0U) 10104 #define FLASH_ACR_LATENCY_Msk (0x7U << FLASH_ACR_LATENCY_Pos) /*!< 0x00000007 */ 10105 #define FLASH_ACR_LATENCY FLASH_ACR_LATENCY_Msk /*!< LATENCY[2:0] bits (Latency) */ 10106 #define FLASH_ACR_LATENCY_0 (0x1U << FLASH_ACR_LATENCY_Pos) /*!< 0x00000001 */ 10107 #define FLASH_ACR_LATENCY_1 (0x2U << FLASH_ACR_LATENCY_Pos) /*!< 0x00000002 */ 10108 #define FLASH_ACR_LATENCY_2 (0x4U << FLASH_ACR_LATENCY_Pos) /*!< 0x00000004 */ 10109 10110 #define FLASH_ACR_HLFCYA_Pos (3U) 10111 #define FLASH_ACR_HLFCYA_Msk (0x1U << FLASH_ACR_HLFCYA_Pos) /*!< 0x00000008 */ 10112 #define FLASH_ACR_HLFCYA FLASH_ACR_HLFCYA_Msk /*!< Flash Half Cycle Access Enable */ 10113 #define FLASH_ACR_PRFTBE_Pos (4U) 10114 #define FLASH_ACR_PRFTBE_Msk (0x1U << FLASH_ACR_PRFTBE_Pos) /*!< 0x00000010 */ 10115 #define FLASH_ACR_PRFTBE FLASH_ACR_PRFTBE_Msk /*!< Prefetch Buffer Enable */ 10116 #define FLASH_ACR_PRFTBS_Pos (5U) 10117 #define FLASH_ACR_PRFTBS_Msk (0x1U << FLASH_ACR_PRFTBS_Pos) /*!< 0x00000020 */ 10118 #define FLASH_ACR_PRFTBS FLASH_ACR_PRFTBS_Msk /*!< Prefetch Buffer Status */ 10119 10120 /****************** Bit definition for FLASH_KEYR register ******************/ 10121 #define FLASH_KEYR_FKEYR_Pos (0U) 10122 #define FLASH_KEYR_FKEYR_Msk (0xFFFFFFFFU << FLASH_KEYR_FKEYR_Pos) /*!< 0xFFFFFFFF */ 10123 #define FLASH_KEYR_FKEYR FLASH_KEYR_FKEYR_Msk /*!< FPEC Key */ 10124 10125 #define RDP_KEY_Pos (0U) 10126 #define RDP_KEY_Msk (0xA5U << RDP_KEY_Pos) /*!< 0x000000A5 */ 10127 #define RDP_KEY RDP_KEY_Msk /*!< RDP Key */ 10128 #define FLASH_KEY1_Pos (0U) 10129 #define FLASH_KEY1_Msk (0x45670123U << FLASH_KEY1_Pos) /*!< 0x45670123 */ 10130 #define FLASH_KEY1 FLASH_KEY1_Msk /*!< FPEC Key1 */ 10131 #define FLASH_KEY2_Pos (0U) 10132 #define FLASH_KEY2_Msk (0xCDEF89ABU << FLASH_KEY2_Pos) /*!< 0xCDEF89AB */ 10133 #define FLASH_KEY2 FLASH_KEY2_Msk /*!< FPEC Key2 */ 10134 10135 /***************** Bit definition for FLASH_OPTKEYR register ****************/ 10136 #define FLASH_OPTKEYR_OPTKEYR_Pos (0U) 10137 #define FLASH_OPTKEYR_OPTKEYR_Msk (0xFFFFFFFFU << FLASH_OPTKEYR_OPTKEYR_Pos) /*!< 0xFFFFFFFF */ 10138 #define FLASH_OPTKEYR_OPTKEYR FLASH_OPTKEYR_OPTKEYR_Msk /*!< Option Byte Key */ 10139 10140 #define FLASH_OPTKEY1 FLASH_KEY1 /*!< Option Byte Key1 */ 10141 #define FLASH_OPTKEY2 FLASH_KEY2 /*!< Option Byte Key2 */ 10142 10143 /****************** Bit definition for FLASH_SR register ********************/ 10144 #define FLASH_SR_BSY_Pos (0U) 10145 #define FLASH_SR_BSY_Msk (0x1U << FLASH_SR_BSY_Pos) /*!< 0x00000001 */ 10146 #define FLASH_SR_BSY FLASH_SR_BSY_Msk /*!< Busy */ 10147 #define FLASH_SR_PGERR_Pos (2U) 10148 #define FLASH_SR_PGERR_Msk (0x1U << FLASH_SR_PGERR_Pos) /*!< 0x00000004 */ 10149 #define FLASH_SR_PGERR FLASH_SR_PGERR_Msk /*!< Programming Error */ 10150 #define FLASH_SR_WRPRTERR_Pos (4U) 10151 #define FLASH_SR_WRPRTERR_Msk (0x1U << FLASH_SR_WRPRTERR_Pos) /*!< 0x00000010 */ 10152 #define FLASH_SR_WRPRTERR FLASH_SR_WRPRTERR_Msk /*!< Write Protection Error */ 10153 #define FLASH_SR_EOP_Pos (5U) 10154 #define FLASH_SR_EOP_Msk (0x1U << FLASH_SR_EOP_Pos) /*!< 0x00000020 */ 10155 #define FLASH_SR_EOP FLASH_SR_EOP_Msk /*!< End of operation */ 10156 10157 /******************* Bit definition for FLASH_CR register *******************/ 10158 #define FLASH_CR_PG_Pos (0U) 10159 #define FLASH_CR_PG_Msk (0x1U << FLASH_CR_PG_Pos) /*!< 0x00000001 */ 10160 #define FLASH_CR_PG FLASH_CR_PG_Msk /*!< Programming */ 10161 #define FLASH_CR_PER_Pos (1U) 10162 #define FLASH_CR_PER_Msk (0x1U << FLASH_CR_PER_Pos) /*!< 0x00000002 */ 10163 #define FLASH_CR_PER FLASH_CR_PER_Msk /*!< Page Erase */ 10164 #define FLASH_CR_MER_Pos (2U) 10165 #define FLASH_CR_MER_Msk (0x1U << FLASH_CR_MER_Pos) /*!< 0x00000004 */ 10166 #define FLASH_CR_MER FLASH_CR_MER_Msk /*!< Mass Erase */ 10167 #define FLASH_CR_OPTPG_Pos (4U) 10168 #define FLASH_CR_OPTPG_Msk (0x1U << FLASH_CR_OPTPG_Pos) /*!< 0x00000010 */ 10169 #define FLASH_CR_OPTPG FLASH_CR_OPTPG_Msk /*!< Option Byte Programming */ 10170 #define FLASH_CR_OPTER_Pos (5U) 10171 #define FLASH_CR_OPTER_Msk (0x1U << FLASH_CR_OPTER_Pos) /*!< 0x00000020 */ 10172 #define FLASH_CR_OPTER FLASH_CR_OPTER_Msk /*!< Option Byte Erase */ 10173 #define FLASH_CR_STRT_Pos (6U) 10174 #define FLASH_CR_STRT_Msk (0x1U << FLASH_CR_STRT_Pos) /*!< 0x00000040 */ 10175 #define FLASH_CR_STRT FLASH_CR_STRT_Msk /*!< Start */ 10176 #define FLASH_CR_LOCK_Pos (7U) 10177 #define FLASH_CR_LOCK_Msk (0x1U << FLASH_CR_LOCK_Pos) /*!< 0x00000080 */ 10178 #define FLASH_CR_LOCK FLASH_CR_LOCK_Msk /*!< Lock */ 10179 #define FLASH_CR_OPTWRE_Pos (9U) 10180 #define FLASH_CR_OPTWRE_Msk (0x1U << FLASH_CR_OPTWRE_Pos) /*!< 0x00000200 */ 10181 #define FLASH_CR_OPTWRE FLASH_CR_OPTWRE_Msk /*!< Option Bytes Write Enable */ 10182 #define FLASH_CR_ERRIE_Pos (10U) 10183 #define FLASH_CR_ERRIE_Msk (0x1U << FLASH_CR_ERRIE_Pos) /*!< 0x00000400 */ 10184 #define FLASH_CR_ERRIE FLASH_CR_ERRIE_Msk /*!< Error Interrupt Enable */ 10185 #define FLASH_CR_EOPIE_Pos (12U) 10186 #define FLASH_CR_EOPIE_Msk (0x1U << FLASH_CR_EOPIE_Pos) /*!< 0x00001000 */ 10187 #define FLASH_CR_EOPIE FLASH_CR_EOPIE_Msk /*!< End of operation interrupt enable */ 10188 10189 /******************* Bit definition for FLASH_AR register *******************/ 10190 #define FLASH_AR_FAR_Pos (0U) 10191 #define FLASH_AR_FAR_Msk (0xFFFFFFFFU << FLASH_AR_FAR_Pos) /*!< 0xFFFFFFFF */ 10192 #define FLASH_AR_FAR FLASH_AR_FAR_Msk /*!< Flash Address */ 10193 10194 /****************** Bit definition for FLASH_OBR register *******************/ 10195 #define FLASH_OBR_OPTERR_Pos (0U) 10196 #define FLASH_OBR_OPTERR_Msk (0x1U << FLASH_OBR_OPTERR_Pos) /*!< 0x00000001 */ 10197 #define FLASH_OBR_OPTERR FLASH_OBR_OPTERR_Msk /*!< Option Byte Error */ 10198 #define FLASH_OBR_RDPRT_Pos (1U) 10199 #define FLASH_OBR_RDPRT_Msk (0x1U << FLASH_OBR_RDPRT_Pos) /*!< 0x00000002 */ 10200 #define FLASH_OBR_RDPRT FLASH_OBR_RDPRT_Msk /*!< Read protection */ 10201 10202 #define FLASH_OBR_IWDG_SW_Pos (2U) 10203 #define FLASH_OBR_IWDG_SW_Msk (0x1U << FLASH_OBR_IWDG_SW_Pos) /*!< 0x00000004 */ 10204 #define FLASH_OBR_IWDG_SW FLASH_OBR_IWDG_SW_Msk /*!< IWDG SW */ 10205 #define FLASH_OBR_nRST_STOP_Pos (3U) 10206 #define FLASH_OBR_nRST_STOP_Msk (0x1U << FLASH_OBR_nRST_STOP_Pos) /*!< 0x00000008 */ 10207 #define FLASH_OBR_nRST_STOP FLASH_OBR_nRST_STOP_Msk /*!< nRST_STOP */ 10208 #define FLASH_OBR_nRST_STDBY_Pos (4U) 10209 #define FLASH_OBR_nRST_STDBY_Msk (0x1U << FLASH_OBR_nRST_STDBY_Pos) /*!< 0x00000010 */ 10210 #define FLASH_OBR_nRST_STDBY FLASH_OBR_nRST_STDBY_Msk /*!< nRST_STDBY */ 10211 #define FLASH_OBR_USER_Pos (2U) 10212 #define FLASH_OBR_USER_Msk (0x7U << FLASH_OBR_USER_Pos) /*!< 0x0000001C */ 10213 #define FLASH_OBR_USER FLASH_OBR_USER_Msk /*!< User Option Bytes */ 10214 #define FLASH_OBR_DATA0_Pos (10U) 10215 #define FLASH_OBR_DATA0_Msk (0xFFU << FLASH_OBR_DATA0_Pos) /*!< 0x0003FC00 */ 10216 #define FLASH_OBR_DATA0 FLASH_OBR_DATA0_Msk /*!< Data0 */ 10217 #define FLASH_OBR_DATA1_Pos (18U) 10218 #define FLASH_OBR_DATA1_Msk (0xFFU << FLASH_OBR_DATA1_Pos) /*!< 0x03FC0000 */ 10219 #define FLASH_OBR_DATA1 FLASH_OBR_DATA1_Msk /*!< Data1 */ 10220 10221 /****************** Bit definition for FLASH_WRPR register ******************/ 10222 #define FLASH_WRPR_WRP_Pos (0U) 10223 #define FLASH_WRPR_WRP_Msk (0xFFFFFFFFU << FLASH_WRPR_WRP_Pos) /*!< 0xFFFFFFFF */ 10224 #define FLASH_WRPR_WRP FLASH_WRPR_WRP_Msk /*!< Write Protect */ 10225 10226 /*----------------------------------------------------------------------------*/ 10227 10228 /****************** Bit definition for FLASH_RDP register *******************/ 10229 #define FLASH_RDP_RDP_Pos (0U) 10230 #define FLASH_RDP_RDP_Msk (0xFFU << FLASH_RDP_RDP_Pos) /*!< 0x000000FF */ 10231 #define FLASH_RDP_RDP FLASH_RDP_RDP_Msk /*!< Read protection option byte */ 10232 #define FLASH_RDP_nRDP_Pos (8U) 10233 #define FLASH_RDP_nRDP_Msk (0xFFU << FLASH_RDP_nRDP_Pos) /*!< 0x0000FF00 */ 10234 #define FLASH_RDP_nRDP FLASH_RDP_nRDP_Msk /*!< Read protection complemented option byte */ 10235 10236 /****************** Bit definition for FLASH_USER register ******************/ 10237 #define FLASH_USER_USER_Pos (16U) 10238 #define FLASH_USER_USER_Msk (0xFFU << FLASH_USER_USER_Pos) /*!< 0x00FF0000 */ 10239 #define FLASH_USER_USER FLASH_USER_USER_Msk /*!< User option byte */ 10240 #define FLASH_USER_nUSER_Pos (24U) 10241 #define FLASH_USER_nUSER_Msk (0xFFU << FLASH_USER_nUSER_Pos) /*!< 0xFF000000 */ 10242 #define FLASH_USER_nUSER FLASH_USER_nUSER_Msk /*!< User complemented option byte */ 10243 10244 /****************** Bit definition for FLASH_Data0 register *****************/ 10245 #define FLASH_DATA0_DATA0_Pos (0U) 10246 #define FLASH_DATA0_DATA0_Msk (0xFFU << FLASH_DATA0_DATA0_Pos) /*!< 0x000000FF */ 10247 #define FLASH_DATA0_DATA0 FLASH_DATA0_DATA0_Msk /*!< User data storage option byte */ 10248 #define FLASH_DATA0_nDATA0_Pos (8U) 10249 #define FLASH_DATA0_nDATA0_Msk (0xFFU << FLASH_DATA0_nDATA0_Pos) /*!< 0x0000FF00 */ 10250 #define FLASH_DATA0_nDATA0 FLASH_DATA0_nDATA0_Msk /*!< User data storage complemented option byte */ 10251 10252 /****************** Bit definition for FLASH_Data1 register *****************/ 10253 #define FLASH_DATA1_DATA1_Pos (16U) 10254 #define FLASH_DATA1_DATA1_Msk (0xFFU << FLASH_DATA1_DATA1_Pos) /*!< 0x00FF0000 */ 10255 #define FLASH_DATA1_DATA1 FLASH_DATA1_DATA1_Msk /*!< User data storage option byte */ 10256 #define FLASH_DATA1_nDATA1_Pos (24U) 10257 #define FLASH_DATA1_nDATA1_Msk (0xFFU << FLASH_DATA1_nDATA1_Pos) /*!< 0xFF000000 */ 10258 #define FLASH_DATA1_nDATA1 FLASH_DATA1_nDATA1_Msk /*!< User data storage complemented option byte */ 10259 10260 /****************** Bit definition for FLASH_WRP0 register ******************/ 10261 #define FLASH_WRP0_WRP0_Pos (0U) 10262 #define FLASH_WRP0_WRP0_Msk (0xFFU << FLASH_WRP0_WRP0_Pos) /*!< 0x000000FF */ 10263 #define FLASH_WRP0_WRP0 FLASH_WRP0_WRP0_Msk /*!< Flash memory write protection option bytes */ 10264 #define FLASH_WRP0_nWRP0_Pos (8U) 10265 #define FLASH_WRP0_nWRP0_Msk (0xFFU << FLASH_WRP0_nWRP0_Pos) /*!< 0x0000FF00 */ 10266 #define FLASH_WRP0_nWRP0 FLASH_WRP0_nWRP0_Msk /*!< Flash memory write protection complemented option bytes */ 10267 10268 /****************** Bit definition for FLASH_WRP1 register ******************/ 10269 #define FLASH_WRP1_WRP1_Pos (16U) 10270 #define FLASH_WRP1_WRP1_Msk (0xFFU << FLASH_WRP1_WRP1_Pos) /*!< 0x00FF0000 */ 10271 #define FLASH_WRP1_WRP1 FLASH_WRP1_WRP1_Msk /*!< Flash memory write protection option bytes */ 10272 #define FLASH_WRP1_nWRP1_Pos (24U) 10273 #define FLASH_WRP1_nWRP1_Msk (0xFFU << FLASH_WRP1_nWRP1_Pos) /*!< 0xFF000000 */ 10274 #define FLASH_WRP1_nWRP1 FLASH_WRP1_nWRP1_Msk /*!< Flash memory write protection complemented option bytes */ 10275 10276 /****************** Bit definition for FLASH_WRP2 register ******************/ 10277 #define FLASH_WRP2_WRP2_Pos (0U) 10278 #define FLASH_WRP2_WRP2_Msk (0xFFU << FLASH_WRP2_WRP2_Pos) /*!< 0x000000FF */ 10279 #define FLASH_WRP2_WRP2 FLASH_WRP2_WRP2_Msk /*!< Flash memory write protection option bytes */ 10280 #define FLASH_WRP2_nWRP2_Pos (8U) 10281 #define FLASH_WRP2_nWRP2_Msk (0xFFU << FLASH_WRP2_nWRP2_Pos) /*!< 0x0000FF00 */ 10282 #define FLASH_WRP2_nWRP2 FLASH_WRP2_nWRP2_Msk /*!< Flash memory write protection complemented option bytes */ 10283 10284 /****************** Bit definition for FLASH_WRP3 register ******************/ 10285 #define FLASH_WRP3_WRP3_Pos (16U) 10286 #define FLASH_WRP3_WRP3_Msk (0xFFU << FLASH_WRP3_WRP3_Pos) /*!< 0x00FF0000 */ 10287 #define FLASH_WRP3_WRP3 FLASH_WRP3_WRP3_Msk /*!< Flash memory write protection option bytes */ 10288 #define FLASH_WRP3_nWRP3_Pos (24U) 10289 #define FLASH_WRP3_nWRP3_Msk (0xFFU << FLASH_WRP3_nWRP3_Pos) /*!< 0xFF000000 */ 10290 #define FLASH_WRP3_nWRP3 FLASH_WRP3_nWRP3_Msk /*!< Flash memory write protection complemented option bytes */ 10291 10292 10293 10294 /** 10295 * @} 10296 */ 10297 10298 /** 10299 * @} 10300 */ 10301 10302 /** @addtogroup Exported_macro 10303 * @{ 10304 */ 10305 10306 /****************************** ADC Instances *********************************/ 10307 #define IS_ADC_ALL_INSTANCE(INSTANCE) (((INSTANCE) == ADC1) || \ 10308 ((INSTANCE) == ADC2)) 10309 10310 #define IS_ADC_COMMON_INSTANCE(INSTANCE) ((INSTANCE) == ADC12_COMMON) 10311 10312 #define IS_ADC_MULTIMODE_MASTER_INSTANCE(INSTANCE) ((INSTANCE) == ADC1) 10313 10314 #define IS_ADC_DMA_CAPABILITY_INSTANCE(INSTANCE) ((INSTANCE) == ADC1) 10315 10316 /****************************** CAN Instances *********************************/ 10317 #define IS_CAN_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CAN1) 10318 10319 /****************************** CRC Instances *********************************/ 10320 #define IS_CRC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CRC) 10321 10322 /****************************** DAC Instances *********************************/ 10323 10324 /****************************** DMA Instances *********************************/ 10325 #define IS_DMA_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMA1_Channel1) || \ 10326 ((INSTANCE) == DMA1_Channel2) || \ 10327 ((INSTANCE) == DMA1_Channel3) || \ 10328 ((INSTANCE) == DMA1_Channel4) || \ 10329 ((INSTANCE) == DMA1_Channel5) || \ 10330 ((INSTANCE) == DMA1_Channel6) || \ 10331 ((INSTANCE) == DMA1_Channel7)) 10332 10333 /******************************* GPIO Instances *******************************/ 10334 #define IS_GPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \ 10335 ((INSTANCE) == GPIOB) || \ 10336 ((INSTANCE) == GPIOC) || \ 10337 ((INSTANCE) == GPIOD) || \ 10338 ((INSTANCE) == GPIOE)) 10339 10340 /**************************** GPIO Alternate Function Instances ***************/ 10341 #define IS_GPIO_AF_INSTANCE(INSTANCE) IS_GPIO_ALL_INSTANCE(INSTANCE) 10342 10343 /**************************** GPIO Lock Instances *****************************/ 10344 #define IS_GPIO_LOCK_INSTANCE(INSTANCE) IS_GPIO_ALL_INSTANCE(INSTANCE) 10345 10346 /******************************** I2C Instances *******************************/ 10347 #define IS_I2C_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) || \ 10348 ((INSTANCE) == I2C2)) 10349 10350 /****************************** IWDG Instances ********************************/ 10351 #define IS_IWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == IWDG) 10352 10353 /******************************** SPI Instances *******************************/ 10354 #define IS_SPI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) || \ 10355 ((INSTANCE) == SPI2)) 10356 10357 /****************************** START TIM Instances ***************************/ 10358 /****************************** TIM Instances *********************************/ 10359 #define IS_TIM_INSTANCE(INSTANCE)\ 10360 (((INSTANCE) == TIM1) || \ 10361 ((INSTANCE) == TIM2) || \ 10362 ((INSTANCE) == TIM3) || \ 10363 ((INSTANCE) == TIM4)) 10364 10365 #define IS_TIM_CC1_INSTANCE(INSTANCE)\ 10366 (((INSTANCE) == TIM1) || \ 10367 ((INSTANCE) == TIM2) || \ 10368 ((INSTANCE) == TIM3) || \ 10369 ((INSTANCE) == TIM4)) 10370 10371 #define IS_TIM_CC2_INSTANCE(INSTANCE)\ 10372 (((INSTANCE) == TIM1) || \ 10373 ((INSTANCE) == TIM2) || \ 10374 ((INSTANCE) == TIM3) || \ 10375 ((INSTANCE) == TIM4)) 10376 10377 #define IS_TIM_CC3_INSTANCE(INSTANCE)\ 10378 (((INSTANCE) == TIM1) || \ 10379 ((INSTANCE) == TIM2) || \ 10380 ((INSTANCE) == TIM3) || \ 10381 ((INSTANCE) == TIM4)) 10382 10383 #define IS_TIM_CC4_INSTANCE(INSTANCE)\ 10384 (((INSTANCE) == TIM1) || \ 10385 ((INSTANCE) == TIM2) || \ 10386 ((INSTANCE) == TIM3) || \ 10387 ((INSTANCE) == TIM4)) 10388 10389 #define IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(INSTANCE)\ 10390 (((INSTANCE) == TIM1) || \ 10391 ((INSTANCE) == TIM2) || \ 10392 ((INSTANCE) == TIM3) || \ 10393 ((INSTANCE) == TIM4)) 10394 10395 #define IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(INSTANCE)\ 10396 (((INSTANCE) == TIM1) || \ 10397 ((INSTANCE) == TIM2) || \ 10398 ((INSTANCE) == TIM3) || \ 10399 ((INSTANCE) == TIM4)) 10400 10401 #define IS_TIM_CLOCKSOURCE_TIX_INSTANCE(INSTANCE)\ 10402 (((INSTANCE) == TIM1) || \ 10403 ((INSTANCE) == TIM2) || \ 10404 ((INSTANCE) == TIM3) || \ 10405 ((INSTANCE) == TIM4)) 10406 10407 #define IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(INSTANCE)\ 10408 (((INSTANCE) == TIM1) || \ 10409 ((INSTANCE) == TIM2) || \ 10410 ((INSTANCE) == TIM3) || \ 10411 ((INSTANCE) == TIM4)) 10412 10413 #define IS_TIM_OCXREF_CLEAR_INSTANCE(INSTANCE)\ 10414 (((INSTANCE) == TIM1) || \ 10415 ((INSTANCE) == TIM2) || \ 10416 ((INSTANCE) == TIM3) || \ 10417 ((INSTANCE) == TIM4)) 10418 10419 #define IS_TIM_ENCODER_INTERFACE_INSTANCE(INSTANCE)\ 10420 (((INSTANCE) == TIM1) || \ 10421 ((INSTANCE) == TIM2) || \ 10422 ((INSTANCE) == TIM3) || \ 10423 ((INSTANCE) == TIM4)) 10424 10425 #define IS_TIM_XOR_INSTANCE(INSTANCE)\ 10426 (((INSTANCE) == TIM1) || \ 10427 ((INSTANCE) == TIM2) || \ 10428 ((INSTANCE) == TIM3) || \ 10429 ((INSTANCE) == TIM4)) 10430 10431 #define IS_TIM_MASTER_INSTANCE(INSTANCE)\ 10432 (((INSTANCE) == TIM1) || \ 10433 ((INSTANCE) == TIM2) || \ 10434 ((INSTANCE) == TIM3) || \ 10435 ((INSTANCE) == TIM4)) 10436 10437 #define IS_TIM_SLAVE_INSTANCE(INSTANCE)\ 10438 (((INSTANCE) == TIM1) || \ 10439 ((INSTANCE) == TIM2) || \ 10440 ((INSTANCE) == TIM3) || \ 10441 ((INSTANCE) == TIM4)) 10442 10443 #define IS_TIM_DMABURST_INSTANCE(INSTANCE)\ 10444 (((INSTANCE) == TIM1) || \ 10445 ((INSTANCE) == TIM2) || \ 10446 ((INSTANCE) == TIM3) || \ 10447 ((INSTANCE) == TIM4)) 10448 10449 #define IS_TIM_BREAK_INSTANCE(INSTANCE)\ 10450 ((INSTANCE) == TIM1) 10451 10452 #define IS_TIM_CCX_INSTANCE(INSTANCE, CHANNEL) \ 10453 ((((INSTANCE) == TIM1) && \ 10454 (((CHANNEL) == TIM_CHANNEL_1) || \ 10455 ((CHANNEL) == TIM_CHANNEL_2) || \ 10456 ((CHANNEL) == TIM_CHANNEL_3) || \ 10457 ((CHANNEL) == TIM_CHANNEL_4))) \ 10458 || \ 10459 (((INSTANCE) == TIM2) && \ 10460 (((CHANNEL) == TIM_CHANNEL_1) || \ 10461 ((CHANNEL) == TIM_CHANNEL_2) || \ 10462 ((CHANNEL) == TIM_CHANNEL_3) || \ 10463 ((CHANNEL) == TIM_CHANNEL_4))) \ 10464 || \ 10465 (((INSTANCE) == TIM3) && \ 10466 (((CHANNEL) == TIM_CHANNEL_1) || \ 10467 ((CHANNEL) == TIM_CHANNEL_2) || \ 10468 ((CHANNEL) == TIM_CHANNEL_3) || \ 10469 ((CHANNEL) == TIM_CHANNEL_4))) \ 10470 || \ 10471 (((INSTANCE) == TIM4) && \ 10472 (((CHANNEL) == TIM_CHANNEL_1) || \ 10473 ((CHANNEL) == TIM_CHANNEL_2) || \ 10474 ((CHANNEL) == TIM_CHANNEL_3) || \ 10475 ((CHANNEL) == TIM_CHANNEL_4)))) 10476 10477 #define IS_TIM_CCXN_INSTANCE(INSTANCE, CHANNEL) \ 10478 (((INSTANCE) == TIM1) && \ 10479 (((CHANNEL) == TIM_CHANNEL_1) || \ 10480 ((CHANNEL) == TIM_CHANNEL_2) || \ 10481 ((CHANNEL) == TIM_CHANNEL_3))) 10482 10483 #define IS_TIM_COUNTER_MODE_SELECT_INSTANCE(INSTANCE)\ 10484 (((INSTANCE) == TIM1) || \ 10485 ((INSTANCE) == TIM2) || \ 10486 ((INSTANCE) == TIM3) || \ 10487 ((INSTANCE) == TIM4)) 10488 10489 #define IS_TIM_REPETITION_COUNTER_INSTANCE(INSTANCE)\ 10490 ((INSTANCE) == TIM1) 10491 10492 #define IS_TIM_CLOCK_DIVISION_INSTANCE(INSTANCE)\ 10493 (((INSTANCE) == TIM1) || \ 10494 ((INSTANCE) == TIM2) || \ 10495 ((INSTANCE) == TIM3) || \ 10496 ((INSTANCE) == TIM4)) 10497 10498 #define IS_TIM_DMA_INSTANCE(INSTANCE)\ 10499 (((INSTANCE) == TIM1) || \ 10500 ((INSTANCE) == TIM2) || \ 10501 ((INSTANCE) == TIM3) || \ 10502 ((INSTANCE) == TIM4)) 10503 10504 #define IS_TIM_DMA_CC_INSTANCE(INSTANCE)\ 10505 (((INSTANCE) == TIM1) || \ 10506 ((INSTANCE) == TIM2) || \ 10507 ((INSTANCE) == TIM3) || \ 10508 ((INSTANCE) == TIM4)) 10509 10510 #define IS_TIM_COMMUTATION_EVENT_INSTANCE(INSTANCE)\ 10511 ((INSTANCE) == TIM1) 10512 10513 /****************************** END TIM Instances *****************************/ 10514 10515 10516 /******************** USART Instances : Synchronous mode **********************/ 10517 #define IS_USART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \ 10518 ((INSTANCE) == USART2) || \ 10519 ((INSTANCE) == USART3)) 10520 10521 /******************** UART Instances : Asynchronous mode **********************/ 10522 #define IS_UART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \ 10523 ((INSTANCE) == USART2) || \ 10524 ((INSTANCE) == USART3)) 10525 10526 /******************** UART Instances : Half-Duplex mode **********************/ 10527 #define IS_UART_HALFDUPLEX_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \ 10528 ((INSTANCE) == USART2) || \ 10529 ((INSTANCE) == USART3)) 10530 10531 /******************** UART Instances : LIN mode **********************/ 10532 #define IS_UART_LIN_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \ 10533 ((INSTANCE) == USART2) || \ 10534 ((INSTANCE) == USART3)) 10535 10536 /****************** UART Instances : Hardware Flow control ********************/ 10537 #define IS_UART_HWFLOW_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \ 10538 ((INSTANCE) == USART2) || \ 10539 ((INSTANCE) == USART3)) 10540 10541 /********************* UART Instances : Smard card mode ***********************/ 10542 #define IS_SMARTCARD_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \ 10543 ((INSTANCE) == USART2) || \ 10544 ((INSTANCE) == USART3)) 10545 10546 /*********************** UART Instances : IRDA mode ***************************/ 10547 #define IS_IRDA_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \ 10548 ((INSTANCE) == USART2) || \ 10549 ((INSTANCE) == USART3)) 10550 10551 /***************** UART Instances : Multi-Processor mode **********************/ 10552 #define IS_UART_MULTIPROCESSOR_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \ 10553 ((INSTANCE) == USART2) || \ 10554 ((INSTANCE) == USART3)) 10555 10556 /***************** UART Instances : DMA mode available **********************/ 10557 #define IS_UART_DMA_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \ 10558 ((INSTANCE) == USART2) || \ 10559 ((INSTANCE) == USART3)) 10560 10561 /****************************** RTC Instances *********************************/ 10562 #define IS_RTC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == RTC) 10563 10564 /**************************** WWDG Instances *****************************/ 10565 #define IS_WWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == WWDG) 10566 10567 /****************************** USB Instances ********************************/ 10568 #define IS_USB_ALL_INSTANCE(INSTANCE) ((INSTANCE) == USB) 10569 10570 10571 10572 10573 /** 10574 * @} 10575 */ 10576 /******************************************************************************/ 10577 /* For a painless codes migration between the STM32F1xx device product */ 10578 /* lines, the aliases defined below are put in place to overcome the */ 10579 /* differences in the interrupt handlers and IRQn definitions. */ 10580 /* No need to update developed interrupt code when moving across */ 10581 /* product lines within the same STM32F1 Family */ 10582 /******************************************************************************/ 10583 10584 /* Aliases for __IRQn */ 10585 #define ADC1_IRQn ADC1_2_IRQn 10586 #define TIM1_BRK_TIM15_IRQn TIM1_BRK_IRQn 10587 #define TIM1_BRK_TIM9_IRQn TIM1_BRK_IRQn 10588 #define TIM9_IRQn TIM1_BRK_IRQn 10589 #define TIM1_TRG_COM_TIM11_IRQn TIM1_TRG_COM_IRQn 10590 #define TIM1_TRG_COM_TIM17_IRQn TIM1_TRG_COM_IRQn 10591 #define TIM11_IRQn TIM1_TRG_COM_IRQn 10592 #define TIM10_IRQn TIM1_UP_IRQn 10593 #define TIM1_UP_TIM16_IRQn TIM1_UP_IRQn 10594 #define TIM1_UP_TIM10_IRQn TIM1_UP_IRQn 10595 #define CEC_IRQn USBWakeUp_IRQn 10596 #define OTG_FS_WKUP_IRQn USBWakeUp_IRQn 10597 #define CAN1_TX_IRQn USB_HP_CAN1_TX_IRQn 10598 #define USB_HP_IRQn USB_HP_CAN1_TX_IRQn 10599 #define USB_LP_IRQn USB_LP_CAN1_RX0_IRQn 10600 #define CAN1_RX0_IRQn USB_LP_CAN1_RX0_IRQn 10601 10602 10603 /* Aliases for __IRQHandler */ 10604 #define ADC1_IRQHandler ADC1_2_IRQHandler 10605 #define TIM1_BRK_TIM15_IRQHandler TIM1_BRK_IRQHandler 10606 #define TIM1_BRK_TIM9_IRQHandler TIM1_BRK_IRQHandler 10607 #define TIM9_IRQHandler TIM1_BRK_IRQHandler 10608 #define TIM1_TRG_COM_TIM11_IRQHandler TIM1_TRG_COM_IRQHandler 10609 #define TIM1_TRG_COM_TIM17_IRQHandler TIM1_TRG_COM_IRQHandler 10610 #define TIM11_IRQHandler TIM1_TRG_COM_IRQHandler 10611 #define TIM10_IRQHandler TIM1_UP_IRQHandler 10612 #define TIM1_UP_TIM16_IRQHandler TIM1_UP_IRQHandler 10613 #define TIM1_UP_TIM10_IRQHandler TIM1_UP_IRQHandler 10614 #define CEC_IRQHandler USBWakeUp_IRQHandler 10615 #define OTG_FS_WKUP_IRQHandler USBWakeUp_IRQHandler 10616 #define CAN1_TX_IRQHandler USB_HP_CAN1_TX_IRQHandler 10617 #define USB_HP_IRQHandler USB_HP_CAN1_TX_IRQHandler 10618 #define USB_LP_IRQHandler USB_LP_CAN1_RX0_IRQHandler 10619 #define CAN1_RX0_IRQHandler USB_LP_CAN1_RX0_IRQHandler 10620 10621 10622 /** 10623 * @} 10624 */ 10625 10626 /** 10627 * @} 10628 */ 10629 10630 10631 #ifdef __cplusplus 10632 } 10633 #endif /* __cplusplus */ 10634 10635 #endif /* __STM32F103xB_H */ 10636 10637 10638 10639 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
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