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stm32f103xb.h File Reference
Data Structures | Enumerations

stm32f103xb.h File Reference

CMSIS Cortex-M3 Device Peripheral Access Layer Header File. This file contains all the peripheral register's definitions, bits definitions and memory mapping for STM32F1xx devices. More...

Go to the source code of this file.

Data Structures

struct  ADC_TypeDef
 Analog to Digital Converter. More...
struct  BKP_TypeDef
 Backup Registers. More...
struct  CAN_TxMailBox_TypeDef
 Controller Area Network TxMailBox. More...
struct  CAN_FIFOMailBox_TypeDef
 Controller Area Network FIFOMailBox. More...
struct  CAN_FilterRegister_TypeDef
 Controller Area Network FilterRegister. More...
struct  CAN_TypeDef
 Controller Area Network. More...
struct  CRC_TypeDef
 CRC calculation unit. More...
struct  DBGMCU_TypeDef
 Debug MCU. More...
struct  DMA_Channel_TypeDef
 DMA Controller. More...
struct  EXTI_TypeDef
 External Interrupt/Event Controller. More...
struct  FLASH_TypeDef
 FLASH Registers. More...
struct  OB_TypeDef
 Option Bytes Registers. More...
struct  GPIO_TypeDef
 General Purpose I/O. More...
struct  AFIO_TypeDef
 Alternate Function I/O. More...
struct  I2C_TypeDef
 Inter Integrated Circuit Interface. More...
struct  IWDG_TypeDef
 Independent WATCHDOG. More...
struct  PWR_TypeDef
 Power Control. More...
struct  RCC_TypeDef
 Reset and Clock Control. More...
struct  RTC_TypeDef
 Real-Time Clock. More...
struct  SDIO_TypeDef
 SD host Interface. More...
struct  SPI_TypeDef
 Serial Peripheral Interface. More...
struct  TIM_TypeDef
 TIM Timers. More...
struct  USART_TypeDef
 Universal Synchronous Asynchronous Receiver Transmitter. More...
struct  USB_TypeDef
 Universal Serial Bus Full Speed Device. More...
struct  WWDG_TypeDef
 Window WATCHDOG. More...

Enumerations

enum  IRQn_Type { ,
  Reset_IRQn = -15, NonMaskableInt_IRQn = -14, HardFault_IRQn = -13, SVCall_IRQn = -5,
  DebugMonitor_IRQn = -4, PendSV_IRQn = -2, SysTick_IRQn = -1, FLEX_INT0_IRQn = 0 ,
  GINT0_IRQn = 8, GINT1_IRQn = 9, Reserved0_IRQn = 10 , SSP1_IRQn = 14,
  I2C_IRQn = 15, TIMER_16_0_IRQn = 16, TIMER_16_1_IRQn = 17, TIMER_32_0_IRQn = 18,
  TIMER_32_1_IRQn = 19, SSP0_IRQn = 20, UART_IRQn = 21, USB_IRQn = 22,
  USB_FIQn = 23, ADC_IRQn = 24, WDT_IRQn = 25, BOD_IRQn = 26,
  FMC_IRQn = 27, Reserved4_IRQn = 28, Reserved5_IRQn = 29, USBWakeup_IRQn = 30,
  Reserved6_IRQn = 31, Reset_IRQn = -15, NonMaskableInt_IRQn = -14, HardFault_IRQn = -13,
  MemoryManagement_IRQn = -12, BusFault_IRQn = -11, UsageFault_IRQn = -10, SVCall_IRQn = -5,
  DebugMonitor_IRQn = -4, PendSV_IRQn = -2, SysTick_IRQn = -1, DAC_IRQn = 0,
  M0CORE_IRQn = 1, DMA_IRQn = 2, RESERVED1_IRQn = 3 , ETHERNET_IRQn = 5,
  SDIO_IRQn = 6, LCD_IRQn = 7, USB0_IRQn = 8, USB1_IRQn = 9,
  SCT_IRQn = 10, RITIMER_IRQn = 11, TIMER0_IRQn = 12, TIMER1_IRQn = 13,
  TIMER2_IRQn = 14, TIMER3_IRQn = 15, MCPWM_IRQn = 16, ADC0_IRQn = 17,
  I2C0_IRQn = 18, I2C1_IRQn = 19, SPI_INT_IRQn = 20, ADC1_IRQn = 21,
  SSP0_IRQn = 22, SSP1_IRQn = 23, USART0_IRQn = 24, UART1_IRQn = 25,
  USART2_IRQn = 26, USART3_IRQn = 27, I2S0_IRQn = 28, I2S1_IRQn = 29 ,
  SGPIO_IINT_IRQn = 31, PIN_INT0_IRQn = 32, PIN_INT1_IRQn = 33, PIN_INT2_IRQn = 34,
  PIN_INT3_IRQn = 35, PIN_INT4_IRQn = 36, PIN_INT5_IRQn = 37, PIN_INT6_IRQn = 38,
  PIN_INT7_IRQn = 39, GINT0_IRQn = 40, GINT1_IRQn = 41, EVENTROUTER_IRQn = 42,
  C_CAN1_IRQn = 43 , VADC_IRQn = 45, ATIMER_IRQn = 46, RTC_IRQn = 47 ,
  WWDT_IRQn = 49 , C_CAN0_IRQn = 51, QEI_IRQn = 52, M0_Reset_IRQn = -15,
  M0_NonMaskableInt_IRQn = -14, M0_HardFault_IRQn = -13, M0_SVCall_IRQn = -5, M0_DebugMonitor_IRQn = -4,
  M0_PendSV_IRQn = -2, M0_SysTick_IRQn = -1, M0_RTC_IRQn = 0, M0_M4CORE_IRQn = 1,
  M0_DMA_IRQn = 2 , M0_ETHERNET_IRQn = 5, M0_SDIO_IRQn = 6, M0_LCD_IRQn = 7,
  M0_USB0_IRQn = 8, M0_USB1_IRQn = 9, M0_SCT_IRQn = 10, M0_RITIMER_OR_WWDT_IRQn = 11,
  M0_TIMER0_IRQn = 12, M0_GINT1_IRQn = 13, M0_TIMER3_IRQn = 15 , M0_MCPWM_IRQn = 16,
  M0_ADC0_IRQn = 17, M0_I2C0_OR_I2C1_IRQn = 18, M0_SGPIO_IRQn = 19, M0_SPI_OR_DAC_IRQn = 20,
  M0_ADC1_IRQn = 21, M0_SSP0_OR_SSP1_IRQn = 22, M0_EVENTROUTER_IRQn = 23, M0_USART0_IRQn = 24,
  M0_UART1_IRQn = 25, M0_USART2_OR_C_CAN1_IRQn = 26, M0_USART3_IRQn = 27, M0_I2S0_OR_I2S1_OR_QEI_IRQn = 28,
  M0_C_CAN0_IRQn = 29, NonMaskableInt_IRQn = -14, HardFault_IRQn = -13, MemoryManagement_IRQn = -12,
  BusFault_IRQn = -11, UsageFault_IRQn = -10, SVCall_IRQn = -5, DebugMonitor_IRQn = -4,
  PendSV_IRQn = -2, SysTick_IRQn = -1, WWDG_IRQn = 0, PVD_IRQn = 1,
  TAMPER_IRQn = 2, RTC_IRQn = 3, FLASH_IRQn = 4, RCC_IRQn = 5,
  EXTI0_IRQn = 6, EXTI1_IRQn = 7, EXTI2_IRQn = 8, EXTI3_IRQn = 9,
  EXTI4_IRQn = 10, DMA1_Channel1_IRQn = 11, DMA1_Channel2_IRQn = 12, DMA1_Channel3_IRQn = 13,
  DMA1_Channel4_IRQn = 14, DMA1_Channel5_IRQn = 15, DMA1_Channel6_IRQn = 16, DMA1_Channel7_IRQn = 17,
  ADC1_2_IRQn = 18, USB_HP_CAN1_TX_IRQn = 19, USB_LP_CAN1_RX0_IRQn = 20, CAN1_RX1_IRQn = 21,
  CAN1_SCE_IRQn = 22, EXTI9_5_IRQn = 23, TIM1_BRK_IRQn = 24, TIM1_UP_IRQn = 25,
  TIM1_TRG_COM_IRQn = 26, TIM1_CC_IRQn = 27, TIM2_IRQn = 28, TIM3_IRQn = 29,
  TIM4_IRQn = 30, I2C1_EV_IRQn = 31, I2C1_ER_IRQn = 32, I2C2_EV_IRQn = 33,
  I2C2_ER_IRQn = 34, SPI1_IRQn = 35, SPI2_IRQn = 36, USART1_IRQn = 37,
  USART2_IRQn = 38, USART3_IRQn = 39, EXTI15_10_IRQn = 40, RTC_Alarm_IRQn = 41,
  USBWakeUp_IRQn = 42
}
 

STM32F10x Interrupt Number Definition, according to the selected device in Library_configuration_section.

More...

Detailed Description

CMSIS Cortex-M3 Device Peripheral Access Layer Header File. This file contains all the peripheral register's definitions, bits definitions and memory mapping for STM32F1xx devices.

Author:
MCD Application Team
Version:
V4.1.0
Date:
29-April-2016 This file contains:
  • Data structures and the address mapping for all peripherals
  • Peripheral's registers declarations and bits definition
  • Macros to access peripheral.s registers hardware
Attention:

© COPYRIGHT(c) 2016 STMicroelectronics

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file stm32f103xb.h.

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