Arrow / Mbed OS DAPLink Reset

Repostiory containing DAPLink source code with Reset Pin workaround for HANI_IOT board.

Upstream: https://github.com/ARMmbed/DAPLink

source/hic_hal/freescale/kl26z/IO_Config.h@0:01f31e923fe2, 2020-04-07 (annotated)

Committer:
Pawel Zarembski
Date:
Tue Apr 07 12:55:42 2020 +0200
Revision:
0:01f31e923fe2
hani: DAPLink with reset workaround

Who changed what in which revision?

UserRevisionLine numberNew contents of line
Pawel Zarembski 0:01f31e923fe2 1 /**
Pawel Zarembski 0:01f31e923fe2 2 * @file IO_Config.h
Pawel Zarembski 0:01f31e923fe2 3 * @brief
Pawel Zarembski 0:01f31e923fe2 4 *
Pawel Zarembski 0:01f31e923fe2 5 * DAPLink Interface Firmware
Pawel Zarembski 0:01f31e923fe2 6 * Copyright (c) 2009-2016, ARM Limited, All Rights Reserved
Pawel Zarembski 0:01f31e923fe2 7 * SPDX-License-Identifier: Apache-2.0
Pawel Zarembski 0:01f31e923fe2 8 *
Pawel Zarembski 0:01f31e923fe2 9 * Licensed under the Apache License, Version 2.0 (the "License"); you may
Pawel Zarembski 0:01f31e923fe2 10 * not use this file except in compliance with the License.
Pawel Zarembski 0:01f31e923fe2 11 * You may obtain a copy of the License at
Pawel Zarembski 0:01f31e923fe2 12 *
Pawel Zarembski 0:01f31e923fe2 13 * http://www.apache.org/licenses/LICENSE-2.0
Pawel Zarembski 0:01f31e923fe2 14 *
Pawel Zarembski 0:01f31e923fe2 15 * Unless required by applicable law or agreed to in writing, software
Pawel Zarembski 0:01f31e923fe2 16 * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
Pawel Zarembski 0:01f31e923fe2 17 * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
Pawel Zarembski 0:01f31e923fe2 18 * See the License for the specific language governing permissions and
Pawel Zarembski 0:01f31e923fe2 19 * limitations under the License.
Pawel Zarembski 0:01f31e923fe2 20 */
Pawel Zarembski 0:01f31e923fe2 21
Pawel Zarembski 0:01f31e923fe2 22 // Override all defines if IO_CONFIG_OVERRIDE is defined
Pawel Zarembski 0:01f31e923fe2 23 #ifdef IO_CONFIG_OVERRIDE
Pawel Zarembski 0:01f31e923fe2 24 #include "IO_Config_Override.h"
Pawel Zarembski 0:01f31e923fe2 25 #ifndef __IO_CONFIG_H__
Pawel Zarembski 0:01f31e923fe2 26 #define __IO_CONFIG_H__
Pawel Zarembski 0:01f31e923fe2 27 #endif
Pawel Zarembski 0:01f31e923fe2 28 #endif
Pawel Zarembski 0:01f31e923fe2 29
Pawel Zarembski 0:01f31e923fe2 30 #ifndef __IO_CONFIG_H__
Pawel Zarembski 0:01f31e923fe2 31 #define __IO_CONFIG_H__
Pawel Zarembski 0:01f31e923fe2 32
Pawel Zarembski 0:01f31e923fe2 33 #include "MKL26Z4.h"
Pawel Zarembski 0:01f31e923fe2 34 #include "compiler.h"
Pawel Zarembski 0:01f31e923fe2 35 #include "daplink.h"
Pawel Zarembski 0:01f31e923fe2 36
Pawel Zarembski 0:01f31e923fe2 37 // This GPIO configuration is only valid for the KL26 HIC
Pawel Zarembski 0:01f31e923fe2 38 COMPILER_ASSERT(DAPLINK_HIC_ID == DAPLINK_HIC_ID_KL26);
Pawel Zarembski 0:01f31e923fe2 39
Pawel Zarembski 0:01f31e923fe2 40
Pawel Zarembski 0:01f31e923fe2 41 // Debug Port I/O Pins
Pawel Zarembski 0:01f31e923fe2 42
Pawel Zarembski 0:01f31e923fe2 43 // SWCLK Pin PTC5(C5)
Pawel Zarembski 0:01f31e923fe2 44 #define PIN_SWCLK_PORT PORTC
Pawel Zarembski 0:01f31e923fe2 45 #define PIN_SWCLK_GPIO PTC
Pawel Zarembski 0:01f31e923fe2 46 #define PIN_SWCLK_BIT (5)
Pawel Zarembski 0:01f31e923fe2 47 #define PIN_SWCLK (1<<PIN_SWCLK_BIT)
Pawel Zarembski 0:01f31e923fe2 48
Pawel Zarembski 0:01f31e923fe2 49 // SWDIO Pin PTC6(C6)
Pawel Zarembski 0:01f31e923fe2 50 #define PIN_SWDIO_PORT PORTC
Pawel Zarembski 0:01f31e923fe2 51 #define PIN_SWDIO_GPIO PTC
Pawel Zarembski 0:01f31e923fe2 52 #define PIN_SWDIO_BIT (6)
Pawel Zarembski 0:01f31e923fe2 53 #define PIN_SWDIO (1<<PIN_SWDIO_BIT)
Pawel Zarembski 0:01f31e923fe2 54
Pawel Zarembski 0:01f31e923fe2 55 // nRESET Pin PTC8(C8)
Pawel Zarembski 0:01f31e923fe2 56 #define PIN_nRESET_PORT PORTC
Pawel Zarembski 0:01f31e923fe2 57 #define PIN_nRESET_GPIO PTC
Pawel Zarembski 0:01f31e923fe2 58 #define PIN_nRESET_BIT (8)
Pawel Zarembski 0:01f31e923fe2 59 #define PIN_nRESET (1<<PIN_nRESET_BIT)
Pawel Zarembski 0:01f31e923fe2 60
Pawel Zarembski 0:01f31e923fe2 61 // PWR_REG_EN PTD2 - Not connected
Pawel Zarembski 0:01f31e923fe2 62 #define PIN_POWER_EN_PORT PORTD
Pawel Zarembski 0:01f31e923fe2 63 #define PIN_POWER_EN_GPIO PTD
Pawel Zarembski 0:01f31e923fe2 64 #define PIN_POWER_EN_BIT (2)
Pawel Zarembski 0:01f31e923fe2 65 #define PIN_POWER_EN (1<<PIN_POWER_EN_BIT)
Pawel Zarembski 0:01f31e923fe2 66
Pawel Zarembski 0:01f31e923fe2 67 // VTRG_FAULT_B PTD3 - Not connected
Pawel Zarembski 0:01f31e923fe2 68 #define PIN_VTRG_FAULT_B_PORT PORTD
Pawel Zarembski 0:01f31e923fe2 69 #define PIN_VTRG_FAULT_B_GPIO PTD
Pawel Zarembski 0:01f31e923fe2 70 #define PIN_VTRG_FAULT_B_BIT (7)
Pawel Zarembski 0:01f31e923fe2 71 #define PIN_VTRG_FAULT_B_EN (1<<PIN_VTRG_FAULT_B_BIT)
Pawel Zarembski 0:01f31e923fe2 72
Pawel Zarembski 0:01f31e923fe2 73 // Debug Unit LEDs
Pawel Zarembski 0:01f31e923fe2 74
Pawel Zarembski 0:01f31e923fe2 75 // HID_LED PTD4
Pawel Zarembski 0:01f31e923fe2 76 #define PIN_HID_LED_PORT PORTD
Pawel Zarembski 0:01f31e923fe2 77 #define PIN_HID_LED_GPIO PTD
Pawel Zarembski 0:01f31e923fe2 78 #define PIN_HID_LED_BIT (4)
Pawel Zarembski 0:01f31e923fe2 79 #define PIN_HID_LED (1<<PIN_HID_LED_BIT)
Pawel Zarembski 0:01f31e923fe2 80
Pawel Zarembski 0:01f31e923fe2 81 // MSC_LED PTD5
Pawel Zarembski 0:01f31e923fe2 82 #define PIN_MSC_LED_PORT PORTD
Pawel Zarembski 0:01f31e923fe2 83 #define PIN_MSC_LED_GPIO PTD
Pawel Zarembski 0:01f31e923fe2 84 #define PIN_MSC_LED_BIT (4)
Pawel Zarembski 0:01f31e923fe2 85 #define PIN_MSC_LED (1<<PIN_MSC_LED_BIT)
Pawel Zarembski 0:01f31e923fe2 86
Pawel Zarembski 0:01f31e923fe2 87 // CDC_LED PTD6
Pawel Zarembski 0:01f31e923fe2 88 #define PIN_CDC_LED_PORT PORTD
Pawel Zarembski 0:01f31e923fe2 89 #define PIN_CDC_LED_GPIO PTD
Pawel Zarembski 0:01f31e923fe2 90 #define PIN_CDC_LED_BIT (4)
Pawel Zarembski 0:01f31e923fe2 91 #define PIN_CDC_LED (1<<PIN_CDC_LED_BIT)
Pawel Zarembski 0:01f31e923fe2 92
Pawel Zarembski 0:01f31e923fe2 93 // SW RESET BUTTON PTB1
Pawel Zarembski 0:01f31e923fe2 94 #define PIN_SW_RESET_PORT PORTB
Pawel Zarembski 0:01f31e923fe2 95 #define PIN_SW_RESET_GPIO PTB
Pawel Zarembski 0:01f31e923fe2 96 #define PIN_SW_RESET_BIT (1)
Pawel Zarembski 0:01f31e923fe2 97 #define PIN_SW_RESET (1<<PIN_SW_RESET_BIT)
Pawel Zarembski 0:01f31e923fe2 98
Pawel Zarembski 0:01f31e923fe2 99 // BOARD TYPE
Pawel Zarembski 0:01f31e923fe2 100 #define PIN_BOARD_TYPE_PORT PORTB
Pawel Zarembski 0:01f31e923fe2 101 #define PIN_BOARD_TYPE_GPIO PTB
Pawel Zarembski 0:01f31e923fe2 102 #define PIN_BOARD_TYPE_BIT (0)
Pawel Zarembski 0:01f31e923fe2 103 #define PIN_BOARD_TYPE (1<<PIN_BOARD_TYPE_BIT)
Pawel Zarembski 0:01f31e923fe2 104
Pawel Zarembski 0:01f31e923fe2 105 // Connected LED Not available
Pawel Zarembski 0:01f31e923fe2 106
Pawel Zarembski 0:01f31e923fe2 107 // Target Running LED Not available
Pawel Zarembski 0:01f31e923fe2 108
Pawel Zarembski 0:01f31e923fe2 109 // UART
Pawel Zarembski 0:01f31e923fe2 110 #define UART_PORT PORTC
Pawel Zarembski 0:01f31e923fe2 111 #define UART_NUM (1)
Pawel Zarembski 0:01f31e923fe2 112 // RX PTC3
Pawel Zarembski 0:01f31e923fe2 113 #define PIN_UART_RX_GPIO PTC
Pawel Zarembski 0:01f31e923fe2 114 #define PIN_UART_RX_BIT (3)
Pawel Zarembski 0:01f31e923fe2 115 #define PIN_UART_RX (1<<PIN_UART_RX_BIT)
Pawel Zarembski 0:01f31e923fe2 116 #define PIN_UART_RX_MUX_ALT (3)
Pawel Zarembski 0:01f31e923fe2 117 // TX PTC4
Pawel Zarembski 0:01f31e923fe2 118 #define PIN_UART_TX_GPIO PTC
Pawel Zarembski 0:01f31e923fe2 119 #define PIN_UART_TX_BIT (4)
Pawel Zarembski 0:01f31e923fe2 120 #define PIN_UART_TX (1<<PIN_UART_TX_BIT)
Pawel Zarembski 0:01f31e923fe2 121 #define PIN_UART_TX_MUX_ALT (3)
Pawel Zarembski 0:01f31e923fe2 122
Pawel Zarembski 0:01f31e923fe2 123 #define UART UART1
Pawel Zarembski 0:01f31e923fe2 124 #define UART_RX_TX_IRQn UART1_IRQn
Pawel Zarembski 0:01f31e923fe2 125 #define UART_RX_TX_IRQHandler UART1_IRQHandler
Pawel Zarembski 0:01f31e923fe2 126
Pawel Zarembski 0:01f31e923fe2 127 #endif