Arrow / Mbed OS DAPLink Reset

Repostiory containing DAPLink source code with Reset Pin workaround for HANI_IOT board.

Upstream: https://github.com/ARMmbed/DAPLink

source/hic_hal/atmel/sam3u2c/instance/usart3.h@0:01f31e923fe2, 2020-04-07 (annotated)

Committer:
Pawel Zarembski
Date:
Tue Apr 07 12:55:42 2020 +0200
Revision:
0:01f31e923fe2
hani: DAPLink with reset workaround

Who changed what in which revision?

UserRevisionLine numberNew contents of line
Pawel Zarembski 0:01f31e923fe2 1 /* ---------------------------------------------------------------------------- */
Pawel Zarembski 0:01f31e923fe2 2 /* Atmel Microcontroller Software Support */
Pawel Zarembski 0:01f31e923fe2 3 /* SAM Software Package License */
Pawel Zarembski 0:01f31e923fe2 4 /* ---------------------------------------------------------------------------- */
Pawel Zarembski 0:01f31e923fe2 5 /* Copyright (c) %copyright_year%, Atmel Corporation */
Pawel Zarembski 0:01f31e923fe2 6 /* */
Pawel Zarembski 0:01f31e923fe2 7 /* All rights reserved. */
Pawel Zarembski 0:01f31e923fe2 8 /* */
Pawel Zarembski 0:01f31e923fe2 9 /* Redistribution and use in source and binary forms, with or without */
Pawel Zarembski 0:01f31e923fe2 10 /* modification, are permitted provided that the following condition is met: */
Pawel Zarembski 0:01f31e923fe2 11 /* */
Pawel Zarembski 0:01f31e923fe2 12 /* - Redistributions of source code must retain the above copyright notice, */
Pawel Zarembski 0:01f31e923fe2 13 /* this list of conditions and the disclaimer below. */
Pawel Zarembski 0:01f31e923fe2 14 /* */
Pawel Zarembski 0:01f31e923fe2 15 /* Atmel's name may not be used to endorse or promote products derived from */
Pawel Zarembski 0:01f31e923fe2 16 /* this software without specific prior written permission. */
Pawel Zarembski 0:01f31e923fe2 17 /* */
Pawel Zarembski 0:01f31e923fe2 18 /* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */
Pawel Zarembski 0:01f31e923fe2 19 /* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */
Pawel Zarembski 0:01f31e923fe2 20 /* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */
Pawel Zarembski 0:01f31e923fe2 21 /* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */
Pawel Zarembski 0:01f31e923fe2 22 /* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */
Pawel Zarembski 0:01f31e923fe2 23 /* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */
Pawel Zarembski 0:01f31e923fe2 24 /* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */
Pawel Zarembski 0:01f31e923fe2 25 /* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */
Pawel Zarembski 0:01f31e923fe2 26 /* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */
Pawel Zarembski 0:01f31e923fe2 27 /* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */
Pawel Zarembski 0:01f31e923fe2 28 /* ---------------------------------------------------------------------------- */
Pawel Zarembski 0:01f31e923fe2 29
Pawel Zarembski 0:01f31e923fe2 30 #ifndef _SAM3U_USART3_INSTANCE_
Pawel Zarembski 0:01f31e923fe2 31 #define _SAM3U_USART3_INSTANCE_
Pawel Zarembski 0:01f31e923fe2 32
Pawel Zarembski 0:01f31e923fe2 33 /* ========== Register definition for USART3 peripheral ========== */
Pawel Zarembski 0:01f31e923fe2 34 #if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
Pawel Zarembski 0:01f31e923fe2 35 #define REG_USART3_CR (0x4009C000U) /**< \brief (USART3) Control Register */
Pawel Zarembski 0:01f31e923fe2 36 #define REG_USART3_MR (0x4009C004U) /**< \brief (USART3) Mode Register */
Pawel Zarembski 0:01f31e923fe2 37 #define REG_USART3_IER (0x4009C008U) /**< \brief (USART3) Interrupt Enable Register */
Pawel Zarembski 0:01f31e923fe2 38 #define REG_USART3_IDR (0x4009C00CU) /**< \brief (USART3) Interrupt Disable Register */
Pawel Zarembski 0:01f31e923fe2 39 #define REG_USART3_IMR (0x4009C010U) /**< \brief (USART3) Interrupt Mask Register */
Pawel Zarembski 0:01f31e923fe2 40 #define REG_USART3_CSR (0x4009C014U) /**< \brief (USART3) Channel Status Register */
Pawel Zarembski 0:01f31e923fe2 41 #define REG_USART3_RHR (0x4009C018U) /**< \brief (USART3) Receiver Holding Register */
Pawel Zarembski 0:01f31e923fe2 42 #define REG_USART3_THR (0x4009C01CU) /**< \brief (USART3) Transmitter Holding Register */
Pawel Zarembski 0:01f31e923fe2 43 #define REG_USART3_BRGR (0x4009C020U) /**< \brief (USART3) Baud Rate Generator Register */
Pawel Zarembski 0:01f31e923fe2 44 #define REG_USART3_RTOR (0x4009C024U) /**< \brief (USART3) Receiver Time-out Register */
Pawel Zarembski 0:01f31e923fe2 45 #define REG_USART3_TTGR (0x4009C028U) /**< \brief (USART3) Transmitter Timeguard Register */
Pawel Zarembski 0:01f31e923fe2 46 #define REG_USART3_FIDI (0x4009C040U) /**< \brief (USART3) FI DI Ratio Register */
Pawel Zarembski 0:01f31e923fe2 47 #define REG_USART3_NER (0x4009C044U) /**< \brief (USART3) Number of Errors Register */
Pawel Zarembski 0:01f31e923fe2 48 #define REG_USART3_IF (0x4009C04CU) /**< \brief (USART3) IrDA Filter Register */
Pawel Zarembski 0:01f31e923fe2 49 #define REG_USART3_MAN (0x4009C050U) /**< \brief (USART3) Manchester Encoder Decoder Register */
Pawel Zarembski 0:01f31e923fe2 50 #define REG_USART3_WPMR (0x4009C0E4U) /**< \brief (USART3) Write Protect Mode Register */
Pawel Zarembski 0:01f31e923fe2 51 #define REG_USART3_WPSR (0x4009C0E8U) /**< \brief (USART3) Write Protect Status Register */
Pawel Zarembski 0:01f31e923fe2 52 #define REG_USART3_RPR (0x4009C100U) /**< \brief (USART3) Receive Pointer Register */
Pawel Zarembski 0:01f31e923fe2 53 #define REG_USART3_RCR (0x4009C104U) /**< \brief (USART3) Receive Counter Register */
Pawel Zarembski 0:01f31e923fe2 54 #define REG_USART3_TPR (0x4009C108U) /**< \brief (USART3) Transmit Pointer Register */
Pawel Zarembski 0:01f31e923fe2 55 #define REG_USART3_TCR (0x4009C10CU) /**< \brief (USART3) Transmit Counter Register */
Pawel Zarembski 0:01f31e923fe2 56 #define REG_USART3_RNPR (0x4009C110U) /**< \brief (USART3) Receive Next Pointer Register */
Pawel Zarembski 0:01f31e923fe2 57 #define REG_USART3_RNCR (0x4009C114U) /**< \brief (USART3) Receive Next Counter Register */
Pawel Zarembski 0:01f31e923fe2 58 #define REG_USART3_TNPR (0x4009C118U) /**< \brief (USART3) Transmit Next Pointer Register */
Pawel Zarembski 0:01f31e923fe2 59 #define REG_USART3_TNCR (0x4009C11CU) /**< \brief (USART3) Transmit Next Counter Register */
Pawel Zarembski 0:01f31e923fe2 60 #define REG_USART3_PTCR (0x4009C120U) /**< \brief (USART3) Transfer Control Register */
Pawel Zarembski 0:01f31e923fe2 61 #define REG_USART3_PTSR (0x4009C124U) /**< \brief (USART3) Transfer Status Register */
Pawel Zarembski 0:01f31e923fe2 62 #else
Pawel Zarembski 0:01f31e923fe2 63 #define REG_USART3_CR (*(WoReg*)0x4009C000U) /**< \brief (USART3) Control Register */
Pawel Zarembski 0:01f31e923fe2 64 #define REG_USART3_MR (*(RwReg*)0x4009C004U) /**< \brief (USART3) Mode Register */
Pawel Zarembski 0:01f31e923fe2 65 #define REG_USART3_IER (*(WoReg*)0x4009C008U) /**< \brief (USART3) Interrupt Enable Register */
Pawel Zarembski 0:01f31e923fe2 66 #define REG_USART3_IDR (*(WoReg*)0x4009C00CU) /**< \brief (USART3) Interrupt Disable Register */
Pawel Zarembski 0:01f31e923fe2 67 #define REG_USART3_IMR (*(RoReg*)0x4009C010U) /**< \brief (USART3) Interrupt Mask Register */
Pawel Zarembski 0:01f31e923fe2 68 #define REG_USART3_CSR (*(RoReg*)0x4009C014U) /**< \brief (USART3) Channel Status Register */
Pawel Zarembski 0:01f31e923fe2 69 #define REG_USART3_RHR (*(RoReg*)0x4009C018U) /**< \brief (USART3) Receiver Holding Register */
Pawel Zarembski 0:01f31e923fe2 70 #define REG_USART3_THR (*(WoReg*)0x4009C01CU) /**< \brief (USART3) Transmitter Holding Register */
Pawel Zarembski 0:01f31e923fe2 71 #define REG_USART3_BRGR (*(RwReg*)0x4009C020U) /**< \brief (USART3) Baud Rate Generator Register */
Pawel Zarembski 0:01f31e923fe2 72 #define REG_USART3_RTOR (*(RwReg*)0x4009C024U) /**< \brief (USART3) Receiver Time-out Register */
Pawel Zarembski 0:01f31e923fe2 73 #define REG_USART3_TTGR (*(RwReg*)0x4009C028U) /**< \brief (USART3) Transmitter Timeguard Register */
Pawel Zarembski 0:01f31e923fe2 74 #define REG_USART3_FIDI (*(RwReg*)0x4009C040U) /**< \brief (USART3) FI DI Ratio Register */
Pawel Zarembski 0:01f31e923fe2 75 #define REG_USART3_NER (*(RoReg*)0x4009C044U) /**< \brief (USART3) Number of Errors Register */
Pawel Zarembski 0:01f31e923fe2 76 #define REG_USART3_IF (*(RwReg*)0x4009C04CU) /**< \brief (USART3) IrDA Filter Register */
Pawel Zarembski 0:01f31e923fe2 77 #define REG_USART3_MAN (*(RwReg*)0x4009C050U) /**< \brief (USART3) Manchester Encoder Decoder Register */
Pawel Zarembski 0:01f31e923fe2 78 #define REG_USART3_WPMR (*(RwReg*)0x4009C0E4U) /**< \brief (USART3) Write Protect Mode Register */
Pawel Zarembski 0:01f31e923fe2 79 #define REG_USART3_WPSR (*(RoReg*)0x4009C0E8U) /**< \brief (USART3) Write Protect Status Register */
Pawel Zarembski 0:01f31e923fe2 80 #define REG_USART3_RPR (*(RwReg*)0x4009C100U) /**< \brief (USART3) Receive Pointer Register */
Pawel Zarembski 0:01f31e923fe2 81 #define REG_USART3_RCR (*(RwReg*)0x4009C104U) /**< \brief (USART3) Receive Counter Register */
Pawel Zarembski 0:01f31e923fe2 82 #define REG_USART3_TPR (*(RwReg*)0x4009C108U) /**< \brief (USART3) Transmit Pointer Register */
Pawel Zarembski 0:01f31e923fe2 83 #define REG_USART3_TCR (*(RwReg*)0x4009C10CU) /**< \brief (USART3) Transmit Counter Register */
Pawel Zarembski 0:01f31e923fe2 84 #define REG_USART3_RNPR (*(RwReg*)0x4009C110U) /**< \brief (USART3) Receive Next Pointer Register */
Pawel Zarembski 0:01f31e923fe2 85 #define REG_USART3_RNCR (*(RwReg*)0x4009C114U) /**< \brief (USART3) Receive Next Counter Register */
Pawel Zarembski 0:01f31e923fe2 86 #define REG_USART3_TNPR (*(RwReg*)0x4009C118U) /**< \brief (USART3) Transmit Next Pointer Register */
Pawel Zarembski 0:01f31e923fe2 87 #define REG_USART3_TNCR (*(RwReg*)0x4009C11CU) /**< \brief (USART3) Transmit Next Counter Register */
Pawel Zarembski 0:01f31e923fe2 88 #define REG_USART3_PTCR (*(WoReg*)0x4009C120U) /**< \brief (USART3) Transfer Control Register */
Pawel Zarembski 0:01f31e923fe2 89 #define REG_USART3_PTSR (*(RoReg*)0x4009C124U) /**< \brief (USART3) Transfer Status Register */
Pawel Zarembski 0:01f31e923fe2 90 #endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
Pawel Zarembski 0:01f31e923fe2 91
Pawel Zarembski 0:01f31e923fe2 92 #endif /* _SAM3U_USART3_INSTANCE_ */