Diff: source/hic_hal/nuvoton/m48ssidae/sdk.c

Revision:

0:01f31e923fe2

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/source/hic_hal/nuvoton/m48ssidae/sdk.c	Tue Apr 07 12:55:42 2020 +0200
@@ -0,0 +1,68 @@
+/**
+ * @file    sdk.c
+ * @brief
+ *
+ * DAPLink Interface Firmware
+ * Copyright (c) 2017-2017, ARM Limited, All Rights Reserved
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "NuMicro.h"
+#include "DAP_config.h"
+#include "gpio.h"
+#include "daplink.h"
+#include "util.h"
+#include "cortex_m.h"
+
+void sdk_init()
+{
+    uint32_t volatile i;
+    /* Unlock protected registers */
+    SYS_UnlockReg();
+    /* Set XT1_OUT(PF.2) and XT1_IN(PF.3) to input mode */
+    PF->MODE &= ~(GPIO_MODE_MODE2_Msk | GPIO_MODE_MODE3_Msk);
+    /* Enable External XTAL (4~24 MHz) */
+    CLK_EnableXtalRC(CLK_PWRCTL_HXTEN_Msk);
+    /* Waiting for 12MHz clock ready */
+    CLK_WaitClockReady(CLK_STATUS_HXTSTB_Msk);
+    /* Switch HCLK clock source to HXT */
+    CLK_SetHCLK(CLK_CLKSEL0_HCLKSEL_HXT, CLK_CLKDIV0_HCLK(1));
+    /* Set core clock as PLL_CLOCK from PLL */
+    CLK_SetCoreClock(FREQ_192MHZ);
+    /* Set PCLK0/PCLK1 to HCLK/2 */
+    CLK->PCLKDIV = (CLK_PCLKDIV_PCLK0DIV2 | CLK_PCLKDIV_PCLK1DIV2);
+    /* Select HSUSBD */
+    SYS->USBPHY &= ~SYS_USBPHY_HSUSBROLE_Msk;
+    /* Enable USB PHY */
+    SYS->USBPHY = (SYS->USBPHY & ~(SYS_USBPHY_HSUSBROLE_Msk | SYS_USBPHY_HSUSBACT_Msk)) | SYS_USBPHY_HSUSBEN_Msk;
+
+    for (i = 0; i < 0x1000; i++); // delay > 10 us
+
+    SYS->USBPHY |= SYS_USBPHY_HSUSBACT_Msk;
+    /* Enable HSUSBD clock */
+    CLK_EnableModuleClock(HSUSBD_MODULE);
+    /* Select UART clock source */
+    CLK_SetModuleClock(UART0_MODULE, CLK_CLKSEL1_UART0SEL_HXT, CLK_CLKDIV0_UART0(1));
+    /* Enable UART clock */
+    CLK_EnableModuleClock(UART0_MODULE);
+    /* Set GPA multi-function pins for UART0 RXD and TXD */
+    SYS->GPA_MFPL &= ~(SYS_GPA_MFPL_PA0MFP_Msk | SYS_GPA_MFPL_PA1MFP_Msk);
+    SYS->GPA_MFPL |= (SYS_GPA_MFPL_PA0MFP_UART0_RXD | SYS_GPA_MFPL_PA1MFP_UART0_TXD);
+    /* Update System Core Clock */
+    /* User can use SystemCoreClockUpdate() to calculate SystemCoreClock. */
+    SystemCoreClockUpdate();
+    /* Lock protected registers */
+    SYS_LockReg();
+}