Arrow / Mbed OS DAPLink Reset

Repostiory containing DAPLink source code with Reset Pin workaround for HANI_IOT board.

Upstream: https://github.com/ARMmbed/DAPLink

source/hic_hal/nuvoton/m48ssidae/sdk.c@0:01f31e923fe2, 2020-04-07 (annotated)

Committer:
Pawel Zarembski
Date:
Tue Apr 07 12:55:42 2020 +0200
Revision:
0:01f31e923fe2
hani: DAPLink with reset workaround

Who changed what in which revision?

UserRevisionLine numberNew contents of line
Pawel Zarembski 0:01f31e923fe2 1 /**
Pawel Zarembski 0:01f31e923fe2 2 * @file sdk.c
Pawel Zarembski 0:01f31e923fe2 3 * @brief
Pawel Zarembski 0:01f31e923fe2 4 *
Pawel Zarembski 0:01f31e923fe2 5 * DAPLink Interface Firmware
Pawel Zarembski 0:01f31e923fe2 6 * Copyright (c) 2017-2017, ARM Limited, All Rights Reserved
Pawel Zarembski 0:01f31e923fe2 7 * SPDX-License-Identifier: Apache-2.0
Pawel Zarembski 0:01f31e923fe2 8 *
Pawel Zarembski 0:01f31e923fe2 9 * Licensed under the Apache License, Version 2.0 (the "License"); you may
Pawel Zarembski 0:01f31e923fe2 10 * not use this file except in compliance with the License.
Pawel Zarembski 0:01f31e923fe2 11 * You may obtain a copy of the License at
Pawel Zarembski 0:01f31e923fe2 12 *
Pawel Zarembski 0:01f31e923fe2 13 * http://www.apache.org/licenses/LICENSE-2.0
Pawel Zarembski 0:01f31e923fe2 14 *
Pawel Zarembski 0:01f31e923fe2 15 * Unless required by applicable law or agreed to in writing, software
Pawel Zarembski 0:01f31e923fe2 16 * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
Pawel Zarembski 0:01f31e923fe2 17 * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
Pawel Zarembski 0:01f31e923fe2 18 * See the License for the specific language governing permissions and
Pawel Zarembski 0:01f31e923fe2 19 * limitations under the License.
Pawel Zarembski 0:01f31e923fe2 20 */
Pawel Zarembski 0:01f31e923fe2 21
Pawel Zarembski 0:01f31e923fe2 22 #include "NuMicro.h"
Pawel Zarembski 0:01f31e923fe2 23 #include "DAP_config.h"
Pawel Zarembski 0:01f31e923fe2 24 #include "gpio.h"
Pawel Zarembski 0:01f31e923fe2 25 #include "daplink.h"
Pawel Zarembski 0:01f31e923fe2 26 #include "util.h"
Pawel Zarembski 0:01f31e923fe2 27 #include "cortex_m.h"
Pawel Zarembski 0:01f31e923fe2 28
Pawel Zarembski 0:01f31e923fe2 29 void sdk_init()
Pawel Zarembski 0:01f31e923fe2 30 {
Pawel Zarembski 0:01f31e923fe2 31 uint32_t volatile i;
Pawel Zarembski 0:01f31e923fe2 32 /* Unlock protected registers */
Pawel Zarembski 0:01f31e923fe2 33 SYS_UnlockReg();
Pawel Zarembski 0:01f31e923fe2 34 /* Set XT1_OUT(PF.2) and XT1_IN(PF.3) to input mode */
Pawel Zarembski 0:01f31e923fe2 35 PF->MODE &= ~(GPIO_MODE_MODE2_Msk | GPIO_MODE_MODE3_Msk);
Pawel Zarembski 0:01f31e923fe2 36 /* Enable External XTAL (4~24 MHz) */
Pawel Zarembski 0:01f31e923fe2 37 CLK_EnableXtalRC(CLK_PWRCTL_HXTEN_Msk);
Pawel Zarembski 0:01f31e923fe2 38 /* Waiting for 12MHz clock ready */
Pawel Zarembski 0:01f31e923fe2 39 CLK_WaitClockReady(CLK_STATUS_HXTSTB_Msk);
Pawel Zarembski 0:01f31e923fe2 40 /* Switch HCLK clock source to HXT */
Pawel Zarembski 0:01f31e923fe2 41 CLK_SetHCLK(CLK_CLKSEL0_HCLKSEL_HXT, CLK_CLKDIV0_HCLK(1));
Pawel Zarembski 0:01f31e923fe2 42 /* Set core clock as PLL_CLOCK from PLL */
Pawel Zarembski 0:01f31e923fe2 43 CLK_SetCoreClock(FREQ_192MHZ);
Pawel Zarembski 0:01f31e923fe2 44 /* Set PCLK0/PCLK1 to HCLK/2 */
Pawel Zarembski 0:01f31e923fe2 45 CLK->PCLKDIV = (CLK_PCLKDIV_PCLK0DIV2 | CLK_PCLKDIV_PCLK1DIV2);
Pawel Zarembski 0:01f31e923fe2 46 /* Select HSUSBD */
Pawel Zarembski 0:01f31e923fe2 47 SYS->USBPHY &= ~SYS_USBPHY_HSUSBROLE_Msk;
Pawel Zarembski 0:01f31e923fe2 48 /* Enable USB PHY */
Pawel Zarembski 0:01f31e923fe2 49 SYS->USBPHY = (SYS->USBPHY & ~(SYS_USBPHY_HSUSBROLE_Msk | SYS_USBPHY_HSUSBACT_Msk)) | SYS_USBPHY_HSUSBEN_Msk;
Pawel Zarembski 0:01f31e923fe2 50
Pawel Zarembski 0:01f31e923fe2 51 for (i = 0; i < 0x1000; i++); // delay > 10 us
Pawel Zarembski 0:01f31e923fe2 52
Pawel Zarembski 0:01f31e923fe2 53 SYS->USBPHY |= SYS_USBPHY_HSUSBACT_Msk;
Pawel Zarembski 0:01f31e923fe2 54 /* Enable HSUSBD clock */
Pawel Zarembski 0:01f31e923fe2 55 CLK_EnableModuleClock(HSUSBD_MODULE);
Pawel Zarembski 0:01f31e923fe2 56 /* Select UART clock source */
Pawel Zarembski 0:01f31e923fe2 57 CLK_SetModuleClock(UART0_MODULE, CLK_CLKSEL1_UART0SEL_HXT, CLK_CLKDIV0_UART0(1));
Pawel Zarembski 0:01f31e923fe2 58 /* Enable UART clock */
Pawel Zarembski 0:01f31e923fe2 59 CLK_EnableModuleClock(UART0_MODULE);
Pawel Zarembski 0:01f31e923fe2 60 /* Set GPA multi-function pins for UART0 RXD and TXD */
Pawel Zarembski 0:01f31e923fe2 61 SYS->GPA_MFPL &= ~(SYS_GPA_MFPL_PA0MFP_Msk | SYS_GPA_MFPL_PA1MFP_Msk);
Pawel Zarembski 0:01f31e923fe2 62 SYS->GPA_MFPL |= (SYS_GPA_MFPL_PA0MFP_UART0_RXD | SYS_GPA_MFPL_PA1MFP_UART0_TXD);
Pawel Zarembski 0:01f31e923fe2 63 /* Update System Core Clock */
Pawel Zarembski 0:01f31e923fe2 64 /* User can use SystemCoreClockUpdate() to calculate SystemCoreClock. */
Pawel Zarembski 0:01f31e923fe2 65 SystemCoreClockUpdate();
Pawel Zarembski 0:01f31e923fe2 66 /* Lock protected registers */
Pawel Zarembski 0:01f31e923fe2 67 SYS_LockReg();
Pawel Zarembski 0:01f31e923fe2 68 }