Repostiory containing DAPLink source code with Reset Pin workaround for HANI_IOT board.
Upstream: https://github.com/ARMmbed/DAPLink
source/hic_hal/stm32/stm32f103xb/IO_Config.h@0:01f31e923fe2, 2020-04-07 (annotated)
- Committer:
- Pawel Zarembski
- Date:
- Tue Apr 07 12:55:42 2020 +0200
- Revision:
- 0:01f31e923fe2
hani: DAPLink with reset workaround
Who changed what in which revision?
User | Revision | Line number | New contents of line |
---|---|---|---|
Pawel Zarembski |
0:01f31e923fe2 | 1 | /** |
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0:01f31e923fe2 | 2 | * @file IO_Config.h |
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0:01f31e923fe2 | 3 | * @brief |
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0:01f31e923fe2 | 4 | * |
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0:01f31e923fe2 | 5 | * DAPLink Interface Firmware |
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0:01f31e923fe2 | 6 | * Copyright (c) 2009-2016, ARM Limited, All Rights Reserved |
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0:01f31e923fe2 | 7 | * SPDX-License-Identifier: Apache-2.0 |
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0:01f31e923fe2 | 8 | * |
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0:01f31e923fe2 | 9 | * Licensed under the Apache License, Version 2.0 (the "License"); you may |
Pawel Zarembski |
0:01f31e923fe2 | 10 | * not use this file except in compliance with the License. |
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0:01f31e923fe2 | 11 | * You may obtain a copy of the License at |
Pawel Zarembski |
0:01f31e923fe2 | 12 | * |
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0:01f31e923fe2 | 13 | * http://www.apache.org/licenses/LICENSE-2.0 |
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0:01f31e923fe2 | 14 | * |
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0:01f31e923fe2 | 15 | * Unless required by applicable law or agreed to in writing, software |
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0:01f31e923fe2 | 16 | * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT |
Pawel Zarembski |
0:01f31e923fe2 | 17 | * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. |
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0:01f31e923fe2 | 18 | * See the License for the specific language governing permissions and |
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0:01f31e923fe2 | 19 | * limitations under the License. |
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0:01f31e923fe2 | 20 | */ |
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0:01f31e923fe2 | 21 | |
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0:01f31e923fe2 | 22 | #ifndef __IO_CONFIG_H__ |
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0:01f31e923fe2 | 23 | #define __IO_CONFIG_H__ |
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0:01f31e923fe2 | 24 | |
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0:01f31e923fe2 | 25 | #include "stm32f1xx.h" |
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0:01f31e923fe2 | 26 | #include "compiler.h" |
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0:01f31e923fe2 | 27 | #include "daplink.h" |
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0:01f31e923fe2 | 28 | |
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0:01f31e923fe2 | 29 | COMPILER_ASSERT(DAPLINK_HIC_ID == DAPLINK_HIC_ID_STM32F103XB); |
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0:01f31e923fe2 | 30 | |
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0:01f31e923fe2 | 31 | //USB control pin |
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0:01f31e923fe2 | 32 | #define USB_CONNECT_PORT_ENABLE() __HAL_RCC_GPIOA_CLK_ENABLE() |
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0:01f31e923fe2 | 33 | #define USB_CONNECT_PORT_DISABLE() __HAL_RCC_GPIOA_CLK_DISABLE() |
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0:01f31e923fe2 | 34 | #define USB_CONNECT_PORT GPIOA |
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0:01f31e923fe2 | 35 | #define USB_CONNECT_PIN GPIO_PIN_15 |
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0:01f31e923fe2 | 36 | #define USB_CONNECT_ON() (USB_CONNECT_PORT->BSRR = USB_CONNECT_PIN) |
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0:01f31e923fe2 | 37 | #define USB_CONNECT_OFF() (USB_CONNECT_PORT->BRR = USB_CONNECT_PIN) |
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0:01f31e923fe2 | 38 | |
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0:01f31e923fe2 | 39 | //Connected LED |
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0:01f31e923fe2 | 40 | #define CONNECTED_LED_PORT GPIOB |
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0:01f31e923fe2 | 41 | #define CONNECTED_LED_PIN GPIO_PIN_6 |
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0:01f31e923fe2 | 42 | #define CONNECTED_LED_PIN_Bit 6 |
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0:01f31e923fe2 | 43 | |
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0:01f31e923fe2 | 44 | //When bootloader, disable the target port(not used) |
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0:01f31e923fe2 | 45 | #define POWER_EN_PIN_PORT GPIOB |
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0:01f31e923fe2 | 46 | #define POWER_EN_PIN GPIO_PIN_15 |
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0:01f31e923fe2 | 47 | #define POWER_EN_Bit 15 |
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0:01f31e923fe2 | 48 | |
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0:01f31e923fe2 | 49 | // nRESET OUT Pin |
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0:01f31e923fe2 | 50 | #define nRESET_PIN_PORT GPIOB |
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0:01f31e923fe2 | 51 | #define nRESET_PIN GPIO_PIN_0 |
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0:01f31e923fe2 | 52 | #define nRESET_PIN_Bit 0 |
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0:01f31e923fe2 | 53 | |
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0:01f31e923fe2 | 54 | //SWD |
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0:01f31e923fe2 | 55 | #define SWCLK_TCK_PIN_PORT GPIOB |
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0:01f31e923fe2 | 56 | #define SWCLK_TCK_PIN GPIO_PIN_13 |
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0:01f31e923fe2 | 57 | #define SWCLK_TCK_PIN_Bit 13 |
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0:01f31e923fe2 | 58 | |
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0:01f31e923fe2 | 59 | #define SWDIO_OUT_PIN_PORT GPIOB |
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0:01f31e923fe2 | 60 | #define SWDIO_OUT_PIN GPIO_PIN_14 |
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0:01f31e923fe2 | 61 | #define SWDIO_OUT_PIN_Bit 14 |
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0:01f31e923fe2 | 62 | |
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0:01f31e923fe2 | 63 | #define SWDIO_IN_PIN_PORT GPIOB |
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0:01f31e923fe2 | 64 | #define SWDIO_IN_PIN GPIO_PIN_12 |
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0:01f31e923fe2 | 65 | #define SWDIO_IN_PIN_Bit 12 |
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0:01f31e923fe2 | 66 | |
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0:01f31e923fe2 | 67 | //LEDs |
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0:01f31e923fe2 | 68 | //USB status LED |
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0:01f31e923fe2 | 69 | #define RUNNING_LED_PORT GPIOA |
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0:01f31e923fe2 | 70 | #define RUNNING_LED_PIN GPIO_PIN_9 |
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0:01f31e923fe2 | 71 | #define RUNNING_LED_Bit 9 |
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0:01f31e923fe2 | 72 | |
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0:01f31e923fe2 | 73 | #define PIN_HID_LED_PORT GPIOA |
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0:01f31e923fe2 | 74 | #define PIN_HID_LED GPIO_PIN_9 |
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0:01f31e923fe2 | 75 | #define PIN_HID_LED_Bit 9 |
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0:01f31e923fe2 | 76 | |
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0:01f31e923fe2 | 77 | #define PIN_CDC_LED_PORT GPIOA |
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0:01f31e923fe2 | 78 | #define PIN_CDC_LED GPIO_PIN_9 |
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0:01f31e923fe2 | 79 | #define PIN_CDC_LED_Bit 9 |
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0:01f31e923fe2 | 80 | |
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0:01f31e923fe2 | 81 | #define PIN_MSC_LED_PORT GPIOA |
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0:01f31e923fe2 | 82 | #define PIN_MSC_LED GPIO_PIN_9 |
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0:01f31e923fe2 | 83 | #define PIN_MSC_LED_Bit 9 |
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0:01f31e923fe2 | 84 | |
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0:01f31e923fe2 | 85 | |
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0:01f31e923fe2 | 86 | #endif |