Arrow
Repostiory containing DAPLink source code with Reset Pin workaround for HANI_IOT board.
Upstream: https://github.com/ARMmbed/DAPLink
source/hic_hal/nxp/lpc4322/DAP_config.h@0:01f31e923fe2, 2020-04-07 (annotated)
- Committer:
- Pawel Zarembski
- Date:
- Tue Apr 07 12:55:42 2020 +0200
- Revision:
- 0:01f31e923fe2
hani: DAPLink with reset workaround
Who changed what in which revision?
| User | Revision | Line number | New contents of line |
|---|---|---|---|
| Pawel Zarembski |
0:01f31e923fe2 | 1 | /** |
| Pawel Zarembski |
0:01f31e923fe2 | 2 | * @file DAP_config.c |
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0:01f31e923fe2 | 3 | * @brief |
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0:01f31e923fe2 | 4 | * |
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0:01f31e923fe2 | 5 | * DAPLink Interface Firmware |
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0:01f31e923fe2 | 6 | * Copyright (c) 2009-2016, ARM Limited, All Rights Reserved |
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0:01f31e923fe2 | 7 | * SPDX-License-Identifier: Apache-2.0 |
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0:01f31e923fe2 | 8 | * |
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0:01f31e923fe2 | 9 | * Licensed under the Apache License, Version 2.0 (the "License"); you may |
| Pawel Zarembski |
0:01f31e923fe2 | 10 | * not use this file except in compliance with the License. |
| Pawel Zarembski |
0:01f31e923fe2 | 11 | * You may obtain a copy of the License at |
| Pawel Zarembski |
0:01f31e923fe2 | 12 | * |
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0:01f31e923fe2 | 13 | * http://www.apache.org/licenses/LICENSE-2.0 |
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0:01f31e923fe2 | 14 | * |
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0:01f31e923fe2 | 15 | * Unless required by applicable law or agreed to in writing, software |
| Pawel Zarembski |
0:01f31e923fe2 | 16 | * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT |
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0:01f31e923fe2 | 17 | * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. |
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0:01f31e923fe2 | 18 | * See the License for the specific language governing permissions and |
| Pawel Zarembski |
0:01f31e923fe2 | 19 | * limitations under the License. |
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0:01f31e923fe2 | 20 | */ |
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0:01f31e923fe2 | 21 | |
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0:01f31e923fe2 | 22 | #ifndef __DAP_CONFIG_H__ |
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0:01f31e923fe2 | 23 | #define __DAP_CONFIG_H__ |
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0:01f31e923fe2 | 24 | |
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0:01f31e923fe2 | 25 | |
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0:01f31e923fe2 | 26 | //************************************************************************************************** |
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0:01f31e923fe2 | 27 | /** |
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0:01f31e923fe2 | 28 | \defgroup DAP_Config_Debug_gr CMSIS-DAP Debug Unit Information |
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0:01f31e923fe2 | 29 | \ingroup DAP_ConfigIO_gr |
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0:01f31e923fe2 | 30 | @{ |
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0:01f31e923fe2 | 31 | Provides definitions about: |
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0:01f31e923fe2 | 32 | - Definition of Cortex-M processor parameters used in CMSIS-DAP Debug Unit. |
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0:01f31e923fe2 | 33 | - Debug Unit communication packet size. |
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0:01f31e923fe2 | 34 | - Debug Access Port communication mode (JTAG or SWD). |
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0:01f31e923fe2 | 35 | - Optional information about a connected Target Device (for Evaluation Boards). |
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0:01f31e923fe2 | 36 | */ |
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0:01f31e923fe2 | 37 | |
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0:01f31e923fe2 | 38 | #include "LPC43xx.h" // Debug Unit Cortex-M Processor Header File |
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0:01f31e923fe2 | 39 | #include "lpc43xx_scu.h" |
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0:01f31e923fe2 | 40 | |
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0:01f31e923fe2 | 41 | typedef unsigned int BOOL; |
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0:01f31e923fe2 | 42 | |
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0:01f31e923fe2 | 43 | #ifndef __TRUE |
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0:01f31e923fe2 | 44 | #define __TRUE 1 |
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0:01f31e923fe2 | 45 | #endif |
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0:01f31e923fe2 | 46 | #ifndef __FALSE |
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0:01f31e923fe2 | 47 | #define __FALSE 0 |
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0:01f31e923fe2 | 48 | #endif |
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0:01f31e923fe2 | 49 | |
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0:01f31e923fe2 | 50 | /// Processor Clock of the Cortex-M MCU used in the Debug Unit. |
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0:01f31e923fe2 | 51 | /// This value is used to calculate the SWD/JTAG clock speed. |
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0:01f31e923fe2 | 52 | #define CPU_CLOCK SystemCoreClock ///< Specifies the CPU Clock in Hz |
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0:01f31e923fe2 | 53 | |
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0:01f31e923fe2 | 54 | /// Number of processor cycles for I/O Port write operations. |
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0:01f31e923fe2 | 55 | /// This value is used to calculate the SWD/JTAG clock speed that is generated with I/O |
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0:01f31e923fe2 | 56 | /// Port write operations in the Debug Unit by a Cortex-M MCU. Most Cortex-M processors |
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0:01f31e923fe2 | 57 | /// requrie 2 processor cycles for a I/O Port Write operation. If the Debug Unit uses |
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0:01f31e923fe2 | 58 | /// a Cortex-M0+ processor with high-speed peripheral I/O only 1 processor cycle might be |
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0:01f31e923fe2 | 59 | /// required. |
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0:01f31e923fe2 | 60 | #define IO_PORT_WRITE_CYCLES 2 ///< I/O Cycles: 2=default, 1=Cortex-M0+ fast I/0 |
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0:01f31e923fe2 | 61 | |
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0:01f31e923fe2 | 62 | /// Indicate that Serial Wire Debug (SWD) communication mode is available at the Debug Access Port. |
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0:01f31e923fe2 | 63 | /// This information is returned by the command \ref DAP_Info as part of <b>Capabilities</b>. |
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0:01f31e923fe2 | 64 | #define DAP_SWD 1 ///< SWD Mode: 1 = available, 0 = not available |
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0:01f31e923fe2 | 65 | |
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0:01f31e923fe2 | 66 | /// Indicate that JTAG communication mode is available at the Debug Port. |
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0:01f31e923fe2 | 67 | /// This information is returned by the command \ref DAP_Info as part of <b>Capabilities</b>. |
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0:01f31e923fe2 | 68 | #define DAP_JTAG 0 ///< JTAG Mode: 1 = available, 0 = not available. |
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0:01f31e923fe2 | 69 | |
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0:01f31e923fe2 | 70 | /// Configure maximum number of JTAG devices on the scan chain connected to the Debug Access Port. |
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0:01f31e923fe2 | 71 | /// This setting impacts the RAM requirements of the Debug Unit. Valid range is 1 .. 255. |
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0:01f31e923fe2 | 72 | #define DAP_JTAG_DEV_CNT 0 ///< Maximum number of JTAG devices on scan chain |
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0:01f31e923fe2 | 73 | |
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0:01f31e923fe2 | 74 | /// Default communication mode on the Debug Access Port. |
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0:01f31e923fe2 | 75 | /// Used for the command \ref DAP_Connect when Port Default mode is selected. |
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0:01f31e923fe2 | 76 | #define DAP_DEFAULT_PORT 1 ///< Default JTAG/SWJ Port Mode: 1 = SWD, 2 = JTAG. |
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0:01f31e923fe2 | 77 | |
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0:01f31e923fe2 | 78 | /// Default communication speed on the Debug Access Port for SWD and JTAG mode. |
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0:01f31e923fe2 | 79 | /// Used to initialize the default SWD/JTAG clock frequency. |
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0:01f31e923fe2 | 80 | /// The command \ref DAP_SWJ_Clock can be used to overwrite this default setting. |
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0:01f31e923fe2 | 81 | #define DAP_DEFAULT_SWJ_CLOCK 5000000 ///< Default SWD/JTAG clock frequency in Hz. |
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0:01f31e923fe2 | 82 | |
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0:01f31e923fe2 | 83 | /// Maximum Package Size for Command and Response data. |
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0:01f31e923fe2 | 84 | /// This configuration settings is used to optimized the communication performance with the |
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0:01f31e923fe2 | 85 | /// debugger and depends on the USB peripheral. Change setting to 1024 for High-Speed USB. |
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0:01f31e923fe2 | 86 | #define DAP_PACKET_SIZE 64 ///< USB: 64 = Full-Speed, 1024 = High-Speed. |
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0:01f31e923fe2 | 87 | |
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0:01f31e923fe2 | 88 | /// Maximum Package Buffers for Command and Response data. |
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0:01f31e923fe2 | 89 | /// This configuration settings is used to optimized the communication performance with the |
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0:01f31e923fe2 | 90 | /// debugger and depends on the USB peripheral. For devices with limited RAM or USB buffer the |
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0:01f31e923fe2 | 91 | /// setting can be reduced (valid range is 1 .. 255). Change setting to 4 for High-Speed USB. |
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0:01f31e923fe2 | 92 | #define DAP_PACKET_COUNT 1 ///< Buffers: 64 = Full-Speed, 4 = High-Speed. |
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0:01f31e923fe2 | 93 | |
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0:01f31e923fe2 | 94 | /// Indicate that UART Serial Wire Output (SWO) trace is available. |
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0:01f31e923fe2 | 95 | /// This information is returned by the command \ref DAP_Info as part of <b>Capabilities</b>. |
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0:01f31e923fe2 | 96 | #define SWO_UART 0 ///< SWO UART: 1 = available, 0 = not available |
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0:01f31e923fe2 | 97 | |
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0:01f31e923fe2 | 98 | /// Maximum SWO UART Baudrate |
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0:01f31e923fe2 | 99 | #define SWO_UART_MAX_BAUDRATE 10000000U ///< SWO UART Maximum Baudrate in Hz |
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0:01f31e923fe2 | 100 | |
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0:01f31e923fe2 | 101 | /// Indicate that Manchester Serial Wire Output (SWO) trace is available. |
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0:01f31e923fe2 | 102 | /// This information is returned by the command \ref DAP_Info as part of <b>Capabilities</b>. |
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0:01f31e923fe2 | 103 | #define SWO_MANCHESTER 0 ///< SWO Manchester: 1 = available, 0 = not available |
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0:01f31e923fe2 | 104 | |
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0:01f31e923fe2 | 105 | /// SWO Trace Buffer Size. |
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0:01f31e923fe2 | 106 | #define SWO_BUFFER_SIZE 4096U ///< SWO Trace Buffer Size in bytes (must be 2^n) |
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0:01f31e923fe2 | 107 | |
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0:01f31e923fe2 | 108 | /// SWO Streaming Trace. |
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0:01f31e923fe2 | 109 | #define SWO_STREAM 0 ///< SWO Streaming Trace: 1 = available, 0 = not available. |
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0:01f31e923fe2 | 110 | |
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0:01f31e923fe2 | 111 | /// Clock frequency of the Test Domain Timer. Timer value is returned with \ref TIMESTAMP_GET. |
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0:01f31e923fe2 | 112 | #define TIMESTAMP_CLOCK 1000000U ///< Timestamp clock in Hz (0 = timestamps not supported). |
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0:01f31e923fe2 | 113 | |
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0:01f31e923fe2 | 114 | |
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0:01f31e923fe2 | 115 | /// Debug Unit is connected to fixed Target Device. |
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0:01f31e923fe2 | 116 | /// The Debug Unit may be part of an evaluation board and always connected to a fixed |
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0:01f31e923fe2 | 117 | /// known device. In this case a Device Vendor and Device Name string is stored which |
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0:01f31e923fe2 | 118 | /// may be used by the debugger or IDE to configure device parameters. |
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0:01f31e923fe2 | 119 | #define TARGET_DEVICE_FIXED 0 ///< Target Device: 1 = known, 0 = unknown; |
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0:01f31e923fe2 | 120 | |
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0:01f31e923fe2 | 121 | #if TARGET_DEVICE_FIXED |
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0:01f31e923fe2 | 122 | #define TARGET_DEVICE_VENDOR "" ///< String indicating the Silicon Vendor |
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0:01f31e923fe2 | 123 | #define TARGET_DEVICE_NAME "" ///< String indicating the Target Device |
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0:01f31e923fe2 | 124 | #endif |
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0:01f31e923fe2 | 125 | |
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0:01f31e923fe2 | 126 | ///@} |
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0:01f31e923fe2 | 127 | |
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0:01f31e923fe2 | 128 | |
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0:01f31e923fe2 | 129 | // LPC43xx peripheral register bit masks (used by macros) |
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0:01f31e923fe2 | 130 | #define CCU_CLK_CFG_RUN (1UL << 0) |
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0:01f31e923fe2 | 131 | #define CCU_CLK_CFG_AUTO (1UL << 1) |
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0:01f31e923fe2 | 132 | #define CCU_CLK_STAT_RUN (1UL << 0) |
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0:01f31e923fe2 | 133 | |
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0:01f31e923fe2 | 134 | // State of Reset Ouput Enable buffer |
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0:01f31e923fe2 | 135 | extern BOOL gpio_reset_pin_is_input; |
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0:01f31e923fe2 | 136 | |
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0:01f31e923fe2 | 137 | // Debug Port I/O Pins |
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0:01f31e923fe2 | 138 | |
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0:01f31e923fe2 | 139 | // SWCLK Pin P1_17: GPIO0[12] |
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0:01f31e923fe2 | 140 | #define PORT_SWCLK 0 |
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0:01f31e923fe2 | 141 | #define PIN_SWCLK_IN_BIT 12 |
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0:01f31e923fe2 | 142 | #define PIN_SWCLK (1<<PIN_SWCLK_IN_BIT) |
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0:01f31e923fe2 | 143 | |
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0:01f31e923fe2 | 144 | // SWDIO Pin P1_6: GPIO1[9] |
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0:01f31e923fe2 | 145 | #define PORT_SWDIO 1 |
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0:01f31e923fe2 | 146 | #define PIN_SWDIO_IN_BIT 9 |
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0:01f31e923fe2 | 147 | #define PIN_SWDIO (1<<PIN_SWDIO_IN_BIT) |
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0:01f31e923fe2 | 148 | |
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0:01f31e923fe2 | 149 | // SWDIO Output Enable Pin P1_5: GPIO1[8] |
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0:01f31e923fe2 | 150 | #define PORT_SWDIO_TXE 1 |
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0:01f31e923fe2 | 151 | #define PIN_SWDIO_TXE_IN_BIT 8 |
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0:01f31e923fe2 | 152 | #define PIN_SWDIO_TXE (1<<PIN_SWDIO_TXE_IN_BIT) |
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0:01f31e923fe2 | 153 | |
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0:01f31e923fe2 | 154 | // nRESET Pin P2_5: GPIO5[5] note: HANI_IOT workaround: changing to GPIO0[7] |
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0:01f31e923fe2 | 155 | #define PORT_nRESET 0 |
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0:01f31e923fe2 | 156 | #define PIN_nRESET_IN_BIT 7 |
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0:01f31e923fe2 | 157 | #define PIN_nRESET (1<<PIN_nRESET_IN_BIT) |
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0:01f31e923fe2 | 158 | |
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0:01f31e923fe2 | 159 | // nRESET Output Enable Pin P2_6: GPIO5[6] |
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0:01f31e923fe2 | 160 | #define PORT_RESET_TXE 5 |
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0:01f31e923fe2 | 161 | #define PIN_RESET_TXE_IN_BIT 6 |
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0:01f31e923fe2 | 162 | #define PIN_RESET_TXE (1<<PIN_RESET_TXE_IN_BIT) |
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0:01f31e923fe2 | 163 | |
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0:01f31e923fe2 | 164 | // ISP Control Pin P2_11: GPIO1[11] |
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0:01f31e923fe2 | 165 | #define ISPCTRL_PORT 1 |
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0:01f31e923fe2 | 166 | #define ISPCTRL_BIT 11 |
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0:01f31e923fe2 | 167 | |
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0:01f31e923fe2 | 168 | #define X_SET(str) LPC_GPIO_PORT->SET[PORT_##str] = PIN_##str |
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0:01f31e923fe2 | 169 | #define X_CLR(str) LPC_GPIO_PORT->CLR[PORT_##str] = PIN_##str |
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0:01f31e923fe2 | 170 | #define X_DIR_OUT(str) LPC_GPIO_PORT->DIR[PORT_##str] |= (PIN_##str) |
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0:01f31e923fe2 | 171 | #define X_DIR_IN(str) LPC_GPIO_PORT->DIR[PORT_##str] &= ~(PIN_##str) |
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0:01f31e923fe2 | 172 | #define X_BYTE(str) LPC_GPIO_PORT->B[(PORT_##str << 5) + PIN_##str##_IN_BIT] |
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0:01f31e923fe2 | 173 | |
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0:01f31e923fe2 | 174 | |
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0:01f31e923fe2 | 175 | //************************************************************************************************** |
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0:01f31e923fe2 | 176 | /** |
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0:01f31e923fe2 | 177 | \defgroup DAP_Config_PortIO_gr CMSIS-DAP Hardware I/O Pin Access |
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0:01f31e923fe2 | 178 | \ingroup DAP_ConfigIO_gr |
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0:01f31e923fe2 | 179 | @{ |
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0:01f31e923fe2 | 180 | |
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0:01f31e923fe2 | 181 | Standard I/O Pins of the CMSIS-DAP Hardware Debug Port support standard JTAG mode |
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0:01f31e923fe2 | 182 | and Serial Wire Debug (SWD) mode. In SWD mode only 2 pins are required to implement the debug |
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0:01f31e923fe2 | 183 | interface of a device. The following I/O Pins are provided: |
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0:01f31e923fe2 | 184 | |
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0:01f31e923fe2 | 185 | JTAG I/O Pin | SWD I/O Pin | CMSIS-DAP Hardware pin mode |
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0:01f31e923fe2 | 186 | ---------------------------- | -------------------- | --------------------------------------------- |
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0:01f31e923fe2 | 187 | TCK: Test Clock | SWCLK: Clock | Output Push/Pull |
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0:01f31e923fe2 | 188 | TMS: Test Mode Select | SWDIO: Data I/O | Output Push/Pull; Input (for receiving data) |
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0:01f31e923fe2 | 189 | TDI: Test Data Input | | Output Push/Pull |
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0:01f31e923fe2 | 190 | TDO: Test Data Output | | Input |
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0:01f31e923fe2 | 191 | nTRST: Test Reset (optional) | | Output Open Drain with pull-up resistor |
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0:01f31e923fe2 | 192 | nRESET: Device Reset | nRESET: Device Reset | Output Open Drain with pull-up resistor |
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0:01f31e923fe2 | 193 | |
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0:01f31e923fe2 | 194 | |
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0:01f31e923fe2 | 195 | DAP Hardware I/O Pin Access Functions |
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0:01f31e923fe2 | 196 | ------------------------------------- |
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0:01f31e923fe2 | 197 | The various I/O Pins are accessed by functions that implement the Read, Write, Set, or Clear to |
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0:01f31e923fe2 | 198 | these I/O Pins. |
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0:01f31e923fe2 | 199 | |
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0:01f31e923fe2 | 200 | For the SWDIO I/O Pin there are additional functions that are called in SWD I/O mode only. |
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0:01f31e923fe2 | 201 | This functions are provided to achieve faster I/O that is possible with some advanced GPIO |
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0:01f31e923fe2 | 202 | peripherals that can independently write/read a single I/O pin without affecting any other pins |
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0:01f31e923fe2 | 203 | of the same I/O port. The following SWDIO I/O Pin functions are provided: |
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0:01f31e923fe2 | 204 | - \ref PIN_SWDIO_OUT_ENABLE to enable the output mode from the DAP hardware. |
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0:01f31e923fe2 | 205 | - \ref PIN_SWDIO_OUT_DISABLE to enable the input mode to the DAP hardware. |
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0:01f31e923fe2 | 206 | - \ref PIN_SWDIO_IN to read from the SWDIO I/O pin with utmost possible speed. |
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0:01f31e923fe2 | 207 | - \ref PIN_SWDIO_OUT to write to the SWDIO I/O pin with utmost possible speed. |
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0:01f31e923fe2 | 208 | */ |
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0:01f31e923fe2 | 209 | |
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0:01f31e923fe2 | 210 | |
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0:01f31e923fe2 | 211 | // Configure DAP I/O pins ------------------------------ |
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0:01f31e923fe2 | 212 | |
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0:01f31e923fe2 | 213 | /** Setup JTAG I/O pins: TCK, TMS, TDI, TDO, nTRST, and nRESET. |
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0:01f31e923fe2 | 214 | Configures the DAP Hardware I/O pins for JTAG mode: |
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0:01f31e923fe2 | 215 | - TCK, TMS, TDI, nTRST, nRESET to output mode and set to high level. |
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0:01f31e923fe2 | 216 | - TDO to input mode. |
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0:01f31e923fe2 | 217 | */ |
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0:01f31e923fe2 | 218 | __STATIC_INLINE void PORT_JTAG_SETUP(void) {} |
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0:01f31e923fe2 | 219 | |
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0:01f31e923fe2 | 220 | /** Setup SWD I/O pins: SWCLK, SWDIO, and nRESET. |
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0:01f31e923fe2 | 221 | Configures the DAP Hardware I/O pins for Serial Wire Debug (SWD) mode: |
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0:01f31e923fe2 | 222 | - SWCLK, SWDIO, nRESET to output mode and set to default high level. |
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0:01f31e923fe2 | 223 | - TDI, TMS, nTRST to HighZ mode (pins are unused in SWD mode). |
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0:01f31e923fe2 | 224 | */ |
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0:01f31e923fe2 | 225 | __STATIC_INLINE void PORT_SWD_SETUP(void) |
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0:01f31e923fe2 | 226 | { |
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0:01f31e923fe2 | 227 | X_SET(SWCLK); |
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0:01f31e923fe2 | 228 | X_SET(SWDIO); |
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0:01f31e923fe2 | 229 | X_DIR_OUT(SWCLK); |
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0:01f31e923fe2 | 230 | X_DIR_OUT(SWDIO); |
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0:01f31e923fe2 | 231 | X_SET(SWDIO_TXE); |
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0:01f31e923fe2 | 232 | X_DIR_OUT(SWDIO_TXE); |
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0:01f31e923fe2 | 233 | } |
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0:01f31e923fe2 | 234 | |
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0:01f31e923fe2 | 235 | |
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0:01f31e923fe2 | 236 | /** Disable JTAG/SWD I/O Pins. |
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0:01f31e923fe2 | 237 | Disables the DAP Hardware I/O pins which configures: |
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0:01f31e923fe2 | 238 | - TCK/SWCLK, TMS/SWDIO, TDI, TDO, nTRST, nRESET to High-Z mode. |
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0:01f31e923fe2 | 239 | */ |
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0:01f31e923fe2 | 240 | __STATIC_INLINE void PORT_OFF(void) |
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0:01f31e923fe2 | 241 | { |
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0:01f31e923fe2 | 242 | X_CLR(SWCLK); |
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0:01f31e923fe2 | 243 | X_CLR(SWDIO); |
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0:01f31e923fe2 | 244 | X_DIR_OUT(SWCLK); |
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0:01f31e923fe2 | 245 | X_DIR_OUT(SWDIO); |
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0:01f31e923fe2 | 246 | X_SET(SWDIO_TXE); |
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0:01f31e923fe2 | 247 | X_DIR_OUT(SWDIO_TXE); |
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0:01f31e923fe2 | 248 | } |
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0:01f31e923fe2 | 249 | |
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0:01f31e923fe2 | 250 | |
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0:01f31e923fe2 | 251 | // SWCLK/TCK I/O pin ------------------------------------- |
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0:01f31e923fe2 | 252 | |
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0:01f31e923fe2 | 253 | /** SWCLK/TCK I/O pin: Get Input. |
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0:01f31e923fe2 | 254 | \return Current status of the SWCLK/TCK DAP hardware I/O pin. |
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0:01f31e923fe2 | 255 | */ |
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0:01f31e923fe2 | 256 | __STATIC_FORCEINLINE uint32_t PIN_SWCLK_TCK_IN(void) |
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0:01f31e923fe2 | 257 | { |
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0:01f31e923fe2 | 258 | return (0); // Not available |
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0:01f31e923fe2 | 259 | } |
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0:01f31e923fe2 | 260 | |
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0:01f31e923fe2 | 261 | /** SWCLK/TCK I/O pin: Set Output to High. |
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0:01f31e923fe2 | 262 | Set the SWCLK/TCK DAP hardware I/O pin to high level. |
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0:01f31e923fe2 | 263 | */ |
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0:01f31e923fe2 | 264 | __STATIC_FORCEINLINE void PIN_SWCLK_TCK_SET(void) |
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0:01f31e923fe2 | 265 | { |
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0:01f31e923fe2 | 266 | X_SET(SWCLK); |
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0:01f31e923fe2 | 267 | } |
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0:01f31e923fe2 | 268 | |
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0:01f31e923fe2 | 269 | /** SWCLK/TCK I/O pin: Set Output to Low. |
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0:01f31e923fe2 | 270 | Set the SWCLK/TCK DAP hardware I/O pin to low level. |
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0:01f31e923fe2 | 271 | */ |
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0:01f31e923fe2 | 272 | __STATIC_FORCEINLINE void PIN_SWCLK_TCK_CLR(void) |
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0:01f31e923fe2 | 273 | { |
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0:01f31e923fe2 | 274 | X_CLR(SWCLK); |
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0:01f31e923fe2 | 275 | } |
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0:01f31e923fe2 | 276 | |
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0:01f31e923fe2 | 277 | |
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0:01f31e923fe2 | 278 | // SWDIO/TMS Pin I/O -------------------------------------- |
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0:01f31e923fe2 | 279 | |
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0:01f31e923fe2 | 280 | /** SWDIO/TMS I/O pin: Get Input. |
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0:01f31e923fe2 | 281 | \return Current status of the SWDIO/TMS DAP hardware I/O pin. |
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0:01f31e923fe2 | 282 | */ |
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0:01f31e923fe2 | 283 | __STATIC_FORCEINLINE uint32_t PIN_SWDIO_TMS_IN(void) |
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0:01f31e923fe2 | 284 | { |
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0:01f31e923fe2 | 285 | return X_BYTE(SWDIO) & 0x1; |
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0:01f31e923fe2 | 286 | } |
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0:01f31e923fe2 | 287 | |
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0:01f31e923fe2 | 288 | /** SWDIO/TMS I/O pin: Set Output to High. |
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0:01f31e923fe2 | 289 | Set the SWDIO/TMS DAP hardware I/O pin to high level. |
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0:01f31e923fe2 | 290 | */ |
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0:01f31e923fe2 | 291 | __STATIC_FORCEINLINE void PIN_SWDIO_TMS_SET(void) |
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0:01f31e923fe2 | 292 | { |
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0:01f31e923fe2 | 293 | X_SET(SWDIO); |
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0:01f31e923fe2 | 294 | } |
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0:01f31e923fe2 | 295 | |
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0:01f31e923fe2 | 296 | /** SWDIO/TMS I/O pin: Set Output to Low. |
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0:01f31e923fe2 | 297 | Set the SWDIO/TMS DAP hardware I/O pin to low level. |
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0:01f31e923fe2 | 298 | */ |
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0:01f31e923fe2 | 299 | __STATIC_FORCEINLINE void PIN_SWDIO_TMS_CLR(void) |
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0:01f31e923fe2 | 300 | { |
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0:01f31e923fe2 | 301 | X_CLR(SWDIO); |
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0:01f31e923fe2 | 302 | } |
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0:01f31e923fe2 | 303 | |
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0:01f31e923fe2 | 304 | /** SWDIO I/O pin: Get Input (used in SWD mode only). |
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0:01f31e923fe2 | 305 | \return Current status of the SWDIO DAP hardware I/O pin. |
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0:01f31e923fe2 | 306 | */ |
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0:01f31e923fe2 | 307 | __STATIC_FORCEINLINE uint32_t PIN_SWDIO_IN(void) |
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0:01f31e923fe2 | 308 | { |
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0:01f31e923fe2 | 309 | return X_BYTE(SWDIO) & 0x1; |
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0:01f31e923fe2 | 310 | } |
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0:01f31e923fe2 | 311 | |
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0:01f31e923fe2 | 312 | /** SWDIO I/O pin: Set Output (used in SWD mode only). |
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0:01f31e923fe2 | 313 | \param bit Output value for the SWDIO DAP hardware I/O pin. |
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0:01f31e923fe2 | 314 | */ |
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0:01f31e923fe2 | 315 | __STATIC_FORCEINLINE void PIN_SWDIO_OUT(uint32_t bit) |
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0:01f31e923fe2 | 316 | { |
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0:01f31e923fe2 | 317 | if (bit & 0x1) { |
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0:01f31e923fe2 | 318 | X_SET(SWDIO); |
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0:01f31e923fe2 | 319 | } else { |
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0:01f31e923fe2 | 320 | X_CLR(SWDIO); |
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0:01f31e923fe2 | 321 | } |
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0:01f31e923fe2 | 322 | } |
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0:01f31e923fe2 | 323 | |
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0:01f31e923fe2 | 324 | /** SWDIO I/O pin: Switch to Output mode (used in SWD mode only). |
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0:01f31e923fe2 | 325 | Configure the SWDIO DAP hardware I/O pin to output mode. This function is |
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0:01f31e923fe2 | 326 | called prior \ref PIN_SWDIO_OUT function calls. |
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0:01f31e923fe2 | 327 | */ |
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0:01f31e923fe2 | 328 | __STATIC_FORCEINLINE void PIN_SWDIO_OUT_ENABLE(void) |
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0:01f31e923fe2 | 329 | { |
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0:01f31e923fe2 | 330 | X_SET(SWDIO_TXE); |
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0:01f31e923fe2 | 331 | X_DIR_OUT(SWDIO); |
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0:01f31e923fe2 | 332 | } |
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0:01f31e923fe2 | 333 | |
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0:01f31e923fe2 | 334 | /** SWDIO I/O pin: Switch to Input mode (used in SWD mode only). |
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0:01f31e923fe2 | 335 | Configure the SWDIO DAP hardware I/O pin to input mode. This function is |
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0:01f31e923fe2 | 336 | called prior \ref PIN_SWDIO_IN function calls. |
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0:01f31e923fe2 | 337 | */ |
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0:01f31e923fe2 | 338 | __STATIC_FORCEINLINE void PIN_SWDIO_OUT_DISABLE(void) |
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0:01f31e923fe2 | 339 | { |
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0:01f31e923fe2 | 340 | X_DIR_IN(SWDIO); |
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0:01f31e923fe2 | 341 | X_CLR(SWDIO_TXE); |
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0:01f31e923fe2 | 342 | } |
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0:01f31e923fe2 | 343 | |
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0:01f31e923fe2 | 344 | |
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0:01f31e923fe2 | 345 | // TDI Pin I/O --------------------------------------------- |
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0:01f31e923fe2 | 346 | |
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0:01f31e923fe2 | 347 | /** TDI I/O pin: Get Input. |
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0:01f31e923fe2 | 348 | \return Current status of the TDI DAP hardware I/O pin. |
| Pawel Zarembski |
0:01f31e923fe2 | 349 | */ |
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0:01f31e923fe2 | 350 | __STATIC_FORCEINLINE uint32_t PIN_TDI_IN(void) |
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0:01f31e923fe2 | 351 | { |
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0:01f31e923fe2 | 352 | return (0); // Not available |
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0:01f31e923fe2 | 353 | } |
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0:01f31e923fe2 | 354 | |
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0:01f31e923fe2 | 355 | /** TDI I/O pin: Set Output. |
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0:01f31e923fe2 | 356 | \param bit Output value for the TDI DAP hardware I/O pin. |
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0:01f31e923fe2 | 357 | */ |
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0:01f31e923fe2 | 358 | __STATIC_FORCEINLINE void PIN_TDI_OUT(uint32_t bit) |
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0:01f31e923fe2 | 359 | { |
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0:01f31e923fe2 | 360 | ; // Not available |
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0:01f31e923fe2 | 361 | } |
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0:01f31e923fe2 | 362 | |
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0:01f31e923fe2 | 363 | |
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0:01f31e923fe2 | 364 | // TDO Pin I/O --------------------------------------------- |
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0:01f31e923fe2 | 365 | |
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0:01f31e923fe2 | 366 | /** TDO I/O pin: Get Input. |
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0:01f31e923fe2 | 367 | \return Current status of the TDO DAP hardware I/O pin. |
| Pawel Zarembski |
0:01f31e923fe2 | 368 | */ |
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0:01f31e923fe2 | 369 | __STATIC_FORCEINLINE uint32_t PIN_TDO_IN(void) |
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0:01f31e923fe2 | 370 | { |
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0:01f31e923fe2 | 371 | return (0); // Not available |
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0:01f31e923fe2 | 372 | } |
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0:01f31e923fe2 | 373 | |
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0:01f31e923fe2 | 374 | |
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0:01f31e923fe2 | 375 | // nTRST Pin I/O ------------------------------------------- |
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0:01f31e923fe2 | 376 | |
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0:01f31e923fe2 | 377 | /** nTRST I/O pin: Get Input. |
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0:01f31e923fe2 | 378 | \return Current status of the nTRST DAP hardware I/O pin. |
| Pawel Zarembski |
0:01f31e923fe2 | 379 | */ |
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0:01f31e923fe2 | 380 | __STATIC_FORCEINLINE uint32_t PIN_nTRST_IN(void) |
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0:01f31e923fe2 | 381 | { |
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0:01f31e923fe2 | 382 | return (0); // Not available |
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0:01f31e923fe2 | 383 | } |
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0:01f31e923fe2 | 384 | |
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0:01f31e923fe2 | 385 | /** nTRST I/O pin: Set Output. |
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0:01f31e923fe2 | 386 | \param bit JTAG TRST Test Reset pin status: |
| Pawel Zarembski |
0:01f31e923fe2 | 387 | - 0: issue a JTAG TRST Test Reset. |
| Pawel Zarembski |
0:01f31e923fe2 | 388 | - 1: release JTAG TRST Test Reset. |
| Pawel Zarembski |
0:01f31e923fe2 | 389 | */ |
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0:01f31e923fe2 | 390 | __STATIC_FORCEINLINE void PIN_nTRST_OUT(uint32_t bit) |
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0:01f31e923fe2 | 391 | { |
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0:01f31e923fe2 | 392 | ; // Not available |
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0:01f31e923fe2 | 393 | } |
| Pawel Zarembski |
0:01f31e923fe2 | 394 | |
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0:01f31e923fe2 | 395 | // nRESET Pin I/O------------------------------------------ |
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0:01f31e923fe2 | 396 | |
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0:01f31e923fe2 | 397 | /** nRESET I/O pin: Get Input. |
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0:01f31e923fe2 | 398 | \return Current status of the nRESET DAP hardware I/O pin. |
| Pawel Zarembski |
0:01f31e923fe2 | 399 | */ |
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0:01f31e923fe2 | 400 | __STATIC_FORCEINLINE uint32_t PIN_nRESET_IN(void) |
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0:01f31e923fe2 | 401 | { |
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0:01f31e923fe2 | 402 | if (gpio_reset_pin_is_input) { |
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0:01f31e923fe2 | 403 | return X_BYTE(nRESET) & 0x1; |
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0:01f31e923fe2 | 404 | } else { |
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0:01f31e923fe2 | 405 | return 0; // Always LOW when output |
| Pawel Zarembski |
0:01f31e923fe2 | 406 | } |
| Pawel Zarembski |
0:01f31e923fe2 | 407 | } |
| Pawel Zarembski |
0:01f31e923fe2 | 408 | |
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0:01f31e923fe2 | 409 | /** nRESET I/O pin: Set Output. |
| Pawel Zarembski |
0:01f31e923fe2 | 410 | \param bit target device hardware reset pin status: |
| Pawel Zarembski |
0:01f31e923fe2 | 411 | - 0: issue a device hardware reset. |
| Pawel Zarembski |
0:01f31e923fe2 | 412 | - 1: release device hardware reset. |
| Pawel Zarembski |
0:01f31e923fe2 | 413 | */ |
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0:01f31e923fe2 | 414 | __STATIC_FORCEINLINE void PIN_nRESET_OUT(uint32_t bit) |
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0:01f31e923fe2 | 415 | { |
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0:01f31e923fe2 | 416 | if (bit) { |
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0:01f31e923fe2 | 417 | // release device hardware reset. (reset INPUT, reset oe LOW=INPUT) |
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0:01f31e923fe2 | 418 | X_DIR_IN(nRESET); |
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0:01f31e923fe2 | 419 | X_CLR(RESET_TXE); |
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0:01f31e923fe2 | 420 | gpio_reset_pin_is_input = __TRUE; |
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0:01f31e923fe2 | 421 | LPC_GPIO_PIN_INT->IST = 0x01; // ACK any pending edge interrupt |
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0:01f31e923fe2 | 422 | LPC_GPIO_PIN_INT->SIENF |= 0x1; // Enable falling edge interrupt |
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0:01f31e923fe2 | 423 | } else { |
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0:01f31e923fe2 | 424 | // issue a device hardware reset. (reset OUTPUT+LOW, reset oe HIGH=OUTPUT) |
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0:01f31e923fe2 | 425 | gpio_reset_pin_is_input = __FALSE; |
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0:01f31e923fe2 | 426 | LPC_GPIO_PIN_INT->CIENF |= 0x1; // Disable falling edge interrupt |
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0:01f31e923fe2 | 427 | LPC_GPIO_PIN_INT->IST = 0x01; // ACK any pending edge interrupt |
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0:01f31e923fe2 | 428 | X_SET(RESET_TXE); |
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0:01f31e923fe2 | 429 | X_CLR(nRESET); |
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0:01f31e923fe2 | 430 | X_DIR_OUT(nRESET); |
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0:01f31e923fe2 | 431 | } |
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0:01f31e923fe2 | 432 | } |
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0:01f31e923fe2 | 433 | |
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0:01f31e923fe2 | 434 | ///@} |
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0:01f31e923fe2 | 435 | |
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0:01f31e923fe2 | 436 | |
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0:01f31e923fe2 | 437 | //************************************************************************************************** |
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0:01f31e923fe2 | 438 | /** |
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0:01f31e923fe2 | 439 | \defgroup DAP_Config_LEDs_gr CMSIS-DAP Hardware Status LEDs |
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0:01f31e923fe2 | 440 | \ingroup DAP_ConfigIO_gr |
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0:01f31e923fe2 | 441 | @{ |
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0:01f31e923fe2 | 442 | |
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0:01f31e923fe2 | 443 | CMSIS-DAP Hardware may provide LEDs that indicate the status of the CMSIS-DAP Debug Unit. |
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0:01f31e923fe2 | 444 | |
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0:01f31e923fe2 | 445 | It is recommended to provide the following LEDs for status indication: |
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0:01f31e923fe2 | 446 | - Connect LED: is active when the DAP hardware is connected to a debugger. |
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0:01f31e923fe2 | 447 | - Running LED: is active when the debugger has put the target device into running state. |
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0:01f31e923fe2 | 448 | */ |
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0:01f31e923fe2 | 449 | |
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0:01f31e923fe2 | 450 | /** Debug Unit: Set status of Connected LED. |
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0:01f31e923fe2 | 451 | \param bit status of the Connect LED. |
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0:01f31e923fe2 | 452 | - 1: Connect LED ON: debugger is connected to CMSIS-DAP Debug Unit. |
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0:01f31e923fe2 | 453 | - 0: Connect LED OFF: debugger is not connected to CMSIS-DAP Debug Unit. |
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0:01f31e923fe2 | 454 | */ |
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0:01f31e923fe2 | 455 | __STATIC_INLINE void LED_CONNECTED_OUT(uint32_t bit) |
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0:01f31e923fe2 | 456 | { |
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0:01f31e923fe2 | 457 | } |
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0:01f31e923fe2 | 458 | |
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0:01f31e923fe2 | 459 | /** Debug Unit: Set status Target Running LED. |
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0:01f31e923fe2 | 460 | \param bit status of the Target Running LED. |
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0:01f31e923fe2 | 461 | - 1: Target Running LED ON: program execution in target started. |
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0:01f31e923fe2 | 462 | - 0: Target Running LED OFF: program execution in target stopped. |
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0:01f31e923fe2 | 463 | */ |
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0:01f31e923fe2 | 464 | __STATIC_INLINE void LED_RUNNING_OUT(uint32_t bit) |
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0:01f31e923fe2 | 465 | { |
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0:01f31e923fe2 | 466 | ; // Not available |
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0:01f31e923fe2 | 467 | } |
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0:01f31e923fe2 | 468 | |
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0:01f31e923fe2 | 469 | ///@} |
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0:01f31e923fe2 | 470 | |
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0:01f31e923fe2 | 471 | |
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0:01f31e923fe2 | 472 | //************************************************************************************************** |
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0:01f31e923fe2 | 473 | /** |
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0:01f31e923fe2 | 474 | \defgroup DAP_Config_Timestamp_gr CMSIS-DAP Timestamp |
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0:01f31e923fe2 | 475 | \ingroup DAP_ConfigIO_gr |
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0:01f31e923fe2 | 476 | @{ |
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0:01f31e923fe2 | 477 | Access function for Test Domain Timer. |
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0:01f31e923fe2 | 478 | |
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0:01f31e923fe2 | 479 | The value of the Test Domain Timer in the Debug Unit is returned by the function \ref TIMESTAMP_GET. By |
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0:01f31e923fe2 | 480 | default, the DWT timer is used. The frequency of this timer is configured with \ref TIMESTAMP_CLOCK. |
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0:01f31e923fe2 | 481 | |
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0:01f31e923fe2 | 482 | */ |
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0:01f31e923fe2 | 483 | |
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0:01f31e923fe2 | 484 | /** Get timestamp of Test Domain Timer. |
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0:01f31e923fe2 | 485 | \return Current timestamp value. |
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0:01f31e923fe2 | 486 | */ |
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0:01f31e923fe2 | 487 | __STATIC_INLINE uint32_t TIMESTAMP_GET (void) { |
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0:01f31e923fe2 | 488 | return (DWT->CYCCNT) / (CPU_CLOCK / TIMESTAMP_CLOCK); |
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0:01f31e923fe2 | 489 | } |
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0:01f31e923fe2 | 490 | |
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0:01f31e923fe2 | 491 | ///@} |
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0:01f31e923fe2 | 492 | |
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0:01f31e923fe2 | 493 | |
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0:01f31e923fe2 | 494 | //************************************************************************************************** |
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0:01f31e923fe2 | 495 | /** |
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0:01f31e923fe2 | 496 | \defgroup DAP_Config_Initialization_gr CMSIS-DAP Initialization |
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0:01f31e923fe2 | 497 | \ingroup DAP_ConfigIO_gr |
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0:01f31e923fe2 | 498 | @{ |
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0:01f31e923fe2 | 499 | |
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0:01f31e923fe2 | 500 | CMSIS-DAP Hardware I/O and LED Pins are initialized with the function \ref DAP_SETUP. |
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0:01f31e923fe2 | 501 | */ |
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0:01f31e923fe2 | 502 | |
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0:01f31e923fe2 | 503 | /** Setup of the Debug Unit I/O pins and LEDs (called when Debug Unit is initialized). |
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0:01f31e923fe2 | 504 | This function performs the initialization of the CMSIS-DAP Hardware I/O Pins and the |
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0:01f31e923fe2 | 505 | Status LEDs. In detail the operation of Hardware I/O and LED pins are enabled and set: |
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0:01f31e923fe2 | 506 | - I/O clock system enabled. |
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0:01f31e923fe2 | 507 | - all I/O pins: input buffer enabled, output pins are set to HighZ mode. |
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0:01f31e923fe2 | 508 | - for nTRST, nRESET a weak pull-up (if available) is enabled. |
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0:01f31e923fe2 | 509 | - LED output pins are enabled and LEDs are turned off. |
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0:01f31e923fe2 | 510 | */ |
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0:01f31e923fe2 | 511 | __STATIC_INLINE void DAP_SETUP(void) |
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0:01f31e923fe2 | 512 | { |
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0:01f31e923fe2 | 513 | /* Enable clock and init GPIO outputs */ |
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0:01f31e923fe2 | 514 | LPC_CCU1->CLK_M4_GPIO_CFG = CCU_CLK_CFG_AUTO | CCU_CLK_CFG_RUN; |
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0:01f31e923fe2 | 515 | |
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0:01f31e923fe2 | 516 | while (!(LPC_CCU1->CLK_M4_GPIO_STAT & CCU_CLK_STAT_RUN)); |
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0:01f31e923fe2 | 517 | |
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0:01f31e923fe2 | 518 | /* Configure I/O pins: function number, input buffer enabled, */ |
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0:01f31e923fe2 | 519 | /* no pull-up/down */ |
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0:01f31e923fe2 | 520 | scu_pinmux(1, 17, GPIO_NOPULL, FUNC0); /* SWCLK/TCK: GPIO0[12] */ |
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0:01f31e923fe2 | 521 | scu_pinmux(1, 6, GPIO_NOPULL, FUNC0); /* SWDIO/TMS: GPIO1[9] */ |
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0:01f31e923fe2 | 522 | scu_pinmux(1, 5, GPIO_NOPULL, FUNC0); /* SWDIO_OE: GPIO1[8] */ |
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0:01f31e923fe2 | 523 | } |
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0:01f31e923fe2 | 524 | |
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0:01f31e923fe2 | 525 | /** Reset Target Device with custom specific I/O pin or command sequence. |
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0:01f31e923fe2 | 526 | This function allows the optional implementation of a device specific reset sequence. |
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0:01f31e923fe2 | 527 | It is called when the command \ref DAP_ResetTarget and is for example required |
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0:01f31e923fe2 | 528 | when a device needs a time-critical unlock sequence that enables the debug port. |
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0:01f31e923fe2 | 529 | \return 0 = no device specific reset sequence is implemented.\n |
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0:01f31e923fe2 | 530 | 1 = a device specific reset sequence is implemented. |
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0:01f31e923fe2 | 531 | */ |
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0:01f31e923fe2 | 532 | __STATIC_INLINE uint32_t RESET_TARGET(void) |
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0:01f31e923fe2 | 533 | { |
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0:01f31e923fe2 | 534 | return (0); // change to '1' when a device reset sequence is implemented |
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0:01f31e923fe2 | 535 | } |
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0:01f31e923fe2 | 536 | |
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0:01f31e923fe2 | 537 | ///@} |
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0:01f31e923fe2 | 538 | |
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0:01f31e923fe2 | 539 | |
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0:01f31e923fe2 | 540 | #endif /* __DAP_CONFIG_H__ */ |