Arrow / Mbed OS DAPLink Reset

Repostiory containing DAPLink source code with Reset Pin workaround for HANI_IOT board.

Upstream: https://github.com/ARMmbed/DAPLink

source/hic_hal/maxim/max32620/system_max32620.c@0:01f31e923fe2, 2020-04-07 (annotated)

Committer:
Pawel Zarembski
Date:
Tue Apr 07 12:55:42 2020 +0200
Revision:
0:01f31e923fe2
hani: DAPLink with reset workaround

Who changed what in which revision?

UserRevisionLine numberNew contents of line
Pawel Zarembski 0:01f31e923fe2 1 /*******************************************************************************
Pawel Zarembski 0:01f31e923fe2 2 * Copyright (C) 2017 Maxim Integrated Products, Inc., All Rights Reserved.
Pawel Zarembski 0:01f31e923fe2 3 *
Pawel Zarembski 0:01f31e923fe2 4 * Permission is hereby granted, free of charge, to any person obtaining a
Pawel Zarembski 0:01f31e923fe2 5 * copy of this software and associated documentation files (the "Software"),
Pawel Zarembski 0:01f31e923fe2 6 * to deal in the Software without restriction, including without limitation
Pawel Zarembski 0:01f31e923fe2 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
Pawel Zarembski 0:01f31e923fe2 8 * and/or sell copies of the Software, and to permit persons to whom the
Pawel Zarembski 0:01f31e923fe2 9 * Software is furnished to do so, subject to the following conditions:
Pawel Zarembski 0:01f31e923fe2 10 *
Pawel Zarembski 0:01f31e923fe2 11 * The above copyright notice and this permission notice shall be included
Pawel Zarembski 0:01f31e923fe2 12 * in all copies or substantial portions of the Software.
Pawel Zarembski 0:01f31e923fe2 13 *
Pawel Zarembski 0:01f31e923fe2 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
Pawel Zarembski 0:01f31e923fe2 15 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
Pawel Zarembski 0:01f31e923fe2 16 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
Pawel Zarembski 0:01f31e923fe2 17 * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
Pawel Zarembski 0:01f31e923fe2 18 * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
Pawel Zarembski 0:01f31e923fe2 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
Pawel Zarembski 0:01f31e923fe2 20 * OTHER DEALINGS IN THE SOFTWARE.
Pawel Zarembski 0:01f31e923fe2 21 *
Pawel Zarembski 0:01f31e923fe2 22 * Except as contained in this notice, the name of Maxim Integrated
Pawel Zarembski 0:01f31e923fe2 23 * Products, Inc. shall not be used except as stated in the Maxim Integrated
Pawel Zarembski 0:01f31e923fe2 24 * Products, Inc. Branding Policy.
Pawel Zarembski 0:01f31e923fe2 25 *
Pawel Zarembski 0:01f31e923fe2 26 * The mere transfer of this software does not imply any licenses
Pawel Zarembski 0:01f31e923fe2 27 * of trade secrets, proprietary technology, copyrights, patents,
Pawel Zarembski 0:01f31e923fe2 28 * trademarks, maskwork rights, or any other form of intellectual
Pawel Zarembski 0:01f31e923fe2 29 * property whatsoever. Maxim Integrated Products, Inc. retains all
Pawel Zarembski 0:01f31e923fe2 30 * ownership rights.
Pawel Zarembski 0:01f31e923fe2 31 *
Pawel Zarembski 0:01f31e923fe2 32 ******************************************************************************/
Pawel Zarembski 0:01f31e923fe2 33
Pawel Zarembski 0:01f31e923fe2 34 #include <string.h>
Pawel Zarembski 0:01f31e923fe2 35 #include <stdio.h>
Pawel Zarembski 0:01f31e923fe2 36 #include <stdlib.h>
Pawel Zarembski 0:01f31e923fe2 37 #include "max32620.h"
Pawel Zarembski 0:01f31e923fe2 38 #include "clkman_regs.h"
Pawel Zarembski 0:01f31e923fe2 39 #include "adc_regs.h"
Pawel Zarembski 0:01f31e923fe2 40 #include "pwrseq_regs.h"
Pawel Zarembski 0:01f31e923fe2 41 #include "pwrman_regs.h"
Pawel Zarembski 0:01f31e923fe2 42 #include "icc_regs.h"
Pawel Zarembski 0:01f31e923fe2 43 #include "flc_regs.h"
Pawel Zarembski 0:01f31e923fe2 44 #include "rtc_regs.h"
Pawel Zarembski 0:01f31e923fe2 45 #include "trim_regs.h"
Pawel Zarembski 0:01f31e923fe2 46
Pawel Zarembski 0:01f31e923fe2 47 #ifndef RO_FREQ
Pawel Zarembski 0:01f31e923fe2 48 #define RO_FREQ 96000000
Pawel Zarembski 0:01f31e923fe2 49 #endif
Pawel Zarembski 0:01f31e923fe2 50
Pawel Zarembski 0:01f31e923fe2 51 #ifndef LP0_POST_HOOK
Pawel Zarembski 0:01f31e923fe2 52 #define LP0_POST_HOOK
Pawel Zarembski 0:01f31e923fe2 53 #endif
Pawel Zarembski 0:01f31e923fe2 54
Pawel Zarembski 0:01f31e923fe2 55 extern void (* const __isr_vector[])(void);
Pawel Zarembski 0:01f31e923fe2 56 /*
Pawel Zarembski 0:01f31e923fe2 57 * Note: When compiling on ARM Keil Toolchain only.
Pawel Zarembski 0:01f31e923fe2 58 * If the SystemCoreClock is left uninitialized, post Scatter load
Pawel Zarembski 0:01f31e923fe2 59 * the clock will default to system reset value(48MHz)
Pawel Zarembski 0:01f31e923fe2 60 */
Pawel Zarembski 0:01f31e923fe2 61 uint32_t SystemCoreClock = RO_FREQ;
Pawel Zarembski 0:01f31e923fe2 62
Pawel Zarembski 0:01f31e923fe2 63 void SystemCoreClockUpdate(void)
Pawel Zarembski 0:01f31e923fe2 64 {
Pawel Zarembski 0:01f31e923fe2 65 if(MXC_PWRSEQ->reg0 & MXC_F_PWRSEQ_REG0_PWR_RCEN_RUN) {
Pawel Zarembski 0:01f31e923fe2 66 /* 4 MHz source */
Pawel Zarembski 0:01f31e923fe2 67 if(MXC_PWRSEQ->reg3 & MXC_F_PWRSEQ_REG3_PWR_RC_DIV) {
Pawel Zarembski 0:01f31e923fe2 68 SystemCoreClock = (4000000 / (0x1 << ((MXC_PWRSEQ->reg3 & MXC_F_PWRSEQ_REG3_PWR_RC_DIV) >>
Pawel Zarembski 0:01f31e923fe2 69 MXC_F_PWRSEQ_REG3_PWR_RC_DIV_POS)));
Pawel Zarembski 0:01f31e923fe2 70 } else {
Pawel Zarembski 0:01f31e923fe2 71 SystemCoreClock = 4000000;
Pawel Zarembski 0:01f31e923fe2 72 }
Pawel Zarembski 0:01f31e923fe2 73 } else {
Pawel Zarembski 0:01f31e923fe2 74 /* 96 MHz source */
Pawel Zarembski 0:01f31e923fe2 75 if(MXC_PWRSEQ->reg3 & MXC_F_PWRSEQ_REG3_PWR_RO_DIV) {
Pawel Zarembski 0:01f31e923fe2 76 SystemCoreClock = (RO_FREQ / (0x1 << ((MXC_PWRSEQ->reg3 & MXC_F_PWRSEQ_REG3_PWR_RO_DIV) >>
Pawel Zarembski 0:01f31e923fe2 77 MXC_F_PWRSEQ_REG3_PWR_RO_DIV_POS)));
Pawel Zarembski 0:01f31e923fe2 78 } else {
Pawel Zarembski 0:01f31e923fe2 79 SystemCoreClock = RO_FREQ;
Pawel Zarembski 0:01f31e923fe2 80 }
Pawel Zarembski 0:01f31e923fe2 81 }
Pawel Zarembski 0:01f31e923fe2 82 }
Pawel Zarembski 0:01f31e923fe2 83
Pawel Zarembski 0:01f31e923fe2 84 void CLKMAN_TrimRO(void)
Pawel Zarembski 0:01f31e923fe2 85 {
Pawel Zarembski 0:01f31e923fe2 86 uint32_t running;
Pawel Zarembski 0:01f31e923fe2 87 uint32_t trim;
Pawel Zarembski 0:01f31e923fe2 88
Pawel Zarembski 0:01f31e923fe2 89 /* Step 1: enable 32KHz RTC */
Pawel Zarembski 0:01f31e923fe2 90 running = MXC_PWRSEQ->reg0 & MXC_F_PWRSEQ_REG0_PWR_RTCEN_RUN;
Pawel Zarembski 0:01f31e923fe2 91 MXC_PWRSEQ->reg0 |= MXC_F_PWRSEQ_REG0_PWR_RTCEN_RUN;
Pawel Zarembski 0:01f31e923fe2 92
Pawel Zarembski 0:01f31e923fe2 93 /* Wait for RTC warm-up */
Pawel Zarembski 0:01f31e923fe2 94 while(MXC_RTCCFG->osc_ctrl & MXC_F_RTC_OSC_CTRL_OSC_WARMUP_ENABLE) {}
Pawel Zarembski 0:01f31e923fe2 95
Pawel Zarembski 0:01f31e923fe2 96 /* Step 2: enable RO calibration complete interrupt */
Pawel Zarembski 0:01f31e923fe2 97 MXC_ADC->intr |= MXC_F_ADC_INTR_RO_CAL_DONE_IE;
Pawel Zarembski 0:01f31e923fe2 98
Pawel Zarembski 0:01f31e923fe2 99 /* Step 3: clear RO calibration complete interrupt */
Pawel Zarembski 0:01f31e923fe2 100 MXC_ADC->intr |= MXC_F_ADC_INTR_RO_CAL_DONE_IF;
Pawel Zarembski 0:01f31e923fe2 101
Pawel Zarembski 0:01f31e923fe2 102 /* Step 4: -- NO LONGER NEEDED / HANDLED BY STARTUP CODE -- */
Pawel Zarembski 0:01f31e923fe2 103
Pawel Zarembski 0:01f31e923fe2 104 /* Step 5: write initial trim to frequency calibration initial condition register */
Pawel Zarembski 0:01f31e923fe2 105 trim = (MXC_PWRSEQ->reg6 & MXC_F_PWRSEQ_REG6_PWR_TRIM_OSC_VREF) >> MXC_F_PWRSEQ_REG6_PWR_TRIM_OSC_VREF_POS;
Pawel Zarembski 0:01f31e923fe2 106 MXC_ADC->ro_cal1 = (MXC_ADC->ro_cal1 & ~MXC_F_ADC_RO_CAL1_TRM_INIT) |
Pawel Zarembski 0:01f31e923fe2 107 ((trim << MXC_F_ADC_RO_CAL1_TRM_INIT_POS) & MXC_F_ADC_RO_CAL1_TRM_INIT);
Pawel Zarembski 0:01f31e923fe2 108
Pawel Zarembski 0:01f31e923fe2 109 /* Step 6: load initial trim to active frequency trim register */
Pawel Zarembski 0:01f31e923fe2 110 MXC_ADC->ro_cal0 |= MXC_F_ADC_RO_CAL0_RO_CAL_LOAD;
Pawel Zarembski 0:01f31e923fe2 111
Pawel Zarembski 0:01f31e923fe2 112 /* Step 7: enable frequency loop to control RO trim */
Pawel Zarembski 0:01f31e923fe2 113 MXC_ADC->ro_cal0 |= MXC_F_ADC_RO_CAL0_RO_CAL_EN;
Pawel Zarembski 0:01f31e923fe2 114
Pawel Zarembski 0:01f31e923fe2 115 /* Step 8: run frequency calibration in atomic mode */
Pawel Zarembski 0:01f31e923fe2 116 MXC_ADC->ro_cal0 |= MXC_F_ADC_RO_CAL0_RO_CAL_ATOMIC;
Pawel Zarembski 0:01f31e923fe2 117
Pawel Zarembski 0:01f31e923fe2 118 /* Step 9: waiting for ro_cal_done flag */
Pawel Zarembski 0:01f31e923fe2 119 while(!(MXC_ADC->intr & MXC_F_ADC_INTR_RO_CAL_DONE_IF));
Pawel Zarembski 0:01f31e923fe2 120
Pawel Zarembski 0:01f31e923fe2 121 /* Step 10: stop frequency calibration */
Pawel Zarembski 0:01f31e923fe2 122 MXC_ADC->ro_cal0 &= ~MXC_F_ADC_RO_CAL0_RO_CAL_RUN;
Pawel Zarembski 0:01f31e923fe2 123
Pawel Zarembski 0:01f31e923fe2 124 /* Step 11: disable RO calibration complete interrupt */
Pawel Zarembski 0:01f31e923fe2 125 MXC_ADC->intr &= ~MXC_F_ADC_INTR_RO_CAL_DONE_IE;
Pawel Zarembski 0:01f31e923fe2 126
Pawel Zarembski 0:01f31e923fe2 127 /* Step 12: read final frequency trim value */
Pawel Zarembski 0:01f31e923fe2 128 trim = (MXC_ADC->ro_cal0 & MXC_F_ADC_RO_CAL0_RO_TRM) >> MXC_F_ADC_RO_CAL0_RO_TRM_POS;
Pawel Zarembski 0:01f31e923fe2 129
Pawel Zarembski 0:01f31e923fe2 130 /* Step 13: write final trim to RO flash trim shadow register */
Pawel Zarembski 0:01f31e923fe2 131 MXC_PWRSEQ->reg6 = (MXC_PWRSEQ->reg6 & ~MXC_F_PWRSEQ_REG6_PWR_TRIM_OSC_VREF) |
Pawel Zarembski 0:01f31e923fe2 132 ((trim << MXC_F_PWRSEQ_REG6_PWR_TRIM_OSC_VREF_POS) & MXC_F_PWRSEQ_REG6_PWR_TRIM_OSC_VREF);
Pawel Zarembski 0:01f31e923fe2 133
Pawel Zarembski 0:01f31e923fe2 134 /* Step 14: restore RTC status */
Pawel Zarembski 0:01f31e923fe2 135 if (!running) {
Pawel Zarembski 0:01f31e923fe2 136 MXC_PWRSEQ->reg0 &= ~MXC_F_PWRSEQ_REG0_PWR_RTCEN_RUN;
Pawel Zarembski 0:01f31e923fe2 137 }
Pawel Zarembski 0:01f31e923fe2 138
Pawel Zarembski 0:01f31e923fe2 139 /* Step 15: disable frequency loop to control RO trim */
Pawel Zarembski 0:01f31e923fe2 140 MXC_ADC->ro_cal0 &= ~MXC_F_ADC_RO_CAL0_RO_CAL_EN;
Pawel Zarembski 0:01f31e923fe2 141 }
Pawel Zarembski 0:01f31e923fe2 142
Pawel Zarembski 0:01f31e923fe2 143 static void ICC_Enable(void)
Pawel Zarembski 0:01f31e923fe2 144 {
Pawel Zarembski 0:01f31e923fe2 145 /* Invalidate cache and wait until ready */
Pawel Zarembski 0:01f31e923fe2 146 MXC_ICC->invdt_all = 1;
Pawel Zarembski 0:01f31e923fe2 147 while (!(MXC_ICC->ctrl_stat & MXC_F_ICC_CTRL_STAT_READY));
Pawel Zarembski 0:01f31e923fe2 148
Pawel Zarembski 0:01f31e923fe2 149 /* Enable cache */
Pawel Zarembski 0:01f31e923fe2 150 MXC_ICC->ctrl_stat |= MXC_F_ICC_CTRL_STAT_ENABLE;
Pawel Zarembski 0:01f31e923fe2 151
Pawel Zarembski 0:01f31e923fe2 152 /* Must invalidate a second time for proper use */
Pawel Zarembski 0:01f31e923fe2 153 MXC_ICC->invdt_all = 1;
Pawel Zarembski 0:01f31e923fe2 154 }
Pawel Zarembski 0:01f31e923fe2 155
Pawel Zarembski 0:01f31e923fe2 156 /* This function is called before C runtime initialization and can be
Pawel Zarembski 0:01f31e923fe2 157 * implemented by the application for early initializations. If a value other
Pawel Zarembski 0:01f31e923fe2 158 * than '0' is returned, the C runtime initialization will be skipped.
Pawel Zarembski 0:01f31e923fe2 159 *
Pawel Zarembski 0:01f31e923fe2 160 * You may over-ride this function in your program by defining a custom
Pawel Zarembski 0:01f31e923fe2 161 * PreInit(), but care should be taken to reproduce the initilization steps
Pawel Zarembski 0:01f31e923fe2 162 * or a non-functional system may result.
Pawel Zarembski 0:01f31e923fe2 163 */
Pawel Zarembski 0:01f31e923fe2 164 __weak int PreInit(void)
Pawel Zarembski 0:01f31e923fe2 165 {
Pawel Zarembski 0:01f31e923fe2 166 /* Increase system clock to 96 MHz */
Pawel Zarembski 0:01f31e923fe2 167 MXC_CLKMAN->clk_ctrl = MXC_V_CLKMAN_CLK_CTRL_SYSTEM_SOURCE_SELECT_96MHZ_RO;
Pawel Zarembski 0:01f31e923fe2 168
Pawel Zarembski 0:01f31e923fe2 169 /* Performance-measurement hook, may be defined as nothing */
Pawel Zarembski 0:01f31e923fe2 170 LP0_POST_HOOK;
Pawel Zarembski 0:01f31e923fe2 171
Pawel Zarembski 0:01f31e923fe2 172 /* Enable cache here to reduce boot time */
Pawel Zarembski 0:01f31e923fe2 173 ICC_Enable();
Pawel Zarembski 0:01f31e923fe2 174
Pawel Zarembski 0:01f31e923fe2 175 return 0;
Pawel Zarembski 0:01f31e923fe2 176 }
Pawel Zarembski 0:01f31e923fe2 177
Pawel Zarembski 0:01f31e923fe2 178 /*
Pawel Zarembski 0:01f31e923fe2 179 * Note: When compiling on ARM Keil Toolchain only.
Pawel Zarembski 0:01f31e923fe2 180 * If the SystemCoreClock is modified in this function, post Scatter load
Pawel Zarembski 0:01f31e923fe2 181 * the clock will default to system reset value(48MHz)
Pawel Zarembski 0:01f31e923fe2 182 */
Pawel Zarembski 0:01f31e923fe2 183 /* This function can be implemented by the application to initialize the board */
Pawel Zarembski 0:01f31e923fe2 184 __weak int Board_Init(void)
Pawel Zarembski 0:01f31e923fe2 185 {
Pawel Zarembski 0:01f31e923fe2 186 /* Do nothing */
Pawel Zarembski 0:01f31e923fe2 187 return 0;
Pawel Zarembski 0:01f31e923fe2 188 }
Pawel Zarembski 0:01f31e923fe2 189
Pawel Zarembski 0:01f31e923fe2 190 /* This function is called just before control is transferred to main().
Pawel Zarembski 0:01f31e923fe2 191 *
Pawel Zarembski 0:01f31e923fe2 192 * You may over-ride this function in your program by defining a custom
Pawel Zarembski 0:01f31e923fe2 193 * SystemInit(), but care should be taken to reproduce the initialization
Pawel Zarembski 0:01f31e923fe2 194 * steps or a non-functional system may result.
Pawel Zarembski 0:01f31e923fe2 195 */
Pawel Zarembski 0:01f31e923fe2 196 __weak void SystemInit(void)
Pawel Zarembski 0:01f31e923fe2 197 {
Pawel Zarembski 0:01f31e923fe2 198 /* Configure the interrupt controller to use the application vector table in */
Pawel Zarembski 0:01f31e923fe2 199 /* the application space */
Pawel Zarembski 0:01f31e923fe2 200 #if defined ( __GNUC__)
Pawel Zarembski 0:01f31e923fe2 201 /* IAR sets the VTOR pointer prior to SystemInit and causes stack corruption to change it here. */
Pawel Zarembski 0:01f31e923fe2 202 __disable_irq(); /* Disable interrupts */
Pawel Zarembski 0:01f31e923fe2 203 // SCB->VTOR = (uint32_t)__isr_vector; /* set the Vector Table to point at our ISR table */
Pawel Zarembski 0:01f31e923fe2 204 __DSB(); /* bus sync */
Pawel Zarembski 0:01f31e923fe2 205 __enable_irq(); /* enable interrupts */
Pawel Zarembski 0:01f31e923fe2 206 #endif /* __GNUC__ */
Pawel Zarembski 0:01f31e923fe2 207
Pawel Zarembski 0:01f31e923fe2 208 /* Copy trim information from shadow registers into power manager registers */
Pawel Zarembski 0:01f31e923fe2 209 /* NOTE: Checks have been added to prevent bad/missing trim values from being loaded */
Pawel Zarembski 0:01f31e923fe2 210 if ((MXC_FLC->ctrl & MXC_F_FLC_CTRL_INFO_BLOCK_VALID) &&
Pawel Zarembski 0:01f31e923fe2 211 (MXC_TRIM->for_pwr_reg5 != 0xffffffff) &&
Pawel Zarembski 0:01f31e923fe2 212 (MXC_TRIM->for_pwr_reg6 != 0xffffffff)) {
Pawel Zarembski 0:01f31e923fe2 213 MXC_PWRSEQ->reg5 = MXC_TRIM->for_pwr_reg5;
Pawel Zarembski 0:01f31e923fe2 214 MXC_PWRSEQ->reg6 = MXC_TRIM->for_pwr_reg6;
Pawel Zarembski 0:01f31e923fe2 215 } else {
Pawel Zarembski 0:01f31e923fe2 216 /* No valid info block, use some reasonable defaults */
Pawel Zarembski 0:01f31e923fe2 217 MXC_PWRSEQ->reg6 &= ~MXC_F_PWRSEQ_REG6_PWR_TRIM_OSC_VREF;
Pawel Zarembski 0:01f31e923fe2 218 MXC_PWRSEQ->reg6 |= (0x1e0 << MXC_F_PWRSEQ_REG6_PWR_TRIM_OSC_VREF_POS);
Pawel Zarembski 0:01f31e923fe2 219 }
Pawel Zarembski 0:01f31e923fe2 220
Pawel Zarembski 0:01f31e923fe2 221 /* Improve flash access timing */
Pawel Zarembski 0:01f31e923fe2 222 MXC_FLC->perform |= (/*MXC_F_FLC_PERFORM_EN_BACK2BACK_RDS | */
Pawel Zarembski 0:01f31e923fe2 223 MXC_F_FLC_PERFORM_EN_MERGE_GRAB_GNT |
Pawel Zarembski 0:01f31e923fe2 224 MXC_F_FLC_PERFORM_AUTO_TACC |
Pawel Zarembski 0:01f31e923fe2 225 MXC_F_FLC_PERFORM_AUTO_CLKDIV);
Pawel Zarembski 0:01f31e923fe2 226
Pawel Zarembski 0:01f31e923fe2 227 /* First, eliminate the unnecessary RTC handshake between clock domains. Must be set as a pair. */
Pawel Zarembski 0:01f31e923fe2 228 MXC_RTCTMR->ctrl |= (MXC_F_RTC_CTRL_USE_ASYNC_FLAGS |
Pawel Zarembski 0:01f31e923fe2 229 MXC_F_RTC_CTRL_AGGRESSIVE_RST);
Pawel Zarembski 0:01f31e923fe2 230 /* Enable fast read of the RTC timer value, and fast write of all other RTC registers */
Pawel Zarembski 0:01f31e923fe2 231 MXC_PWRSEQ->rtc_ctrl2 |= (MXC_F_PWRSEQ_RTC_CTRL2_TIMER_AUTO_UPDATE |
Pawel Zarembski 0:01f31e923fe2 232 MXC_F_PWRSEQ_RTC_CTRL2_TIMER_ASYNC_WR);
Pawel Zarembski 0:01f31e923fe2 233 MXC_PWRSEQ->rtc_ctrl2 &= ~(MXC_F_PWRSEQ_RTC_CTRL2_TIMER_ASYNC_RD);
Pawel Zarembski 0:01f31e923fe2 234
Pawel Zarembski 0:01f31e923fe2 235 /* Clear the GPIO WUD event if not waking up from LP0 */
Pawel Zarembski 0:01f31e923fe2 236 /* this is necessary because WUD flops come up in undetermined state out of POR or SRST*/
Pawel Zarembski 0:01f31e923fe2 237 if(MXC_PWRSEQ->reg0 & MXC_F_PWRSEQ_REG0_PWR_FIRST_BOOT ||
Pawel Zarembski 0:01f31e923fe2 238 !(MXC_PWRMAN->pwr_rst_ctrl & MXC_F_PWRMAN_PWR_RST_CTRL_POR)) {
Pawel Zarembski 0:01f31e923fe2 239 /* Clear GPIO WUD event and configuration registers, globally */
Pawel Zarembski 0:01f31e923fe2 240 MXC_PWRSEQ->reg1 |= (MXC_F_PWRSEQ_REG1_PWR_CLR_IO_EVENT_LATCH |
Pawel Zarembski 0:01f31e923fe2 241 MXC_F_PWRSEQ_REG1_PWR_CLR_IO_CFG_LATCH);
Pawel Zarembski 0:01f31e923fe2 242 MXC_PWRSEQ->reg1 &= ~(MXC_F_PWRSEQ_REG1_PWR_CLR_IO_EVENT_LATCH |
Pawel Zarembski 0:01f31e923fe2 243 MXC_F_PWRSEQ_REG1_PWR_CLR_IO_CFG_LATCH);
Pawel Zarembski 0:01f31e923fe2 244 } else {
Pawel Zarembski 0:01f31e923fe2 245 /* Unfreeze the GPIO by clearing MBUS_GATE, when returning from LP0 */
Pawel Zarembski 0:01f31e923fe2 246 MXC_PWRSEQ->reg1 &= ~(MXC_F_PWRSEQ_REG1_PWR_MBUS_GATE);
Pawel Zarembski 0:01f31e923fe2 247 /* LP0 wake-up: Turn off special switch to eliminate ~50nA of leakage on VDD12 */
Pawel Zarembski 0:01f31e923fe2 248 MXC_PWRSEQ->reg1 &= ~MXC_F_PWRSEQ_REG1_PWR_SRAM_NWELL_SW;
Pawel Zarembski 0:01f31e923fe2 249 }
Pawel Zarembski 0:01f31e923fe2 250
Pawel Zarembski 0:01f31e923fe2 251 /* Turn on retention regulator */
Pawel Zarembski 0:01f31e923fe2 252 MXC_PWRSEQ->reg0 |= (MXC_F_PWRSEQ_REG0_PWR_RETREGEN_RUN |
Pawel Zarembski 0:01f31e923fe2 253 MXC_F_PWRSEQ_REG0_PWR_RETREGEN_SLP);
Pawel Zarembski 0:01f31e923fe2 254
Pawel Zarembski 0:01f31e923fe2 255 /* Turn on Auto GPIO Freeze/UnFreeze in sleep modes */
Pawel Zarembski 0:01f31e923fe2 256 MXC_PWRSEQ->reg1 |= MXC_F_PWRSEQ_REG1_PWR_AUTO_MBUS_GATE;
Pawel Zarembski 0:01f31e923fe2 257
Pawel Zarembski 0:01f31e923fe2 258 /* Adjust settings in the retention controller for fastest wake-up time */
Pawel Zarembski 0:01f31e923fe2 259 MXC_PWRSEQ->retn_ctrl0 |= (MXC_F_PWRSEQ_RETN_CTRL0_RC_REL_CCG_EARLY |
Pawel Zarembski 0:01f31e923fe2 260 MXC_F_PWRSEQ_RETN_CTRL0_RC_POLL_FLASH);
Pawel Zarembski 0:01f31e923fe2 261 MXC_PWRSEQ->retn_ctrl0 &= ~(MXC_F_PWRSEQ_RETN_CTRL0_RC_USE_FLC_TWK);
Pawel Zarembski 0:01f31e923fe2 262
Pawel Zarembski 0:01f31e923fe2 263
Pawel Zarembski 0:01f31e923fe2 264 /* Set retention controller TWake cycle count to 1us to minimize the wake-up time */
Pawel Zarembski 0:01f31e923fe2 265 /* NOTE: flash polling (...PWRSEQ_RETN_CTRL0_RC_POLL_FLASH) must be enabled before changing POR default! */
Pawel Zarembski 0:01f31e923fe2 266 MXC_PWRSEQ->retn_ctrl1 = (MXC_PWRSEQ->retn_ctrl1 & ~MXC_F_PWRSEQ_RETN_CTRL1_RC_TWK) |
Pawel Zarembski 0:01f31e923fe2 267 (1 << MXC_F_PWRSEQ_RETN_CTRL1_RC_TWK_POS);
Pawel Zarembski 0:01f31e923fe2 268
Pawel Zarembski 0:01f31e923fe2 269 /* Improve wake-up time by changing ROSEL to 140ns */
Pawel Zarembski 0:01f31e923fe2 270 MXC_PWRSEQ->reg3 = (1 << MXC_F_PWRSEQ_REG3_PWR_ROSEL_POS) |
Pawel Zarembski 0:01f31e923fe2 271 (1 << MXC_F_PWRSEQ_REG3_PWR_FAILSEL_POS) |
Pawel Zarembski 0:01f31e923fe2 272 (MXC_PWRSEQ->reg3 & ~(MXC_F_PWRSEQ_REG3_PWR_ROSEL |
Pawel Zarembski 0:01f31e923fe2 273 MXC_F_PWRSEQ_REG3_PWR_FLTRROSEL));
Pawel Zarembski 0:01f31e923fe2 274
Pawel Zarembski 0:01f31e923fe2 275 /* Enable RTOS Mode: Enable 32kHz clock synchronizer to SysTick external clock input */
Pawel Zarembski 0:01f31e923fe2 276 MXC_CLKMAN->clk_ctrl |= MXC_F_CLKMAN_CLK_CTRL_RTOS_MODE;
Pawel Zarembski 0:01f31e923fe2 277
Pawel Zarembski 0:01f31e923fe2 278 /* Set this so all bits of PWR_MSK_FLAGS are active low to mask the corresponding flags */
Pawel Zarembski 0:01f31e923fe2 279 MXC_PWRSEQ->pwr_misc |= MXC_F_PWRSEQ_PWR_MISC_INVERT_4_MASK_BITS;
Pawel Zarembski 0:01f31e923fe2 280
Pawel Zarembski 0:01f31e923fe2 281 /* Clear this bit to get the latest PT */
Pawel Zarembski 0:01f31e923fe2 282 MXC_PWRMAN->pt_regmap_ctrl &= ~MXC_F_PWRMAN_PT_REGMAP_CTRL_ME02A_MODE;
Pawel Zarembski 0:01f31e923fe2 283
Pawel Zarembski 0:01f31e923fe2 284 /* Enable FPU on Cortex-M4, which occupies coprocessor slots 10 & 11 */
Pawel Zarembski 0:01f31e923fe2 285 /* Grant full access, per "Table B3-24 CPACR bit assignments". */
Pawel Zarembski 0:01f31e923fe2 286 /* DDI0403D "ARMv7-M Architecture Reference Manual" */
Pawel Zarembski 0:01f31e923fe2 287 SCB->CPACR |= SCB_CPACR_CP10_Msk | SCB_CPACR_CP11_Msk;
Pawel Zarembski 0:01f31e923fe2 288 __DSB();
Pawel Zarembski 0:01f31e923fe2 289 __ISB();
Pawel Zarembski 0:01f31e923fe2 290
Pawel Zarembski 0:01f31e923fe2 291 /* Perform an initial trim of the internal ring oscillator */
Pawel Zarembski 0:01f31e923fe2 292 CLKMAN_TrimRO();
Pawel Zarembski 0:01f31e923fe2 293
Pawel Zarembski 0:01f31e923fe2 294 SystemCoreClockUpdate();
Pawel Zarembski 0:01f31e923fe2 295 Board_Init();
Pawel Zarembski 0:01f31e923fe2 296 }