Arrow / Mbed OS DAPLink Reset

Repostiory containing DAPLink source code with Reset Pin workaround for HANI_IOT board.

Upstream: https://github.com/ARMmbed/DAPLink

source/hic_hal/freescale/k26f/gpio.c@0:01f31e923fe2, 2020-04-07 (annotated)

Committer:
Pawel Zarembski
Date:
Tue Apr 07 12:55:42 2020 +0200
Revision:
0:01f31e923fe2
hani: DAPLink with reset workaround

Who changed what in which revision?

UserRevisionLine numberNew contents of line
Pawel Zarembski 0:01f31e923fe2 1 /**
Pawel Zarembski 0:01f31e923fe2 2 * @file gpio.c
Pawel Zarembski 0:01f31e923fe2 3 * @brief
Pawel Zarembski 0:01f31e923fe2 4 *
Pawel Zarembski 0:01f31e923fe2 5 * DAPLink Interface Firmware
Pawel Zarembski 0:01f31e923fe2 6 * Copyright (c) 2009-2016, ARM Limited, All Rights Reserved
Pawel Zarembski 0:01f31e923fe2 7 * Copyright (c) 2016-2017 NXP
Pawel Zarembski 0:01f31e923fe2 8 * SPDX-License-Identifier: Apache-2.0
Pawel Zarembski 0:01f31e923fe2 9 *
Pawel Zarembski 0:01f31e923fe2 10 * Licensed under the Apache License, Version 2.0 (the "License"); you may
Pawel Zarembski 0:01f31e923fe2 11 * not use this file except in compliance with the License.
Pawel Zarembski 0:01f31e923fe2 12 * You may obtain a copy of the License at
Pawel Zarembski 0:01f31e923fe2 13 *
Pawel Zarembski 0:01f31e923fe2 14 * http://www.apache.org/licenses/LICENSE-2.0
Pawel Zarembski 0:01f31e923fe2 15 *
Pawel Zarembski 0:01f31e923fe2 16 * Unless required by applicable law or agreed to in writing, software
Pawel Zarembski 0:01f31e923fe2 17 * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
Pawel Zarembski 0:01f31e923fe2 18 * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
Pawel Zarembski 0:01f31e923fe2 19 * See the License for the specific language governing permissions and
Pawel Zarembski 0:01f31e923fe2 20 * limitations under the License.
Pawel Zarembski 0:01f31e923fe2 21 */
Pawel Zarembski 0:01f31e923fe2 22
Pawel Zarembski 0:01f31e923fe2 23 #include "fsl_device_registers.h"
Pawel Zarembski 0:01f31e923fe2 24 #include "DAP_config.h"
Pawel Zarembski 0:01f31e923fe2 25 #include "gpio.h"
Pawel Zarembski 0:01f31e923fe2 26 #include "daplink.h"
Pawel Zarembski 0:01f31e923fe2 27 #include "hic_init.h"
Pawel Zarembski 0:01f31e923fe2 28 #include "fsl_clock.h"
Pawel Zarembski 0:01f31e923fe2 29
Pawel Zarembski 0:01f31e923fe2 30 static void busy_wait(uint32_t cycles)
Pawel Zarembski 0:01f31e923fe2 31 {
Pawel Zarembski 0:01f31e923fe2 32 volatile uint32_t i = cycles;
Pawel Zarembski 0:01f31e923fe2 33 while (i > 0) {
Pawel Zarembski 0:01f31e923fe2 34 i--;
Pawel Zarembski 0:01f31e923fe2 35 }
Pawel Zarembski 0:01f31e923fe2 36 }
Pawel Zarembski 0:01f31e923fe2 37
Pawel Zarembski 0:01f31e923fe2 38 void gpio_init(void)
Pawel Zarembski 0:01f31e923fe2 39 {
Pawel Zarembski 0:01f31e923fe2 40 // Enable hardfault on unaligned access for the interface only.
Pawel Zarembski 0:01f31e923fe2 41 // If this is done in the bootloader than then it might (will) break
Pawel Zarembski 0:01f31e923fe2 42 // older application firmware or firmware from 3rd party vendors.
Pawel Zarembski 0:01f31e923fe2 43 #if defined(DAPLINK_IF)
Pawel Zarembski 0:01f31e923fe2 44 SCB->CCR |= SCB_CCR_UNALIGN_TRP_Msk;
Pawel Zarembski 0:01f31e923fe2 45 #endif
Pawel Zarembski 0:01f31e923fe2 46 // enable clock to ports
Pawel Zarembski 0:01f31e923fe2 47 SIM->SCGC5 |= SIM_SCGC5_PORTA_MASK | SIM_SCGC5_PORTB_MASK | SIM_SCGC5_PORTC_MASK | SIM_SCGC5_PORTD_MASK | SIM_SCGC5_PORTE_MASK;
Pawel Zarembski 0:01f31e923fe2 48 SIM->SCGC6 |= SIM_SCGC6_DMAMUX_MASK;
Pawel Zarembski 0:01f31e923fe2 49 // configure pin as GPIO
Pawel Zarembski 0:01f31e923fe2 50 LED_CONNECTED_PORT->PCR[LED_CONNECTED_BIT] = PORT_PCR_MUX(1);
Pawel Zarembski 0:01f31e923fe2 51 // led off - enable output
Pawel Zarembski 0:01f31e923fe2 52 LED_CONNECTED_GPIO->PDOR = 1UL << LED_CONNECTED_BIT;
Pawel Zarembski 0:01f31e923fe2 53 LED_CONNECTED_GPIO->PDDR = 1UL << LED_CONNECTED_BIT;
Pawel Zarembski 0:01f31e923fe2 54 // led on
Pawel Zarembski 0:01f31e923fe2 55 LED_CONNECTED_GPIO->PCOR = 1UL << LED_CONNECTED_BIT;
Pawel Zarembski 0:01f31e923fe2 56 // reset button configured as gpio input
Pawel Zarembski 0:01f31e923fe2 57 PIN_nRESET_GPIO->PDDR &= ~PIN_nRESET;
Pawel Zarembski 0:01f31e923fe2 58 PIN_nRESET_PORT->PCR[PIN_nRESET_BIT] = PORT_PCR_MUX(1);
Pawel Zarembski 0:01f31e923fe2 59 /* Enable LVLRST_EN */
Pawel Zarembski 0:01f31e923fe2 60 PIN_nRESET_EN_PORT->PCR[PIN_nRESET_EN_BIT] = PORT_PCR_MUX(1) | /* GPIO */
Pawel Zarembski 0:01f31e923fe2 61 PORT_PCR_ODE_MASK; /* Open-drain */
Pawel Zarembski 0:01f31e923fe2 62 PIN_nRESET_EN_GPIO->PSOR = PIN_nRESET_EN;
Pawel Zarembski 0:01f31e923fe2 63 PIN_nRESET_EN_GPIO->PDDR |= PIN_nRESET_EN;
Pawel Zarembski 0:01f31e923fe2 64 // Configure SWO UART RX.
Pawel Zarembski 0:01f31e923fe2 65 PIN_SWO_RX_PORT->PCR[PIN_SWO_RX_BIT] = PORT_PCR_MUX(3); // UART1
Pawel Zarembski 0:01f31e923fe2 66 PIN_SWO_RX_GPIO->PDDR &= ~(1 << PIN_SWO_RX_BIT); // Input
Pawel Zarembski 0:01f31e923fe2 67
Pawel Zarembski 0:01f31e923fe2 68 // Enable pulldowns on power monitor control signals to reduce power consumption.
Pawel Zarembski 0:01f31e923fe2 69 PIN_CTRL0_PORT->PCR[PIN_CTRL0_BIT] = PORT_PCR_MUX(1) | PORT_PCR_PE_MASK | PORT_PCR_PS(0);
Pawel Zarembski 0:01f31e923fe2 70 PIN_CTRL1_PORT->PCR[PIN_CTRL1_BIT] = PORT_PCR_MUX(1) | PORT_PCR_PE_MASK | PORT_PCR_PS(0);
Pawel Zarembski 0:01f31e923fe2 71 PIN_CTRL2_PORT->PCR[PIN_CTRL2_BIT] = PORT_PCR_MUX(1) | PORT_PCR_PE_MASK | PORT_PCR_PS(0);
Pawel Zarembski 0:01f31e923fe2 72 PIN_CTRL3_PORT->PCR[PIN_CTRL3_BIT] = PORT_PCR_MUX(1) | PORT_PCR_PE_MASK | PORT_PCR_PS(0);
Pawel Zarembski 0:01f31e923fe2 73
Pawel Zarembski 0:01f31e923fe2 74 // Enable pulldown on GPIO0_B to prevent it floating.
Pawel Zarembski 0:01f31e923fe2 75 PIN_GPIO0_B_PORT->PCR[PIN_GPIO0_B_BIT] = PORT_PCR_MUX(1) | PORT_PCR_PE_MASK | PORT_PCR_PS(0);
Pawel Zarembski 0:01f31e923fe2 76
Pawel Zarembski 0:01f31e923fe2 77 // configure power enable pin as GPIO
Pawel Zarembski 0:01f31e923fe2 78 PIN_POWER_EN_PORT->PCR[PIN_POWER_EN_BIT] = PORT_PCR_MUX(1);
Pawel Zarembski 0:01f31e923fe2 79 // set output to 0
Pawel Zarembski 0:01f31e923fe2 80 PIN_POWER_EN_GPIO->PCOR = PIN_POWER_EN;
Pawel Zarembski 0:01f31e923fe2 81 // switch gpio to output
Pawel Zarembski 0:01f31e923fe2 82 PIN_POWER_EN_GPIO->PDDR |= PIN_POWER_EN;
Pawel Zarembski 0:01f31e923fe2 83
Pawel Zarembski 0:01f31e923fe2 84 // Let the voltage rails stabilize. This is especailly important
Pawel Zarembski 0:01f31e923fe2 85 // during software resets, since the target's 3.3v rail can take
Pawel Zarembski 0:01f31e923fe2 86 // 20-50ms to drain. During this time the target could be driving
Pawel Zarembski 0:01f31e923fe2 87 // the reset pin low, causing the bootloader to think the reset
Pawel Zarembski 0:01f31e923fe2 88 // button is pressed.
Pawel Zarembski 0:01f31e923fe2 89 // Note: With optimization set to -O2 the value 1000000 delays for ~85ms
Pawel Zarembski 0:01f31e923fe2 90 busy_wait(1000000);
Pawel Zarembski 0:01f31e923fe2 91 }
Pawel Zarembski 0:01f31e923fe2 92
Pawel Zarembski 0:01f31e923fe2 93 void gpio_set_board_power(bool powerEnabled)
Pawel Zarembski 0:01f31e923fe2 94 {
Pawel Zarembski 0:01f31e923fe2 95 if (powerEnabled) {
Pawel Zarembski 0:01f31e923fe2 96 // enable power switch
Pawel Zarembski 0:01f31e923fe2 97 PIN_POWER_EN_GPIO->PSOR = PIN_POWER_EN;
Pawel Zarembski 0:01f31e923fe2 98 }
Pawel Zarembski 0:01f31e923fe2 99 else {
Pawel Zarembski 0:01f31e923fe2 100 // disable power switch
Pawel Zarembski 0:01f31e923fe2 101 PIN_POWER_EN_GPIO->PCOR = PIN_POWER_EN;
Pawel Zarembski 0:01f31e923fe2 102 }
Pawel Zarembski 0:01f31e923fe2 103 }
Pawel Zarembski 0:01f31e923fe2 104
Pawel Zarembski 0:01f31e923fe2 105 uint32_t UART1_GetFreq(void)
Pawel Zarembski 0:01f31e923fe2 106 {
Pawel Zarembski 0:01f31e923fe2 107 return CLOCK_GetCoreSysClkFreq();
Pawel Zarembski 0:01f31e923fe2 108 }
Pawel Zarembski 0:01f31e923fe2 109
Pawel Zarembski 0:01f31e923fe2 110 void UART1_InitPins(void)
Pawel Zarembski 0:01f31e923fe2 111 {
Pawel Zarembski 0:01f31e923fe2 112 // RX pin inited in gpio_init();
Pawel Zarembski 0:01f31e923fe2 113 // TX not used.
Pawel Zarembski 0:01f31e923fe2 114 }
Pawel Zarembski 0:01f31e923fe2 115
Pawel Zarembski 0:01f31e923fe2 116 void UART1_DeinitPins(void)
Pawel Zarembski 0:01f31e923fe2 117 {
Pawel Zarembski 0:01f31e923fe2 118 // No need to deinit the RX pin.
Pawel Zarembski 0:01f31e923fe2 119 // TX not used.
Pawel Zarembski 0:01f31e923fe2 120 }
Pawel Zarembski 0:01f31e923fe2 121
Pawel Zarembski 0:01f31e923fe2 122 void gpio_set_hid_led(gpio_led_state_t state)
Pawel Zarembski 0:01f31e923fe2 123 {
Pawel Zarembski 0:01f31e923fe2 124 if (state) {
Pawel Zarembski 0:01f31e923fe2 125 LED_CONNECTED_GPIO->PCOR = LED_CONNECTED; // LED on
Pawel Zarembski 0:01f31e923fe2 126 } else {
Pawel Zarembski 0:01f31e923fe2 127 LED_CONNECTED_GPIO->PSOR = LED_CONNECTED; // LED off
Pawel Zarembski 0:01f31e923fe2 128 }
Pawel Zarembski 0:01f31e923fe2 129 }
Pawel Zarembski 0:01f31e923fe2 130
Pawel Zarembski 0:01f31e923fe2 131 void gpio_set_cdc_led(gpio_led_state_t state)
Pawel Zarembski 0:01f31e923fe2 132 {
Pawel Zarembski 0:01f31e923fe2 133 gpio_set_hid_led(state);
Pawel Zarembski 0:01f31e923fe2 134 }
Pawel Zarembski 0:01f31e923fe2 135
Pawel Zarembski 0:01f31e923fe2 136 void gpio_set_msc_led(gpio_led_state_t state)
Pawel Zarembski 0:01f31e923fe2 137 {
Pawel Zarembski 0:01f31e923fe2 138 gpio_set_hid_led(state);
Pawel Zarembski 0:01f31e923fe2 139 }
Pawel Zarembski 0:01f31e923fe2 140
Pawel Zarembski 0:01f31e923fe2 141 uint8_t gpio_get_reset_btn_no_fwrd(void)
Pawel Zarembski 0:01f31e923fe2 142 {
Pawel Zarembski 0:01f31e923fe2 143 return (PIN_nRESET_GPIO->PDIR & PIN_nRESET) ? 0 : 1;
Pawel Zarembski 0:01f31e923fe2 144 }
Pawel Zarembski 0:01f31e923fe2 145
Pawel Zarembski 0:01f31e923fe2 146 uint8_t gpio_get_reset_btn_fwrd(void)
Pawel Zarembski 0:01f31e923fe2 147 {
Pawel Zarembski 0:01f31e923fe2 148 return 0;
Pawel Zarembski 0:01f31e923fe2 149 }