Repostiory containing DAPLink source code with Reset Pin workaround for HANI_IOT board.
Upstream: https://github.com/ARMmbed/DAPLink
source/hic_hal/freescale/k26f/fsl_uart.h@0:01f31e923fe2, 2020-04-07 (annotated)
- Committer:
- Pawel Zarembski
- Date:
- Tue Apr 07 12:55:42 2020 +0200
- Revision:
- 0:01f31e923fe2
hani: DAPLink with reset workaround
Who changed what in which revision?
User | Revision | Line number | New contents of line |
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Pawel Zarembski |
0:01f31e923fe2 | 1 | /* |
Pawel Zarembski |
0:01f31e923fe2 | 2 | * Copyright (c) 2015-2016, Freescale Semiconductor, Inc. |
Pawel Zarembski |
0:01f31e923fe2 | 3 | * Copyright 2016-2017 NXP |
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0:01f31e923fe2 | 4 | * All rights reserved. |
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0:01f31e923fe2 | 5 | * |
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0:01f31e923fe2 | 6 | * SPDX-License-Identifier: BSD-3-Clause |
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0:01f31e923fe2 | 7 | */ |
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0:01f31e923fe2 | 8 | #ifndef _FSL_UART_H_ |
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0:01f31e923fe2 | 9 | #define _FSL_UART_H_ |
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0:01f31e923fe2 | 10 | |
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0:01f31e923fe2 | 11 | #include "fsl_common.h" |
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0:01f31e923fe2 | 12 | |
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0:01f31e923fe2 | 13 | /*! |
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0:01f31e923fe2 | 14 | * @addtogroup uart_driver |
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0:01f31e923fe2 | 15 | * @{ |
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0:01f31e923fe2 | 16 | */ |
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0:01f31e923fe2 | 17 | |
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0:01f31e923fe2 | 18 | /******************************************************************************* |
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0:01f31e923fe2 | 19 | * Definitions |
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0:01f31e923fe2 | 20 | ******************************************************************************/ |
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0:01f31e923fe2 | 21 | |
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0:01f31e923fe2 | 22 | /*! @name Driver version */ |
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0:01f31e923fe2 | 23 | /*@{*/ |
Pawel Zarembski |
0:01f31e923fe2 | 24 | /*! @brief UART driver version 2.1.6. */ |
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0:01f31e923fe2 | 25 | #define FSL_UART_DRIVER_VERSION (MAKE_VERSION(2, 1, 6)) |
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0:01f31e923fe2 | 26 | /*@}*/ |
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0:01f31e923fe2 | 27 | |
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0:01f31e923fe2 | 28 | /*! @brief Error codes for the UART driver. */ |
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0:01f31e923fe2 | 29 | enum _uart_status |
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0:01f31e923fe2 | 30 | { |
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0:01f31e923fe2 | 31 | kStatus_UART_TxBusy = MAKE_STATUS(kStatusGroup_UART, 0), /*!< Transmitter is busy. */ |
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0:01f31e923fe2 | 32 | kStatus_UART_RxBusy = MAKE_STATUS(kStatusGroup_UART, 1), /*!< Receiver is busy. */ |
Pawel Zarembski |
0:01f31e923fe2 | 33 | kStatus_UART_TxIdle = MAKE_STATUS(kStatusGroup_UART, 2), /*!< UART transmitter is idle. */ |
Pawel Zarembski |
0:01f31e923fe2 | 34 | kStatus_UART_RxIdle = MAKE_STATUS(kStatusGroup_UART, 3), /*!< UART receiver is idle. */ |
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0:01f31e923fe2 | 35 | kStatus_UART_TxWatermarkTooLarge = MAKE_STATUS(kStatusGroup_UART, 4), /*!< TX FIFO watermark too large */ |
Pawel Zarembski |
0:01f31e923fe2 | 36 | kStatus_UART_RxWatermarkTooLarge = MAKE_STATUS(kStatusGroup_UART, 5), /*!< RX FIFO watermark too large */ |
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0:01f31e923fe2 | 37 | kStatus_UART_FlagCannotClearManually = |
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0:01f31e923fe2 | 38 | MAKE_STATUS(kStatusGroup_UART, 6), /*!< UART flag can't be manually cleared. */ |
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0:01f31e923fe2 | 39 | kStatus_UART_Error = MAKE_STATUS(kStatusGroup_UART, 7), /*!< Error happens on UART. */ |
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0:01f31e923fe2 | 40 | kStatus_UART_RxRingBufferOverrun = MAKE_STATUS(kStatusGroup_UART, 8), /*!< UART RX software ring buffer overrun. */ |
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0:01f31e923fe2 | 41 | kStatus_UART_RxHardwareOverrun = MAKE_STATUS(kStatusGroup_UART, 9), /*!< UART RX receiver overrun. */ |
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0:01f31e923fe2 | 42 | kStatus_UART_NoiseError = MAKE_STATUS(kStatusGroup_UART, 10), /*!< UART noise error. */ |
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0:01f31e923fe2 | 43 | kStatus_UART_FramingError = MAKE_STATUS(kStatusGroup_UART, 11), /*!< UART framing error. */ |
Pawel Zarembski |
0:01f31e923fe2 | 44 | kStatus_UART_ParityError = MAKE_STATUS(kStatusGroup_UART, 12), /*!< UART parity error. */ |
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0:01f31e923fe2 | 45 | kStatus_UART_BaudrateNotSupport = |
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0:01f31e923fe2 | 46 | MAKE_STATUS(kStatusGroup_UART, 13), /*!< Baudrate is not support in current clock source */ |
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0:01f31e923fe2 | 47 | kStatus_UART_IdleLineDetected = MAKE_STATUS(kStatusGroup_UART, 14), /*!< UART IDLE line detected. */ |
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0:01f31e923fe2 | 48 | }; |
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0:01f31e923fe2 | 49 | |
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0:01f31e923fe2 | 50 | /*! @brief UART parity mode. */ |
Pawel Zarembski |
0:01f31e923fe2 | 51 | typedef enum _uart_parity_mode |
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0:01f31e923fe2 | 52 | { |
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0:01f31e923fe2 | 53 | kUART_ParityDisabled = 0x0U, /*!< Parity disabled */ |
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0:01f31e923fe2 | 54 | kUART_ParityEven = 0x2U, /*!< Parity enabled, type even, bit setting: PE|PT = 10 */ |
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0:01f31e923fe2 | 55 | kUART_ParityOdd = 0x3U, /*!< Parity enabled, type odd, bit setting: PE|PT = 11 */ |
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0:01f31e923fe2 | 56 | } uart_parity_mode_t; |
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0:01f31e923fe2 | 57 | |
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0:01f31e923fe2 | 58 | /*! @brief UART stop bit count. */ |
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0:01f31e923fe2 | 59 | typedef enum _uart_stop_bit_count |
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0:01f31e923fe2 | 60 | { |
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0:01f31e923fe2 | 61 | kUART_OneStopBit = 0U, /*!< One stop bit */ |
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0:01f31e923fe2 | 62 | kUART_TwoStopBit = 1U, /*!< Two stop bits */ |
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0:01f31e923fe2 | 63 | } uart_stop_bit_count_t; |
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0:01f31e923fe2 | 64 | |
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0:01f31e923fe2 | 65 | /*! @brief UART idle type select. */ |
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0:01f31e923fe2 | 66 | typedef enum _uart_idle_type_select |
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0:01f31e923fe2 | 67 | { |
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0:01f31e923fe2 | 68 | kUART_IdleTypeStartBit = 0U, /*!< Start counting after a valid start bit. */ |
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0:01f31e923fe2 | 69 | kUART_IdleTypeStopBit = 1U, /*!< Start counting after a stop bit. */ |
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0:01f31e923fe2 | 70 | } uart_idle_type_select_t; |
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0:01f31e923fe2 | 71 | |
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0:01f31e923fe2 | 72 | /*! |
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0:01f31e923fe2 | 73 | * @brief UART interrupt configuration structure, default settings all disabled. |
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0:01f31e923fe2 | 74 | * |
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0:01f31e923fe2 | 75 | * This structure contains the settings for all of the UART interrupt configurations. |
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0:01f31e923fe2 | 76 | */ |
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0:01f31e923fe2 | 77 | enum _uart_interrupt_enable |
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0:01f31e923fe2 | 78 | { |
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0:01f31e923fe2 | 79 | #if defined(FSL_FEATURE_UART_HAS_LIN_BREAK_DETECT) && FSL_FEATURE_UART_HAS_LIN_BREAK_DETECT |
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0:01f31e923fe2 | 80 | kUART_LinBreakInterruptEnable = (UART_BDH_LBKDIE_MASK), /*!< LIN break detect interrupt. */ |
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0:01f31e923fe2 | 81 | #endif |
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0:01f31e923fe2 | 82 | kUART_RxActiveEdgeInterruptEnable = (UART_BDH_RXEDGIE_MASK), /*!< RX active edge interrupt. */ |
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0:01f31e923fe2 | 83 | kUART_TxDataRegEmptyInterruptEnable = (UART_C2_TIE_MASK << 8), /*!< Transmit data register empty interrupt. */ |
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0:01f31e923fe2 | 84 | kUART_TransmissionCompleteInterruptEnable = (UART_C2_TCIE_MASK << 8), /*!< Transmission complete interrupt. */ |
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0:01f31e923fe2 | 85 | kUART_RxDataRegFullInterruptEnable = (UART_C2_RIE_MASK << 8), /*!< Receiver data register full interrupt. */ |
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0:01f31e923fe2 | 86 | kUART_IdleLineInterruptEnable = (UART_C2_ILIE_MASK << 8), /*!< Idle line interrupt. */ |
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0:01f31e923fe2 | 87 | kUART_RxOverrunInterruptEnable = (UART_C3_ORIE_MASK << 16), /*!< Receiver overrun interrupt. */ |
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0:01f31e923fe2 | 88 | kUART_NoiseErrorInterruptEnable = (UART_C3_NEIE_MASK << 16), /*!< Noise error flag interrupt. */ |
Pawel Zarembski |
0:01f31e923fe2 | 89 | kUART_FramingErrorInterruptEnable = (UART_C3_FEIE_MASK << 16), /*!< Framing error flag interrupt. */ |
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0:01f31e923fe2 | 90 | kUART_ParityErrorInterruptEnable = (UART_C3_PEIE_MASK << 16), /*!< Parity error flag interrupt. */ |
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0:01f31e923fe2 | 91 | #if defined(FSL_FEATURE_UART_HAS_FIFO) && FSL_FEATURE_UART_HAS_FIFO |
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0:01f31e923fe2 | 92 | kUART_RxFifoOverflowInterruptEnable = (UART_CFIFO_RXOFE_MASK << 24), /*!< RX FIFO overflow interrupt. */ |
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0:01f31e923fe2 | 93 | kUART_TxFifoOverflowInterruptEnable = (UART_CFIFO_TXOFE_MASK << 24), /*!< TX FIFO overflow interrupt. */ |
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0:01f31e923fe2 | 94 | kUART_RxFifoUnderflowInterruptEnable = (UART_CFIFO_RXUFE_MASK << 24), /*!< RX FIFO underflow interrupt. */ |
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0:01f31e923fe2 | 95 | #endif |
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0:01f31e923fe2 | 96 | kUART_AllInterruptsEnable = |
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0:01f31e923fe2 | 97 | #if defined(FSL_FEATURE_UART_HAS_LIN_BREAK_DETECT) && FSL_FEATURE_UART_HAS_LIN_BREAK_DETECT |
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0:01f31e923fe2 | 98 | kUART_LinBreakInterruptEnable | |
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0:01f31e923fe2 | 99 | #endif |
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0:01f31e923fe2 | 100 | kUART_RxActiveEdgeInterruptEnable | kUART_TxDataRegEmptyInterruptEnable | |
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0:01f31e923fe2 | 101 | kUART_TransmissionCompleteInterruptEnable | kUART_RxDataRegFullInterruptEnable | kUART_IdleLineInterruptEnable | |
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0:01f31e923fe2 | 102 | kUART_RxOverrunInterruptEnable | kUART_NoiseErrorInterruptEnable | kUART_FramingErrorInterruptEnable | |
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0:01f31e923fe2 | 103 | kUART_ParityErrorInterruptEnable |
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0:01f31e923fe2 | 104 | #if defined(FSL_FEATURE_UART_HAS_FIFO) && FSL_FEATURE_UART_HAS_FIFO |
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0:01f31e923fe2 | 105 | | |
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0:01f31e923fe2 | 106 | kUART_RxFifoOverflowInterruptEnable | kUART_TxFifoOverflowInterruptEnable | kUART_RxFifoUnderflowInterruptEnable |
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0:01f31e923fe2 | 107 | #endif |
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0:01f31e923fe2 | 108 | , |
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0:01f31e923fe2 | 109 | }; |
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0:01f31e923fe2 | 110 | |
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0:01f31e923fe2 | 111 | /*! |
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0:01f31e923fe2 | 112 | * @brief UART status flags. |
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0:01f31e923fe2 | 113 | * |
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0:01f31e923fe2 | 114 | * This provides constants for the UART status flags for use in the UART functions. |
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0:01f31e923fe2 | 115 | */ |
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0:01f31e923fe2 | 116 | enum _uart_flags |
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0:01f31e923fe2 | 117 | { |
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0:01f31e923fe2 | 118 | kUART_TxDataRegEmptyFlag = (UART_S1_TDRE_MASK), /*!< TX data register empty flag. */ |
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0:01f31e923fe2 | 119 | kUART_TransmissionCompleteFlag = (UART_S1_TC_MASK), /*!< Transmission complete flag. */ |
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0:01f31e923fe2 | 120 | kUART_RxDataRegFullFlag = (UART_S1_RDRF_MASK), /*!< RX data register full flag. */ |
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0:01f31e923fe2 | 121 | kUART_IdleLineFlag = (UART_S1_IDLE_MASK), /*!< Idle line detect flag. */ |
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0:01f31e923fe2 | 122 | kUART_RxOverrunFlag = (UART_S1_OR_MASK), /*!< RX overrun flag. */ |
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0:01f31e923fe2 | 123 | kUART_NoiseErrorFlag = (UART_S1_NF_MASK), /*!< RX takes 3 samples of each received bit. |
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0:01f31e923fe2 | 124 | If any of these samples differ, noise flag sets */ |
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0:01f31e923fe2 | 125 | kUART_FramingErrorFlag = (UART_S1_FE_MASK), /*!< Frame error flag, sets if logic 0 was detected |
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0:01f31e923fe2 | 126 | where stop bit expected */ |
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0:01f31e923fe2 | 127 | kUART_ParityErrorFlag = (UART_S1_PF_MASK), /*!< If parity enabled, sets upon parity error detection */ |
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0:01f31e923fe2 | 128 | #if defined(FSL_FEATURE_UART_HAS_LIN_BREAK_DETECT) && FSL_FEATURE_UART_HAS_LIN_BREAK_DETECT |
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0:01f31e923fe2 | 129 | kUART_LinBreakFlag = |
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0:01f31e923fe2 | 130 | (UART_S2_LBKDIF_MASK |
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0:01f31e923fe2 | 131 | << 8), /*!< LIN break detect interrupt flag, sets when LIN break char detected and LIN circuit enabled */ |
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0:01f31e923fe2 | 132 | #endif |
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0:01f31e923fe2 | 133 | kUART_RxActiveEdgeFlag = |
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0:01f31e923fe2 | 134 | (UART_S2_RXEDGIF_MASK << 8), /*!< RX pin active edge interrupt flag,sets when active edge detected */ |
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0:01f31e923fe2 | 135 | kUART_RxActiveFlag = |
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0:01f31e923fe2 | 136 | (UART_S2_RAF_MASK << 8), /*!< Receiver Active Flag (RAF), sets at beginning of valid start bit */ |
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0:01f31e923fe2 | 137 | #if defined(FSL_FEATURE_UART_HAS_EXTENDED_DATA_REGISTER_FLAGS) && FSL_FEATURE_UART_HAS_EXTENDED_DATA_REGISTER_FLAGS |
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0:01f31e923fe2 | 138 | kUART_NoiseErrorInRxDataRegFlag = (UART_ED_NOISY_MASK << 16), /*!< Noisy bit, sets if noise detected. */ |
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0:01f31e923fe2 | 139 | kUART_ParityErrorInRxDataRegFlag = (UART_ED_PARITYE_MASK << 16), /*!< Parity bit, sets if parity error detected. */ |
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0:01f31e923fe2 | 140 | #endif |
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0:01f31e923fe2 | 141 | #if defined(FSL_FEATURE_UART_HAS_FIFO) && FSL_FEATURE_UART_HAS_FIFO |
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0:01f31e923fe2 | 142 | kUART_TxFifoEmptyFlag = (int)(UART_SFIFO_TXEMPT_MASK << 24), /*!< TXEMPT bit, sets if TX buffer is empty */ |
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0:01f31e923fe2 | 143 | kUART_RxFifoEmptyFlag = (UART_SFIFO_RXEMPT_MASK << 24), /*!< RXEMPT bit, sets if RX buffer is empty */ |
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0:01f31e923fe2 | 144 | kUART_TxFifoOverflowFlag = (UART_SFIFO_TXOF_MASK << 24), /*!< TXOF bit, sets if TX buffer overflow occurred */ |
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0:01f31e923fe2 | 145 | kUART_RxFifoOverflowFlag = (UART_SFIFO_RXOF_MASK << 24), /*!< RXOF bit, sets if receive buffer overflow */ |
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0:01f31e923fe2 | 146 | kUART_RxFifoUnderflowFlag = (UART_SFIFO_RXUF_MASK << 24), /*!< RXUF bit, sets if receive buffer underflow */ |
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0:01f31e923fe2 | 147 | #endif |
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0:01f31e923fe2 | 148 | }; |
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0:01f31e923fe2 | 149 | |
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0:01f31e923fe2 | 150 | /*! @brief UART configuration structure. */ |
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0:01f31e923fe2 | 151 | typedef struct _uart_config |
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0:01f31e923fe2 | 152 | { |
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0:01f31e923fe2 | 153 | uint32_t baudRate_Bps; /*!< UART baud rate */ |
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0:01f31e923fe2 | 154 | uart_parity_mode_t parityMode; /*!< Parity mode, disabled (default), even, odd */ |
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0:01f31e923fe2 | 155 | #if defined(FSL_FEATURE_UART_HAS_STOP_BIT_CONFIG_SUPPORT) && FSL_FEATURE_UART_HAS_STOP_BIT_CONFIG_SUPPORT |
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0:01f31e923fe2 | 156 | uart_stop_bit_count_t stopBitCount; /*!< Number of stop bits, 1 stop bit (default) or 2 stop bits */ |
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0:01f31e923fe2 | 157 | #endif |
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0:01f31e923fe2 | 158 | #if defined(FSL_FEATURE_UART_HAS_FIFO) && FSL_FEATURE_UART_HAS_FIFO |
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0:01f31e923fe2 | 159 | uint8_t txFifoWatermark; /*!< TX FIFO watermark */ |
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0:01f31e923fe2 | 160 | uint8_t rxFifoWatermark; /*!< RX FIFO watermark */ |
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0:01f31e923fe2 | 161 | #endif |
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0:01f31e923fe2 | 162 | #if defined(FSL_FEATURE_UART_HAS_MODEM_SUPPORT) && FSL_FEATURE_UART_HAS_MODEM_SUPPORT |
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0:01f31e923fe2 | 163 | bool enableRxRTS; /*!< RX RTS enable */ |
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0:01f31e923fe2 | 164 | bool enableTxCTS; /*!< TX CTS enable */ |
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0:01f31e923fe2 | 165 | #endif |
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0:01f31e923fe2 | 166 | uart_idle_type_select_t idleType; /*!< IDLE type select. */ |
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0:01f31e923fe2 | 167 | bool enableTx; /*!< Enable TX */ |
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0:01f31e923fe2 | 168 | bool enableRx; /*!< Enable RX */ |
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0:01f31e923fe2 | 169 | } uart_config_t; |
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0:01f31e923fe2 | 170 | |
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0:01f31e923fe2 | 171 | /*! @brief UART transfer structure. */ |
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0:01f31e923fe2 | 172 | typedef struct _uart_transfer |
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0:01f31e923fe2 | 173 | { |
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0:01f31e923fe2 | 174 | uint8_t *data; /*!< The buffer of data to be transfer.*/ |
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0:01f31e923fe2 | 175 | size_t dataSize; /*!< The byte count to be transfer. */ |
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0:01f31e923fe2 | 176 | } uart_transfer_t; |
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0:01f31e923fe2 | 177 | |
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0:01f31e923fe2 | 178 | /* Forward declaration of the handle typedef. */ |
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0:01f31e923fe2 | 179 | typedef struct _uart_handle uart_handle_t; |
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0:01f31e923fe2 | 180 | |
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0:01f31e923fe2 | 181 | /*! @brief UART transfer callback function. */ |
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0:01f31e923fe2 | 182 | typedef void (*uart_transfer_callback_t)(UART_Type *base, uart_handle_t *handle, status_t status, void *userData); |
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0:01f31e923fe2 | 183 | |
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0:01f31e923fe2 | 184 | /*! @brief UART handle structure. */ |
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0:01f31e923fe2 | 185 | struct _uart_handle |
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0:01f31e923fe2 | 186 | { |
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0:01f31e923fe2 | 187 | uint8_t *volatile txData; /*!< Address of remaining data to send. */ |
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0:01f31e923fe2 | 188 | volatile size_t txDataSize; /*!< Size of the remaining data to send. */ |
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0:01f31e923fe2 | 189 | size_t txDataSizeAll; /*!< Size of the data to send out. */ |
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0:01f31e923fe2 | 190 | uint8_t *volatile rxData; /*!< Address of remaining data to receive. */ |
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0:01f31e923fe2 | 191 | volatile size_t rxDataSize; /*!< Size of the remaining data to receive. */ |
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0:01f31e923fe2 | 192 | size_t rxDataSizeAll; /*!< Size of the data to receive. */ |
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0:01f31e923fe2 | 193 | |
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0:01f31e923fe2 | 194 | uint8_t *rxRingBuffer; /*!< Start address of the receiver ring buffer. */ |
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0:01f31e923fe2 | 195 | size_t rxRingBufferSize; /*!< Size of the ring buffer. */ |
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0:01f31e923fe2 | 196 | volatile uint16_t rxRingBufferHead; /*!< Index for the driver to store received data into ring buffer. */ |
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0:01f31e923fe2 | 197 | volatile uint16_t rxRingBufferTail; /*!< Index for the user to get data from the ring buffer. */ |
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0:01f31e923fe2 | 198 | |
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0:01f31e923fe2 | 199 | uart_transfer_callback_t callback; /*!< Callback function. */ |
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0:01f31e923fe2 | 200 | void *userData; /*!< UART callback function parameter.*/ |
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0:01f31e923fe2 | 201 | |
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0:01f31e923fe2 | 202 | volatile uint8_t txState; /*!< TX transfer state. */ |
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0:01f31e923fe2 | 203 | volatile uint8_t rxState; /*!< RX transfer state */ |
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0:01f31e923fe2 | 204 | }; |
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0:01f31e923fe2 | 205 | |
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0:01f31e923fe2 | 206 | /******************************************************************************* |
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0:01f31e923fe2 | 207 | * API |
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0:01f31e923fe2 | 208 | ******************************************************************************/ |
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0:01f31e923fe2 | 209 | |
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0:01f31e923fe2 | 210 | #if defined(__cplusplus) |
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0:01f31e923fe2 | 211 | extern "C" { |
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0:01f31e923fe2 | 212 | #endif /* _cplusplus */ |
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0:01f31e923fe2 | 213 | |
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0:01f31e923fe2 | 214 | /*! |
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0:01f31e923fe2 | 215 | * @brief Get the UART instance from peripheral base address. |
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0:01f31e923fe2 | 216 | * |
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0:01f31e923fe2 | 217 | * @param base UART peripheral base address. |
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0:01f31e923fe2 | 218 | * @return UART instance. |
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0:01f31e923fe2 | 219 | */ |
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0:01f31e923fe2 | 220 | uint32_t UART_GetInstance(UART_Type *base); |
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0:01f31e923fe2 | 221 | |
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0:01f31e923fe2 | 222 | /*! |
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0:01f31e923fe2 | 223 | * @name Initialization and deinitialization |
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0:01f31e923fe2 | 224 | * @{ |
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0:01f31e923fe2 | 225 | */ |
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0:01f31e923fe2 | 226 | |
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0:01f31e923fe2 | 227 | /*! |
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0:01f31e923fe2 | 228 | * @brief Initializes a UART instance with a user configuration structure and peripheral clock. |
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0:01f31e923fe2 | 229 | * |
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0:01f31e923fe2 | 230 | * This function configures the UART module with the user-defined settings. The user can configure the configuration |
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0:01f31e923fe2 | 231 | * structure and also get the default configuration by using the UART_GetDefaultConfig() function. |
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0:01f31e923fe2 | 232 | * The example below shows how to use this API to configure UART. |
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0:01f31e923fe2 | 233 | * @code |
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0:01f31e923fe2 | 234 | * uart_config_t uartConfig; |
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0:01f31e923fe2 | 235 | * uartConfig.baudRate_Bps = 115200U; |
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0:01f31e923fe2 | 236 | * uartConfig.parityMode = kUART_ParityDisabled; |
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0:01f31e923fe2 | 237 | * uartConfig.stopBitCount = kUART_OneStopBit; |
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0:01f31e923fe2 | 238 | * uartConfig.txFifoWatermark = 0; |
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0:01f31e923fe2 | 239 | * uartConfig.rxFifoWatermark = 1; |
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0:01f31e923fe2 | 240 | * UART_Init(UART1, &uartConfig, 20000000U); |
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0:01f31e923fe2 | 241 | * @endcode |
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0:01f31e923fe2 | 242 | * |
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0:01f31e923fe2 | 243 | * @param base UART peripheral base address. |
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0:01f31e923fe2 | 244 | * @param config Pointer to the user-defined configuration structure. |
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0:01f31e923fe2 | 245 | * @param srcClock_Hz UART clock source frequency in HZ. |
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0:01f31e923fe2 | 246 | * @retval kStatus_UART_BaudrateNotSupport Baudrate is not support in current clock source. |
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0:01f31e923fe2 | 247 | * @retval kStatus_Success Status UART initialize succeed |
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0:01f31e923fe2 | 248 | */ |
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0:01f31e923fe2 | 249 | status_t UART_Init(UART_Type *base, const uart_config_t *config, uint32_t srcClock_Hz); |
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0:01f31e923fe2 | 250 | |
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0:01f31e923fe2 | 251 | /*! |
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0:01f31e923fe2 | 252 | * @brief Deinitializes a UART instance. |
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0:01f31e923fe2 | 253 | * |
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0:01f31e923fe2 | 254 | * This function waits for TX complete, disables TX and RX, and disables the UART clock. |
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0:01f31e923fe2 | 255 | * |
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0:01f31e923fe2 | 256 | * @param base UART peripheral base address. |
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0:01f31e923fe2 | 257 | */ |
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0:01f31e923fe2 | 258 | void UART_Deinit(UART_Type *base); |
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0:01f31e923fe2 | 259 | |
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0:01f31e923fe2 | 260 | /*! |
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0:01f31e923fe2 | 261 | * @brief Gets the default configuration structure. |
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0:01f31e923fe2 | 262 | * |
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0:01f31e923fe2 | 263 | * This function initializes the UART configuration structure to a default value. The default |
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0:01f31e923fe2 | 264 | * values are as follows. |
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0:01f31e923fe2 | 265 | * uartConfig->baudRate_Bps = 115200U; |
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0:01f31e923fe2 | 266 | * uartConfig->bitCountPerChar = kUART_8BitsPerChar; |
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0:01f31e923fe2 | 267 | * uartConfig->parityMode = kUART_ParityDisabled; |
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0:01f31e923fe2 | 268 | * uartConfig->stopBitCount = kUART_OneStopBit; |
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0:01f31e923fe2 | 269 | * uartConfig->txFifoWatermark = 0; |
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0:01f31e923fe2 | 270 | * uartConfig->rxFifoWatermark = 1; |
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0:01f31e923fe2 | 271 | * uartConfig->idleType = kUART_IdleTypeStartBit; |
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0:01f31e923fe2 | 272 | * uartConfig->enableTx = false; |
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0:01f31e923fe2 | 273 | * uartConfig->enableRx = false; |
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0:01f31e923fe2 | 274 | * |
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0:01f31e923fe2 | 275 | * @param config Pointer to configuration structure. |
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0:01f31e923fe2 | 276 | */ |
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0:01f31e923fe2 | 277 | void UART_GetDefaultConfig(uart_config_t *config); |
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0:01f31e923fe2 | 278 | |
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0:01f31e923fe2 | 279 | /*! |
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0:01f31e923fe2 | 280 | * @brief Sets the UART instance baud rate. |
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0:01f31e923fe2 | 281 | * |
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0:01f31e923fe2 | 282 | * This function configures the UART module baud rate. This function is used to update |
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0:01f31e923fe2 | 283 | * the UART module baud rate after the UART module is initialized by the UART_Init. |
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0:01f31e923fe2 | 284 | * @code |
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0:01f31e923fe2 | 285 | * UART_SetBaudRate(UART1, 115200U, 20000000U); |
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0:01f31e923fe2 | 286 | * @endcode |
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0:01f31e923fe2 | 287 | * |
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0:01f31e923fe2 | 288 | * @param base UART peripheral base address. |
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0:01f31e923fe2 | 289 | * @param baudRate_Bps UART baudrate to be set. |
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0:01f31e923fe2 | 290 | * @param srcClock_Hz UART clock source freqency in Hz. |
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0:01f31e923fe2 | 291 | * @retval kStatus_UART_BaudrateNotSupport Baudrate is not support in the current clock source. |
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0:01f31e923fe2 | 292 | * @retval kStatus_Success Set baudrate succeeded. |
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0:01f31e923fe2 | 293 | */ |
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0:01f31e923fe2 | 294 | status_t UART_SetBaudRate(UART_Type *base, uint32_t baudRate_Bps, uint32_t srcClock_Hz); |
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0:01f31e923fe2 | 295 | |
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0:01f31e923fe2 | 296 | /* @} */ |
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0:01f31e923fe2 | 297 | |
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0:01f31e923fe2 | 298 | /*! |
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0:01f31e923fe2 | 299 | * @name Status |
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0:01f31e923fe2 | 300 | * @{ |
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0:01f31e923fe2 | 301 | */ |
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0:01f31e923fe2 | 302 | |
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0:01f31e923fe2 | 303 | /*! |
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0:01f31e923fe2 | 304 | * @brief Gets UART status flags. |
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0:01f31e923fe2 | 305 | * |
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0:01f31e923fe2 | 306 | * This function gets all UART status flags. The flags are returned as the logical |
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0:01f31e923fe2 | 307 | * OR value of the enumerators @ref _uart_flags. To check a specific status, |
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0:01f31e923fe2 | 308 | * compare the return value with enumerators in @ref _uart_flags. |
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0:01f31e923fe2 | 309 | * For example, to check whether the TX is empty, do the following. |
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0:01f31e923fe2 | 310 | * @code |
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0:01f31e923fe2 | 311 | * if (kUART_TxDataRegEmptyFlag & UART_GetStatusFlags(UART1)) |
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0:01f31e923fe2 | 312 | * { |
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0:01f31e923fe2 | 313 | * ... |
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0:01f31e923fe2 | 314 | * } |
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0:01f31e923fe2 | 315 | * @endcode |
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0:01f31e923fe2 | 316 | * |
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0:01f31e923fe2 | 317 | * @param base UART peripheral base address. |
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0:01f31e923fe2 | 318 | * @return UART status flags which are ORed by the enumerators in the _uart_flags. |
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0:01f31e923fe2 | 319 | */ |
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0:01f31e923fe2 | 320 | uint32_t UART_GetStatusFlags(UART_Type *base); |
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0:01f31e923fe2 | 321 | |
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0:01f31e923fe2 | 322 | /*! |
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0:01f31e923fe2 | 323 | * @brief Clears status flags with the provided mask. |
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0:01f31e923fe2 | 324 | * |
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0:01f31e923fe2 | 325 | * This function clears UART status flags with a provided mask. An automatically cleared flag |
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0:01f31e923fe2 | 326 | * can't be cleared by this function. |
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0:01f31e923fe2 | 327 | * These flags can only be cleared or set by hardware. |
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0:01f31e923fe2 | 328 | * kUART_TxDataRegEmptyFlag, kUART_TransmissionCompleteFlag, kUART_RxDataRegFullFlag, |
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0:01f31e923fe2 | 329 | * kUART_RxActiveFlag, kUART_NoiseErrorInRxDataRegFlag, kUART_ParityErrorInRxDataRegFlag, |
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0:01f31e923fe2 | 330 | * kUART_TxFifoEmptyFlag,kUART_RxFifoEmptyFlag |
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0:01f31e923fe2 | 331 | * Note that this API should be called when the Tx/Rx is idle. Otherwise it has no effect. |
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0:01f31e923fe2 | 332 | * |
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0:01f31e923fe2 | 333 | * @param base UART peripheral base address. |
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0:01f31e923fe2 | 334 | * @param mask The status flags to be cleared; it is logical OR value of @ref _uart_flags. |
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0:01f31e923fe2 | 335 | * @retval kStatus_UART_FlagCannotClearManually The flag can't be cleared by this function but |
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0:01f31e923fe2 | 336 | * it is cleared automatically by hardware. |
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0:01f31e923fe2 | 337 | * @retval kStatus_Success Status in the mask is cleared. |
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0:01f31e923fe2 | 338 | */ |
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0:01f31e923fe2 | 339 | status_t UART_ClearStatusFlags(UART_Type *base, uint32_t mask); |
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0:01f31e923fe2 | 340 | |
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0:01f31e923fe2 | 341 | /* @} */ |
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0:01f31e923fe2 | 342 | |
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0:01f31e923fe2 | 343 | /*! |
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0:01f31e923fe2 | 344 | * @name Interrupts |
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0:01f31e923fe2 | 345 | * @{ |
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0:01f31e923fe2 | 346 | */ |
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0:01f31e923fe2 | 347 | |
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0:01f31e923fe2 | 348 | /*! |
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0:01f31e923fe2 | 349 | * @brief Enables UART interrupts according to the provided mask. |
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0:01f31e923fe2 | 350 | * |
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0:01f31e923fe2 | 351 | * This function enables the UART interrupts according to the provided mask. The mask |
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0:01f31e923fe2 | 352 | * is a logical OR of enumeration members. See @ref _uart_interrupt_enable. |
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0:01f31e923fe2 | 353 | * For example, to enable TX empty interrupt and RX full interrupt, do the following. |
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0:01f31e923fe2 | 354 | * @code |
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0:01f31e923fe2 | 355 | * UART_EnableInterrupts(UART1,kUART_TxDataRegEmptyInterruptEnable | kUART_RxDataRegFullInterruptEnable); |
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0:01f31e923fe2 | 356 | * @endcode |
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0:01f31e923fe2 | 357 | * |
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0:01f31e923fe2 | 358 | * @param base UART peripheral base address. |
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0:01f31e923fe2 | 359 | * @param mask The interrupts to enable. Logical OR of @ref _uart_interrupt_enable. |
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0:01f31e923fe2 | 360 | */ |
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0:01f31e923fe2 | 361 | void UART_EnableInterrupts(UART_Type *base, uint32_t mask); |
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0:01f31e923fe2 | 362 | |
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0:01f31e923fe2 | 363 | /*! |
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0:01f31e923fe2 | 364 | * @brief Disables the UART interrupts according to the provided mask. |
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0:01f31e923fe2 | 365 | * |
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0:01f31e923fe2 | 366 | * This function disables the UART interrupts according to the provided mask. The mask |
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0:01f31e923fe2 | 367 | * is a logical OR of enumeration members. See @ref _uart_interrupt_enable. |
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0:01f31e923fe2 | 368 | * For example, to disable TX empty interrupt and RX full interrupt do the following. |
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0:01f31e923fe2 | 369 | * @code |
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0:01f31e923fe2 | 370 | * UART_DisableInterrupts(UART1,kUART_TxDataRegEmptyInterruptEnable | kUART_RxDataRegFullInterruptEnable); |
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0:01f31e923fe2 | 371 | * @endcode |
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0:01f31e923fe2 | 372 | * |
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0:01f31e923fe2 | 373 | * @param base UART peripheral base address. |
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0:01f31e923fe2 | 374 | * @param mask The interrupts to disable. Logical OR of @ref _uart_interrupt_enable. |
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0:01f31e923fe2 | 375 | */ |
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0:01f31e923fe2 | 376 | void UART_DisableInterrupts(UART_Type *base, uint32_t mask); |
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0:01f31e923fe2 | 377 | |
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0:01f31e923fe2 | 378 | /*! |
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0:01f31e923fe2 | 379 | * @brief Gets the enabled UART interrupts. |
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0:01f31e923fe2 | 380 | * |
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0:01f31e923fe2 | 381 | * This function gets the enabled UART interrupts. The enabled interrupts are returned |
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0:01f31e923fe2 | 382 | * as the logical OR value of the enumerators @ref _uart_interrupt_enable. To check |
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0:01f31e923fe2 | 383 | * a specific interrupts enable status, compare the return value with enumerators |
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0:01f31e923fe2 | 384 | * in @ref _uart_interrupt_enable. |
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0:01f31e923fe2 | 385 | * For example, to check whether TX empty interrupt is enabled, do the following. |
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0:01f31e923fe2 | 386 | * @code |
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0:01f31e923fe2 | 387 | * uint32_t enabledInterrupts = UART_GetEnabledInterrupts(UART1); |
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0:01f31e923fe2 | 388 | * |
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0:01f31e923fe2 | 389 | * if (kUART_TxDataRegEmptyInterruptEnable & enabledInterrupts) |
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0:01f31e923fe2 | 390 | * { |
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0:01f31e923fe2 | 391 | * ... |
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0:01f31e923fe2 | 392 | * } |
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0:01f31e923fe2 | 393 | * @endcode |
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0:01f31e923fe2 | 394 | * |
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0:01f31e923fe2 | 395 | * @param base UART peripheral base address. |
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0:01f31e923fe2 | 396 | * @return UART interrupt flags which are logical OR of the enumerators in @ref _uart_interrupt_enable. |
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0:01f31e923fe2 | 397 | */ |
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0:01f31e923fe2 | 398 | uint32_t UART_GetEnabledInterrupts(UART_Type *base); |
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0:01f31e923fe2 | 399 | |
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0:01f31e923fe2 | 400 | /* @} */ |
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0:01f31e923fe2 | 401 | |
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0:01f31e923fe2 | 402 | #if defined(FSL_FEATURE_UART_HAS_DMA_SELECT) && FSL_FEATURE_UART_HAS_DMA_SELECT |
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0:01f31e923fe2 | 403 | /*! |
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0:01f31e923fe2 | 404 | * @name DMA Control |
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0:01f31e923fe2 | 405 | * @{ |
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0:01f31e923fe2 | 406 | */ |
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0:01f31e923fe2 | 407 | |
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0:01f31e923fe2 | 408 | /*! |
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0:01f31e923fe2 | 409 | * @brief Gets the UART data register address. |
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0:01f31e923fe2 | 410 | * |
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0:01f31e923fe2 | 411 | * This function returns the UART data register address, which is mainly used by DMA/eDMA. |
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0:01f31e923fe2 | 412 | * |
Pawel Zarembski |
0:01f31e923fe2 | 413 | * @param base UART peripheral base address. |
Pawel Zarembski |
0:01f31e923fe2 | 414 | * @return UART data register addresses which are used both by the transmitter and the receiver. |
Pawel Zarembski |
0:01f31e923fe2 | 415 | */ |
Pawel Zarembski |
0:01f31e923fe2 | 416 | static inline uint32_t UART_GetDataRegisterAddress(UART_Type *base) |
Pawel Zarembski |
0:01f31e923fe2 | 417 | { |
Pawel Zarembski |
0:01f31e923fe2 | 418 | return (uint32_t) & (base->D); |
Pawel Zarembski |
0:01f31e923fe2 | 419 | } |
Pawel Zarembski |
0:01f31e923fe2 | 420 | |
Pawel Zarembski |
0:01f31e923fe2 | 421 | /*! |
Pawel Zarembski |
0:01f31e923fe2 | 422 | * @brief Enables or disables the UART transmitter DMA request. |
Pawel Zarembski |
0:01f31e923fe2 | 423 | * |
Pawel Zarembski |
0:01f31e923fe2 | 424 | * This function enables or disables the transmit data register empty flag, S1[TDRE], to generate the DMA requests. |
Pawel Zarembski |
0:01f31e923fe2 | 425 | * |
Pawel Zarembski |
0:01f31e923fe2 | 426 | * @param base UART peripheral base address. |
Pawel Zarembski |
0:01f31e923fe2 | 427 | * @param enable True to enable, false to disable. |
Pawel Zarembski |
0:01f31e923fe2 | 428 | */ |
Pawel Zarembski |
0:01f31e923fe2 | 429 | static inline void UART_EnableTxDMA(UART_Type *base, bool enable) |
Pawel Zarembski |
0:01f31e923fe2 | 430 | { |
Pawel Zarembski |
0:01f31e923fe2 | 431 | if (enable) |
Pawel Zarembski |
0:01f31e923fe2 | 432 | { |
Pawel Zarembski |
0:01f31e923fe2 | 433 | #if (defined(FSL_FEATURE_UART_IS_SCI) && FSL_FEATURE_UART_IS_SCI) |
Pawel Zarembski |
0:01f31e923fe2 | 434 | base->C4 |= UART_C4_TDMAS_MASK; |
Pawel Zarembski |
0:01f31e923fe2 | 435 | #else |
Pawel Zarembski |
0:01f31e923fe2 | 436 | base->C5 |= UART_C5_TDMAS_MASK; |
Pawel Zarembski |
0:01f31e923fe2 | 437 | #endif |
Pawel Zarembski |
0:01f31e923fe2 | 438 | base->C2 |= UART_C2_TIE_MASK; |
Pawel Zarembski |
0:01f31e923fe2 | 439 | } |
Pawel Zarembski |
0:01f31e923fe2 | 440 | else |
Pawel Zarembski |
0:01f31e923fe2 | 441 | { |
Pawel Zarembski |
0:01f31e923fe2 | 442 | #if (defined(FSL_FEATURE_UART_IS_SCI) && FSL_FEATURE_UART_IS_SCI) |
Pawel Zarembski |
0:01f31e923fe2 | 443 | base->C4 &= ~UART_C4_TDMAS_MASK; |
Pawel Zarembski |
0:01f31e923fe2 | 444 | #else |
Pawel Zarembski |
0:01f31e923fe2 | 445 | base->C5 &= ~UART_C5_TDMAS_MASK; |
Pawel Zarembski |
0:01f31e923fe2 | 446 | #endif |
Pawel Zarembski |
0:01f31e923fe2 | 447 | base->C2 &= ~UART_C2_TIE_MASK; |
Pawel Zarembski |
0:01f31e923fe2 | 448 | } |
Pawel Zarembski |
0:01f31e923fe2 | 449 | } |
Pawel Zarembski |
0:01f31e923fe2 | 450 | |
Pawel Zarembski |
0:01f31e923fe2 | 451 | /*! |
Pawel Zarembski |
0:01f31e923fe2 | 452 | * @brief Enables or disables the UART receiver DMA. |
Pawel Zarembski |
0:01f31e923fe2 | 453 | * |
Pawel Zarembski |
0:01f31e923fe2 | 454 | * This function enables or disables the receiver data register full flag, S1[RDRF], to generate DMA requests. |
Pawel Zarembski |
0:01f31e923fe2 | 455 | * |
Pawel Zarembski |
0:01f31e923fe2 | 456 | * @param base UART peripheral base address. |
Pawel Zarembski |
0:01f31e923fe2 | 457 | * @param enable True to enable, false to disable. |
Pawel Zarembski |
0:01f31e923fe2 | 458 | */ |
Pawel Zarembski |
0:01f31e923fe2 | 459 | static inline void UART_EnableRxDMA(UART_Type *base, bool enable) |
Pawel Zarembski |
0:01f31e923fe2 | 460 | { |
Pawel Zarembski |
0:01f31e923fe2 | 461 | if (enable) |
Pawel Zarembski |
0:01f31e923fe2 | 462 | { |
Pawel Zarembski |
0:01f31e923fe2 | 463 | #if (defined(FSL_FEATURE_UART_IS_SCI) && FSL_FEATURE_UART_IS_SCI) |
Pawel Zarembski |
0:01f31e923fe2 | 464 | base->C4 |= UART_C4_RDMAS_MASK; |
Pawel Zarembski |
0:01f31e923fe2 | 465 | #else |
Pawel Zarembski |
0:01f31e923fe2 | 466 | base->C5 |= UART_C5_RDMAS_MASK; |
Pawel Zarembski |
0:01f31e923fe2 | 467 | #endif |
Pawel Zarembski |
0:01f31e923fe2 | 468 | base->C2 |= UART_C2_RIE_MASK; |
Pawel Zarembski |
0:01f31e923fe2 | 469 | } |
Pawel Zarembski |
0:01f31e923fe2 | 470 | else |
Pawel Zarembski |
0:01f31e923fe2 | 471 | { |
Pawel Zarembski |
0:01f31e923fe2 | 472 | #if (defined(FSL_FEATURE_UART_IS_SCI) && FSL_FEATURE_UART_IS_SCI) |
Pawel Zarembski |
0:01f31e923fe2 | 473 | base->C4 &= ~UART_C4_RDMAS_MASK; |
Pawel Zarembski |
0:01f31e923fe2 | 474 | #else |
Pawel Zarembski |
0:01f31e923fe2 | 475 | base->C5 &= ~UART_C5_RDMAS_MASK; |
Pawel Zarembski |
0:01f31e923fe2 | 476 | #endif |
Pawel Zarembski |
0:01f31e923fe2 | 477 | base->C2 &= ~UART_C2_RIE_MASK; |
Pawel Zarembski |
0:01f31e923fe2 | 478 | } |
Pawel Zarembski |
0:01f31e923fe2 | 479 | } |
Pawel Zarembski |
0:01f31e923fe2 | 480 | |
Pawel Zarembski |
0:01f31e923fe2 | 481 | /* @} */ |
Pawel Zarembski |
0:01f31e923fe2 | 482 | #endif /* FSL_FEATURE_UART_HAS_DMA_SELECT */ |
Pawel Zarembski |
0:01f31e923fe2 | 483 | |
Pawel Zarembski |
0:01f31e923fe2 | 484 | /*! |
Pawel Zarembski |
0:01f31e923fe2 | 485 | * @name Bus Operations |
Pawel Zarembski |
0:01f31e923fe2 | 486 | * @{ |
Pawel Zarembski |
0:01f31e923fe2 | 487 | */ |
Pawel Zarembski |
0:01f31e923fe2 | 488 | |
Pawel Zarembski |
0:01f31e923fe2 | 489 | /*! |
Pawel Zarembski |
0:01f31e923fe2 | 490 | * @brief Enables or disables the UART transmitter. |
Pawel Zarembski |
0:01f31e923fe2 | 491 | * |
Pawel Zarembski |
0:01f31e923fe2 | 492 | * This function enables or disables the UART transmitter. |
Pawel Zarembski |
0:01f31e923fe2 | 493 | * |
Pawel Zarembski |
0:01f31e923fe2 | 494 | * @param base UART peripheral base address. |
Pawel Zarembski |
0:01f31e923fe2 | 495 | * @param enable True to enable, false to disable. |
Pawel Zarembski |
0:01f31e923fe2 | 496 | */ |
Pawel Zarembski |
0:01f31e923fe2 | 497 | static inline void UART_EnableTx(UART_Type *base, bool enable) |
Pawel Zarembski |
0:01f31e923fe2 | 498 | { |
Pawel Zarembski |
0:01f31e923fe2 | 499 | if (enable) |
Pawel Zarembski |
0:01f31e923fe2 | 500 | { |
Pawel Zarembski |
0:01f31e923fe2 | 501 | base->C2 |= UART_C2_TE_MASK; |
Pawel Zarembski |
0:01f31e923fe2 | 502 | } |
Pawel Zarembski |
0:01f31e923fe2 | 503 | else |
Pawel Zarembski |
0:01f31e923fe2 | 504 | { |
Pawel Zarembski |
0:01f31e923fe2 | 505 | base->C2 &= ~UART_C2_TE_MASK; |
Pawel Zarembski |
0:01f31e923fe2 | 506 | } |
Pawel Zarembski |
0:01f31e923fe2 | 507 | } |
Pawel Zarembski |
0:01f31e923fe2 | 508 | |
Pawel Zarembski |
0:01f31e923fe2 | 509 | /*! |
Pawel Zarembski |
0:01f31e923fe2 | 510 | * @brief Enables or disables the UART receiver. |
Pawel Zarembski |
0:01f31e923fe2 | 511 | * |
Pawel Zarembski |
0:01f31e923fe2 | 512 | * This function enables or disables the UART receiver. |
Pawel Zarembski |
0:01f31e923fe2 | 513 | * |
Pawel Zarembski |
0:01f31e923fe2 | 514 | * @param base UART peripheral base address. |
Pawel Zarembski |
0:01f31e923fe2 | 515 | * @param enable True to enable, false to disable. |
Pawel Zarembski |
0:01f31e923fe2 | 516 | */ |
Pawel Zarembski |
0:01f31e923fe2 | 517 | static inline void UART_EnableRx(UART_Type *base, bool enable) |
Pawel Zarembski |
0:01f31e923fe2 | 518 | { |
Pawel Zarembski |
0:01f31e923fe2 | 519 | if (enable) |
Pawel Zarembski |
0:01f31e923fe2 | 520 | { |
Pawel Zarembski |
0:01f31e923fe2 | 521 | base->C2 |= UART_C2_RE_MASK; |
Pawel Zarembski |
0:01f31e923fe2 | 522 | } |
Pawel Zarembski |
0:01f31e923fe2 | 523 | else |
Pawel Zarembski |
0:01f31e923fe2 | 524 | { |
Pawel Zarembski |
0:01f31e923fe2 | 525 | base->C2 &= ~UART_C2_RE_MASK; |
Pawel Zarembski |
0:01f31e923fe2 | 526 | } |
Pawel Zarembski |
0:01f31e923fe2 | 527 | } |
Pawel Zarembski |
0:01f31e923fe2 | 528 | |
Pawel Zarembski |
0:01f31e923fe2 | 529 | /*! |
Pawel Zarembski |
0:01f31e923fe2 | 530 | * @brief Writes to the TX register. |
Pawel Zarembski |
0:01f31e923fe2 | 531 | * |
Pawel Zarembski |
0:01f31e923fe2 | 532 | * This function writes data to the TX register directly. The upper layer must ensure |
Pawel Zarembski |
0:01f31e923fe2 | 533 | * that the TX register is empty or TX FIFO has empty room before calling this function. |
Pawel Zarembski |
0:01f31e923fe2 | 534 | * |
Pawel Zarembski |
0:01f31e923fe2 | 535 | * @param base UART peripheral base address. |
Pawel Zarembski |
0:01f31e923fe2 | 536 | * @param data The byte to write. |
Pawel Zarembski |
0:01f31e923fe2 | 537 | */ |
Pawel Zarembski |
0:01f31e923fe2 | 538 | static inline void UART_WriteByte(UART_Type *base, uint8_t data) |
Pawel Zarembski |
0:01f31e923fe2 | 539 | { |
Pawel Zarembski |
0:01f31e923fe2 | 540 | base->D = data; |
Pawel Zarembski |
0:01f31e923fe2 | 541 | } |
Pawel Zarembski |
0:01f31e923fe2 | 542 | |
Pawel Zarembski |
0:01f31e923fe2 | 543 | /*! |
Pawel Zarembski |
0:01f31e923fe2 | 544 | * @brief Reads the RX register directly. |
Pawel Zarembski |
0:01f31e923fe2 | 545 | * |
Pawel Zarembski |
0:01f31e923fe2 | 546 | * This function reads data from the RX register directly. The upper layer must |
Pawel Zarembski |
0:01f31e923fe2 | 547 | * ensure that the RX register is full or that the TX FIFO has data before calling this function. |
Pawel Zarembski |
0:01f31e923fe2 | 548 | * |
Pawel Zarembski |
0:01f31e923fe2 | 549 | * @param base UART peripheral base address. |
Pawel Zarembski |
0:01f31e923fe2 | 550 | * @return The byte read from UART data register. |
Pawel Zarembski |
0:01f31e923fe2 | 551 | */ |
Pawel Zarembski |
0:01f31e923fe2 | 552 | static inline uint8_t UART_ReadByte(UART_Type *base) |
Pawel Zarembski |
0:01f31e923fe2 | 553 | { |
Pawel Zarembski |
0:01f31e923fe2 | 554 | return base->D; |
Pawel Zarembski |
0:01f31e923fe2 | 555 | } |
Pawel Zarembski |
0:01f31e923fe2 | 556 | |
Pawel Zarembski |
0:01f31e923fe2 | 557 | /*! |
Pawel Zarembski |
0:01f31e923fe2 | 558 | * @brief Writes to the TX register using a blocking method. |
Pawel Zarembski |
0:01f31e923fe2 | 559 | * |
Pawel Zarembski |
0:01f31e923fe2 | 560 | * This function polls the TX register, waits for the TX register to be empty or for the TX FIFO |
Pawel Zarembski |
0:01f31e923fe2 | 561 | * to have room and writes data to the TX buffer. |
Pawel Zarembski |
0:01f31e923fe2 | 562 | * |
Pawel Zarembski |
0:01f31e923fe2 | 563 | * @note This function does not check whether all data is sent out to the bus. |
Pawel Zarembski |
0:01f31e923fe2 | 564 | * Before disabling the TX, check kUART_TransmissionCompleteFlag to ensure that the TX is |
Pawel Zarembski |
0:01f31e923fe2 | 565 | * finished. |
Pawel Zarembski |
0:01f31e923fe2 | 566 | * |
Pawel Zarembski |
0:01f31e923fe2 | 567 | * @param base UART peripheral base address. |
Pawel Zarembski |
0:01f31e923fe2 | 568 | * @param data Start address of the data to write. |
Pawel Zarembski |
0:01f31e923fe2 | 569 | * @param length Size of the data to write. |
Pawel Zarembski |
0:01f31e923fe2 | 570 | */ |
Pawel Zarembski |
0:01f31e923fe2 | 571 | void UART_WriteBlocking(UART_Type *base, const uint8_t *data, size_t length); |
Pawel Zarembski |
0:01f31e923fe2 | 572 | |
Pawel Zarembski |
0:01f31e923fe2 | 573 | /*! |
Pawel Zarembski |
0:01f31e923fe2 | 574 | * @brief Read RX data register using a blocking method. |
Pawel Zarembski |
0:01f31e923fe2 | 575 | * |
Pawel Zarembski |
0:01f31e923fe2 | 576 | * This function polls the RX register, waits for the RX register to be full or for RX FIFO to |
Pawel Zarembski |
0:01f31e923fe2 | 577 | * have data, and reads data from the TX register. |
Pawel Zarembski |
0:01f31e923fe2 | 578 | * |
Pawel Zarembski |
0:01f31e923fe2 | 579 | * @param base UART peripheral base address. |
Pawel Zarembski |
0:01f31e923fe2 | 580 | * @param data Start address of the buffer to store the received data. |
Pawel Zarembski |
0:01f31e923fe2 | 581 | * @param length Size of the buffer. |
Pawel Zarembski |
0:01f31e923fe2 | 582 | * @retval kStatus_UART_RxHardwareOverrun Receiver overrun occurred while receiving data. |
Pawel Zarembski |
0:01f31e923fe2 | 583 | * @retval kStatus_UART_NoiseError A noise error occurred while receiving data. |
Pawel Zarembski |
0:01f31e923fe2 | 584 | * @retval kStatus_UART_FramingError A framing error occurred while receiving data. |
Pawel Zarembski |
0:01f31e923fe2 | 585 | * @retval kStatus_UART_ParityError A parity error occurred while receiving data. |
Pawel Zarembski |
0:01f31e923fe2 | 586 | * @retval kStatus_Success Successfully received all data. |
Pawel Zarembski |
0:01f31e923fe2 | 587 | */ |
Pawel Zarembski |
0:01f31e923fe2 | 588 | status_t UART_ReadBlocking(UART_Type *base, uint8_t *data, size_t length); |
Pawel Zarembski |
0:01f31e923fe2 | 589 | |
Pawel Zarembski |
0:01f31e923fe2 | 590 | /* @} */ |
Pawel Zarembski |
0:01f31e923fe2 | 591 | |
Pawel Zarembski |
0:01f31e923fe2 | 592 | /*! |
Pawel Zarembski |
0:01f31e923fe2 | 593 | * @name Transactional |
Pawel Zarembski |
0:01f31e923fe2 | 594 | * @{ |
Pawel Zarembski |
0:01f31e923fe2 | 595 | */ |
Pawel Zarembski |
0:01f31e923fe2 | 596 | |
Pawel Zarembski |
0:01f31e923fe2 | 597 | /*! |
Pawel Zarembski |
0:01f31e923fe2 | 598 | * @brief Initializes the UART handle. |
Pawel Zarembski |
0:01f31e923fe2 | 599 | * |
Pawel Zarembski |
0:01f31e923fe2 | 600 | * This function initializes the UART handle which can be used for other UART |
Pawel Zarembski |
0:01f31e923fe2 | 601 | * transactional APIs. Usually, for a specified UART instance, |
Pawel Zarembski |
0:01f31e923fe2 | 602 | * call this API once to get the initialized handle. |
Pawel Zarembski |
0:01f31e923fe2 | 603 | * |
Pawel Zarembski |
0:01f31e923fe2 | 604 | * @param base UART peripheral base address. |
Pawel Zarembski |
0:01f31e923fe2 | 605 | * @param handle UART handle pointer. |
Pawel Zarembski |
0:01f31e923fe2 | 606 | * @param callback The callback function. |
Pawel Zarembski |
0:01f31e923fe2 | 607 | * @param userData The parameter of the callback function. |
Pawel Zarembski |
0:01f31e923fe2 | 608 | */ |
Pawel Zarembski |
0:01f31e923fe2 | 609 | void UART_TransferCreateHandle(UART_Type *base, |
Pawel Zarembski |
0:01f31e923fe2 | 610 | uart_handle_t *handle, |
Pawel Zarembski |
0:01f31e923fe2 | 611 | uart_transfer_callback_t callback, |
Pawel Zarembski |
0:01f31e923fe2 | 612 | void *userData); |
Pawel Zarembski |
0:01f31e923fe2 | 613 | |
Pawel Zarembski |
0:01f31e923fe2 | 614 | /*! |
Pawel Zarembski |
0:01f31e923fe2 | 615 | * @brief Sets up the RX ring buffer. |
Pawel Zarembski |
0:01f31e923fe2 | 616 | * |
Pawel Zarembski |
0:01f31e923fe2 | 617 | * This function sets up the RX ring buffer to a specific UART handle. |
Pawel Zarembski |
0:01f31e923fe2 | 618 | * |
Pawel Zarembski |
0:01f31e923fe2 | 619 | * When the RX ring buffer is used, data received are stored into the ring buffer even when the |
Pawel Zarembski |
0:01f31e923fe2 | 620 | * user doesn't call the UART_TransferReceiveNonBlocking() API. If data is already received |
Pawel Zarembski |
0:01f31e923fe2 | 621 | * in the ring buffer, the user can get the received data from the ring buffer directly. |
Pawel Zarembski |
0:01f31e923fe2 | 622 | * |
Pawel Zarembski |
0:01f31e923fe2 | 623 | * @note When using the RX ring buffer, one byte is reserved for internal use. In other |
Pawel Zarembski |
0:01f31e923fe2 | 624 | * words, if @p ringBufferSize is 32, only 31 bytes are used for saving data. |
Pawel Zarembski |
0:01f31e923fe2 | 625 | * |
Pawel Zarembski |
0:01f31e923fe2 | 626 | * @param base UART peripheral base address. |
Pawel Zarembski |
0:01f31e923fe2 | 627 | * @param handle UART handle pointer. |
Pawel Zarembski |
0:01f31e923fe2 | 628 | * @param ringBuffer Start address of the ring buffer for background receiving. Pass NULL to disable the ring buffer. |
Pawel Zarembski |
0:01f31e923fe2 | 629 | * @param ringBufferSize Size of the ring buffer. |
Pawel Zarembski |
0:01f31e923fe2 | 630 | */ |
Pawel Zarembski |
0:01f31e923fe2 | 631 | void UART_TransferStartRingBuffer(UART_Type *base, uart_handle_t *handle, uint8_t *ringBuffer, size_t ringBufferSize); |
Pawel Zarembski |
0:01f31e923fe2 | 632 | |
Pawel Zarembski |
0:01f31e923fe2 | 633 | /*! |
Pawel Zarembski |
0:01f31e923fe2 | 634 | * @brief Aborts the background transfer and uninstalls the ring buffer. |
Pawel Zarembski |
0:01f31e923fe2 | 635 | * |
Pawel Zarembski |
0:01f31e923fe2 | 636 | * This function aborts the background transfer and uninstalls the ring buffer. |
Pawel Zarembski |
0:01f31e923fe2 | 637 | * |
Pawel Zarembski |
0:01f31e923fe2 | 638 | * @param base UART peripheral base address. |
Pawel Zarembski |
0:01f31e923fe2 | 639 | * @param handle UART handle pointer. |
Pawel Zarembski |
0:01f31e923fe2 | 640 | */ |
Pawel Zarembski |
0:01f31e923fe2 | 641 | void UART_TransferStopRingBuffer(UART_Type *base, uart_handle_t *handle); |
Pawel Zarembski |
0:01f31e923fe2 | 642 | |
Pawel Zarembski |
0:01f31e923fe2 | 643 | /*! |
Pawel Zarembski |
0:01f31e923fe2 | 644 | * @brief Get the length of received data in RX ring buffer. |
Pawel Zarembski |
0:01f31e923fe2 | 645 | * |
Pawel Zarembski |
0:01f31e923fe2 | 646 | * @param handle UART handle pointer. |
Pawel Zarembski |
0:01f31e923fe2 | 647 | * @return Length of received data in RX ring buffer. |
Pawel Zarembski |
0:01f31e923fe2 | 648 | */ |
Pawel Zarembski |
0:01f31e923fe2 | 649 | size_t UART_TransferGetRxRingBufferLength(uart_handle_t *handle); |
Pawel Zarembski |
0:01f31e923fe2 | 650 | |
Pawel Zarembski |
0:01f31e923fe2 | 651 | /*! |
Pawel Zarembski |
0:01f31e923fe2 | 652 | * @brief Transmits a buffer of data using the interrupt method. |
Pawel Zarembski |
0:01f31e923fe2 | 653 | * |
Pawel Zarembski |
0:01f31e923fe2 | 654 | * This function sends data using an interrupt method. This is a non-blocking function, which |
Pawel Zarembski |
0:01f31e923fe2 | 655 | * returns directly without waiting for all data to be written to the TX register. When |
Pawel Zarembski |
0:01f31e923fe2 | 656 | * all data is written to the TX register in the ISR, the UART driver calls the callback |
Pawel Zarembski |
0:01f31e923fe2 | 657 | * function and passes the @ref kStatus_UART_TxIdle as status parameter. |
Pawel Zarembski |
0:01f31e923fe2 | 658 | * |
Pawel Zarembski |
0:01f31e923fe2 | 659 | * @note The kStatus_UART_TxIdle is passed to the upper layer when all data is written |
Pawel Zarembski |
0:01f31e923fe2 | 660 | * to the TX register. However, it does not ensure that all data is sent out. Before disabling the TX, |
Pawel Zarembski |
0:01f31e923fe2 | 661 | * check the kUART_TransmissionCompleteFlag to ensure that the TX is finished. |
Pawel Zarembski |
0:01f31e923fe2 | 662 | * |
Pawel Zarembski |
0:01f31e923fe2 | 663 | * @param base UART peripheral base address. |
Pawel Zarembski |
0:01f31e923fe2 | 664 | * @param handle UART handle pointer. |
Pawel Zarembski |
0:01f31e923fe2 | 665 | * @param xfer UART transfer structure. See #uart_transfer_t. |
Pawel Zarembski |
0:01f31e923fe2 | 666 | * @retval kStatus_Success Successfully start the data transmission. |
Pawel Zarembski |
0:01f31e923fe2 | 667 | * @retval kStatus_UART_TxBusy Previous transmission still not finished; data not all written to TX register yet. |
Pawel Zarembski |
0:01f31e923fe2 | 668 | * @retval kStatus_InvalidArgument Invalid argument. |
Pawel Zarembski |
0:01f31e923fe2 | 669 | */ |
Pawel Zarembski |
0:01f31e923fe2 | 670 | status_t UART_TransferSendNonBlocking(UART_Type *base, uart_handle_t *handle, uart_transfer_t *xfer); |
Pawel Zarembski |
0:01f31e923fe2 | 671 | |
Pawel Zarembski |
0:01f31e923fe2 | 672 | /*! |
Pawel Zarembski |
0:01f31e923fe2 | 673 | * @brief Aborts the interrupt-driven data transmit. |
Pawel Zarembski |
0:01f31e923fe2 | 674 | * |
Pawel Zarembski |
0:01f31e923fe2 | 675 | * This function aborts the interrupt-driven data sending. The user can get the remainBytes to find out |
Pawel Zarembski |
0:01f31e923fe2 | 676 | * how many bytes are not sent out. |
Pawel Zarembski |
0:01f31e923fe2 | 677 | * |
Pawel Zarembski |
0:01f31e923fe2 | 678 | * @param base UART peripheral base address. |
Pawel Zarembski |
0:01f31e923fe2 | 679 | * @param handle UART handle pointer. |
Pawel Zarembski |
0:01f31e923fe2 | 680 | */ |
Pawel Zarembski |
0:01f31e923fe2 | 681 | void UART_TransferAbortSend(UART_Type *base, uart_handle_t *handle); |
Pawel Zarembski |
0:01f31e923fe2 | 682 | |
Pawel Zarembski |
0:01f31e923fe2 | 683 | /*! |
Pawel Zarembski |
0:01f31e923fe2 | 684 | * @brief Gets the number of bytes written to the UART TX register. |
Pawel Zarembski |
0:01f31e923fe2 | 685 | * |
Pawel Zarembski |
0:01f31e923fe2 | 686 | * This function gets the number of bytes written to the UART TX |
Pawel Zarembski |
0:01f31e923fe2 | 687 | * register by using the interrupt method. |
Pawel Zarembski |
0:01f31e923fe2 | 688 | * |
Pawel Zarembski |
0:01f31e923fe2 | 689 | * @param base UART peripheral base address. |
Pawel Zarembski |
0:01f31e923fe2 | 690 | * @param handle UART handle pointer. |
Pawel Zarembski |
0:01f31e923fe2 | 691 | * @param count Send bytes count. |
Pawel Zarembski |
0:01f31e923fe2 | 692 | * @retval kStatus_NoTransferInProgress No send in progress. |
Pawel Zarembski |
0:01f31e923fe2 | 693 | * @retval kStatus_InvalidArgument The parameter is invalid. |
Pawel Zarembski |
0:01f31e923fe2 | 694 | * @retval kStatus_Success Get successfully through the parameter \p count; |
Pawel Zarembski |
0:01f31e923fe2 | 695 | */ |
Pawel Zarembski |
0:01f31e923fe2 | 696 | status_t UART_TransferGetSendCount(UART_Type *base, uart_handle_t *handle, uint32_t *count); |
Pawel Zarembski |
0:01f31e923fe2 | 697 | |
Pawel Zarembski |
0:01f31e923fe2 | 698 | /*! |
Pawel Zarembski |
0:01f31e923fe2 | 699 | * @brief Receives a buffer of data using an interrupt method. |
Pawel Zarembski |
0:01f31e923fe2 | 700 | * |
Pawel Zarembski |
0:01f31e923fe2 | 701 | * This function receives data using an interrupt method. This is a non-blocking function, which |
Pawel Zarembski |
0:01f31e923fe2 | 702 | * returns without waiting for all data to be received. |
Pawel Zarembski |
0:01f31e923fe2 | 703 | * If the RX ring buffer is used and not empty, the data in the ring buffer is copied and |
Pawel Zarembski |
0:01f31e923fe2 | 704 | * the parameter @p receivedBytes shows how many bytes are copied from the ring buffer. |
Pawel Zarembski |
0:01f31e923fe2 | 705 | * After copying, if the data in the ring buffer is not enough to read, the receive |
Pawel Zarembski |
0:01f31e923fe2 | 706 | * request is saved by the UART driver. When the new data arrives, the receive request |
Pawel Zarembski |
0:01f31e923fe2 | 707 | * is serviced first. When all data is received, the UART driver notifies the upper layer |
Pawel Zarembski |
0:01f31e923fe2 | 708 | * through a callback function and passes the status parameter @ref kStatus_UART_RxIdle. |
Pawel Zarembski |
0:01f31e923fe2 | 709 | * For example, the upper layer needs 10 bytes but there are only 5 bytes in the ring buffer. |
Pawel Zarembski |
0:01f31e923fe2 | 710 | * The 5 bytes are copied to the xfer->data and this function returns with the |
Pawel Zarembski |
0:01f31e923fe2 | 711 | * parameter @p receivedBytes set to 5. For the left 5 bytes, newly arrived data is |
Pawel Zarembski |
0:01f31e923fe2 | 712 | * saved from the xfer->data[5]. When 5 bytes are received, the UART driver notifies the upper layer. |
Pawel Zarembski |
0:01f31e923fe2 | 713 | * If the RX ring buffer is not enabled, this function enables the RX and RX interrupt |
Pawel Zarembski |
0:01f31e923fe2 | 714 | * to receive data to the xfer->data. When all data is received, the upper layer is notified. |
Pawel Zarembski |
0:01f31e923fe2 | 715 | * |
Pawel Zarembski |
0:01f31e923fe2 | 716 | * @param base UART peripheral base address. |
Pawel Zarembski |
0:01f31e923fe2 | 717 | * @param handle UART handle pointer. |
Pawel Zarembski |
0:01f31e923fe2 | 718 | * @param xfer UART transfer structure, see #uart_transfer_t. |
Pawel Zarembski |
0:01f31e923fe2 | 719 | * @param receivedBytes Bytes received from the ring buffer directly. |
Pawel Zarembski |
0:01f31e923fe2 | 720 | * @retval kStatus_Success Successfully queue the transfer into transmit queue. |
Pawel Zarembski |
0:01f31e923fe2 | 721 | * @retval kStatus_UART_RxBusy Previous receive request is not finished. |
Pawel Zarembski |
0:01f31e923fe2 | 722 | * @retval kStatus_InvalidArgument Invalid argument. |
Pawel Zarembski |
0:01f31e923fe2 | 723 | */ |
Pawel Zarembski |
0:01f31e923fe2 | 724 | status_t UART_TransferReceiveNonBlocking(UART_Type *base, |
Pawel Zarembski |
0:01f31e923fe2 | 725 | uart_handle_t *handle, |
Pawel Zarembski |
0:01f31e923fe2 | 726 | uart_transfer_t *xfer, |
Pawel Zarembski |
0:01f31e923fe2 | 727 | size_t *receivedBytes); |
Pawel Zarembski |
0:01f31e923fe2 | 728 | |
Pawel Zarembski |
0:01f31e923fe2 | 729 | /*! |
Pawel Zarembski |
0:01f31e923fe2 | 730 | * @brief Aborts the interrupt-driven data receiving. |
Pawel Zarembski |
0:01f31e923fe2 | 731 | * |
Pawel Zarembski |
0:01f31e923fe2 | 732 | * This function aborts the interrupt-driven data receiving. The user can get the remainBytes to know |
Pawel Zarembski |
0:01f31e923fe2 | 733 | * how many bytes are not received yet. |
Pawel Zarembski |
0:01f31e923fe2 | 734 | * |
Pawel Zarembski |
0:01f31e923fe2 | 735 | * @param base UART peripheral base address. |
Pawel Zarembski |
0:01f31e923fe2 | 736 | * @param handle UART handle pointer. |
Pawel Zarembski |
0:01f31e923fe2 | 737 | */ |
Pawel Zarembski |
0:01f31e923fe2 | 738 | void UART_TransferAbortReceive(UART_Type *base, uart_handle_t *handle); |
Pawel Zarembski |
0:01f31e923fe2 | 739 | |
Pawel Zarembski |
0:01f31e923fe2 | 740 | /*! |
Pawel Zarembski |
0:01f31e923fe2 | 741 | * @brief Gets the number of bytes that have been received. |
Pawel Zarembski |
0:01f31e923fe2 | 742 | * |
Pawel Zarembski |
0:01f31e923fe2 | 743 | * This function gets the number of bytes that have been received. |
Pawel Zarembski |
0:01f31e923fe2 | 744 | * |
Pawel Zarembski |
0:01f31e923fe2 | 745 | * @param base UART peripheral base address. |
Pawel Zarembski |
0:01f31e923fe2 | 746 | * @param handle UART handle pointer. |
Pawel Zarembski |
0:01f31e923fe2 | 747 | * @param count Receive bytes count. |
Pawel Zarembski |
0:01f31e923fe2 | 748 | * @retval kStatus_NoTransferInProgress No receive in progress. |
Pawel Zarembski |
0:01f31e923fe2 | 749 | * @retval kStatus_InvalidArgument Parameter is invalid. |
Pawel Zarembski |
0:01f31e923fe2 | 750 | * @retval kStatus_Success Get successfully through the parameter \p count; |
Pawel Zarembski |
0:01f31e923fe2 | 751 | */ |
Pawel Zarembski |
0:01f31e923fe2 | 752 | status_t UART_TransferGetReceiveCount(UART_Type *base, uart_handle_t *handle, uint32_t *count); |
Pawel Zarembski |
0:01f31e923fe2 | 753 | |
Pawel Zarembski |
0:01f31e923fe2 | 754 | /*! |
Pawel Zarembski |
0:01f31e923fe2 | 755 | * @brief UART IRQ handle function. |
Pawel Zarembski |
0:01f31e923fe2 | 756 | * |
Pawel Zarembski |
0:01f31e923fe2 | 757 | * This function handles the UART transmit and receive IRQ request. |
Pawel Zarembski |
0:01f31e923fe2 | 758 | * |
Pawel Zarembski |
0:01f31e923fe2 | 759 | * @param base UART peripheral base address. |
Pawel Zarembski |
0:01f31e923fe2 | 760 | * @param handle UART handle pointer. |
Pawel Zarembski |
0:01f31e923fe2 | 761 | */ |
Pawel Zarembski |
0:01f31e923fe2 | 762 | void UART_TransferHandleIRQ(UART_Type *base, uart_handle_t *handle); |
Pawel Zarembski |
0:01f31e923fe2 | 763 | |
Pawel Zarembski |
0:01f31e923fe2 | 764 | /*! |
Pawel Zarembski |
0:01f31e923fe2 | 765 | * @brief UART Error IRQ handle function. |
Pawel Zarembski |
0:01f31e923fe2 | 766 | * |
Pawel Zarembski |
0:01f31e923fe2 | 767 | * This function handles the UART error IRQ request. |
Pawel Zarembski |
0:01f31e923fe2 | 768 | * |
Pawel Zarembski |
0:01f31e923fe2 | 769 | * @param base UART peripheral base address. |
Pawel Zarembski |
0:01f31e923fe2 | 770 | * @param handle UART handle pointer. |
Pawel Zarembski |
0:01f31e923fe2 | 771 | */ |
Pawel Zarembski |
0:01f31e923fe2 | 772 | void UART_TransferHandleErrorIRQ(UART_Type *base, uart_handle_t *handle); |
Pawel Zarembski |
0:01f31e923fe2 | 773 | |
Pawel Zarembski |
0:01f31e923fe2 | 774 | /* @} */ |
Pawel Zarembski |
0:01f31e923fe2 | 775 | |
Pawel Zarembski |
0:01f31e923fe2 | 776 | #if defined(__cplusplus) |
Pawel Zarembski |
0:01f31e923fe2 | 777 | } |
Pawel Zarembski |
0:01f31e923fe2 | 778 | #endif |
Pawel Zarembski |
0:01f31e923fe2 | 779 | |
Pawel Zarembski |
0:01f31e923fe2 | 780 | /*! @}*/ |
Pawel Zarembski |
0:01f31e923fe2 | 781 | |
Pawel Zarembski |
0:01f31e923fe2 | 782 | #endif /* _FSL_UART_H_ */ |