Arrow / Mbed OS DAPLink Reset

Repostiory containing DAPLink source code with Reset Pin workaround for HANI_IOT board.

Upstream: https://github.com/ARMmbed/DAPLink

source/hic_hal/atmel/sam3u2c/instance/tc0.h@0:01f31e923fe2, 2020-04-07 (annotated)

Committer:
Pawel Zarembski
Date:
Tue Apr 07 12:55:42 2020 +0200
Revision:
0:01f31e923fe2
hani: DAPLink with reset workaround

Who changed what in which revision?

UserRevisionLine numberNew contents of line
Pawel Zarembski 0:01f31e923fe2 1 /* ---------------------------------------------------------------------------- */
Pawel Zarembski 0:01f31e923fe2 2 /* Atmel Microcontroller Software Support */
Pawel Zarembski 0:01f31e923fe2 3 /* SAM Software Package License */
Pawel Zarembski 0:01f31e923fe2 4 /* ---------------------------------------------------------------------------- */
Pawel Zarembski 0:01f31e923fe2 5 /* Copyright (c) %copyright_year%, Atmel Corporation */
Pawel Zarembski 0:01f31e923fe2 6 /* */
Pawel Zarembski 0:01f31e923fe2 7 /* All rights reserved. */
Pawel Zarembski 0:01f31e923fe2 8 /* */
Pawel Zarembski 0:01f31e923fe2 9 /* Redistribution and use in source and binary forms, with or without */
Pawel Zarembski 0:01f31e923fe2 10 /* modification, are permitted provided that the following condition is met: */
Pawel Zarembski 0:01f31e923fe2 11 /* */
Pawel Zarembski 0:01f31e923fe2 12 /* - Redistributions of source code must retain the above copyright notice, */
Pawel Zarembski 0:01f31e923fe2 13 /* this list of conditions and the disclaimer below. */
Pawel Zarembski 0:01f31e923fe2 14 /* */
Pawel Zarembski 0:01f31e923fe2 15 /* Atmel's name may not be used to endorse or promote products derived from */
Pawel Zarembski 0:01f31e923fe2 16 /* this software without specific prior written permission. */
Pawel Zarembski 0:01f31e923fe2 17 /* */
Pawel Zarembski 0:01f31e923fe2 18 /* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */
Pawel Zarembski 0:01f31e923fe2 19 /* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */
Pawel Zarembski 0:01f31e923fe2 20 /* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */
Pawel Zarembski 0:01f31e923fe2 21 /* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */
Pawel Zarembski 0:01f31e923fe2 22 /* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */
Pawel Zarembski 0:01f31e923fe2 23 /* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */
Pawel Zarembski 0:01f31e923fe2 24 /* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */
Pawel Zarembski 0:01f31e923fe2 25 /* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */
Pawel Zarembski 0:01f31e923fe2 26 /* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */
Pawel Zarembski 0:01f31e923fe2 27 /* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */
Pawel Zarembski 0:01f31e923fe2 28 /* ---------------------------------------------------------------------------- */
Pawel Zarembski 0:01f31e923fe2 29
Pawel Zarembski 0:01f31e923fe2 30 #ifndef _SAM3U_TC0_INSTANCE_
Pawel Zarembski 0:01f31e923fe2 31 #define _SAM3U_TC0_INSTANCE_
Pawel Zarembski 0:01f31e923fe2 32
Pawel Zarembski 0:01f31e923fe2 33 /* ========== Register definition for TC0 peripheral ========== */
Pawel Zarembski 0:01f31e923fe2 34 #if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
Pawel Zarembski 0:01f31e923fe2 35 #define REG_TC0_CCR0 (0x40080000U) /**< \brief (TC0) Channel Control Register (channel = 0) */
Pawel Zarembski 0:01f31e923fe2 36 #define REG_TC0_CMR0 (0x40080004U) /**< \brief (TC0) Channel Mode Register (channel = 0) */
Pawel Zarembski 0:01f31e923fe2 37 #define REG_TC0_CV0 (0x40080010U) /**< \brief (TC0) Counter Value (channel = 0) */
Pawel Zarembski 0:01f31e923fe2 38 #define REG_TC0_RA0 (0x40080014U) /**< \brief (TC0) Register A (channel = 0) */
Pawel Zarembski 0:01f31e923fe2 39 #define REG_TC0_RB0 (0x40080018U) /**< \brief (TC0) Register B (channel = 0) */
Pawel Zarembski 0:01f31e923fe2 40 #define REG_TC0_RC0 (0x4008001CU) /**< \brief (TC0) Register C (channel = 0) */
Pawel Zarembski 0:01f31e923fe2 41 #define REG_TC0_SR0 (0x40080020U) /**< \brief (TC0) Status Register (channel = 0) */
Pawel Zarembski 0:01f31e923fe2 42 #define REG_TC0_IER0 (0x40080024U) /**< \brief (TC0) Interrupt Enable Register (channel = 0) */
Pawel Zarembski 0:01f31e923fe2 43 #define REG_TC0_IDR0 (0x40080028U) /**< \brief (TC0) Interrupt Disable Register (channel = 0) */
Pawel Zarembski 0:01f31e923fe2 44 #define REG_TC0_IMR0 (0x4008002CU) /**< \brief (TC0) Interrupt Mask Register (channel = 0) */
Pawel Zarembski 0:01f31e923fe2 45 #define REG_TC0_CCR1 (0x40080040U) /**< \brief (TC0) Channel Control Register (channel = 1) */
Pawel Zarembski 0:01f31e923fe2 46 #define REG_TC0_CMR1 (0x40080044U) /**< \brief (TC0) Channel Mode Register (channel = 1) */
Pawel Zarembski 0:01f31e923fe2 47 #define REG_TC0_CV1 (0x40080050U) /**< \brief (TC0) Counter Value (channel = 1) */
Pawel Zarembski 0:01f31e923fe2 48 #define REG_TC0_RA1 (0x40080054U) /**< \brief (TC0) Register A (channel = 1) */
Pawel Zarembski 0:01f31e923fe2 49 #define REG_TC0_RB1 (0x40080058U) /**< \brief (TC0) Register B (channel = 1) */
Pawel Zarembski 0:01f31e923fe2 50 #define REG_TC0_RC1 (0x4008005CU) /**< \brief (TC0) Register C (channel = 1) */
Pawel Zarembski 0:01f31e923fe2 51 #define REG_TC0_SR1 (0x40080060U) /**< \brief (TC0) Status Register (channel = 1) */
Pawel Zarembski 0:01f31e923fe2 52 #define REG_TC0_IER1 (0x40080064U) /**< \brief (TC0) Interrupt Enable Register (channel = 1) */
Pawel Zarembski 0:01f31e923fe2 53 #define REG_TC0_IDR1 (0x40080068U) /**< \brief (TC0) Interrupt Disable Register (channel = 1) */
Pawel Zarembski 0:01f31e923fe2 54 #define REG_TC0_IMR1 (0x4008006CU) /**< \brief (TC0) Interrupt Mask Register (channel = 1) */
Pawel Zarembski 0:01f31e923fe2 55 #define REG_TC0_CCR2 (0x40080080U) /**< \brief (TC0) Channel Control Register (channel = 2) */
Pawel Zarembski 0:01f31e923fe2 56 #define REG_TC0_CMR2 (0x40080084U) /**< \brief (TC0) Channel Mode Register (channel = 2) */
Pawel Zarembski 0:01f31e923fe2 57 #define REG_TC0_CV2 (0x40080090U) /**< \brief (TC0) Counter Value (channel = 2) */
Pawel Zarembski 0:01f31e923fe2 58 #define REG_TC0_RA2 (0x40080094U) /**< \brief (TC0) Register A (channel = 2) */
Pawel Zarembski 0:01f31e923fe2 59 #define REG_TC0_RB2 (0x40080098U) /**< \brief (TC0) Register B (channel = 2) */
Pawel Zarembski 0:01f31e923fe2 60 #define REG_TC0_RC2 (0x4008009CU) /**< \brief (TC0) Register C (channel = 2) */
Pawel Zarembski 0:01f31e923fe2 61 #define REG_TC0_SR2 (0x400800A0U) /**< \brief (TC0) Status Register (channel = 2) */
Pawel Zarembski 0:01f31e923fe2 62 #define REG_TC0_IER2 (0x400800A4U) /**< \brief (TC0) Interrupt Enable Register (channel = 2) */
Pawel Zarembski 0:01f31e923fe2 63 #define REG_TC0_IDR2 (0x400800A8U) /**< \brief (TC0) Interrupt Disable Register (channel = 2) */
Pawel Zarembski 0:01f31e923fe2 64 #define REG_TC0_IMR2 (0x400800ACU) /**< \brief (TC0) Interrupt Mask Register (channel = 2) */
Pawel Zarembski 0:01f31e923fe2 65 #define REG_TC0_BCR (0x400800C0U) /**< \brief (TC0) Block Control Register */
Pawel Zarembski 0:01f31e923fe2 66 #define REG_TC0_BMR (0x400800C4U) /**< \brief (TC0) Block Mode Register */
Pawel Zarembski 0:01f31e923fe2 67 #define REG_TC0_QIER (0x400800C8U) /**< \brief (TC0) QDEC Interrupt Enable Register */
Pawel Zarembski 0:01f31e923fe2 68 #define REG_TC0_QIDR (0x400800CCU) /**< \brief (TC0) QDEC Interrupt Disable Register */
Pawel Zarembski 0:01f31e923fe2 69 #define REG_TC0_QIMR (0x400800D0U) /**< \brief (TC0) QDEC Interrupt Mask Register */
Pawel Zarembski 0:01f31e923fe2 70 #define REG_TC0_QISR (0x400800D4U) /**< \brief (TC0) QDEC Interrupt Status Register */
Pawel Zarembski 0:01f31e923fe2 71 #else
Pawel Zarembski 0:01f31e923fe2 72 #define REG_TC0_CCR0 (*(WoReg*)0x40080000U) /**< \brief (TC0) Channel Control Register (channel = 0) */
Pawel Zarembski 0:01f31e923fe2 73 #define REG_TC0_CMR0 (*(RwReg*)0x40080004U) /**< \brief (TC0) Channel Mode Register (channel = 0) */
Pawel Zarembski 0:01f31e923fe2 74 #define REG_TC0_CV0 (*(RoReg*)0x40080010U) /**< \brief (TC0) Counter Value (channel = 0) */
Pawel Zarembski 0:01f31e923fe2 75 #define REG_TC0_RA0 (*(RwReg*)0x40080014U) /**< \brief (TC0) Register A (channel = 0) */
Pawel Zarembski 0:01f31e923fe2 76 #define REG_TC0_RB0 (*(RwReg*)0x40080018U) /**< \brief (TC0) Register B (channel = 0) */
Pawel Zarembski 0:01f31e923fe2 77 #define REG_TC0_RC0 (*(RwReg*)0x4008001CU) /**< \brief (TC0) Register C (channel = 0) */
Pawel Zarembski 0:01f31e923fe2 78 #define REG_TC0_SR0 (*(RoReg*)0x40080020U) /**< \brief (TC0) Status Register (channel = 0) */
Pawel Zarembski 0:01f31e923fe2 79 #define REG_TC0_IER0 (*(WoReg*)0x40080024U) /**< \brief (TC0) Interrupt Enable Register (channel = 0) */
Pawel Zarembski 0:01f31e923fe2 80 #define REG_TC0_IDR0 (*(WoReg*)0x40080028U) /**< \brief (TC0) Interrupt Disable Register (channel = 0) */
Pawel Zarembski 0:01f31e923fe2 81 #define REG_TC0_IMR0 (*(RoReg*)0x4008002CU) /**< \brief (TC0) Interrupt Mask Register (channel = 0) */
Pawel Zarembski 0:01f31e923fe2 82 #define REG_TC0_CCR1 (*(WoReg*)0x40080040U) /**< \brief (TC0) Channel Control Register (channel = 1) */
Pawel Zarembski 0:01f31e923fe2 83 #define REG_TC0_CMR1 (*(RwReg*)0x40080044U) /**< \brief (TC0) Channel Mode Register (channel = 1) */
Pawel Zarembski 0:01f31e923fe2 84 #define REG_TC0_CV1 (*(RoReg*)0x40080050U) /**< \brief (TC0) Counter Value (channel = 1) */
Pawel Zarembski 0:01f31e923fe2 85 #define REG_TC0_RA1 (*(RwReg*)0x40080054U) /**< \brief (TC0) Register A (channel = 1) */
Pawel Zarembski 0:01f31e923fe2 86 #define REG_TC0_RB1 (*(RwReg*)0x40080058U) /**< \brief (TC0) Register B (channel = 1) */
Pawel Zarembski 0:01f31e923fe2 87 #define REG_TC0_RC1 (*(RwReg*)0x4008005CU) /**< \brief (TC0) Register C (channel = 1) */
Pawel Zarembski 0:01f31e923fe2 88 #define REG_TC0_SR1 (*(RoReg*)0x40080060U) /**< \brief (TC0) Status Register (channel = 1) */
Pawel Zarembski 0:01f31e923fe2 89 #define REG_TC0_IER1 (*(WoReg*)0x40080064U) /**< \brief (TC0) Interrupt Enable Register (channel = 1) */
Pawel Zarembski 0:01f31e923fe2 90 #define REG_TC0_IDR1 (*(WoReg*)0x40080068U) /**< \brief (TC0) Interrupt Disable Register (channel = 1) */
Pawel Zarembski 0:01f31e923fe2 91 #define REG_TC0_IMR1 (*(RoReg*)0x4008006CU) /**< \brief (TC0) Interrupt Mask Register (channel = 1) */
Pawel Zarembski 0:01f31e923fe2 92 #define REG_TC0_CCR2 (*(WoReg*)0x40080080U) /**< \brief (TC0) Channel Control Register (channel = 2) */
Pawel Zarembski 0:01f31e923fe2 93 #define REG_TC0_CMR2 (*(RwReg*)0x40080084U) /**< \brief (TC0) Channel Mode Register (channel = 2) */
Pawel Zarembski 0:01f31e923fe2 94 #define REG_TC0_CV2 (*(RoReg*)0x40080090U) /**< \brief (TC0) Counter Value (channel = 2) */
Pawel Zarembski 0:01f31e923fe2 95 #define REG_TC0_RA2 (*(RwReg*)0x40080094U) /**< \brief (TC0) Register A (channel = 2) */
Pawel Zarembski 0:01f31e923fe2 96 #define REG_TC0_RB2 (*(RwReg*)0x40080098U) /**< \brief (TC0) Register B (channel = 2) */
Pawel Zarembski 0:01f31e923fe2 97 #define REG_TC0_RC2 (*(RwReg*)0x4008009CU) /**< \brief (TC0) Register C (channel = 2) */
Pawel Zarembski 0:01f31e923fe2 98 #define REG_TC0_SR2 (*(RoReg*)0x400800A0U) /**< \brief (TC0) Status Register (channel = 2) */
Pawel Zarembski 0:01f31e923fe2 99 #define REG_TC0_IER2 (*(WoReg*)0x400800A4U) /**< \brief (TC0) Interrupt Enable Register (channel = 2) */
Pawel Zarembski 0:01f31e923fe2 100 #define REG_TC0_IDR2 (*(WoReg*)0x400800A8U) /**< \brief (TC0) Interrupt Disable Register (channel = 2) */
Pawel Zarembski 0:01f31e923fe2 101 #define REG_TC0_IMR2 (*(RoReg*)0x400800ACU) /**< \brief (TC0) Interrupt Mask Register (channel = 2) */
Pawel Zarembski 0:01f31e923fe2 102 #define REG_TC0_BCR (*(WoReg*)0x400800C0U) /**< \brief (TC0) Block Control Register */
Pawel Zarembski 0:01f31e923fe2 103 #define REG_TC0_BMR (*(RwReg*)0x400800C4U) /**< \brief (TC0) Block Mode Register */
Pawel Zarembski 0:01f31e923fe2 104 #define REG_TC0_QIER (*(WoReg*)0x400800C8U) /**< \brief (TC0) QDEC Interrupt Enable Register */
Pawel Zarembski 0:01f31e923fe2 105 #define REG_TC0_QIDR (*(WoReg*)0x400800CCU) /**< \brief (TC0) QDEC Interrupt Disable Register */
Pawel Zarembski 0:01f31e923fe2 106 #define REG_TC0_QIMR (*(RoReg*)0x400800D0U) /**< \brief (TC0) QDEC Interrupt Mask Register */
Pawel Zarembski 0:01f31e923fe2 107 #define REG_TC0_QISR (*(RoReg*)0x400800D4U) /**< \brief (TC0) QDEC Interrupt Status Register */
Pawel Zarembski 0:01f31e923fe2 108 #endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
Pawel Zarembski 0:01f31e923fe2 109
Pawel Zarembski 0:01f31e923fe2 110 #endif /* _SAM3U_TC0_INSTANCE_ */