Arrow / Mbed OS DAPLink Reset

Repostiory containing DAPLink source code with Reset Pin workaround for HANI_IOT board.

Upstream: https://github.com/ARMmbed/DAPLink

source/hic_hal/atmel/sam3u2c/instance/pioc.h@0:01f31e923fe2, 2020-04-07 (annotated)

Committer:
Pawel Zarembski
Date:
Tue Apr 07 12:55:42 2020 +0200
Revision:
0:01f31e923fe2
hani: DAPLink with reset workaround

Who changed what in which revision?

UserRevisionLine numberNew contents of line
Pawel Zarembski 0:01f31e923fe2 1 /* ---------------------------------------------------------------------------- */
Pawel Zarembski 0:01f31e923fe2 2 /* Atmel Microcontroller Software Support */
Pawel Zarembski 0:01f31e923fe2 3 /* SAM Software Package License */
Pawel Zarembski 0:01f31e923fe2 4 /* ---------------------------------------------------------------------------- */
Pawel Zarembski 0:01f31e923fe2 5 /* Copyright (c) %copyright_year%, Atmel Corporation */
Pawel Zarembski 0:01f31e923fe2 6 /* */
Pawel Zarembski 0:01f31e923fe2 7 /* All rights reserved. */
Pawel Zarembski 0:01f31e923fe2 8 /* */
Pawel Zarembski 0:01f31e923fe2 9 /* Redistribution and use in source and binary forms, with or without */
Pawel Zarembski 0:01f31e923fe2 10 /* modification, are permitted provided that the following condition is met: */
Pawel Zarembski 0:01f31e923fe2 11 /* */
Pawel Zarembski 0:01f31e923fe2 12 /* - Redistributions of source code must retain the above copyright notice, */
Pawel Zarembski 0:01f31e923fe2 13 /* this list of conditions and the disclaimer below. */
Pawel Zarembski 0:01f31e923fe2 14 /* */
Pawel Zarembski 0:01f31e923fe2 15 /* Atmel's name may not be used to endorse or promote products derived from */
Pawel Zarembski 0:01f31e923fe2 16 /* this software without specific prior written permission. */
Pawel Zarembski 0:01f31e923fe2 17 /* */
Pawel Zarembski 0:01f31e923fe2 18 /* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */
Pawel Zarembski 0:01f31e923fe2 19 /* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */
Pawel Zarembski 0:01f31e923fe2 20 /* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */
Pawel Zarembski 0:01f31e923fe2 21 /* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */
Pawel Zarembski 0:01f31e923fe2 22 /* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */
Pawel Zarembski 0:01f31e923fe2 23 /* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */
Pawel Zarembski 0:01f31e923fe2 24 /* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */
Pawel Zarembski 0:01f31e923fe2 25 /* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */
Pawel Zarembski 0:01f31e923fe2 26 /* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */
Pawel Zarembski 0:01f31e923fe2 27 /* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */
Pawel Zarembski 0:01f31e923fe2 28 /* ---------------------------------------------------------------------------- */
Pawel Zarembski 0:01f31e923fe2 29
Pawel Zarembski 0:01f31e923fe2 30 #ifndef _SAM3U_PIOC_INSTANCE_
Pawel Zarembski 0:01f31e923fe2 31 #define _SAM3U_PIOC_INSTANCE_
Pawel Zarembski 0:01f31e923fe2 32
Pawel Zarembski 0:01f31e923fe2 33 /* ========== Register definition for PIOC peripheral ========== */
Pawel Zarembski 0:01f31e923fe2 34 #if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
Pawel Zarembski 0:01f31e923fe2 35 #define REG_PIOC_PER (0x400E1000U) /**< \brief (PIOC) PIO Enable Register */
Pawel Zarembski 0:01f31e923fe2 36 #define REG_PIOC_PDR (0x400E1004U) /**< \brief (PIOC) PIO Disable Register */
Pawel Zarembski 0:01f31e923fe2 37 #define REG_PIOC_PSR (0x400E1008U) /**< \brief (PIOC) PIO Status Register */
Pawel Zarembski 0:01f31e923fe2 38 #define REG_PIOC_OER (0x400E1010U) /**< \brief (PIOC) Output Enable Register */
Pawel Zarembski 0:01f31e923fe2 39 #define REG_PIOC_ODR (0x400E1014U) /**< \brief (PIOC) Output Disable Register */
Pawel Zarembski 0:01f31e923fe2 40 #define REG_PIOC_OSR (0x400E1018U) /**< \brief (PIOC) Output Status Register */
Pawel Zarembski 0:01f31e923fe2 41 #define REG_PIOC_IFER (0x400E1020U) /**< \brief (PIOC) Glitch Input Filter Enable Register */
Pawel Zarembski 0:01f31e923fe2 42 #define REG_PIOC_IFDR (0x400E1024U) /**< \brief (PIOC) Glitch Input Filter Disable Register */
Pawel Zarembski 0:01f31e923fe2 43 #define REG_PIOC_IFSR (0x400E1028U) /**< \brief (PIOC) Glitch Input Filter Status Register */
Pawel Zarembski 0:01f31e923fe2 44 #define REG_PIOC_SODR (0x400E1030U) /**< \brief (PIOC) Set Output Data Register */
Pawel Zarembski 0:01f31e923fe2 45 #define REG_PIOC_CODR (0x400E1034U) /**< \brief (PIOC) Clear Output Data Register */
Pawel Zarembski 0:01f31e923fe2 46 #define REG_PIOC_ODSR (0x400E1038U) /**< \brief (PIOC) Output Data Status Register */
Pawel Zarembski 0:01f31e923fe2 47 #define REG_PIOC_PDSR (0x400E103CU) /**< \brief (PIOC) Pin Data Status Register */
Pawel Zarembski 0:01f31e923fe2 48 #define REG_PIOC_IER (0x400E1040U) /**< \brief (PIOC) Interrupt Enable Register */
Pawel Zarembski 0:01f31e923fe2 49 #define REG_PIOC_IDR (0x400E1044U) /**< \brief (PIOC) Interrupt Disable Register */
Pawel Zarembski 0:01f31e923fe2 50 #define REG_PIOC_IMR (0x400E1048U) /**< \brief (PIOC) Interrupt Mask Register */
Pawel Zarembski 0:01f31e923fe2 51 #define REG_PIOC_ISR (0x400E104CU) /**< \brief (PIOC) Interrupt Status Register */
Pawel Zarembski 0:01f31e923fe2 52 #define REG_PIOC_MDER (0x400E1050U) /**< \brief (PIOC) Multi-driver Enable Register */
Pawel Zarembski 0:01f31e923fe2 53 #define REG_PIOC_MDDR (0x400E1054U) /**< \brief (PIOC) Multi-driver Disable Register */
Pawel Zarembski 0:01f31e923fe2 54 #define REG_PIOC_MDSR (0x400E1058U) /**< \brief (PIOC) Multi-driver Status Register */
Pawel Zarembski 0:01f31e923fe2 55 #define REG_PIOC_PUDR (0x400E1060U) /**< \brief (PIOC) Pull-up Disable Register */
Pawel Zarembski 0:01f31e923fe2 56 #define REG_PIOC_PUER (0x400E1064U) /**< \brief (PIOC) Pull-up Enable Register */
Pawel Zarembski 0:01f31e923fe2 57 #define REG_PIOC_PUSR (0x400E1068U) /**< \brief (PIOC) Pad Pull-up Status Register */
Pawel Zarembski 0:01f31e923fe2 58 #define REG_PIOC_ABSR (0x400E1070U) /**< \brief (PIOC) Peripheral AB Select Register */
Pawel Zarembski 0:01f31e923fe2 59 #define REG_PIOC_SCIFSR (0x400E1080U) /**< \brief (PIOC) System Clock Glitch Input Filter Select Register */
Pawel Zarembski 0:01f31e923fe2 60 #define REG_PIOC_DIFSR (0x400E1084U) /**< \brief (PIOC) Debouncing Input Filter Select Register */
Pawel Zarembski 0:01f31e923fe2 61 #define REG_PIOC_IFDGSR (0x400E1088U) /**< \brief (PIOC) Glitch or Debouncing Input Filter Clock Selection Status Register */
Pawel Zarembski 0:01f31e923fe2 62 #define REG_PIOC_SCDR (0x400E108CU) /**< \brief (PIOC) Slow Clock Divider Debouncing Register */
Pawel Zarembski 0:01f31e923fe2 63 #define REG_PIOC_OWER (0x400E10A0U) /**< \brief (PIOC) Output Write Enable */
Pawel Zarembski 0:01f31e923fe2 64 #define REG_PIOC_OWDR (0x400E10A4U) /**< \brief (PIOC) Output Write Disable */
Pawel Zarembski 0:01f31e923fe2 65 #define REG_PIOC_OWSR (0x400E10A8U) /**< \brief (PIOC) Output Write Status Register */
Pawel Zarembski 0:01f31e923fe2 66 #define REG_PIOC_AIMER (0x400E10B0U) /**< \brief (PIOC) Additional Interrupt Modes Enable Register */
Pawel Zarembski 0:01f31e923fe2 67 #define REG_PIOC_AIMDR (0x400E10B4U) /**< \brief (PIOC) Additional Interrupt Modes Disables Register */
Pawel Zarembski 0:01f31e923fe2 68 #define REG_PIOC_AIMMR (0x400E10B8U) /**< \brief (PIOC) Additional Interrupt Modes Mask Register */
Pawel Zarembski 0:01f31e923fe2 69 #define REG_PIOC_ESR (0x400E10C0U) /**< \brief (PIOC) Edge Select Register */
Pawel Zarembski 0:01f31e923fe2 70 #define REG_PIOC_LSR (0x400E10C4U) /**< \brief (PIOC) Level Select Register */
Pawel Zarembski 0:01f31e923fe2 71 #define REG_PIOC_ELSR (0x400E10C8U) /**< \brief (PIOC) Edge/Level Status Register */
Pawel Zarembski 0:01f31e923fe2 72 #define REG_PIOC_FELLSR (0x400E10D0U) /**< \brief (PIOC) Falling Edge/Low Level Select Register */
Pawel Zarembski 0:01f31e923fe2 73 #define REG_PIOC_REHLSR (0x400E10D4U) /**< \brief (PIOC) Rising Edge/ High Level Select Register */
Pawel Zarembski 0:01f31e923fe2 74 #define REG_PIOC_FRLHSR (0x400E10D8U) /**< \brief (PIOC) Fall/Rise - Low/High Status Register */
Pawel Zarembski 0:01f31e923fe2 75 #define REG_PIOC_LOCKSR (0x400E10E0U) /**< \brief (PIOC) Lock Status */
Pawel Zarembski 0:01f31e923fe2 76 #define REG_PIOC_WPMR (0x400E10E4U) /**< \brief (PIOC) Write Protect Mode Register */
Pawel Zarembski 0:01f31e923fe2 77 #define REG_PIOC_WPSR (0x400E10E8U) /**< \brief (PIOC) Write Protect Status Register */
Pawel Zarembski 0:01f31e923fe2 78 #else
Pawel Zarembski 0:01f31e923fe2 79 #define REG_PIOC_PER (*(WoReg*)0x400E1000U) /**< \brief (PIOC) PIO Enable Register */
Pawel Zarembski 0:01f31e923fe2 80 #define REG_PIOC_PDR (*(WoReg*)0x400E1004U) /**< \brief (PIOC) PIO Disable Register */
Pawel Zarembski 0:01f31e923fe2 81 #define REG_PIOC_PSR (*(RoReg*)0x400E1008U) /**< \brief (PIOC) PIO Status Register */
Pawel Zarembski 0:01f31e923fe2 82 #define REG_PIOC_OER (*(WoReg*)0x400E1010U) /**< \brief (PIOC) Output Enable Register */
Pawel Zarembski 0:01f31e923fe2 83 #define REG_PIOC_ODR (*(WoReg*)0x400E1014U) /**< \brief (PIOC) Output Disable Register */
Pawel Zarembski 0:01f31e923fe2 84 #define REG_PIOC_OSR (*(RoReg*)0x400E1018U) /**< \brief (PIOC) Output Status Register */
Pawel Zarembski 0:01f31e923fe2 85 #define REG_PIOC_IFER (*(WoReg*)0x400E1020U) /**< \brief (PIOC) Glitch Input Filter Enable Register */
Pawel Zarembski 0:01f31e923fe2 86 #define REG_PIOC_IFDR (*(WoReg*)0x400E1024U) /**< \brief (PIOC) Glitch Input Filter Disable Register */
Pawel Zarembski 0:01f31e923fe2 87 #define REG_PIOC_IFSR (*(RoReg*)0x400E1028U) /**< \brief (PIOC) Glitch Input Filter Status Register */
Pawel Zarembski 0:01f31e923fe2 88 #define REG_PIOC_SODR (*(WoReg*)0x400E1030U) /**< \brief (PIOC) Set Output Data Register */
Pawel Zarembski 0:01f31e923fe2 89 #define REG_PIOC_CODR (*(WoReg*)0x400E1034U) /**< \brief (PIOC) Clear Output Data Register */
Pawel Zarembski 0:01f31e923fe2 90 #define REG_PIOC_ODSR (*(RwReg*)0x400E1038U) /**< \brief (PIOC) Output Data Status Register */
Pawel Zarembski 0:01f31e923fe2 91 #define REG_PIOC_PDSR (*(RoReg*)0x400E103CU) /**< \brief (PIOC) Pin Data Status Register */
Pawel Zarembski 0:01f31e923fe2 92 #define REG_PIOC_IER (*(WoReg*)0x400E1040U) /**< \brief (PIOC) Interrupt Enable Register */
Pawel Zarembski 0:01f31e923fe2 93 #define REG_PIOC_IDR (*(WoReg*)0x400E1044U) /**< \brief (PIOC) Interrupt Disable Register */
Pawel Zarembski 0:01f31e923fe2 94 #define REG_PIOC_IMR (*(RoReg*)0x400E1048U) /**< \brief (PIOC) Interrupt Mask Register */
Pawel Zarembski 0:01f31e923fe2 95 #define REG_PIOC_ISR (*(RoReg*)0x400E104CU) /**< \brief (PIOC) Interrupt Status Register */
Pawel Zarembski 0:01f31e923fe2 96 #define REG_PIOC_MDER (*(WoReg*)0x400E1050U) /**< \brief (PIOC) Multi-driver Enable Register */
Pawel Zarembski 0:01f31e923fe2 97 #define REG_PIOC_MDDR (*(WoReg*)0x400E1054U) /**< \brief (PIOC) Multi-driver Disable Register */
Pawel Zarembski 0:01f31e923fe2 98 #define REG_PIOC_MDSR (*(RoReg*)0x400E1058U) /**< \brief (PIOC) Multi-driver Status Register */
Pawel Zarembski 0:01f31e923fe2 99 #define REG_PIOC_PUDR (*(WoReg*)0x400E1060U) /**< \brief (PIOC) Pull-up Disable Register */
Pawel Zarembski 0:01f31e923fe2 100 #define REG_PIOC_PUER (*(WoReg*)0x400E1064U) /**< \brief (PIOC) Pull-up Enable Register */
Pawel Zarembski 0:01f31e923fe2 101 #define REG_PIOC_PUSR (*(RoReg*)0x400E1068U) /**< \brief (PIOC) Pad Pull-up Status Register */
Pawel Zarembski 0:01f31e923fe2 102 #define REG_PIOC_ABSR (*(RwReg*)0x400E1070U) /**< \brief (PIOC) Peripheral AB Select Register */
Pawel Zarembski 0:01f31e923fe2 103 #define REG_PIOC_SCIFSR (*(WoReg*)0x400E1080U) /**< \brief (PIOC) System Clock Glitch Input Filter Select Register */
Pawel Zarembski 0:01f31e923fe2 104 #define REG_PIOC_DIFSR (*(WoReg*)0x400E1084U) /**< \brief (PIOC) Debouncing Input Filter Select Register */
Pawel Zarembski 0:01f31e923fe2 105 #define REG_PIOC_IFDGSR (*(RoReg*)0x400E1088U) /**< \brief (PIOC) Glitch or Debouncing Input Filter Clock Selection Status Register */
Pawel Zarembski 0:01f31e923fe2 106 #define REG_PIOC_SCDR (*(RwReg*)0x400E108CU) /**< \brief (PIOC) Slow Clock Divider Debouncing Register */
Pawel Zarembski 0:01f31e923fe2 107 #define REG_PIOC_OWER (*(WoReg*)0x400E10A0U) /**< \brief (PIOC) Output Write Enable */
Pawel Zarembski 0:01f31e923fe2 108 #define REG_PIOC_OWDR (*(WoReg*)0x400E10A4U) /**< \brief (PIOC) Output Write Disable */
Pawel Zarembski 0:01f31e923fe2 109 #define REG_PIOC_OWSR (*(RoReg*)0x400E10A8U) /**< \brief (PIOC) Output Write Status Register */
Pawel Zarembski 0:01f31e923fe2 110 #define REG_PIOC_AIMER (*(WoReg*)0x400E10B0U) /**< \brief (PIOC) Additional Interrupt Modes Enable Register */
Pawel Zarembski 0:01f31e923fe2 111 #define REG_PIOC_AIMDR (*(WoReg*)0x400E10B4U) /**< \brief (PIOC) Additional Interrupt Modes Disables Register */
Pawel Zarembski 0:01f31e923fe2 112 #define REG_PIOC_AIMMR (*(RoReg*)0x400E10B8U) /**< \brief (PIOC) Additional Interrupt Modes Mask Register */
Pawel Zarembski 0:01f31e923fe2 113 #define REG_PIOC_ESR (*(WoReg*)0x400E10C0U) /**< \brief (PIOC) Edge Select Register */
Pawel Zarembski 0:01f31e923fe2 114 #define REG_PIOC_LSR (*(WoReg*)0x400E10C4U) /**< \brief (PIOC) Level Select Register */
Pawel Zarembski 0:01f31e923fe2 115 #define REG_PIOC_ELSR (*(RoReg*)0x400E10C8U) /**< \brief (PIOC) Edge/Level Status Register */
Pawel Zarembski 0:01f31e923fe2 116 #define REG_PIOC_FELLSR (*(WoReg*)0x400E10D0U) /**< \brief (PIOC) Falling Edge/Low Level Select Register */
Pawel Zarembski 0:01f31e923fe2 117 #define REG_PIOC_REHLSR (*(WoReg*)0x400E10D4U) /**< \brief (PIOC) Rising Edge/ High Level Select Register */
Pawel Zarembski 0:01f31e923fe2 118 #define REG_PIOC_FRLHSR (*(RoReg*)0x400E10D8U) /**< \brief (PIOC) Fall/Rise - Low/High Status Register */
Pawel Zarembski 0:01f31e923fe2 119 #define REG_PIOC_LOCKSR (*(RoReg*)0x400E10E0U) /**< \brief (PIOC) Lock Status */
Pawel Zarembski 0:01f31e923fe2 120 #define REG_PIOC_WPMR (*(RwReg*)0x400E10E4U) /**< \brief (PIOC) Write Protect Mode Register */
Pawel Zarembski 0:01f31e923fe2 121 #define REG_PIOC_WPSR (*(RoReg*)0x400E10E8U) /**< \brief (PIOC) Write Protect Status Register */
Pawel Zarembski 0:01f31e923fe2 122 #endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
Pawel Zarembski 0:01f31e923fe2 123
Pawel Zarembski 0:01f31e923fe2 124 #endif /* _SAM3U_PIOC_INSTANCE_ */