SPI CPHA/CPOL confusion

27 Aug 2010 . Edited: 27 Aug 2010

Hello, I have an oled that I talk to over SPI, it works really well, however, there's something that I can't seem to understand and I hope someone here could shed some light on the subject.


According to the driver data sheet "SDIN is shifted into an 8-bit shift register on every rising edge of SCLK"  as far as I know when CPHA=0 MOSI data is shifted out on falling edge, so CPHA should be 1 right ? however when I try spi.format(8, 1) it doesn't work, and spi.format(8, 0) does !! any ideas ?


Also, I read that "CPOL determines whether the shift clock's idle state is low or high", what does that mean in English :D ?


27 Aug 2010

What follows is just guesswork; I'd need to see a copy of the datasheet to be sure.

I think that the statement about CPOL menas that its value specifies whether the clock is active-high or active-low. The idle (inactive) state is the level of the clock signal when nothing is being sent on the SPI bus.

The CPOL setting might account for the behaviour you are seeing. Changing it may switch clock 'rising' and 'falling' as far as the device is concerned.

28 Aug 2010

I've been reading this wiki and after some head-scratching I think I figured it out, the oled data is shifted on raising edge of the clock so this can either work if you set CPHA to first clock edge and CPOL to raising when it's active (that is CPOL=0 when idle) or if you set CPHA to second edge and CPOL to falling (that is CPOL=1 when idle) because either way when the bit is sampled the clock will be raising from low to high, so I tried it with CPOL=0 CPHA=0 and with CPOL=1 and CPHA=1 and it works both ways :)


Thanks for your help.