I have been measuring the SysTick frequency on my mbed 1768 and discovered that I am getting 0.3% more interrupts than expected (equating to a gain of about 270 seconds, or 4.5 minutes, per day, which is too much for use as a long-term clock).

I'd have expected a crystal-controlled clock to be stable within around 30 ppm, but that's about 3000 ppm faster than expected.

Hence I am wondering what the part number of the 12MHz clock is (it's not on the schematic!) so I can check its specs. Or, has anyone else has seen anything similar?

Thanks; Mike

A severe case of Schematic Blindness! The Oscillator is there, centre bottom on page 1; it is an ASE-12-D-C-T, which is a 12MHz crystal oscillator with an expected stability of +/- 50 ppm. I have confirmed (with a calibrated frequency meter) that that oscillator is delivering a stable 11.99987 MHz (within 13 ppm of ideal).

Since my first post I've carried out several more measurements (including using the calibrated frequency counter) and have found that the SysTick rate varies quite wildly, from 0.3% fast to 1.16% slow (measured over nearly 12 hours). 1.16% slow is an error of 11,600 ppm.

Anyone have any ideas of why this might be? I'm mystified at the moment...

Mike

Mystery solved. The SysTick_Config inline routine (in core_cm3.h) has the undocumented side-effect for setting the SysTick interrupt priority to lowest (by default it is at highest priority). Since my interrupt handlers for accelerometer and gyro were at a medium priority and could run for more than 100us this caused occasional lost SysTick events (overrun).

Mike

thanks for the update!