<June 9th, 2015>
I recognized that Nucleo board have three hardware version, MB1136 C-01, C-02 and C-03.
Followings are LSE difference those 3 versions.

Please check DocID025833 Rev.7 (UM1724 User Manual) 5.7.3 OSC 32kHz clock supply.
If you have C-03 version board, I hope you don't have a LSE oscillation problem.

<May 17th, 2015>
Time-out setting value are changed officially as of today mbed-src (Rev.541) and mbed(Rev.99).

Unfortunately this countermeasure is not enough for permanent solution!
During power-on sequence, sometimes the program cannot select LSE and shows "NO CLOCK" condition even LSE 32.768KHz Xtal is equipped correctly.

For LSE(External Xtal) issue, please also refer following link. (added on Feb. 20th, 2015)
/users/kenjiArai/notebook/nucleo-series-rtc-control-under-power-onoff-and-re/

1) Summary

Here I would like to explain two issues for ST Nucleo Board, (a) LSE Problem, (b)HSE without additional Xtal(X3).

====================
(a)LSE Problem
<Problem>
"Problem" is as of October 25th, 2014.
Below is the page which you can see the problem and answer.
http://developer.mbed.org/questions/4531/RTC-External-Crystal-Nucleo/
This problem is not only for ST Nucleo L152 Problem but also so at least F401 & F411 and I expected all of kinds of ST Nucleo boards.
Everybody want to use actual 32.768kHz clock of RTC but you can use if you have a lucky condition!
<Route Cause>
Hardware design(load capacitors) and software design(time-out) problem which Mr.Drescher pointed out in the above Q&A session.
if you have an interest for the detail route cause explanation, please see following session.
<Solution>
Two solutions are available.
1) Change X2 load capacitors -> Change hardware -> C31 and C32 value -> I don't know best value
2) Change software-> Please refer this page https://developer.mbed.org/users/kenjiArai/code/Nucleo_RTC_Clock_setting/

====================
(b)HSE without additional Xtal(X3)
New board doesn't have a X3 Xtal but it can run with best speed without X3!!
Why? Use X1 Xtal for main CPU Clock. Please refer follows.

2) HSE without additional Xtal(X3)

New board has a connection SB16 and SB50.
X1 is for ST/Link control CPU but they can deliver the clock to main CPU via MCO line because X1 = 8MHz Xtal and CPU needs 8MHz clock. Latest version of software can detect this connection and auto configure it.
Old board is only internal HSI clock but you can modify the board to connect SB16 & SB50 also.

3) LSE control problem

I have following Necleo boards.

New board has external Xtal, 32.768kHz as X2 RTC, LSE clock source (Old version doesn't have it (You can check C-01(old) or C-02(new one as of today(Oct. 25th,2014) on your board bottom side)).
You can check your board new or old as follows(example Nucleo F401RE board).


As I mentioned above, the route cause is un-proper capacitors for X2.
Xtal and capacitor combination is very fundamental and very important hardware design issue.
You can see AN2867 application note provided by STM.
https://docs.google.com/viewer?url=http%3A%2F%2Fwww.st.com%2Fweb%2Fen%2Fresource%2Ftechnical%2Fdocument%2Fapplication_note%2FCD00221665.pdf%23search%3D%27AN2867%27
ST Nucleo board has 10pF capacitor as C31 and C32.
Capacitors value is not good for the board!! and software time-out setting is also bad!!(May 17th, 2015)
Board engineers didn't consider proper value for the capacitors and no collaboration with software engineers.
A software function which can select LSI(internal clock) and LSE(X2 Xtal) is also cannot work properly.
In the Q&A session which mentioned above, you can see function call "rtc_init()" but this routine cannot help for your problem.
In the AN2867 page 14, you can see following sentence.
4.5. Start-up time
Current mbed-src and mbed library has changed to 5s but still has a problem.(May 17th, 2015)
Start-up time of 32kHz crystal is within the 1s to 5s range.

followings are related program list.

file:rtc_api.c

void rtc_init(void){
    // ------deleted here--------
    // Enable LSE Oscillator
    RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_LSE;
    RCC_OscInitStruct.PLL.PLLState   = RCC_PLL_NONE; /* Mandatory, otherwise the PLL is reconfigured! */
    RCC_OscInitStruct.LSEState       = RCC_LSE_ON; /* External 32.768 kHz clock on OSC_IN/OSC_OUT */
    if (HAL_RCC_OscConfig(&RCC_OscInitStruct) == HAL_OK) {
        // Connect LSE to RTC
        __HAL_RCC_RTC_CLKPRESCALER(RCC_RTCCLKSOURCE_LSE);
        __HAL_RCC_RTC_CONFIG(RCC_RTCCLKSOURCE_LSE);
        rtc_freq = LSE_VALUE;
    } else {
        // Enable LSI clock
        // ------deleted here--------
        rtc_freq = LSI_VALUE;
    }
    // ------deleted here--------
}

file: stm32f4xx_hal_rcc.c

HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef  *RCC_OscInitStruct){
  // ------deleted here--------
  /*------------------------------ LSE Configuration -------------------------*/
  if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE) {
    // ------deleted here--------
    __PWR_CLK_ENABLE();
    PWR->CR |= PWR_CR_DBP;
    /* Wait for Backup domain Write protection disable */
    tickstart = HAL_GetTick();
    while((PWR->CR & PWR_CR_DBP) == RESET)  {
      // ------deleted here--------
    }
    /* Reset LSEON and LSEBYP bits before configuring the LSE ----------------*/
    __HAL_RCC_LSE_CONFIG(RCC_LSE_OFF);
    tickstart = HAL_GetTick();
    while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != RESET) {
      if((HAL_GetTick() - tickstart ) > LSE_TIMEOUT_VALUE) {
        return HAL_TIMEOUT;
      }
    }
    /* Set the new LSE configuration -----------------------------------------*/
    __HAL_RCC_LSE_CONFIG(RCC_OscInitStruct->LSEState);
    /* Check the LSE State */
    if((RCC_OscInitStruct->LSEState) == RCC_LSE_ON)  {
      tickstart = HAL_GetTick();
      /* Wait till LSE is ready */
      while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET)      {
        if((HAL_GetTick() - tickstart ) > LSE_TIMEOUT_VALUE)        {
          return HAL_TIMEOUT;
        }
      }
    } else {
      tickstart = HAL_GetTick();
      while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != RESET)      {
        if((HAL_GetTick() - tickstart ) > LSE_TIMEOUT_VALUE)        {
          return HAL_TIMEOUT;
        }
      }
    }
  }
  // ------deleted here--------
  return HAL_OK;
}

files: stm32f3xx_hal_rcc.h, stm32f4xx_hal_rcc.h, stm32l0xx_hal_rcc.h, stm32l1xx_hal_rcc.h

updated to 5000
followings are old information
 (May 17th, 2015)

//  /TARGET_NUCLEO_F302R8/stm32f3xx_hal_rcc.h
/* LSE state change timeout */
#define LSE_TIMEOUT_VALUE        ((uint32_t)5000) /* 5 s    */
//  /TARGET_NUCLEO_F401RE/stm32f4xx_hal_rcc.h
/* LSE state change timeout */
#define LSE_TIMEOUT_VALUE        ((uint32_t)500)
//  /TARGET_NUCLEO_F411RE/stm32f4xx_hal_rcc.h
/* LSE state change timeout */
#define LSE_TIMEOUT_VALUE        ((uint32_t)600)
//  /TARGET_NUCLEO_L152RE/stm32l1xx_hal_rcc.h
#if !defined  (LSE_STARTUP_TIMEOUT)
  #define LSE_STARTUP_TIMEOUT   ((uint32_t)500)   /*!< Time out for LSE start up, in ms */
#endif /* HSE_STARTUP_TIMEOUT */
/* LSE state change timeout */
#define LSE_TIMEOUT_VALUE         LSE_STARTUP_TIMEOUT

Time-out for each CPU are here.
Here is old (please refer top of this page) (May 17th, 2015)

Please check your board using this program.

NOW you can use this program not only for F401 and F411 but also L152.
Here is my board results -> time-out sets original (0.5 or 0.6Sec).

Most of the case, it reaches a time-out condition.
Some times, it can set LSE but not always.
Here is 2nd check.
Results -> Time-out sets 5sec

Startup time for X3, LSE oscillator is diverse form 0.4 sec to over 1.2sec!!

4) Request to STMicroelectronics and the mbed team

Easy Solution Please modify definition as follows.

Thanks!  Followings are done. (May 17th, 2015)

//  /TARGET_NUCLEO_F401RE/stm32f4xx_hal_rcc.h
/* LSE state change timeout */
#define LSE_TIMEOUT_VALUE         ((uint32_t)5000) /* 5 s    */
//  /TARGET_NUCLEO_F411RE/stm32f4xx_hal_rcc.h
/* LSE state change timeout */
#define LSE_TIMEOUT_VALUE        ((uint32_t)5000) /* 5 s    */
//  /TARGET_NUCLEO_L152RE/stm32l1xx_hal_rcc.h
#if !defined  (LSE_STARTUP_TIMEOUT)
  #define LSE_STARTUP_TIMEOUT   ((uint32_t)5000) /* 5 s    */ 
#endif /* HSE_STARTUP_TIMEOUT */
/* LSE state change timeout */
#define LSE_TIMEOUT_VALUE         LSE_STARTUP_TIMEOUT

Better Solution
Change "Time-out period " as function argument.
Best Solution
AN2867 application note is not only for user but also STMicroelectronics engineers.
Route case is very clear that combination of hardware load capacitor value and time-out setting.
I believe they will change the best value both capacitors and time-out ASAP.
Added on May 17th, 2015
In the power-on sequence, I think LSE setting program is called when CPU VDD is still unstable period.
My recommendation is that LSE setting program is calling just before go to main().