zain aftab / mbed-src3

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Dependents:   RPC_Serial_V_mac

Diff: targets/hal/TARGET_Freescale/TARGET_K20D5M/serial_api.c

Revision:
73:299c67215126
Parent:
68:41613245dfd7
Child:
158:3121b9889f7b
--- a/targets/hal/TARGET_Freescale/TARGET_K20D5M/serial_api.c	Mon Jan 13 10:45:05 2014 +0000
+++ b/targets/hal/TARGET_Freescale/TARGET_K20D5M/serial_api.c	Tue Jan 14 20:45:05 2014 +0000
@@ -53,7 +53,7 @@
     obj->uart = (UART_Type *)uart;
     // enable clk
     switch (uart) {
-        case UART_0: SIM->SOPT2 |= SIM_SOPT2_PLLFLLSEL_MASK | (1<<SIM_SOPT5_UART0TXSRC_SHIFT);
+        case UART_0: SIM->SOPT2 |= SIM_SOPT2_PLLFLLSEL_MASK;
                      SIM->SCGC5 |= SIM_SCGC5_PORTA_MASK; SIM->SCGC4 |= SIM_SCGC4_UART0_MASK; break;
         case UART_1: SIM->SCGC5 |= SIM_SCGC5_PORTC_MASK; SIM->SCGC4 |= SIM_SCGC4_UART1_MASK; break;
         case UART_2: SIM->SCGC5 |= SIM_SCGC5_PORTD_MASK; SIM->SCGC4 |= SIM_SCGC4_UART2_MASK; break;
@@ -98,8 +98,7 @@
     // Disable UART before changing registers
     obj->uart->C2 &= ~(UART_C2_RE_MASK | UART_C2_TE_MASK);
 
-    // [TODO] not hardcode this value
-    uint32_t PCLK = (obj->uart == UART0) ? 48000000u : 24000000u;
+    uint32_t PCLK = (obj->uart == UART0) ? SystemCoreClock : SystemCoreClock/2;
 
     // First we check to see if the basic divide with no DivAddVal/MulVal
     // ratio gives us an integer result. If it does, we set DivAddVal = 0,