雄介 太田
mbed(SerialHalfDuplex入り)
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mbed official
TARGET_NUCLEO_F103RB/stm32f1xx_hal_pwr.h@96:487b796308b0, 2015-03-17 (annotated)
- Committer:
- Kojto
- Date:
- Tue Mar 17 14:27:45 2015 +0000
- Revision:
- 96:487b796308b0
Release 96 of the mbed library
Changes:
- IAR support for ble boards, lpc, ethernet stack
- RTC - attach function to redirect time functions
- Nucleo F103RB - cube driver
- k20xx - fixes for teensy and k20 platforms in sleep/deepsleep and usb
- STM32L0, Nucleo/Disco L053 - refactoring
Who changed what in which revision?
| User | Revision | Line number | New contents of line |
|---|---|---|---|
| Kojto | 96:487b796308b0 | 1 | /** |
| Kojto | 96:487b796308b0 | 2 | ****************************************************************************** |
| Kojto | 96:487b796308b0 | 3 | * @file stm32f1xx_hal_pwr.h |
| Kojto | 96:487b796308b0 | 4 | * @author MCD Application Team |
| Kojto | 96:487b796308b0 | 5 | * @version V1.0.0 |
| Kojto | 96:487b796308b0 | 6 | * @date 15-December-2014 |
| Kojto | 96:487b796308b0 | 7 | * @brief Header file of PWR HAL module. |
| Kojto | 96:487b796308b0 | 8 | ****************************************************************************** |
| Kojto | 96:487b796308b0 | 9 | * @attention |
| Kojto | 96:487b796308b0 | 10 | * |
| Kojto | 96:487b796308b0 | 11 | * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2> |
| Kojto | 96:487b796308b0 | 12 | * |
| Kojto | 96:487b796308b0 | 13 | * Redistribution and use in source and binary forms, with or without modification, |
| Kojto | 96:487b796308b0 | 14 | * are permitted provided that the following conditions are met: |
| Kojto | 96:487b796308b0 | 15 | * 1. Redistributions of source code must retain the above copyright notice, |
| Kojto | 96:487b796308b0 | 16 | * this list of conditions and the following disclaimer. |
| Kojto | 96:487b796308b0 | 17 | * 2. Redistributions in binary form must reproduce the above copyright notice, |
| Kojto | 96:487b796308b0 | 18 | * this list of conditions and the following disclaimer in the documentation |
| Kojto | 96:487b796308b0 | 19 | * and/or other materials provided with the distribution. |
| Kojto | 96:487b796308b0 | 20 | * 3. Neither the name of STMicroelectronics nor the names of its contributors |
| Kojto | 96:487b796308b0 | 21 | * may be used to endorse or promote products derived from this software |
| Kojto | 96:487b796308b0 | 22 | * without specific prior written permission. |
| Kojto | 96:487b796308b0 | 23 | * |
| Kojto | 96:487b796308b0 | 24 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
| Kojto | 96:487b796308b0 | 25 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
| Kojto | 96:487b796308b0 | 26 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
| Kojto | 96:487b796308b0 | 27 | * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE |
| Kojto | 96:487b796308b0 | 28 | * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
| Kojto | 96:487b796308b0 | 29 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR |
| Kojto | 96:487b796308b0 | 30 | * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER |
| Kojto | 96:487b796308b0 | 31 | * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, |
| Kojto | 96:487b796308b0 | 32 | * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE |
| Kojto | 96:487b796308b0 | 33 | * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
| Kojto | 96:487b796308b0 | 34 | * |
| Kojto | 96:487b796308b0 | 35 | ****************************************************************************** |
| Kojto | 96:487b796308b0 | 36 | */ |
| Kojto | 96:487b796308b0 | 37 | |
| Kojto | 96:487b796308b0 | 38 | /* Define to prevent recursive inclusion -------------------------------------*/ |
| Kojto | 96:487b796308b0 | 39 | #ifndef __STM32F1xx_HAL_PWR_H |
| Kojto | 96:487b796308b0 | 40 | #define __STM32F1xx_HAL_PWR_H |
| Kojto | 96:487b796308b0 | 41 | |
| Kojto | 96:487b796308b0 | 42 | #ifdef __cplusplus |
| Kojto | 96:487b796308b0 | 43 | extern "C" { |
| Kojto | 96:487b796308b0 | 44 | #endif |
| Kojto | 96:487b796308b0 | 45 | |
| Kojto | 96:487b796308b0 | 46 | /* Includes ------------------------------------------------------------------*/ |
| Kojto | 96:487b796308b0 | 47 | #include "stm32f1xx_hal_def.h" |
| Kojto | 96:487b796308b0 | 48 | |
| Kojto | 96:487b796308b0 | 49 | /** @addtogroup STM32F1xx_HAL_Driver |
| Kojto | 96:487b796308b0 | 50 | * @{ |
| Kojto | 96:487b796308b0 | 51 | */ |
| Kojto | 96:487b796308b0 | 52 | |
| Kojto | 96:487b796308b0 | 53 | /** @addtogroup PWR |
| Kojto | 96:487b796308b0 | 54 | * @{ |
| Kojto | 96:487b796308b0 | 55 | */ |
| Kojto | 96:487b796308b0 | 56 | |
| Kojto | 96:487b796308b0 | 57 | /* Exported types ------------------------------------------------------------*/ |
| Kojto | 96:487b796308b0 | 58 | |
| Kojto | 96:487b796308b0 | 59 | /** @defgroup PWR_Exported_Types PWR Exported Types |
| Kojto | 96:487b796308b0 | 60 | * @{ |
| Kojto | 96:487b796308b0 | 61 | */ |
| Kojto | 96:487b796308b0 | 62 | |
| Kojto | 96:487b796308b0 | 63 | /** |
| Kojto | 96:487b796308b0 | 64 | * @brief PWR PVD configuration structure definition |
| Kojto | 96:487b796308b0 | 65 | */ |
| Kojto | 96:487b796308b0 | 66 | typedef struct |
| Kojto | 96:487b796308b0 | 67 | { |
| Kojto | 96:487b796308b0 | 68 | uint32_t PVDLevel; /*!< PVDLevel: Specifies the PVD detection level. |
| Kojto | 96:487b796308b0 | 69 | This parameter can be a value of @ref PWR_PVD_detection_level */ |
| Kojto | 96:487b796308b0 | 70 | |
| Kojto | 96:487b796308b0 | 71 | uint32_t Mode; /*!< Mode: Specifies the operating mode for the selected pins. |
| Kojto | 96:487b796308b0 | 72 | This parameter can be a value of @ref PWR_PVD_Mode */ |
| Kojto | 96:487b796308b0 | 73 | }PWR_PVDTypeDef; |
| Kojto | 96:487b796308b0 | 74 | |
| Kojto | 96:487b796308b0 | 75 | |
| Kojto | 96:487b796308b0 | 76 | /** |
| Kojto | 96:487b796308b0 | 77 | * @} |
| Kojto | 96:487b796308b0 | 78 | */ |
| Kojto | 96:487b796308b0 | 79 | |
| Kojto | 96:487b796308b0 | 80 | |
| Kojto | 96:487b796308b0 | 81 | /* Internal constants --------------------------------------------------------*/ |
| Kojto | 96:487b796308b0 | 82 | |
| Kojto | 96:487b796308b0 | 83 | /** @addtogroup PWR_Private_Constants |
| Kojto | 96:487b796308b0 | 84 | * @{ |
| Kojto | 96:487b796308b0 | 85 | */ |
| Kojto | 96:487b796308b0 | 86 | |
| Kojto | 96:487b796308b0 | 87 | #define PWR_EXTI_LINE_PVD ((uint32_t)0x00010000) /*!< External interrupt line 16 Connected to the PVD EXTI Line */ |
| Kojto | 96:487b796308b0 | 88 | |
| Kojto | 96:487b796308b0 | 89 | /** |
| Kojto | 96:487b796308b0 | 90 | * @} |
| Kojto | 96:487b796308b0 | 91 | */ |
| Kojto | 96:487b796308b0 | 92 | |
| Kojto | 96:487b796308b0 | 93 | |
| Kojto | 96:487b796308b0 | 94 | /* Exported constants --------------------------------------------------------*/ |
| Kojto | 96:487b796308b0 | 95 | |
| Kojto | 96:487b796308b0 | 96 | /** @defgroup PWR_Exported_Constants PWR Exported Constants |
| Kojto | 96:487b796308b0 | 97 | * @{ |
| Kojto | 96:487b796308b0 | 98 | */ |
| Kojto | 96:487b796308b0 | 99 | |
| Kojto | 96:487b796308b0 | 100 | /** @defgroup PWR_PVD_detection_level PWR PVD detection level |
| Kojto | 96:487b796308b0 | 101 | * @{ |
| Kojto | 96:487b796308b0 | 102 | */ |
| Kojto | 96:487b796308b0 | 103 | #define PWR_PVDLEVEL_0 PWR_CR_PLS_2V2 |
| Kojto | 96:487b796308b0 | 104 | #define PWR_PVDLEVEL_1 PWR_CR_PLS_2V3 |
| Kojto | 96:487b796308b0 | 105 | #define PWR_PVDLEVEL_2 PWR_CR_PLS_2V4 |
| Kojto | 96:487b796308b0 | 106 | #define PWR_PVDLEVEL_3 PWR_CR_PLS_2V5 |
| Kojto | 96:487b796308b0 | 107 | #define PWR_PVDLEVEL_4 PWR_CR_PLS_2V6 |
| Kojto | 96:487b796308b0 | 108 | #define PWR_PVDLEVEL_5 PWR_CR_PLS_2V7 |
| Kojto | 96:487b796308b0 | 109 | #define PWR_PVDLEVEL_6 PWR_CR_PLS_2V8 |
| Kojto | 96:487b796308b0 | 110 | #define PWR_PVDLEVEL_7 PWR_CR_PLS_2V9 |
| Kojto | 96:487b796308b0 | 111 | |
| Kojto | 96:487b796308b0 | 112 | /** |
| Kojto | 96:487b796308b0 | 113 | * @} |
| Kojto | 96:487b796308b0 | 114 | */ |
| Kojto | 96:487b796308b0 | 115 | |
| Kojto | 96:487b796308b0 | 116 | /** @defgroup PWR_PVD_Mode PWR PVD Mode |
| Kojto | 96:487b796308b0 | 117 | * @{ |
| Kojto | 96:487b796308b0 | 118 | */ |
| Kojto | 96:487b796308b0 | 119 | #define PWR_PVD_MODE_NORMAL ((uint32_t)0x00000000) /*!< basic mode is used */ |
| Kojto | 96:487b796308b0 | 120 | #define PWR_PVD_MODE_IT_RISING ((uint32_t)0x00010001) /*!< External Interrupt Mode with Rising edge trigger detection */ |
| Kojto | 96:487b796308b0 | 121 | #define PWR_PVD_MODE_IT_FALLING ((uint32_t)0x00010002) /*!< External Interrupt Mode with Falling edge trigger detection */ |
| Kojto | 96:487b796308b0 | 122 | #define PWR_PVD_MODE_IT_RISING_FALLING ((uint32_t)0x00010003) /*!< External Interrupt Mode with Rising/Falling edge trigger detection */ |
| Kojto | 96:487b796308b0 | 123 | #define PWR_PVD_MODE_EVENT_RISING ((uint32_t)0x00020001) /*!< Event Mode with Rising edge trigger detection */ |
| Kojto | 96:487b796308b0 | 124 | #define PWR_PVD_MODE_EVENT_FALLING ((uint32_t)0x00020002) /*!< Event Mode with Falling edge trigger detection */ |
| Kojto | 96:487b796308b0 | 125 | #define PWR_PVD_MODE_EVENT_RISING_FALLING ((uint32_t)0x00020003) /*!< Event Mode with Rising/Falling edge trigger detection */ |
| Kojto | 96:487b796308b0 | 126 | |
| Kojto | 96:487b796308b0 | 127 | /** |
| Kojto | 96:487b796308b0 | 128 | * @} |
| Kojto | 96:487b796308b0 | 129 | */ |
| Kojto | 96:487b796308b0 | 130 | |
| Kojto | 96:487b796308b0 | 131 | |
| Kojto | 96:487b796308b0 | 132 | /** @defgroup PWR_WakeUp_Pins PWR WakeUp Pins |
| Kojto | 96:487b796308b0 | 133 | * @{ |
| Kojto | 96:487b796308b0 | 134 | */ |
| Kojto | 96:487b796308b0 | 135 | |
| Kojto | 96:487b796308b0 | 136 | #define PWR_WAKEUP_PIN1 PWR_CSR_EWUP |
| Kojto | 96:487b796308b0 | 137 | |
| Kojto | 96:487b796308b0 | 138 | /** |
| Kojto | 96:487b796308b0 | 139 | * @} |
| Kojto | 96:487b796308b0 | 140 | */ |
| Kojto | 96:487b796308b0 | 141 | |
| Kojto | 96:487b796308b0 | 142 | /** @defgroup PWR_Regulator_state_in_SLEEP_STOP_mode PWR Regulator state in SLEEP/STOP mode |
| Kojto | 96:487b796308b0 | 143 | * @{ |
| Kojto | 96:487b796308b0 | 144 | */ |
| Kojto | 96:487b796308b0 | 145 | #define PWR_MAINREGULATOR_ON ((uint32_t)0x00000000) |
| Kojto | 96:487b796308b0 | 146 | #define PWR_LOWPOWERREGULATOR_ON PWR_CR_LPDS |
| Kojto | 96:487b796308b0 | 147 | |
| Kojto | 96:487b796308b0 | 148 | /** |
| Kojto | 96:487b796308b0 | 149 | * @} |
| Kojto | 96:487b796308b0 | 150 | */ |
| Kojto | 96:487b796308b0 | 151 | |
| Kojto | 96:487b796308b0 | 152 | /** @defgroup PWR_SLEEP_mode_entry PWR SLEEP mode entry |
| Kojto | 96:487b796308b0 | 153 | * @{ |
| Kojto | 96:487b796308b0 | 154 | */ |
| Kojto | 96:487b796308b0 | 155 | #define PWR_SLEEPENTRY_WFI ((uint8_t)0x01) |
| Kojto | 96:487b796308b0 | 156 | #define PWR_SLEEPENTRY_WFE ((uint8_t)0x02) |
| Kojto | 96:487b796308b0 | 157 | |
| Kojto | 96:487b796308b0 | 158 | /** |
| Kojto | 96:487b796308b0 | 159 | * @} |
| Kojto | 96:487b796308b0 | 160 | */ |
| Kojto | 96:487b796308b0 | 161 | |
| Kojto | 96:487b796308b0 | 162 | /** @defgroup PWR_STOP_mode_entry PWR STOP mode entry |
| Kojto | 96:487b796308b0 | 163 | * @{ |
| Kojto | 96:487b796308b0 | 164 | */ |
| Kojto | 96:487b796308b0 | 165 | #define PWR_STOPENTRY_WFI ((uint8_t)0x01) |
| Kojto | 96:487b796308b0 | 166 | #define PWR_STOPENTRY_WFE ((uint8_t)0x02) |
| Kojto | 96:487b796308b0 | 167 | |
| Kojto | 96:487b796308b0 | 168 | /** |
| Kojto | 96:487b796308b0 | 169 | * @} |
| Kojto | 96:487b796308b0 | 170 | */ |
| Kojto | 96:487b796308b0 | 171 | |
| Kojto | 96:487b796308b0 | 172 | /** @defgroup PWR_Flag PWR Flag |
| Kojto | 96:487b796308b0 | 173 | * @{ |
| Kojto | 96:487b796308b0 | 174 | */ |
| Kojto | 96:487b796308b0 | 175 | #define PWR_FLAG_WU PWR_CSR_WUF |
| Kojto | 96:487b796308b0 | 176 | #define PWR_FLAG_SB PWR_CSR_SBF |
| Kojto | 96:487b796308b0 | 177 | #define PWR_FLAG_PVDO PWR_CSR_PVDO |
| Kojto | 96:487b796308b0 | 178 | |
| Kojto | 96:487b796308b0 | 179 | |
| Kojto | 96:487b796308b0 | 180 | /** |
| Kojto | 96:487b796308b0 | 181 | * @} |
| Kojto | 96:487b796308b0 | 182 | */ |
| Kojto | 96:487b796308b0 | 183 | |
| Kojto | 96:487b796308b0 | 184 | /** |
| Kojto | 96:487b796308b0 | 185 | * @} |
| Kojto | 96:487b796308b0 | 186 | */ |
| Kojto | 96:487b796308b0 | 187 | |
| Kojto | 96:487b796308b0 | 188 | /* Exported macro ------------------------------------------------------------*/ |
| Kojto | 96:487b796308b0 | 189 | /** @defgroup PWR_Exported_Macros PWR Exported Macros |
| Kojto | 96:487b796308b0 | 190 | * @{ |
| Kojto | 96:487b796308b0 | 191 | */ |
| Kojto | 96:487b796308b0 | 192 | |
| Kojto | 96:487b796308b0 | 193 | /** @brief Check PWR flag is set or not. |
| Kojto | 96:487b796308b0 | 194 | * @param __FLAG__: specifies the flag to check. |
| Kojto | 96:487b796308b0 | 195 | * This parameter can be one of the following values: |
| Kojto | 96:487b796308b0 | 196 | * @arg PWR_FLAG_WU: Wake Up flag. This flag indicates that a wakeup event |
| Kojto | 96:487b796308b0 | 197 | * was received from the WKUP pin or from the RTC alarm |
| Kojto | 96:487b796308b0 | 198 | * An additional wakeup event is detected if the WKUP pin is enabled |
| Kojto | 96:487b796308b0 | 199 | * (by setting the EWUP bit) when the WKUP pin level is already high. |
| Kojto | 96:487b796308b0 | 200 | * @arg PWR_FLAG_SB: StandBy flag. This flag indicates that the system was |
| Kojto | 96:487b796308b0 | 201 | * resumed from StandBy mode. |
| Kojto | 96:487b796308b0 | 202 | * @arg PWR_FLAG_PVDO: PVD Output. This flag is valid only if PVD is enabled |
| Kojto | 96:487b796308b0 | 203 | * by the HAL_PWR_EnablePVD() function. The PVD is stopped by Standby mode |
| Kojto | 96:487b796308b0 | 204 | * For this reason, this bit is equal to 0 after Standby or reset |
| Kojto | 96:487b796308b0 | 205 | * until the PVDE bit is set. |
| Kojto | 96:487b796308b0 | 206 | * @retval The new state of __FLAG__ (TRUE or FALSE). |
| Kojto | 96:487b796308b0 | 207 | */ |
| Kojto | 96:487b796308b0 | 208 | #define __HAL_PWR_GET_FLAG(__FLAG__) ((PWR->CSR & (__FLAG__)) == (__FLAG__)) |
| Kojto | 96:487b796308b0 | 209 | |
| Kojto | 96:487b796308b0 | 210 | /** @brief Clear the PWR's pending flags. |
| Kojto | 96:487b796308b0 | 211 | * @param __FLAG__: specifies the flag to clear. |
| Kojto | 96:487b796308b0 | 212 | * This parameter can be one of the following values: |
| Kojto | 96:487b796308b0 | 213 | * @arg PWR_FLAG_WU: Wake Up flag |
| Kojto | 96:487b796308b0 | 214 | * @arg PWR_FLAG_SB: StandBy flag |
| Kojto | 96:487b796308b0 | 215 | */ |
| Kojto | 96:487b796308b0 | 216 | #define __HAL_PWR_CLEAR_FLAG(__FLAG__) SET_BIT(PWR->CR, ((__FLAG__) << 2)) |
| Kojto | 96:487b796308b0 | 217 | |
| Kojto | 96:487b796308b0 | 218 | /** |
| Kojto | 96:487b796308b0 | 219 | * @brief Enable interrupt on PVD Exti Line 16. |
| Kojto | 96:487b796308b0 | 220 | * @retval None. |
| Kojto | 96:487b796308b0 | 221 | */ |
| Kojto | 96:487b796308b0 | 222 | #define __HAL_PWR_PVD_EXTI_ENABLE_IT() SET_BIT(EXTI->IMR, PWR_EXTI_LINE_PVD) |
| Kojto | 96:487b796308b0 | 223 | |
| Kojto | 96:487b796308b0 | 224 | /** |
| Kojto | 96:487b796308b0 | 225 | * @brief Disable interrupt on PVD Exti Line 16. |
| Kojto | 96:487b796308b0 | 226 | * @retval None. |
| Kojto | 96:487b796308b0 | 227 | */ |
| Kojto | 96:487b796308b0 | 228 | #define __HAL_PWR_PVD_EXTI_DISABLE_IT() CLEAR_BIT(EXTI->IMR, PWR_EXTI_LINE_PVD) |
| Kojto | 96:487b796308b0 | 229 | |
| Kojto | 96:487b796308b0 | 230 | /** |
| Kojto | 96:487b796308b0 | 231 | * @brief Enable event on PVD Exti Line 16. |
| Kojto | 96:487b796308b0 | 232 | * @retval None. |
| Kojto | 96:487b796308b0 | 233 | */ |
| Kojto | 96:487b796308b0 | 234 | #define __HAL_PWR_PVD_EXTI_ENABLE_EVENT() SET_BIT(EXTI->EMR, PWR_EXTI_LINE_PVD) |
| Kojto | 96:487b796308b0 | 235 | |
| Kojto | 96:487b796308b0 | 236 | /** |
| Kojto | 96:487b796308b0 | 237 | * @brief Disable event on PVD Exti Line 16. |
| Kojto | 96:487b796308b0 | 238 | * @retval None. |
| Kojto | 96:487b796308b0 | 239 | */ |
| Kojto | 96:487b796308b0 | 240 | #define __HAL_PWR_PVD_EXTI_DISABLE_EVENT() CLEAR_BIT(EXTI->EMR, PWR_EXTI_LINE_PVD) |
| Kojto | 96:487b796308b0 | 241 | |
| Kojto | 96:487b796308b0 | 242 | |
| Kojto | 96:487b796308b0 | 243 | /** |
| Kojto | 96:487b796308b0 | 244 | * @brief PVD EXTI line configuration: set falling edge trigger. |
| Kojto | 96:487b796308b0 | 245 | * @retval None. |
| Kojto | 96:487b796308b0 | 246 | */ |
| Kojto | 96:487b796308b0 | 247 | #define __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE() SET_BIT(EXTI->FTSR, PWR_EXTI_LINE_PVD) |
| Kojto | 96:487b796308b0 | 248 | |
| Kojto | 96:487b796308b0 | 249 | |
| Kojto | 96:487b796308b0 | 250 | /** |
| Kojto | 96:487b796308b0 | 251 | * @brief Disable the PVD Extended Interrupt Falling Trigger. |
| Kojto | 96:487b796308b0 | 252 | * @retval None. |
| Kojto | 96:487b796308b0 | 253 | */ |
| Kojto | 96:487b796308b0 | 254 | #define __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE() CLEAR_BIT(EXTI->FTSR, PWR_EXTI_LINE_PVD) |
| Kojto | 96:487b796308b0 | 255 | |
| Kojto | 96:487b796308b0 | 256 | |
| Kojto | 96:487b796308b0 | 257 | /** |
| Kojto | 96:487b796308b0 | 258 | * @brief PVD EXTI line configuration: set rising edge trigger. |
| Kojto | 96:487b796308b0 | 259 | * @retval None. |
| Kojto | 96:487b796308b0 | 260 | */ |
| Kojto | 96:487b796308b0 | 261 | #define __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE() SET_BIT(EXTI->RTSR, PWR_EXTI_LINE_PVD) |
| Kojto | 96:487b796308b0 | 262 | |
| Kojto | 96:487b796308b0 | 263 | /** |
| Kojto | 96:487b796308b0 | 264 | * @brief Disable the PVD Extended Interrupt Rising Trigger. |
| Kojto | 96:487b796308b0 | 265 | * This parameter can be: |
| Kojto | 96:487b796308b0 | 266 | * @retval None. |
| Kojto | 96:487b796308b0 | 267 | */ |
| Kojto | 96:487b796308b0 | 268 | #define __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE() CLEAR_BIT(EXTI->RTSR, PWR_EXTI_LINE_PVD) |
| Kojto | 96:487b796308b0 | 269 | |
| Kojto | 96:487b796308b0 | 270 | /** |
| Kojto | 96:487b796308b0 | 271 | * @brief PVD EXTI line configuration: set rising & falling edge trigger. |
| Kojto | 96:487b796308b0 | 272 | * @retval None. |
| Kojto | 96:487b796308b0 | 273 | */ |
| Kojto | 96:487b796308b0 | 274 | #define __HAL_PWR_PVD_EXTI_ENABLE_RISING_FALLING_EDGE() __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE();__HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE(); |
| Kojto | 96:487b796308b0 | 275 | |
| Kojto | 96:487b796308b0 | 276 | /** |
| Kojto | 96:487b796308b0 | 277 | * @brief Disable the PVD Extended Interrupt Rising & Falling Trigger. |
| Kojto | 96:487b796308b0 | 278 | * This parameter can be: |
| Kojto | 96:487b796308b0 | 279 | * @retval None. |
| Kojto | 96:487b796308b0 | 280 | */ |
| Kojto | 96:487b796308b0 | 281 | #define __HAL_PWR_PVD_EXTI_DISABLE_RISING_FALLING_EDGE() __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE();__HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE(); |
| Kojto | 96:487b796308b0 | 282 | |
| Kojto | 96:487b796308b0 | 283 | |
| Kojto | 96:487b796308b0 | 284 | |
| Kojto | 96:487b796308b0 | 285 | /** |
| Kojto | 96:487b796308b0 | 286 | * @brief Check whether the specified PVD EXTI interrupt flag is set or not. |
| Kojto | 96:487b796308b0 | 287 | * @retval EXTI PVD Line Status. |
| Kojto | 96:487b796308b0 | 288 | */ |
| Kojto | 96:487b796308b0 | 289 | #define __HAL_PWR_PVD_EXTI_GET_FLAG() (EXTI->PR & (PWR_EXTI_LINE_PVD)) |
| Kojto | 96:487b796308b0 | 290 | |
| Kojto | 96:487b796308b0 | 291 | /** |
| Kojto | 96:487b796308b0 | 292 | * @brief Clear the PVD EXTI flag. |
| Kojto | 96:487b796308b0 | 293 | * @retval None. |
| Kojto | 96:487b796308b0 | 294 | */ |
| Kojto | 96:487b796308b0 | 295 | #define __HAL_PWR_PVD_EXTI_CLEAR_FLAG() (EXTI->PR = (PWR_EXTI_LINE_PVD)) |
| Kojto | 96:487b796308b0 | 296 | |
| Kojto | 96:487b796308b0 | 297 | /** |
| Kojto | 96:487b796308b0 | 298 | * @brief Generate a Software interrupt on selected EXTI line. |
| Kojto | 96:487b796308b0 | 299 | * @retval None. |
| Kojto | 96:487b796308b0 | 300 | */ |
| Kojto | 96:487b796308b0 | 301 | #define __HAL_PWR_PVD_EXTI_GENERATE_SWIT() SET_BIT(EXTI->SWIER, PWR_EXTI_LINE_PVD) |
| Kojto | 96:487b796308b0 | 302 | /** |
| Kojto | 96:487b796308b0 | 303 | * @} |
| Kojto | 96:487b796308b0 | 304 | */ |
| Kojto | 96:487b796308b0 | 305 | |
| Kojto | 96:487b796308b0 | 306 | /* Private macro -------------------------------------------------------------*/ |
| Kojto | 96:487b796308b0 | 307 | /** @defgroup PWR_Private_Macros PWR Private Macros |
| Kojto | 96:487b796308b0 | 308 | * @{ |
| Kojto | 96:487b796308b0 | 309 | */ |
| Kojto | 96:487b796308b0 | 310 | #define IS_PWR_PVD_LEVEL(LEVEL) (((LEVEL) == PWR_PVDLEVEL_0) || ((LEVEL) == PWR_PVDLEVEL_1)|| \ |
| Kojto | 96:487b796308b0 | 311 | ((LEVEL) == PWR_PVDLEVEL_2) || ((LEVEL) == PWR_PVDLEVEL_3)|| \ |
| Kojto | 96:487b796308b0 | 312 | ((LEVEL) == PWR_PVDLEVEL_4) || ((LEVEL) == PWR_PVDLEVEL_5)|| \ |
| Kojto | 96:487b796308b0 | 313 | ((LEVEL) == PWR_PVDLEVEL_6) || ((LEVEL) == PWR_PVDLEVEL_7)) |
| Kojto | 96:487b796308b0 | 314 | |
| Kojto | 96:487b796308b0 | 315 | |
| Kojto | 96:487b796308b0 | 316 | #define IS_PWR_PVD_MODE(MODE) (((MODE) == PWR_PVD_MODE_IT_RISING)|| ((MODE) == PWR_PVD_MODE_IT_FALLING) || \ |
| Kojto | 96:487b796308b0 | 317 | ((MODE) == PWR_PVD_MODE_IT_RISING_FALLING) || ((MODE) == PWR_PVD_MODE_EVENT_RISING) || \ |
| Kojto | 96:487b796308b0 | 318 | ((MODE) == PWR_PVD_MODE_EVENT_FALLING) || ((MODE) == PWR_PVD_MODE_EVENT_RISING_FALLING) || \ |
| Kojto | 96:487b796308b0 | 319 | ((MODE) == PWR_PVD_MODE_NORMAL)) |
| Kojto | 96:487b796308b0 | 320 | |
| Kojto | 96:487b796308b0 | 321 | #define IS_PWR_WAKEUP_PIN(PIN) (((PIN) == PWR_WAKEUP_PIN1)) |
| Kojto | 96:487b796308b0 | 322 | |
| Kojto | 96:487b796308b0 | 323 | #define IS_PWR_REGULATOR(REGULATOR) (((REGULATOR) == PWR_MAINREGULATOR_ON) || \ |
| Kojto | 96:487b796308b0 | 324 | ((REGULATOR) == PWR_LOWPOWERREGULATOR_ON)) |
| Kojto | 96:487b796308b0 | 325 | |
| Kojto | 96:487b796308b0 | 326 | #define IS_PWR_SLEEP_ENTRY(ENTRY) (((ENTRY) == PWR_SLEEPENTRY_WFI) || ((ENTRY) == PWR_SLEEPENTRY_WFE)) |
| Kojto | 96:487b796308b0 | 327 | |
| Kojto | 96:487b796308b0 | 328 | #define IS_PWR_STOP_ENTRY(ENTRY) (((ENTRY) == PWR_STOPENTRY_WFI) || ((ENTRY) == PWR_STOPENTRY_WFE)) |
| Kojto | 96:487b796308b0 | 329 | |
| Kojto | 96:487b796308b0 | 330 | /** |
| Kojto | 96:487b796308b0 | 331 | * @} |
| Kojto | 96:487b796308b0 | 332 | */ |
| Kojto | 96:487b796308b0 | 333 | |
| Kojto | 96:487b796308b0 | 334 | |
| Kojto | 96:487b796308b0 | 335 | |
| Kojto | 96:487b796308b0 | 336 | /* Exported functions --------------------------------------------------------*/ |
| Kojto | 96:487b796308b0 | 337 | |
| Kojto | 96:487b796308b0 | 338 | /** @addtogroup PWR_Exported_Functions PWR Exported Functions |
| Kojto | 96:487b796308b0 | 339 | * @{ |
| Kojto | 96:487b796308b0 | 340 | */ |
| Kojto | 96:487b796308b0 | 341 | |
| Kojto | 96:487b796308b0 | 342 | /** @addtogroup PWR_Exported_Functions_Group1 Initialization and de-initialization functions |
| Kojto | 96:487b796308b0 | 343 | * @{ |
| Kojto | 96:487b796308b0 | 344 | */ |
| Kojto | 96:487b796308b0 | 345 | |
| Kojto | 96:487b796308b0 | 346 | /* Initialization and de-initialization functions *******************************/ |
| Kojto | 96:487b796308b0 | 347 | void HAL_PWR_DeInit(void); |
| Kojto | 96:487b796308b0 | 348 | void HAL_PWR_EnableBkUpAccess(void); |
| Kojto | 96:487b796308b0 | 349 | void HAL_PWR_DisableBkUpAccess(void); |
| Kojto | 96:487b796308b0 | 350 | |
| Kojto | 96:487b796308b0 | 351 | /** |
| Kojto | 96:487b796308b0 | 352 | * @} |
| Kojto | 96:487b796308b0 | 353 | */ |
| Kojto | 96:487b796308b0 | 354 | |
| Kojto | 96:487b796308b0 | 355 | /** @addtogroup PWR_Exported_Functions_Group2 Peripheral Control functions |
| Kojto | 96:487b796308b0 | 356 | * @{ |
| Kojto | 96:487b796308b0 | 357 | */ |
| Kojto | 96:487b796308b0 | 358 | |
| Kojto | 96:487b796308b0 | 359 | /* Peripheral Control functions ************************************************/ |
| Kojto | 96:487b796308b0 | 360 | void HAL_PWR_ConfigPVD(PWR_PVDTypeDef *sConfigPVD); |
| Kojto | 96:487b796308b0 | 361 | /* #define HAL_PWR_ConfigPVD 12*/ |
| Kojto | 96:487b796308b0 | 362 | void HAL_PWR_EnablePVD(void); |
| Kojto | 96:487b796308b0 | 363 | void HAL_PWR_DisablePVD(void); |
| Kojto | 96:487b796308b0 | 364 | |
| Kojto | 96:487b796308b0 | 365 | /* WakeUp pins configuration functions ****************************************/ |
| Kojto | 96:487b796308b0 | 366 | void HAL_PWR_EnableWakeUpPin(uint32_t WakeUpPinx); |
| Kojto | 96:487b796308b0 | 367 | void HAL_PWR_DisableWakeUpPin(uint32_t WakeUpPinx); |
| Kojto | 96:487b796308b0 | 368 | |
| Kojto | 96:487b796308b0 | 369 | /* Low Power modes configuration functions ************************************/ |
| Kojto | 96:487b796308b0 | 370 | void HAL_PWR_EnterSTOPMode(uint32_t Regulator, uint8_t STOPEntry); |
| Kojto | 96:487b796308b0 | 371 | void HAL_PWR_EnterSLEEPMode(uint32_t Regulator, uint8_t SLEEPEntry); |
| Kojto | 96:487b796308b0 | 372 | void HAL_PWR_EnterSTANDBYMode(void); |
| Kojto | 96:487b796308b0 | 373 | |
| Kojto | 96:487b796308b0 | 374 | void HAL_PWR_EnableSleepOnExit(void); |
| Kojto | 96:487b796308b0 | 375 | void HAL_PWR_DisableSleepOnExit(void); |
| Kojto | 96:487b796308b0 | 376 | void HAL_PWR_EnableSEVOnPend(void); |
| Kojto | 96:487b796308b0 | 377 | void HAL_PWR_DisableSEVOnPend(void); |
| Kojto | 96:487b796308b0 | 378 | |
| Kojto | 96:487b796308b0 | 379 | |
| Kojto | 96:487b796308b0 | 380 | |
| Kojto | 96:487b796308b0 | 381 | void HAL_PWR_PVD_IRQHandler(void); |
| Kojto | 96:487b796308b0 | 382 | void HAL_PWR_PVDCallback(void); |
| Kojto | 96:487b796308b0 | 383 | /** |
| Kojto | 96:487b796308b0 | 384 | * @} |
| Kojto | 96:487b796308b0 | 385 | */ |
| Kojto | 96:487b796308b0 | 386 | |
| Kojto | 96:487b796308b0 | 387 | /** |
| Kojto | 96:487b796308b0 | 388 | * @} |
| Kojto | 96:487b796308b0 | 389 | */ |
| Kojto | 96:487b796308b0 | 390 | |
| Kojto | 96:487b796308b0 | 391 | /** |
| Kojto | 96:487b796308b0 | 392 | * @} |
| Kojto | 96:487b796308b0 | 393 | */ |
| Kojto | 96:487b796308b0 | 394 | |
| Kojto | 96:487b796308b0 | 395 | /** |
| Kojto | 96:487b796308b0 | 396 | * @} |
| Kojto | 96:487b796308b0 | 397 | */ |
| Kojto | 96:487b796308b0 | 398 | |
| Kojto | 96:487b796308b0 | 399 | #ifdef __cplusplus |
| Kojto | 96:487b796308b0 | 400 | } |
| Kojto | 96:487b796308b0 | 401 | #endif |
| Kojto | 96:487b796308b0 | 402 | |
| Kojto | 96:487b796308b0 | 403 | |
| Kojto | 96:487b796308b0 | 404 | #endif /* __STM32F1xx_HAL_PWR_H */ |
| Kojto | 96:487b796308b0 | 405 | |
| Kojto | 96:487b796308b0 | 406 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |