雄介 太田 / mbed

mbed(SerialHalfDuplex入り)

Fork of mbed by mbed official

LPC2368/core_arm7.h@11:1c1ebd0324fa, 2009-08-28 (annotated)

Committer:
rolf.meyer@arm.com
Date:
Fri Aug 28 12:10:11 2009 +0000
Revision:
11:1c1ebd0324fa
A shiny new version

Who changed what in which revision?

UserRevisionLine numberNew contents of line
rolf.meyer@arm.com 11:1c1ebd0324fa 1 /* mbed Microcontroller Library
rolf.meyer@arm.com 11:1c1ebd0324fa 2 * Copyright (C) 2008-2009 ARM Limited. All rights reserved.
rolf.meyer@arm.com 11:1c1ebd0324fa 3 *
rolf.meyer@arm.com 11:1c1ebd0324fa 4 * ARM7 version of CMSIS-like functionality - not advised for use outside mbed!
rolf.meyer@arm.com 11:1c1ebd0324fa 5 * based on core_cm3.h, V1.20
rolf.meyer@arm.com 11:1c1ebd0324fa 6 */
rolf.meyer@arm.com 11:1c1ebd0324fa 7
rolf.meyer@arm.com 11:1c1ebd0324fa 8 #ifndef __ARM7_CORE_H__
rolf.meyer@arm.com 11:1c1ebd0324fa 9 #define __ARM7_CORE_H__
rolf.meyer@arm.com 11:1c1ebd0324fa 10
rolf.meyer@arm.com 11:1c1ebd0324fa 11 #ifdef __cplusplus
rolf.meyer@arm.com 11:1c1ebd0324fa 12 extern "C" {
rolf.meyer@arm.com 11:1c1ebd0324fa 13 #endif
rolf.meyer@arm.com 11:1c1ebd0324fa 14
rolf.meyer@arm.com 11:1c1ebd0324fa 15 #define __CM3_CMSIS_VERSION_MAIN (0x01) /*!< [31:16] CMSIS HAL main version */
rolf.meyer@arm.com 11:1c1ebd0324fa 16 #define __CM3_CMSIS_VERSION_SUB (0x20) /*!< [15:0] CMSIS HAL sub version */
rolf.meyer@arm.com 11:1c1ebd0324fa 17 #define __CM3_CMSIS_VERSION ((__CM3_CMSIS_VERSION_MAIN << 16) | __CM3_CMSIS_VERSION_SUB) /*!< CMSIS HAL version number */
rolf.meyer@arm.com 11:1c1ebd0324fa 18
rolf.meyer@arm.com 11:1c1ebd0324fa 19 #define __CORTEX_M (0x03) /*!< Cortex core */
rolf.meyer@arm.com 11:1c1ebd0324fa 20
rolf.meyer@arm.com 11:1c1ebd0324fa 21 /**
rolf.meyer@arm.com 11:1c1ebd0324fa 22 * Lint configuration \n
rolf.meyer@arm.com 11:1c1ebd0324fa 23 * ----------------------- \n
rolf.meyer@arm.com 11:1c1ebd0324fa 24 *
rolf.meyer@arm.com 11:1c1ebd0324fa 25 * The following Lint messages will be suppressed and not shown: \n
rolf.meyer@arm.com 11:1c1ebd0324fa 26 * \n
rolf.meyer@arm.com 11:1c1ebd0324fa 27 * --- Error 10: --- \n
rolf.meyer@arm.com 11:1c1ebd0324fa 28 * register uint32_t __regBasePri __asm("basepri"); \n
rolf.meyer@arm.com 11:1c1ebd0324fa 29 * Error 10: Expecting ';' \n
rolf.meyer@arm.com 11:1c1ebd0324fa 30 * \n
rolf.meyer@arm.com 11:1c1ebd0324fa 31 * --- Error 530: --- \n
rolf.meyer@arm.com 11:1c1ebd0324fa 32 * return(__regBasePri); \n
rolf.meyer@arm.com 11:1c1ebd0324fa 33 * Warning 530: Symbol '__regBasePri' (line 264) not initialized \n
rolf.meyer@arm.com 11:1c1ebd0324fa 34 * \n
rolf.meyer@arm.com 11:1c1ebd0324fa 35 * --- Error 550: --- \n
rolf.meyer@arm.com 11:1c1ebd0324fa 36 * __regBasePri = (basePri & 0x1ff); \n
rolf.meyer@arm.com 11:1c1ebd0324fa 37 * } \n
rolf.meyer@arm.com 11:1c1ebd0324fa 38 * Warning 550: Symbol '__regBasePri' (line 271) not accessed \n
rolf.meyer@arm.com 11:1c1ebd0324fa 39 * \n
rolf.meyer@arm.com 11:1c1ebd0324fa 40 * --- Error 754: --- \n
rolf.meyer@arm.com 11:1c1ebd0324fa 41 * uint32_t RESERVED0[24]; \n
rolf.meyer@arm.com 11:1c1ebd0324fa 42 * Info 754: local structure member '<some, not used in the HAL>' (line 109, file ./cm3_core.h) not referenced \n
rolf.meyer@arm.com 11:1c1ebd0324fa 43 * \n
rolf.meyer@arm.com 11:1c1ebd0324fa 44 * --- Error 750: --- \n
rolf.meyer@arm.com 11:1c1ebd0324fa 45 * #define __CM3_CORE_H__ \n
rolf.meyer@arm.com 11:1c1ebd0324fa 46 * Info 750: local macro '__CM3_CORE_H__' (line 43, file./cm3_core.h) not referenced \n
rolf.meyer@arm.com 11:1c1ebd0324fa 47 * \n
rolf.meyer@arm.com 11:1c1ebd0324fa 48 * --- Error 528: --- \n
rolf.meyer@arm.com 11:1c1ebd0324fa 49 * static __INLINE void NVIC_DisableIRQ(uint32_t IRQn) \n
rolf.meyer@arm.com 11:1c1ebd0324fa 50 * Warning 528: Symbol 'NVIC_DisableIRQ(unsigned int)' (line 419, file ./cm3_core.h) not referenced \n
rolf.meyer@arm.com 11:1c1ebd0324fa 51 * \n
rolf.meyer@arm.com 11:1c1ebd0324fa 52 * --- Error 751: --- \n
rolf.meyer@arm.com 11:1c1ebd0324fa 53 * } InterruptType_Type; \n
rolf.meyer@arm.com 11:1c1ebd0324fa 54 * Info 751: local typedef 'InterruptType_Type' (line 170, file ./cm3_core.h) not referenced \n
rolf.meyer@arm.com 11:1c1ebd0324fa 55 * \n
rolf.meyer@arm.com 11:1c1ebd0324fa 56 * \n
rolf.meyer@arm.com 11:1c1ebd0324fa 57 * Note: To re-enable a Message, insert a space before 'lint' * \n
rolf.meyer@arm.com 11:1c1ebd0324fa 58 *
rolf.meyer@arm.com 11:1c1ebd0324fa 59 */
rolf.meyer@arm.com 11:1c1ebd0324fa 60
rolf.meyer@arm.com 11:1c1ebd0324fa 61 /*lint -save */
rolf.meyer@arm.com 11:1c1ebd0324fa 62 /*lint -e10 */
rolf.meyer@arm.com 11:1c1ebd0324fa 63 /*lint -e530 */
rolf.meyer@arm.com 11:1c1ebd0324fa 64 /*lint -e550 */
rolf.meyer@arm.com 11:1c1ebd0324fa 65 /*lint -e754 */
rolf.meyer@arm.com 11:1c1ebd0324fa 66 /*lint -e750 */
rolf.meyer@arm.com 11:1c1ebd0324fa 67 /*lint -e528 */
rolf.meyer@arm.com 11:1c1ebd0324fa 68 /*lint -e751 */
rolf.meyer@arm.com 11:1c1ebd0324fa 69
rolf.meyer@arm.com 11:1c1ebd0324fa 70 #include <stdint.h> /* Include standard types */
rolf.meyer@arm.com 11:1c1ebd0324fa 71
rolf.meyer@arm.com 11:1c1ebd0324fa 72 /**
rolf.meyer@arm.com 11:1c1ebd0324fa 73 * @brief Return the Main Stack Pointer (current ARM7 stack)
rolf.meyer@arm.com 11:1c1ebd0324fa 74 *
rolf.meyer@arm.com 11:1c1ebd0324fa 75 * @param none
rolf.meyer@arm.com 11:1c1ebd0324fa 76 * @return uint32_t Main Stack Pointer
rolf.meyer@arm.com 11:1c1ebd0324fa 77 *
rolf.meyer@arm.com 11:1c1ebd0324fa 78 * Return the current value of the MSP (main stack pointer)
rolf.meyer@arm.com 11:1c1ebd0324fa 79 * Cortex processor register
rolf.meyer@arm.com 11:1c1ebd0324fa 80 */
rolf.meyer@arm.com 11:1c1ebd0324fa 81 extern uint32_t __get_MSP(void);
rolf.meyer@arm.com 11:1c1ebd0324fa 82
rolf.meyer@arm.com 11:1c1ebd0324fa 83
rolf.meyer@arm.com 11:1c1ebd0324fa 84
rolf.meyer@arm.com 11:1c1ebd0324fa 85 #if defined (__ICCARM__)
rolf.meyer@arm.com 11:1c1ebd0324fa 86 #include <intrinsics.h> /* IAR Intrinsics */
rolf.meyer@arm.com 11:1c1ebd0324fa 87 #endif
rolf.meyer@arm.com 11:1c1ebd0324fa 88
rolf.meyer@arm.com 11:1c1ebd0324fa 89
rolf.meyer@arm.com 11:1c1ebd0324fa 90 #ifndef __NVIC_PRIO_BITS
rolf.meyer@arm.com 11:1c1ebd0324fa 91 #define __NVIC_PRIO_BITS 4 /*!< standard definition for NVIC Priority Bits */
rolf.meyer@arm.com 11:1c1ebd0324fa 92 #endif
rolf.meyer@arm.com 11:1c1ebd0324fa 93
rolf.meyer@arm.com 11:1c1ebd0324fa 94 typedef struct
rolf.meyer@arm.com 11:1c1ebd0324fa 95 {
rolf.meyer@arm.com 11:1c1ebd0324fa 96 uint32_t IRQStatus;
rolf.meyer@arm.com 11:1c1ebd0324fa 97 uint32_t FIQStatus;
rolf.meyer@arm.com 11:1c1ebd0324fa 98 uint32_t RawIntr;
rolf.meyer@arm.com 11:1c1ebd0324fa 99 uint32_t IntSelect;
rolf.meyer@arm.com 11:1c1ebd0324fa 100 uint32_t IntEnable;
rolf.meyer@arm.com 11:1c1ebd0324fa 101 uint32_t IntEnClr;
rolf.meyer@arm.com 11:1c1ebd0324fa 102 uint32_t SoftInt;
rolf.meyer@arm.com 11:1c1ebd0324fa 103 uint32_t SoftIntClr;
rolf.meyer@arm.com 11:1c1ebd0324fa 104 uint32_t Protection;
rolf.meyer@arm.com 11:1c1ebd0324fa 105 uint32_t SWPriorityMask;
rolf.meyer@arm.com 11:1c1ebd0324fa 106 uint32_t RESERVED0[54];
rolf.meyer@arm.com 11:1c1ebd0324fa 107 uint32_t VectAddr[32];
rolf.meyer@arm.com 11:1c1ebd0324fa 108 uint32_t RESERVED1[32];
rolf.meyer@arm.com 11:1c1ebd0324fa 109 uint32_t VectPriority[32];
rolf.meyer@arm.com 11:1c1ebd0324fa 110 uint32_t RESERVED2[800];
rolf.meyer@arm.com 11:1c1ebd0324fa 111 uint32_t Address;
rolf.meyer@arm.com 11:1c1ebd0324fa 112 } NVIC_TypeDef;
rolf.meyer@arm.com 11:1c1ebd0324fa 113
rolf.meyer@arm.com 11:1c1ebd0324fa 114 #define NVIC_BASE (0xFFFFF000)
rolf.meyer@arm.com 11:1c1ebd0324fa 115 #define NVIC (( NVIC_TypeDef *) NVIC_BASE)
rolf.meyer@arm.com 11:1c1ebd0324fa 116
rolf.meyer@arm.com 11:1c1ebd0324fa 117
rolf.meyer@arm.com 11:1c1ebd0324fa 118
rolf.meyer@arm.com 11:1c1ebd0324fa 119 /**
rolf.meyer@arm.com 11:1c1ebd0324fa 120 * IO definitions
rolf.meyer@arm.com 11:1c1ebd0324fa 121 *
rolf.meyer@arm.com 11:1c1ebd0324fa 122 * define access restrictions to peripheral registers
rolf.meyer@arm.com 11:1c1ebd0324fa 123 */
rolf.meyer@arm.com 11:1c1ebd0324fa 124
rolf.meyer@arm.com 11:1c1ebd0324fa 125 #ifdef __cplusplus
rolf.meyer@arm.com 11:1c1ebd0324fa 126 #define __I volatile /*!< defines 'read only' permissions */
rolf.meyer@arm.com 11:1c1ebd0324fa 127 #else
rolf.meyer@arm.com 11:1c1ebd0324fa 128 #define __I volatile const /*!< defines 'read only' permissions */
rolf.meyer@arm.com 11:1c1ebd0324fa 129 #endif
rolf.meyer@arm.com 11:1c1ebd0324fa 130 #define __O volatile /*!< defines 'write only' permissions */
rolf.meyer@arm.com 11:1c1ebd0324fa 131 #define __IO volatile /*!< defines 'read / write' permissions */
rolf.meyer@arm.com 11:1c1ebd0324fa 132
rolf.meyer@arm.com 11:1c1ebd0324fa 133
rolf.meyer@arm.com 11:1c1ebd0324fa 134
rolf.meyer@arm.com 11:1c1ebd0324fa 135
rolf.meyer@arm.com 11:1c1ebd0324fa 136
rolf.meyer@arm.com 11:1c1ebd0324fa 137 #if defined ( __CC_ARM )
rolf.meyer@arm.com 11:1c1ebd0324fa 138 #define __ASM __asm /*!< asm keyword for ARM Compiler */
rolf.meyer@arm.com 11:1c1ebd0324fa 139 #define __INLINE __inline /*!< inline keyword for ARM Compiler */
rolf.meyer@arm.com 11:1c1ebd0324fa 140
rolf.meyer@arm.com 11:1c1ebd0324fa 141 #elif defined ( __ICCARM__ )
rolf.meyer@arm.com 11:1c1ebd0324fa 142 #define __ASM __asm /*!< asm keyword for IAR Compiler */
rolf.meyer@arm.com 11:1c1ebd0324fa 143 #define __INLINE inline /*!< inline keyword for IAR Compiler. Only avaiable in High optimization mode! */
rolf.meyer@arm.com 11:1c1ebd0324fa 144
rolf.meyer@arm.com 11:1c1ebd0324fa 145 #elif defined ( __GNUC__ )
rolf.meyer@arm.com 11:1c1ebd0324fa 146 #define __ASM __asm /*!< asm keyword for GNU Compiler */
rolf.meyer@arm.com 11:1c1ebd0324fa 147 #define __INLINE inline /*!< inline keyword for GNU Compiler */
rolf.meyer@arm.com 11:1c1ebd0324fa 148
rolf.meyer@arm.com 11:1c1ebd0324fa 149 #elif defined ( __TASKING__ )
rolf.meyer@arm.com 11:1c1ebd0324fa 150 #define __ASM __asm /*!< asm keyword for TASKING Compiler */
rolf.meyer@arm.com 11:1c1ebd0324fa 151 #define __INLINE inline /*!< inline keyword for TASKING Compiler */
rolf.meyer@arm.com 11:1c1ebd0324fa 152
rolf.meyer@arm.com 11:1c1ebd0324fa 153 #endif
rolf.meyer@arm.com 11:1c1ebd0324fa 154
rolf.meyer@arm.com 11:1c1ebd0324fa 155
rolf.meyer@arm.com 11:1c1ebd0324fa 156 /* ################### Compiler specific Intrinsics ########################### */
rolf.meyer@arm.com 11:1c1ebd0324fa 157
rolf.meyer@arm.com 11:1c1ebd0324fa 158 #if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
rolf.meyer@arm.com 11:1c1ebd0324fa 159 /* ARM armcc specific functions */
rolf.meyer@arm.com 11:1c1ebd0324fa 160
rolf.meyer@arm.com 11:1c1ebd0324fa 161 #define __enable_fault_irq __enable_fiq
rolf.meyer@arm.com 11:1c1ebd0324fa 162 #define __disable_fault_irq __disable_fiq
rolf.meyer@arm.com 11:1c1ebd0324fa 163
rolf.meyer@arm.com 11:1c1ebd0324fa 164 #define __NOP __nop
rolf.meyer@arm.com 11:1c1ebd0324fa 165 //#define __WFI __wfi
rolf.meyer@arm.com 11:1c1ebd0324fa 166 //#define __WFE __wfe
rolf.meyer@arm.com 11:1c1ebd0324fa 167 //#define __SEV __sev
rolf.meyer@arm.com 11:1c1ebd0324fa 168 //#define __ISB() __isb(0)
rolf.meyer@arm.com 11:1c1ebd0324fa 169 //#define __DSB() __dsb(0)
rolf.meyer@arm.com 11:1c1ebd0324fa 170 //#define __DMB() __dmb(0)
rolf.meyer@arm.com 11:1c1ebd0324fa 171 //#define __REV __rev
rolf.meyer@arm.com 11:1c1ebd0324fa 172 //#define __RBIT __rbit
rolf.meyer@arm.com 11:1c1ebd0324fa 173 #define __LDREXB(ptr) ((unsigned char ) __ldrex(ptr))
rolf.meyer@arm.com 11:1c1ebd0324fa 174 #define __LDREXH(ptr) ((unsigned short) __ldrex(ptr))
rolf.meyer@arm.com 11:1c1ebd0324fa 175 #define __LDREXW(ptr) ((unsigned int ) __ldrex(ptr))
rolf.meyer@arm.com 11:1c1ebd0324fa 176 #define __STREXB(value, ptr) __strex(value, ptr)
rolf.meyer@arm.com 11:1c1ebd0324fa 177 #define __STREXH(value, ptr) __strex(value, ptr)
rolf.meyer@arm.com 11:1c1ebd0324fa 178 #define __STREXW(value, ptr) __strex(value, ptr)
rolf.meyer@arm.com 11:1c1ebd0324fa 179
rolf.meyer@arm.com 11:1c1ebd0324fa 180
rolf.meyer@arm.com 11:1c1ebd0324fa 181 #elif (defined (__ICCARM__)) /*------------------ ICC Compiler -------------------*/
rolf.meyer@arm.com 11:1c1ebd0324fa 182
rolf.meyer@arm.com 11:1c1ebd0324fa 183 #define __enable_irq __enable_interrupt /*!< global Interrupt enable */
rolf.meyer@arm.com 11:1c1ebd0324fa 184 #define __disable_irq __disable_interrupt /*!< global Interrupt disable */
rolf.meyer@arm.com 11:1c1ebd0324fa 185 #define __NOP __no_operation() /*!< no operation intrinsic in IAR Compiler */
rolf.meyer@arm.com 11:1c1ebd0324fa 186
rolf.meyer@arm.com 11:1c1ebd0324fa 187 #elif (defined (__GNUC__)) /*------------------ GNU Compiler ---------------------*/
rolf.meyer@arm.com 11:1c1ebd0324fa 188
rolf.meyer@arm.com 11:1c1ebd0324fa 189 static __INLINE void __enable_irq() { __ASM volatile ("cpsie i"); }
rolf.meyer@arm.com 11:1c1ebd0324fa 190 static __INLINE void __disable_irq() { __ASM volatile ("cpsid i"); }
rolf.meyer@arm.com 11:1c1ebd0324fa 191
rolf.meyer@arm.com 11:1c1ebd0324fa 192 static __INLINE void __NOP() { __ASM volatile ("nop"); }
rolf.meyer@arm.com 11:1c1ebd0324fa 193
rolf.meyer@arm.com 11:1c1ebd0324fa 194 #elif (defined (__TASKING__)) /*------------------ TASKING Compiler ---------------------*/
rolf.meyer@arm.com 11:1c1ebd0324fa 195 /* TASKING carm specific functions */
rolf.meyer@arm.com 11:1c1ebd0324fa 196
rolf.meyer@arm.com 11:1c1ebd0324fa 197 /*
rolf.meyer@arm.com 11:1c1ebd0324fa 198 * The CMSIS functions have been implemented as intrinsics in the compiler.
rolf.meyer@arm.com 11:1c1ebd0324fa 199 * Please use "carm -?i" to get an up to date list of all instrinsics,
rolf.meyer@arm.com 11:1c1ebd0324fa 200 * Including the CMSIS ones.
rolf.meyer@arm.com 11:1c1ebd0324fa 201 */
rolf.meyer@arm.com 11:1c1ebd0324fa 202
rolf.meyer@arm.com 11:1c1ebd0324fa 203 #endif
rolf.meyer@arm.com 11:1c1ebd0324fa 204
rolf.meyer@arm.com 11:1c1ebd0324fa 205
rolf.meyer@arm.com 11:1c1ebd0324fa 206 /**
rolf.meyer@arm.com 11:1c1ebd0324fa 207 * @brief Enable Interrupt in NVIC Interrupt Controller
rolf.meyer@arm.com 11:1c1ebd0324fa 208 *
rolf.meyer@arm.com 11:1c1ebd0324fa 209 * @param IRQn_Type IRQn specifies the interrupt number
rolf.meyer@arm.com 11:1c1ebd0324fa 210 * @return none
rolf.meyer@arm.com 11:1c1ebd0324fa 211 *
rolf.meyer@arm.com 11:1c1ebd0324fa 212 * Enable a device specific interupt in the NVIC interrupt controller.
rolf.meyer@arm.com 11:1c1ebd0324fa 213 * The interrupt number cannot be a negative value.
rolf.meyer@arm.com 11:1c1ebd0324fa 214 */
rolf.meyer@arm.com 11:1c1ebd0324fa 215 static __INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
rolf.meyer@arm.com 11:1c1ebd0324fa 216 {
rolf.meyer@arm.com 11:1c1ebd0324fa 217 NVIC->IntEnable = 1 << (uint32_t)IRQn;
rolf.meyer@arm.com 11:1c1ebd0324fa 218 }
rolf.meyer@arm.com 11:1c1ebd0324fa 219
rolf.meyer@arm.com 11:1c1ebd0324fa 220
rolf.meyer@arm.com 11:1c1ebd0324fa 221 /**
rolf.meyer@arm.com 11:1c1ebd0324fa 222 * @brief Disable the interrupt line for external interrupt specified
rolf.meyer@arm.com 11:1c1ebd0324fa 223 *
rolf.meyer@arm.com 11:1c1ebd0324fa 224 * @param IRQn_Type IRQn is the positive number of the external interrupt
rolf.meyer@arm.com 11:1c1ebd0324fa 225 * @return none
rolf.meyer@arm.com 11:1c1ebd0324fa 226 *
rolf.meyer@arm.com 11:1c1ebd0324fa 227 * Disable a device specific interupt in the NVIC interrupt controller.
rolf.meyer@arm.com 11:1c1ebd0324fa 228 * The interrupt number cannot be a negative value.
rolf.meyer@arm.com 11:1c1ebd0324fa 229 */
rolf.meyer@arm.com 11:1c1ebd0324fa 230 static __INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
rolf.meyer@arm.com 11:1c1ebd0324fa 231 {
rolf.meyer@arm.com 11:1c1ebd0324fa 232 NVIC->IntEnClr = 1 << (uint32_t)IRQn;
rolf.meyer@arm.com 11:1c1ebd0324fa 233 }
rolf.meyer@arm.com 11:1c1ebd0324fa 234
rolf.meyer@arm.com 11:1c1ebd0324fa 235
rolf.meyer@arm.com 11:1c1ebd0324fa 236 #ifdef __cplusplus
rolf.meyer@arm.com 11:1c1ebd0324fa 237 }
rolf.meyer@arm.com 11:1c1ebd0324fa 238 #endif
rolf.meyer@arm.com 11:1c1ebd0324fa 239
rolf.meyer@arm.com 11:1c1ebd0324fa 240 #endif /* __ARM7_CORE_H__ */
rolf.meyer@arm.com 11:1c1ebd0324fa 241
rolf.meyer@arm.com 11:1c1ebd0324fa 242 /*lint -restore */