mbed(SerialHalfDuplex入り)
Fork of mbed by
TARGET_NUCLEO_F334R8/stm32f334x8.h@86:04dd9b1680ae, 2014-07-02 (annotated)
- Committer:
- bogdanm
- Date:
- Wed Jul 02 13:22:23 2014 +0100
- Revision:
- 86:04dd9b1680ae
- Child:
- 92:4fc01daae5a5
Release 86 of the mbed library
Main changes:
- bug fixes in various backends
- mbed "error" replaced by assert logic (mbed_assert)
- new ST Nucleo targets
Who changed what in which revision?
User | Revision | Line number | New contents of line |
---|---|---|---|
bogdanm | 86:04dd9b1680ae | 1 | /** |
bogdanm | 86:04dd9b1680ae | 2 | ****************************************************************************** |
bogdanm | 86:04dd9b1680ae | 3 | * @file stm32f334x8.h |
bogdanm | 86:04dd9b1680ae | 4 | * @author MCD Application Team |
bogdanm | 86:04dd9b1680ae | 5 | * @version V2.0.1 |
bogdanm | 86:04dd9b1680ae | 6 | * @date 18-June-2014 |
bogdanm | 86:04dd9b1680ae | 7 | * @brief CMSIS STM32F334x4/STM32F334x6/STM32F334x8 Devices Peripheral Access Layer Header File. |
bogdanm | 86:04dd9b1680ae | 8 | * |
bogdanm | 86:04dd9b1680ae | 9 | * This file contains: |
bogdanm | 86:04dd9b1680ae | 10 | * - Data structures and the address mapping for all peripherals |
bogdanm | 86:04dd9b1680ae | 11 | * - Peripheral's registers declarations and bits definition |
bogdanm | 86:04dd9b1680ae | 12 | * - Macros to access peripherals registers hardware |
bogdanm | 86:04dd9b1680ae | 13 | * |
bogdanm | 86:04dd9b1680ae | 14 | ****************************************************************************** |
bogdanm | 86:04dd9b1680ae | 15 | * @attention |
bogdanm | 86:04dd9b1680ae | 16 | * |
bogdanm | 86:04dd9b1680ae | 17 | * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2> |
bogdanm | 86:04dd9b1680ae | 18 | * |
bogdanm | 86:04dd9b1680ae | 19 | * Redistribution and use in source and binary forms, with or without modification, |
bogdanm | 86:04dd9b1680ae | 20 | * are permitted provided that the following conditions are met: |
bogdanm | 86:04dd9b1680ae | 21 | * 1. Redistributions of source code must retain the above copyright notice, |
bogdanm | 86:04dd9b1680ae | 22 | * this list of conditions and the following disclaimer. |
bogdanm | 86:04dd9b1680ae | 23 | * 2. Redistributions in binary form must reproduce the above copyright notice, |
bogdanm | 86:04dd9b1680ae | 24 | * this list of conditions and the following disclaimer in the documentation |
bogdanm | 86:04dd9b1680ae | 25 | * and/or other materials provided with the distribution. |
bogdanm | 86:04dd9b1680ae | 26 | * 3. Neither the name of STMicroelectronics nor the names of its contributors |
bogdanm | 86:04dd9b1680ae | 27 | * may be used to endorse or promote products derived from this software |
bogdanm | 86:04dd9b1680ae | 28 | * without specific prior written permission. |
bogdanm | 86:04dd9b1680ae | 29 | * |
bogdanm | 86:04dd9b1680ae | 30 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
bogdanm | 86:04dd9b1680ae | 31 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
bogdanm | 86:04dd9b1680ae | 32 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
bogdanm | 86:04dd9b1680ae | 33 | * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE |
bogdanm | 86:04dd9b1680ae | 34 | * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
bogdanm | 86:04dd9b1680ae | 35 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR |
bogdanm | 86:04dd9b1680ae | 36 | * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER |
bogdanm | 86:04dd9b1680ae | 37 | * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, |
bogdanm | 86:04dd9b1680ae | 38 | * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE |
bogdanm | 86:04dd9b1680ae | 39 | * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
bogdanm | 86:04dd9b1680ae | 40 | * |
bogdanm | 86:04dd9b1680ae | 41 | ****************************************************************************** |
bogdanm | 86:04dd9b1680ae | 42 | */ |
bogdanm | 86:04dd9b1680ae | 43 | |
bogdanm | 86:04dd9b1680ae | 44 | /** @addtogroup CMSIS_Device |
bogdanm | 86:04dd9b1680ae | 45 | * @{ |
bogdanm | 86:04dd9b1680ae | 46 | */ |
bogdanm | 86:04dd9b1680ae | 47 | |
bogdanm | 86:04dd9b1680ae | 48 | /** @addtogroup stm32f334x8 |
bogdanm | 86:04dd9b1680ae | 49 | * @{ |
bogdanm | 86:04dd9b1680ae | 50 | */ |
bogdanm | 86:04dd9b1680ae | 51 | |
bogdanm | 86:04dd9b1680ae | 52 | #ifndef __STM32F334x8_H |
bogdanm | 86:04dd9b1680ae | 53 | #define __STM32F334x8_H |
bogdanm | 86:04dd9b1680ae | 54 | |
bogdanm | 86:04dd9b1680ae | 55 | #ifdef __cplusplus |
bogdanm | 86:04dd9b1680ae | 56 | extern "C" { |
bogdanm | 86:04dd9b1680ae | 57 | #endif /* __cplusplus */ |
bogdanm | 86:04dd9b1680ae | 58 | |
bogdanm | 86:04dd9b1680ae | 59 | /** @addtogroup Configuration_section_for_CMSIS |
bogdanm | 86:04dd9b1680ae | 60 | * @{ |
bogdanm | 86:04dd9b1680ae | 61 | */ |
bogdanm | 86:04dd9b1680ae | 62 | |
bogdanm | 86:04dd9b1680ae | 63 | /** |
bogdanm | 86:04dd9b1680ae | 64 | * @brief Configuration of the Cortex-M4 Processor and Core Peripherals |
bogdanm | 86:04dd9b1680ae | 65 | */ |
bogdanm | 86:04dd9b1680ae | 66 | #define __CM4_REV 0x0001 /*!< Core revision r0p1 */ |
bogdanm | 86:04dd9b1680ae | 67 | #define __MPU_PRESENT 0 /*!< STM32F334x4/STM32F334x6/STM32F334x8 devices do not provide an MPU */ |
bogdanm | 86:04dd9b1680ae | 68 | #define __NVIC_PRIO_BITS 4 /*!< STM32F334x4/STM32F334x6/STM32F334x8 devices use 4 Bits for the Priority Levels */ |
bogdanm | 86:04dd9b1680ae | 69 | #define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ |
bogdanm | 86:04dd9b1680ae | 70 | #define __FPU_PRESENT 1 /*!< STM32F334x4/STM32F334x6/STM32F334x8 devices provide an FPU */ |
bogdanm | 86:04dd9b1680ae | 71 | |
bogdanm | 86:04dd9b1680ae | 72 | /** |
bogdanm | 86:04dd9b1680ae | 73 | * @} |
bogdanm | 86:04dd9b1680ae | 74 | */ |
bogdanm | 86:04dd9b1680ae | 75 | |
bogdanm | 86:04dd9b1680ae | 76 | /** @addtogroup Peripheral_interrupt_number_definition |
bogdanm | 86:04dd9b1680ae | 77 | * @{ |
bogdanm | 86:04dd9b1680ae | 78 | */ |
bogdanm | 86:04dd9b1680ae | 79 | |
bogdanm | 86:04dd9b1680ae | 80 | /** |
bogdanm | 86:04dd9b1680ae | 81 | * @brief STM32F334x4/STM32F334x6/STM32F334x8 device Interrupt Number Definition, according to the selected device |
bogdanm | 86:04dd9b1680ae | 82 | * in @ref Library_configuration_section |
bogdanm | 86:04dd9b1680ae | 83 | */ |
bogdanm | 86:04dd9b1680ae | 84 | typedef enum |
bogdanm | 86:04dd9b1680ae | 85 | { |
bogdanm | 86:04dd9b1680ae | 86 | /****** Cortex-M4 Processor Exceptions Numbers ****************************************************************/ |
bogdanm | 86:04dd9b1680ae | 87 | NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */ |
bogdanm | 86:04dd9b1680ae | 88 | MemoryManagement_IRQn = -12, /*!< 4 Cortex-M4 Memory Management Interrupt */ |
bogdanm | 86:04dd9b1680ae | 89 | BusFault_IRQn = -11, /*!< 5 Cortex-M4 Bus Fault Interrupt */ |
bogdanm | 86:04dd9b1680ae | 90 | UsageFault_IRQn = -10, /*!< 6 Cortex-M4 Usage Fault Interrupt */ |
bogdanm | 86:04dd9b1680ae | 91 | SVCall_IRQn = -5, /*!< 11 Cortex-M4 SV Call Interrupt */ |
bogdanm | 86:04dd9b1680ae | 92 | DebugMonitor_IRQn = -4, /*!< 12 Cortex-M4 Debug Monitor Interrupt */ |
bogdanm | 86:04dd9b1680ae | 93 | PendSV_IRQn = -2, /*!< 14 Cortex-M4 Pend SV Interrupt */ |
bogdanm | 86:04dd9b1680ae | 94 | SysTick_IRQn = -1, /*!< 15 Cortex-M4 System Tick Interrupt */ |
bogdanm | 86:04dd9b1680ae | 95 | /****** STM32 specific Interrupt Numbers **********************************************************************/ |
bogdanm | 86:04dd9b1680ae | 96 | WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */ |
bogdanm | 86:04dd9b1680ae | 97 | PVD_IRQn = 1, /*!< PVD through EXTI Line detection Interrupt */ |
bogdanm | 86:04dd9b1680ae | 98 | TAMP_STAMP_IRQn = 2, /*!< Tamper and TimeStamp interrupts through the EXTI line 19 */ |
bogdanm | 86:04dd9b1680ae | 99 | RTC_WKUP_IRQn = 3, /*!< RTC Wakeup interrupt through the EXTI line 20 */ |
bogdanm | 86:04dd9b1680ae | 100 | FLASH_IRQn = 4, /*!< FLASH global Interrupt */ |
bogdanm | 86:04dd9b1680ae | 101 | RCC_IRQn = 5, /*!< RCC global Interrupt */ |
bogdanm | 86:04dd9b1680ae | 102 | EXTI0_IRQn = 6, /*!< EXTI Line0 Interrupt */ |
bogdanm | 86:04dd9b1680ae | 103 | EXTI1_IRQn = 7, /*!< EXTI Line1 Interrupt */ |
bogdanm | 86:04dd9b1680ae | 104 | EXTI2_TSC_IRQn = 8, /*!< EXTI Line2 Interrupt and Touch Sense Controller Interrupt */ |
bogdanm | 86:04dd9b1680ae | 105 | EXTI3_IRQn = 9, /*!< EXTI Line3 Interrupt */ |
bogdanm | 86:04dd9b1680ae | 106 | EXTI4_IRQn = 10, /*!< EXTI Line4 Interrupt */ |
bogdanm | 86:04dd9b1680ae | 107 | DMA1_Channel1_IRQn = 11, /*!< DMA1 Channel 1 Interrupt */ |
bogdanm | 86:04dd9b1680ae | 108 | DMA1_Channel2_IRQn = 12, /*!< DMA1 Channel 2 Interrupt */ |
bogdanm | 86:04dd9b1680ae | 109 | DMA1_Channel3_IRQn = 13, /*!< DMA1 Channel 3 Interrupt */ |
bogdanm | 86:04dd9b1680ae | 110 | DMA1_Channel4_IRQn = 14, /*!< DMA1 Channel 4 Interrupt */ |
bogdanm | 86:04dd9b1680ae | 111 | DMA1_Channel5_IRQn = 15, /*!< DMA1 Channel 5 Interrupt */ |
bogdanm | 86:04dd9b1680ae | 112 | DMA1_Channel6_IRQn = 16, /*!< DMA1 Channel 6 Interrupt */ |
bogdanm | 86:04dd9b1680ae | 113 | DMA1_Channel7_IRQn = 17, /*!< DMA1 Channel 7 Interrupt */ |
bogdanm | 86:04dd9b1680ae | 114 | ADC1_2_IRQn = 18, /*!< ADC1 & ADC2 Interrupts */ |
bogdanm | 86:04dd9b1680ae | 115 | CAN_TX_IRQn = 19, /*!< CAN TX Interrupts */ |
bogdanm | 86:04dd9b1680ae | 116 | CAN_RX0_IRQn = 20, /*!< CAN RX0 Interrupts */ |
bogdanm | 86:04dd9b1680ae | 117 | CAN_RX1_IRQn = 21, /*!< CAN RX1 Interrupt */ |
bogdanm | 86:04dd9b1680ae | 118 | CAN_SCE_IRQn = 22, /*!< CAN SCE Interrupt */ |
bogdanm | 86:04dd9b1680ae | 119 | EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */ |
bogdanm | 86:04dd9b1680ae | 120 | TIM1_BRK_TIM15_IRQn = 24, /*!< TIM1 Break and TIM15 Interrupts */ |
bogdanm | 86:04dd9b1680ae | 121 | TIM1_UP_TIM16_IRQn = 25, /*!< TIM1 Update and TIM16 Interrupts */ |
bogdanm | 86:04dd9b1680ae | 122 | TIM1_TRG_COM_TIM17_IRQn = 26, /*!< TIM1 Trigger and Commutation and TIM17 Interrupt */ |
bogdanm | 86:04dd9b1680ae | 123 | TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */ |
bogdanm | 86:04dd9b1680ae | 124 | TIM2_IRQn = 28, /*!< TIM2 global Interrupt */ |
bogdanm | 86:04dd9b1680ae | 125 | TIM3_IRQn = 29, /*!< TIM3 global Interrupt */ |
bogdanm | 86:04dd9b1680ae | 126 | I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt & EXTI Line23 Interrupt (I2C1 wakeup) */ |
bogdanm | 86:04dd9b1680ae | 127 | I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */ |
bogdanm | 86:04dd9b1680ae | 128 | SPI1_IRQn = 35, /*!< SPI1 global Interrupt */ |
bogdanm | 86:04dd9b1680ae | 129 | USART1_IRQn = 37, /*!< USART1 global Interrupt & EXTI Line25 Interrupt (USART1 wakeup) */ |
bogdanm | 86:04dd9b1680ae | 130 | USART2_IRQn = 38, /*!< USART2 global Interrupt & EXTI Line26 Interrupt (USART2 wakeup) */ |
bogdanm | 86:04dd9b1680ae | 131 | USART3_IRQn = 39, /*!< USART3 global Interrupt & EXTI Line28 Interrupt (USART3 wakeup) */ |
bogdanm | 86:04dd9b1680ae | 132 | EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */ |
bogdanm | 86:04dd9b1680ae | 133 | RTC_Alarm_IRQn = 41, /*!< RTC Alarm (A and B) through EXTI Line 17 Interrupt */ |
bogdanm | 86:04dd9b1680ae | 134 | TIM6_DAC1_IRQn = 54, /*!< TIM6 global and DAC1 channel1 & 2 underrun error interrupts */ |
bogdanm | 86:04dd9b1680ae | 135 | TIM7_DAC2_IRQn = 55, /*!< TIM7 global and DAC2 channel1 underrun error Interrupt */ |
bogdanm | 86:04dd9b1680ae | 136 | COMP2_IRQn = 64, /*!< COMP2 global Interrupt via EXT Line22 */ |
bogdanm | 86:04dd9b1680ae | 137 | COMP4_6_IRQn = 65, /*!< COMP4 and COMP6 global Interrupt via EXT Line30 and 32 */ |
bogdanm | 86:04dd9b1680ae | 138 | HRTIM1_Master_IRQn = 67, /*!< HRTIM Master Timer global Interrupts */ |
bogdanm | 86:04dd9b1680ae | 139 | HRTIM1_TIMA_IRQn = 68, /*!< HRTIM Timer A global Interrupt */ |
bogdanm | 86:04dd9b1680ae | 140 | HRTIM1_TIMB_IRQn = 69, /*!< HRTIM Timer B global Interrupt */ |
bogdanm | 86:04dd9b1680ae | 141 | HRTIM1_TIMC_IRQn = 70, /*!< HRTIM Timer C global Interrupt */ |
bogdanm | 86:04dd9b1680ae | 142 | HRTIM1_TIMD_IRQn = 71, /*!< HRTIM Timer D global Interrupt */ |
bogdanm | 86:04dd9b1680ae | 143 | HRTIM1_TIME_IRQn = 72, /*!< HRTIM Timer E global Interrupt */ |
bogdanm | 86:04dd9b1680ae | 144 | HRTIM1_FLT_IRQn = 73, /*!< HRTIM Fault global Interrupt */ |
bogdanm | 86:04dd9b1680ae | 145 | FPU_IRQn = 81 /*!< Floating point Interrupt */ |
bogdanm | 86:04dd9b1680ae | 146 | } IRQn_Type; |
bogdanm | 86:04dd9b1680ae | 147 | |
bogdanm | 86:04dd9b1680ae | 148 | /** |
bogdanm | 86:04dd9b1680ae | 149 | * @} |
bogdanm | 86:04dd9b1680ae | 150 | */ |
bogdanm | 86:04dd9b1680ae | 151 | |
bogdanm | 86:04dd9b1680ae | 152 | #include "core_cm4.h" /* Cortex-M4 processor and core peripherals */ |
bogdanm | 86:04dd9b1680ae | 153 | #include "system_stm32f3xx.h" /* STM32F3xx System Header */ |
bogdanm | 86:04dd9b1680ae | 154 | #include <stdint.h> |
bogdanm | 86:04dd9b1680ae | 155 | |
bogdanm | 86:04dd9b1680ae | 156 | /** @addtogroup Peripheral_registers_structures |
bogdanm | 86:04dd9b1680ae | 157 | * @{ |
bogdanm | 86:04dd9b1680ae | 158 | */ |
bogdanm | 86:04dd9b1680ae | 159 | |
bogdanm | 86:04dd9b1680ae | 160 | /** |
bogdanm | 86:04dd9b1680ae | 161 | * @brief Analog to Digital Converter |
bogdanm | 86:04dd9b1680ae | 162 | */ |
bogdanm | 86:04dd9b1680ae | 163 | |
bogdanm | 86:04dd9b1680ae | 164 | typedef struct |
bogdanm | 86:04dd9b1680ae | 165 | { |
bogdanm | 86:04dd9b1680ae | 166 | __IO uint32_t ISR; /*!< ADC Interrupt and Status Register, Address offset: 0x00 */ |
bogdanm | 86:04dd9b1680ae | 167 | __IO uint32_t IER; /*!< ADC Interrupt Enable Register, Address offset: 0x04 */ |
bogdanm | 86:04dd9b1680ae | 168 | __IO uint32_t CR; /*!< ADC control register, Address offset: 0x08 */ |
bogdanm | 86:04dd9b1680ae | 169 | __IO uint32_t CFGR; /*!< ADC Configuration register, Address offset: 0x0C */ |
bogdanm | 86:04dd9b1680ae | 170 | uint32_t RESERVED0; /*!< Reserved, 0x010 */ |
bogdanm | 86:04dd9b1680ae | 171 | __IO uint32_t SMPR1; /*!< ADC sample time register 1, Address offset: 0x14 */ |
bogdanm | 86:04dd9b1680ae | 172 | __IO uint32_t SMPR2; /*!< ADC sample time register 2, Address offset: 0x18 */ |
bogdanm | 86:04dd9b1680ae | 173 | uint32_t RESERVED1; /*!< Reserved, 0x01C */ |
bogdanm | 86:04dd9b1680ae | 174 | __IO uint32_t TR1; /*!< ADC watchdog threshold register 1, Address offset: 0x20 */ |
bogdanm | 86:04dd9b1680ae | 175 | __IO uint32_t TR2; /*!< ADC watchdog threshold register 2, Address offset: 0x24 */ |
bogdanm | 86:04dd9b1680ae | 176 | __IO uint32_t TR3; /*!< ADC watchdog threshold register 3, Address offset: 0x28 */ |
bogdanm | 86:04dd9b1680ae | 177 | uint32_t RESERVED2; /*!< Reserved, 0x02C */ |
bogdanm | 86:04dd9b1680ae | 178 | __IO uint32_t SQR1; /*!< ADC regular sequence register 1, Address offset: 0x30 */ |
bogdanm | 86:04dd9b1680ae | 179 | __IO uint32_t SQR2; /*!< ADC regular sequence register 2, Address offset: 0x34 */ |
bogdanm | 86:04dd9b1680ae | 180 | __IO uint32_t SQR3; /*!< ADC regular sequence register 3, Address offset: 0x38 */ |
bogdanm | 86:04dd9b1680ae | 181 | __IO uint32_t SQR4; /*!< ADC regular sequence register 4, Address offset: 0x3C */ |
bogdanm | 86:04dd9b1680ae | 182 | __IO uint32_t DR; /*!< ADC regular data register, Address offset: 0x40 */ |
bogdanm | 86:04dd9b1680ae | 183 | uint32_t RESERVED3; /*!< Reserved, 0x044 */ |
bogdanm | 86:04dd9b1680ae | 184 | uint32_t RESERVED4; /*!< Reserved, 0x048 */ |
bogdanm | 86:04dd9b1680ae | 185 | __IO uint32_t JSQR; /*!< ADC injected sequence register, Address offset: 0x4C */ |
bogdanm | 86:04dd9b1680ae | 186 | uint32_t RESERVED5[4]; /*!< Reserved, 0x050 - 0x05C */ |
bogdanm | 86:04dd9b1680ae | 187 | __IO uint32_t OFR1; /*!< ADC offset register 1, Address offset: 0x60 */ |
bogdanm | 86:04dd9b1680ae | 188 | __IO uint32_t OFR2; /*!< ADC offset register 2, Address offset: 0x64 */ |
bogdanm | 86:04dd9b1680ae | 189 | __IO uint32_t OFR3; /*!< ADC offset register 3, Address offset: 0x68 */ |
bogdanm | 86:04dd9b1680ae | 190 | __IO uint32_t OFR4; /*!< ADC offset register 4, Address offset: 0x6C */ |
bogdanm | 86:04dd9b1680ae | 191 | uint32_t RESERVED6[4]; /*!< Reserved, 0x070 - 0x07C */ |
bogdanm | 86:04dd9b1680ae | 192 | __IO uint32_t JDR1; /*!< ADC injected data register 1, Address offset: 0x80 */ |
bogdanm | 86:04dd9b1680ae | 193 | __IO uint32_t JDR2; /*!< ADC injected data register 2, Address offset: 0x84 */ |
bogdanm | 86:04dd9b1680ae | 194 | __IO uint32_t JDR3; /*!< ADC injected data register 3, Address offset: 0x88 */ |
bogdanm | 86:04dd9b1680ae | 195 | __IO uint32_t JDR4; /*!< ADC injected data register 4, Address offset: 0x8C */ |
bogdanm | 86:04dd9b1680ae | 196 | uint32_t RESERVED7[4]; /*!< Reserved, 0x090 - 0x09C */ |
bogdanm | 86:04dd9b1680ae | 197 | __IO uint32_t AWD2CR; /*!< ADC Analog Watchdog 2 Configuration Register, Address offset: 0xA0 */ |
bogdanm | 86:04dd9b1680ae | 198 | __IO uint32_t AWD3CR; /*!< ADC Analog Watchdog 3 Configuration Register, Address offset: 0xA4 */ |
bogdanm | 86:04dd9b1680ae | 199 | uint32_t RESERVED8; /*!< Reserved, 0x0A8 */ |
bogdanm | 86:04dd9b1680ae | 200 | uint32_t RESERVED9; /*!< Reserved, 0x0AC */ |
bogdanm | 86:04dd9b1680ae | 201 | __IO uint32_t DIFSEL; /*!< ADC Differential Mode Selection Register, Address offset: 0xB0 */ |
bogdanm | 86:04dd9b1680ae | 202 | __IO uint32_t CALFACT; /*!< ADC Calibration Factors, Address offset: 0xB4 */ |
bogdanm | 86:04dd9b1680ae | 203 | |
bogdanm | 86:04dd9b1680ae | 204 | } ADC_TypeDef; |
bogdanm | 86:04dd9b1680ae | 205 | |
bogdanm | 86:04dd9b1680ae | 206 | typedef struct |
bogdanm | 86:04dd9b1680ae | 207 | { |
bogdanm | 86:04dd9b1680ae | 208 | __IO uint32_t CSR; /*!< ADC Common status register, Address offset: ADC1/3 base address + 0x300 */ |
bogdanm | 86:04dd9b1680ae | 209 | uint32_t RESERVED; /*!< Reserved, ADC1/3 base address + 0x304 */ |
bogdanm | 86:04dd9b1680ae | 210 | __IO uint32_t CCR; /*!< ADC common control register, Address offset: ADC1/3 base address + 0x308 */ |
bogdanm | 86:04dd9b1680ae | 211 | __IO uint32_t CDR; /*!< ADC common regular data register for dual |
bogdanm | 86:04dd9b1680ae | 212 | AND triple modes, Address offset: ADC1/3 base address + 0x30C */ |
bogdanm | 86:04dd9b1680ae | 213 | } ADC_Common_TypeDef; |
bogdanm | 86:04dd9b1680ae | 214 | |
bogdanm | 86:04dd9b1680ae | 215 | /** |
bogdanm | 86:04dd9b1680ae | 216 | * @brief Controller Area Network TxMailBox |
bogdanm | 86:04dd9b1680ae | 217 | */ |
bogdanm | 86:04dd9b1680ae | 218 | typedef struct |
bogdanm | 86:04dd9b1680ae | 219 | { |
bogdanm | 86:04dd9b1680ae | 220 | __IO uint32_t TIR; /*!< CAN TX mailbox identifier register */ |
bogdanm | 86:04dd9b1680ae | 221 | __IO uint32_t TDTR; /*!< CAN mailbox data length control and time stamp register */ |
bogdanm | 86:04dd9b1680ae | 222 | __IO uint32_t TDLR; /*!< CAN mailbox data low register */ |
bogdanm | 86:04dd9b1680ae | 223 | __IO uint32_t TDHR; /*!< CAN mailbox data high register */ |
bogdanm | 86:04dd9b1680ae | 224 | } CAN_TxMailBox_TypeDef; |
bogdanm | 86:04dd9b1680ae | 225 | |
bogdanm | 86:04dd9b1680ae | 226 | /** |
bogdanm | 86:04dd9b1680ae | 227 | * @brief Controller Area Network FIFOMailBox |
bogdanm | 86:04dd9b1680ae | 228 | */ |
bogdanm | 86:04dd9b1680ae | 229 | typedef struct |
bogdanm | 86:04dd9b1680ae | 230 | { |
bogdanm | 86:04dd9b1680ae | 231 | __IO uint32_t RIR; /*!< CAN receive FIFO mailbox identifier register */ |
bogdanm | 86:04dd9b1680ae | 232 | __IO uint32_t RDTR; /*!< CAN receive FIFO mailbox data length control and time stamp register */ |
bogdanm | 86:04dd9b1680ae | 233 | __IO uint32_t RDLR; /*!< CAN receive FIFO mailbox data low register */ |
bogdanm | 86:04dd9b1680ae | 234 | __IO uint32_t RDHR; /*!< CAN receive FIFO mailbox data high register */ |
bogdanm | 86:04dd9b1680ae | 235 | } CAN_FIFOMailBox_TypeDef; |
bogdanm | 86:04dd9b1680ae | 236 | |
bogdanm | 86:04dd9b1680ae | 237 | /** |
bogdanm | 86:04dd9b1680ae | 238 | * @brief Controller Area Network FilterRegister |
bogdanm | 86:04dd9b1680ae | 239 | */ |
bogdanm | 86:04dd9b1680ae | 240 | typedef struct |
bogdanm | 86:04dd9b1680ae | 241 | { |
bogdanm | 86:04dd9b1680ae | 242 | __IO uint32_t FR1; /*!< CAN Filter bank register 1 */ |
bogdanm | 86:04dd9b1680ae | 243 | __IO uint32_t FR2; /*!< CAN Filter bank register 1 */ |
bogdanm | 86:04dd9b1680ae | 244 | } CAN_FilterRegister_TypeDef; |
bogdanm | 86:04dd9b1680ae | 245 | |
bogdanm | 86:04dd9b1680ae | 246 | /** |
bogdanm | 86:04dd9b1680ae | 247 | * @brief Controller Area Network |
bogdanm | 86:04dd9b1680ae | 248 | */ |
bogdanm | 86:04dd9b1680ae | 249 | typedef struct |
bogdanm | 86:04dd9b1680ae | 250 | { |
bogdanm | 86:04dd9b1680ae | 251 | __IO uint32_t MCR; /*!< CAN master control register, Address offset: 0x00 */ |
bogdanm | 86:04dd9b1680ae | 252 | __IO uint32_t MSR; /*!< CAN master status register, Address offset: 0x04 */ |
bogdanm | 86:04dd9b1680ae | 253 | __IO uint32_t TSR; /*!< CAN transmit status register, Address offset: 0x08 */ |
bogdanm | 86:04dd9b1680ae | 254 | __IO uint32_t RF0R; /*!< CAN receive FIFO 0 register, Address offset: 0x0C */ |
bogdanm | 86:04dd9b1680ae | 255 | __IO uint32_t RF1R; /*!< CAN receive FIFO 1 register, Address offset: 0x10 */ |
bogdanm | 86:04dd9b1680ae | 256 | __IO uint32_t IER; /*!< CAN interrupt enable register, Address offset: 0x14 */ |
bogdanm | 86:04dd9b1680ae | 257 | __IO uint32_t ESR; /*!< CAN error status register, Address offset: 0x18 */ |
bogdanm | 86:04dd9b1680ae | 258 | __IO uint32_t BTR; /*!< CAN bit timing register, Address offset: 0x1C */ |
bogdanm | 86:04dd9b1680ae | 259 | uint32_t RESERVED0[88]; /*!< Reserved, 0x020 - 0x17F */ |
bogdanm | 86:04dd9b1680ae | 260 | CAN_TxMailBox_TypeDef sTxMailBox[3]; /*!< CAN Tx MailBox, Address offset: 0x180 - 0x1AC */ |
bogdanm | 86:04dd9b1680ae | 261 | CAN_FIFOMailBox_TypeDef sFIFOMailBox[2]; /*!< CAN FIFO MailBox, Address offset: 0x1B0 - 0x1CC */ |
bogdanm | 86:04dd9b1680ae | 262 | uint32_t RESERVED1[12]; /*!< Reserved, 0x1D0 - 0x1FF */ |
bogdanm | 86:04dd9b1680ae | 263 | __IO uint32_t FMR; /*!< CAN filter master register, Address offset: 0x200 */ |
bogdanm | 86:04dd9b1680ae | 264 | __IO uint32_t FM1R; /*!< CAN filter mode register, Address offset: 0x204 */ |
bogdanm | 86:04dd9b1680ae | 265 | uint32_t RESERVED2; /*!< Reserved, 0x208 */ |
bogdanm | 86:04dd9b1680ae | 266 | __IO uint32_t FS1R; /*!< CAN filter scale register, Address offset: 0x20C */ |
bogdanm | 86:04dd9b1680ae | 267 | uint32_t RESERVED3; /*!< Reserved, 0x210 */ |
bogdanm | 86:04dd9b1680ae | 268 | __IO uint32_t FFA1R; /*!< CAN filter FIFO assignment register, Address offset: 0x214 */ |
bogdanm | 86:04dd9b1680ae | 269 | uint32_t RESERVED4; /*!< Reserved, 0x218 */ |
bogdanm | 86:04dd9b1680ae | 270 | __IO uint32_t FA1R; /*!< CAN filter activation register, Address offset: 0x21C */ |
bogdanm | 86:04dd9b1680ae | 271 | uint32_t RESERVED5[8]; /*!< Reserved, 0x220-0x23F */ |
bogdanm | 86:04dd9b1680ae | 272 | CAN_FilterRegister_TypeDef sFilterRegister[28]; /*!< CAN Filter Register, Address offset: 0x240-0x31C */ |
bogdanm | 86:04dd9b1680ae | 273 | } CAN_TypeDef; |
bogdanm | 86:04dd9b1680ae | 274 | |
bogdanm | 86:04dd9b1680ae | 275 | /** |
bogdanm | 86:04dd9b1680ae | 276 | * @brief Analog Comparators |
bogdanm | 86:04dd9b1680ae | 277 | */ |
bogdanm | 86:04dd9b1680ae | 278 | |
bogdanm | 86:04dd9b1680ae | 279 | typedef struct |
bogdanm | 86:04dd9b1680ae | 280 | { |
bogdanm | 86:04dd9b1680ae | 281 | __IO uint32_t CSR; /*!< Comparator control Status register, Address offset: 0x00 */ |
bogdanm | 86:04dd9b1680ae | 282 | } COMP_TypeDef; |
bogdanm | 86:04dd9b1680ae | 283 | |
bogdanm | 86:04dd9b1680ae | 284 | /** |
bogdanm | 86:04dd9b1680ae | 285 | * @brief CRC calculation unit |
bogdanm | 86:04dd9b1680ae | 286 | */ |
bogdanm | 86:04dd9b1680ae | 287 | |
bogdanm | 86:04dd9b1680ae | 288 | typedef struct |
bogdanm | 86:04dd9b1680ae | 289 | { |
bogdanm | 86:04dd9b1680ae | 290 | __IO uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */ |
bogdanm | 86:04dd9b1680ae | 291 | __IO uint8_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */ |
bogdanm | 86:04dd9b1680ae | 292 | uint8_t RESERVED0; /*!< Reserved, 0x05 */ |
bogdanm | 86:04dd9b1680ae | 293 | uint16_t RESERVED1; /*!< Reserved, 0x06 */ |
bogdanm | 86:04dd9b1680ae | 294 | __IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */ |
bogdanm | 86:04dd9b1680ae | 295 | uint32_t RESERVED2; /*!< Reserved, 0x0C */ |
bogdanm | 86:04dd9b1680ae | 296 | __IO uint32_t INIT; /*!< Initial CRC value register, Address offset: 0x10 */ |
bogdanm | 86:04dd9b1680ae | 297 | __IO uint32_t POL; /*!< CRC polynomial register, Address offset: 0x14 */ |
bogdanm | 86:04dd9b1680ae | 298 | } CRC_TypeDef; |
bogdanm | 86:04dd9b1680ae | 299 | |
bogdanm | 86:04dd9b1680ae | 300 | /** |
bogdanm | 86:04dd9b1680ae | 301 | * @brief Digital to Analog Converter |
bogdanm | 86:04dd9b1680ae | 302 | */ |
bogdanm | 86:04dd9b1680ae | 303 | |
bogdanm | 86:04dd9b1680ae | 304 | typedef struct |
bogdanm | 86:04dd9b1680ae | 305 | { |
bogdanm | 86:04dd9b1680ae | 306 | __IO uint32_t CR; /*!< DAC control register, Address offset: 0x00 */ |
bogdanm | 86:04dd9b1680ae | 307 | __IO uint32_t SWTRIGR; /*!< DAC software trigger register, Address offset: 0x04 */ |
bogdanm | 86:04dd9b1680ae | 308 | __IO uint32_t DHR12R1; /*!< DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08 */ |
bogdanm | 86:04dd9b1680ae | 309 | __IO uint32_t DHR12L1; /*!< DAC channel1 12-bit left aligned data holding register, Address offset: 0x0C */ |
bogdanm | 86:04dd9b1680ae | 310 | __IO uint32_t DHR8R1; /*!< DAC channel1 8-bit right aligned data holding register, Address offset: 0x10 */ |
bogdanm | 86:04dd9b1680ae | 311 | __IO uint32_t DHR12R2; /*!< DAC channel2 12-bit right aligned data holding register, Address offset: 0x14 */ |
bogdanm | 86:04dd9b1680ae | 312 | __IO uint32_t DHR12L2; /*!< DAC channel2 12-bit left aligned data holding register, Address offset: 0x18 */ |
bogdanm | 86:04dd9b1680ae | 313 | __IO uint32_t DHR8R2; /*!< DAC channel2 8-bit right-aligned data holding register, Address offset: 0x1C */ |
bogdanm | 86:04dd9b1680ae | 314 | __IO uint32_t DHR12RD; /*!< Dual DAC 12-bit right-aligned data holding register, Address offset: 0x20 */ |
bogdanm | 86:04dd9b1680ae | 315 | __IO uint32_t DHR12LD; /*!< DUAL DAC 12-bit left aligned data holding register, Address offset: 0x24 */ |
bogdanm | 86:04dd9b1680ae | 316 | __IO uint32_t DHR8RD; /*!< DUAL DAC 8-bit right aligned data holding register, Address offset: 0x28 */ |
bogdanm | 86:04dd9b1680ae | 317 | __IO uint32_t DOR1; /*!< DAC channel1 data output register, Address offset: 0x2C */ |
bogdanm | 86:04dd9b1680ae | 318 | __IO uint32_t DOR2; /*!< DAC channel2 data output register, Address offset: 0x30 */ |
bogdanm | 86:04dd9b1680ae | 319 | __IO uint32_t SR; /*!< DAC status register, Address offset: 0x34 */ |
bogdanm | 86:04dd9b1680ae | 320 | } DAC_TypeDef; |
bogdanm | 86:04dd9b1680ae | 321 | |
bogdanm | 86:04dd9b1680ae | 322 | /** |
bogdanm | 86:04dd9b1680ae | 323 | * @brief Debug MCU |
bogdanm | 86:04dd9b1680ae | 324 | */ |
bogdanm | 86:04dd9b1680ae | 325 | |
bogdanm | 86:04dd9b1680ae | 326 | typedef struct |
bogdanm | 86:04dd9b1680ae | 327 | { |
bogdanm | 86:04dd9b1680ae | 328 | __IO uint32_t IDCODE; /*!< MCU device ID code, Address offset: 0x00 */ |
bogdanm | 86:04dd9b1680ae | 329 | __IO uint32_t CR; /*!< Debug MCU configuration register, Address offset: 0x04 */ |
bogdanm | 86:04dd9b1680ae | 330 | __IO uint32_t APB1FZ; /*!< Debug MCU APB1 freeze register, Address offset: 0x08 */ |
bogdanm | 86:04dd9b1680ae | 331 | __IO uint32_t APB2FZ; /*!< Debug MCU APB2 freeze register, Address offset: 0x0C */ |
bogdanm | 86:04dd9b1680ae | 332 | }DBGMCU_TypeDef; |
bogdanm | 86:04dd9b1680ae | 333 | |
bogdanm | 86:04dd9b1680ae | 334 | /** |
bogdanm | 86:04dd9b1680ae | 335 | * @brief DMA Controller |
bogdanm | 86:04dd9b1680ae | 336 | */ |
bogdanm | 86:04dd9b1680ae | 337 | |
bogdanm | 86:04dd9b1680ae | 338 | typedef struct |
bogdanm | 86:04dd9b1680ae | 339 | { |
bogdanm | 86:04dd9b1680ae | 340 | __IO uint32_t CCR; /*!< DMA channel x configuration register */ |
bogdanm | 86:04dd9b1680ae | 341 | __IO uint32_t CNDTR; /*!< DMA channel x number of data register */ |
bogdanm | 86:04dd9b1680ae | 342 | __IO uint32_t CPAR; /*!< DMA channel x peripheral address register */ |
bogdanm | 86:04dd9b1680ae | 343 | __IO uint32_t CMAR; /*!< DMA channel x memory address register */ |
bogdanm | 86:04dd9b1680ae | 344 | } DMA_Channel_TypeDef; |
bogdanm | 86:04dd9b1680ae | 345 | |
bogdanm | 86:04dd9b1680ae | 346 | typedef struct |
bogdanm | 86:04dd9b1680ae | 347 | { |
bogdanm | 86:04dd9b1680ae | 348 | __IO uint32_t ISR; /*!< DMA interrupt status register, Address offset: 0x00 */ |
bogdanm | 86:04dd9b1680ae | 349 | __IO uint32_t IFCR; /*!< DMA interrupt clear flag register, Address offset: 0x04 */ |
bogdanm | 86:04dd9b1680ae | 350 | } DMA_TypeDef; |
bogdanm | 86:04dd9b1680ae | 351 | |
bogdanm | 86:04dd9b1680ae | 352 | /** |
bogdanm | 86:04dd9b1680ae | 353 | * @brief External Interrupt/Event Controller |
bogdanm | 86:04dd9b1680ae | 354 | */ |
bogdanm | 86:04dd9b1680ae | 355 | |
bogdanm | 86:04dd9b1680ae | 356 | typedef struct |
bogdanm | 86:04dd9b1680ae | 357 | { |
bogdanm | 86:04dd9b1680ae | 358 | __IO uint32_t IMR; /*!< EXTI Interrupt mask register, Address offset: 0x00 */ |
bogdanm | 86:04dd9b1680ae | 359 | __IO uint32_t EMR; /*!< EXTI Event mask register, Address offset: 0x04 */ |
bogdanm | 86:04dd9b1680ae | 360 | __IO uint32_t RTSR; /*!< EXTI Rising trigger selection register, Address offset: 0x08 */ |
bogdanm | 86:04dd9b1680ae | 361 | __IO uint32_t FTSR; /*!< EXTI Falling trigger selection register, Address offset: 0x0C */ |
bogdanm | 86:04dd9b1680ae | 362 | __IO uint32_t SWIER; /*!< EXTI Software interrupt event register, Address offset: 0x10 */ |
bogdanm | 86:04dd9b1680ae | 363 | __IO uint32_t PR; /*!< EXTI Pending register, Address offset: 0x14 */ |
bogdanm | 86:04dd9b1680ae | 364 | uint32_t RESERVED1; /*!< Reserved, 0x18 */ |
bogdanm | 86:04dd9b1680ae | 365 | uint32_t RESERVED2; /*!< Reserved, 0x1C */ |
bogdanm | 86:04dd9b1680ae | 366 | __IO uint32_t IMR2; /*!< EXTI Interrupt mask register, Address offset: 0x20 */ |
bogdanm | 86:04dd9b1680ae | 367 | __IO uint32_t EMR2; /*!< EXTI Event mask register, Address offset: 0x24 */ |
bogdanm | 86:04dd9b1680ae | 368 | __IO uint32_t RTSR2; /*!< EXTI Rising trigger selection register, Address offset: 0x28 */ |
bogdanm | 86:04dd9b1680ae | 369 | __IO uint32_t FTSR2; /*!< EXTI Falling trigger selection register, Address offset: 0x2C */ |
bogdanm | 86:04dd9b1680ae | 370 | __IO uint32_t SWIER2; /*!< EXTI Software interrupt event register, Address offset: 0x30 */ |
bogdanm | 86:04dd9b1680ae | 371 | __IO uint32_t PR2; /*!< EXTI Pending register, Address offset: 0x34 */ |
bogdanm | 86:04dd9b1680ae | 372 | }EXTI_TypeDef; |
bogdanm | 86:04dd9b1680ae | 373 | |
bogdanm | 86:04dd9b1680ae | 374 | /** |
bogdanm | 86:04dd9b1680ae | 375 | * @brief FLASH Registers |
bogdanm | 86:04dd9b1680ae | 376 | */ |
bogdanm | 86:04dd9b1680ae | 377 | |
bogdanm | 86:04dd9b1680ae | 378 | typedef struct |
bogdanm | 86:04dd9b1680ae | 379 | { |
bogdanm | 86:04dd9b1680ae | 380 | __IO uint32_t ACR; /*!< FLASH access control register, Address offset: 0x00 */ |
bogdanm | 86:04dd9b1680ae | 381 | __IO uint32_t KEYR; /*!< FLASH key register, Address offset: 0x04 */ |
bogdanm | 86:04dd9b1680ae | 382 | __IO uint32_t OPTKEYR; /*!< FLASH option key register, Address offset: 0x08 */ |
bogdanm | 86:04dd9b1680ae | 383 | __IO uint32_t SR; /*!< FLASH status register, Address offset: 0x0C */ |
bogdanm | 86:04dd9b1680ae | 384 | __IO uint32_t CR; /*!< FLASH control register, Address offset: 0x10 */ |
bogdanm | 86:04dd9b1680ae | 385 | __IO uint32_t AR; /*!< FLASH address register, Address offset: 0x14 */ |
bogdanm | 86:04dd9b1680ae | 386 | uint32_t RESERVED; /*!< Reserved, 0x18 */ |
bogdanm | 86:04dd9b1680ae | 387 | __IO uint32_t OBR; /*!< FLASH Option byte register, Address offset: 0x1C */ |
bogdanm | 86:04dd9b1680ae | 388 | __IO uint32_t WRPR; /*!< FLASH Write register, Address offset: 0x20 */ |
bogdanm | 86:04dd9b1680ae | 389 | |
bogdanm | 86:04dd9b1680ae | 390 | } FLASH_TypeDef; |
bogdanm | 86:04dd9b1680ae | 391 | |
bogdanm | 86:04dd9b1680ae | 392 | /** |
bogdanm | 86:04dd9b1680ae | 393 | * @brief Option Bytes Registers |
bogdanm | 86:04dd9b1680ae | 394 | */ |
bogdanm | 86:04dd9b1680ae | 395 | typedef struct |
bogdanm | 86:04dd9b1680ae | 396 | { |
bogdanm | 86:04dd9b1680ae | 397 | __IO uint16_t RDP; /*!<FLASH option byte Read protection, Address offset: 0x00 */ |
bogdanm | 86:04dd9b1680ae | 398 | __IO uint16_t USER; /*!<FLASH option byte user options, Address offset: 0x02 */ |
bogdanm | 86:04dd9b1680ae | 399 | uint16_t RESERVED0; /*!< Reserved, 0x04 */ |
bogdanm | 86:04dd9b1680ae | 400 | uint16_t RESERVED1; /*!< Reserved, 0x06 */ |
bogdanm | 86:04dd9b1680ae | 401 | __IO uint16_t WRP0; /*!<FLASH option byte write protection 0, Address offset: 0x08 */ |
bogdanm | 86:04dd9b1680ae | 402 | __IO uint16_t WRP1; /*!<FLASH option byte write protection 1, Address offset: 0x0C */ |
bogdanm | 86:04dd9b1680ae | 403 | __IO uint16_t WRP2; /*!<FLASH option byte write protection 2, Address offset: 0x10 */ |
bogdanm | 86:04dd9b1680ae | 404 | __IO uint16_t WRP3; /*!<FLASH option byte write protection 3, Address offset: 0x12 */ |
bogdanm | 86:04dd9b1680ae | 405 | } OB_TypeDef; |
bogdanm | 86:04dd9b1680ae | 406 | |
bogdanm | 86:04dd9b1680ae | 407 | /** |
bogdanm | 86:04dd9b1680ae | 408 | * @brief General Purpose I/O |
bogdanm | 86:04dd9b1680ae | 409 | */ |
bogdanm | 86:04dd9b1680ae | 410 | |
bogdanm | 86:04dd9b1680ae | 411 | typedef struct |
bogdanm | 86:04dd9b1680ae | 412 | { |
bogdanm | 86:04dd9b1680ae | 413 | __IO uint32_t MODER; /*!< GPIO port mode register, Address offset: 0x00 */ |
bogdanm | 86:04dd9b1680ae | 414 | __IO uint32_t OTYPER; /*!< GPIO port output type register, Address offset: 0x04 */ |
bogdanm | 86:04dd9b1680ae | 415 | __IO uint32_t OSPEEDR; /*!< GPIO port output speed register, Address offset: 0x08 */ |
bogdanm | 86:04dd9b1680ae | 416 | __IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x0C */ |
bogdanm | 86:04dd9b1680ae | 417 | __IO uint32_t IDR; /*!< GPIO port input data register, Address offset: 0x10 */ |
bogdanm | 86:04dd9b1680ae | 418 | __IO uint32_t ODR; /*!< GPIO port output data register, Address offset: 0x14 */ |
bogdanm | 86:04dd9b1680ae | 419 | __IO uint16_t BSRRL; /*!< GPIO port bit set/reset low register, Address offset: 0x18 */ |
bogdanm | 86:04dd9b1680ae | 420 | __IO uint16_t BSRRH; /*!< GPIO port bit set/reset high register, Address offset: 0x1A */ |
bogdanm | 86:04dd9b1680ae | 421 | __IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x1C */ |
bogdanm | 86:04dd9b1680ae | 422 | __IO uint32_t AFR[2]; /*!< GPIO alternate function registers, Address offset: 0x20-0x24 */ |
bogdanm | 86:04dd9b1680ae | 423 | __IO uint32_t BRR; /*!< GPIO bit reset register, Address offset: 0x28 */ |
bogdanm | 86:04dd9b1680ae | 424 | }GPIO_TypeDef; |
bogdanm | 86:04dd9b1680ae | 425 | |
bogdanm | 86:04dd9b1680ae | 426 | /** |
bogdanm | 86:04dd9b1680ae | 427 | * @brief Operational Amplifier (OPAMP) |
bogdanm | 86:04dd9b1680ae | 428 | */ |
bogdanm | 86:04dd9b1680ae | 429 | |
bogdanm | 86:04dd9b1680ae | 430 | typedef struct |
bogdanm | 86:04dd9b1680ae | 431 | { |
bogdanm | 86:04dd9b1680ae | 432 | __IO uint32_t CSR; /*!< OPAMP control and status register, Address offset: 0x00 */ |
bogdanm | 86:04dd9b1680ae | 433 | } OPAMP_TypeDef; |
bogdanm | 86:04dd9b1680ae | 434 | |
bogdanm | 86:04dd9b1680ae | 435 | /** |
bogdanm | 86:04dd9b1680ae | 436 | * @brief High resolution Timer (HRTIM) |
bogdanm | 86:04dd9b1680ae | 437 | */ |
bogdanm | 86:04dd9b1680ae | 438 | /* HRTIM master registers definition */ |
bogdanm | 86:04dd9b1680ae | 439 | typedef struct |
bogdanm | 86:04dd9b1680ae | 440 | { |
bogdanm | 86:04dd9b1680ae | 441 | __IO uint32_t MCR; /*!< HRTIM Master Timer control register, Address offset: 0x00 */ |
bogdanm | 86:04dd9b1680ae | 442 | __IO uint32_t MISR; /*!< HRTIM Master Timer interrupt status register, Address offset: 0x04 */ |
bogdanm | 86:04dd9b1680ae | 443 | __IO uint32_t MICR; /*!< HRTIM Master Timer interupt clear register, Address offset: 0x08 */ |
bogdanm | 86:04dd9b1680ae | 444 | __IO uint32_t MDIER; /*!< HRTIM Master Timer DMA/interrupt enable register Address offset: 0x0C */ |
bogdanm | 86:04dd9b1680ae | 445 | __IO uint32_t MCNTR; /*!< HRTIM Master Timer counter register, Address offset: 0x10 */ |
bogdanm | 86:04dd9b1680ae | 446 | __IO uint32_t MPER; /*!< HRTIM Master Timer period register, Address offset: 0x14 */ |
bogdanm | 86:04dd9b1680ae | 447 | __IO uint32_t MREP; /*!< HRTIM Master Timer repetition register, Address offset: 0x18 */ |
bogdanm | 86:04dd9b1680ae | 448 | __IO uint32_t MCMP1R; /*!< HRTIM Master Timer compare 1 register, Address offset: 0x1C */ |
bogdanm | 86:04dd9b1680ae | 449 | uint32_t RESERVED0; /*!< Reserved, 0x20 */ |
bogdanm | 86:04dd9b1680ae | 450 | __IO uint32_t MCMP2R; /*!< HRTIM Master Timer compare 2 register, Address offset: 0x24 */ |
bogdanm | 86:04dd9b1680ae | 451 | __IO uint32_t MCMP3R; /*!< HRTIM Master Timer compare 3 register, Address offset: 0x28 */ |
bogdanm | 86:04dd9b1680ae | 452 | __IO uint32_t MCMP4R; /*!< HRTIM Master Timer compare 4 register, Address offset: 0x2C */ |
bogdanm | 86:04dd9b1680ae | 453 | uint32_t RESERVED1[20]; /*!< Reserved, 0x30..0x7C */ |
bogdanm | 86:04dd9b1680ae | 454 | }HRTIM_Master_TypeDef; |
bogdanm | 86:04dd9b1680ae | 455 | |
bogdanm | 86:04dd9b1680ae | 456 | /* HRTIM Timer A to E registers definition */ |
bogdanm | 86:04dd9b1680ae | 457 | typedef struct |
bogdanm | 86:04dd9b1680ae | 458 | { |
bogdanm | 86:04dd9b1680ae | 459 | __IO uint32_t TIMxCR; /*!< HRTIM Timerx control register, Address offset: 0x00 */ |
bogdanm | 86:04dd9b1680ae | 460 | __IO uint32_t TIMxISR; /*!< HRTIM Timerx interrupt status register, Address offset: 0x04 */ |
bogdanm | 86:04dd9b1680ae | 461 | __IO uint32_t TIMxICR; /*!< HRTIM Timerx interrupt clear register, Address offset: 0x08 */ |
bogdanm | 86:04dd9b1680ae | 462 | __IO uint32_t TIMxDIER; /*!< HRTIM Timerx DMA/interrupt enable register, Address offset: 0x0C */ |
bogdanm | 86:04dd9b1680ae | 463 | __IO uint32_t CNTxR; /*!< HRTIM Timerx counter register, Address offset: 0x10 */ |
bogdanm | 86:04dd9b1680ae | 464 | __IO uint32_t PERxR; /*!< HRTIM Timerx period register, Address offset: 0x14 */ |
bogdanm | 86:04dd9b1680ae | 465 | __IO uint32_t REPxR; /*!< HRTIM Timerx repetition register, Address offset: 0x18 */ |
bogdanm | 86:04dd9b1680ae | 466 | __IO uint32_t CMP1xR; /*!< HRTIM Timerx compare 1 register, Address offset: 0x1C */ |
bogdanm | 86:04dd9b1680ae | 467 | __IO uint32_t CMP1CxR; /*!< HRTIM Timerx compare 1 compound register, Address offset: 0x20 */ |
bogdanm | 86:04dd9b1680ae | 468 | __IO uint32_t CMP2xR; /*!< HRTIM Timerx compare 2 register, Address offset: 0x24 */ |
bogdanm | 86:04dd9b1680ae | 469 | __IO uint32_t CMP3xR; /*!< HRTIM Timerx compare 3 register, Address offset: 0x28 */ |
bogdanm | 86:04dd9b1680ae | 470 | __IO uint32_t CMP4xR; /*!< HRTIM Timerx compare 4 register, Address offset: 0x2C */ |
bogdanm | 86:04dd9b1680ae | 471 | __IO uint32_t CPT1xR; /*!< HRTIM Timerx capture 1 register, Address offset: 0x30 */ |
bogdanm | 86:04dd9b1680ae | 472 | __IO uint32_t CPT2xR; /*!< HRTIM Timerx capture 2 register, Address offset: 0x34 */ |
bogdanm | 86:04dd9b1680ae | 473 | __IO uint32_t DTxR; /*!< HRTIM Timerx dead time register, Address offset: 0x38 */ |
bogdanm | 86:04dd9b1680ae | 474 | __IO uint32_t SETx1R; /*!< HRTIM Timerx output 1 set register, Address offset: 0x3C */ |
bogdanm | 86:04dd9b1680ae | 475 | __IO uint32_t RSTx1R; /*!< HRTIM Timerx output 1 reset register, Address offset: 0x40 */ |
bogdanm | 86:04dd9b1680ae | 476 | __IO uint32_t SETx2R; /*!< HRTIM Timerx output 2 set register, Address offset: 0x44 */ |
bogdanm | 86:04dd9b1680ae | 477 | __IO uint32_t RSTx2R; /*!< HRTIM Timerx output 2 reset register, Address offset: 0x48 */ |
bogdanm | 86:04dd9b1680ae | 478 | __IO uint32_t EEFxR1; /*!< HRTIM Timerx external event filtering 1 register, Address offset: 0x4C */ |
bogdanm | 86:04dd9b1680ae | 479 | __IO uint32_t EEFxR2; /*!< HRTIM Timerx external event filtering 2 register, Address offset: 0x50 */ |
bogdanm | 86:04dd9b1680ae | 480 | __IO uint32_t RSTxR; /*!< HRTIM Timerx Reset register, Address offset: 0x54 */ |
bogdanm | 86:04dd9b1680ae | 481 | __IO uint32_t CHPxR; /*!< HRTIM Timerx Chopper register, Address offset: 0x58 */ |
bogdanm | 86:04dd9b1680ae | 482 | __IO uint32_t CPT1xCR; /*!< HRTIM Timerx Capture 1 register, Address offset: 0x5C */ |
bogdanm | 86:04dd9b1680ae | 483 | __IO uint32_t CPT2xCR; /*!< HRTIM Timerx Capture 2 register, Address offset: 0x60 */ |
bogdanm | 86:04dd9b1680ae | 484 | __IO uint32_t OUTxR; /*!< HRTIM Timerx Output register, Address offset: 0x64 */ |
bogdanm | 86:04dd9b1680ae | 485 | __IO uint32_t FLTxR; /*!< HRTIM Timerx Fault register, Address offset: 0x68 */ |
bogdanm | 86:04dd9b1680ae | 486 | uint32_t RESERVED0[5]; /*!< Reserved, 0x6C..0x7C */ |
bogdanm | 86:04dd9b1680ae | 487 | }HRTIM_Timerx_TypeDef; |
bogdanm | 86:04dd9b1680ae | 488 | |
bogdanm | 86:04dd9b1680ae | 489 | /* HRTIM common register definition */ |
bogdanm | 86:04dd9b1680ae | 490 | typedef struct |
bogdanm | 86:04dd9b1680ae | 491 | { |
bogdanm | 86:04dd9b1680ae | 492 | __IO uint32_t CR1; /*!< HRTIM control register1, Address offset: 0x00 */ |
bogdanm | 86:04dd9b1680ae | 493 | __IO uint32_t CR2; /*!< HRTIM control register2, Address offset: 0x04 */ |
bogdanm | 86:04dd9b1680ae | 494 | __IO uint32_t ISR; /*!< HRTIM interrupt status register, Address offset: 0x08 */ |
bogdanm | 86:04dd9b1680ae | 495 | __IO uint32_t ICR; /*!< HRTIM interrupt clear register, Address offset: 0x0C */ |
bogdanm | 86:04dd9b1680ae | 496 | __IO uint32_t IER; /*!< HRTIM interrupt enable register, Address offset: 0x10 */ |
bogdanm | 86:04dd9b1680ae | 497 | __IO uint32_t OENR; /*!< HRTIM Output enable register, Address offset: 0x14 */ |
bogdanm | 86:04dd9b1680ae | 498 | __IO uint32_t ODISR; /*!< HRTIM Output disable register, Address offset: 0x18 */ |
bogdanm | 86:04dd9b1680ae | 499 | __IO uint32_t ODSR; /*!< HRTIM Output disable status register, Address offset: 0x1C */ |
bogdanm | 86:04dd9b1680ae | 500 | __IO uint32_t BMCR; /*!< HRTIM Burst mode control register, Address offset: 0x20 */ |
bogdanm | 86:04dd9b1680ae | 501 | __IO uint32_t BMTRGR; /*!< HRTIM Busrt mode trigger register, Address offset: 0x24 */ |
bogdanm | 86:04dd9b1680ae | 502 | __IO uint32_t BMCMPR; /*!< HRTIM Burst mode compare register, Address offset: 0x28 */ |
bogdanm | 86:04dd9b1680ae | 503 | __IO uint32_t BMPER; /*!< HRTIM Burst mode period register, Address offset: 0x2C */ |
bogdanm | 86:04dd9b1680ae | 504 | __IO uint32_t EECR1; /*!< HRTIM Timer external event control register1, Address offset: 0x30 */ |
bogdanm | 86:04dd9b1680ae | 505 | __IO uint32_t EECR2; /*!< HRTIM Timer external event control register2, Address offset: 0x34 */ |
bogdanm | 86:04dd9b1680ae | 506 | __IO uint32_t EECR3; /*!< HRTIM Timer external event control register3, Address offset: 0x38 */ |
bogdanm | 86:04dd9b1680ae | 507 | __IO uint32_t ADC1R; /*!< HRTIM ADC Trigger 1 register, Address offset: 0x3C */ |
bogdanm | 86:04dd9b1680ae | 508 | __IO uint32_t ADC2R; /*!< HRTIM ADC Trigger 2 register, Address offset: 0x40 */ |
bogdanm | 86:04dd9b1680ae | 509 | __IO uint32_t ADC3R; /*!< HRTIM ADC Trigger 3 register, Address offset: 0x44 */ |
bogdanm | 86:04dd9b1680ae | 510 | __IO uint32_t ADC4R; /*!< HRTIM ADC Trigger 4 register, Address offset: 0x48 */ |
bogdanm | 86:04dd9b1680ae | 511 | __IO uint32_t DLLCR; /*!< HRTIM DLL control register, Address offset: 0x4C */ |
bogdanm | 86:04dd9b1680ae | 512 | __IO uint32_t FLTINR1; /*!< HRTIM Fault input register1, Address offset: 0x50 */ |
bogdanm | 86:04dd9b1680ae | 513 | __IO uint32_t FLTINR2; /*!< HRTIM Fault input register2, Address offset: 0x54 */ |
bogdanm | 86:04dd9b1680ae | 514 | __IO uint32_t BDMUPR; /*!< HRTIM Burst DMA Master Timer update register, Address offset: 0x58 */ |
bogdanm | 86:04dd9b1680ae | 515 | __IO uint32_t BDTAUPR; /*!< HRTIM Burst DMA Timerx update register, Address offset: 0x5C */ |
bogdanm | 86:04dd9b1680ae | 516 | __IO uint32_t BDTBUPR; /*!< HRTIM Burst DMA Timerx update register, Address offset: 0x60 */ |
bogdanm | 86:04dd9b1680ae | 517 | __IO uint32_t BDTCUPR; /*!< HRTIM Burst DMA Timerx update register, Address offset: 0x64 */ |
bogdanm | 86:04dd9b1680ae | 518 | __IO uint32_t BDTDUPR; /*!< HRTIM Burst DMA Timerx update register, Address offset: 0x68 */ |
bogdanm | 86:04dd9b1680ae | 519 | __IO uint32_t BDTEUPR; /*!< HRTIM Burst DMA Timerx update register, Address offset: 0x6C */ |
bogdanm | 86:04dd9b1680ae | 520 | __IO uint32_t BDMADR; /*!< HRTIM Burst DMA Master Data register, Address offset: 0x70 */ |
bogdanm | 86:04dd9b1680ae | 521 | }HRTIM_Common_TypeDef; |
bogdanm | 86:04dd9b1680ae | 522 | |
bogdanm | 86:04dd9b1680ae | 523 | /* HRTIM register definition */ |
bogdanm | 86:04dd9b1680ae | 524 | typedef struct { |
bogdanm | 86:04dd9b1680ae | 525 | HRTIM_Master_TypeDef sMasterRegs; |
bogdanm | 86:04dd9b1680ae | 526 | HRTIM_Timerx_TypeDef sTimerxRegs[5]; |
bogdanm | 86:04dd9b1680ae | 527 | uint32_t RESERVED0[32]; |
bogdanm | 86:04dd9b1680ae | 528 | HRTIM_Common_TypeDef sCommonRegs; |
bogdanm | 86:04dd9b1680ae | 529 | }HRTIM_TypeDef; |
bogdanm | 86:04dd9b1680ae | 530 | |
bogdanm | 86:04dd9b1680ae | 531 | /** |
bogdanm | 86:04dd9b1680ae | 532 | * @brief System configuration controller |
bogdanm | 86:04dd9b1680ae | 533 | */ |
bogdanm | 86:04dd9b1680ae | 534 | |
bogdanm | 86:04dd9b1680ae | 535 | typedef struct |
bogdanm | 86:04dd9b1680ae | 536 | { |
bogdanm | 86:04dd9b1680ae | 537 | __IO uint32_t CFGR1; /*!< SYSCFG configuration register 1, Address offset: 0x00 */ |
bogdanm | 86:04dd9b1680ae | 538 | __IO uint32_t RCR; /*!< SYSCFG CCM SRAM protection register, Address offset: 0x04 */ |
bogdanm | 86:04dd9b1680ae | 539 | __IO uint32_t EXTICR[4]; /*!< SYSCFG external interrupt configuration registers, Address offset: 0x14-0x08 */ |
bogdanm | 86:04dd9b1680ae | 540 | __IO uint32_t CFGR2; /*!< SYSCFG configuration register 2, Address offset: 0x18 */ |
bogdanm | 86:04dd9b1680ae | 541 | __IO uint32_t RESERVED0; /*!< Reserved, 0x1C */ |
bogdanm | 86:04dd9b1680ae | 542 | __IO uint32_t RESERVED1; /*!< Reserved, 0x20 */ |
bogdanm | 86:04dd9b1680ae | 543 | __IO uint32_t RESERVED2; /*!< Reserved, 0x24 */ |
bogdanm | 86:04dd9b1680ae | 544 | __IO uint32_t RESERVED4; /*!< Reserved, 0x28 */ |
bogdanm | 86:04dd9b1680ae | 545 | __IO uint32_t RESERVED5; /*!< Reserved, 0x2C */ |
bogdanm | 86:04dd9b1680ae | 546 | __IO uint32_t RESERVED6; /*!< Reserved, 0x30 */ |
bogdanm | 86:04dd9b1680ae | 547 | __IO uint32_t RESERVED7; /*!< Reserved, 0x34 */ |
bogdanm | 86:04dd9b1680ae | 548 | __IO uint32_t RESERVED8; /*!< Reserved, 0x38 */ |
bogdanm | 86:04dd9b1680ae | 549 | __IO uint32_t RESERVED9; /*!< Reserved, 0x3C */ |
bogdanm | 86:04dd9b1680ae | 550 | __IO uint32_t RESERVED10; /*!< Reserved, 0x40 */ |
bogdanm | 86:04dd9b1680ae | 551 | __IO uint32_t RESERVED11; /*!< Reserved, 0x44 */ |
bogdanm | 86:04dd9b1680ae | 552 | __IO uint32_t RESERVED12; /*!< Reserved, 0x48 */ |
bogdanm | 86:04dd9b1680ae | 553 | __IO uint32_t RESERVED13; /*!< Reserved, 0x4C */ |
bogdanm | 86:04dd9b1680ae | 554 | __IO uint32_t CFGR3; /*!< SYSCFG configuration register 3, Address offset: 0x50 */ |
bogdanm | 86:04dd9b1680ae | 555 | } SYSCFG_TypeDef; |
bogdanm | 86:04dd9b1680ae | 556 | |
bogdanm | 86:04dd9b1680ae | 557 | /** |
bogdanm | 86:04dd9b1680ae | 558 | * @brief Inter-integrated Circuit Interface |
bogdanm | 86:04dd9b1680ae | 559 | */ |
bogdanm | 86:04dd9b1680ae | 560 | |
bogdanm | 86:04dd9b1680ae | 561 | typedef struct |
bogdanm | 86:04dd9b1680ae | 562 | { |
bogdanm | 86:04dd9b1680ae | 563 | __IO uint32_t CR1; /*!< I2C Control register 1, Address offset: 0x00 */ |
bogdanm | 86:04dd9b1680ae | 564 | __IO uint32_t CR2; /*!< I2C Control register 2, Address offset: 0x04 */ |
bogdanm | 86:04dd9b1680ae | 565 | __IO uint32_t OAR1; /*!< I2C Own address 1 register, Address offset: 0x08 */ |
bogdanm | 86:04dd9b1680ae | 566 | __IO uint32_t OAR2; /*!< I2C Own address 2 register, Address offset: 0x0C */ |
bogdanm | 86:04dd9b1680ae | 567 | __IO uint32_t TIMINGR; /*!< I2C Timing register, Address offset: 0x10 */ |
bogdanm | 86:04dd9b1680ae | 568 | __IO uint32_t TIMEOUTR; /*!< I2C Timeout register, Address offset: 0x14 */ |
bogdanm | 86:04dd9b1680ae | 569 | __IO uint32_t ISR; /*!< I2C Interrupt and status register, Address offset: 0x18 */ |
bogdanm | 86:04dd9b1680ae | 570 | __IO uint32_t ICR; /*!< I2C Interrupt clear register, Address offset: 0x1C */ |
bogdanm | 86:04dd9b1680ae | 571 | __IO uint32_t PECR; /*!< I2C PEC register, Address offset: 0x20 */ |
bogdanm | 86:04dd9b1680ae | 572 | __IO uint32_t RXDR; /*!< I2C Receive data register, Address offset: 0x24 */ |
bogdanm | 86:04dd9b1680ae | 573 | __IO uint32_t TXDR; /*!< I2C Transmit data register, Address offset: 0x28 */ |
bogdanm | 86:04dd9b1680ae | 574 | }I2C_TypeDef; |
bogdanm | 86:04dd9b1680ae | 575 | |
bogdanm | 86:04dd9b1680ae | 576 | /** |
bogdanm | 86:04dd9b1680ae | 577 | * @brief Independent WATCHDOG |
bogdanm | 86:04dd9b1680ae | 578 | */ |
bogdanm | 86:04dd9b1680ae | 579 | |
bogdanm | 86:04dd9b1680ae | 580 | typedef struct |
bogdanm | 86:04dd9b1680ae | 581 | { |
bogdanm | 86:04dd9b1680ae | 582 | __IO uint32_t KR; /*!< IWDG Key register, Address offset: 0x00 */ |
bogdanm | 86:04dd9b1680ae | 583 | __IO uint32_t PR; /*!< IWDG Prescaler register, Address offset: 0x04 */ |
bogdanm | 86:04dd9b1680ae | 584 | __IO uint32_t RLR; /*!< IWDG Reload register, Address offset: 0x08 */ |
bogdanm | 86:04dd9b1680ae | 585 | __IO uint32_t SR; /*!< IWDG Status register, Address offset: 0x0C */ |
bogdanm | 86:04dd9b1680ae | 586 | __IO uint32_t WINR; /*!< IWDG Window register, Address offset: 0x10 */ |
bogdanm | 86:04dd9b1680ae | 587 | } IWDG_TypeDef; |
bogdanm | 86:04dd9b1680ae | 588 | |
bogdanm | 86:04dd9b1680ae | 589 | /** |
bogdanm | 86:04dd9b1680ae | 590 | * @brief Power Control |
bogdanm | 86:04dd9b1680ae | 591 | */ |
bogdanm | 86:04dd9b1680ae | 592 | |
bogdanm | 86:04dd9b1680ae | 593 | typedef struct |
bogdanm | 86:04dd9b1680ae | 594 | { |
bogdanm | 86:04dd9b1680ae | 595 | __IO uint32_t CR; /*!< PWR power control register, Address offset: 0x00 */ |
bogdanm | 86:04dd9b1680ae | 596 | __IO uint32_t CSR; /*!< PWR power control/status register, Address offset: 0x04 */ |
bogdanm | 86:04dd9b1680ae | 597 | } PWR_TypeDef; |
bogdanm | 86:04dd9b1680ae | 598 | |
bogdanm | 86:04dd9b1680ae | 599 | /** |
bogdanm | 86:04dd9b1680ae | 600 | * @brief Reset and Clock Control |
bogdanm | 86:04dd9b1680ae | 601 | */ |
bogdanm | 86:04dd9b1680ae | 602 | typedef struct |
bogdanm | 86:04dd9b1680ae | 603 | { |
bogdanm | 86:04dd9b1680ae | 604 | __IO uint32_t CR; /*!< RCC clock control register, Address offset: 0x00 */ |
bogdanm | 86:04dd9b1680ae | 605 | __IO uint32_t CFGR; /*!< RCC clock configuration register, Address offset: 0x04 */ |
bogdanm | 86:04dd9b1680ae | 606 | __IO uint32_t CIR; /*!< RCC clock interrupt register, Address offset: 0x08 */ |
bogdanm | 86:04dd9b1680ae | 607 | __IO uint32_t APB2RSTR; /*!< RCC APB2 peripheral reset register, Address offset: 0x0C */ |
bogdanm | 86:04dd9b1680ae | 608 | __IO uint32_t APB1RSTR; /*!< RCC APB1 peripheral reset register, Address offset: 0x10 */ |
bogdanm | 86:04dd9b1680ae | 609 | __IO uint32_t AHBENR; /*!< RCC AHB peripheral clock register, Address offset: 0x14 */ |
bogdanm | 86:04dd9b1680ae | 610 | __IO uint32_t APB2ENR; /*!< RCC APB2 peripheral clock enable register, Address offset: 0x18 */ |
bogdanm | 86:04dd9b1680ae | 611 | __IO uint32_t APB1ENR; /*!< RCC APB1 peripheral clock enable register, Address offset: 0x1C */ |
bogdanm | 86:04dd9b1680ae | 612 | __IO uint32_t BDCR; /*!< RCC Backup domain control register, Address offset: 0x20 */ |
bogdanm | 86:04dd9b1680ae | 613 | __IO uint32_t CSR; /*!< RCC clock control & status register, Address offset: 0x24 */ |
bogdanm | 86:04dd9b1680ae | 614 | __IO uint32_t AHBRSTR; /*!< RCC AHB peripheral reset register, Address offset: 0x28 */ |
bogdanm | 86:04dd9b1680ae | 615 | __IO uint32_t CFGR2; /*!< RCC clock configuration register 2, Address offset: 0x2C */ |
bogdanm | 86:04dd9b1680ae | 616 | __IO uint32_t CFGR3; /*!< RCC clock configuration register 3, Address offset: 0x30 */ |
bogdanm | 86:04dd9b1680ae | 617 | } RCC_TypeDef; |
bogdanm | 86:04dd9b1680ae | 618 | |
bogdanm | 86:04dd9b1680ae | 619 | /** |
bogdanm | 86:04dd9b1680ae | 620 | * @brief Real-Time Clock |
bogdanm | 86:04dd9b1680ae | 621 | */ |
bogdanm | 86:04dd9b1680ae | 622 | |
bogdanm | 86:04dd9b1680ae | 623 | typedef struct |
bogdanm | 86:04dd9b1680ae | 624 | { |
bogdanm | 86:04dd9b1680ae | 625 | __IO uint32_t TR; /*!< RTC time register, Address offset: 0x00 */ |
bogdanm | 86:04dd9b1680ae | 626 | __IO uint32_t DR; /*!< RTC date register, Address offset: 0x04 */ |
bogdanm | 86:04dd9b1680ae | 627 | __IO uint32_t CR; /*!< RTC control register, Address offset: 0x08 */ |
bogdanm | 86:04dd9b1680ae | 628 | __IO uint32_t ISR; /*!< RTC initialization and status register, Address offset: 0x0C */ |
bogdanm | 86:04dd9b1680ae | 629 | __IO uint32_t PRER; /*!< RTC prescaler register, Address offset: 0x10 */ |
bogdanm | 86:04dd9b1680ae | 630 | __IO uint32_t WUTR; /*!< RTC wakeup timer register, Address offset: 0x14 */ |
bogdanm | 86:04dd9b1680ae | 631 | uint32_t RESERVED0; /*!< Reserved, 0x18 */ |
bogdanm | 86:04dd9b1680ae | 632 | __IO uint32_t ALRMAR; /*!< RTC alarm A register, Address offset: 0x1C */ |
bogdanm | 86:04dd9b1680ae | 633 | __IO uint32_t ALRMBR; /*!< RTC alarm B register, Address offset: 0x20 */ |
bogdanm | 86:04dd9b1680ae | 634 | __IO uint32_t WPR; /*!< RTC write protection register, Address offset: 0x24 */ |
bogdanm | 86:04dd9b1680ae | 635 | __IO uint32_t SSR; /*!< RTC sub second register, Address offset: 0x28 */ |
bogdanm | 86:04dd9b1680ae | 636 | __IO uint32_t SHIFTR; /*!< RTC shift control register, Address offset: 0x2C */ |
bogdanm | 86:04dd9b1680ae | 637 | __IO uint32_t TSTR; /*!< RTC time stamp time register, Address offset: 0x30 */ |
bogdanm | 86:04dd9b1680ae | 638 | __IO uint32_t TSDR; /*!< RTC time stamp date register, Address offset: 0x34 */ |
bogdanm | 86:04dd9b1680ae | 639 | __IO uint32_t TSSSR; /*!< RTC time-stamp sub second register, Address offset: 0x38 */ |
bogdanm | 86:04dd9b1680ae | 640 | __IO uint32_t CALR; /*!< RTC calibration register, Address offset: 0x3C */ |
bogdanm | 86:04dd9b1680ae | 641 | __IO uint32_t TAFCR; /*!< RTC tamper and alternate function configuration register, Address offset: 0x40 */ |
bogdanm | 86:04dd9b1680ae | 642 | __IO uint32_t ALRMASSR; /*!< RTC alarm A sub second register, Address offset: 0x44 */ |
bogdanm | 86:04dd9b1680ae | 643 | __IO uint32_t ALRMBSSR; /*!< RTC alarm B sub second register, Address offset: 0x48 */ |
bogdanm | 86:04dd9b1680ae | 644 | uint32_t RESERVED7; /*!< Reserved, 0x4C */ |
bogdanm | 86:04dd9b1680ae | 645 | __IO uint32_t BKP0R; /*!< RTC backup register 0, Address offset: 0x50 */ |
bogdanm | 86:04dd9b1680ae | 646 | __IO uint32_t BKP1R; /*!< RTC backup register 1, Address offset: 0x54 */ |
bogdanm | 86:04dd9b1680ae | 647 | __IO uint32_t BKP2R; /*!< RTC backup register 2, Address offset: 0x58 */ |
bogdanm | 86:04dd9b1680ae | 648 | __IO uint32_t BKP3R; /*!< RTC backup register 3, Address offset: 0x5C */ |
bogdanm | 86:04dd9b1680ae | 649 | __IO uint32_t BKP4R; /*!< RTC backup register 4, Address offset: 0x60 */ |
bogdanm | 86:04dd9b1680ae | 650 | __IO uint32_t BKP5R; /*!< RTC backup register 5, Address offset: 0x64 */ |
bogdanm | 86:04dd9b1680ae | 651 | __IO uint32_t BKP6R; /*!< RTC backup register 6, Address offset: 0x68 */ |
bogdanm | 86:04dd9b1680ae | 652 | __IO uint32_t BKP7R; /*!< RTC backup register 7, Address offset: 0x6C */ |
bogdanm | 86:04dd9b1680ae | 653 | __IO uint32_t BKP8R; /*!< RTC backup register 8, Address offset: 0x70 */ |
bogdanm | 86:04dd9b1680ae | 654 | __IO uint32_t BKP9R; /*!< RTC backup register 9, Address offset: 0x74 */ |
bogdanm | 86:04dd9b1680ae | 655 | __IO uint32_t BKP10R; /*!< RTC backup register 10, Address offset: 0x78 */ |
bogdanm | 86:04dd9b1680ae | 656 | __IO uint32_t BKP11R; /*!< RTC backup register 11, Address offset: 0x7C */ |
bogdanm | 86:04dd9b1680ae | 657 | __IO uint32_t BKP12R; /*!< RTC backup register 12, Address offset: 0x80 */ |
bogdanm | 86:04dd9b1680ae | 658 | __IO uint32_t BKP13R; /*!< RTC backup register 13, Address offset: 0x84 */ |
bogdanm | 86:04dd9b1680ae | 659 | __IO uint32_t BKP14R; /*!< RTC backup register 14, Address offset: 0x88 */ |
bogdanm | 86:04dd9b1680ae | 660 | __IO uint32_t BKP15R; /*!< RTC backup register 15, Address offset: 0x8C */ |
bogdanm | 86:04dd9b1680ae | 661 | } RTC_TypeDef; |
bogdanm | 86:04dd9b1680ae | 662 | |
bogdanm | 86:04dd9b1680ae | 663 | |
bogdanm | 86:04dd9b1680ae | 664 | /** |
bogdanm | 86:04dd9b1680ae | 665 | * @brief Serial Peripheral Interface |
bogdanm | 86:04dd9b1680ae | 666 | */ |
bogdanm | 86:04dd9b1680ae | 667 | |
bogdanm | 86:04dd9b1680ae | 668 | typedef struct |
bogdanm | 86:04dd9b1680ae | 669 | { |
bogdanm | 86:04dd9b1680ae | 670 | __IO uint32_t CR1; /*!< SPI Control register 1, Address offset: 0x00 */ |
bogdanm | 86:04dd9b1680ae | 671 | __IO uint32_t CR2; /*!< SPI Control register 2, Address offset: 0x04 */ |
bogdanm | 86:04dd9b1680ae | 672 | __IO uint32_t SR; /*!< SPI Status register, Address offset: 0x08 */ |
bogdanm | 86:04dd9b1680ae | 673 | __IO uint32_t DR; /*!< SPI data register, Address offset: 0x0C */ |
bogdanm | 86:04dd9b1680ae | 674 | __IO uint32_t CRCPR; /*!< SPI CRC polynomial register, Address offset: 0x10 */ |
bogdanm | 86:04dd9b1680ae | 675 | __IO uint32_t RXCRCR; /*!< SPI Rx CRC register, Address offset: 0x14 */ |
bogdanm | 86:04dd9b1680ae | 676 | __IO uint32_t TXCRCR; /*!< SPI Tx CRC register, Address offset: 0x18 */ |
bogdanm | 86:04dd9b1680ae | 677 | } SPI_TypeDef; |
bogdanm | 86:04dd9b1680ae | 678 | |
bogdanm | 86:04dd9b1680ae | 679 | /** |
bogdanm | 86:04dd9b1680ae | 680 | * @brief TIM |
bogdanm | 86:04dd9b1680ae | 681 | */ |
bogdanm | 86:04dd9b1680ae | 682 | typedef struct |
bogdanm | 86:04dd9b1680ae | 683 | { |
bogdanm | 86:04dd9b1680ae | 684 | __IO uint32_t CR1; /*!< TIM control register 1, Address offset: 0x00 */ |
bogdanm | 86:04dd9b1680ae | 685 | __IO uint32_t CR2; /*!< TIM control register 2, Address offset: 0x04 */ |
bogdanm | 86:04dd9b1680ae | 686 | __IO uint32_t SMCR; /*!< TIM slave mode control register, Address offset: 0x08 */ |
bogdanm | 86:04dd9b1680ae | 687 | __IO uint32_t DIER; /*!< TIM DMA/interrupt enable register, Address offset: 0x0C */ |
bogdanm | 86:04dd9b1680ae | 688 | __IO uint32_t SR; /*!< TIM status register, Address offset: 0x10 */ |
bogdanm | 86:04dd9b1680ae | 689 | __IO uint32_t EGR; /*!< TIM event generation register, Address offset: 0x14 */ |
bogdanm | 86:04dd9b1680ae | 690 | __IO uint32_t CCMR1; /*!< TIM capture/compare mode register 1, Address offset: 0x18 */ |
bogdanm | 86:04dd9b1680ae | 691 | __IO uint32_t CCMR2; /*!< TIM capture/compare mode register 2, Address offset: 0x1C */ |
bogdanm | 86:04dd9b1680ae | 692 | __IO uint32_t CCER; /*!< TIM capture/compare enable register, Address offset: 0x20 */ |
bogdanm | 86:04dd9b1680ae | 693 | __IO uint32_t CNT; /*!< TIM counter register, Address offset: 0x24 */ |
bogdanm | 86:04dd9b1680ae | 694 | __IO uint32_t PSC; /*!< TIM prescaler, Address offset: 0x28 */ |
bogdanm | 86:04dd9b1680ae | 695 | __IO uint32_t ARR; /*!< TIM auto-reload register, Address offset: 0x2C */ |
bogdanm | 86:04dd9b1680ae | 696 | __IO uint32_t RCR; /*!< TIM repetition counter register, Address offset: 0x30 */ |
bogdanm | 86:04dd9b1680ae | 697 | __IO uint32_t CCR1; /*!< TIM capture/compare register 1, Address offset: 0x34 */ |
bogdanm | 86:04dd9b1680ae | 698 | __IO uint32_t CCR2; /*!< TIM capture/compare register 2, Address offset: 0x38 */ |
bogdanm | 86:04dd9b1680ae | 699 | __IO uint32_t CCR3; /*!< TIM capture/compare register 3, Address offset: 0x3C */ |
bogdanm | 86:04dd9b1680ae | 700 | __IO uint32_t CCR4; /*!< TIM capture/compare register 4, Address offset: 0x40 */ |
bogdanm | 86:04dd9b1680ae | 701 | __IO uint32_t BDTR; /*!< TIM break and dead-time register, Address offset: 0x44 */ |
bogdanm | 86:04dd9b1680ae | 702 | __IO uint32_t DCR; /*!< TIM DMA control register, Address offset: 0x48 */ |
bogdanm | 86:04dd9b1680ae | 703 | __IO uint32_t DMAR; /*!< TIM DMA address for full transfer, Address offset: 0x4C */ |
bogdanm | 86:04dd9b1680ae | 704 | __IO uint32_t OR; /*!< TIM option register, Address offset: 0x50 */ |
bogdanm | 86:04dd9b1680ae | 705 | __IO uint32_t CCMR3; /*!< TIM capture/compare mode register 3, Address offset: 0x54 */ |
bogdanm | 86:04dd9b1680ae | 706 | __IO uint32_t CCR5; /*!< TIM capture/compare register5, Address offset: 0x58 */ |
bogdanm | 86:04dd9b1680ae | 707 | __IO uint32_t CCR6; /*!< TIM capture/compare register 4, Address offset: 0x5C */ |
bogdanm | 86:04dd9b1680ae | 708 | } TIM_TypeDef; |
bogdanm | 86:04dd9b1680ae | 709 | |
bogdanm | 86:04dd9b1680ae | 710 | /** |
bogdanm | 86:04dd9b1680ae | 711 | * @brief Touch Sensing Controller (TSC) |
bogdanm | 86:04dd9b1680ae | 712 | */ |
bogdanm | 86:04dd9b1680ae | 713 | typedef struct |
bogdanm | 86:04dd9b1680ae | 714 | { |
bogdanm | 86:04dd9b1680ae | 715 | __IO uint32_t CR; /*!< TSC control register, Address offset: 0x00 */ |
bogdanm | 86:04dd9b1680ae | 716 | __IO uint32_t IER; /*!< TSC interrupt enable register, Address offset: 0x04 */ |
bogdanm | 86:04dd9b1680ae | 717 | __IO uint32_t ICR; /*!< TSC interrupt clear register, Address offset: 0x08 */ |
bogdanm | 86:04dd9b1680ae | 718 | __IO uint32_t ISR; /*!< TSC interrupt status register, Address offset: 0x0C */ |
bogdanm | 86:04dd9b1680ae | 719 | __IO uint32_t IOHCR; /*!< TSC I/O hysteresis control register, Address offset: 0x10 */ |
bogdanm | 86:04dd9b1680ae | 720 | uint32_t RESERVED1; /*!< Reserved, Address offset: 0x14 */ |
bogdanm | 86:04dd9b1680ae | 721 | __IO uint32_t IOASCR; /*!< TSC I/O analog switch control register, Address offset: 0x18 */ |
bogdanm | 86:04dd9b1680ae | 722 | uint32_t RESERVED2; /*!< Reserved, Address offset: 0x1C */ |
bogdanm | 86:04dd9b1680ae | 723 | __IO uint32_t IOSCR; /*!< TSC I/O sampling control register, Address offset: 0x20 */ |
bogdanm | 86:04dd9b1680ae | 724 | uint32_t RESERVED3; /*!< Reserved, Address offset: 0x24 */ |
bogdanm | 86:04dd9b1680ae | 725 | __IO uint32_t IOCCR; /*!< TSC I/O channel control register, Address offset: 0x28 */ |
bogdanm | 86:04dd9b1680ae | 726 | uint32_t RESERVED4; /*!< Reserved, Address offset: 0x2C */ |
bogdanm | 86:04dd9b1680ae | 727 | __IO uint32_t IOGCSR; /*!< TSC I/O group control status register, Address offset: 0x30 */ |
bogdanm | 86:04dd9b1680ae | 728 | __IO uint32_t IOGXCR[8]; /*!< TSC I/O group x counter register, Address offset: 0x34-50 */ |
bogdanm | 86:04dd9b1680ae | 729 | } TSC_TypeDef; |
bogdanm | 86:04dd9b1680ae | 730 | |
bogdanm | 86:04dd9b1680ae | 731 | /** |
bogdanm | 86:04dd9b1680ae | 732 | * @brief Universal Synchronous Asynchronous Receiver Transmitter |
bogdanm | 86:04dd9b1680ae | 733 | */ |
bogdanm | 86:04dd9b1680ae | 734 | |
bogdanm | 86:04dd9b1680ae | 735 | typedef struct |
bogdanm | 86:04dd9b1680ae | 736 | { |
bogdanm | 86:04dd9b1680ae | 737 | __IO uint32_t CR1; /*!< USART Control register 1, Address offset: 0x00 */ |
bogdanm | 86:04dd9b1680ae | 738 | __IO uint32_t CR2; /*!< USART Control register 2, Address offset: 0x04 */ |
bogdanm | 86:04dd9b1680ae | 739 | __IO uint32_t CR3; /*!< USART Control register 3, Address offset: 0x08 */ |
bogdanm | 86:04dd9b1680ae | 740 | __IO uint32_t BRR; /*!< USART Baud rate register, Address offset: 0x0C */ |
bogdanm | 86:04dd9b1680ae | 741 | __IO uint32_t GTPR; /*!< USART Guard time and prescaler register, Address offset: 0x10 */ |
bogdanm | 86:04dd9b1680ae | 742 | __IO uint32_t RTOR; /*!< USART Receiver Time Out register, Address offset: 0x14 */ |
bogdanm | 86:04dd9b1680ae | 743 | __IO uint32_t RQR; /*!< USART Request register, Address offset: 0x18 */ |
bogdanm | 86:04dd9b1680ae | 744 | __IO uint32_t ISR; /*!< USART Interrupt and status register, Address offset: 0x1C */ |
bogdanm | 86:04dd9b1680ae | 745 | __IO uint32_t ICR; /*!< USART Interrupt flag Clear register, Address offset: 0x20 */ |
bogdanm | 86:04dd9b1680ae | 746 | __IO uint16_t RDR; /*!< USART Receive Data register, Address offset: 0x24 */ |
bogdanm | 86:04dd9b1680ae | 747 | uint16_t RESERVED1; /*!< Reserved, 0x26 */ |
bogdanm | 86:04dd9b1680ae | 748 | __IO uint16_t TDR; /*!< USART Transmit Data register, Address offset: 0x28 */ |
bogdanm | 86:04dd9b1680ae | 749 | uint16_t RESERVED2; /*!< Reserved, 0x2A */ |
bogdanm | 86:04dd9b1680ae | 750 | } USART_TypeDef; |
bogdanm | 86:04dd9b1680ae | 751 | |
bogdanm | 86:04dd9b1680ae | 752 | /** |
bogdanm | 86:04dd9b1680ae | 753 | * @brief Window WATCHDOG |
bogdanm | 86:04dd9b1680ae | 754 | */ |
bogdanm | 86:04dd9b1680ae | 755 | typedef struct |
bogdanm | 86:04dd9b1680ae | 756 | { |
bogdanm | 86:04dd9b1680ae | 757 | __IO uint32_t CR; /*!< WWDG Control register, Address offset: 0x00 */ |
bogdanm | 86:04dd9b1680ae | 758 | __IO uint32_t CFR; /*!< WWDG Configuration register, Address offset: 0x04 */ |
bogdanm | 86:04dd9b1680ae | 759 | __IO uint32_t SR; /*!< WWDG Status register, Address offset: 0x08 */ |
bogdanm | 86:04dd9b1680ae | 760 | } WWDG_TypeDef; |
bogdanm | 86:04dd9b1680ae | 761 | |
bogdanm | 86:04dd9b1680ae | 762 | /** @addtogroup Peripheral_memory_map |
bogdanm | 86:04dd9b1680ae | 763 | * @{ |
bogdanm | 86:04dd9b1680ae | 764 | */ |
bogdanm | 86:04dd9b1680ae | 765 | |
bogdanm | 86:04dd9b1680ae | 766 | #define FLASH_BASE ((uint32_t)0x08000000) /*!< FLASH(up to 64KB) base address in the alias region */ |
bogdanm | 86:04dd9b1680ae | 767 | #define CCMDATARAM_BASE ((uint32_t)0x10000000) /*!< CCM(core coupled memory) data RAM(4 KB) base address in the alias region */ |
bogdanm | 86:04dd9b1680ae | 768 | #define SRAM_BASE ((uint32_t)0x20000000) /*!< SRAM(up to 12KB) base address in the alias region */ |
bogdanm | 86:04dd9b1680ae | 769 | #define PERIPH_BASE ((uint32_t)0x40000000) /*!< Peripheral base address in the alias region */ |
bogdanm | 86:04dd9b1680ae | 770 | |
bogdanm | 86:04dd9b1680ae | 771 | #define CCMDATARAM_BB_BASE ((uint32_t)0x12000000) /*!< CCM(core coupled memory) data RAM(4 KB) base address in the bit-band region */ |
bogdanm | 86:04dd9b1680ae | 772 | #define SRAM_BB_BASE ((uint32_t)0x22000000) /*!< SRAM(up to 12KB) base address in the bit-band region */ |
bogdanm | 86:04dd9b1680ae | 773 | #define PERIPH_BB_BASE ((uint32_t)0x42000000) /*!< Peripheral base address in the bit-band region */ |
bogdanm | 86:04dd9b1680ae | 774 | |
bogdanm | 86:04dd9b1680ae | 775 | |
bogdanm | 86:04dd9b1680ae | 776 | /*!< Peripheral memory map */ |
bogdanm | 86:04dd9b1680ae | 777 | #define APB1PERIPH_BASE PERIPH_BASE |
bogdanm | 86:04dd9b1680ae | 778 | #define APB2PERIPH_BASE (PERIPH_BASE + 0x00010000) |
bogdanm | 86:04dd9b1680ae | 779 | #define AHB1PERIPH_BASE (PERIPH_BASE + 0x00020000) |
bogdanm | 86:04dd9b1680ae | 780 | #define AHB2PERIPH_BASE (PERIPH_BASE + 0x08000000) |
bogdanm | 86:04dd9b1680ae | 781 | #define AHB3PERIPH_BASE (PERIPH_BASE + 0x10000000) |
bogdanm | 86:04dd9b1680ae | 782 | |
bogdanm | 86:04dd9b1680ae | 783 | /*!< APB1 peripherals */ |
bogdanm | 86:04dd9b1680ae | 784 | #define TIM2_BASE (APB1PERIPH_BASE + 0x00000000) |
bogdanm | 86:04dd9b1680ae | 785 | #define TIM3_BASE (APB1PERIPH_BASE + 0x00000400) |
bogdanm | 86:04dd9b1680ae | 786 | #define TIM6_BASE (APB1PERIPH_BASE + 0x00001000) |
bogdanm | 86:04dd9b1680ae | 787 | #define TIM7_BASE (APB1PERIPH_BASE + 0x00001400) |
bogdanm | 86:04dd9b1680ae | 788 | #define RTC_BASE (APB1PERIPH_BASE + 0x00002800) |
bogdanm | 86:04dd9b1680ae | 789 | #define WWDG_BASE (APB1PERIPH_BASE + 0x00002C00) |
bogdanm | 86:04dd9b1680ae | 790 | #define IWDG_BASE (APB1PERIPH_BASE + 0x00003000) |
bogdanm | 86:04dd9b1680ae | 791 | #define USART2_BASE (APB1PERIPH_BASE + 0x00004400) |
bogdanm | 86:04dd9b1680ae | 792 | #define USART3_BASE (APB1PERIPH_BASE + 0x00004800) |
bogdanm | 86:04dd9b1680ae | 793 | #define I2C1_BASE (APB1PERIPH_BASE + 0x00005400) |
bogdanm | 86:04dd9b1680ae | 794 | #define CAN_BASE (APB1PERIPH_BASE + 0x00006400) |
bogdanm | 86:04dd9b1680ae | 795 | #define PWR_BASE (APB1PERIPH_BASE + 0x00007000) |
bogdanm | 86:04dd9b1680ae | 796 | #define DAC1_BASE (APB1PERIPH_BASE + 0x00007400) |
bogdanm | 86:04dd9b1680ae | 797 | #define DAC2_BASE (APB1PERIPH_BASE + 0x00009800) |
bogdanm | 86:04dd9b1680ae | 798 | #define DAC_BASE DAC1_BASE |
bogdanm | 86:04dd9b1680ae | 799 | |
bogdanm | 86:04dd9b1680ae | 800 | /*!< APB2 peripherals */ |
bogdanm | 86:04dd9b1680ae | 801 | #define SYSCFG_BASE (APB2PERIPH_BASE + 0x00000000) |
bogdanm | 86:04dd9b1680ae | 802 | #define COMP2_BASE (APB2PERIPH_BASE + 0x00000020) |
bogdanm | 86:04dd9b1680ae | 803 | #define COMP4_BASE (APB2PERIPH_BASE + 0x00000028) |
bogdanm | 86:04dd9b1680ae | 804 | #define COMP6_BASE (APB2PERIPH_BASE + 0x00000030) |
bogdanm | 86:04dd9b1680ae | 805 | #define COMP_BASE COMP2_BASE |
bogdanm | 86:04dd9b1680ae | 806 | #define OPAMP2_BASE (APB2PERIPH_BASE + 0x0000003C) |
bogdanm | 86:04dd9b1680ae | 807 | #define OPAMP_BASE OPAMP2_BASE |
bogdanm | 86:04dd9b1680ae | 808 | #define EXTI_BASE (APB2PERIPH_BASE + 0x00000400) |
bogdanm | 86:04dd9b1680ae | 809 | #define TIM1_BASE (APB2PERIPH_BASE + 0x00002C00) |
bogdanm | 86:04dd9b1680ae | 810 | #define SPI1_BASE (APB2PERIPH_BASE + 0x00003000) |
bogdanm | 86:04dd9b1680ae | 811 | #define USART1_BASE (APB2PERIPH_BASE + 0x00003800) |
bogdanm | 86:04dd9b1680ae | 812 | #define TIM15_BASE (APB2PERIPH_BASE + 0x00004000) |
bogdanm | 86:04dd9b1680ae | 813 | #define TIM16_BASE (APB2PERIPH_BASE + 0x00004400) |
bogdanm | 86:04dd9b1680ae | 814 | #define TIM17_BASE (APB2PERIPH_BASE + 0x00004800) |
bogdanm | 86:04dd9b1680ae | 815 | #define HRTIM1_BASE (APB2PERIPH_BASE + 0x00007400) |
bogdanm | 86:04dd9b1680ae | 816 | #define HRTIM1_TIMA_BASE (HRTIM1_BASE + 0x00000080) |
bogdanm | 86:04dd9b1680ae | 817 | #define HRTIM1_TIMB_BASE (HRTIM1_BASE + 0x00000100) |
bogdanm | 86:04dd9b1680ae | 818 | #define HRTIM1_TIMC_BASE (HRTIM1_BASE + 0x00000180) |
bogdanm | 86:04dd9b1680ae | 819 | #define HRTIM1_TIMD_BASE (HRTIM1_BASE + 0x00000200) |
bogdanm | 86:04dd9b1680ae | 820 | #define HRTIM1_TIME_BASE (HRTIM1_BASE + 0x00000280) |
bogdanm | 86:04dd9b1680ae | 821 | #define HRTIM1_COMMON_BASE (HRTIM1_BASE + 0x00000380) |
bogdanm | 86:04dd9b1680ae | 822 | |
bogdanm | 86:04dd9b1680ae | 823 | /*!< AHB1 peripherals */ |
bogdanm | 86:04dd9b1680ae | 824 | #define DMA1_BASE (AHB1PERIPH_BASE + 0x00000000) |
bogdanm | 86:04dd9b1680ae | 825 | #define DMA1_Channel1_BASE (AHB1PERIPH_BASE + 0x00000008) |
bogdanm | 86:04dd9b1680ae | 826 | #define DMA1_Channel2_BASE (AHB1PERIPH_BASE + 0x0000001C) |
bogdanm | 86:04dd9b1680ae | 827 | #define DMA1_Channel3_BASE (AHB1PERIPH_BASE + 0x00000030) |
bogdanm | 86:04dd9b1680ae | 828 | #define DMA1_Channel4_BASE (AHB1PERIPH_BASE + 0x00000044) |
bogdanm | 86:04dd9b1680ae | 829 | #define DMA1_Channel5_BASE (AHB1PERIPH_BASE + 0x00000058) |
bogdanm | 86:04dd9b1680ae | 830 | #define DMA1_Channel6_BASE (AHB1PERIPH_BASE + 0x0000006C) |
bogdanm | 86:04dd9b1680ae | 831 | #define DMA1_Channel7_BASE (AHB1PERIPH_BASE + 0x00000080) |
bogdanm | 86:04dd9b1680ae | 832 | #define RCC_BASE (AHB1PERIPH_BASE + 0x00001000) |
bogdanm | 86:04dd9b1680ae | 833 | #define FLASH_R_BASE (AHB1PERIPH_BASE + 0x00002000) /*!< Flash registers base address */ |
bogdanm | 86:04dd9b1680ae | 834 | #define OB_BASE ((uint32_t)0x1FFFF800) /*!< Flash Option Bytes base address */ |
bogdanm | 86:04dd9b1680ae | 835 | #define CRC_BASE (AHB1PERIPH_BASE + 0x00003000) |
bogdanm | 86:04dd9b1680ae | 836 | #define TSC_BASE (AHB1PERIPH_BASE + 0x00004000) |
bogdanm | 86:04dd9b1680ae | 837 | |
bogdanm | 86:04dd9b1680ae | 838 | /*!< AHB2 peripherals */ |
bogdanm | 86:04dd9b1680ae | 839 | #define GPIOA_BASE (AHB2PERIPH_BASE + 0x00000000) |
bogdanm | 86:04dd9b1680ae | 840 | #define GPIOB_BASE (AHB2PERIPH_BASE + 0x00000400) |
bogdanm | 86:04dd9b1680ae | 841 | #define GPIOC_BASE (AHB2PERIPH_BASE + 0x00000800) |
bogdanm | 86:04dd9b1680ae | 842 | #define GPIOD_BASE (AHB2PERIPH_BASE + 0x00000C00) |
bogdanm | 86:04dd9b1680ae | 843 | #define GPIOF_BASE (AHB2PERIPH_BASE + 0x00001400) |
bogdanm | 86:04dd9b1680ae | 844 | |
bogdanm | 86:04dd9b1680ae | 845 | /*!< AHB3 peripherals */ |
bogdanm | 86:04dd9b1680ae | 846 | #define ADC1_BASE (AHB3PERIPH_BASE + 0x00000000) |
bogdanm | 86:04dd9b1680ae | 847 | #define ADC2_BASE (AHB3PERIPH_BASE + 0x00000100) |
bogdanm | 86:04dd9b1680ae | 848 | #define ADC1_2_COMMON_BASE (AHB3PERIPH_BASE + 0x00000300) |
bogdanm | 86:04dd9b1680ae | 849 | |
bogdanm | 86:04dd9b1680ae | 850 | #define DBGMCU_BASE ((uint32_t)0xE0042000) /*!< Debug MCU registers base address */ |
bogdanm | 86:04dd9b1680ae | 851 | /** |
bogdanm | 86:04dd9b1680ae | 852 | * @} |
bogdanm | 86:04dd9b1680ae | 853 | */ |
bogdanm | 86:04dd9b1680ae | 854 | |
bogdanm | 86:04dd9b1680ae | 855 | /** @addtogroup Peripheral_declaration |
bogdanm | 86:04dd9b1680ae | 856 | * @{ |
bogdanm | 86:04dd9b1680ae | 857 | */ |
bogdanm | 86:04dd9b1680ae | 858 | #define HRTIM1 ((HRTIM_TypeDef *) HRTIM1_BASE) |
bogdanm | 86:04dd9b1680ae | 859 | #define HRTIM1_TIMA ((HRTIM_TIM_TypeDef *) HRTIM1_TIMA_BASE) |
bogdanm | 86:04dd9b1680ae | 860 | #define HRTIM1_TIMB ((HRTIM_TIM_TypeDef *) HRTIM1_TIMB_BASE) |
bogdanm | 86:04dd9b1680ae | 861 | #define HRTIM1_TIMC ((HRTIM_TIM_TypeDef *) HRTIM1_TIMC_BASE) |
bogdanm | 86:04dd9b1680ae | 862 | #define HRTIM1_TIMD ((HRTIM_TIM_TypeDef *) HRTIM1_TIMD_BASE) |
bogdanm | 86:04dd9b1680ae | 863 | #define HRTIM1_TIME ((HRTIM_TIM_TypeDef *) HRTIM1_TIME_BASE) |
bogdanm | 86:04dd9b1680ae | 864 | #define HRTIM1_COMMON ((HRTIM_Common_TypeDef *) HRTIM1_COMMON_BASE) |
bogdanm | 86:04dd9b1680ae | 865 | #define TIM2 ((TIM_TypeDef *) TIM2_BASE) |
bogdanm | 86:04dd9b1680ae | 866 | #define TIM3 ((TIM_TypeDef *) TIM3_BASE) |
bogdanm | 86:04dd9b1680ae | 867 | #define TIM6 ((TIM_TypeDef *) TIM6_BASE) |
bogdanm | 86:04dd9b1680ae | 868 | #define TIM7 ((TIM_TypeDef *) TIM7_BASE) |
bogdanm | 86:04dd9b1680ae | 869 | #define RTC ((RTC_TypeDef *) RTC_BASE) |
bogdanm | 86:04dd9b1680ae | 870 | #define WWDG ((WWDG_TypeDef *) WWDG_BASE) |
bogdanm | 86:04dd9b1680ae | 871 | #define IWDG ((IWDG_TypeDef *) IWDG_BASE) |
bogdanm | 86:04dd9b1680ae | 872 | #define USART2 ((USART_TypeDef *) USART2_BASE) |
bogdanm | 86:04dd9b1680ae | 873 | #define USART3 ((USART_TypeDef *) USART3_BASE) |
bogdanm | 86:04dd9b1680ae | 874 | #define I2C1 ((I2C_TypeDef *) I2C1_BASE) |
bogdanm | 86:04dd9b1680ae | 875 | #define CAN ((CAN_TypeDef *) CAN_BASE) |
bogdanm | 86:04dd9b1680ae | 876 | #define PWR ((PWR_TypeDef *) PWR_BASE) |
bogdanm | 86:04dd9b1680ae | 877 | #define DAC1 ((DAC_TypeDef *) DAC1_BASE) |
bogdanm | 86:04dd9b1680ae | 878 | #define DAC2 ((DAC_TypeDef *) DAC2_BASE) |
bogdanm | 86:04dd9b1680ae | 879 | #define DAC ((DAC_TypeDef *) DAC_BASE) |
bogdanm | 86:04dd9b1680ae | 880 | #define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE) |
bogdanm | 86:04dd9b1680ae | 881 | #define COMP2 ((COMP_TypeDef *) COMP2_BASE) |
bogdanm | 86:04dd9b1680ae | 882 | #define COMP4 ((COMP_TypeDef *) COMP4_BASE) |
bogdanm | 86:04dd9b1680ae | 883 | #define COMP6 ((COMP_TypeDef *) COMP6_BASE) |
bogdanm | 86:04dd9b1680ae | 884 | #define COMP ((COMP_TypeDef *) COMP_BASE) |
bogdanm | 86:04dd9b1680ae | 885 | #define OPAMP2 ((OPAMP_TypeDef *) OPAMP2_BASE) |
bogdanm | 86:04dd9b1680ae | 886 | #define OPAMP ((OPAMP_TypeDef *) OPAMP_BASE) |
bogdanm | 86:04dd9b1680ae | 887 | #define EXTI ((EXTI_TypeDef *) EXTI_BASE) |
bogdanm | 86:04dd9b1680ae | 888 | #define TIM1 ((TIM_TypeDef *) TIM1_BASE) |
bogdanm | 86:04dd9b1680ae | 889 | #define SPI1 ((SPI_TypeDef *) SPI1_BASE) |
bogdanm | 86:04dd9b1680ae | 890 | #define USART1 ((USART_TypeDef *) USART1_BASE) |
bogdanm | 86:04dd9b1680ae | 891 | #define TIM15 ((TIM_TypeDef *) TIM15_BASE) |
bogdanm | 86:04dd9b1680ae | 892 | #define TIM16 ((TIM_TypeDef *) TIM16_BASE) |
bogdanm | 86:04dd9b1680ae | 893 | #define TIM17 ((TIM_TypeDef *) TIM17_BASE) |
bogdanm | 86:04dd9b1680ae | 894 | #define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE) |
bogdanm | 86:04dd9b1680ae | 895 | #define DMA1 ((DMA_TypeDef *) DMA1_BASE) |
bogdanm | 86:04dd9b1680ae | 896 | #define DMA1_Channel1 ((DMA_Channel_TypeDef *) DMA1_Channel1_BASE) |
bogdanm | 86:04dd9b1680ae | 897 | #define DMA1_Channel2 ((DMA_Channel_TypeDef *) DMA1_Channel2_BASE) |
bogdanm | 86:04dd9b1680ae | 898 | #define DMA1_Channel3 ((DMA_Channel_TypeDef *) DMA1_Channel3_BASE) |
bogdanm | 86:04dd9b1680ae | 899 | #define DMA1_Channel4 ((DMA_Channel_TypeDef *) DMA1_Channel4_BASE) |
bogdanm | 86:04dd9b1680ae | 900 | #define DMA1_Channel5 ((DMA_Channel_TypeDef *) DMA1_Channel5_BASE) |
bogdanm | 86:04dd9b1680ae | 901 | #define DMA1_Channel6 ((DMA_Channel_TypeDef *) DMA1_Channel6_BASE) |
bogdanm | 86:04dd9b1680ae | 902 | #define DMA1_Channel7 ((DMA_Channel_TypeDef *) DMA1_Channel7_BASE) |
bogdanm | 86:04dd9b1680ae | 903 | #define RCC ((RCC_TypeDef *) RCC_BASE) |
bogdanm | 86:04dd9b1680ae | 904 | #define FLASH ((FLASH_TypeDef *) FLASH_R_BASE) |
bogdanm | 86:04dd9b1680ae | 905 | #define OB ((OB_TypeDef *) OB_BASE) |
bogdanm | 86:04dd9b1680ae | 906 | #define CRC ((CRC_TypeDef *) CRC_BASE) |
bogdanm | 86:04dd9b1680ae | 907 | #define TSC ((TSC_TypeDef *) TSC_BASE) |
bogdanm | 86:04dd9b1680ae | 908 | #define GPIOA ((GPIO_TypeDef *) GPIOA_BASE) |
bogdanm | 86:04dd9b1680ae | 909 | #define GPIOB ((GPIO_TypeDef *) GPIOB_BASE) |
bogdanm | 86:04dd9b1680ae | 910 | #define GPIOC ((GPIO_TypeDef *) GPIOC_BASE) |
bogdanm | 86:04dd9b1680ae | 911 | #define GPIOD ((GPIO_TypeDef *) GPIOD_BASE) |
bogdanm | 86:04dd9b1680ae | 912 | #define GPIOF ((GPIO_TypeDef *) GPIOF_BASE) |
bogdanm | 86:04dd9b1680ae | 913 | #define ADC1 ((ADC_TypeDef *) ADC1_BASE) |
bogdanm | 86:04dd9b1680ae | 914 | #define ADC2 ((ADC_TypeDef *) ADC2_BASE) |
bogdanm | 86:04dd9b1680ae | 915 | #define ADC1_2_COMMON ((ADC_Common_TypeDef *) ADC1_2_COMMON_BASE) |
bogdanm | 86:04dd9b1680ae | 916 | /** |
bogdanm | 86:04dd9b1680ae | 917 | * @} |
bogdanm | 86:04dd9b1680ae | 918 | */ |
bogdanm | 86:04dd9b1680ae | 919 | |
bogdanm | 86:04dd9b1680ae | 920 | /** @addtogroup Exported_constants |
bogdanm | 86:04dd9b1680ae | 921 | * @{ |
bogdanm | 86:04dd9b1680ae | 922 | */ |
bogdanm | 86:04dd9b1680ae | 923 | |
bogdanm | 86:04dd9b1680ae | 924 | /** @addtogroup Peripheral_Registers_Bits_Definition |
bogdanm | 86:04dd9b1680ae | 925 | * @{ |
bogdanm | 86:04dd9b1680ae | 926 | */ |
bogdanm | 86:04dd9b1680ae | 927 | |
bogdanm | 86:04dd9b1680ae | 928 | /******************************************************************************/ |
bogdanm | 86:04dd9b1680ae | 929 | /* Peripheral Registers_Bits_Definition */ |
bogdanm | 86:04dd9b1680ae | 930 | /******************************************************************************/ |
bogdanm | 86:04dd9b1680ae | 931 | |
bogdanm | 86:04dd9b1680ae | 932 | /******************************************************************************/ |
bogdanm | 86:04dd9b1680ae | 933 | /* */ |
bogdanm | 86:04dd9b1680ae | 934 | /* Analog to Digital Converter SAR (ADC) */ |
bogdanm | 86:04dd9b1680ae | 935 | /* */ |
bogdanm | 86:04dd9b1680ae | 936 | /******************************************************************************/ |
bogdanm | 86:04dd9b1680ae | 937 | /******************** Bit definition for ADC_ISR register ********************/ |
bogdanm | 86:04dd9b1680ae | 938 | #define ADC_ISR_ADRD ((uint32_t)0x00000001) /*!< ADC Ready (ADRDY) flag */ |
bogdanm | 86:04dd9b1680ae | 939 | #define ADC_ISR_EOSMP ((uint32_t)0x00000002) /*!< ADC End of Sampling flag */ |
bogdanm | 86:04dd9b1680ae | 940 | #define ADC_ISR_EOC ((uint32_t)0x00000004) /*!< ADC End of Regular Conversion flag */ |
bogdanm | 86:04dd9b1680ae | 941 | #define ADC_ISR_EOS ((uint32_t)0x00000008) /*!< ADC End of Regular sequence of Conversions flag */ |
bogdanm | 86:04dd9b1680ae | 942 | #define ADC_ISR_OVR ((uint32_t)0x00000010) /*!< ADC overrun flag */ |
bogdanm | 86:04dd9b1680ae | 943 | #define ADC_ISR_JEOC ((uint32_t)0x00000020) /*!< ADC End of Injected Conversion flag */ |
bogdanm | 86:04dd9b1680ae | 944 | #define ADC_ISR_JEOS ((uint32_t)0x00000040) /*!< ADC End of Injected sequence of Conversions flag */ |
bogdanm | 86:04dd9b1680ae | 945 | #define ADC_ISR_AWD1 ((uint32_t)0x00000080) /*!< ADC Analog watchdog 1 flag */ |
bogdanm | 86:04dd9b1680ae | 946 | #define ADC_ISR_AWD2 ((uint32_t)0x00000100) /*!< ADC Analog watchdog 2 flag */ |
bogdanm | 86:04dd9b1680ae | 947 | #define ADC_ISR_AWD3 ((uint32_t)0x00000200) /*!< ADC Analog watchdog 3 flag */ |
bogdanm | 86:04dd9b1680ae | 948 | #define ADC_ISR_JQOVF ((uint32_t)0x00000400) /*!< ADC Injected Context Queue Overflow flag */ |
bogdanm | 86:04dd9b1680ae | 949 | |
bogdanm | 86:04dd9b1680ae | 950 | /******************** Bit definition for ADC_IER register ********************/ |
bogdanm | 86:04dd9b1680ae | 951 | #define ADC_IER_RDY ((uint32_t)0x00000001) /*!< ADC Ready (ADRDY) interrupt source */ |
bogdanm | 86:04dd9b1680ae | 952 | #define ADC_IER_EOSMP ((uint32_t)0x00000002) /*!< ADC End of Sampling interrupt source */ |
bogdanm | 86:04dd9b1680ae | 953 | #define ADC_IER_EOC ((uint32_t)0x00000004) /*!< ADC End of Regular Conversion interrupt source */ |
bogdanm | 86:04dd9b1680ae | 954 | #define ADC_IER_EOS ((uint32_t)0x00000008) /*!< ADC End of Regular sequence of Conversions interrupt source */ |
bogdanm | 86:04dd9b1680ae | 955 | #define ADC_IER_OVR ((uint32_t)0x00000010) /*!< ADC overrun interrupt source */ |
bogdanm | 86:04dd9b1680ae | 956 | #define ADC_IER_JEOC ((uint32_t)0x00000020) /*!< ADC End of Injected Conversion interrupt source */ |
bogdanm | 86:04dd9b1680ae | 957 | #define ADC_IER_JEOS ((uint32_t)0x00000040) /*!< ADC End of Injected sequence of Conversions interrupt source */ |
bogdanm | 86:04dd9b1680ae | 958 | #define ADC_IER_AWD1 ((uint32_t)0x00000080) /*!< ADC Analog watchdog 1 interrupt source */ |
bogdanm | 86:04dd9b1680ae | 959 | #define ADC_IER_AWD2 ((uint32_t)0x00000100) /*!< ADC Analog watchdog 2 interrupt source */ |
bogdanm | 86:04dd9b1680ae | 960 | #define ADC_IER_AWD3 ((uint32_t)0x00000200) /*!< ADC Analog watchdog 3 interrupt source */ |
bogdanm | 86:04dd9b1680ae | 961 | #define ADC_IER_JQOVF ((uint32_t)0x00000400) /*!< ADC Injected Context Queue Overflow interrupt source */ |
bogdanm | 86:04dd9b1680ae | 962 | |
bogdanm | 86:04dd9b1680ae | 963 | /******************** Bit definition for ADC_CR register ********************/ |
bogdanm | 86:04dd9b1680ae | 964 | #define ADC_CR_ADEN ((uint32_t)0x00000001) /*!< ADC Enable control */ |
bogdanm | 86:04dd9b1680ae | 965 | #define ADC_CR_ADDIS ((uint32_t)0x00000002) /*!< ADC Disable command */ |
bogdanm | 86:04dd9b1680ae | 966 | #define ADC_CR_ADSTART ((uint32_t)0x00000004) /*!< ADC Start of Regular conversion */ |
bogdanm | 86:04dd9b1680ae | 967 | #define ADC_CR_JADSTART ((uint32_t)0x00000008) /*!< ADC Start of injected conversion */ |
bogdanm | 86:04dd9b1680ae | 968 | #define ADC_CR_ADSTP ((uint32_t)0x00000010) /*!< ADC Stop of Regular conversion */ |
bogdanm | 86:04dd9b1680ae | 969 | #define ADC_CR_JADSTP ((uint32_t)0x00000020) /*!< ADC Stop of injected conversion */ |
bogdanm | 86:04dd9b1680ae | 970 | #define ADC_CR_ADVREGEN ((uint32_t)0x30000000) /*!< ADC Voltage regulator Enable */ |
bogdanm | 86:04dd9b1680ae | 971 | #define ADC_CR_ADVREGEN_0 ((uint32_t)0x10000000) /*!< ADC ADVREGEN bit 0 */ |
bogdanm | 86:04dd9b1680ae | 972 | #define ADC_CR_ADVREGEN_1 ((uint32_t)0x20000000) /*!< ADC ADVREGEN bit 1 */ |
bogdanm | 86:04dd9b1680ae | 973 | #define ADC_CR_ADCALDIF ((uint32_t)0x40000000) /*!< ADC Differential Mode for calibration */ |
bogdanm | 86:04dd9b1680ae | 974 | #define ADC_CR_ADCAL ((uint32_t)0x80000000) /*!< ADC Calibration */ |
bogdanm | 86:04dd9b1680ae | 975 | |
bogdanm | 86:04dd9b1680ae | 976 | /******************** Bit definition for ADC_CFGR register ********************/ |
bogdanm | 86:04dd9b1680ae | 977 | #define ADC_CFGR_DMAEN ((uint32_t)0x00000001) /*!< ADC DMA Enable */ |
bogdanm | 86:04dd9b1680ae | 978 | #define ADC_CFGR_DMACFG ((uint32_t)0x00000002) /*!< ADC DMA configuration */ |
bogdanm | 86:04dd9b1680ae | 979 | |
bogdanm | 86:04dd9b1680ae | 980 | #define ADC_CFGR_RES ((uint32_t)0x00000018) /*!< ADC Data resolution */ |
bogdanm | 86:04dd9b1680ae | 981 | #define ADC_CFGR_RES_0 ((uint32_t)0x00000008) /*!< ADC RES bit 0 */ |
bogdanm | 86:04dd9b1680ae | 982 | #define ADC_CFGR_RES_1 ((uint32_t)0x00000010) /*!< ADC RES bit 1 */ |
bogdanm | 86:04dd9b1680ae | 983 | |
bogdanm | 86:04dd9b1680ae | 984 | #define ADC_CFGR_ALIGN ((uint32_t)0x00000020) /*!< ADC Data Alignement */ |
bogdanm | 86:04dd9b1680ae | 985 | |
bogdanm | 86:04dd9b1680ae | 986 | #define ADC_CFGR_EXTSEL ((uint32_t)0x000003C0) /*!< ADC External trigger selection for regular group */ |
bogdanm | 86:04dd9b1680ae | 987 | #define ADC_CFGR_EXTSEL_0 ((uint32_t)0x00000040) /*!< ADC EXTSEL bit 0 */ |
bogdanm | 86:04dd9b1680ae | 988 | #define ADC_CFGR_EXTSEL_1 ((uint32_t)0x00000080) /*!< ADC EXTSEL bit 1 */ |
bogdanm | 86:04dd9b1680ae | 989 | #define ADC_CFGR_EXTSEL_2 ((uint32_t)0x00000100) /*!< ADC EXTSEL bit 2 */ |
bogdanm | 86:04dd9b1680ae | 990 | #define ADC_CFGR_EXTSEL_3 ((uint32_t)0x00000200) /*!< ADC EXTSEL bit 3 */ |
bogdanm | 86:04dd9b1680ae | 991 | |
bogdanm | 86:04dd9b1680ae | 992 | #define ADC_CFGR_EXTEN ((uint32_t)0x00000C00) /*!< ADC External trigger enable and polarity selection for regular channels */ |
bogdanm | 86:04dd9b1680ae | 993 | #define ADC_CFGR_EXTEN_0 ((uint32_t)0x00000400) /*!< ADC EXTEN bit 0 */ |
bogdanm | 86:04dd9b1680ae | 994 | #define ADC_CFGR_EXTEN_1 ((uint32_t)0x00000800) /*!< ADC EXTEN bit 1 */ |
bogdanm | 86:04dd9b1680ae | 995 | |
bogdanm | 86:04dd9b1680ae | 996 | #define ADC_CFGR_OVRMOD ((uint32_t)0x00001000) /*!< ADC overrun mode */ |
bogdanm | 86:04dd9b1680ae | 997 | #define ADC_CFGR_CONT ((uint32_t)0x00002000) /*!< ADC Single/continuous conversion mode for regular conversion */ |
bogdanm | 86:04dd9b1680ae | 998 | #define ADC_CFGR_AUTDLY ((uint32_t)0x00004000) /*!< ADC Delayed conversion mode */ |
bogdanm | 86:04dd9b1680ae | 999 | #define ADC_CFGR_AUTOFF ((uint32_t)0x00008000) /*!< ADC Auto power OFF */ |
bogdanm | 86:04dd9b1680ae | 1000 | #define ADC_CFGR_DISCEN ((uint32_t)0x00010000) /*!< ADC Discontinuous mode for regular channels */ |
bogdanm | 86:04dd9b1680ae | 1001 | |
bogdanm | 86:04dd9b1680ae | 1002 | #define ADC_CFGR_DISCNUM ((uint32_t)0x000E0000) /*!< ADC Discontinuous mode channel count */ |
bogdanm | 86:04dd9b1680ae | 1003 | #define ADC_CFGR_DISCNUM_0 ((uint32_t)0x00020000) /*!< ADC DISCNUM bit 0 */ |
bogdanm | 86:04dd9b1680ae | 1004 | #define ADC_CFGR_DISCNUM_1 ((uint32_t)0x00040000) /*!< ADC DISCNUM bit 1 */ |
bogdanm | 86:04dd9b1680ae | 1005 | #define ADC_CFGR_DISCNUM_2 ((uint32_t)0x00080000) /*!< ADC DISCNUM bit 2 */ |
bogdanm | 86:04dd9b1680ae | 1006 | |
bogdanm | 86:04dd9b1680ae | 1007 | #define ADC_CFGR_JDISCEN ((uint32_t)0x00100000) /*!< ADC Discontinous mode on injected channels */ |
bogdanm | 86:04dd9b1680ae | 1008 | #define ADC_CFGR_JQM ((uint32_t)0x00200000) /*!< ADC JSQR Queue mode */ |
bogdanm | 86:04dd9b1680ae | 1009 | #define ADC_CFGR_AWD1SGL ((uint32_t)0x00400000) /*!< Eanble the watchdog 1 on a single channel or on all channels */ |
bogdanm | 86:04dd9b1680ae | 1010 | #define ADC_CFGR_AWD1EN ((uint32_t)0x00800000) /*!< ADC Analog watchdog 1 enable on regular Channels */ |
bogdanm | 86:04dd9b1680ae | 1011 | #define ADC_CFGR_JAWD1EN ((uint32_t)0x01000000) /*!< ADC Analog watchdog 1 enable on injected Channels */ |
bogdanm | 86:04dd9b1680ae | 1012 | #define ADC_CFGR_JAUTO ((uint32_t)0x02000000) /*!< ADC Automatic injected group conversion */ |
bogdanm | 86:04dd9b1680ae | 1013 | |
bogdanm | 86:04dd9b1680ae | 1014 | #define ADC_CFGR_AWD1CH ((uint32_t)0x7C000000) /*!< ADC Analog watchdog 1 Channel selection */ |
bogdanm | 86:04dd9b1680ae | 1015 | #define ADC_CFGR_AWD1CH_0 ((uint32_t)0x04000000) /*!< ADC AWD1CH bit 0 */ |
bogdanm | 86:04dd9b1680ae | 1016 | #define ADC_CFGR_AWD1CH_1 ((uint32_t)0x08000000) /*!< ADC AWD1CH bit 1 */ |
bogdanm | 86:04dd9b1680ae | 1017 | #define ADC_CFGR_AWD1CH_2 ((uint32_t)0x10000000) /*!< ADC AWD1CH bit 2 */ |
bogdanm | 86:04dd9b1680ae | 1018 | #define ADC_CFGR_AWD1CH_3 ((uint32_t)0x20000000) /*!< ADC AWD1CH bit 3 */ |
bogdanm | 86:04dd9b1680ae | 1019 | #define ADC_CFGR_AWD1CH_4 ((uint32_t)0x40000000) /*!< ADC AWD1CH bit 4 */ |
bogdanm | 86:04dd9b1680ae | 1020 | |
bogdanm | 86:04dd9b1680ae | 1021 | /******************** Bit definition for ADC_SMPR1 register ********************/ |
bogdanm | 86:04dd9b1680ae | 1022 | #define ADC_SMPR1_SMP0 ((uint32_t)0x00000007) /*!< ADC Channel 0 Sampling time selection */ |
bogdanm | 86:04dd9b1680ae | 1023 | #define ADC_SMPR1_SMP0_0 ((uint32_t)0x00000001) /*!< ADC SMP0 bit 0 */ |
bogdanm | 86:04dd9b1680ae | 1024 | #define ADC_SMPR1_SMP0_1 ((uint32_t)0x00000002) /*!< ADC SMP0 bit 1 */ |
bogdanm | 86:04dd9b1680ae | 1025 | #define ADC_SMPR1_SMP0_2 ((uint32_t)0x00000004) /*!< ADC SMP0 bit 2 */ |
bogdanm | 86:04dd9b1680ae | 1026 | |
bogdanm | 86:04dd9b1680ae | 1027 | #define ADC_SMPR1_SMP1 ((uint32_t)0x00000038) /*!< ADC Channel 1 Sampling time selection */ |
bogdanm | 86:04dd9b1680ae | 1028 | #define ADC_SMPR1_SMP1_0 ((uint32_t)0x00000008) /*!< ADC SMP1 bit 0 */ |
bogdanm | 86:04dd9b1680ae | 1029 | #define ADC_SMPR1_SMP1_1 ((uint32_t)0x00000010) /*!< ADC SMP1 bit 1 */ |
bogdanm | 86:04dd9b1680ae | 1030 | #define ADC_SMPR1_SMP1_2 ((uint32_t)0x00000020) /*!< ADC SMP1 bit 2 */ |
bogdanm | 86:04dd9b1680ae | 1031 | |
bogdanm | 86:04dd9b1680ae | 1032 | #define ADC_SMPR1_SMP2 ((uint32_t)0x000001C0) /*!< ADC Channel 2 Sampling time selection */ |
bogdanm | 86:04dd9b1680ae | 1033 | #define ADC_SMPR1_SMP2_0 ((uint32_t)0x00000040) /*!< ADC SMP2 bit 0 */ |
bogdanm | 86:04dd9b1680ae | 1034 | #define ADC_SMPR1_SMP2_1 ((uint32_t)0x00000080) /*!< ADC SMP2 bit 1 */ |
bogdanm | 86:04dd9b1680ae | 1035 | #define ADC_SMPR1_SMP2_2 ((uint32_t)0x00000100) /*!< ADC SMP2 bit 2 */ |
bogdanm | 86:04dd9b1680ae | 1036 | |
bogdanm | 86:04dd9b1680ae | 1037 | #define ADC_SMPR1_SMP3 ((uint32_t)0x00000E00) /*!< ADC Channel 3 Sampling time selection */ |
bogdanm | 86:04dd9b1680ae | 1038 | #define ADC_SMPR1_SMP3_0 ((uint32_t)0x00000200) /*!< ADC SMP3 bit 0 */ |
bogdanm | 86:04dd9b1680ae | 1039 | #define ADC_SMPR1_SMP3_1 ((uint32_t)0x00000400) /*!< ADC SMP3 bit 1 */ |
bogdanm | 86:04dd9b1680ae | 1040 | #define ADC_SMPR1_SMP3_2 ((uint32_t)0x00000800) /*!< ADC SMP3 bit 2 */ |
bogdanm | 86:04dd9b1680ae | 1041 | |
bogdanm | 86:04dd9b1680ae | 1042 | #define ADC_SMPR1_SMP4 ((uint32_t)0x00007000) /*!< ADC Channel 4 Sampling time selection */ |
bogdanm | 86:04dd9b1680ae | 1043 | #define ADC_SMPR1_SMP4_0 ((uint32_t)0x00001000) /*!< ADC SMP4 bit 0 */ |
bogdanm | 86:04dd9b1680ae | 1044 | #define ADC_SMPR1_SMP4_1 ((uint32_t)0x00002000) /*!< ADC SMP4 bit 1 */ |
bogdanm | 86:04dd9b1680ae | 1045 | #define ADC_SMPR1_SMP4_2 ((uint32_t)0x00004000) /*!< ADC SMP4 bit 2 */ |
bogdanm | 86:04dd9b1680ae | 1046 | |
bogdanm | 86:04dd9b1680ae | 1047 | #define ADC_SMPR1_SMP5 ((uint32_t)0x00038000) /*!< ADC Channel 5 Sampling time selection */ |
bogdanm | 86:04dd9b1680ae | 1048 | #define ADC_SMPR1_SMP5_0 ((uint32_t)0x00008000) /*!< ADC SMP5 bit 0 */ |
bogdanm | 86:04dd9b1680ae | 1049 | #define ADC_SMPR1_SMP5_1 ((uint32_t)0x00010000) /*!< ADC SMP5 bit 1 */ |
bogdanm | 86:04dd9b1680ae | 1050 | #define ADC_SMPR1_SMP5_2 ((uint32_t)0x00020000) /*!< ADC SMP5 bit 2 */ |
bogdanm | 86:04dd9b1680ae | 1051 | |
bogdanm | 86:04dd9b1680ae | 1052 | #define ADC_SMPR1_SMP6 ((uint32_t)0x001C0000) /*!< ADC Channel 6 Sampling time selection */ |
bogdanm | 86:04dd9b1680ae | 1053 | #define ADC_SMPR1_SMP6_0 ((uint32_t)0x00040000) /*!< ADC SMP6 bit 0 */ |
bogdanm | 86:04dd9b1680ae | 1054 | #define ADC_SMPR1_SMP6_1 ((uint32_t)0x00080000) /*!< ADC SMP6 bit 1 */ |
bogdanm | 86:04dd9b1680ae | 1055 | #define ADC_SMPR1_SMP6_2 ((uint32_t)0x00100000) /*!< ADC SMP6 bit 2 */ |
bogdanm | 86:04dd9b1680ae | 1056 | |
bogdanm | 86:04dd9b1680ae | 1057 | #define ADC_SMPR1_SMP7 ((uint32_t)0x00E00000) /*!< ADC Channel 7 Sampling time selection */ |
bogdanm | 86:04dd9b1680ae | 1058 | #define ADC_SMPR1_SMP7_0 ((uint32_t)0x00200000) /*!< ADC SMP7 bit 0 */ |
bogdanm | 86:04dd9b1680ae | 1059 | #define ADC_SMPR1_SMP7_1 ((uint32_t)0x00400000) /*!< ADC SMP7 bit 1 */ |
bogdanm | 86:04dd9b1680ae | 1060 | #define ADC_SMPR1_SMP7_2 ((uint32_t)0x00800000) /*!< ADC SMP7 bit 2 */ |
bogdanm | 86:04dd9b1680ae | 1061 | |
bogdanm | 86:04dd9b1680ae | 1062 | #define ADC_SMPR1_SMP8 ((uint32_t)0x07000000) /*!< ADC Channel 8 Sampling time selection */ |
bogdanm | 86:04dd9b1680ae | 1063 | #define ADC_SMPR1_SMP8_0 ((uint32_t)0x01000000) /*!< ADC SMP8 bit 0 */ |
bogdanm | 86:04dd9b1680ae | 1064 | #define ADC_SMPR1_SMP8_1 ((uint32_t)0x02000000) /*!< ADC SMP8 bit 1 */ |
bogdanm | 86:04dd9b1680ae | 1065 | #define ADC_SMPR1_SMP8_2 ((uint32_t)0x04000000) /*!< ADC SMP8 bit 2 */ |
bogdanm | 86:04dd9b1680ae | 1066 | |
bogdanm | 86:04dd9b1680ae | 1067 | #define ADC_SMPR1_SMP9 ((uint32_t)0x38000000) /*!< ADC Channel 9 Sampling time selection */ |
bogdanm | 86:04dd9b1680ae | 1068 | #define ADC_SMPR1_SMP9_0 ((uint32_t)0x08000000) /*!< ADC SMP9 bit 0 */ |
bogdanm | 86:04dd9b1680ae | 1069 | #define ADC_SMPR1_SMP9_1 ((uint32_t)0x10000000) /*!< ADC SMP9 bit 1 */ |
bogdanm | 86:04dd9b1680ae | 1070 | #define ADC_SMPR1_SMP9_2 ((uint32_t)0x20000000) /*!< ADC SMP9 bit 2 */ |
bogdanm | 86:04dd9b1680ae | 1071 | |
bogdanm | 86:04dd9b1680ae | 1072 | /******************** Bit definition for ADC_SMPR2 register ********************/ |
bogdanm | 86:04dd9b1680ae | 1073 | #define ADC_SMPR2_SMP10 ((uint32_t)0x00000007) /*!< ADC Channel 10 Sampling time selection */ |
bogdanm | 86:04dd9b1680ae | 1074 | #define ADC_SMPR2_SMP10_0 ((uint32_t)0x00000001) /*!< ADC SMP10 bit 0 */ |
bogdanm | 86:04dd9b1680ae | 1075 | #define ADC_SMPR2_SMP10_1 ((uint32_t)0x00000002) /*!< ADC SMP10 bit 1 */ |
bogdanm | 86:04dd9b1680ae | 1076 | #define ADC_SMPR2_SMP10_2 ((uint32_t)0x00000004) /*!< ADC SMP10 bit 2 */ |
bogdanm | 86:04dd9b1680ae | 1077 | |
bogdanm | 86:04dd9b1680ae | 1078 | #define ADC_SMPR2_SMP11 ((uint32_t)0x00000038) /*!< ADC Channel 11 Sampling time selection */ |
bogdanm | 86:04dd9b1680ae | 1079 | #define ADC_SMPR2_SMP11_0 ((uint32_t)0x00000008) /*!< ADC SMP11 bit 0 */ |
bogdanm | 86:04dd9b1680ae | 1080 | #define ADC_SMPR2_SMP11_1 ((uint32_t)0x00000010) /*!< ADC SMP11 bit 1 */ |
bogdanm | 86:04dd9b1680ae | 1081 | #define ADC_SMPR2_SMP11_2 ((uint32_t)0x00000020) /*!< ADC SMP11 bit 2 */ |
bogdanm | 86:04dd9b1680ae | 1082 | |
bogdanm | 86:04dd9b1680ae | 1083 | #define ADC_SMPR2_SMP12 ((uint32_t)0x000001C0) /*!< ADC Channel 12 Sampling time selection */ |
bogdanm | 86:04dd9b1680ae | 1084 | #define ADC_SMPR2_SMP12_0 ((uint32_t)0x00000040) /*!< ADC SMP12 bit 0 */ |
bogdanm | 86:04dd9b1680ae | 1085 | #define ADC_SMPR2_SMP12_1 ((uint32_t)0x00000080) /*!< ADC SMP12 bit 1 */ |
bogdanm | 86:04dd9b1680ae | 1086 | #define ADC_SMPR2_SMP12_2 ((uint32_t)0x00000100) /*!< ADC SMP12 bit 2 */ |
bogdanm | 86:04dd9b1680ae | 1087 | |
bogdanm | 86:04dd9b1680ae | 1088 | #define ADC_SMPR2_SMP13 ((uint32_t)0x00000E00) /*!< ADC Channel 13 Sampling time selection */ |
bogdanm | 86:04dd9b1680ae | 1089 | #define ADC_SMPR2_SMP13_0 ((uint32_t)0x00000200) /*!< ADC SMP13 bit 0 */ |
bogdanm | 86:04dd9b1680ae | 1090 | #define ADC_SMPR2_SMP13_1 ((uint32_t)0x00000400) /*!< ADC SMP13 bit 1 */ |
bogdanm | 86:04dd9b1680ae | 1091 | #define ADC_SMPR2_SMP13_2 ((uint32_t)0x00000800) /*!< ADC SMP13 bit 2 */ |
bogdanm | 86:04dd9b1680ae | 1092 | |
bogdanm | 86:04dd9b1680ae | 1093 | #define ADC_SMPR2_SMP14 ((uint32_t)0x00007000) /*!< ADC Channel 14 Sampling time selection */ |
bogdanm | 86:04dd9b1680ae | 1094 | #define ADC_SMPR2_SMP14_0 ((uint32_t)0x00001000) /*!< ADC SMP14 bit 0 */ |
bogdanm | 86:04dd9b1680ae | 1095 | #define ADC_SMPR2_SMP14_1 ((uint32_t)0x00002000) /*!< ADC SMP14 bit 1 */ |
bogdanm | 86:04dd9b1680ae | 1096 | #define ADC_SMPR2_SMP14_2 ((uint32_t)0x00004000) /*!< ADC SMP14 bit 2 */ |
bogdanm | 86:04dd9b1680ae | 1097 | |
bogdanm | 86:04dd9b1680ae | 1098 | #define ADC_SMPR2_SMP15 ((uint32_t)0x00038000) /*!< ADC Channel 15 Sampling time selection */ |
bogdanm | 86:04dd9b1680ae | 1099 | #define ADC_SMPR2_SMP15_0 ((uint32_t)0x00008000) /*!< ADC SMP15 bit 0 */ |
bogdanm | 86:04dd9b1680ae | 1100 | #define ADC_SMPR2_SMP15_1 ((uint32_t)0x00010000) /*!< ADC SMP15 bit 1 */ |
bogdanm | 86:04dd9b1680ae | 1101 | #define ADC_SMPR2_SMP15_2 ((uint32_t)0x00020000) /*!< ADC SMP15 bit 2 */ |
bogdanm | 86:04dd9b1680ae | 1102 | |
bogdanm | 86:04dd9b1680ae | 1103 | #define ADC_SMPR2_SMP16 ((uint32_t)0x001C0000) /*!< ADC Channel 16 Sampling time selection */ |
bogdanm | 86:04dd9b1680ae | 1104 | #define ADC_SMPR2_SMP16_0 ((uint32_t)0x00040000) /*!< ADC SMP16 bit 0 */ |
bogdanm | 86:04dd9b1680ae | 1105 | #define ADC_SMPR2_SMP16_1 ((uint32_t)0x00080000) /*!< ADC SMP16 bit 1 */ |
bogdanm | 86:04dd9b1680ae | 1106 | #define ADC_SMPR2_SMP16_2 ((uint32_t)0x00100000) /*!< ADC SMP16 bit 2 */ |
bogdanm | 86:04dd9b1680ae | 1107 | |
bogdanm | 86:04dd9b1680ae | 1108 | #define ADC_SMPR2_SMP17 ((uint32_t)0x00E00000) /*!< ADC Channel 17 Sampling time selection */ |
bogdanm | 86:04dd9b1680ae | 1109 | #define ADC_SMPR2_SMP17_0 ((uint32_t)0x00200000) /*!< ADC SMP17 bit 0 */ |
bogdanm | 86:04dd9b1680ae | 1110 | #define ADC_SMPR2_SMP17_1 ((uint32_t)0x00400000) /*!< ADC SMP17 bit 1 */ |
bogdanm | 86:04dd9b1680ae | 1111 | #define ADC_SMPR2_SMP17_2 ((uint32_t)0x00800000) /*!< ADC SMP17 bit 2 */ |
bogdanm | 86:04dd9b1680ae | 1112 | |
bogdanm | 86:04dd9b1680ae | 1113 | #define ADC_SMPR2_SMP18 ((uint32_t)0x07000000) /*!< ADC Channel 18 Sampling time selection */ |
bogdanm | 86:04dd9b1680ae | 1114 | #define ADC_SMPR2_SMP18_0 ((uint32_t)0x01000000) /*!< ADC SMP18 bit 0 */ |
bogdanm | 86:04dd9b1680ae | 1115 | #define ADC_SMPR2_SMP18_1 ((uint32_t)0x02000000) /*!< ADC SMP18 bit 1 */ |
bogdanm | 86:04dd9b1680ae | 1116 | #define ADC_SMPR2_SMP18_2 ((uint32_t)0x04000000) /*!< ADC SMP18 bit 2 */ |
bogdanm | 86:04dd9b1680ae | 1117 | |
bogdanm | 86:04dd9b1680ae | 1118 | /******************** Bit definition for ADC_TR1 register ********************/ |
bogdanm | 86:04dd9b1680ae | 1119 | #define ADC_TR1_LT1 ((uint32_t)0x00000FFF) /*!< ADC Analog watchdog 1 lower threshold */ |
bogdanm | 86:04dd9b1680ae | 1120 | #define ADC_TR1_LT1_0 ((uint32_t)0x00000001) /*!< ADC LT1 bit 0 */ |
bogdanm | 86:04dd9b1680ae | 1121 | #define ADC_TR1_LT1_1 ((uint32_t)0x00000002) /*!< ADC LT1 bit 1 */ |
bogdanm | 86:04dd9b1680ae | 1122 | #define ADC_TR1_LT1_2 ((uint32_t)0x00000004) /*!< ADC LT1 bit 2 */ |
bogdanm | 86:04dd9b1680ae | 1123 | #define ADC_TR1_LT1_3 ((uint32_t)0x00000008) /*!< ADC LT1 bit 3 */ |
bogdanm | 86:04dd9b1680ae | 1124 | #define ADC_TR1_LT1_4 ((uint32_t)0x00000010) /*!< ADC LT1 bit 4 */ |
bogdanm | 86:04dd9b1680ae | 1125 | #define ADC_TR1_LT1_5 ((uint32_t)0x00000020) /*!< ADC LT1 bit 5 */ |
bogdanm | 86:04dd9b1680ae | 1126 | #define ADC_TR1_LT1_6 ((uint32_t)0x00000040) /*!< ADC LT1 bit 6 */ |
bogdanm | 86:04dd9b1680ae | 1127 | #define ADC_TR1_LT1_7 ((uint32_t)0x00000080) /*!< ADC LT1 bit 7 */ |
bogdanm | 86:04dd9b1680ae | 1128 | #define ADC_TR1_LT1_8 ((uint32_t)0x00000100) /*!< ADC LT1 bit 8 */ |
bogdanm | 86:04dd9b1680ae | 1129 | #define ADC_TR1_LT1_9 ((uint32_t)0x00000200) /*!< ADC LT1 bit 9 */ |
bogdanm | 86:04dd9b1680ae | 1130 | #define ADC_TR1_LT1_10 ((uint32_t)0x00000400) /*!< ADC LT1 bit 10 */ |
bogdanm | 86:04dd9b1680ae | 1131 | #define ADC_TR1_LT1_11 ((uint32_t)0x00000800) /*!< ADC LT1 bit 11 */ |
bogdanm | 86:04dd9b1680ae | 1132 | |
bogdanm | 86:04dd9b1680ae | 1133 | #define ADC_TR1_HT1 ((uint32_t)0x0FFF0000) /*!< ADC Analog watchdog 1 higher threshold */ |
bogdanm | 86:04dd9b1680ae | 1134 | #define ADC_TR1_HT1_0 ((uint32_t)0x00010000) /*!< ADC HT1 bit 0 */ |
bogdanm | 86:04dd9b1680ae | 1135 | #define ADC_TR1_HT1_1 ((uint32_t)0x00020000) /*!< ADC HT1 bit 1 */ |
bogdanm | 86:04dd9b1680ae | 1136 | #define ADC_TR1_HT1_2 ((uint32_t)0x00040000) /*!< ADC HT1 bit 2 */ |
bogdanm | 86:04dd9b1680ae | 1137 | #define ADC_TR1_HT1_3 ((uint32_t)0x00080000) /*!< ADC HT1 bit 3 */ |
bogdanm | 86:04dd9b1680ae | 1138 | #define ADC_TR1_HT1_4 ((uint32_t)0x00100000) /*!< ADC HT1 bit 4 */ |
bogdanm | 86:04dd9b1680ae | 1139 | #define ADC_TR1_HT1_5 ((uint32_t)0x00200000) /*!< ADC HT1 bit 5 */ |
bogdanm | 86:04dd9b1680ae | 1140 | #define ADC_TR1_HT1_6 ((uint32_t)0x00400000) /*!< ADC HT1 bit 6 */ |
bogdanm | 86:04dd9b1680ae | 1141 | #define ADC_TR1_HT1_7 ((uint32_t)0x00800000) /*!< ADC HT1 bit 7 */ |
bogdanm | 86:04dd9b1680ae | 1142 | #define ADC_TR1_HT1_8 ((uint32_t)0x01000000) /*!< ADC HT1 bit 8 */ |
bogdanm | 86:04dd9b1680ae | 1143 | #define ADC_TR1_HT1_9 ((uint32_t)0x02000000) /*!< ADC HT1 bit 9 */ |
bogdanm | 86:04dd9b1680ae | 1144 | #define ADC_TR1_HT1_10 ((uint32_t)0x04000000) /*!< ADC HT1 bit 10 */ |
bogdanm | 86:04dd9b1680ae | 1145 | #define ADC_TR1_HT1_11 ((uint32_t)0x08000000) /*!< ADC HT1 bit 11 */ |
bogdanm | 86:04dd9b1680ae | 1146 | |
bogdanm | 86:04dd9b1680ae | 1147 | /******************** Bit definition for ADC_TR2 register ********************/ |
bogdanm | 86:04dd9b1680ae | 1148 | #define ADC_TR2_LT2 ((uint32_t)0x000000FF) /*!< ADC Analog watchdog 2 lower threshold */ |
bogdanm | 86:04dd9b1680ae | 1149 | #define ADC_TR2_LT2_0 ((uint32_t)0x00000001) /*!< ADC LT2 bit 0 */ |
bogdanm | 86:04dd9b1680ae | 1150 | #define ADC_TR2_LT2_1 ((uint32_t)0x00000002) /*!< ADC LT2 bit 1 */ |
bogdanm | 86:04dd9b1680ae | 1151 | #define ADC_TR2_LT2_2 ((uint32_t)0x00000004) /*!< ADC LT2 bit 2 */ |
bogdanm | 86:04dd9b1680ae | 1152 | #define ADC_TR2_LT2_3 ((uint32_t)0x00000008) /*!< ADC LT2 bit 3 */ |
bogdanm | 86:04dd9b1680ae | 1153 | #define ADC_TR2_LT2_4 ((uint32_t)0x00000010) /*!< ADC LT2 bit 4 */ |
bogdanm | 86:04dd9b1680ae | 1154 | #define ADC_TR2_LT2_5 ((uint32_t)0x00000020) /*!< ADC LT2 bit 5 */ |
bogdanm | 86:04dd9b1680ae | 1155 | #define ADC_TR2_LT2_6 ((uint32_t)0x00000040) /*!< ADC LT2 bit 6 */ |
bogdanm | 86:04dd9b1680ae | 1156 | #define ADC_TR2_LT2_7 ((uint32_t)0x00000080) /*!< ADC LT2 bit 7 */ |
bogdanm | 86:04dd9b1680ae | 1157 | |
bogdanm | 86:04dd9b1680ae | 1158 | #define ADC_TR2_HT2 ((uint32_t)0x00FF0000) /*!< ADC Analog watchdog 2 higher threshold */ |
bogdanm | 86:04dd9b1680ae | 1159 | #define ADC_TR2_HT2_0 ((uint32_t)0x00010000) /*!< ADC HT2 bit 0 */ |
bogdanm | 86:04dd9b1680ae | 1160 | #define ADC_TR2_HT2_1 ((uint32_t)0x00020000) /*!< ADC HT2 bit 1 */ |
bogdanm | 86:04dd9b1680ae | 1161 | #define ADC_TR2_HT2_2 ((uint32_t)0x00040000) /*!< ADC HT2 bit 2 */ |
bogdanm | 86:04dd9b1680ae | 1162 | #define ADC_TR2_HT2_3 ((uint32_t)0x00080000) /*!< ADC HT2 bit 3 */ |
bogdanm | 86:04dd9b1680ae | 1163 | #define ADC_TR2_HT2_4 ((uint32_t)0x00100000) /*!< ADC HT2 bit 4 */ |
bogdanm | 86:04dd9b1680ae | 1164 | #define ADC_TR2_HT2_5 ((uint32_t)0x00200000) /*!< ADC HT2 bit 5 */ |
bogdanm | 86:04dd9b1680ae | 1165 | #define ADC_TR2_HT2_6 ((uint32_t)0x00400000) /*!< ADC HT2 bit 6 */ |
bogdanm | 86:04dd9b1680ae | 1166 | #define ADC_TR2_HT2_7 ((uint32_t)0x00800000) /*!< ADC HT2 bit 7 */ |
bogdanm | 86:04dd9b1680ae | 1167 | |
bogdanm | 86:04dd9b1680ae | 1168 | /******************** Bit definition for ADC_TR3 register ********************/ |
bogdanm | 86:04dd9b1680ae | 1169 | #define ADC_TR3_LT3 ((uint32_t)0x000000FF) /*!< ADC Analog watchdog 3 lower threshold */ |
bogdanm | 86:04dd9b1680ae | 1170 | #define ADC_TR3_LT3_0 ((uint32_t)0x00000001) /*!< ADC LT3 bit 0 */ |
bogdanm | 86:04dd9b1680ae | 1171 | #define ADC_TR3_LT3_1 ((uint32_t)0x00000002) /*!< ADC LT3 bit 1 */ |
bogdanm | 86:04dd9b1680ae | 1172 | #define ADC_TR3_LT3_2 ((uint32_t)0x00000004) /*!< ADC LT3 bit 2 */ |
bogdanm | 86:04dd9b1680ae | 1173 | #define ADC_TR3_LT3_3 ((uint32_t)0x00000008) /*!< ADC LT3 bit 3 */ |
bogdanm | 86:04dd9b1680ae | 1174 | #define ADC_TR3_LT3_4 ((uint32_t)0x00000010) /*!< ADC LT3 bit 4 */ |
bogdanm | 86:04dd9b1680ae | 1175 | #define ADC_TR3_LT3_5 ((uint32_t)0x00000020) /*!< ADC LT3 bit 5 */ |
bogdanm | 86:04dd9b1680ae | 1176 | #define ADC_TR3_LT3_6 ((uint32_t)0x00000040) /*!< ADC LT3 bit 6 */ |
bogdanm | 86:04dd9b1680ae | 1177 | #define ADC_TR3_LT3_7 ((uint32_t)0x00000080) /*!< ADC LT3 bit 7 */ |
bogdanm | 86:04dd9b1680ae | 1178 | |
bogdanm | 86:04dd9b1680ae | 1179 | #define ADC_TR3_HT3 ((uint32_t)0x00FF0000) /*!< ADC Analog watchdog 3 higher threshold */ |
bogdanm | 86:04dd9b1680ae | 1180 | #define ADC_TR3_HT3_0 ((uint32_t)0x00010000) /*!< ADC HT3 bit 0 */ |
bogdanm | 86:04dd9b1680ae | 1181 | #define ADC_TR3_HT3_1 ((uint32_t)0x00020000) /*!< ADC HT3 bit 1 */ |
bogdanm | 86:04dd9b1680ae | 1182 | #define ADC_TR3_HT3_2 ((uint32_t)0x00040000) /*!< ADC HT3 bit 2 */ |
bogdanm | 86:04dd9b1680ae | 1183 | #define ADC_TR3_HT3_3 ((uint32_t)0x00080000) /*!< ADC HT3 bit 3 */ |
bogdanm | 86:04dd9b1680ae | 1184 | #define ADC_TR3_HT3_4 ((uint32_t)0x00100000) /*!< ADC HT3 bit 4 */ |
bogdanm | 86:04dd9b1680ae | 1185 | #define ADC_TR3_HT3_5 ((uint32_t)0x00200000) /*!< ADC HT3 bit 5 */ |
bogdanm | 86:04dd9b1680ae | 1186 | #define ADC_TR3_HT3_6 ((uint32_t)0x00400000) /*!< ADC HT3 bit 6 */ |
bogdanm | 86:04dd9b1680ae | 1187 | #define ADC_TR3_HT3_7 ((uint32_t)0x00800000) /*!< ADC HT3 bit 7 */ |
bogdanm | 86:04dd9b1680ae | 1188 | |
bogdanm | 86:04dd9b1680ae | 1189 | /******************** Bit definition for ADC_SQR1 register ********************/ |
bogdanm | 86:04dd9b1680ae | 1190 | #define ADC_SQR1_L ((uint32_t)0x0000000F) /*!< ADC regular channel sequence lenght */ |
bogdanm | 86:04dd9b1680ae | 1191 | #define ADC_SQR1_L_0 ((uint32_t)0x00000001) /*!< ADC L bit 0 */ |
bogdanm | 86:04dd9b1680ae | 1192 | #define ADC_SQR1_L_1 ((uint32_t)0x00000002) /*!< ADC L bit 1 */ |
bogdanm | 86:04dd9b1680ae | 1193 | #define ADC_SQR1_L_2 ((uint32_t)0x00000004) /*!< ADC L bit 2 */ |
bogdanm | 86:04dd9b1680ae | 1194 | #define ADC_SQR1_L_3 ((uint32_t)0x00000008) /*!< ADC L bit 3 */ |
bogdanm | 86:04dd9b1680ae | 1195 | |
bogdanm | 86:04dd9b1680ae | 1196 | #define ADC_SQR1_SQ1 ((uint32_t)0x000007C0) /*!< ADC 1st conversion in regular sequence */ |
bogdanm | 86:04dd9b1680ae | 1197 | #define ADC_SQR1_SQ1_0 ((uint32_t)0x00000040) /*!< ADC SQ1 bit 0 */ |
bogdanm | 86:04dd9b1680ae | 1198 | #define ADC_SQR1_SQ1_1 ((uint32_t)0x00000080) /*!< ADC SQ1 bit 1 */ |
bogdanm | 86:04dd9b1680ae | 1199 | #define ADC_SQR1_SQ1_2 ((uint32_t)0x00000100) /*!< ADC SQ1 bit 2 */ |
bogdanm | 86:04dd9b1680ae | 1200 | #define ADC_SQR1_SQ1_3 ((uint32_t)0x00000200) /*!< ADC SQ1 bit 3 */ |
bogdanm | 86:04dd9b1680ae | 1201 | #define ADC_SQR1_SQ1_4 ((uint32_t)0x00000400) /*!< ADC SQ1 bit 4 */ |
bogdanm | 86:04dd9b1680ae | 1202 | |
bogdanm | 86:04dd9b1680ae | 1203 | #define ADC_SQR1_SQ2 ((uint32_t)0x0001F000) /*!< ADC 2nd conversion in regular sequence */ |
bogdanm | 86:04dd9b1680ae | 1204 | #define ADC_SQR1_SQ2_0 ((uint32_t)0x00001000) /*!< ADC SQ2 bit 0 */ |
bogdanm | 86:04dd9b1680ae | 1205 | #define ADC_SQR1_SQ2_1 ((uint32_t)0x00002000) /*!< ADC SQ2 bit 1 */ |
bogdanm | 86:04dd9b1680ae | 1206 | #define ADC_SQR1_SQ2_2 ((uint32_t)0x00004000) /*!< ADC SQ2 bit 2 */ |
bogdanm | 86:04dd9b1680ae | 1207 | #define ADC_SQR1_SQ2_3 ((uint32_t)0x00008000) /*!< ADC SQ2 bit 3 */ |
bogdanm | 86:04dd9b1680ae | 1208 | #define ADC_SQR1_SQ2_4 ((uint32_t)0x00010000) /*!< ADC SQ2 bit 4 */ |
bogdanm | 86:04dd9b1680ae | 1209 | |
bogdanm | 86:04dd9b1680ae | 1210 | #define ADC_SQR1_SQ3 ((uint32_t)0x007C0000) /*!< ADC 3rd conversion in regular sequence */ |
bogdanm | 86:04dd9b1680ae | 1211 | #define ADC_SQR1_SQ3_0 ((uint32_t)0x00040000) /*!< ADC SQ3 bit 0 */ |
bogdanm | 86:04dd9b1680ae | 1212 | #define ADC_SQR1_SQ3_1 ((uint32_t)0x00080000) /*!< ADC SQ3 bit 1 */ |
bogdanm | 86:04dd9b1680ae | 1213 | #define ADC_SQR1_SQ3_2 ((uint32_t)0x00100000) /*!< ADC SQ3 bit 2 */ |
bogdanm | 86:04dd9b1680ae | 1214 | #define ADC_SQR1_SQ3_3 ((uint32_t)0x00200000) /*!< ADC SQ3 bit 3 */ |
bogdanm | 86:04dd9b1680ae | 1215 | #define ADC_SQR1_SQ3_4 ((uint32_t)0x00400000) /*!< ADC SQ3 bit 4 */ |
bogdanm | 86:04dd9b1680ae | 1216 | |
bogdanm | 86:04dd9b1680ae | 1217 | #define ADC_SQR1_SQ4 ((uint32_t)0x1F000000) /*!< ADC 4th conversion in regular sequence */ |
bogdanm | 86:04dd9b1680ae | 1218 | #define ADC_SQR1_SQ4_0 ((uint32_t)0x01000000) /*!< ADC SQ4 bit 0 */ |
bogdanm | 86:04dd9b1680ae | 1219 | #define ADC_SQR1_SQ4_1 ((uint32_t)0x02000000) /*!< ADC SQ4 bit 1 */ |
bogdanm | 86:04dd9b1680ae | 1220 | #define ADC_SQR1_SQ4_2 ((uint32_t)0x04000000) /*!< ADC SQ4 bit 2 */ |
bogdanm | 86:04dd9b1680ae | 1221 | #define ADC_SQR1_SQ4_3 ((uint32_t)0x08000000) /*!< ADC SQ4 bit 3 */ |
bogdanm | 86:04dd9b1680ae | 1222 | #define ADC_SQR1_SQ4_4 ((uint32_t)0x10000000) /*!< ADC SQ4 bit 4 */ |
bogdanm | 86:04dd9b1680ae | 1223 | |
bogdanm | 86:04dd9b1680ae | 1224 | /******************** Bit definition for ADC_SQR2 register ********************/ |
bogdanm | 86:04dd9b1680ae | 1225 | #define ADC_SQR2_SQ5 ((uint32_t)0x0000001F) /*!< ADC 5th conversion in regular sequence */ |
bogdanm | 86:04dd9b1680ae | 1226 | #define ADC_SQR2_SQ5_0 ((uint32_t)0x00000001) /*!< ADC SQ5 bit 0 */ |
bogdanm | 86:04dd9b1680ae | 1227 | #define ADC_SQR2_SQ5_1 ((uint32_t)0x00000002) /*!< ADC SQ5 bit 1 */ |
bogdanm | 86:04dd9b1680ae | 1228 | #define ADC_SQR2_SQ5_2 ((uint32_t)0x00000004) /*!< ADC SQ5 bit 2 */ |
bogdanm | 86:04dd9b1680ae | 1229 | #define ADC_SQR2_SQ5_3 ((uint32_t)0x00000008) /*!< ADC SQ5 bit 3 */ |
bogdanm | 86:04dd9b1680ae | 1230 | #define ADC_SQR2_SQ5_4 ((uint32_t)0x00000010) /*!< ADC SQ5 bit 4 */ |
bogdanm | 86:04dd9b1680ae | 1231 | |
bogdanm | 86:04dd9b1680ae | 1232 | #define ADC_SQR2_SQ6 ((uint32_t)0x000007C0) /*!< ADC 6th conversion in regular sequence */ |
bogdanm | 86:04dd9b1680ae | 1233 | #define ADC_SQR2_SQ6_0 ((uint32_t)0x00000040) /*!< ADC SQ6 bit 0 */ |
bogdanm | 86:04dd9b1680ae | 1234 | #define ADC_SQR2_SQ6_1 ((uint32_t)0x00000080) /*!< ADC SQ6 bit 1 */ |
bogdanm | 86:04dd9b1680ae | 1235 | #define ADC_SQR2_SQ6_2 ((uint32_t)0x00000100) /*!< ADC SQ6 bit 2 */ |
bogdanm | 86:04dd9b1680ae | 1236 | #define ADC_SQR2_SQ6_3 ((uint32_t)0x00000200) /*!< ADC SQ6 bit 3 */ |
bogdanm | 86:04dd9b1680ae | 1237 | #define ADC_SQR2_SQ6_4 ((uint32_t)0x00000400) /*!< ADC SQ6 bit 4 */ |
bogdanm | 86:04dd9b1680ae | 1238 | |
bogdanm | 86:04dd9b1680ae | 1239 | #define ADC_SQR2_SQ7 ((uint32_t)0x0001F000) /*!< ADC 7th conversion in regular sequence */ |
bogdanm | 86:04dd9b1680ae | 1240 | #define ADC_SQR2_SQ7_0 ((uint32_t)0x00001000) /*!< ADC SQ7 bit 0 */ |
bogdanm | 86:04dd9b1680ae | 1241 | #define ADC_SQR2_SQ7_1 ((uint32_t)0x00002000) /*!< ADC SQ7 bit 1 */ |
bogdanm | 86:04dd9b1680ae | 1242 | #define ADC_SQR2_SQ7_2 ((uint32_t)0x00004000) /*!< ADC SQ7 bit 2 */ |
bogdanm | 86:04dd9b1680ae | 1243 | #define ADC_SQR2_SQ7_3 ((uint32_t)0x00008000) /*!< ADC SQ7 bit 3 */ |
bogdanm | 86:04dd9b1680ae | 1244 | #define ADC_SQR2_SQ7_4 ((uint32_t)0x00010000) /*!< ADC SQ7 bit 4 */ |
bogdanm | 86:04dd9b1680ae | 1245 | |
bogdanm | 86:04dd9b1680ae | 1246 | #define ADC_SQR2_SQ8 ((uint32_t)0x007C0000) /*!< ADC 8th conversion in regular sequence */ |
bogdanm | 86:04dd9b1680ae | 1247 | #define ADC_SQR2_SQ8_0 ((uint32_t)0x00040000) /*!< ADC SQ8 bit 0 */ |
bogdanm | 86:04dd9b1680ae | 1248 | #define ADC_SQR2_SQ8_1 ((uint32_t)0x00080000) /*!< ADC SQ8 bit 1 */ |
bogdanm | 86:04dd9b1680ae | 1249 | #define ADC_SQR2_SQ8_2 ((uint32_t)0x00100000) /*!< ADC SQ8 bit 2 */ |
bogdanm | 86:04dd9b1680ae | 1250 | #define ADC_SQR2_SQ8_3 ((uint32_t)0x00200000) /*!< ADC SQ8 bit 3 */ |
bogdanm | 86:04dd9b1680ae | 1251 | #define ADC_SQR2_SQ8_4 ((uint32_t)0x00400000) /*!< ADC SQ8 bit 4 */ |
bogdanm | 86:04dd9b1680ae | 1252 | |
bogdanm | 86:04dd9b1680ae | 1253 | #define ADC_SQR2_SQ9 ((uint32_t)0x1F000000) /*!< ADC 9th conversion in regular sequence */ |
bogdanm | 86:04dd9b1680ae | 1254 | #define ADC_SQR2_SQ9_0 ((uint32_t)0x01000000) /*!< ADC SQ9 bit 0 */ |
bogdanm | 86:04dd9b1680ae | 1255 | #define ADC_SQR2_SQ9_1 ((uint32_t)0x02000000) /*!< ADC SQ9 bit 1 */ |
bogdanm | 86:04dd9b1680ae | 1256 | #define ADC_SQR2_SQ9_2 ((uint32_t)0x04000000) /*!< ADC SQ9 bit 2 */ |
bogdanm | 86:04dd9b1680ae | 1257 | #define ADC_SQR2_SQ9_3 ((uint32_t)0x08000000) /*!< ADC SQ9 bit 3 */ |
bogdanm | 86:04dd9b1680ae | 1258 | #define ADC_SQR2_SQ9_4 ((uint32_t)0x10000000) /*!< ADC SQ9 bit 4 */ |
bogdanm | 86:04dd9b1680ae | 1259 | |
bogdanm | 86:04dd9b1680ae | 1260 | /******************** Bit definition for ADC_SQR3 register ********************/ |
bogdanm | 86:04dd9b1680ae | 1261 | #define ADC_SQR3_SQ10 ((uint32_t)0x0000001F) /*!< ADC 10th conversion in regular sequence */ |
bogdanm | 86:04dd9b1680ae | 1262 | #define ADC_SQR3_SQ10_0 ((uint32_t)0x00000001) /*!< ADC SQ10 bit 0 */ |
bogdanm | 86:04dd9b1680ae | 1263 | #define ADC_SQR3_SQ10_1 ((uint32_t)0x00000002) /*!< ADC SQ10 bit 1 */ |
bogdanm | 86:04dd9b1680ae | 1264 | #define ADC_SQR3_SQ10_2 ((uint32_t)0x00000004) /*!< ADC SQ10 bit 2 */ |
bogdanm | 86:04dd9b1680ae | 1265 | #define ADC_SQR3_SQ10_3 ((uint32_t)0x00000008) /*!< ADC SQ10 bit 3 */ |
bogdanm | 86:04dd9b1680ae | 1266 | #define ADC_SQR3_SQ10_4 ((uint32_t)0x00000010) /*!< ADC SQ10 bit 4 */ |
bogdanm | 86:04dd9b1680ae | 1267 | |
bogdanm | 86:04dd9b1680ae | 1268 | #define ADC_SQR3_SQ11 ((uint32_t)0x000007C0) /*!< ADC 11th conversion in regular sequence */ |
bogdanm | 86:04dd9b1680ae | 1269 | #define ADC_SQR3_SQ11_0 ((uint32_t)0x00000040) /*!< ADC SQ11 bit 0 */ |
bogdanm | 86:04dd9b1680ae | 1270 | #define ADC_SQR3_SQ11_1 ((uint32_t)0x00000080) /*!< ADC SQ11 bit 1 */ |
bogdanm | 86:04dd9b1680ae | 1271 | #define ADC_SQR3_SQ11_2 ((uint32_t)0x00000100) /*!< ADC SQ11 bit 2 */ |
bogdanm | 86:04dd9b1680ae | 1272 | #define ADC_SQR3_SQ11_3 ((uint32_t)0x00000200) /*!< ADC SQ11 bit 3 */ |
bogdanm | 86:04dd9b1680ae | 1273 | #define ADC_SQR3_SQ11_4 ((uint32_t)0x00000400) /*!< ADC SQ11 bit 4 */ |
bogdanm | 86:04dd9b1680ae | 1274 | |
bogdanm | 86:04dd9b1680ae | 1275 | #define ADC_SQR3_SQ12 ((uint32_t)0x0001F000) /*!< ADC 12th conversion in regular sequence */ |
bogdanm | 86:04dd9b1680ae | 1276 | #define ADC_SQR3_SQ12_0 ((uint32_t)0x00001000) /*!< ADC SQ12 bit 0 */ |
bogdanm | 86:04dd9b1680ae | 1277 | #define ADC_SQR3_SQ12_1 ((uint32_t)0x00002000) /*!< ADC SQ12 bit 1 */ |
bogdanm | 86:04dd9b1680ae | 1278 | #define ADC_SQR3_SQ12_2 ((uint32_t)0x00004000) /*!< ADC SQ12 bit 2 */ |
bogdanm | 86:04dd9b1680ae | 1279 | #define ADC_SQR3_SQ12_3 ((uint32_t)0x00008000) /*!< ADC SQ12 bit 3 */ |
bogdanm | 86:04dd9b1680ae | 1280 | #define ADC_SQR3_SQ12_4 ((uint32_t)0x00010000) /*!< ADC SQ12 bit 4 */ |
bogdanm | 86:04dd9b1680ae | 1281 | |
bogdanm | 86:04dd9b1680ae | 1282 | #define ADC_SQR3_SQ13 ((uint32_t)0x007C0000) /*!< ADC 13th conversion in regular sequence */ |
bogdanm | 86:04dd9b1680ae | 1283 | #define ADC_SQR3_SQ13_0 ((uint32_t)0x00040000) /*!< ADC SQ13 bit 0 */ |
bogdanm | 86:04dd9b1680ae | 1284 | #define ADC_SQR3_SQ13_1 ((uint32_t)0x00080000) /*!< ADC SQ13 bit 1 */ |
bogdanm | 86:04dd9b1680ae | 1285 | #define ADC_SQR3_SQ13_2 ((uint32_t)0x00100000) /*!< ADC SQ13 bit 2 */ |
bogdanm | 86:04dd9b1680ae | 1286 | #define ADC_SQR3_SQ13_3 ((uint32_t)0x00200000) /*!< ADC SQ13 bit 3 */ |
bogdanm | 86:04dd9b1680ae | 1287 | #define ADC_SQR3_SQ13_4 ((uint32_t)0x00400000) /*!< ADC SQ13 bit 4 */ |
bogdanm | 86:04dd9b1680ae | 1288 | |
bogdanm | 86:04dd9b1680ae | 1289 | #define ADC_SQR3_SQ14 ((uint32_t)0x1F000000) /*!< ADC 14th conversion in regular sequence */ |
bogdanm | 86:04dd9b1680ae | 1290 | #define ADC_SQR3_SQ14_0 ((uint32_t)0x01000000) /*!< ADC SQ14 bit 0 */ |
bogdanm | 86:04dd9b1680ae | 1291 | #define ADC_SQR3_SQ14_1 ((uint32_t)0x02000000) /*!< ADC SQ14 bit 1 */ |
bogdanm | 86:04dd9b1680ae | 1292 | #define ADC_SQR3_SQ14_2 ((uint32_t)0x04000000) /*!< ADC SQ14 bit 2 */ |
bogdanm | 86:04dd9b1680ae | 1293 | #define ADC_SQR3_SQ14_3 ((uint32_t)0x08000000) /*!< ADC SQ14 bit 3 */ |
bogdanm | 86:04dd9b1680ae | 1294 | #define ADC_SQR3_SQ14_4 ((uint32_t)0x10000000) /*!< ADC SQ14 bit 4 */ |
bogdanm | 86:04dd9b1680ae | 1295 | |
bogdanm | 86:04dd9b1680ae | 1296 | /******************** Bit definition for ADC_SQR4 register ********************/ |
bogdanm | 86:04dd9b1680ae | 1297 | #define ADC_SQR4_SQ15 ((uint32_t)0x0000001F) /*!< ADC 15th conversion in regular sequence */ |
bogdanm | 86:04dd9b1680ae | 1298 | #define ADC_SQR4_SQ15_0 ((uint32_t)0x00000001) /*!< ADC SQ15 bit 0 */ |
bogdanm | 86:04dd9b1680ae | 1299 | #define ADC_SQR4_SQ15_1 ((uint32_t)0x00000002) /*!< ADC SQ15 bit 1 */ |
bogdanm | 86:04dd9b1680ae | 1300 | #define ADC_SQR4_SQ15_2 ((uint32_t)0x00000004) /*!< ADC SQ15 bit 2 */ |
bogdanm | 86:04dd9b1680ae | 1301 | #define ADC_SQR4_SQ15_3 ((uint32_t)0x00000008) /*!< ADC SQ15 bit 3 */ |
bogdanm | 86:04dd9b1680ae | 1302 | #define ADC_SQR4_SQ15_4 ((uint32_t)0x00000010) /*!< ADC SQ105 bit 4 */ |
bogdanm | 86:04dd9b1680ae | 1303 | |
bogdanm | 86:04dd9b1680ae | 1304 | #define ADC_SQR4_SQ16 ((uint32_t)0x000007C0) /*!< ADC 16th conversion in regular sequence */ |
bogdanm | 86:04dd9b1680ae | 1305 | #define ADC_SQR4_SQ16_0 ((uint32_t)0x00000040) /*!< ADC SQ16 bit 0 */ |
bogdanm | 86:04dd9b1680ae | 1306 | #define ADC_SQR4_SQ16_1 ((uint32_t)0x00000080) /*!< ADC SQ16 bit 1 */ |
bogdanm | 86:04dd9b1680ae | 1307 | #define ADC_SQR4_SQ16_2 ((uint32_t)0x00000100) /*!< ADC SQ16 bit 2 */ |
bogdanm | 86:04dd9b1680ae | 1308 | #define ADC_SQR4_SQ16_3 ((uint32_t)0x00000200) /*!< ADC SQ16 bit 3 */ |
bogdanm | 86:04dd9b1680ae | 1309 | #define ADC_SQR4_SQ16_4 ((uint32_t)0x00000400) /*!< ADC SQ16 bit 4 */ |
bogdanm | 86:04dd9b1680ae | 1310 | /******************** Bit definition for ADC_DR register ********************/ |
bogdanm | 86:04dd9b1680ae | 1311 | #define ADC_DR_RDATA ((uint32_t)0x0000FFFF) /*!< ADC regular Data converted */ |
bogdanm | 86:04dd9b1680ae | 1312 | #define ADC_DR_RDATA_0 ((uint32_t)0x00000001) /*!< ADC RDATA bit 0 */ |
bogdanm | 86:04dd9b1680ae | 1313 | #define ADC_DR_RDATA_1 ((uint32_t)0x00000002) /*!< ADC RDATA bit 1 */ |
bogdanm | 86:04dd9b1680ae | 1314 | #define ADC_DR_RDATA_2 ((uint32_t)0x00000004) /*!< ADC RDATA bit 2 */ |
bogdanm | 86:04dd9b1680ae | 1315 | #define ADC_DR_RDATA_3 ((uint32_t)0x00000008) /*!< ADC RDATA bit 3 */ |
bogdanm | 86:04dd9b1680ae | 1316 | #define ADC_DR_RDATA_4 ((uint32_t)0x00000010) /*!< ADC RDATA bit 4 */ |
bogdanm | 86:04dd9b1680ae | 1317 | #define ADC_DR_RDATA_5 ((uint32_t)0x00000020) /*!< ADC RDATA bit 5 */ |
bogdanm | 86:04dd9b1680ae | 1318 | #define ADC_DR_RDATA_6 ((uint32_t)0x00000040) /*!< ADC RDATA bit 6 */ |
bogdanm | 86:04dd9b1680ae | 1319 | #define ADC_DR_RDATA_7 ((uint32_t)0x00000080) /*!< ADC RDATA bit 7 */ |
bogdanm | 86:04dd9b1680ae | 1320 | #define ADC_DR_RDATA_8 ((uint32_t)0x00000100) /*!< ADC RDATA bit 8 */ |
bogdanm | 86:04dd9b1680ae | 1321 | #define ADC_DR_RDATA_9 ((uint32_t)0x00000200) /*!< ADC RDATA bit 9 */ |
bogdanm | 86:04dd9b1680ae | 1322 | #define ADC_DR_RDATA_10 ((uint32_t)0x00000400) /*!< ADC RDATA bit 10 */ |
bogdanm | 86:04dd9b1680ae | 1323 | #define ADC_DR_RDATA_11 ((uint32_t)0x00000800) /*!< ADC RDATA bit 11 */ |
bogdanm | 86:04dd9b1680ae | 1324 | #define ADC_DR_RDATA_12 ((uint32_t)0x00001000) /*!< ADC RDATA bit 12 */ |
bogdanm | 86:04dd9b1680ae | 1325 | #define ADC_DR_RDATA_13 ((uint32_t)0x00002000) /*!< ADC RDATA bit 13 */ |
bogdanm | 86:04dd9b1680ae | 1326 | #define ADC_DR_RDATA_14 ((uint32_t)0x00004000) /*!< ADC RDATA bit 14 */ |
bogdanm | 86:04dd9b1680ae | 1327 | #define ADC_DR_RDATA_15 ((uint32_t)0x00008000) /*!< ADC RDATA bit 15 */ |
bogdanm | 86:04dd9b1680ae | 1328 | |
bogdanm | 86:04dd9b1680ae | 1329 | /******************** Bit definition for ADC_JSQR register ********************/ |
bogdanm | 86:04dd9b1680ae | 1330 | #define ADC_JSQR_JL ((uint32_t)0x00000003) /*!< ADC injected channel sequence length */ |
bogdanm | 86:04dd9b1680ae | 1331 | #define ADC_JSQR_JL_0 ((uint32_t)0x00000001) /*!< ADC JL bit 0 */ |
bogdanm | 86:04dd9b1680ae | 1332 | #define ADC_JSQR_JL_1 ((uint32_t)0x00000002) /*!< ADC JL bit 1 */ |
bogdanm | 86:04dd9b1680ae | 1333 | |
bogdanm | 86:04dd9b1680ae | 1334 | #define ADC_JSQR_JEXTSEL ((uint32_t)0x0000003C) /*!< ADC external trigger selection for injected group */ |
bogdanm | 86:04dd9b1680ae | 1335 | #define ADC_JSQR_JEXTSEL_0 ((uint32_t)0x00000004) /*!< ADC JEXTSEL bit 0 */ |
bogdanm | 86:04dd9b1680ae | 1336 | #define ADC_JSQR_JEXTSEL_1 ((uint32_t)0x00000008) /*!< ADC JEXTSEL bit 1 */ |
bogdanm | 86:04dd9b1680ae | 1337 | #define ADC_JSQR_JEXTSEL_2 ((uint32_t)0x00000010) /*!< ADC JEXTSEL bit 2 */ |
bogdanm | 86:04dd9b1680ae | 1338 | #define ADC_JSQR_JEXTSEL_3 ((uint32_t)0x00000020) /*!< ADC JEXTSEL bit 3 */ |
bogdanm | 86:04dd9b1680ae | 1339 | |
bogdanm | 86:04dd9b1680ae | 1340 | #define ADC_JSQR_JEXTEN ((uint32_t)0x000000C0) /*!< ADC external trigger enable and polarity selection for injected channels */ |
bogdanm | 86:04dd9b1680ae | 1341 | #define ADC_JSQR_JEXTEN_0 ((uint32_t)0x00000040) /*!< ADC JEXTEN bit 0 */ |
bogdanm | 86:04dd9b1680ae | 1342 | #define ADC_JSQR_JEXTEN_1 ((uint32_t)0x00000080) /*!< ADC JEXTEN bit 1 */ |
bogdanm | 86:04dd9b1680ae | 1343 | |
bogdanm | 86:04dd9b1680ae | 1344 | #define ADC_JSQR_JSQ1 ((uint32_t)0x00001F00) /*!< ADC 1st conversion in injected sequence */ |
bogdanm | 86:04dd9b1680ae | 1345 | #define ADC_JSQR_JSQ1_0 ((uint32_t)0x00000100) /*!< ADC JSQ1 bit 0 */ |
bogdanm | 86:04dd9b1680ae | 1346 | #define ADC_JSQR_JSQ1_1 ((uint32_t)0x00000200) /*!< ADC JSQ1 bit 1 */ |
bogdanm | 86:04dd9b1680ae | 1347 | #define ADC_JSQR_JSQ1_2 ((uint32_t)0x00000400) /*!< ADC JSQ1 bit 2 */ |
bogdanm | 86:04dd9b1680ae | 1348 | #define ADC_JSQR_JSQ1_3 ((uint32_t)0x00000800) /*!< ADC JSQ1 bit 3 */ |
bogdanm | 86:04dd9b1680ae | 1349 | #define ADC_JSQR_JSQ1_4 ((uint32_t)0x00001000) /*!< ADC JSQ1 bit 4 */ |
bogdanm | 86:04dd9b1680ae | 1350 | |
bogdanm | 86:04dd9b1680ae | 1351 | #define ADC_JSQR_JSQ2 ((uint32_t)0x0007C000) /*!< ADC 2nd conversion in injected sequence */ |
bogdanm | 86:04dd9b1680ae | 1352 | #define ADC_JSQR_JSQ2_0 ((uint32_t)0x00004000) /*!< ADC JSQ2 bit 0 */ |
bogdanm | 86:04dd9b1680ae | 1353 | #define ADC_JSQR_JSQ2_1 ((uint32_t)0x00008000) /*!< ADC JSQ2 bit 1 */ |
bogdanm | 86:04dd9b1680ae | 1354 | #define ADC_JSQR_JSQ2_2 ((uint32_t)0x00010000) /*!< ADC JSQ2 bit 2 */ |
bogdanm | 86:04dd9b1680ae | 1355 | #define ADC_JSQR_JSQ2_3 ((uint32_t)0x00020000) /*!< ADC JSQ2 bit 3 */ |
bogdanm | 86:04dd9b1680ae | 1356 | #define ADC_JSQR_JSQ2_4 ((uint32_t)0x00040000) /*!< ADC JSQ2 bit 4 */ |
bogdanm | 86:04dd9b1680ae | 1357 | |
bogdanm | 86:04dd9b1680ae | 1358 | #define ADC_JSQR_JSQ3 ((uint32_t)0x01F00000) /*!< ADC 3rd conversion in injected sequence */ |
bogdanm | 86:04dd9b1680ae | 1359 | #define ADC_JSQR_JSQ3_0 ((uint32_t)0x00100000) /*!< ADC JSQ3 bit 0 */ |
bogdanm | 86:04dd9b1680ae | 1360 | #define ADC_JSQR_JSQ3_1 ((uint32_t)0x00200000) /*!< ADC JSQ3 bit 1 */ |
bogdanm | 86:04dd9b1680ae | 1361 | #define ADC_JSQR_JSQ3_2 ((uint32_t)0x00400000) /*!< ADC JSQ3 bit 2 */ |
bogdanm | 86:04dd9b1680ae | 1362 | #define ADC_JSQR_JSQ3_3 ((uint32_t)0x00800000) /*!< ADC JSQ3 bit 3 */ |
bogdanm | 86:04dd9b1680ae | 1363 | #define ADC_JSQR_JSQ3_4 ((uint32_t)0x01000000) /*!< ADC JSQ3 bit 4 */ |
bogdanm | 86:04dd9b1680ae | 1364 | |
bogdanm | 86:04dd9b1680ae | 1365 | #define ADC_JSQR_JSQ4 ((uint32_t)0x7C000000) /*!< ADC 4th conversion in injected sequence */ |
bogdanm | 86:04dd9b1680ae | 1366 | #define ADC_JSQR_JSQ4_0 ((uint32_t)0x04000000) /*!< ADC JSQ4 bit 0 */ |
bogdanm | 86:04dd9b1680ae | 1367 | #define ADC_JSQR_JSQ4_1 ((uint32_t)0x08000000) /*!< ADC JSQ4 bit 1 */ |
bogdanm | 86:04dd9b1680ae | 1368 | #define ADC_JSQR_JSQ4_2 ((uint32_t)0x10000000) /*!< ADC JSQ4 bit 2 */ |
bogdanm | 86:04dd9b1680ae | 1369 | #define ADC_JSQR_JSQ4_3 ((uint32_t)0x20000000) /*!< ADC JSQ4 bit 3 */ |
bogdanm | 86:04dd9b1680ae | 1370 | #define ADC_JSQR_JSQ4_4 ((uint32_t)0x40000000) /*!< ADC JSQ4 bit 4 */ |
bogdanm | 86:04dd9b1680ae | 1371 | |
bogdanm | 86:04dd9b1680ae | 1372 | /******************** Bit definition for ADC_OFR1 register ********************/ |
bogdanm | 86:04dd9b1680ae | 1373 | #define ADC_OFR1_OFFSET1 ((uint32_t)0x00000FFF) /*!< ADC data offset 1 for channel programmed into bits OFFSET1_CH[4:0] */ |
bogdanm | 86:04dd9b1680ae | 1374 | #define ADC_OFR1_OFFSET1_0 ((uint32_t)0x00000001) /*!< ADC OFFSET1 bit 0 */ |
bogdanm | 86:04dd9b1680ae | 1375 | #define ADC_OFR1_OFFSET1_1 ((uint32_t)0x00000002) /*!< ADC OFFSET1 bit 1 */ |
bogdanm | 86:04dd9b1680ae | 1376 | #define ADC_OFR1_OFFSET1_2 ((uint32_t)0x00000004) /*!< ADC OFFSET1 bit 2 */ |
bogdanm | 86:04dd9b1680ae | 1377 | #define ADC_OFR1_OFFSET1_3 ((uint32_t)0x00000008) /*!< ADC OFFSET1 bit 3 */ |
bogdanm | 86:04dd9b1680ae | 1378 | #define ADC_OFR1_OFFSET1_4 ((uint32_t)0x00000010) /*!< ADC OFFSET1 bit 4 */ |
bogdanm | 86:04dd9b1680ae | 1379 | #define ADC_OFR1_OFFSET1_5 ((uint32_t)0x00000020) /*!< ADC OFFSET1 bit 5 */ |
bogdanm | 86:04dd9b1680ae | 1380 | #define ADC_OFR1_OFFSET1_6 ((uint32_t)0x00000040) /*!< ADC OFFSET1 bit 6 */ |
bogdanm | 86:04dd9b1680ae | 1381 | #define ADC_OFR1_OFFSET1_7 ((uint32_t)0x00000080) /*!< ADC OFFSET1 bit 7 */ |
bogdanm | 86:04dd9b1680ae | 1382 | #define ADC_OFR1_OFFSET1_8 ((uint32_t)0x00000100) /*!< ADC OFFSET1 bit 8 */ |
bogdanm | 86:04dd9b1680ae | 1383 | #define ADC_OFR1_OFFSET1_9 ((uint32_t)0x00000200) /*!< ADC OFFSET1 bit 9 */ |
bogdanm | 86:04dd9b1680ae | 1384 | #define ADC_OFR1_OFFSET1_10 ((uint32_t)0x00000400) /*!< ADC OFFSET1 bit 10 */ |
bogdanm | 86:04dd9b1680ae | 1385 | #define ADC_OFR1_OFFSET1_11 ((uint32_t)0x00000800) /*!< ADC OFFSET1 bit 11 */ |
bogdanm | 86:04dd9b1680ae | 1386 | |
bogdanm | 86:04dd9b1680ae | 1387 | #define ADC_OFR1_OFFSET1_CH ((uint32_t)0x7C000000) /*!< ADC Channel selection for the data offset 1 */ |
bogdanm | 86:04dd9b1680ae | 1388 | #define ADC_OFR1_OFFSET1_CH_0 ((uint32_t)0x04000000) /*!< ADC OFFSET1_CH bit 0 */ |
bogdanm | 86:04dd9b1680ae | 1389 | #define ADC_OFR1_OFFSET1_CH_1 ((uint32_t)0x08000000) /*!< ADC OFFSET1_CH bit 1 */ |
bogdanm | 86:04dd9b1680ae | 1390 | #define ADC_OFR1_OFFSET1_CH_2 ((uint32_t)0x10000000) /*!< ADC OFFSET1_CH bit 2 */ |
bogdanm | 86:04dd9b1680ae | 1391 | #define ADC_OFR1_OFFSET1_CH_3 ((uint32_t)0x20000000) /*!< ADC OFFSET1_CH bit 3 */ |
bogdanm | 86:04dd9b1680ae | 1392 | #define ADC_OFR1_OFFSET1_CH_4 ((uint32_t)0x40000000) /*!< ADC OFFSET1_CH bit 4 */ |
bogdanm | 86:04dd9b1680ae | 1393 | |
bogdanm | 86:04dd9b1680ae | 1394 | #define ADC_OFR1_OFFSET1_EN ((uint32_t)0x80000000) /*!< ADC offset 1 enable */ |
bogdanm | 86:04dd9b1680ae | 1395 | |
bogdanm | 86:04dd9b1680ae | 1396 | /******************** Bit definition for ADC_OFR2 register ********************/ |
bogdanm | 86:04dd9b1680ae | 1397 | #define ADC_OFR2_OFFSET2 ((uint32_t)0x00000FFF) /*!< ADC data offset 2 for channel programmed into bits OFFSET2_CH[4:0] */ |
bogdanm | 86:04dd9b1680ae | 1398 | #define ADC_OFR2_OFFSET2_0 ((uint32_t)0x00000001) /*!< ADC OFFSET2 bit 0 */ |
bogdanm | 86:04dd9b1680ae | 1399 | #define ADC_OFR2_OFFSET2_1 ((uint32_t)0x00000002) /*!< ADC OFFSET2 bit 1 */ |
bogdanm | 86:04dd9b1680ae | 1400 | #define ADC_OFR2_OFFSET2_2 ((uint32_t)0x00000004) /*!< ADC OFFSET2 bit 2 */ |
bogdanm | 86:04dd9b1680ae | 1401 | #define ADC_OFR2_OFFSET2_3 ((uint32_t)0x00000008) /*!< ADC OFFSET2 bit 3 */ |
bogdanm | 86:04dd9b1680ae | 1402 | #define ADC_OFR2_OFFSET2_4 ((uint32_t)0x00000010) /*!< ADC OFFSET2 bit 4 */ |
bogdanm | 86:04dd9b1680ae | 1403 | #define ADC_OFR2_OFFSET2_5 ((uint32_t)0x00000020) /*!< ADC OFFSET2 bit 5 */ |
bogdanm | 86:04dd9b1680ae | 1404 | #define ADC_OFR2_OFFSET2_6 ((uint32_t)0x00000040) /*!< ADC OFFSET2 bit 6 */ |
bogdanm | 86:04dd9b1680ae | 1405 | #define ADC_OFR2_OFFSET2_7 ((uint32_t)0x00000080) /*!< ADC OFFSET2 bit 7 */ |
bogdanm | 86:04dd9b1680ae | 1406 | #define ADC_OFR2_OFFSET2_8 ((uint32_t)0x00000100) /*!< ADC OFFSET2 bit 8 */ |
bogdanm | 86:04dd9b1680ae | 1407 | #define ADC_OFR2_OFFSET2_9 ((uint32_t)0x00000200) /*!< ADC OFFSET2 bit 9 */ |
bogdanm | 86:04dd9b1680ae | 1408 | #define ADC_OFR2_OFFSET2_10 ((uint32_t)0x00000400) /*!< ADC OFFSET2 bit 10 */ |
bogdanm | 86:04dd9b1680ae | 1409 | #define ADC_OFR2_OFFSET2_11 ((uint32_t)0x00000800) /*!< ADC OFFSET2 bit 11 */ |
bogdanm | 86:04dd9b1680ae | 1410 | |
bogdanm | 86:04dd9b1680ae | 1411 | #define ADC_OFR2_OFFSET2_CH ((uint32_t)0x7C000000) /*!< ADC Channel selection for the data offset 2 */ |
bogdanm | 86:04dd9b1680ae | 1412 | #define ADC_OFR2_OFFSET2_CH_0 ((uint32_t)0x04000000) /*!< ADC OFFSET2_CH bit 0 */ |
bogdanm | 86:04dd9b1680ae | 1413 | #define ADC_OFR2_OFFSET2_CH_1 ((uint32_t)0x08000000) /*!< ADC OFFSET2_CH bit 1 */ |
bogdanm | 86:04dd9b1680ae | 1414 | #define ADC_OFR2_OFFSET2_CH_2 ((uint32_t)0x10000000) /*!< ADC OFFSET2_CH bit 2 */ |
bogdanm | 86:04dd9b1680ae | 1415 | #define ADC_OFR2_OFFSET2_CH_3 ((uint32_t)0x20000000) /*!< ADC OFFSET2_CH bit 3 */ |
bogdanm | 86:04dd9b1680ae | 1416 | #define ADC_OFR2_OFFSET2_CH_4 ((uint32_t)0x40000000) /*!< ADC OFFSET2_CH bit 4 */ |
bogdanm | 86:04dd9b1680ae | 1417 | |
bogdanm | 86:04dd9b1680ae | 1418 | #define ADC_OFR2_OFFSET2_EN ((uint32_t)0x80000000) /*!< ADC offset 2 enable */ |
bogdanm | 86:04dd9b1680ae | 1419 | |
bogdanm | 86:04dd9b1680ae | 1420 | /******************** Bit definition for ADC_OFR3 register ********************/ |
bogdanm | 86:04dd9b1680ae | 1421 | #define ADC_OFR3_OFFSET3 ((uint32_t)0x00000FFF) /*!< ADC data offset 3 for channel programmed into bits OFFSET3_CH[4:0] */ |
bogdanm | 86:04dd9b1680ae | 1422 | #define ADC_OFR3_OFFSET3_0 ((uint32_t)0x00000001) /*!< ADC OFFSET3 bit 0 */ |
bogdanm | 86:04dd9b1680ae | 1423 | #define ADC_OFR3_OFFSET3_1 ((uint32_t)0x00000002) /*!< ADC OFFSET3 bit 1 */ |
bogdanm | 86:04dd9b1680ae | 1424 | #define ADC_OFR3_OFFSET3_2 ((uint32_t)0x00000004) /*!< ADC OFFSET3 bit 2 */ |
bogdanm | 86:04dd9b1680ae | 1425 | #define ADC_OFR3_OFFSET3_3 ((uint32_t)0x00000008) /*!< ADC OFFSET3 bit 3 */ |
bogdanm | 86:04dd9b1680ae | 1426 | #define ADC_OFR3_OFFSET3_4 ((uint32_t)0x00000010) /*!< ADC OFFSET3 bit 4 */ |
bogdanm | 86:04dd9b1680ae | 1427 | #define ADC_OFR3_OFFSET3_5 ((uint32_t)0x00000020) /*!< ADC OFFSET3 bit 5 */ |
bogdanm | 86:04dd9b1680ae | 1428 | #define ADC_OFR3_OFFSET3_6 ((uint32_t)0x00000040) /*!< ADC OFFSET3 bit 6 */ |
bogdanm | 86:04dd9b1680ae | 1429 | #define ADC_OFR3_OFFSET3_7 ((uint32_t)0x00000080) /*!< ADC OFFSET3 bit 7 */ |
bogdanm | 86:04dd9b1680ae | 1430 | #define ADC_OFR3_OFFSET3_8 ((uint32_t)0x00000100) /*!< ADC OFFSET3 bit 8 */ |
bogdanm | 86:04dd9b1680ae | 1431 | #define ADC_OFR3_OFFSET3_9 ((uint32_t)0x00000200) /*!< ADC OFFSET3 bit 9 */ |
bogdanm | 86:04dd9b1680ae | 1432 | #define ADC_OFR3_OFFSET3_10 ((uint32_t)0x00000400) /*!< ADC OFFSET3 bit 10 */ |
bogdanm | 86:04dd9b1680ae | 1433 | #define ADC_OFR3_OFFSET3_11 ((uint32_t)0x00000800) /*!< ADC OFFSET3 bit 11 */ |
bogdanm | 86:04dd9b1680ae | 1434 | |
bogdanm | 86:04dd9b1680ae | 1435 | #define ADC_OFR3_OFFSET3_CH ((uint32_t)0x7C000000) /*!< ADC Channel selection for the data offset 3 */ |
bogdanm | 86:04dd9b1680ae | 1436 | #define ADC_OFR3_OFFSET3_CH_0 ((uint32_t)0x04000000) /*!< ADC OFFSET3_CH bit 0 */ |
bogdanm | 86:04dd9b1680ae | 1437 | #define ADC_OFR3_OFFSET3_CH_1 ((uint32_t)0x08000000) /*!< ADC OFFSET3_CH bit 1 */ |
bogdanm | 86:04dd9b1680ae | 1438 | #define ADC_OFR3_OFFSET3_CH_2 ((uint32_t)0x10000000) /*!< ADC OFFSET3_CH bit 2 */ |
bogdanm | 86:04dd9b1680ae | 1439 | #define ADC_OFR3_OFFSET3_CH_3 ((uint32_t)0x20000000) /*!< ADC OFFSET3_CH bit 3 */ |
bogdanm | 86:04dd9b1680ae | 1440 | #define ADC_OFR3_OFFSET3_CH_4 ((uint32_t)0x40000000) /*!< ADC OFFSET3_CH bit 4 */ |
bogdanm | 86:04dd9b1680ae | 1441 | |
bogdanm | 86:04dd9b1680ae | 1442 | #define ADC_OFR3_OFFSET3_EN ((uint32_t)0x80000000) /*!< ADC offset 3 enable */ |
bogdanm | 86:04dd9b1680ae | 1443 | |
bogdanm | 86:04dd9b1680ae | 1444 | /******************** Bit definition for ADC_OFR4 register ********************/ |
bogdanm | 86:04dd9b1680ae | 1445 | #define ADC_OFR4_OFFSET4 ((uint32_t)0x00000FFF) /*!< ADC data offset 4 for channel programmed into bits OFFSET4_CH[4:0] */ |
bogdanm | 86:04dd9b1680ae | 1446 | #define ADC_OFR4_OFFSET4_0 ((uint32_t)0x00000001) /*!< ADC OFFSET4 bit 0 */ |
bogdanm | 86:04dd9b1680ae | 1447 | #define ADC_OFR4_OFFSET4_1 ((uint32_t)0x00000002) /*!< ADC OFFSET4 bit 1 */ |
bogdanm | 86:04dd9b1680ae | 1448 | #define ADC_OFR4_OFFSET4_2 ((uint32_t)0x00000004) /*!< ADC OFFSET4 bit 2 */ |
bogdanm | 86:04dd9b1680ae | 1449 | #define ADC_OFR4_OFFSET4_3 ((uint32_t)0x00000008) /*!< ADC OFFSET4 bit 3 */ |
bogdanm | 86:04dd9b1680ae | 1450 | #define ADC_OFR4_OFFSET4_4 ((uint32_t)0x00000010) /*!< ADC OFFSET4 bit 4 */ |
bogdanm | 86:04dd9b1680ae | 1451 | #define ADC_OFR4_OFFSET4_5 ((uint32_t)0x00000020) /*!< ADC OFFSET4 bit 5 */ |
bogdanm | 86:04dd9b1680ae | 1452 | #define ADC_OFR4_OFFSET4_6 ((uint32_t)0x00000040) /*!< ADC OFFSET4 bit 6 */ |
bogdanm | 86:04dd9b1680ae | 1453 | #define ADC_OFR4_OFFSET4_7 ((uint32_t)0x00000080) /*!< ADC OFFSET4 bit 7 */ |
bogdanm | 86:04dd9b1680ae | 1454 | #define ADC_OFR4_OFFSET4_8 ((uint32_t)0x00000100) /*!< ADC OFFSET4 bit 8 */ |
bogdanm | 86:04dd9b1680ae | 1455 | #define ADC_OFR4_OFFSET4_9 ((uint32_t)0x00000200) /*!< ADC OFFSET4 bit 9 */ |
bogdanm | 86:04dd9b1680ae | 1456 | #define ADC_OFR4_OFFSET4_10 ((uint32_t)0x00000400) /*!< ADC OFFSET4 bit 10 */ |
bogdanm | 86:04dd9b1680ae | 1457 | #define ADC_OFR4_OFFSET4_11 ((uint32_t)0x00000800) /*!< ADC OFFSET4 bit 11 */ |
bogdanm | 86:04dd9b1680ae | 1458 | |
bogdanm | 86:04dd9b1680ae | 1459 | #define ADC_OFR4_OFFSET4_CH ((uint32_t)0x7C000000) /*!< ADC Channel selection for the data offset 4 */ |
bogdanm | 86:04dd9b1680ae | 1460 | #define ADC_OFR4_OFFSET4_CH_0 ((uint32_t)0x04000000) /*!< ADC OFFSET4_CH bit 0 */ |
bogdanm | 86:04dd9b1680ae | 1461 | #define ADC_OFR4_OFFSET4_CH_1 ((uint32_t)0x08000000) /*!< ADC OFFSET4_CH bit 1 */ |
bogdanm | 86:04dd9b1680ae | 1462 | #define ADC_OFR4_OFFSET4_CH_2 ((uint32_t)0x10000000) /*!< ADC OFFSET4_CH bit 2 */ |
bogdanm | 86:04dd9b1680ae | 1463 | #define ADC_OFR4_OFFSET4_CH_3 ((uint32_t)0x20000000) /*!< ADC OFFSET4_CH bit 3 */ |
bogdanm | 86:04dd9b1680ae | 1464 | #define ADC_OFR4_OFFSET4_CH_4 ((uint32_t)0x40000000) /*!< ADC OFFSET4_CH bit 4 */ |
bogdanm | 86:04dd9b1680ae | 1465 | |
bogdanm | 86:04dd9b1680ae | 1466 | #define ADC_OFR4_OFFSET4_EN ((uint32_t)0x80000000) /*!< ADC offset 4 enable */ |
bogdanm | 86:04dd9b1680ae | 1467 | |
bogdanm | 86:04dd9b1680ae | 1468 | /******************** Bit definition for ADC_JDR1 register ********************/ |
bogdanm | 86:04dd9b1680ae | 1469 | #define ADC_JDR1_JDATA ((uint32_t)0x0000FFFF) /*!< ADC Injected DATA */ |
bogdanm | 86:04dd9b1680ae | 1470 | #define ADC_JDR1_JDATA_0 ((uint32_t)0x00000001) /*!< ADC JDATA bit 0 */ |
bogdanm | 86:04dd9b1680ae | 1471 | #define ADC_JDR1_JDATA_1 ((uint32_t)0x00000002) /*!< ADC JDATA bit 1 */ |
bogdanm | 86:04dd9b1680ae | 1472 | #define ADC_JDR1_JDATA_2 ((uint32_t)0x00000004) /*!< ADC JDATA bit 2 */ |
bogdanm | 86:04dd9b1680ae | 1473 | #define ADC_JDR1_JDATA_3 ((uint32_t)0x00000008) /*!< ADC JDATA bit 3 */ |
bogdanm | 86:04dd9b1680ae | 1474 | #define ADC_JDR1_JDATA_4 ((uint32_t)0x00000010) /*!< ADC JDATA bit 4 */ |
bogdanm | 86:04dd9b1680ae | 1475 | #define ADC_JDR1_JDATA_5 ((uint32_t)0x00000020) /*!< ADC JDATA bit 5 */ |
bogdanm | 86:04dd9b1680ae | 1476 | #define ADC_JDR1_JDATA_6 ((uint32_t)0x00000040) /*!< ADC JDATA bit 6 */ |
bogdanm | 86:04dd9b1680ae | 1477 | #define ADC_JDR1_JDATA_7 ((uint32_t)0x00000080) /*!< ADC JDATA bit 7 */ |
bogdanm | 86:04dd9b1680ae | 1478 | #define ADC_JDR1_JDATA_8 ((uint32_t)0x00000100) /*!< ADC JDATA bit 8 */ |
bogdanm | 86:04dd9b1680ae | 1479 | #define ADC_JDR1_JDATA_9 ((uint32_t)0x00000200) /*!< ADC JDATA bit 9 */ |
bogdanm | 86:04dd9b1680ae | 1480 | #define ADC_JDR1_JDATA_10 ((uint32_t)0x00000400) /*!< ADC JDATA bit 10 */ |
bogdanm | 86:04dd9b1680ae | 1481 | #define ADC_JDR1_JDATA_11 ((uint32_t)0x00000800) /*!< ADC JDATA bit 11 */ |
bogdanm | 86:04dd9b1680ae | 1482 | #define ADC_JDR1_JDATA_12 ((uint32_t)0x00001000) /*!< ADC JDATA bit 12 */ |
bogdanm | 86:04dd9b1680ae | 1483 | #define ADC_JDR1_JDATA_13 ((uint32_t)0x00002000) /*!< ADC JDATA bit 13 */ |
bogdanm | 86:04dd9b1680ae | 1484 | #define ADC_JDR1_JDATA_14 ((uint32_t)0x00004000) /*!< ADC JDATA bit 14 */ |
bogdanm | 86:04dd9b1680ae | 1485 | #define ADC_JDR1_JDATA_15 ((uint32_t)0x00008000) /*!< ADC JDATA bit 15 */ |
bogdanm | 86:04dd9b1680ae | 1486 | |
bogdanm | 86:04dd9b1680ae | 1487 | /******************** Bit definition for ADC_JDR2 register ********************/ |
bogdanm | 86:04dd9b1680ae | 1488 | #define ADC_JDR2_JDATA ((uint32_t)0x0000FFFF) /*!< ADC Injected DATA */ |
bogdanm | 86:04dd9b1680ae | 1489 | #define ADC_JDR2_JDATA_0 ((uint32_t)0x00000001) /*!< ADC JDATA bit 0 */ |
bogdanm | 86:04dd9b1680ae | 1490 | #define ADC_JDR2_JDATA_1 ((uint32_t)0x00000002) /*!< ADC JDATA bit 1 */ |
bogdanm | 86:04dd9b1680ae | 1491 | #define ADC_JDR2_JDATA_2 ((uint32_t)0x00000004) /*!< ADC JDATA bit 2 */ |
bogdanm | 86:04dd9b1680ae | 1492 | #define ADC_JDR2_JDATA_3 ((uint32_t)0x00000008) /*!< ADC JDATA bit 3 */ |
bogdanm | 86:04dd9b1680ae | 1493 | #define ADC_JDR2_JDATA_4 ((uint32_t)0x00000010) /*!< ADC JDATA bit 4 */ |
bogdanm | 86:04dd9b1680ae | 1494 | #define ADC_JDR2_JDATA_5 ((uint32_t)0x00000020) /*!< ADC JDATA bit 5 */ |
bogdanm | 86:04dd9b1680ae | 1495 | #define ADC_JDR2_JDATA_6 ((uint32_t)0x00000040) /*!< ADC JDATA bit 6 */ |
bogdanm | 86:04dd9b1680ae | 1496 | #define ADC_JDR2_JDATA_7 ((uint32_t)0x00000080) /*!< ADC JDATA bit 7 */ |
bogdanm | 86:04dd9b1680ae | 1497 | #define ADC_JDR2_JDATA_8 ((uint32_t)0x00000100) /*!< ADC JDATA bit 8 */ |
bogdanm | 86:04dd9b1680ae | 1498 | #define ADC_JDR2_JDATA_9 ((uint32_t)0x00000200) /*!< ADC JDATA bit 9 */ |
bogdanm | 86:04dd9b1680ae | 1499 | #define ADC_JDR2_JDATA_10 ((uint32_t)0x00000400) /*!< ADC JDATA bit 10 */ |
bogdanm | 86:04dd9b1680ae | 1500 | #define ADC_JDR2_JDATA_11 ((uint32_t)0x00000800) /*!< ADC JDATA bit 11 */ |
bogdanm | 86:04dd9b1680ae | 1501 | #define ADC_JDR2_JDATA_12 ((uint32_t)0x00001000) /*!< ADC JDATA bit 12 */ |
bogdanm | 86:04dd9b1680ae | 1502 | #define ADC_JDR2_JDATA_13 ((uint32_t)0x00002000) /*!< ADC JDATA bit 13 */ |
bogdanm | 86:04dd9b1680ae | 1503 | #define ADC_JDR2_JDATA_14 ((uint32_t)0x00004000) /*!< ADC JDATA bit 14 */ |
bogdanm | 86:04dd9b1680ae | 1504 | #define ADC_JDR2_JDATA_15 ((uint32_t)0x00008000) /*!< ADC JDATA bit 15 */ |
bogdanm | 86:04dd9b1680ae | 1505 | |
bogdanm | 86:04dd9b1680ae | 1506 | /******************** Bit definition for ADC_JDR3 register ********************/ |
bogdanm | 86:04dd9b1680ae | 1507 | #define ADC_JDR3_JDATA ((uint32_t)0x0000FFFF) /*!< ADC Injected DATA */ |
bogdanm | 86:04dd9b1680ae | 1508 | #define ADC_JDR3_JDATA_0 ((uint32_t)0x00000001) /*!< ADC JDATA bit 0 */ |
bogdanm | 86:04dd9b1680ae | 1509 | #define ADC_JDR3_JDATA_1 ((uint32_t)0x00000002) /*!< ADC JDATA bit 1 */ |
bogdanm | 86:04dd9b1680ae | 1510 | #define ADC_JDR3_JDATA_2 ((uint32_t)0x00000004) /*!< ADC JDATA bit 2 */ |
bogdanm | 86:04dd9b1680ae | 1511 | #define ADC_JDR3_JDATA_3 ((uint32_t)0x00000008) /*!< ADC JDATA bit 3 */ |
bogdanm | 86:04dd9b1680ae | 1512 | #define ADC_JDR3_JDATA_4 ((uint32_t)0x00000010) /*!< ADC JDATA bit 4 */ |
bogdanm | 86:04dd9b1680ae | 1513 | #define ADC_JDR3_JDATA_5 ((uint32_t)0x00000020) /*!< ADC JDATA bit 5 */ |
bogdanm | 86:04dd9b1680ae | 1514 | #define ADC_JDR3_JDATA_6 ((uint32_t)0x00000040) /*!< ADC JDATA bit 6 */ |
bogdanm | 86:04dd9b1680ae | 1515 | #define ADC_JDR3_JDATA_7 ((uint32_t)0x00000080) /*!< ADC JDATA bit 7 */ |
bogdanm | 86:04dd9b1680ae | 1516 | #define ADC_JDR3_JDATA_8 ((uint32_t)0x00000100) /*!< ADC JDATA bit 8 */ |
bogdanm | 86:04dd9b1680ae | 1517 | #define ADC_JDR3_JDATA_9 ((uint32_t)0x00000200) /*!< ADC JDATA bit 9 */ |
bogdanm | 86:04dd9b1680ae | 1518 | #define ADC_JDR3_JDATA_10 ((uint32_t)0x00000400) /*!< ADC JDATA bit 10 */ |
bogdanm | 86:04dd9b1680ae | 1519 | #define ADC_JDR3_JDATA_11 ((uint32_t)0x00000800) /*!< ADC JDATA bit 11 */ |
bogdanm | 86:04dd9b1680ae | 1520 | #define ADC_JDR3_JDATA_12 ((uint32_t)0x00001000) /*!< ADC JDATA bit 12 */ |
bogdanm | 86:04dd9b1680ae | 1521 | #define ADC_JDR3_JDATA_13 ((uint32_t)0x00002000) /*!< ADC JDATA bit 13 */ |
bogdanm | 86:04dd9b1680ae | 1522 | #define ADC_JDR3_JDATA_14 ((uint32_t)0x00004000) /*!< ADC JDATA bit 14 */ |
bogdanm | 86:04dd9b1680ae | 1523 | #define ADC_JDR3_JDATA_15 ((uint32_t)0x00008000) /*!< ADC JDATA bit 15 */ |
bogdanm | 86:04dd9b1680ae | 1524 | |
bogdanm | 86:04dd9b1680ae | 1525 | /******************** Bit definition for ADC_JDR4 register ********************/ |
bogdanm | 86:04dd9b1680ae | 1526 | #define ADC_JDR4_JDATA ((uint32_t)0x0000FFFF) /*!< ADC Injected DATA */ |
bogdanm | 86:04dd9b1680ae | 1527 | #define ADC_JDR4_JDATA_0 ((uint32_t)0x00000001) /*!< ADC JDATA bit 0 */ |
bogdanm | 86:04dd9b1680ae | 1528 | #define ADC_JDR4_JDATA_1 ((uint32_t)0x00000002) /*!< ADC JDATA bit 1 */ |
bogdanm | 86:04dd9b1680ae | 1529 | #define ADC_JDR4_JDATA_2 ((uint32_t)0x00000004) /*!< ADC JDATA bit 2 */ |
bogdanm | 86:04dd9b1680ae | 1530 | #define ADC_JDR4_JDATA_3 ((uint32_t)0x00000008) /*!< ADC JDATA bit 3 */ |
bogdanm | 86:04dd9b1680ae | 1531 | #define ADC_JDR4_JDATA_4 ((uint32_t)0x00000010) /*!< ADC JDATA bit 4 */ |
bogdanm | 86:04dd9b1680ae | 1532 | #define ADC_JDR4_JDATA_5 ((uint32_t)0x00000020) /*!< ADC JDATA bit 5 */ |
bogdanm | 86:04dd9b1680ae | 1533 | #define ADC_JDR4_JDATA_6 ((uint32_t)0x00000040) /*!< ADC JDATA bit 6 */ |
bogdanm | 86:04dd9b1680ae | 1534 | #define ADC_JDR4_JDATA_7 ((uint32_t)0x00000080) /*!< ADC JDATA bit 7 */ |
bogdanm | 86:04dd9b1680ae | 1535 | #define ADC_JDR4_JDATA_8 ((uint32_t)0x00000100) /*!< ADC JDATA bit 8 */ |
bogdanm | 86:04dd9b1680ae | 1536 | #define ADC_JDR4_JDATA_9 ((uint32_t)0x00000200) /*!< ADC JDATA bit 9 */ |
bogdanm | 86:04dd9b1680ae | 1537 | #define ADC_JDR4_JDATA_10 ((uint32_t)0x00000400) /*!< ADC JDATA bit 10 */ |
bogdanm | 86:04dd9b1680ae | 1538 | #define ADC_JDR4_JDATA_11 ((uint32_t)0x00000800) /*!< ADC JDATA bit 11 */ |
bogdanm | 86:04dd9b1680ae | 1539 | #define ADC_JDR4_JDATA_12 ((uint32_t)0x00001000) /*!< ADC JDATA bit 12 */ |
bogdanm | 86:04dd9b1680ae | 1540 | #define ADC_JDR4_JDATA_13 ((uint32_t)0x00002000) /*!< ADC JDATA bit 13 */ |
bogdanm | 86:04dd9b1680ae | 1541 | #define ADC_JDR4_JDATA_14 ((uint32_t)0x00004000) /*!< ADC JDATA bit 14 */ |
bogdanm | 86:04dd9b1680ae | 1542 | #define ADC_JDR4_JDATA_15 ((uint32_t)0x00008000) /*!< ADC JDATA bit 15 */ |
bogdanm | 86:04dd9b1680ae | 1543 | |
bogdanm | 86:04dd9b1680ae | 1544 | /******************** Bit definition for ADC_AWD2CR register ********************/ |
bogdanm | 86:04dd9b1680ae | 1545 | #define ADC_AWD2CR_AWD2CH ((uint32_t)0x0007FFFE) /*!< ADC Analog watchdog 2 channel selection */ |
bogdanm | 86:04dd9b1680ae | 1546 | #define ADC_AWD2CR_AWD2CH_0 ((uint32_t)0x00000002) /*!< ADC AWD2CH bit 0 */ |
bogdanm | 86:04dd9b1680ae | 1547 | #define ADC_AWD2CR_AWD2CH_1 ((uint32_t)0x00000004) /*!< ADC AWD2CH bit 1 */ |
bogdanm | 86:04dd9b1680ae | 1548 | #define ADC_AWD2CR_AWD2CH_2 ((uint32_t)0x00000008) /*!< ADC AWD2CH bit 2 */ |
bogdanm | 86:04dd9b1680ae | 1549 | #define ADC_AWD2CR_AWD2CH_3 ((uint32_t)0x00000010) /*!< ADC AWD2CH bit 3 */ |
bogdanm | 86:04dd9b1680ae | 1550 | #define ADC_AWD2CR_AWD2CH_4 ((uint32_t)0x00000020) /*!< ADC AWD2CH bit 4 */ |
bogdanm | 86:04dd9b1680ae | 1551 | #define ADC_AWD2CR_AWD2CH_5 ((uint32_t)0x00000040) /*!< ADC AWD2CH bit 5 */ |
bogdanm | 86:04dd9b1680ae | 1552 | #define ADC_AWD2CR_AWD2CH_6 ((uint32_t)0x00000080) /*!< ADC AWD2CH bit 6 */ |
bogdanm | 86:04dd9b1680ae | 1553 | #define ADC_AWD2CR_AWD2CH_7 ((uint32_t)0x00000100) /*!< ADC AWD2CH bit 7 */ |
bogdanm | 86:04dd9b1680ae | 1554 | #define ADC_AWD2CR_AWD2CH_8 ((uint32_t)0x00000200) /*!< ADC AWD2CH bit 8 */ |
bogdanm | 86:04dd9b1680ae | 1555 | #define ADC_AWD2CR_AWD2CH_9 ((uint32_t)0x00000400) /*!< ADC AWD2CH bit 9 */ |
bogdanm | 86:04dd9b1680ae | 1556 | #define ADC_AWD2CR_AWD2CH_10 ((uint32_t)0x00000800) /*!< ADC AWD2CH bit 10 */ |
bogdanm | 86:04dd9b1680ae | 1557 | #define ADC_AWD2CR_AWD2CH_11 ((uint32_t)0x00001000) /*!< ADC AWD2CH bit 11 */ |
bogdanm | 86:04dd9b1680ae | 1558 | #define ADC_AWD2CR_AWD2CH_12 ((uint32_t)0x00002000) /*!< ADC AWD2CH bit 12 */ |
bogdanm | 86:04dd9b1680ae | 1559 | #define ADC_AWD2CR_AWD2CH_13 ((uint32_t)0x00004000) /*!< ADC AWD2CH bit 13 */ |
bogdanm | 86:04dd9b1680ae | 1560 | #define ADC_AWD2CR_AWD2CH_14 ((uint32_t)0x00008000) /*!< ADC AWD2CH bit 14 */ |
bogdanm | 86:04dd9b1680ae | 1561 | #define ADC_AWD2CR_AWD2CH_15 ((uint32_t)0x00010000) /*!< ADC AWD2CH bit 15 */ |
bogdanm | 86:04dd9b1680ae | 1562 | #define ADC_AWD2CR_AWD2CH_16 ((uint32_t)0x00020000) /*!< ADC AWD2CH bit 16 */ |
bogdanm | 86:04dd9b1680ae | 1563 | #define ADC_AWD2CR_AWD2CH_17 ((uint32_t)0x00030000) /*!< ADC AWD2CH bit 17 */ |
bogdanm | 86:04dd9b1680ae | 1564 | |
bogdanm | 86:04dd9b1680ae | 1565 | /******************** Bit definition for ADC_AWD3CR register ********************/ |
bogdanm | 86:04dd9b1680ae | 1566 | #define ADC_AWD3CR_AWD3CH ((uint32_t)0x0007FFFE) /*!< ADC Analog watchdog 2 channel selection */ |
bogdanm | 86:04dd9b1680ae | 1567 | #define ADC_AWD3CR_AWD3CH_0 ((uint32_t)0x00000002) /*!< ADC AWD3CH bit 0 */ |
bogdanm | 86:04dd9b1680ae | 1568 | #define ADC_AWD3CR_AWD3CH_1 ((uint32_t)0x00000004) /*!< ADC AWD3CH bit 1 */ |
bogdanm | 86:04dd9b1680ae | 1569 | #define ADC_AWD3CR_AWD3CH_2 ((uint32_t)0x00000008) /*!< ADC AWD3CH bit 2 */ |
bogdanm | 86:04dd9b1680ae | 1570 | #define ADC_AWD3CR_AWD3CH_3 ((uint32_t)0x00000010) /*!< ADC AWD3CH bit 3 */ |
bogdanm | 86:04dd9b1680ae | 1571 | #define ADC_AWD3CR_AWD3CH_4 ((uint32_t)0x00000020) /*!< ADC AWD3CH bit 4 */ |
bogdanm | 86:04dd9b1680ae | 1572 | #define ADC_AWD3CR_AWD3CH_5 ((uint32_t)0x00000040) /*!< ADC AWD3CH bit 5 */ |
bogdanm | 86:04dd9b1680ae | 1573 | #define ADC_AWD3CR_AWD3CH_6 ((uint32_t)0x00000080) /*!< ADC AWD3CH bit 6 */ |
bogdanm | 86:04dd9b1680ae | 1574 | #define ADC_AWD3CR_AWD3CH_7 ((uint32_t)0x00000100) /*!< ADC AWD3CH bit 7 */ |
bogdanm | 86:04dd9b1680ae | 1575 | #define ADC_AWD3CR_AWD3CH_8 ((uint32_t)0x00000200) /*!< ADC AWD3CH bit 8 */ |
bogdanm | 86:04dd9b1680ae | 1576 | #define ADC_AWD3CR_AWD3CH_9 ((uint32_t)0x00000400) /*!< ADC AWD3CH bit 9 */ |
bogdanm | 86:04dd9b1680ae | 1577 | #define ADC_AWD3CR_AWD3CH_10 ((uint32_t)0x00000800) /*!< ADC AWD3CH bit 10 */ |
bogdanm | 86:04dd9b1680ae | 1578 | #define ADC_AWD3CR_AWD3CH_11 ((uint32_t)0x00001000) /*!< ADC AWD3CH bit 11 */ |
bogdanm | 86:04dd9b1680ae | 1579 | #define ADC_AWD3CR_AWD3CH_12 ((uint32_t)0x00002000) /*!< ADC AWD3CH bit 12 */ |
bogdanm | 86:04dd9b1680ae | 1580 | #define ADC_AWD3CR_AWD3CH_13 ((uint32_t)0x00004000) /*!< ADC AWD3CH bit 13 */ |
bogdanm | 86:04dd9b1680ae | 1581 | #define ADC_AWD3CR_AWD3CH_14 ((uint32_t)0x00008000) /*!< ADC AWD3CH bit 14 */ |
bogdanm | 86:04dd9b1680ae | 1582 | #define ADC_AWD3CR_AWD3CH_15 ((uint32_t)0x00010000) /*!< ADC AWD3CH bit 15 */ |
bogdanm | 86:04dd9b1680ae | 1583 | #define ADC_AWD3CR_AWD3CH_16 ((uint32_t)0x00020000) /*!< ADC AWD3CH bit 16 */ |
bogdanm | 86:04dd9b1680ae | 1584 | #define ADC_AWD3CR_AWD3CH_17 ((uint32_t)0x00030000) /*!< ADC AWD3CH bit 17 */ |
bogdanm | 86:04dd9b1680ae | 1585 | |
bogdanm | 86:04dd9b1680ae | 1586 | /******************** Bit definition for ADC_DIFSEL register ********************/ |
bogdanm | 86:04dd9b1680ae | 1587 | #define ADC_DIFSEL_DIFSEL ((uint32_t)0x0007FFFE) /*!< ADC differential modes for channels 1 to 18 */ |
bogdanm | 86:04dd9b1680ae | 1588 | #define ADC_DIFSEL_DIFSEL_0 ((uint32_t)0x00000002) /*!< ADC DIFSEL bit 0 */ |
bogdanm | 86:04dd9b1680ae | 1589 | #define ADC_DIFSEL_DIFSEL_1 ((uint32_t)0x00000004) /*!< ADC DIFSEL bit 1 */ |
bogdanm | 86:04dd9b1680ae | 1590 | #define ADC_DIFSEL_DIFSEL_2 ((uint32_t)0x00000008) /*!< ADC DIFSEL bit 2 */ |
bogdanm | 86:04dd9b1680ae | 1591 | #define ADC_DIFSEL_DIFSEL_3 ((uint32_t)0x00000010) /*!< ADC DIFSEL bit 3 */ |
bogdanm | 86:04dd9b1680ae | 1592 | #define ADC_DIFSEL_DIFSEL_4 ((uint32_t)0x00000020) /*!< ADC DIFSEL bit 4 */ |
bogdanm | 86:04dd9b1680ae | 1593 | #define ADC_DIFSEL_DIFSEL_5 ((uint32_t)0x00000040) /*!< ADC DIFSEL bit 5 */ |
bogdanm | 86:04dd9b1680ae | 1594 | #define ADC_DIFSEL_DIFSEL_6 ((uint32_t)0x00000080) /*!< ADC DIFSEL bit 6 */ |
bogdanm | 86:04dd9b1680ae | 1595 | #define ADC_DIFSEL_DIFSEL_7 ((uint32_t)0x00000100) /*!< ADC DIFSEL bit 7 */ |
bogdanm | 86:04dd9b1680ae | 1596 | #define ADC_DIFSEL_DIFSEL_8 ((uint32_t)0x00000200) /*!< ADC DIFSEL bit 8 */ |
bogdanm | 86:04dd9b1680ae | 1597 | #define ADC_DIFSEL_DIFSEL_9 ((uint32_t)0x00000400) /*!< ADC DIFSEL bit 9 */ |
bogdanm | 86:04dd9b1680ae | 1598 | #define ADC_DIFSEL_DIFSEL_10 ((uint32_t)0x00000800) /*!< ADC DIFSEL bit 10 */ |
bogdanm | 86:04dd9b1680ae | 1599 | #define ADC_DIFSEL_DIFSEL_11 ((uint32_t)0x00001000) /*!< ADC DIFSEL bit 11 */ |
bogdanm | 86:04dd9b1680ae | 1600 | #define ADC_DIFSEL_DIFSEL_12 ((uint32_t)0x00002000) /*!< ADC DIFSEL bit 12 */ |
bogdanm | 86:04dd9b1680ae | 1601 | #define ADC_DIFSEL_DIFSEL_13 ((uint32_t)0x00004000) /*!< ADC DIFSEL bit 13 */ |
bogdanm | 86:04dd9b1680ae | 1602 | #define ADC_DIFSEL_DIFSEL_14 ((uint32_t)0x00008000) /*!< ADC DIFSEL bit 14 */ |
bogdanm | 86:04dd9b1680ae | 1603 | #define ADC_DIFSEL_DIFSEL_15 ((uint32_t)0x00010000) /*!< ADC DIFSEL bit 15 */ |
bogdanm | 86:04dd9b1680ae | 1604 | #define ADC_DIFSEL_DIFSEL_16 ((uint32_t)0x00020000) /*!< ADC DIFSEL bit 16 */ |
bogdanm | 86:04dd9b1680ae | 1605 | #define ADC_DIFSEL_DIFSEL_17 ((uint32_t)0x00030000) /*!< ADC DIFSEL bit 17 */ |
bogdanm | 86:04dd9b1680ae | 1606 | |
bogdanm | 86:04dd9b1680ae | 1607 | /******************** Bit definition for ADC_CALFACT register ********************/ |
bogdanm | 86:04dd9b1680ae | 1608 | #define ADC_CALFACT_CALFACT_S ((uint32_t)0x0000007F) /*!< ADC calibration factors in single-ended mode */ |
bogdanm | 86:04dd9b1680ae | 1609 | #define ADC_CALFACT_CALFACT_S_0 ((uint32_t)0x00000001) /*!< ADC CALFACT_S bit 0 */ |
bogdanm | 86:04dd9b1680ae | 1610 | #define ADC_CALFACT_CALFACT_S_1 ((uint32_t)0x00000002) /*!< ADC CALFACT_S bit 1 */ |
bogdanm | 86:04dd9b1680ae | 1611 | #define ADC_CALFACT_CALFACT_S_2 ((uint32_t)0x00000004) /*!< ADC CALFACT_S bit 2 */ |
bogdanm | 86:04dd9b1680ae | 1612 | #define ADC_CALFACT_CALFACT_S_3 ((uint32_t)0x00000008) /*!< ADC CALFACT_S bit 3 */ |
bogdanm | 86:04dd9b1680ae | 1613 | #define ADC_CALFACT_CALFACT_S_4 ((uint32_t)0x00000010) /*!< ADC CALFACT_S bit 4 */ |
bogdanm | 86:04dd9b1680ae | 1614 | #define ADC_CALFACT_CALFACT_S_5 ((uint32_t)0x00000020) /*!< ADC CALFACT_S bit 5 */ |
bogdanm | 86:04dd9b1680ae | 1615 | #define ADC_CALFACT_CALFACT_S_6 ((uint32_t)0x00000040) /*!< ADC CALFACT_S bit 6 */ |
bogdanm | 86:04dd9b1680ae | 1616 | #define ADC_CALFACT_CALFACT_D ((uint32_t)0x007F0000) /*!< ADC calibration factors in differential mode */ |
bogdanm | 86:04dd9b1680ae | 1617 | #define ADC_CALFACT_CALFACT_D_0 ((uint32_t)0x00010000) /*!< ADC CALFACT_D bit 0 */ |
bogdanm | 86:04dd9b1680ae | 1618 | #define ADC_CALFACT_CALFACT_D_1 ((uint32_t)0x00020000) /*!< ADC CALFACT_D bit 1 */ |
bogdanm | 86:04dd9b1680ae | 1619 | #define ADC_CALFACT_CALFACT_D_2 ((uint32_t)0x00040000) /*!< ADC CALFACT_D bit 2 */ |
bogdanm | 86:04dd9b1680ae | 1620 | #define ADC_CALFACT_CALFACT_D_3 ((uint32_t)0x00080000) /*!< ADC CALFACT_D bit 3 */ |
bogdanm | 86:04dd9b1680ae | 1621 | #define ADC_CALFACT_CALFACT_D_4 ((uint32_t)0x00100000) /*!< ADC CALFACT_D bit 4 */ |
bogdanm | 86:04dd9b1680ae | 1622 | #define ADC_CALFACT_CALFACT_D_5 ((uint32_t)0x00200000) /*!< ADC CALFACT_D bit 5 */ |
bogdanm | 86:04dd9b1680ae | 1623 | #define ADC_CALFACT_CALFACT_D_6 ((uint32_t)0x00400000) /*!< ADC CALFACT_D bit 6 */ |
bogdanm | 86:04dd9b1680ae | 1624 | |
bogdanm | 86:04dd9b1680ae | 1625 | /************************* ADC Common registers *****************************/ |
bogdanm | 86:04dd9b1680ae | 1626 | /******************** Bit definition for ADC12_CSR register ********************/ |
bogdanm | 86:04dd9b1680ae | 1627 | #define ADC12_CSR_ADRDY_MST ((uint32_t)0x00000001) /*!< Master ADC ready */ |
bogdanm | 86:04dd9b1680ae | 1628 | #define ADC12_CSR_ADRDY_EOSMP_MST ((uint32_t)0x00000002) /*!< End of sampling phase flag of the master ADC */ |
bogdanm | 86:04dd9b1680ae | 1629 | #define ADC12_CSR_ADRDY_EOC_MST ((uint32_t)0x00000004) /*!< End of regular conversion of the master ADC */ |
bogdanm | 86:04dd9b1680ae | 1630 | #define ADC12_CSR_ADRDY_EOS_MST ((uint32_t)0x00000008) /*!< End of regular sequence flag of the master ADC */ |
bogdanm | 86:04dd9b1680ae | 1631 | #define ADC12_CSR_ADRDY_OVR_MST ((uint32_t)0x00000010) /*!< Overrun flag of the master ADC */ |
bogdanm | 86:04dd9b1680ae | 1632 | #define ADC12_CSR_ADRDY_JEOC_MST ((uint32_t)0x00000020) /*!< End of injected conversion of the master ADC */ |
bogdanm | 86:04dd9b1680ae | 1633 | #define ADC12_CSR_ADRDY_JEOS_MST ((uint32_t)0x00000040) /*!< End of injected sequence flag of the master ADC */ |
bogdanm | 86:04dd9b1680ae | 1634 | #define ADC12_CSR_AWD1_MST ((uint32_t)0x00000080) /*!< Analog watchdog 1 flag of the master ADC */ |
bogdanm | 86:04dd9b1680ae | 1635 | #define ADC12_CSR_AWD2_MST ((uint32_t)0x00000100) /*!< Analog watchdog 2 flag of the master ADC */ |
bogdanm | 86:04dd9b1680ae | 1636 | #define ADC12_CSR_AWD3_MST ((uint32_t)0x00000200) /*!< Analog watchdog 3 flag of the master ADC */ |
bogdanm | 86:04dd9b1680ae | 1637 | #define ADC12_CSR_JQOVF_MST ((uint32_t)0x00000400) /*!< Injected context queue overflow flag of the master ADC */ |
bogdanm | 86:04dd9b1680ae | 1638 | #define ADC12_CSR_ADRDY_SLV ((uint32_t)0x00010000) /*!< Slave ADC ready */ |
bogdanm | 86:04dd9b1680ae | 1639 | #define ADC12_CSR_ADRDY_EOSMP_SLV ((uint32_t)0x00020000) /*!< End of sampling phase flag of the slave ADC */ |
bogdanm | 86:04dd9b1680ae | 1640 | #define ADC12_CSR_ADRDY_EOC_SLV ((uint32_t)0x00040000) /*!< End of regular conversion of the slave ADC */ |
bogdanm | 86:04dd9b1680ae | 1641 | #define ADC12_CSR_ADRDY_EOS_SLV ((uint32_t)0x00080000) /*!< End of regular sequence flag of the slave ADC */ |
bogdanm | 86:04dd9b1680ae | 1642 | #define ADC12_CSR_ADRDY_OVR_SLV ((uint32_t)0x00100000) /*!< Overrun flag of the slave ADC */ |
bogdanm | 86:04dd9b1680ae | 1643 | #define ADC12_CSR_ADRDY_JEOC_SLV ((uint32_t)0x00200000) /*!< End of injected conversion of the slave ADC */ |
bogdanm | 86:04dd9b1680ae | 1644 | #define ADC12_CSR_ADRDY_JEOS_SLV ((uint32_t)0x00400000) /*!< End of injected sequence flag of the slave ADC */ |
bogdanm | 86:04dd9b1680ae | 1645 | #define ADC12_CSR_AWD1_SLV ((uint32_t)0x00800000) /*!< Analog watchdog 1 flag of the slave ADC */ |
bogdanm | 86:04dd9b1680ae | 1646 | #define ADC12_CSR_AWD2_SLV ((uint32_t)0x01000000) /*!< Analog watchdog 2 flag of the slave ADC */ |
bogdanm | 86:04dd9b1680ae | 1647 | #define ADC12_CSR_AWD3_SLV ((uint32_t)0x02000000) /*!< Analog watchdog 3 flag of the slave ADC */ |
bogdanm | 86:04dd9b1680ae | 1648 | #define ADC12_CSR_JQOVF_SLV ((uint32_t)0x04000000) /*!< Injected context queue overflow flag of the slave ADC */ |
bogdanm | 86:04dd9b1680ae | 1649 | |
bogdanm | 86:04dd9b1680ae | 1650 | /******************** Bit definition for ADC34_CSR register ********************/ |
bogdanm | 86:04dd9b1680ae | 1651 | #define ADC34_CSR_ADRDY_MST ((uint32_t)0x00000001) /*!< Master ADC ready */ |
bogdanm | 86:04dd9b1680ae | 1652 | #define ADC34_CSR_ADRDY_EOSMP_MST ((uint32_t)0x00000002) /*!< End of sampling phase flag of the master ADC */ |
bogdanm | 86:04dd9b1680ae | 1653 | #define ADC34_CSR_ADRDY_EOC_MST ((uint32_t)0x00000004) /*!< End of regular conversion of the master ADC */ |
bogdanm | 86:04dd9b1680ae | 1654 | #define ADC34_CSR_ADRDY_EOS_MST ((uint32_t)0x00000008) /*!< End of regular sequence flag of the master ADC */ |
bogdanm | 86:04dd9b1680ae | 1655 | #define ADC34_CSR_ADRDY_OVR_MST ((uint32_t)0x00000010) /*!< Overrun flag of the master ADC */ |
bogdanm | 86:04dd9b1680ae | 1656 | #define ADC34_CSR_ADRDY_JEOC_MST ((uint32_t)0x00000020) /*!< End of injected conversion of the master ADC */ |
bogdanm | 86:04dd9b1680ae | 1657 | #define ADC34_CSR_ADRDY_JEOS_MST ((uint32_t)0x00000040) /*!< End of injected sequence flag of the master ADC */ |
bogdanm | 86:04dd9b1680ae | 1658 | #define ADC34_CSR_AWD1_MST ((uint32_t)0x00000080) /*!< Analog watchdog 1 flag of the master ADC */ |
bogdanm | 86:04dd9b1680ae | 1659 | #define ADC34_CSR_AWD2_MST ((uint32_t)0x00000100) /*!< Analog watchdog 2 flag of the master ADC */ |
bogdanm | 86:04dd9b1680ae | 1660 | #define ADC34_CSR_AWD3_MST ((uint32_t)0x00000200) /*!< Analog watchdog 3 flag of the master ADC */ |
bogdanm | 86:04dd9b1680ae | 1661 | #define ADC34_CSR_JQOVF_MST ((uint32_t)0x00000400) /*!< Injected context queue overflow flag of the master ADC */ |
bogdanm | 86:04dd9b1680ae | 1662 | #define ADC34_CSR_ADRDY_SLV ((uint32_t)0x00010000) /*!< Slave ADC ready */ |
bogdanm | 86:04dd9b1680ae | 1663 | #define ADC34_CSR_ADRDY_EOSMP_SLV ((uint32_t)0x00020000) /*!< End of sampling phase flag of the slave ADC */ |
bogdanm | 86:04dd9b1680ae | 1664 | #define ADC34_CSR_ADRDY_EOC_SLV ((uint32_t)0x00040000) /*!< End of regular conversion of the slave ADC */ |
bogdanm | 86:04dd9b1680ae | 1665 | #define ADC34_CSR_ADRDY_EOS_SLV ((uint32_t)0x00080000) /*!< End of regular sequence flag of the slave ADC */ |
bogdanm | 86:04dd9b1680ae | 1666 | #define ADC12_CSR_ADRDY_OVR_SLV ((uint32_t)0x00100000) /*!< Overrun flag of the slave ADC */ |
bogdanm | 86:04dd9b1680ae | 1667 | #define ADC34_CSR_ADRDY_JEOC_SLV ((uint32_t)0x00200000) /*!< End of injected conversion of the slave ADC */ |
bogdanm | 86:04dd9b1680ae | 1668 | #define ADC34_CSR_ADRDY_JEOS_SLV ((uint32_t)0x00400000) /*!< End of injected sequence flag of the slave ADC */ |
bogdanm | 86:04dd9b1680ae | 1669 | #define ADC34_CSR_AWD1_SLV ((uint32_t)0x00800000) /*!< Analog watchdog 1 flag of the slave ADC */ |
bogdanm | 86:04dd9b1680ae | 1670 | #define ADC34_CSR_AWD2_SLV ((uint32_t)0x01000000) /*!< Analog watchdog 2 flag of the slave ADC */ |
bogdanm | 86:04dd9b1680ae | 1671 | #define ADC34_CSR_AWD3_SLV ((uint32_t)0x02000000) /*!< Analog watchdog 3 flag of the slave ADC */ |
bogdanm | 86:04dd9b1680ae | 1672 | #define ADC34_CSR_JQOVF_SLV ((uint32_t)0x04000000) /*!< Injected context queue overflow flag of the slave ADC */ |
bogdanm | 86:04dd9b1680ae | 1673 | |
bogdanm | 86:04dd9b1680ae | 1674 | /******************** Bit definition for ADC_CCR register ********************/ |
bogdanm | 86:04dd9b1680ae | 1675 | #define ADC12_CCR_MULTI ((uint32_t)0x0000001F) /*!< Multi ADC mode selection */ |
bogdanm | 86:04dd9b1680ae | 1676 | #define ADC12_CCR_MULTI_0 ((uint32_t)0x00000001) /*!< MULTI bit 0 */ |
bogdanm | 86:04dd9b1680ae | 1677 | #define ADC12_CCR_MULTI_1 ((uint32_t)0x00000002) /*!< MULTI bit 1 */ |
bogdanm | 86:04dd9b1680ae | 1678 | #define ADC12_CCR_MULTI_2 ((uint32_t)0x00000004) /*!< MULTI bit 2 */ |
bogdanm | 86:04dd9b1680ae | 1679 | #define ADC12_CCR_MULTI_3 ((uint32_t)0x00000008) /*!< MULTI bit 3 */ |
bogdanm | 86:04dd9b1680ae | 1680 | #define ADC12_CCR_MULTI_4 ((uint32_t)0x00000010) /*!< MULTI bit 4 */ |
bogdanm | 86:04dd9b1680ae | 1681 | #define ADC12_CCR_DELAY ((uint32_t)0x00000F00) /*!< Delay between 2 sampling phases */ |
bogdanm | 86:04dd9b1680ae | 1682 | #define ADC12_CCR_DELAY_0 ((uint32_t)0x00000100) /*!< DELAY bit 0 */ |
bogdanm | 86:04dd9b1680ae | 1683 | #define ADC12_CCR_DELAY_1 ((uint32_t)0x00000200) /*!< DELAY bit 1 */ |
bogdanm | 86:04dd9b1680ae | 1684 | #define ADC12_CCR_DELAY_2 ((uint32_t)0x00000400) /*!< DELAY bit 2 */ |
bogdanm | 86:04dd9b1680ae | 1685 | #define ADC12_CCR_DELAY_3 ((uint32_t)0x00000800) /*!< DELAY bit 3 */ |
bogdanm | 86:04dd9b1680ae | 1686 | #define ADC12_CCR_DMACFG ((uint32_t)0x00002000) /*!< DMA configuration for multi-ADC mode */ |
bogdanm | 86:04dd9b1680ae | 1687 | #define ADC12_CCR_MDMA ((uint32_t)0x0000C000) /*!< DMA mode for multi-ADC mode */ |
bogdanm | 86:04dd9b1680ae | 1688 | #define ADC12_CCR_MDMA_0 ((uint32_t)0x00004000) /*!< MDMA bit 0 */ |
bogdanm | 86:04dd9b1680ae | 1689 | #define ADC12_CCR_MDMA_1 ((uint32_t)0x00008000) /*!< MDMA bit 1 */ |
bogdanm | 86:04dd9b1680ae | 1690 | #define ADC12_CCR_CKMODE ((uint32_t)0x00030000) /*!< ADC clock mode */ |
bogdanm | 86:04dd9b1680ae | 1691 | #define ADC12_CCR_CKMODE_0 ((uint32_t)0x00010000) /*!< CKMODE bit 0 */ |
bogdanm | 86:04dd9b1680ae | 1692 | #define ADC12_CCR_CKMODE_1 ((uint32_t)0x00020000) /*!< CKMODE bit 1 */ |
bogdanm | 86:04dd9b1680ae | 1693 | #define ADC12_CCR_VREFEN ((uint32_t)0x00400000) /*!< VREFINT enable */ |
bogdanm | 86:04dd9b1680ae | 1694 | #define ADC12_CCR_TSEN ((uint32_t)0x00800000) /*!< Temperature sensor enable */ |
bogdanm | 86:04dd9b1680ae | 1695 | #define ADC12_CCR_VBATEN ((uint32_t)0x01000000) /*!< VBAT enable */ |
bogdanm | 86:04dd9b1680ae | 1696 | |
bogdanm | 86:04dd9b1680ae | 1697 | /******************** Bit definition for ADC_CDR register ********************/ |
bogdanm | 86:04dd9b1680ae | 1698 | #define ADC12_CDR_RDATA_MST ((uint32_t)0x0000FFFF) /*!< Regular Data of the master ADC */ |
bogdanm | 86:04dd9b1680ae | 1699 | #define ADC12_CDR_RDATA_MST_0 ((uint32_t)0x00000001) /*!< RDATA_MST bit 0 */ |
bogdanm | 86:04dd9b1680ae | 1700 | #define ADC12_CDR_RDATA_MST_1 ((uint32_t)0x00000002) /*!< RDATA_MST bit 1 */ |
bogdanm | 86:04dd9b1680ae | 1701 | #define ADC12_CDR_RDATA_MST_2 ((uint32_t)0x00000004) /*!< RDATA_MST bit 2 */ |
bogdanm | 86:04dd9b1680ae | 1702 | #define ADC12_CDR_RDATA_MST_3 ((uint32_t)0x00000008) /*!< RDATA_MST bit 3 */ |
bogdanm | 86:04dd9b1680ae | 1703 | #define ADC12_CDR_RDATA_MST_4 ((uint32_t)0x00000010) /*!< RDATA_MST bit 4 */ |
bogdanm | 86:04dd9b1680ae | 1704 | #define ADC12_CDR_RDATA_MST_5 ((uint32_t)0x00000020) /*!< RDATA_MST bit 5 */ |
bogdanm | 86:04dd9b1680ae | 1705 | #define ADC12_CDR_RDATA_MST_6 ((uint32_t)0x00000040) /*!< RDATA_MST bit 6 */ |
bogdanm | 86:04dd9b1680ae | 1706 | #define ADC12_CDR_RDATA_MST_7 ((uint32_t)0x00000080) /*!< RDATA_MST bit 7 */ |
bogdanm | 86:04dd9b1680ae | 1707 | #define ADC12_CDR_RDATA_MST_8 ((uint32_t)0x00000100) /*!< RDATA_MST bit 8 */ |
bogdanm | 86:04dd9b1680ae | 1708 | #define ADC12_CDR_RDATA_MST_9 ((uint32_t)0x00000200) /*!< RDATA_MST bit 9 */ |
bogdanm | 86:04dd9b1680ae | 1709 | #define ADC12_CDR_RDATA_MST_10 ((uint32_t)0x00000400) /*!< RDATA_MST bit 10 */ |
bogdanm | 86:04dd9b1680ae | 1710 | #define ADC12_CDR_RDATA_MST_11 ((uint32_t)0x00000800) /*!< RDATA_MST bit 11 */ |
bogdanm | 86:04dd9b1680ae | 1711 | #define ADC12_CDR_RDATA_MST_12 ((uint32_t)0x00001000) /*!< RDATA_MST bit 12 */ |
bogdanm | 86:04dd9b1680ae | 1712 | #define ADC12_CDR_RDATA_MST_13 ((uint32_t)0x00002000) /*!< RDATA_MST bit 13 */ |
bogdanm | 86:04dd9b1680ae | 1713 | #define ADC12_CDR_RDATA_MST_14 ((uint32_t)0x00004000) /*!< RDATA_MST bit 14 */ |
bogdanm | 86:04dd9b1680ae | 1714 | #define ADC12_CDR_RDATA_MST_15 ((uint32_t)0x00008000) /*!< RDATA_MST bit 15 */ |
bogdanm | 86:04dd9b1680ae | 1715 | |
bogdanm | 86:04dd9b1680ae | 1716 | #define ADC12_CDR_RDATA_SLV ((uint32_t)0xFFFF0000) /*!< Regular Data of the master ADC */ |
bogdanm | 86:04dd9b1680ae | 1717 | #define ADC12_CDR_RDATA_SLV_0 ((uint32_t)0x00010000) /*!< RDATA_SLV bit 0 */ |
bogdanm | 86:04dd9b1680ae | 1718 | #define ADC12_CDR_RDATA_SLV_1 ((uint32_t)0x00020000) /*!< RDATA_SLV bit 1 */ |
bogdanm | 86:04dd9b1680ae | 1719 | #define ADC12_CDR_RDATA_SLV_2 ((uint32_t)0x00040000) /*!< RDATA_SLV bit 2 */ |
bogdanm | 86:04dd9b1680ae | 1720 | #define ADC12_CDR_RDATA_SLV_3 ((uint32_t)0x00080000) /*!< RDATA_SLV bit 3 */ |
bogdanm | 86:04dd9b1680ae | 1721 | #define ADC12_CDR_RDATA_SLV_4 ((uint32_t)0x00100000) /*!< RDATA_SLV bit 4 */ |
bogdanm | 86:04dd9b1680ae | 1722 | #define ADC12_CDR_RDATA_SLV_5 ((uint32_t)0x00200000) /*!< RDATA_SLV bit 5 */ |
bogdanm | 86:04dd9b1680ae | 1723 | #define ADC12_CDR_RDATA_SLV_6 ((uint32_t)0x00400000) /*!< RDATA_SLV bit 6 */ |
bogdanm | 86:04dd9b1680ae | 1724 | #define ADC12_CDR_RDATA_SLV_7 ((uint32_t)0x00800000) /*!< RDATA_SLV bit 7 */ |
bogdanm | 86:04dd9b1680ae | 1725 | #define ADC12_CDR_RDATA_SLV_8 ((uint32_t)0x01000000) /*!< RDATA_SLV bit 8 */ |
bogdanm | 86:04dd9b1680ae | 1726 | #define ADC12_CDR_RDATA_SLV_9 ((uint32_t)0x02000000) /*!< RDATA_SLV bit 9 */ |
bogdanm | 86:04dd9b1680ae | 1727 | #define ADC12_CDR_RDATA_SLV_10 ((uint32_t)0x04000000) /*!< RDATA_SLV bit 10 */ |
bogdanm | 86:04dd9b1680ae | 1728 | #define ADC12_CDR_RDATA_SLV_11 ((uint32_t)0x08000000) /*!< RDATA_SLV bit 11 */ |
bogdanm | 86:04dd9b1680ae | 1729 | #define ADC12_CDR_RDATA_SLV_12 ((uint32_t)0x10000000) /*!< RDATA_SLV bit 12 */ |
bogdanm | 86:04dd9b1680ae | 1730 | #define ADC12_CDR_RDATA_SLV_13 ((uint32_t)0x20000000) /*!< RDATA_SLV bit 13 */ |
bogdanm | 86:04dd9b1680ae | 1731 | #define ADC12_CDR_RDATA_SLV_14 ((uint32_t)0x40000000) /*!< RDATA_SLV bit 14 */ |
bogdanm | 86:04dd9b1680ae | 1732 | #define ADC12_CDR_RDATA_SLV_15 ((uint32_t)0x80000000) /*!< RDATA_SLV bit 15 */ |
bogdanm | 86:04dd9b1680ae | 1733 | |
bogdanm | 86:04dd9b1680ae | 1734 | /******************************************************************************/ |
bogdanm | 86:04dd9b1680ae | 1735 | /* */ |
bogdanm | 86:04dd9b1680ae | 1736 | /* Analog Comparators (COMP) */ |
bogdanm | 86:04dd9b1680ae | 1737 | /* */ |
bogdanm | 86:04dd9b1680ae | 1738 | /******************************************************************************/ |
bogdanm | 86:04dd9b1680ae | 1739 | /********************** Bit definition for COMP2_CSR register ***************/ |
bogdanm | 86:04dd9b1680ae | 1740 | #define COMP2_CSR_COMP2EN ((uint32_t)0x00000001) /*!< COMP2 enable */ |
bogdanm | 86:04dd9b1680ae | 1741 | #define COMP2_CSR_COMP2INSEL ((uint32_t)0x00400070) /*!< COMP2 inverting input select */ |
bogdanm | 86:04dd9b1680ae | 1742 | #define COMP2_CSR_COMP2INSEL_0 ((uint32_t)0x00000010) /*!< COMP2 inverting input select bit 0 */ |
bogdanm | 86:04dd9b1680ae | 1743 | #define COMP2_CSR_COMP2INSEL_1 ((uint32_t)0x00000020) /*!< COMP2 inverting input select bit 1 */ |
bogdanm | 86:04dd9b1680ae | 1744 | #define COMP2_CSR_COMP2INSEL_2 ((uint32_t)0x00000040) /*!< COMP2 inverting input select bit 2 */ |
bogdanm | 86:04dd9b1680ae | 1745 | #define COMP2_CSR_COMP2INSEL_3 ((uint32_t)0x00400000) /*!< COMP2 inverting input select bit 3 */ |
bogdanm | 86:04dd9b1680ae | 1746 | #define COMP2_CSR_COMP2OUTSEL ((uint32_t)0x00003C00) /*!< COMP2 output select */ |
bogdanm | 86:04dd9b1680ae | 1747 | #define COMP2_CSR_COMP2OUTSEL_0 ((uint32_t)0x00000400) /*!< COMP2 output select bit 0 */ |
bogdanm | 86:04dd9b1680ae | 1748 | #define COMP2_CSR_COMP2OUTSEL_1 ((uint32_t)0x00000800) /*!< COMP2 output select bit 1 */ |
bogdanm | 86:04dd9b1680ae | 1749 | #define COMP2_CSR_COMP2OUTSEL_2 ((uint32_t)0x00001000) /*!< COMP2 output select bit 2 */ |
bogdanm | 86:04dd9b1680ae | 1750 | #define COMP2_CSR_COMP2OUTSEL_3 ((uint32_t)0x00002000) /*!< COMP2 output select bit 3 */ |
bogdanm | 86:04dd9b1680ae | 1751 | #define COMP2_CSR_COMP2POL ((uint32_t)0x00008000) /*!< COMP2 output polarity */ |
bogdanm | 86:04dd9b1680ae | 1752 | #define COMP2_CSR_COMP2BLANKING ((uint32_t)0x000C0000) /*!< COMP2 blanking */ |
bogdanm | 86:04dd9b1680ae | 1753 | #define COMP2_CSR_COMP2BLANKING_0 ((uint32_t)0x00040000) /*!< COMP2 blanking bit 0 */ |
bogdanm | 86:04dd9b1680ae | 1754 | #define COMP2_CSR_COMP2BLANKING_1 ((uint32_t)0x00080000) /*!< COMP2 blanking bit 1 */ |
bogdanm | 86:04dd9b1680ae | 1755 | #define COMP2_CSR_COMP2BLANKING_2 ((uint32_t)0x00100000) /*!< COMP2 blanking bit 2 */ |
bogdanm | 86:04dd9b1680ae | 1756 | #define COMP2_CSR_COMP2OUT ((uint32_t)0x40000000) /*!< COMP2 output level */ |
bogdanm | 86:04dd9b1680ae | 1757 | #define COMP2_CSR_COMP2LOCK ((uint32_t)0x80000000) /*!< COMP2 lock */ |
bogdanm | 86:04dd9b1680ae | 1758 | |
bogdanm | 86:04dd9b1680ae | 1759 | /********************** Bit definition for COMP4_CSR register ***************/ |
bogdanm | 86:04dd9b1680ae | 1760 | #define COMP4_CSR_COMP4EN ((uint32_t)0x00000001) /*!< COMP4 enable */ |
bogdanm | 86:04dd9b1680ae | 1761 | #define COMP4_CSR_COMP4INSEL ((uint32_t)0x00400070) /*!< COMP4 inverting input select */ |
bogdanm | 86:04dd9b1680ae | 1762 | #define COMP4_CSR_COMP4INSEL_0 ((uint32_t)0x00000010) /*!< COMP4 inverting input select bit 0 */ |
bogdanm | 86:04dd9b1680ae | 1763 | #define COMP4_CSR_COMP4INSEL_1 ((uint32_t)0x00000020) /*!< COMP4 inverting input select bit 1 */ |
bogdanm | 86:04dd9b1680ae | 1764 | #define COMP4_CSR_COMP4INSEL_2 ((uint32_t)0x00000040) /*!< COMP4 inverting input select bit 2 */ |
bogdanm | 86:04dd9b1680ae | 1765 | #define COMP4_CSR_COMP4INSEL_3 ((uint32_t)0x00400000) /*!< COMP4 inverting input select bit 3 */ |
bogdanm | 86:04dd9b1680ae | 1766 | #define COMP4_CSR_COMP4OUTSEL ((uint32_t)0x00003C00) /*!< COMP4 output select */ |
bogdanm | 86:04dd9b1680ae | 1767 | #define COMP4_CSR_COMP4OUTSEL_0 ((uint32_t)0x00000400) /*!< COMP4 output select bit 0 */ |
bogdanm | 86:04dd9b1680ae | 1768 | #define COMP4_CSR_COMP4OUTSEL_1 ((uint32_t)0x00000800) /*!< COMP4 output select bit 1 */ |
bogdanm | 86:04dd9b1680ae | 1769 | #define COMP4_CSR_COMP4OUTSEL_2 ((uint32_t)0x00001000) /*!< COMP4 output select bit 2 */ |
bogdanm | 86:04dd9b1680ae | 1770 | #define COMP4_CSR_COMP4OUTSEL_3 ((uint32_t)0x00002000) /*!< COMP4 output select bit 3 */ |
bogdanm | 86:04dd9b1680ae | 1771 | #define COMP4_CSR_COMP4POL ((uint32_t)0x00008000) /*!< COMP4 output polarity */ |
bogdanm | 86:04dd9b1680ae | 1772 | #define COMP4_CSR_COMP4BLANKING ((uint32_t)0x000C0000) /*!< COMP4 blanking */ |
bogdanm | 86:04dd9b1680ae | 1773 | #define COMP4_CSR_COMP4BLANKING_0 ((uint32_t)0x00040000) /*!< COMP4 blanking bit 0 */ |
bogdanm | 86:04dd9b1680ae | 1774 | #define COMP4_CSR_COMP4BLANKING_1 ((uint32_t)0x00080000) /*!< COMP4 blanking bit 1 */ |
bogdanm | 86:04dd9b1680ae | 1775 | #define COMP4_CSR_COMP4BLANKING_2 ((uint32_t)0x00100000) /*!< COMP4 blanking bit 2 */ |
bogdanm | 86:04dd9b1680ae | 1776 | #define COMP4_CSR_COMP4OUT ((uint32_t)0x40000000) /*!< COMP4 output level */ |
bogdanm | 86:04dd9b1680ae | 1777 | #define COMP4_CSR_COMP4LOCK ((uint32_t)0x80000000) /*!< COMP4 lock */ |
bogdanm | 86:04dd9b1680ae | 1778 | |
bogdanm | 86:04dd9b1680ae | 1779 | /********************** Bit definition for COMP6_CSR register ***************/ |
bogdanm | 86:04dd9b1680ae | 1780 | #define COMP6_CSR_COMP6EN ((uint32_t)0x00000001) /*!< COMP6 enable */ |
bogdanm | 86:04dd9b1680ae | 1781 | #define COMP6_CSR_COMP6INSEL ((uint32_t)0x00400070) /*!< COMP6 inverting input select */ |
bogdanm | 86:04dd9b1680ae | 1782 | #define COMP6_CSR_COMP6INSEL_0 ((uint32_t)0x00000010) /*!< COMP6 inverting input select bit 0 */ |
bogdanm | 86:04dd9b1680ae | 1783 | #define COMP6_CSR_COMP6INSEL_1 ((uint32_t)0x00000020) /*!< COMP6 inverting input select bit 1 */ |
bogdanm | 86:04dd9b1680ae | 1784 | #define COMP6_CSR_COMP6INSEL_2 ((uint32_t)0x00000040) /*!< COMP6 inverting input select bit 2 */ |
bogdanm | 86:04dd9b1680ae | 1785 | #define COMP6_CSR_COMP6INSEL_3 ((uint32_t)0x00400000) /*!< COMP6 inverting input select bit 3 */ |
bogdanm | 86:04dd9b1680ae | 1786 | #define COMP6_CSR_COMP6OUTSEL ((uint32_t)0x00003C00) /*!< COMP6 output select */ |
bogdanm | 86:04dd9b1680ae | 1787 | #define COMP6_CSR_COMP6OUTSEL_0 ((uint32_t)0x00000400) /*!< COMP6 output select bit 0 */ |
bogdanm | 86:04dd9b1680ae | 1788 | #define COMP6_CSR_COMP6OUTSEL_1 ((uint32_t)0x00000800) /*!< COMP6 output select bit 1 */ |
bogdanm | 86:04dd9b1680ae | 1789 | #define COMP6_CSR_COMP6OUTSEL_2 ((uint32_t)0x00001000) /*!< COMP6 output select bit 2 */ |
bogdanm | 86:04dd9b1680ae | 1790 | #define COMP6_CSR_COMP6OUTSEL_3 ((uint32_t)0x00002000) /*!< COMP6 output select bit 3 */ |
bogdanm | 86:04dd9b1680ae | 1791 | #define COMP6_CSR_COMP6POL ((uint32_t)0x00008000) /*!< COMP6 output polarity */ |
bogdanm | 86:04dd9b1680ae | 1792 | #define COMP6_CSR_COMP6BLANKING ((uint32_t)0x000C0000) /*!< COMP6 blanking */ |
bogdanm | 86:04dd9b1680ae | 1793 | #define COMP6_CSR_COMP6BLANKING_0 ((uint32_t)0x00040000) /*!< COMP6 blanking bit 0 */ |
bogdanm | 86:04dd9b1680ae | 1794 | #define COMP6_CSR_COMP6BLANKING_1 ((uint32_t)0x00080000) /*!< COMP6 blanking bit 1 */ |
bogdanm | 86:04dd9b1680ae | 1795 | #define COMP6_CSR_COMP6BLANKING_2 ((uint32_t)0x00100000) /*!< COMP6 blanking bit 2 */ |
bogdanm | 86:04dd9b1680ae | 1796 | #define COMP6_CSR_COMP6OUT ((uint32_t)0x40000000) /*!< COMP6 output level */ |
bogdanm | 86:04dd9b1680ae | 1797 | #define COMP6_CSR_COMP6LOCK ((uint32_t)0x80000000) /*!< COMP6 lock */ |
bogdanm | 86:04dd9b1680ae | 1798 | |
bogdanm | 86:04dd9b1680ae | 1799 | /********************** Bit definition for COMP_CSR register ****************/ |
bogdanm | 86:04dd9b1680ae | 1800 | #define COMP_CSR_COMPxEN ((uint32_t)0x00000001) /*!< COMPx enable */ |
bogdanm | 86:04dd9b1680ae | 1801 | #define COMP_CSR_COMPxINSEL ((uint32_t)0x00400070) /*!< COMPx inverting input select */ |
bogdanm | 86:04dd9b1680ae | 1802 | #define COMP_CSR_COMPxINSEL_0 ((uint32_t)0x00000010) /*!< COMPx inverting input select bit 0 */ |
bogdanm | 86:04dd9b1680ae | 1803 | #define COMP_CSR_COMPxINSEL_1 ((uint32_t)0x00000020) /*!< COMPx inverting input select bit 1 */ |
bogdanm | 86:04dd9b1680ae | 1804 | #define COMP_CSR_COMPxINSEL_2 ((uint32_t)0x00000040) /*!< COMPx inverting input select bit 2 */ |
bogdanm | 86:04dd9b1680ae | 1805 | #define COMP_CSR_COMPxINSEL_3 ((uint32_t)0x00400000) /*!< COMPx inverting input select bit 3 */ |
bogdanm | 86:04dd9b1680ae | 1806 | #define COMP_CSR_COMPxOUTSEL ((uint32_t)0x00003C00) /*!< COMPx output select */ |
bogdanm | 86:04dd9b1680ae | 1807 | #define COMP_CSR_COMPxOUTSEL_0 ((uint32_t)0x00000400) /*!< COMPx output select bit 0 */ |
bogdanm | 86:04dd9b1680ae | 1808 | #define COMP_CSR_COMPxOUTSEL_1 ((uint32_t)0x00000800) /*!< COMPx output select bit 1 */ |
bogdanm | 86:04dd9b1680ae | 1809 | #define COMP_CSR_COMPxOUTSEL_2 ((uint32_t)0x00001000) /*!< COMPx output select bit 2 */ |
bogdanm | 86:04dd9b1680ae | 1810 | #define COMP_CSR_COMPxOUTSEL_3 ((uint32_t)0x00002000) /*!< COMPx output select bit 3 */ |
bogdanm | 86:04dd9b1680ae | 1811 | #define COMP_CSR_COMPxPOL ((uint32_t)0x00008000) /*!< COMPx output polarity */ |
bogdanm | 86:04dd9b1680ae | 1812 | #define COMP_CSR_COMPxBLANKING ((uint32_t)0x000C0000) /*!< COMPx blanking */ |
bogdanm | 86:04dd9b1680ae | 1813 | #define COMP_CSR_COMPxBLANKING_0 ((uint32_t)0x00040000) /*!< COMPx blanking bit 0 */ |
bogdanm | 86:04dd9b1680ae | 1814 | #define COMP_CSR_COMPxBLANKING_1 ((uint32_t)0x00080000) /*!< COMPx blanking bit 1 */ |
bogdanm | 86:04dd9b1680ae | 1815 | #define COMP_CSR_COMPxBLANKING_2 ((uint32_t)0x00100000) /*!< COMPx blanking bit 2 */ |
bogdanm | 86:04dd9b1680ae | 1816 | #define COMP_CSR_COMPxOUT ((uint32_t)0x40000000) /*!< COMPx output level */ |
bogdanm | 86:04dd9b1680ae | 1817 | #define COMP_CSR_COMPxLOCK ((uint32_t)0x80000000) /*!< COMPx lock */ |
bogdanm | 86:04dd9b1680ae | 1818 | |
bogdanm | 86:04dd9b1680ae | 1819 | /******************************************************************************/ |
bogdanm | 86:04dd9b1680ae | 1820 | /* */ |
bogdanm | 86:04dd9b1680ae | 1821 | /* Operational Amplifier (OPAMP) */ |
bogdanm | 86:04dd9b1680ae | 1822 | /* */ |
bogdanm | 86:04dd9b1680ae | 1823 | /******************************************************************************/ |
bogdanm | 86:04dd9b1680ae | 1824 | /********************* Bit definition for OPAMP2_CSR register ***************/ |
bogdanm | 86:04dd9b1680ae | 1825 | #define OPAMP2_CSR_OPAMP2EN ((uint32_t)0x00000001) /*!< OPAMP2 enable */ |
bogdanm | 86:04dd9b1680ae | 1826 | #define OPAMP2_CSR_FORCEVP ((uint32_t)0x00000002) /*!< Connect the internal references to the plus input of the OPAMPX */ |
bogdanm | 86:04dd9b1680ae | 1827 | #define OPAMP2_CSR_VPSEL ((uint32_t)0x0000000C) /*!< Non inverting input selection */ |
bogdanm | 86:04dd9b1680ae | 1828 | #define OPAMP2_CSR_VPSEL_0 ((uint32_t)0x00000004) /*!< Bit 0 */ |
bogdanm | 86:04dd9b1680ae | 1829 | #define OPAMP2_CSR_VPSEL_1 ((uint32_t)0x00000008) /*!< Bit 1 */ |
bogdanm | 86:04dd9b1680ae | 1830 | #define OPAMP2_CSR_VMSEL ((uint32_t)0x00000060) /*!< Inverting input selection */ |
bogdanm | 86:04dd9b1680ae | 1831 | #define OPAMP2_CSR_VMSEL_0 ((uint32_t)0x00000020) /*!< Bit 0 */ |
bogdanm | 86:04dd9b1680ae | 1832 | #define OPAMP2_CSR_VMSEL_1 ((uint32_t)0x00000040) /*!< Bit 1 */ |
bogdanm | 86:04dd9b1680ae | 1833 | #define OPAMP2_CSR_TCMEN ((uint32_t)0x00000080) /*!< Timer-Controlled Mux mode enable */ |
bogdanm | 86:04dd9b1680ae | 1834 | #define OPAMP2_CSR_VMSSEL ((uint32_t)0x00000100) /*!< Inverting input secondary selection */ |
bogdanm | 86:04dd9b1680ae | 1835 | #define OPAMP2_CSR_VPSSEL ((uint32_t)0x00000600) /*!< Non inverting input secondary selection */ |
bogdanm | 86:04dd9b1680ae | 1836 | #define OPAMP2_CSR_VPSSEL_0 ((uint32_t)0x00000200) /*!< Bit 0 */ |
bogdanm | 86:04dd9b1680ae | 1837 | #define OPAMP2_CSR_VPSSEL_1 ((uint32_t)0x00000400) /*!< Bit 1 */ |
bogdanm | 86:04dd9b1680ae | 1838 | #define OPAMP2_CSR_CALON ((uint32_t)0x00000800) /*!< Calibration mode enable */ |
bogdanm | 86:04dd9b1680ae | 1839 | #define OPAMP2_CSR_CALSEL ((uint32_t)0x00003000) /*!< Calibration selection */ |
bogdanm | 86:04dd9b1680ae | 1840 | #define OPAMP2_CSR_CALSEL_0 ((uint32_t)0x00001000) /*!< Bit 0 */ |
bogdanm | 86:04dd9b1680ae | 1841 | #define OPAMP2_CSR_CALSEL_1 ((uint32_t)0x00002000) /*!< Bit 1 */ |
bogdanm | 86:04dd9b1680ae | 1842 | #define OPAMP2_CSR_PGGAIN ((uint32_t)0x0003C000) /*!< Gain in PGA mode */ |
bogdanm | 86:04dd9b1680ae | 1843 | #define OPAMP2_CSR_PGGAIN_0 ((uint32_t)0x00004000) /*!< Bit 0 */ |
bogdanm | 86:04dd9b1680ae | 1844 | #define OPAMP2_CSR_PGGAIN_1 ((uint32_t)0x00008000) /*!< Bit 1 */ |
bogdanm | 86:04dd9b1680ae | 1845 | #define OPAMP2_CSR_PGGAIN_2 ((uint32_t)0x00010000) /*!< Bit 2 */ |
bogdanm | 86:04dd9b1680ae | 1846 | #define OPAMP2_CSR_PGGAIN_3 ((uint32_t)0x00020000) /*!< Bit 3 */ |
bogdanm | 86:04dd9b1680ae | 1847 | #define OPAMP2_CSR_USERTRIM ((uint32_t)0x00040000) /*!< User trimming enable */ |
bogdanm | 86:04dd9b1680ae | 1848 | #define OPAMP2_CSR_TRIMOFFSETP ((uint32_t)0x00F80000) /*!< Offset trimming value (PMOS) */ |
bogdanm | 86:04dd9b1680ae | 1849 | #define OPAMP2_CSR_TRIMOFFSETN ((uint32_t)0x1F000000) /*!< Offset trimming value (NMOS) */ |
bogdanm | 86:04dd9b1680ae | 1850 | #define OPAMP2_CSR_TSTREF ((uint32_t)0x20000000) /*!< It enables the switch to put out the internal reference */ |
bogdanm | 86:04dd9b1680ae | 1851 | #define OPAMP2_CSR_OUTCAL ((uint32_t)0x40000000) /*!< OPAMP ouput status flag */ |
bogdanm | 86:04dd9b1680ae | 1852 | #define OPAMP2_CSR_LOCK ((uint32_t)0x80000000) /*!< OPAMP lock */ |
bogdanm | 86:04dd9b1680ae | 1853 | |
bogdanm | 86:04dd9b1680ae | 1854 | /********************* Bit definition for OPAMPx_CSR register ***************/ |
bogdanm | 86:04dd9b1680ae | 1855 | #define OPAMP_CSR_OPAMPxEN ((uint32_t)0x00000001) /*!< OPAMP enable */ |
bogdanm | 86:04dd9b1680ae | 1856 | #define OPAMP_CSR_FORCEVP ((uint32_t)0x00000002) /*!< Connect the internal references to the plus input of the OPAMPX */ |
bogdanm | 86:04dd9b1680ae | 1857 | #define OPAMP_CSR_VPSEL ((uint32_t)0x0000000C) /*!< Non inverting input selection */ |
bogdanm | 86:04dd9b1680ae | 1858 | #define OPAMP_CSR_VPSEL_0 ((uint32_t)0x00000004) /*!< Bit 0 */ |
bogdanm | 86:04dd9b1680ae | 1859 | #define OPAMP_CSR_VPSEL_1 ((uint32_t)0x00000008) /*!< Bit 1 */ |
bogdanm | 86:04dd9b1680ae | 1860 | #define OPAMP_CSR_VMSEL ((uint32_t)0x00000060) /*!< Inverting input selection */ |
bogdanm | 86:04dd9b1680ae | 1861 | #define OPAMP_CSR_VMSEL_0 ((uint32_t)0x00000020) /*!< Bit 0 */ |
bogdanm | 86:04dd9b1680ae | 1862 | #define OPAMP_CSR_VMSEL_1 ((uint32_t)0x00000040) /*!< Bit 1 */ |
bogdanm | 86:04dd9b1680ae | 1863 | #define OPAMP_CSR_TCMEN ((uint32_t)0x00000080) /*!< Timer-Controlled Mux mode enable */ |
bogdanm | 86:04dd9b1680ae | 1864 | #define OPAMP_CSR_VMSSEL ((uint32_t)0x00000100) /*!< Inverting input secondary selection */ |
bogdanm | 86:04dd9b1680ae | 1865 | #define OPAMP_CSR_VPSSEL ((uint32_t)0x00000600) /*!< Non inverting input secondary selection */ |
bogdanm | 86:04dd9b1680ae | 1866 | #define OPAMP_CSR_VPSSEL_0 ((uint32_t)0x00000200) /*!< Bit 0 */ |
bogdanm | 86:04dd9b1680ae | 1867 | #define OPAMP_CSR_VPSSEL_1 ((uint32_t)0x00000400) /*!< Bit 1 */ |
bogdanm | 86:04dd9b1680ae | 1868 | #define OPAMP_CSR_CALON ((uint32_t)0x00000800) /*!< Calibration mode enable */ |
bogdanm | 86:04dd9b1680ae | 1869 | #define OPAMP_CSR_CALSEL ((uint32_t)0x00003000) /*!< Calibration selection */ |
bogdanm | 86:04dd9b1680ae | 1870 | #define OPAMP_CSR_CALSEL_0 ((uint32_t)0x00001000) /*!< Bit 0 */ |
bogdanm | 86:04dd9b1680ae | 1871 | #define OPAMP_CSR_CALSEL_1 ((uint32_t)0x00002000) /*!< Bit 1 */ |
bogdanm | 86:04dd9b1680ae | 1872 | #define OPAMP_CSR_PGGAIN ((uint32_t)0x0003C000) /*!< Gain in PGA mode */ |
bogdanm | 86:04dd9b1680ae | 1873 | #define OPAMP_CSR_PGGAIN_0 ((uint32_t)0x00004000) /*!< Bit 0 */ |
bogdanm | 86:04dd9b1680ae | 1874 | #define OPAMP_CSR_PGGAIN_1 ((uint32_t)0x00008000) /*!< Bit 1 */ |
bogdanm | 86:04dd9b1680ae | 1875 | #define OPAMP_CSR_PGGAIN_2 ((uint32_t)0x00010000) /*!< Bit 2 */ |
bogdanm | 86:04dd9b1680ae | 1876 | #define OPAMP_CSR_PGGAIN_3 ((uint32_t)0x00020000) /*!< Bit 3 */ |
bogdanm | 86:04dd9b1680ae | 1877 | #define OPAMP_CSR_USERTRIM ((uint32_t)0x00040000) /*!< User trimming enable */ |
bogdanm | 86:04dd9b1680ae | 1878 | #define OPAMP_CSR_TRIMOFFSETP ((uint32_t)0x00F80000) /*!< Offset trimming value (PMOS) */ |
bogdanm | 86:04dd9b1680ae | 1879 | #define OPAMP_CSR_TRIMOFFSETN ((uint32_t)0x1F000000) /*!< Offset trimming value (NMOS) */ |
bogdanm | 86:04dd9b1680ae | 1880 | #define OPAMP_CSR_TSTREF ((uint32_t)0x20000000) /*!< It enables the switch to put out the internal reference */ |
bogdanm | 86:04dd9b1680ae | 1881 | #define OPAMP_CSR_OUTCAL ((uint32_t)0x40000000) /*!< OPAMP ouput status flag */ |
bogdanm | 86:04dd9b1680ae | 1882 | #define OPAMP_CSR_LOCK ((uint32_t)0x80000000) /*!< OPAMP lock */ |
bogdanm | 86:04dd9b1680ae | 1883 | |
bogdanm | 86:04dd9b1680ae | 1884 | /******************************************************************************/ |
bogdanm | 86:04dd9b1680ae | 1885 | /* */ |
bogdanm | 86:04dd9b1680ae | 1886 | /* Controller Area Network (CAN ) */ |
bogdanm | 86:04dd9b1680ae | 1887 | /* */ |
bogdanm | 86:04dd9b1680ae | 1888 | /******************************************************************************/ |
bogdanm | 86:04dd9b1680ae | 1889 | /******************* Bit definition for CAN_MCR register ********************/ |
bogdanm | 86:04dd9b1680ae | 1890 | #define CAN_MCR_INRQ ((uint32_t)0x00000001) /*!<Initialization Request */ |
bogdanm | 86:04dd9b1680ae | 1891 | #define CAN_MCR_SLEEP ((uint32_t)0x00000002) /*!<Sleep Mode Request */ |
bogdanm | 86:04dd9b1680ae | 1892 | #define CAN_MCR_TXFP ((uint32_t)0x00000004) /*!<Transmit FIFO Priority */ |
bogdanm | 86:04dd9b1680ae | 1893 | #define CAN_MCR_RFLM ((uint32_t)0x00000008) /*!<Receive FIFO Locked Mode */ |
bogdanm | 86:04dd9b1680ae | 1894 | #define CAN_MCR_NART ((uint32_t)0x00000010) /*!<No Automatic Retransmission */ |
bogdanm | 86:04dd9b1680ae | 1895 | #define CAN_MCR_AWUM ((uint32_t)0x00000020) /*!<Automatic Wakeup Mode */ |
bogdanm | 86:04dd9b1680ae | 1896 | #define CAN_MCR_ABOM ((uint32_t)0x00000040) /*!<Automatic Bus-Off Management */ |
bogdanm | 86:04dd9b1680ae | 1897 | #define CAN_MCR_TTCM ((uint32_t)0x00000080) /*!<Time Triggered Communication Mode */ |
bogdanm | 86:04dd9b1680ae | 1898 | #define CAN_MCR_RESET ((uint32_t)0x00008000) /*!<bxCAN software master reset */ |
bogdanm | 86:04dd9b1680ae | 1899 | |
bogdanm | 86:04dd9b1680ae | 1900 | /******************* Bit definition for CAN_MSR register ********************/ |
bogdanm | 86:04dd9b1680ae | 1901 | #define CAN_MSR_INAK ((uint32_t)0x00000001) /*!<Initialization Acknowledge */ |
bogdanm | 86:04dd9b1680ae | 1902 | #define CAN_MSR_SLAK ((uint32_t)0x00000002) /*!<Sleep Acknowledge */ |
bogdanm | 86:04dd9b1680ae | 1903 | #define CAN_MSR_ERRI ((uint32_t)0x00000004) /*!<Error Interrupt */ |
bogdanm | 86:04dd9b1680ae | 1904 | #define CAN_MSR_WKUI ((uint32_t)0x00000008) /*!<Wakeup Interrupt */ |
bogdanm | 86:04dd9b1680ae | 1905 | #define CAN_MSR_SLAKI ((uint32_t)0x00000010) /*!<Sleep Acknowledge Interrupt */ |
bogdanm | 86:04dd9b1680ae | 1906 | #define CAN_MSR_TXM ((uint32_t)0x00000100) /*!<Transmit Mode */ |
bogdanm | 86:04dd9b1680ae | 1907 | #define CAN_MSR_RXM ((uint32_t)0x00000200) /*!<Receive Mode */ |
bogdanm | 86:04dd9b1680ae | 1908 | #define CAN_MSR_SAMP ((uint32_t)0x00000400) /*!<Last Sample Point */ |
bogdanm | 86:04dd9b1680ae | 1909 | #define CAN_MSR_RX ((uint32_t)0x00000800) /*!<CAN Rx Signal */ |
bogdanm | 86:04dd9b1680ae | 1910 | |
bogdanm | 86:04dd9b1680ae | 1911 | /******************* Bit definition for CAN_TSR register ********************/ |
bogdanm | 86:04dd9b1680ae | 1912 | #define CAN_TSR_RQCP0 ((uint32_t)0x00000001) /*!<Request Completed Mailbox0 */ |
bogdanm | 86:04dd9b1680ae | 1913 | #define CAN_TSR_TXOK0 ((uint32_t)0x00000002) /*!<Transmission OK of Mailbox0 */ |
bogdanm | 86:04dd9b1680ae | 1914 | #define CAN_TSR_ALST0 ((uint32_t)0x00000004) /*!<Arbitration Lost for Mailbox0 */ |
bogdanm | 86:04dd9b1680ae | 1915 | #define CAN_TSR_TERR0 ((uint32_t)0x00000008) /*!<Transmission Error of Mailbox0 */ |
bogdanm | 86:04dd9b1680ae | 1916 | #define CAN_TSR_ABRQ0 ((uint32_t)0x00000080) /*!<Abort Request for Mailbox0 */ |
bogdanm | 86:04dd9b1680ae | 1917 | #define CAN_TSR_RQCP1 ((uint32_t)0x00000100) /*!<Request Completed Mailbox1 */ |
bogdanm | 86:04dd9b1680ae | 1918 | #define CAN_TSR_TXOK1 ((uint32_t)0x00000200) /*!<Transmission OK of Mailbox1 */ |
bogdanm | 86:04dd9b1680ae | 1919 | #define CAN_TSR_ALST1 ((uint32_t)0x00000400) /*!<Arbitration Lost for Mailbox1 */ |
bogdanm | 86:04dd9b1680ae | 1920 | #define CAN_TSR_TERR1 ((uint32_t)0x00000800) /*!<Transmission Error of Mailbox1 */ |
bogdanm | 86:04dd9b1680ae | 1921 | #define CAN_TSR_ABRQ1 ((uint32_t)0x00008000) /*!<Abort Request for Mailbox 1 */ |
bogdanm | 86:04dd9b1680ae | 1922 | #define CAN_TSR_RQCP2 ((uint32_t)0x00010000) /*!<Request Completed Mailbox2 */ |
bogdanm | 86:04dd9b1680ae | 1923 | #define CAN_TSR_TXOK2 ((uint32_t)0x00020000) /*!<Transmission OK of Mailbox 2 */ |
bogdanm | 86:04dd9b1680ae | 1924 | #define CAN_TSR_ALST2 ((uint32_t)0x00040000) /*!<Arbitration Lost for mailbox 2 */ |
bogdanm | 86:04dd9b1680ae | 1925 | #define CAN_TSR_TERR2 ((uint32_t)0x00080000) /*!<Transmission Error of Mailbox 2 */ |
bogdanm | 86:04dd9b1680ae | 1926 | #define CAN_TSR_ABRQ2 ((uint32_t)0x00800000) /*!<Abort Request for Mailbox 2 */ |
bogdanm | 86:04dd9b1680ae | 1927 | #define CAN_TSR_CODE ((uint32_t)0x03000000) /*!<Mailbox Code */ |
bogdanm | 86:04dd9b1680ae | 1928 | |
bogdanm | 86:04dd9b1680ae | 1929 | #define CAN_TSR_TME ((uint32_t)0x1C000000) /*!<TME[2:0] bits */ |
bogdanm | 86:04dd9b1680ae | 1930 | #define CAN_TSR_TME0 ((uint32_t)0x04000000) /*!<Transmit Mailbox 0 Empty */ |
bogdanm | 86:04dd9b1680ae | 1931 | #define CAN_TSR_TME1 ((uint32_t)0x08000000) /*!<Transmit Mailbox 1 Empty */ |
bogdanm | 86:04dd9b1680ae | 1932 | #define CAN_TSR_TME2 ((uint32_t)0x10000000) /*!<Transmit Mailbox 2 Empty */ |
bogdanm | 86:04dd9b1680ae | 1933 | |
bogdanm | 86:04dd9b1680ae | 1934 | #define CAN_TSR_LOW ((uint32_t)0xE0000000) /*!<LOW[2:0] bits */ |
bogdanm | 86:04dd9b1680ae | 1935 | #define CAN_TSR_LOW0 ((uint32_t)0x20000000) /*!<Lowest Priority Flag for Mailbox 0 */ |
bogdanm | 86:04dd9b1680ae | 1936 | #define CAN_TSR_LOW1 ((uint32_t)0x40000000) /*!<Lowest Priority Flag for Mailbox 1 */ |
bogdanm | 86:04dd9b1680ae | 1937 | #define CAN_TSR_LOW2 ((uint32_t)0x80000000) /*!<Lowest Priority Flag for Mailbox 2 */ |
bogdanm | 86:04dd9b1680ae | 1938 | |
bogdanm | 86:04dd9b1680ae | 1939 | /******************* Bit definition for CAN_RF0R register *******************/ |
bogdanm | 86:04dd9b1680ae | 1940 | #define CAN_RF0R_FMP0 ((uint32_t)0x00000003) /*!<FIFO 0 Message Pending */ |
bogdanm | 86:04dd9b1680ae | 1941 | #define CAN_RF0R_FULL0 ((uint32_t)0x00000008) /*!<FIFO 0 Full */ |
bogdanm | 86:04dd9b1680ae | 1942 | #define CAN_RF0R_FOVR0 ((uint32_t)0x00000010) /*!<FIFO 0 Overrun */ |
bogdanm | 86:04dd9b1680ae | 1943 | #define CAN_RF0R_RFOM0 ((uint32_t)0x00000020) /*!<Release FIFO 0 Output Mailbox */ |
bogdanm | 86:04dd9b1680ae | 1944 | |
bogdanm | 86:04dd9b1680ae | 1945 | /******************* Bit definition for CAN_RF1R register *******************/ |
bogdanm | 86:04dd9b1680ae | 1946 | #define CAN_RF1R_FMP1 ((uint32_t)0x00000003) /*!<FIFO 1 Message Pending */ |
bogdanm | 86:04dd9b1680ae | 1947 | #define CAN_RF1R_FULL1 ((uint32_t)0x00000008) /*!<FIFO 1 Full */ |
bogdanm | 86:04dd9b1680ae | 1948 | #define CAN_RF1R_FOVR1 ((uint32_t)0x00000010) /*!<FIFO 1 Overrun */ |
bogdanm | 86:04dd9b1680ae | 1949 | #define CAN_RF1R_RFOM1 ((uint32_t)0x00000020) /*!<Release FIFO 1 Output Mailbox */ |
bogdanm | 86:04dd9b1680ae | 1950 | |
bogdanm | 86:04dd9b1680ae | 1951 | /******************** Bit definition for CAN_IER register *******************/ |
bogdanm | 86:04dd9b1680ae | 1952 | #define CAN_IER_TMEIE ((uint32_t)0x00000001) /*!<Transmit Mailbox Empty Interrupt Enable */ |
bogdanm | 86:04dd9b1680ae | 1953 | #define CAN_IER_FMPIE0 ((uint32_t)0x00000002) /*!<FIFO Message Pending Interrupt Enable */ |
bogdanm | 86:04dd9b1680ae | 1954 | #define CAN_IER_FFIE0 ((uint32_t)0x00000004) /*!<FIFO Full Interrupt Enable */ |
bogdanm | 86:04dd9b1680ae | 1955 | #define CAN_IER_FOVIE0 ((uint32_t)0x00000008) /*!<FIFO Overrun Interrupt Enable */ |
bogdanm | 86:04dd9b1680ae | 1956 | #define CAN_IER_FMPIE1 ((uint32_t)0x00000010) /*!<FIFO Message Pending Interrupt Enable */ |
bogdanm | 86:04dd9b1680ae | 1957 | #define CAN_IER_FFIE1 ((uint32_t)0x00000020) /*!<FIFO Full Interrupt Enable */ |
bogdanm | 86:04dd9b1680ae | 1958 | #define CAN_IER_FOVIE1 ((uint32_t)0x00000040) /*!<FIFO Overrun Interrupt Enable */ |
bogdanm | 86:04dd9b1680ae | 1959 | #define CAN_IER_EWGIE ((uint32_t)0x00000100) /*!<Error Warning Interrupt Enable */ |
bogdanm | 86:04dd9b1680ae | 1960 | #define CAN_IER_EPVIE ((uint32_t)0x00000200) /*!<Error Passive Interrupt Enable */ |
bogdanm | 86:04dd9b1680ae | 1961 | #define CAN_IER_BOFIE ((uint32_t)0x00000400) /*!<Bus-Off Interrupt Enable */ |
bogdanm | 86:04dd9b1680ae | 1962 | #define CAN_IER_LECIE ((uint32_t)0x00000800) /*!<Last Error Code Interrupt Enable */ |
bogdanm | 86:04dd9b1680ae | 1963 | #define CAN_IER_ERRIE ((uint32_t)0x00008000) /*!<Error Interrupt Enable */ |
bogdanm | 86:04dd9b1680ae | 1964 | #define CAN_IER_WKUIE ((uint32_t)0x00010000) /*!<Wakeup Interrupt Enable */ |
bogdanm | 86:04dd9b1680ae | 1965 | #define CAN_IER_SLKIE ((uint32_t)0x00020000) /*!<Sleep Interrupt Enable */ |
bogdanm | 86:04dd9b1680ae | 1966 | |
bogdanm | 86:04dd9b1680ae | 1967 | /******************** Bit definition for CAN_ESR register *******************/ |
bogdanm | 86:04dd9b1680ae | 1968 | #define CAN_ESR_EWGF ((uint32_t)0x00000001) /*!<Error Warning Flag */ |
bogdanm | 86:04dd9b1680ae | 1969 | #define CAN_ESR_EPVF ((uint32_t)0x00000002) /*!<Error Passive Flag */ |
bogdanm | 86:04dd9b1680ae | 1970 | #define CAN_ESR_BOFF ((uint32_t)0x00000004) /*!<Bus-Off Flag */ |
bogdanm | 86:04dd9b1680ae | 1971 | |
bogdanm | 86:04dd9b1680ae | 1972 | #define CAN_ESR_LEC ((uint32_t)0x00000070) /*!<LEC[2:0] bits (Last Error Code) */ |
bogdanm | 86:04dd9b1680ae | 1973 | #define CAN_ESR_LEC_0 ((uint32_t)0x00000010) /*!<Bit 0 */ |
bogdanm | 86:04dd9b1680ae | 1974 | #define CAN_ESR_LEC_1 ((uint32_t)0x00000020) /*!<Bit 1 */ |
bogdanm | 86:04dd9b1680ae | 1975 | #define CAN_ESR_LEC_2 ((uint32_t)0x00000040) /*!<Bit 2 */ |
bogdanm | 86:04dd9b1680ae | 1976 | |
bogdanm | 86:04dd9b1680ae | 1977 | #define CAN_ESR_TEC ((uint32_t)0x00FF0000) /*!<Least significant byte of the 9-bit Transmit Error Counter */ |
bogdanm | 86:04dd9b1680ae | 1978 | #define CAN_ESR_REC ((uint32_t)0xFF000000) /*!<Receive Error Counter */ |
bogdanm | 86:04dd9b1680ae | 1979 | |
bogdanm | 86:04dd9b1680ae | 1980 | /******************* Bit definition for CAN_BTR register ********************/ |
bogdanm | 86:04dd9b1680ae | 1981 | #define CAN_BTR_BRP ((uint32_t)0x000003FF) /*!<Baud Rate Prescaler */ |
bogdanm | 86:04dd9b1680ae | 1982 | #define CAN_BTR_TS1 ((uint32_t)0x000F0000) /*!<Time Segment 1 */ |
bogdanm | 86:04dd9b1680ae | 1983 | #define CAN_BTR_TS1_0 ((uint32_t)0x00010000) /*!<Time Segment 1 (Bit 0) */ |
bogdanm | 86:04dd9b1680ae | 1984 | #define CAN_BTR_TS1_1 ((uint32_t)0x00020000) /*!<Time Segment 1 (Bit 1) */ |
bogdanm | 86:04dd9b1680ae | 1985 | #define CAN_BTR_TS1_2 ((uint32_t)0x00040000) /*!<Time Segment 1 (Bit 2) */ |
bogdanm | 86:04dd9b1680ae | 1986 | #define CAN_BTR_TS1_3 ((uint32_t)0x00080000) /*!<Time Segment 1 (Bit 3) */ |
bogdanm | 86:04dd9b1680ae | 1987 | #define CAN_BTR_TS2 ((uint32_t)0x00700000) /*!<Time Segment 2 */ |
bogdanm | 86:04dd9b1680ae | 1988 | #define CAN_BTR_TS2_0 ((uint32_t)0x00100000) /*!<Time Segment 2 (Bit 0) */ |
bogdanm | 86:04dd9b1680ae | 1989 | #define CAN_BTR_TS2_1 ((uint32_t)0x00200000) /*!<Time Segment 2 (Bit 1) */ |
bogdanm | 86:04dd9b1680ae | 1990 | #define CAN_BTR_TS2_2 ((uint32_t)0x00400000) /*!<Time Segment 2 (Bit 2) */ |
bogdanm | 86:04dd9b1680ae | 1991 | #define CAN_BTR_SJW ((uint32_t)0x03000000) /*!<Resynchronization Jump Width */ |
bogdanm | 86:04dd9b1680ae | 1992 | #define CAN_BTR_SJW_0 ((uint32_t)0x01000000) /*!<Resynchronization Jump Width (Bit 0) */ |
bogdanm | 86:04dd9b1680ae | 1993 | #define CAN_BTR_SJW_1 ((uint32_t)0x02000000) /*!<Resynchronization Jump Width (Bit 1) */ |
bogdanm | 86:04dd9b1680ae | 1994 | #define CAN_BTR_LBKM ((uint32_t)0x40000000) /*!<Loop Back Mode (Debug) */ |
bogdanm | 86:04dd9b1680ae | 1995 | #define CAN_BTR_SILM ((uint32_t)0x80000000) /*!<Silent Mode */ |
bogdanm | 86:04dd9b1680ae | 1996 | |
bogdanm | 86:04dd9b1680ae | 1997 | /*!<Mailbox registers */ |
bogdanm | 86:04dd9b1680ae | 1998 | /****************** Bit definition for CAN_TI0R register ********************/ |
bogdanm | 86:04dd9b1680ae | 1999 | #define CAN_TI0R_TXRQ ((uint32_t)0x00000001) /*!<Transmit Mailbox Request */ |
bogdanm | 86:04dd9b1680ae | 2000 | #define CAN_TI0R_RTR ((uint32_t)0x00000002) /*!<Remote Transmission Request */ |
bogdanm | 86:04dd9b1680ae | 2001 | #define CAN_TI0R_IDE ((uint32_t)0x00000004) /*!<Identifier Extension */ |
bogdanm | 86:04dd9b1680ae | 2002 | #define CAN_TI0R_EXID ((uint32_t)0x001FFFF8) /*!<Extended Identifier */ |
bogdanm | 86:04dd9b1680ae | 2003 | #define CAN_TI0R_STID ((uint32_t)0xFFE00000) /*!<Standard Identifier or Extended Identifier */ |
bogdanm | 86:04dd9b1680ae | 2004 | |
bogdanm | 86:04dd9b1680ae | 2005 | /****************** Bit definition for CAN_TDT0R register *******************/ |
bogdanm | 86:04dd9b1680ae | 2006 | #define CAN_TDT0R_DLC ((uint32_t)0x0000000F) /*!<Data Length Code */ |
bogdanm | 86:04dd9b1680ae | 2007 | #define CAN_TDT0R_TGT ((uint32_t)0x00000100) /*!<Transmit Global Time */ |
bogdanm | 86:04dd9b1680ae | 2008 | #define CAN_TDT0R_TIME ((uint32_t)0xFFFF0000) /*!<Message Time Stamp */ |
bogdanm | 86:04dd9b1680ae | 2009 | |
bogdanm | 86:04dd9b1680ae | 2010 | /****************** Bit definition for CAN_TDL0R register *******************/ |
bogdanm | 86:04dd9b1680ae | 2011 | #define CAN_TDL0R_DATA0 ((uint32_t)0x000000FF) /*!<Data byte 0 */ |
bogdanm | 86:04dd9b1680ae | 2012 | #define CAN_TDL0R_DATA1 ((uint32_t)0x0000FF00) /*!<Data byte 1 */ |
bogdanm | 86:04dd9b1680ae | 2013 | #define CAN_TDL0R_DATA2 ((uint32_t)0x00FF0000) /*!<Data byte 2 */ |
bogdanm | 86:04dd9b1680ae | 2014 | #define CAN_TDL0R_DATA3 ((uint32_t)0xFF000000) /*!<Data byte 3 */ |
bogdanm | 86:04dd9b1680ae | 2015 | |
bogdanm | 86:04dd9b1680ae | 2016 | /****************** Bit definition for CAN_TDH0R register *******************/ |
bogdanm | 86:04dd9b1680ae | 2017 | #define CAN_TDH0R_DATA4 ((uint32_t)0x000000FF) /*!<Data byte 4 */ |
bogdanm | 86:04dd9b1680ae | 2018 | #define CAN_TDH0R_DATA5 ((uint32_t)0x0000FF00) /*!<Data byte 5 */ |
bogdanm | 86:04dd9b1680ae | 2019 | #define CAN_TDH0R_DATA6 ((uint32_t)0x00FF0000) /*!<Data byte 6 */ |
bogdanm | 86:04dd9b1680ae | 2020 | #define CAN_TDH0R_DATA7 ((uint32_t)0xFF000000) /*!<Data byte 7 */ |
bogdanm | 86:04dd9b1680ae | 2021 | |
bogdanm | 86:04dd9b1680ae | 2022 | /******************* Bit definition for CAN_TI1R register *******************/ |
bogdanm | 86:04dd9b1680ae | 2023 | #define CAN_TI1R_TXRQ ((uint32_t)0x00000001) /*!<Transmit Mailbox Request */ |
bogdanm | 86:04dd9b1680ae | 2024 | #define CAN_TI1R_RTR ((uint32_t)0x00000002) /*!<Remote Transmission Request */ |
bogdanm | 86:04dd9b1680ae | 2025 | #define CAN_TI1R_IDE ((uint32_t)0x00000004) /*!<Identifier Extension */ |
bogdanm | 86:04dd9b1680ae | 2026 | #define CAN_TI1R_EXID ((uint32_t)0x001FFFF8) /*!<Extended Identifier */ |
bogdanm | 86:04dd9b1680ae | 2027 | #define CAN_TI1R_STID ((uint32_t)0xFFE00000) /*!<Standard Identifier or Extended Identifier */ |
bogdanm | 86:04dd9b1680ae | 2028 | |
bogdanm | 86:04dd9b1680ae | 2029 | /******************* Bit definition for CAN_TDT1R register ******************/ |
bogdanm | 86:04dd9b1680ae | 2030 | #define CAN_TDT1R_DLC ((uint32_t)0x0000000F) /*!<Data Length Code */ |
bogdanm | 86:04dd9b1680ae | 2031 | #define CAN_TDT1R_TGT ((uint32_t)0x00000100) /*!<Transmit Global Time */ |
bogdanm | 86:04dd9b1680ae | 2032 | #define CAN_TDT1R_TIME ((uint32_t)0xFFFF0000) /*!<Message Time Stamp */ |
bogdanm | 86:04dd9b1680ae | 2033 | |
bogdanm | 86:04dd9b1680ae | 2034 | /******************* Bit definition for CAN_TDL1R register ******************/ |
bogdanm | 86:04dd9b1680ae | 2035 | #define CAN_TDL1R_DATA0 ((uint32_t)0x000000FF) /*!<Data byte 0 */ |
bogdanm | 86:04dd9b1680ae | 2036 | #define CAN_TDL1R_DATA1 ((uint32_t)0x0000FF00) /*!<Data byte 1 */ |
bogdanm | 86:04dd9b1680ae | 2037 | #define CAN_TDL1R_DATA2 ((uint32_t)0x00FF0000) /*!<Data byte 2 */ |
bogdanm | 86:04dd9b1680ae | 2038 | #define CAN_TDL1R_DATA3 ((uint32_t)0xFF000000) /*!<Data byte 3 */ |
bogdanm | 86:04dd9b1680ae | 2039 | |
bogdanm | 86:04dd9b1680ae | 2040 | /******************* Bit definition for CAN_TDH1R register ******************/ |
bogdanm | 86:04dd9b1680ae | 2041 | #define CAN_TDH1R_DATA4 ((uint32_t)0x000000FF) /*!<Data byte 4 */ |
bogdanm | 86:04dd9b1680ae | 2042 | #define CAN_TDH1R_DATA5 ((uint32_t)0x0000FF00) /*!<Data byte 5 */ |
bogdanm | 86:04dd9b1680ae | 2043 | #define CAN_TDH1R_DATA6 ((uint32_t)0x00FF0000) /*!<Data byte 6 */ |
bogdanm | 86:04dd9b1680ae | 2044 | #define CAN_TDH1R_DATA7 ((uint32_t)0xFF000000) /*!<Data byte 7 */ |
bogdanm | 86:04dd9b1680ae | 2045 | |
bogdanm | 86:04dd9b1680ae | 2046 | /******************* Bit definition for CAN_TI2R register *******************/ |
bogdanm | 86:04dd9b1680ae | 2047 | #define CAN_TI2R_TXRQ ((uint32_t)0x00000001) /*!<Transmit Mailbox Request */ |
bogdanm | 86:04dd9b1680ae | 2048 | #define CAN_TI2R_RTR ((uint32_t)0x00000002) /*!<Remote Transmission Request */ |
bogdanm | 86:04dd9b1680ae | 2049 | #define CAN_TI2R_IDE ((uint32_t)0x00000004) /*!<Identifier Extension */ |
bogdanm | 86:04dd9b1680ae | 2050 | #define CAN_TI2R_EXID ((uint32_t)0x001FFFF8) /*!<Extended identifier */ |
bogdanm | 86:04dd9b1680ae | 2051 | #define CAN_TI2R_STID ((uint32_t)0xFFE00000) /*!<Standard Identifier or Extended Identifier */ |
bogdanm | 86:04dd9b1680ae | 2052 | |
bogdanm | 86:04dd9b1680ae | 2053 | /******************* Bit definition for CAN_TDT2R register ******************/ |
bogdanm | 86:04dd9b1680ae | 2054 | #define CAN_TDT2R_DLC ((uint32_t)0x0000000F) /*!<Data Length Code */ |
bogdanm | 86:04dd9b1680ae | 2055 | #define CAN_TDT2R_TGT ((uint32_t)0x00000100) /*!<Transmit Global Time */ |
bogdanm | 86:04dd9b1680ae | 2056 | #define CAN_TDT2R_TIME ((uint32_t)0xFFFF0000) /*!<Message Time Stamp */ |
bogdanm | 86:04dd9b1680ae | 2057 | |
bogdanm | 86:04dd9b1680ae | 2058 | /******************* Bit definition for CAN_TDL2R register ******************/ |
bogdanm | 86:04dd9b1680ae | 2059 | #define CAN_TDL2R_DATA0 ((uint32_t)0x000000FF) /*!<Data byte 0 */ |
bogdanm | 86:04dd9b1680ae | 2060 | #define CAN_TDL2R_DATA1 ((uint32_t)0x0000FF00) /*!<Data byte 1 */ |
bogdanm | 86:04dd9b1680ae | 2061 | #define CAN_TDL2R_DATA2 ((uint32_t)0x00FF0000) /*!<Data byte 2 */ |
bogdanm | 86:04dd9b1680ae | 2062 | #define CAN_TDL2R_DATA3 ((uint32_t)0xFF000000) /*!<Data byte 3 */ |
bogdanm | 86:04dd9b1680ae | 2063 | |
bogdanm | 86:04dd9b1680ae | 2064 | /******************* Bit definition for CAN_TDH2R register ******************/ |
bogdanm | 86:04dd9b1680ae | 2065 | #define CAN_TDH2R_DATA4 ((uint32_t)0x000000FF) /*!<Data byte 4 */ |
bogdanm | 86:04dd9b1680ae | 2066 | #define CAN_TDH2R_DATA5 ((uint32_t)0x0000FF00) /*!<Data byte 5 */ |
bogdanm | 86:04dd9b1680ae | 2067 | #define CAN_TDH2R_DATA6 ((uint32_t)0x00FF0000) /*!<Data byte 6 */ |
bogdanm | 86:04dd9b1680ae | 2068 | #define CAN_TDH2R_DATA7 ((uint32_t)0xFF000000) /*!<Data byte 7 */ |
bogdanm | 86:04dd9b1680ae | 2069 | |
bogdanm | 86:04dd9b1680ae | 2070 | /******************* Bit definition for CAN_RI0R register *******************/ |
bogdanm | 86:04dd9b1680ae | 2071 | #define CAN_RI0R_RTR ((uint32_t)0x00000002) /*!<Remote Transmission Request */ |
bogdanm | 86:04dd9b1680ae | 2072 | #define CAN_RI0R_IDE ((uint32_t)0x00000004) /*!<Identifier Extension */ |
bogdanm | 86:04dd9b1680ae | 2073 | #define CAN_RI0R_EXID ((uint32_t)0x001FFFF8) /*!<Extended Identifier */ |
bogdanm | 86:04dd9b1680ae | 2074 | #define CAN_RI0R_STID ((uint32_t)0xFFE00000) /*!<Standard Identifier or Extended Identifier */ |
bogdanm | 86:04dd9b1680ae | 2075 | |
bogdanm | 86:04dd9b1680ae | 2076 | /******************* Bit definition for CAN_RDT0R register ******************/ |
bogdanm | 86:04dd9b1680ae | 2077 | #define CAN_RDT0R_DLC ((uint32_t)0x0000000F) /*!<Data Length Code */ |
bogdanm | 86:04dd9b1680ae | 2078 | #define CAN_RDT0R_FMI ((uint32_t)0x0000FF00) /*!<Filter Match Index */ |
bogdanm | 86:04dd9b1680ae | 2079 | #define CAN_RDT0R_TIME ((uint32_t)0xFFFF0000) /*!<Message Time Stamp */ |
bogdanm | 86:04dd9b1680ae | 2080 | |
bogdanm | 86:04dd9b1680ae | 2081 | /******************* Bit definition for CAN_RDL0R register ******************/ |
bogdanm | 86:04dd9b1680ae | 2082 | #define CAN_RDL0R_DATA0 ((uint32_t)0x000000FF) /*!<Data byte 0 */ |
bogdanm | 86:04dd9b1680ae | 2083 | #define CAN_RDL0R_DATA1 ((uint32_t)0x0000FF00) /*!<Data byte 1 */ |
bogdanm | 86:04dd9b1680ae | 2084 | #define CAN_RDL0R_DATA2 ((uint32_t)0x00FF0000) /*!<Data byte 2 */ |
bogdanm | 86:04dd9b1680ae | 2085 | #define CAN_RDL0R_DATA3 ((uint32_t)0xFF000000) /*!<Data byte 3 */ |
bogdanm | 86:04dd9b1680ae | 2086 | |
bogdanm | 86:04dd9b1680ae | 2087 | /******************* Bit definition for CAN_RDH0R register ******************/ |
bogdanm | 86:04dd9b1680ae | 2088 | #define CAN_RDH0R_DATA4 ((uint32_t)0x000000FF) /*!<Data byte 4 */ |
bogdanm | 86:04dd9b1680ae | 2089 | #define CAN_RDH0R_DATA5 ((uint32_t)0x0000FF00) /*!<Data byte 5 */ |
bogdanm | 86:04dd9b1680ae | 2090 | #define CAN_RDH0R_DATA6 ((uint32_t)0x00FF0000) /*!<Data byte 6 */ |
bogdanm | 86:04dd9b1680ae | 2091 | #define CAN_RDH0R_DATA7 ((uint32_t)0xFF000000) /*!<Data byte 7 */ |
bogdanm | 86:04dd9b1680ae | 2092 | |
bogdanm | 86:04dd9b1680ae | 2093 | /******************* Bit definition for CAN_RI1R register *******************/ |
bogdanm | 86:04dd9b1680ae | 2094 | #define CAN_RI1R_RTR ((uint32_t)0x00000002) /*!<Remote Transmission Request */ |
bogdanm | 86:04dd9b1680ae | 2095 | #define CAN_RI1R_IDE ((uint32_t)0x00000004) /*!<Identifier Extension */ |
bogdanm | 86:04dd9b1680ae | 2096 | #define CAN_RI1R_EXID ((uint32_t)0x001FFFF8) /*!<Extended identifier */ |
bogdanm | 86:04dd9b1680ae | 2097 | #define CAN_RI1R_STID ((uint32_t)0xFFE00000) /*!<Standard Identifier or Extended Identifier */ |
bogdanm | 86:04dd9b1680ae | 2098 | |
bogdanm | 86:04dd9b1680ae | 2099 | /******************* Bit definition for CAN_RDT1R register ******************/ |
bogdanm | 86:04dd9b1680ae | 2100 | #define CAN_RDT1R_DLC ((uint32_t)0x0000000F) /*!<Data Length Code */ |
bogdanm | 86:04dd9b1680ae | 2101 | #define CAN_RDT1R_FMI ((uint32_t)0x0000FF00) /*!<Filter Match Index */ |
bogdanm | 86:04dd9b1680ae | 2102 | #define CAN_RDT1R_TIME ((uint32_t)0xFFFF0000) /*!<Message Time Stamp */ |
bogdanm | 86:04dd9b1680ae | 2103 | |
bogdanm | 86:04dd9b1680ae | 2104 | /******************* Bit definition for CAN_RDL1R register ******************/ |
bogdanm | 86:04dd9b1680ae | 2105 | #define CAN_RDL1R_DATA0 ((uint32_t)0x000000FF) /*!<Data byte 0 */ |
bogdanm | 86:04dd9b1680ae | 2106 | #define CAN_RDL1R_DATA1 ((uint32_t)0x0000FF00) /*!<Data byte 1 */ |
bogdanm | 86:04dd9b1680ae | 2107 | #define CAN_RDL1R_DATA2 ((uint32_t)0x00FF0000) /*!<Data byte 2 */ |
bogdanm | 86:04dd9b1680ae | 2108 | #define CAN_RDL1R_DATA3 ((uint32_t)0xFF000000) /*!<Data byte 3 */ |
bogdanm | 86:04dd9b1680ae | 2109 | |
bogdanm | 86:04dd9b1680ae | 2110 | /******************* Bit definition for CAN_RDH1R register ******************/ |
bogdanm | 86:04dd9b1680ae | 2111 | #define CAN_RDH1R_DATA4 ((uint32_t)0x000000FF) /*!<Data byte 4 */ |
bogdanm | 86:04dd9b1680ae | 2112 | #define CAN_RDH1R_DATA5 ((uint32_t)0x0000FF00) /*!<Data byte 5 */ |
bogdanm | 86:04dd9b1680ae | 2113 | #define CAN_RDH1R_DATA6 ((uint32_t)0x00FF0000) /*!<Data byte 6 */ |
bogdanm | 86:04dd9b1680ae | 2114 | #define CAN_RDH1R_DATA7 ((uint32_t)0xFF000000) /*!<Data byte 7 */ |
bogdanm | 86:04dd9b1680ae | 2115 | |
bogdanm | 86:04dd9b1680ae | 2116 | /*!<CAN filter registers */ |
bogdanm | 86:04dd9b1680ae | 2117 | /******************* Bit definition for CAN_FMR register ********************/ |
bogdanm | 86:04dd9b1680ae | 2118 | #define CAN_FMR_FINIT ((uint32_t)0x00000001) /*!<Filter Init Mode */ |
bogdanm | 86:04dd9b1680ae | 2119 | |
bogdanm | 86:04dd9b1680ae | 2120 | /******************* Bit definition for CAN_FM1R register *******************/ |
bogdanm | 86:04dd9b1680ae | 2121 | #define CAN_FM1R_FBM ((uint32_t)0x00003FFF) /*!<Filter Mode */ |
bogdanm | 86:04dd9b1680ae | 2122 | #define CAN_FM1R_FBM0 ((uint32_t)0x00000001) /*!<Filter Init Mode bit 0 */ |
bogdanm | 86:04dd9b1680ae | 2123 | #define CAN_FM1R_FBM1 ((uint32_t)0x00000002) /*!<Filter Init Mode bit 1 */ |
bogdanm | 86:04dd9b1680ae | 2124 | #define CAN_FM1R_FBM2 ((uint32_t)0x00000004) /*!<Filter Init Mode bit 2 */ |
bogdanm | 86:04dd9b1680ae | 2125 | #define CAN_FM1R_FBM3 ((uint32_t)0x00000008) /*!<Filter Init Mode bit 3 */ |
bogdanm | 86:04dd9b1680ae | 2126 | #define CAN_FM1R_FBM4 ((uint32_t)0x00000010) /*!<Filter Init Mode bit 4 */ |
bogdanm | 86:04dd9b1680ae | 2127 | #define CAN_FM1R_FBM5 ((uint32_t)0x00000020) /*!<Filter Init Mode bit 5 */ |
bogdanm | 86:04dd9b1680ae | 2128 | #define CAN_FM1R_FBM6 ((uint32_t)0x00000040) /*!<Filter Init Mode bit 6 */ |
bogdanm | 86:04dd9b1680ae | 2129 | #define CAN_FM1R_FBM7 ((uint32_t)0x00000080) /*!<Filter Init Mode bit 7 */ |
bogdanm | 86:04dd9b1680ae | 2130 | #define CAN_FM1R_FBM8 ((uint32_t)0x00000100) /*!<Filter Init Mode bit 8 */ |
bogdanm | 86:04dd9b1680ae | 2131 | #define CAN_FM1R_FBM9 ((uint32_t)0x00000200) /*!<Filter Init Mode bit 9 */ |
bogdanm | 86:04dd9b1680ae | 2132 | #define CAN_FM1R_FBM10 ((uint32_t)0x00000400) /*!<Filter Init Mode bit 10 */ |
bogdanm | 86:04dd9b1680ae | 2133 | #define CAN_FM1R_FBM11 ((uint32_t)0x00000800) /*!<Filter Init Mode bit 11 */ |
bogdanm | 86:04dd9b1680ae | 2134 | #define CAN_FM1R_FBM12 ((uint32_t)0x00001000) /*!<Filter Init Mode bit 12 */ |
bogdanm | 86:04dd9b1680ae | 2135 | #define CAN_FM1R_FBM13 ((uint32_t)0x00002000) /*!<Filter Init Mode bit 13 */ |
bogdanm | 86:04dd9b1680ae | 2136 | |
bogdanm | 86:04dd9b1680ae | 2137 | /******************* Bit definition for CAN_FS1R register *******************/ |
bogdanm | 86:04dd9b1680ae | 2138 | #define CAN_FS1R_FSC ((uint32_t)0x00003FFF) /*!<Filter Scale Configuration */ |
bogdanm | 86:04dd9b1680ae | 2139 | #define CAN_FS1R_FSC0 ((uint32_t)0x00000001) /*!<Filter Scale Configuration bit 0 */ |
bogdanm | 86:04dd9b1680ae | 2140 | #define CAN_FS1R_FSC1 ((uint32_t)0x00000002) /*!<Filter Scale Configuration bit 1 */ |
bogdanm | 86:04dd9b1680ae | 2141 | #define CAN_FS1R_FSC2 ((uint32_t)0x00000004) /*!<Filter Scale Configuration bit 2 */ |
bogdanm | 86:04dd9b1680ae | 2142 | #define CAN_FS1R_FSC3 ((uint32_t)0x00000008) /*!<Filter Scale Configuration bit 3 */ |
bogdanm | 86:04dd9b1680ae | 2143 | #define CAN_FS1R_FSC4 ((uint32_t)0x00000010) /*!<Filter Scale Configuration bit 4 */ |
bogdanm | 86:04dd9b1680ae | 2144 | #define CAN_FS1R_FSC5 ((uint32_t)0x00000020) /*!<Filter Scale Configuration bit 5 */ |
bogdanm | 86:04dd9b1680ae | 2145 | #define CAN_FS1R_FSC6 ((uint32_t)0x00000040) /*!<Filter Scale Configuration bit 6 */ |
bogdanm | 86:04dd9b1680ae | 2146 | #define CAN_FS1R_FSC7 ((uint32_t)0x00000080) /*!<Filter Scale Configuration bit 7 */ |
bogdanm | 86:04dd9b1680ae | 2147 | #define CAN_FS1R_FSC8 ((uint32_t)0x00000100) /*!<Filter Scale Configuration bit 8 */ |
bogdanm | 86:04dd9b1680ae | 2148 | #define CAN_FS1R_FSC9 ((uint32_t)0x00000200) /*!<Filter Scale Configuration bit 9 */ |
bogdanm | 86:04dd9b1680ae | 2149 | #define CAN_FS1R_FSC10 ((uint32_t)0x00000400) /*!<Filter Scale Configuration bit 10 */ |
bogdanm | 86:04dd9b1680ae | 2150 | #define CAN_FS1R_FSC11 ((uint32_t)0x00000800) /*!<Filter Scale Configuration bit 11 */ |
bogdanm | 86:04dd9b1680ae | 2151 | #define CAN_FS1R_FSC12 ((uint32_t)0x00001000) /*!<Filter Scale Configuration bit 12 */ |
bogdanm | 86:04dd9b1680ae | 2152 | #define CAN_FS1R_FSC13 ((uint32_t)0x00002000) /*!<Filter Scale Configuration bit 13 */ |
bogdanm | 86:04dd9b1680ae | 2153 | |
bogdanm | 86:04dd9b1680ae | 2154 | /****************** Bit definition for CAN_FFA1R register *******************/ |
bogdanm | 86:04dd9b1680ae | 2155 | #define CAN_FFA1R_FFA ((uint32_t)0x00003FFF) /*!<Filter FIFO Assignment */ |
bogdanm | 86:04dd9b1680ae | 2156 | #define CAN_FFA1R_FFA0 ((uint32_t)0x00000001) /*!<Filter FIFO Assignment for Filter 0 */ |
bogdanm | 86:04dd9b1680ae | 2157 | #define CAN_FFA1R_FFA1 ((uint32_t)0x00000002) /*!<Filter FIFO Assignment for Filter 1 */ |
bogdanm | 86:04dd9b1680ae | 2158 | #define CAN_FFA1R_FFA2 ((uint32_t)0x00000004) /*!<Filter FIFO Assignment for Filter 2 */ |
bogdanm | 86:04dd9b1680ae | 2159 | #define CAN_FFA1R_FFA3 ((uint32_t)0x00000008) /*!<Filter FIFO Assignment for Filter 3 */ |
bogdanm | 86:04dd9b1680ae | 2160 | #define CAN_FFA1R_FFA4 ((uint32_t)0x00000010) /*!<Filter FIFO Assignment for Filter 4 */ |
bogdanm | 86:04dd9b1680ae | 2161 | #define CAN_FFA1R_FFA5 ((uint32_t)0x00000020) /*!<Filter FIFO Assignment for Filter 5 */ |
bogdanm | 86:04dd9b1680ae | 2162 | #define CAN_FFA1R_FFA6 ((uint32_t)0x00000040) /*!<Filter FIFO Assignment for Filter 6 */ |
bogdanm | 86:04dd9b1680ae | 2163 | #define CAN_FFA1R_FFA7 ((uint32_t)0x00000080) /*!<Filter FIFO Assignment for Filter 7 */ |
bogdanm | 86:04dd9b1680ae | 2164 | #define CAN_FFA1R_FFA8 ((uint32_t)0x00000100) /*!<Filter FIFO Assignment for Filter 8 */ |
bogdanm | 86:04dd9b1680ae | 2165 | #define CAN_FFA1R_FFA9 ((uint32_t)0x00000200) /*!<Filter FIFO Assignment for Filter 9 */ |
bogdanm | 86:04dd9b1680ae | 2166 | #define CAN_FFA1R_FFA10 ((uint32_t)0x00000400) /*!<Filter FIFO Assignment for Filter 10 */ |
bogdanm | 86:04dd9b1680ae | 2167 | #define CAN_FFA1R_FFA11 ((uint32_t)0x00000800) /*!<Filter FIFO Assignment for Filter 11 */ |
bogdanm | 86:04dd9b1680ae | 2168 | #define CAN_FFA1R_FFA12 ((uint32_t)0x00001000) /*!<Filter FIFO Assignment for Filter 12 */ |
bogdanm | 86:04dd9b1680ae | 2169 | #define CAN_FFA1R_FFA13 ((uint32_t)0x00002000) /*!<Filter FIFO Assignment for Filter 13 */ |
bogdanm | 86:04dd9b1680ae | 2170 | |
bogdanm | 86:04dd9b1680ae | 2171 | /******************* Bit definition for CAN_FA1R register *******************/ |
bogdanm | 86:04dd9b1680ae | 2172 | #define CAN_FA1R_FACT ((uint32_t)0x00003FFF) /*!<Filter Active */ |
bogdanm | 86:04dd9b1680ae | 2173 | #define CAN_FA1R_FACT0 ((uint32_t)0x00000001) /*!<Filter 0 Active */ |
bogdanm | 86:04dd9b1680ae | 2174 | #define CAN_FA1R_FACT1 ((uint32_t)0x00000002) /*!<Filter 1 Active */ |
bogdanm | 86:04dd9b1680ae | 2175 | #define CAN_FA1R_FACT2 ((uint32_t)0x00000004) /*!<Filter 2 Active */ |
bogdanm | 86:04dd9b1680ae | 2176 | #define CAN_FA1R_FACT3 ((uint32_t)0x00000008) /*!<Filter 3 Active */ |
bogdanm | 86:04dd9b1680ae | 2177 | #define CAN_FA1R_FACT4 ((uint32_t)0x00000010) /*!<Filter 4 Active */ |
bogdanm | 86:04dd9b1680ae | 2178 | #define CAN_FA1R_FACT5 ((uint32_t)0x00000020) /*!<Filter 5 Active */ |
bogdanm | 86:04dd9b1680ae | 2179 | #define CAN_FA1R_FACT6 ((uint32_t)0x00000040) /*!<Filter 6 Active */ |
bogdanm | 86:04dd9b1680ae | 2180 | #define CAN_FA1R_FACT7 ((uint32_t)0x00000080) /*!<Filter 7 Active */ |
bogdanm | 86:04dd9b1680ae | 2181 | #define CAN_FA1R_FACT8 ((uint32_t)0x00000100) /*!<Filter 8 Active */ |
bogdanm | 86:04dd9b1680ae | 2182 | #define CAN_FA1R_FACT9 ((uint32_t)0x00000200) /*!<Filter 9 Active */ |
bogdanm | 86:04dd9b1680ae | 2183 | #define CAN_FA1R_FACT10 ((uint32_t)0x00000400) /*!<Filter 10 Active */ |
bogdanm | 86:04dd9b1680ae | 2184 | #define CAN_FA1R_FACT11 ((uint32_t)0x00000800) /*!<Filter 11 Active */ |
bogdanm | 86:04dd9b1680ae | 2185 | #define CAN_FA1R_FACT12 ((uint32_t)0x00001000) /*!<Filter 12 Active */ |
bogdanm | 86:04dd9b1680ae | 2186 | #define CAN_FA1R_FACT13 ((uint32_t)0x00002000) /*!<Filter 13 Active */ |
bogdanm | 86:04dd9b1680ae | 2187 | |
bogdanm | 86:04dd9b1680ae | 2188 | /******************* Bit definition for CAN_F0R1 register *******************/ |
bogdanm | 86:04dd9b1680ae | 2189 | #define CAN_F0R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */ |
bogdanm | 86:04dd9b1680ae | 2190 | #define CAN_F0R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */ |
bogdanm | 86:04dd9b1680ae | 2191 | #define CAN_F0R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */ |
bogdanm | 86:04dd9b1680ae | 2192 | #define CAN_F0R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */ |
bogdanm | 86:04dd9b1680ae | 2193 | #define CAN_F0R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */ |
bogdanm | 86:04dd9b1680ae | 2194 | #define CAN_F0R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */ |
bogdanm | 86:04dd9b1680ae | 2195 | #define CAN_F0R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */ |
bogdanm | 86:04dd9b1680ae | 2196 | #define CAN_F0R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */ |
bogdanm | 86:04dd9b1680ae | 2197 | #define CAN_F0R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */ |
bogdanm | 86:04dd9b1680ae | 2198 | #define CAN_F0R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */ |
bogdanm | 86:04dd9b1680ae | 2199 | #define CAN_F0R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */ |
bogdanm | 86:04dd9b1680ae | 2200 | #define CAN_F0R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */ |
bogdanm | 86:04dd9b1680ae | 2201 | #define CAN_F0R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */ |
bogdanm | 86:04dd9b1680ae | 2202 | #define CAN_F0R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */ |
bogdanm | 86:04dd9b1680ae | 2203 | #define CAN_F0R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */ |
bogdanm | 86:04dd9b1680ae | 2204 | #define CAN_F0R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */ |
bogdanm | 86:04dd9b1680ae | 2205 | #define CAN_F0R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */ |
bogdanm | 86:04dd9b1680ae | 2206 | #define CAN_F0R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */ |
bogdanm | 86:04dd9b1680ae | 2207 | #define CAN_F0R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */ |
bogdanm | 86:04dd9b1680ae | 2208 | #define CAN_F0R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */ |
bogdanm | 86:04dd9b1680ae | 2209 | #define CAN_F0R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */ |
bogdanm | 86:04dd9b1680ae | 2210 | #define CAN_F0R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */ |
bogdanm | 86:04dd9b1680ae | 2211 | #define CAN_F0R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */ |
bogdanm | 86:04dd9b1680ae | 2212 | #define CAN_F0R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */ |
bogdanm | 86:04dd9b1680ae | 2213 | #define CAN_F0R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */ |
bogdanm | 86:04dd9b1680ae | 2214 | #define CAN_F0R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */ |
bogdanm | 86:04dd9b1680ae | 2215 | #define CAN_F0R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */ |
bogdanm | 86:04dd9b1680ae | 2216 | #define CAN_F0R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */ |
bogdanm | 86:04dd9b1680ae | 2217 | #define CAN_F0R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */ |
bogdanm | 86:04dd9b1680ae | 2218 | #define CAN_F0R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */ |
bogdanm | 86:04dd9b1680ae | 2219 | #define CAN_F0R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */ |
bogdanm | 86:04dd9b1680ae | 2220 | #define CAN_F0R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */ |
bogdanm | 86:04dd9b1680ae | 2221 | |
bogdanm | 86:04dd9b1680ae | 2222 | /******************* Bit definition for CAN_F1R1 register *******************/ |
bogdanm | 86:04dd9b1680ae | 2223 | #define CAN_F1R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */ |
bogdanm | 86:04dd9b1680ae | 2224 | #define CAN_F1R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */ |
bogdanm | 86:04dd9b1680ae | 2225 | #define CAN_F1R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */ |
bogdanm | 86:04dd9b1680ae | 2226 | #define CAN_F1R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */ |
bogdanm | 86:04dd9b1680ae | 2227 | #define CAN_F1R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */ |
bogdanm | 86:04dd9b1680ae | 2228 | #define CAN_F1R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */ |
bogdanm | 86:04dd9b1680ae | 2229 | #define CAN_F1R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */ |
bogdanm | 86:04dd9b1680ae | 2230 | #define CAN_F1R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */ |
bogdanm | 86:04dd9b1680ae | 2231 | #define CAN_F1R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */ |
bogdanm | 86:04dd9b1680ae | 2232 | #define CAN_F1R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */ |
bogdanm | 86:04dd9b1680ae | 2233 | #define CAN_F1R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */ |
bogdanm | 86:04dd9b1680ae | 2234 | #define CAN_F1R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */ |
bogdanm | 86:04dd9b1680ae | 2235 | #define CAN_F1R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */ |
bogdanm | 86:04dd9b1680ae | 2236 | #define CAN_F1R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */ |
bogdanm | 86:04dd9b1680ae | 2237 | #define CAN_F1R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */ |
bogdanm | 86:04dd9b1680ae | 2238 | #define CAN_F1R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */ |
bogdanm | 86:04dd9b1680ae | 2239 | #define CAN_F1R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */ |
bogdanm | 86:04dd9b1680ae | 2240 | #define CAN_F1R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */ |
bogdanm | 86:04dd9b1680ae | 2241 | #define CAN_F1R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */ |
bogdanm | 86:04dd9b1680ae | 2242 | #define CAN_F1R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */ |
bogdanm | 86:04dd9b1680ae | 2243 | #define CAN_F1R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */ |
bogdanm | 86:04dd9b1680ae | 2244 | #define CAN_F1R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */ |
bogdanm | 86:04dd9b1680ae | 2245 | #define CAN_F1R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */ |
bogdanm | 86:04dd9b1680ae | 2246 | #define CAN_F1R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */ |
bogdanm | 86:04dd9b1680ae | 2247 | #define CAN_F1R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */ |
bogdanm | 86:04dd9b1680ae | 2248 | #define CAN_F1R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */ |
bogdanm | 86:04dd9b1680ae | 2249 | #define CAN_F1R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */ |
bogdanm | 86:04dd9b1680ae | 2250 | #define CAN_F1R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */ |
bogdanm | 86:04dd9b1680ae | 2251 | #define CAN_F1R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */ |
bogdanm | 86:04dd9b1680ae | 2252 | #define CAN_F1R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */ |
bogdanm | 86:04dd9b1680ae | 2253 | #define CAN_F1R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */ |
bogdanm | 86:04dd9b1680ae | 2254 | #define CAN_F1R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */ |
bogdanm | 86:04dd9b1680ae | 2255 | |
bogdanm | 86:04dd9b1680ae | 2256 | /******************* Bit definition for CAN_F2R1 register *******************/ |
bogdanm | 86:04dd9b1680ae | 2257 | #define CAN_F2R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */ |
bogdanm | 86:04dd9b1680ae | 2258 | #define CAN_F2R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */ |
bogdanm | 86:04dd9b1680ae | 2259 | #define CAN_F2R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */ |
bogdanm | 86:04dd9b1680ae | 2260 | #define CAN_F2R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */ |
bogdanm | 86:04dd9b1680ae | 2261 | #define CAN_F2R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */ |
bogdanm | 86:04dd9b1680ae | 2262 | #define CAN_F2R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */ |
bogdanm | 86:04dd9b1680ae | 2263 | #define CAN_F2R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */ |
bogdanm | 86:04dd9b1680ae | 2264 | #define CAN_F2R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */ |
bogdanm | 86:04dd9b1680ae | 2265 | #define CAN_F2R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */ |
bogdanm | 86:04dd9b1680ae | 2266 | #define CAN_F2R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */ |
bogdanm | 86:04dd9b1680ae | 2267 | #define CAN_F2R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */ |
bogdanm | 86:04dd9b1680ae | 2268 | #define CAN_F2R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */ |
bogdanm | 86:04dd9b1680ae | 2269 | #define CAN_F2R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */ |
bogdanm | 86:04dd9b1680ae | 2270 | #define CAN_F2R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */ |
bogdanm | 86:04dd9b1680ae | 2271 | #define CAN_F2R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */ |
bogdanm | 86:04dd9b1680ae | 2272 | #define CAN_F2R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */ |
bogdanm | 86:04dd9b1680ae | 2273 | #define CAN_F2R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */ |
bogdanm | 86:04dd9b1680ae | 2274 | #define CAN_F2R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */ |
bogdanm | 86:04dd9b1680ae | 2275 | #define CAN_F2R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */ |
bogdanm | 86:04dd9b1680ae | 2276 | #define CAN_F2R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */ |
bogdanm | 86:04dd9b1680ae | 2277 | #define CAN_F2R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */ |
bogdanm | 86:04dd9b1680ae | 2278 | #define CAN_F2R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */ |
bogdanm | 86:04dd9b1680ae | 2279 | #define CAN_F2R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */ |
bogdanm | 86:04dd9b1680ae | 2280 | #define CAN_F2R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */ |
bogdanm | 86:04dd9b1680ae | 2281 | #define CAN_F2R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */ |
bogdanm | 86:04dd9b1680ae | 2282 | #define CAN_F2R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */ |
bogdanm | 86:04dd9b1680ae | 2283 | #define CAN_F2R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */ |
bogdanm | 86:04dd9b1680ae | 2284 | #define CAN_F2R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */ |
bogdanm | 86:04dd9b1680ae | 2285 | #define CAN_F2R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */ |
bogdanm | 86:04dd9b1680ae | 2286 | #define CAN_F2R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */ |
bogdanm | 86:04dd9b1680ae | 2287 | #define CAN_F2R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */ |
bogdanm | 86:04dd9b1680ae | 2288 | #define CAN_F2R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */ |
bogdanm | 86:04dd9b1680ae | 2289 | |
bogdanm | 86:04dd9b1680ae | 2290 | /******************* Bit definition for CAN_F3R1 register *******************/ |
bogdanm | 86:04dd9b1680ae | 2291 | #define CAN_F3R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */ |
bogdanm | 86:04dd9b1680ae | 2292 | #define CAN_F3R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */ |
bogdanm | 86:04dd9b1680ae | 2293 | #define CAN_F3R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */ |
bogdanm | 86:04dd9b1680ae | 2294 | #define CAN_F3R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */ |
bogdanm | 86:04dd9b1680ae | 2295 | #define CAN_F3R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */ |
bogdanm | 86:04dd9b1680ae | 2296 | #define CAN_F3R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */ |
bogdanm | 86:04dd9b1680ae | 2297 | #define CAN_F3R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */ |
bogdanm | 86:04dd9b1680ae | 2298 | #define CAN_F3R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */ |
bogdanm | 86:04dd9b1680ae | 2299 | #define CAN_F3R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */ |
bogdanm | 86:04dd9b1680ae | 2300 | #define CAN_F3R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */ |
bogdanm | 86:04dd9b1680ae | 2301 | #define CAN_F3R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */ |
bogdanm | 86:04dd9b1680ae | 2302 | #define CAN_F3R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */ |
bogdanm | 86:04dd9b1680ae | 2303 | #define CAN_F3R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */ |
bogdanm | 86:04dd9b1680ae | 2304 | #define CAN_F3R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */ |
bogdanm | 86:04dd9b1680ae | 2305 | #define CAN_F3R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */ |
bogdanm | 86:04dd9b1680ae | 2306 | #define CAN_F3R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */ |
bogdanm | 86:04dd9b1680ae | 2307 | #define CAN_F3R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */ |
bogdanm | 86:04dd9b1680ae | 2308 | #define CAN_F3R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */ |
bogdanm | 86:04dd9b1680ae | 2309 | #define CAN_F3R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */ |
bogdanm | 86:04dd9b1680ae | 2310 | #define CAN_F3R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */ |
bogdanm | 86:04dd9b1680ae | 2311 | #define CAN_F3R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */ |
bogdanm | 86:04dd9b1680ae | 2312 | #define CAN_F3R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */ |
bogdanm | 86:04dd9b1680ae | 2313 | #define CAN_F3R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */ |
bogdanm | 86:04dd9b1680ae | 2314 | #define CAN_F3R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */ |
bogdanm | 86:04dd9b1680ae | 2315 | #define CAN_F3R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */ |
bogdanm | 86:04dd9b1680ae | 2316 | #define CAN_F3R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */ |
bogdanm | 86:04dd9b1680ae | 2317 | #define CAN_F3R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */ |
bogdanm | 86:04dd9b1680ae | 2318 | #define CAN_F3R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */ |
bogdanm | 86:04dd9b1680ae | 2319 | #define CAN_F3R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */ |
bogdanm | 86:04dd9b1680ae | 2320 | #define CAN_F3R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */ |
bogdanm | 86:04dd9b1680ae | 2321 | #define CAN_F3R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */ |
bogdanm | 86:04dd9b1680ae | 2322 | #define CAN_F3R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */ |
bogdanm | 86:04dd9b1680ae | 2323 | |
bogdanm | 86:04dd9b1680ae | 2324 | /******************* Bit definition for CAN_F4R1 register *******************/ |
bogdanm | 86:04dd9b1680ae | 2325 | #define CAN_F4R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */ |
bogdanm | 86:04dd9b1680ae | 2326 | #define CAN_F4R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */ |
bogdanm | 86:04dd9b1680ae | 2327 | #define CAN_F4R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */ |
bogdanm | 86:04dd9b1680ae | 2328 | #define CAN_F4R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */ |
bogdanm | 86:04dd9b1680ae | 2329 | #define CAN_F4R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */ |
bogdanm | 86:04dd9b1680ae | 2330 | #define CAN_F4R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */ |
bogdanm | 86:04dd9b1680ae | 2331 | #define CAN_F4R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */ |
bogdanm | 86:04dd9b1680ae | 2332 | #define CAN_F4R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */ |
bogdanm | 86:04dd9b1680ae | 2333 | #define CAN_F4R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */ |
bogdanm | 86:04dd9b1680ae | 2334 | #define CAN_F4R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */ |
bogdanm | 86:04dd9b1680ae | 2335 | #define CAN_F4R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */ |
bogdanm | 86:04dd9b1680ae | 2336 | #define CAN_F4R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */ |
bogdanm | 86:04dd9b1680ae | 2337 | #define CAN_F4R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */ |
bogdanm | 86:04dd9b1680ae | 2338 | #define CAN_F4R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */ |
bogdanm | 86:04dd9b1680ae | 2339 | #define CAN_F4R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */ |
bogdanm | 86:04dd9b1680ae | 2340 | #define CAN_F4R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */ |
bogdanm | 86:04dd9b1680ae | 2341 | #define CAN_F4R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */ |
bogdanm | 86:04dd9b1680ae | 2342 | #define CAN_F4R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */ |
bogdanm | 86:04dd9b1680ae | 2343 | #define CAN_F4R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */ |
bogdanm | 86:04dd9b1680ae | 2344 | #define CAN_F4R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */ |
bogdanm | 86:04dd9b1680ae | 2345 | #define CAN_F4R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */ |
bogdanm | 86:04dd9b1680ae | 2346 | #define CAN_F4R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */ |
bogdanm | 86:04dd9b1680ae | 2347 | #define CAN_F4R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */ |
bogdanm | 86:04dd9b1680ae | 2348 | #define CAN_F4R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */ |
bogdanm | 86:04dd9b1680ae | 2349 | #define CAN_F4R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */ |
bogdanm | 86:04dd9b1680ae | 2350 | #define CAN_F4R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */ |
bogdanm | 86:04dd9b1680ae | 2351 | #define CAN_F4R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */ |
bogdanm | 86:04dd9b1680ae | 2352 | #define CAN_F4R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */ |
bogdanm | 86:04dd9b1680ae | 2353 | #define CAN_F4R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */ |
bogdanm | 86:04dd9b1680ae | 2354 | #define CAN_F4R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */ |
bogdanm | 86:04dd9b1680ae | 2355 | #define CAN_F4R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */ |
bogdanm | 86:04dd9b1680ae | 2356 | #define CAN_F4R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */ |
bogdanm | 86:04dd9b1680ae | 2357 | |
bogdanm | 86:04dd9b1680ae | 2358 | /******************* Bit definition for CAN_F5R1 register *******************/ |
bogdanm | 86:04dd9b1680ae | 2359 | #define CAN_F5R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */ |
bogdanm | 86:04dd9b1680ae | 2360 | #define CAN_F5R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */ |
bogdanm | 86:04dd9b1680ae | 2361 | #define CAN_F5R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */ |
bogdanm | 86:04dd9b1680ae | 2362 | #define CAN_F5R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */ |
bogdanm | 86:04dd9b1680ae | 2363 | #define CAN_F5R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */ |
bogdanm | 86:04dd9b1680ae | 2364 | #define CAN_F5R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */ |
bogdanm | 86:04dd9b1680ae | 2365 | #define CAN_F5R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */ |
bogdanm | 86:04dd9b1680ae | 2366 | #define CAN_F5R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */ |
bogdanm | 86:04dd9b1680ae | 2367 | #define CAN_F5R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */ |
bogdanm | 86:04dd9b1680ae | 2368 | #define CAN_F5R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */ |
bogdanm | 86:04dd9b1680ae | 2369 | #define CAN_F5R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */ |
bogdanm | 86:04dd9b1680ae | 2370 | #define CAN_F5R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */ |
bogdanm | 86:04dd9b1680ae | 2371 | #define CAN_F5R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */ |
bogdanm | 86:04dd9b1680ae | 2372 | #define CAN_F5R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */ |
bogdanm | 86:04dd9b1680ae | 2373 | #define CAN_F5R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */ |
bogdanm | 86:04dd9b1680ae | 2374 | #define CAN_F5R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */ |
bogdanm | 86:04dd9b1680ae | 2375 | #define CAN_F5R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */ |
bogdanm | 86:04dd9b1680ae | 2376 | #define CAN_F5R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */ |
bogdanm | 86:04dd9b1680ae | 2377 | #define CAN_F5R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */ |
bogdanm | 86:04dd9b1680ae | 2378 | #define CAN_F5R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */ |
bogdanm | 86:04dd9b1680ae | 2379 | #define CAN_F5R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */ |
bogdanm | 86:04dd9b1680ae | 2380 | #define CAN_F5R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */ |
bogdanm | 86:04dd9b1680ae | 2381 | #define CAN_F5R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */ |
bogdanm | 86:04dd9b1680ae | 2382 | #define CAN_F5R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */ |
bogdanm | 86:04dd9b1680ae | 2383 | #define CAN_F5R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */ |
bogdanm | 86:04dd9b1680ae | 2384 | #define CAN_F5R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */ |
bogdanm | 86:04dd9b1680ae | 2385 | #define CAN_F5R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */ |
bogdanm | 86:04dd9b1680ae | 2386 | #define CAN_F5R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */ |
bogdanm | 86:04dd9b1680ae | 2387 | #define CAN_F5R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */ |
bogdanm | 86:04dd9b1680ae | 2388 | #define CAN_F5R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */ |
bogdanm | 86:04dd9b1680ae | 2389 | #define CAN_F5R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */ |
bogdanm | 86:04dd9b1680ae | 2390 | #define CAN_F5R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */ |
bogdanm | 86:04dd9b1680ae | 2391 | |
bogdanm | 86:04dd9b1680ae | 2392 | /******************* Bit definition for CAN_F6R1 register *******************/ |
bogdanm | 86:04dd9b1680ae | 2393 | #define CAN_F6R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */ |
bogdanm | 86:04dd9b1680ae | 2394 | #define CAN_F6R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */ |
bogdanm | 86:04dd9b1680ae | 2395 | #define CAN_F6R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */ |
bogdanm | 86:04dd9b1680ae | 2396 | #define CAN_F6R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */ |
bogdanm | 86:04dd9b1680ae | 2397 | #define CAN_F6R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */ |
bogdanm | 86:04dd9b1680ae | 2398 | #define CAN_F6R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */ |
bogdanm | 86:04dd9b1680ae | 2399 | #define CAN_F6R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */ |
bogdanm | 86:04dd9b1680ae | 2400 | #define CAN_F6R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */ |
bogdanm | 86:04dd9b1680ae | 2401 | #define CAN_F6R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */ |
bogdanm | 86:04dd9b1680ae | 2402 | #define CAN_F6R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */ |
bogdanm | 86:04dd9b1680ae | 2403 | #define CAN_F6R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */ |
bogdanm | 86:04dd9b1680ae | 2404 | #define CAN_F6R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */ |
bogdanm | 86:04dd9b1680ae | 2405 | #define CAN_F6R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */ |
bogdanm | 86:04dd9b1680ae | 2406 | #define CAN_F6R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */ |
bogdanm | 86:04dd9b1680ae | 2407 | #define CAN_F6R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */ |
bogdanm | 86:04dd9b1680ae | 2408 | #define CAN_F6R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */ |
bogdanm | 86:04dd9b1680ae | 2409 | #define CAN_F6R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */ |
bogdanm | 86:04dd9b1680ae | 2410 | #define CAN_F6R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */ |
bogdanm | 86:04dd9b1680ae | 2411 | #define CAN_F6R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */ |
bogdanm | 86:04dd9b1680ae | 2412 | #define CAN_F6R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */ |
bogdanm | 86:04dd9b1680ae | 2413 | #define CAN_F6R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */ |
bogdanm | 86:04dd9b1680ae | 2414 | #define CAN_F6R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */ |
bogdanm | 86:04dd9b1680ae | 2415 | #define CAN_F6R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */ |
bogdanm | 86:04dd9b1680ae | 2416 | #define CAN_F6R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */ |
bogdanm | 86:04dd9b1680ae | 2417 | #define CAN_F6R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */ |
bogdanm | 86:04dd9b1680ae | 2418 | #define CAN_F6R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */ |
bogdanm | 86:04dd9b1680ae | 2419 | #define CAN_F6R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */ |
bogdanm | 86:04dd9b1680ae | 2420 | #define CAN_F6R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */ |
bogdanm | 86:04dd9b1680ae | 2421 | #define CAN_F6R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */ |
bogdanm | 86:04dd9b1680ae | 2422 | #define CAN_F6R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */ |
bogdanm | 86:04dd9b1680ae | 2423 | #define CAN_F6R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */ |
bogdanm | 86:04dd9b1680ae | 2424 | #define CAN_F6R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */ |
bogdanm | 86:04dd9b1680ae | 2425 | |
bogdanm | 86:04dd9b1680ae | 2426 | /******************* Bit definition for CAN_F7R1 register *******************/ |
bogdanm | 86:04dd9b1680ae | 2427 | #define CAN_F7R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */ |
bogdanm | 86:04dd9b1680ae | 2428 | #define CAN_F7R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */ |
bogdanm | 86:04dd9b1680ae | 2429 | #define CAN_F7R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */ |
bogdanm | 86:04dd9b1680ae | 2430 | #define CAN_F7R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */ |
bogdanm | 86:04dd9b1680ae | 2431 | #define CAN_F7R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */ |
bogdanm | 86:04dd9b1680ae | 2432 | #define CAN_F7R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */ |
bogdanm | 86:04dd9b1680ae | 2433 | #define CAN_F7R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */ |
bogdanm | 86:04dd9b1680ae | 2434 | #define CAN_F7R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */ |
bogdanm | 86:04dd9b1680ae | 2435 | #define CAN_F7R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */ |
bogdanm | 86:04dd9b1680ae | 2436 | #define CAN_F7R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */ |
bogdanm | 86:04dd9b1680ae | 2437 | #define CAN_F7R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */ |
bogdanm | 86:04dd9b1680ae | 2438 | #define CAN_F7R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */ |
bogdanm | 86:04dd9b1680ae | 2439 | #define CAN_F7R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */ |
bogdanm | 86:04dd9b1680ae | 2440 | #define CAN_F7R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */ |
bogdanm | 86:04dd9b1680ae | 2441 | #define CAN_F7R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */ |
bogdanm | 86:04dd9b1680ae | 2442 | #define CAN_F7R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */ |
bogdanm | 86:04dd9b1680ae | 2443 | #define CAN_F7R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */ |
bogdanm | 86:04dd9b1680ae | 2444 | #define CAN_F7R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */ |
bogdanm | 86:04dd9b1680ae | 2445 | #define CAN_F7R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */ |
bogdanm | 86:04dd9b1680ae | 2446 | #define CAN_F7R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */ |
bogdanm | 86:04dd9b1680ae | 2447 | #define CAN_F7R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */ |
bogdanm | 86:04dd9b1680ae | 2448 | #define CAN_F7R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */ |
bogdanm | 86:04dd9b1680ae | 2449 | #define CAN_F7R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */ |
bogdanm | 86:04dd9b1680ae | 2450 | #define CAN_F7R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */ |
bogdanm | 86:04dd9b1680ae | 2451 | #define CAN_F7R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */ |
bogdanm | 86:04dd9b1680ae | 2452 | #define CAN_F7R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */ |
bogdanm | 86:04dd9b1680ae | 2453 | #define CAN_F7R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */ |
bogdanm | 86:04dd9b1680ae | 2454 | #define CAN_F7R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */ |
bogdanm | 86:04dd9b1680ae | 2455 | #define CAN_F7R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */ |
bogdanm | 86:04dd9b1680ae | 2456 | #define CAN_F7R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */ |
bogdanm | 86:04dd9b1680ae | 2457 | #define CAN_F7R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */ |
bogdanm | 86:04dd9b1680ae | 2458 | #define CAN_F7R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */ |
bogdanm | 86:04dd9b1680ae | 2459 | |
bogdanm | 86:04dd9b1680ae | 2460 | /******************* Bit definition for CAN_F8R1 register *******************/ |
bogdanm | 86:04dd9b1680ae | 2461 | #define CAN_F8R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */ |
bogdanm | 86:04dd9b1680ae | 2462 | #define CAN_F8R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */ |
bogdanm | 86:04dd9b1680ae | 2463 | #define CAN_F8R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */ |
bogdanm | 86:04dd9b1680ae | 2464 | #define CAN_F8R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */ |
bogdanm | 86:04dd9b1680ae | 2465 | #define CAN_F8R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */ |
bogdanm | 86:04dd9b1680ae | 2466 | #define CAN_F8R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */ |
bogdanm | 86:04dd9b1680ae | 2467 | #define CAN_F8R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */ |
bogdanm | 86:04dd9b1680ae | 2468 | #define CAN_F8R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */ |
bogdanm | 86:04dd9b1680ae | 2469 | #define CAN_F8R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */ |
bogdanm | 86:04dd9b1680ae | 2470 | #define CAN_F8R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */ |
bogdanm | 86:04dd9b1680ae | 2471 | #define CAN_F8R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */ |
bogdanm | 86:04dd9b1680ae | 2472 | #define CAN_F8R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */ |
bogdanm | 86:04dd9b1680ae | 2473 | #define CAN_F8R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */ |
bogdanm | 86:04dd9b1680ae | 2474 | #define CAN_F8R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */ |
bogdanm | 86:04dd9b1680ae | 2475 | #define CAN_F8R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */ |
bogdanm | 86:04dd9b1680ae | 2476 | #define CAN_F8R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */ |
bogdanm | 86:04dd9b1680ae | 2477 | #define CAN_F8R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */ |
bogdanm | 86:04dd9b1680ae | 2478 | #define CAN_F8R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */ |
bogdanm | 86:04dd9b1680ae | 2479 | #define CAN_F8R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */ |
bogdanm | 86:04dd9b1680ae | 2480 | #define CAN_F8R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */ |
bogdanm | 86:04dd9b1680ae | 2481 | #define CAN_F8R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */ |
bogdanm | 86:04dd9b1680ae | 2482 | #define CAN_F8R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */ |
bogdanm | 86:04dd9b1680ae | 2483 | #define CAN_F8R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */ |
bogdanm | 86:04dd9b1680ae | 2484 | #define CAN_F8R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */ |
bogdanm | 86:04dd9b1680ae | 2485 | #define CAN_F8R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */ |
bogdanm | 86:04dd9b1680ae | 2486 | #define CAN_F8R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */ |
bogdanm | 86:04dd9b1680ae | 2487 | #define CAN_F8R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */ |
bogdanm | 86:04dd9b1680ae | 2488 | #define CAN_F8R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */ |
bogdanm | 86:04dd9b1680ae | 2489 | #define CAN_F8R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */ |
bogdanm | 86:04dd9b1680ae | 2490 | #define CAN_F8R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */ |
bogdanm | 86:04dd9b1680ae | 2491 | #define CAN_F8R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */ |
bogdanm | 86:04dd9b1680ae | 2492 | #define CAN_F8R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */ |
bogdanm | 86:04dd9b1680ae | 2493 | |
bogdanm | 86:04dd9b1680ae | 2494 | /******************* Bit definition for CAN_F9R1 register *******************/ |
bogdanm | 86:04dd9b1680ae | 2495 | #define CAN_F9R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */ |
bogdanm | 86:04dd9b1680ae | 2496 | #define CAN_F9R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */ |
bogdanm | 86:04dd9b1680ae | 2497 | #define CAN_F9R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */ |
bogdanm | 86:04dd9b1680ae | 2498 | #define CAN_F9R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */ |
bogdanm | 86:04dd9b1680ae | 2499 | #define CAN_F9R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */ |
bogdanm | 86:04dd9b1680ae | 2500 | #define CAN_F9R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */ |
bogdanm | 86:04dd9b1680ae | 2501 | #define CAN_F9R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */ |
bogdanm | 86:04dd9b1680ae | 2502 | #define CAN_F9R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */ |
bogdanm | 86:04dd9b1680ae | 2503 | #define CAN_F9R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */ |
bogdanm | 86:04dd9b1680ae | 2504 | #define CAN_F9R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */ |
bogdanm | 86:04dd9b1680ae | 2505 | #define CAN_F9R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */ |
bogdanm | 86:04dd9b1680ae | 2506 | #define CAN_F9R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */ |
bogdanm | 86:04dd9b1680ae | 2507 | #define CAN_F9R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */ |
bogdanm | 86:04dd9b1680ae | 2508 | #define CAN_F9R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */ |
bogdanm | 86:04dd9b1680ae | 2509 | #define CAN_F9R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */ |
bogdanm | 86:04dd9b1680ae | 2510 | #define CAN_F9R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */ |
bogdanm | 86:04dd9b1680ae | 2511 | #define CAN_F9R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */ |
bogdanm | 86:04dd9b1680ae | 2512 | #define CAN_F9R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */ |
bogdanm | 86:04dd9b1680ae | 2513 | #define CAN_F9R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */ |
bogdanm | 86:04dd9b1680ae | 2514 | #define CAN_F9R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */ |
bogdanm | 86:04dd9b1680ae | 2515 | #define CAN_F9R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */ |
bogdanm | 86:04dd9b1680ae | 2516 | #define CAN_F9R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */ |
bogdanm | 86:04dd9b1680ae | 2517 | #define CAN_F9R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */ |
bogdanm | 86:04dd9b1680ae | 2518 | #define CAN_F9R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */ |
bogdanm | 86:04dd9b1680ae | 2519 | #define CAN_F9R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */ |
bogdanm | 86:04dd9b1680ae | 2520 | #define CAN_F9R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */ |
bogdanm | 86:04dd9b1680ae | 2521 | #define CAN_F9R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */ |
bogdanm | 86:04dd9b1680ae | 2522 | #define CAN_F9R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */ |
bogdanm | 86:04dd9b1680ae | 2523 | #define CAN_F9R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */ |
bogdanm | 86:04dd9b1680ae | 2524 | #define CAN_F9R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */ |
bogdanm | 86:04dd9b1680ae | 2525 | #define CAN_F9R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */ |
bogdanm | 86:04dd9b1680ae | 2526 | #define CAN_F9R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */ |
bogdanm | 86:04dd9b1680ae | 2527 | |
bogdanm | 86:04dd9b1680ae | 2528 | /******************* Bit definition for CAN_F10R1 register ******************/ |
bogdanm | 86:04dd9b1680ae | 2529 | #define CAN_F10R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */ |
bogdanm | 86:04dd9b1680ae | 2530 | #define CAN_F10R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */ |
bogdanm | 86:04dd9b1680ae | 2531 | #define CAN_F10R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */ |
bogdanm | 86:04dd9b1680ae | 2532 | #define CAN_F10R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */ |
bogdanm | 86:04dd9b1680ae | 2533 | #define CAN_F10R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */ |
bogdanm | 86:04dd9b1680ae | 2534 | #define CAN_F10R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */ |
bogdanm | 86:04dd9b1680ae | 2535 | #define CAN_F10R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */ |
bogdanm | 86:04dd9b1680ae | 2536 | #define CAN_F10R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */ |
bogdanm | 86:04dd9b1680ae | 2537 | #define CAN_F10R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */ |
bogdanm | 86:04dd9b1680ae | 2538 | #define CAN_F10R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */ |
bogdanm | 86:04dd9b1680ae | 2539 | #define CAN_F10R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */ |
bogdanm | 86:04dd9b1680ae | 2540 | #define CAN_F10R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */ |
bogdanm | 86:04dd9b1680ae | 2541 | #define CAN_F10R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */ |
bogdanm | 86:04dd9b1680ae | 2542 | #define CAN_F10R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */ |
bogdanm | 86:04dd9b1680ae | 2543 | #define CAN_F10R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */ |
bogdanm | 86:04dd9b1680ae | 2544 | #define CAN_F10R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */ |
bogdanm | 86:04dd9b1680ae | 2545 | #define CAN_F10R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */ |
bogdanm | 86:04dd9b1680ae | 2546 | #define CAN_F10R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */ |
bogdanm | 86:04dd9b1680ae | 2547 | #define CAN_F10R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */ |
bogdanm | 86:04dd9b1680ae | 2548 | #define CAN_F10R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */ |
bogdanm | 86:04dd9b1680ae | 2549 | #define CAN_F10R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */ |
bogdanm | 86:04dd9b1680ae | 2550 | #define CAN_F10R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */ |
bogdanm | 86:04dd9b1680ae | 2551 | #define CAN_F10R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */ |
bogdanm | 86:04dd9b1680ae | 2552 | #define CAN_F10R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */ |
bogdanm | 86:04dd9b1680ae | 2553 | #define CAN_F10R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */ |
bogdanm | 86:04dd9b1680ae | 2554 | #define CAN_F10R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */ |
bogdanm | 86:04dd9b1680ae | 2555 | #define CAN_F10R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */ |
bogdanm | 86:04dd9b1680ae | 2556 | #define CAN_F10R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */ |
bogdanm | 86:04dd9b1680ae | 2557 | #define CAN_F10R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */ |
bogdanm | 86:04dd9b1680ae | 2558 | #define CAN_F10R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */ |
bogdanm | 86:04dd9b1680ae | 2559 | #define CAN_F10R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */ |
bogdanm | 86:04dd9b1680ae | 2560 | #define CAN_F10R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */ |
bogdanm | 86:04dd9b1680ae | 2561 | |
bogdanm | 86:04dd9b1680ae | 2562 | /******************* Bit definition for CAN_F11R1 register ******************/ |
bogdanm | 86:04dd9b1680ae | 2563 | #define CAN_F11R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */ |
bogdanm | 86:04dd9b1680ae | 2564 | #define CAN_F11R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */ |
bogdanm | 86:04dd9b1680ae | 2565 | #define CAN_F11R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */ |
bogdanm | 86:04dd9b1680ae | 2566 | #define CAN_F11R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */ |
bogdanm | 86:04dd9b1680ae | 2567 | #define CAN_F11R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */ |
bogdanm | 86:04dd9b1680ae | 2568 | #define CAN_F11R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */ |
bogdanm | 86:04dd9b1680ae | 2569 | #define CAN_F11R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */ |
bogdanm | 86:04dd9b1680ae | 2570 | #define CAN_F11R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */ |
bogdanm | 86:04dd9b1680ae | 2571 | #define CAN_F11R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */ |
bogdanm | 86:04dd9b1680ae | 2572 | #define CAN_F11R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */ |
bogdanm | 86:04dd9b1680ae | 2573 | #define CAN_F11R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */ |
bogdanm | 86:04dd9b1680ae | 2574 | #define CAN_F11R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */ |
bogdanm | 86:04dd9b1680ae | 2575 | #define CAN_F11R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */ |
bogdanm | 86:04dd9b1680ae | 2576 | #define CAN_F11R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */ |
bogdanm | 86:04dd9b1680ae | 2577 | #define CAN_F11R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */ |
bogdanm | 86:04dd9b1680ae | 2578 | #define CAN_F11R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */ |
bogdanm | 86:04dd9b1680ae | 2579 | #define CAN_F11R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */ |
bogdanm | 86:04dd9b1680ae | 2580 | #define CAN_F11R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */ |
bogdanm | 86:04dd9b1680ae | 2581 | #define CAN_F11R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */ |
bogdanm | 86:04dd9b1680ae | 2582 | #define CAN_F11R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */ |
bogdanm | 86:04dd9b1680ae | 2583 | #define CAN_F11R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */ |
bogdanm | 86:04dd9b1680ae | 2584 | #define CAN_F11R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */ |
bogdanm | 86:04dd9b1680ae | 2585 | #define CAN_F11R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */ |
bogdanm | 86:04dd9b1680ae | 2586 | #define CAN_F11R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */ |
bogdanm | 86:04dd9b1680ae | 2587 | #define CAN_F11R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */ |
bogdanm | 86:04dd9b1680ae | 2588 | #define CAN_F11R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */ |
bogdanm | 86:04dd9b1680ae | 2589 | #define CAN_F11R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */ |
bogdanm | 86:04dd9b1680ae | 2590 | #define CAN_F11R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */ |
bogdanm | 86:04dd9b1680ae | 2591 | #define CAN_F11R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */ |
bogdanm | 86:04dd9b1680ae | 2592 | #define CAN_F11R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */ |
bogdanm | 86:04dd9b1680ae | 2593 | #define CAN_F11R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */ |
bogdanm | 86:04dd9b1680ae | 2594 | #define CAN_F11R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */ |
bogdanm | 86:04dd9b1680ae | 2595 | |
bogdanm | 86:04dd9b1680ae | 2596 | /******************* Bit definition for CAN_F12R1 register ******************/ |
bogdanm | 86:04dd9b1680ae | 2597 | #define CAN_F12R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */ |
bogdanm | 86:04dd9b1680ae | 2598 | #define CAN_F12R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */ |
bogdanm | 86:04dd9b1680ae | 2599 | #define CAN_F12R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */ |
bogdanm | 86:04dd9b1680ae | 2600 | #define CAN_F12R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */ |
bogdanm | 86:04dd9b1680ae | 2601 | #define CAN_F12R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */ |
bogdanm | 86:04dd9b1680ae | 2602 | #define CAN_F12R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */ |
bogdanm | 86:04dd9b1680ae | 2603 | #define CAN_F12R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */ |
bogdanm | 86:04dd9b1680ae | 2604 | #define CAN_F12R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */ |
bogdanm | 86:04dd9b1680ae | 2605 | #define CAN_F12R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */ |
bogdanm | 86:04dd9b1680ae | 2606 | #define CAN_F12R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */ |
bogdanm | 86:04dd9b1680ae | 2607 | #define CAN_F12R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */ |
bogdanm | 86:04dd9b1680ae | 2608 | #define CAN_F12R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */ |
bogdanm | 86:04dd9b1680ae | 2609 | #define CAN_F12R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */ |
bogdanm | 86:04dd9b1680ae | 2610 | #define CAN_F12R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */ |
bogdanm | 86:04dd9b1680ae | 2611 | #define CAN_F12R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */ |
bogdanm | 86:04dd9b1680ae | 2612 | #define CAN_F12R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */ |
bogdanm | 86:04dd9b1680ae | 2613 | #define CAN_F12R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */ |
bogdanm | 86:04dd9b1680ae | 2614 | #define CAN_F12R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */ |
bogdanm | 86:04dd9b1680ae | 2615 | #define CAN_F12R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */ |
bogdanm | 86:04dd9b1680ae | 2616 | #define CAN_F12R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */ |
bogdanm | 86:04dd9b1680ae | 2617 | #define CAN_F12R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */ |
bogdanm | 86:04dd9b1680ae | 2618 | #define CAN_F12R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */ |
bogdanm | 86:04dd9b1680ae | 2619 | #define CAN_F12R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */ |
bogdanm | 86:04dd9b1680ae | 2620 | #define CAN_F12R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */ |
bogdanm | 86:04dd9b1680ae | 2621 | #define CAN_F12R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */ |
bogdanm | 86:04dd9b1680ae | 2622 | #define CAN_F12R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */ |
bogdanm | 86:04dd9b1680ae | 2623 | #define CAN_F12R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */ |
bogdanm | 86:04dd9b1680ae | 2624 | #define CAN_F12R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */ |
bogdanm | 86:04dd9b1680ae | 2625 | #define CAN_F12R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */ |
bogdanm | 86:04dd9b1680ae | 2626 | #define CAN_F12R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */ |
bogdanm | 86:04dd9b1680ae | 2627 | #define CAN_F12R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */ |
bogdanm | 86:04dd9b1680ae | 2628 | #define CAN_F12R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */ |
bogdanm | 86:04dd9b1680ae | 2629 | |
bogdanm | 86:04dd9b1680ae | 2630 | /******************* Bit definition for CAN_F13R1 register ******************/ |
bogdanm | 86:04dd9b1680ae | 2631 | #define CAN_F13R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */ |
bogdanm | 86:04dd9b1680ae | 2632 | #define CAN_F13R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */ |
bogdanm | 86:04dd9b1680ae | 2633 | #define CAN_F13R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */ |
bogdanm | 86:04dd9b1680ae | 2634 | #define CAN_F13R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */ |
bogdanm | 86:04dd9b1680ae | 2635 | #define CAN_F13R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */ |
bogdanm | 86:04dd9b1680ae | 2636 | #define CAN_F13R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */ |
bogdanm | 86:04dd9b1680ae | 2637 | #define CAN_F13R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */ |
bogdanm | 86:04dd9b1680ae | 2638 | #define CAN_F13R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */ |
bogdanm | 86:04dd9b1680ae | 2639 | #define CAN_F13R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */ |
bogdanm | 86:04dd9b1680ae | 2640 | #define CAN_F13R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */ |
bogdanm | 86:04dd9b1680ae | 2641 | #define CAN_F13R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */ |
bogdanm | 86:04dd9b1680ae | 2642 | #define CAN_F13R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */ |
bogdanm | 86:04dd9b1680ae | 2643 | #define CAN_F13R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */ |
bogdanm | 86:04dd9b1680ae | 2644 | #define CAN_F13R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */ |
bogdanm | 86:04dd9b1680ae | 2645 | #define CAN_F13R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */ |
bogdanm | 86:04dd9b1680ae | 2646 | #define CAN_F13R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */ |
bogdanm | 86:04dd9b1680ae | 2647 | #define CAN_F13R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */ |
bogdanm | 86:04dd9b1680ae | 2648 | #define CAN_F13R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */ |
bogdanm | 86:04dd9b1680ae | 2649 | #define CAN_F13R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */ |
bogdanm | 86:04dd9b1680ae | 2650 | #define CAN_F13R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */ |
bogdanm | 86:04dd9b1680ae | 2651 | #define CAN_F13R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */ |
bogdanm | 86:04dd9b1680ae | 2652 | #define CAN_F13R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */ |
bogdanm | 86:04dd9b1680ae | 2653 | #define CAN_F13R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */ |
bogdanm | 86:04dd9b1680ae | 2654 | #define CAN_F13R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */ |
bogdanm | 86:04dd9b1680ae | 2655 | #define CAN_F13R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */ |
bogdanm | 86:04dd9b1680ae | 2656 | #define CAN_F13R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */ |
bogdanm | 86:04dd9b1680ae | 2657 | #define CAN_F13R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */ |
bogdanm | 86:04dd9b1680ae | 2658 | #define CAN_F13R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */ |
bogdanm | 86:04dd9b1680ae | 2659 | #define CAN_F13R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */ |
bogdanm | 86:04dd9b1680ae | 2660 | #define CAN_F13R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */ |
bogdanm | 86:04dd9b1680ae | 2661 | #define CAN_F13R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */ |
bogdanm | 86:04dd9b1680ae | 2662 | #define CAN_F13R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */ |
bogdanm | 86:04dd9b1680ae | 2663 | |
bogdanm | 86:04dd9b1680ae | 2664 | /******************* Bit definition for CAN_F0R2 register *******************/ |
bogdanm | 86:04dd9b1680ae | 2665 | #define CAN_F0R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */ |
bogdanm | 86:04dd9b1680ae | 2666 | #define CAN_F0R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */ |
bogdanm | 86:04dd9b1680ae | 2667 | #define CAN_F0R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */ |
bogdanm | 86:04dd9b1680ae | 2668 | #define CAN_F0R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */ |
bogdanm | 86:04dd9b1680ae | 2669 | #define CAN_F0R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */ |
bogdanm | 86:04dd9b1680ae | 2670 | #define CAN_F0R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */ |
bogdanm | 86:04dd9b1680ae | 2671 | #define CAN_F0R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */ |
bogdanm | 86:04dd9b1680ae | 2672 | #define CAN_F0R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */ |
bogdanm | 86:04dd9b1680ae | 2673 | #define CAN_F0R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */ |
bogdanm | 86:04dd9b1680ae | 2674 | #define CAN_F0R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */ |
bogdanm | 86:04dd9b1680ae | 2675 | #define CAN_F0R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */ |
bogdanm | 86:04dd9b1680ae | 2676 | #define CAN_F0R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */ |
bogdanm | 86:04dd9b1680ae | 2677 | #define CAN_F0R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */ |
bogdanm | 86:04dd9b1680ae | 2678 | #define CAN_F0R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */ |
bogdanm | 86:04dd9b1680ae | 2679 | #define CAN_F0R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */ |
bogdanm | 86:04dd9b1680ae | 2680 | #define CAN_F0R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */ |
bogdanm | 86:04dd9b1680ae | 2681 | #define CAN_F0R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */ |
bogdanm | 86:04dd9b1680ae | 2682 | #define CAN_F0R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */ |
bogdanm | 86:04dd9b1680ae | 2683 | #define CAN_F0R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */ |
bogdanm | 86:04dd9b1680ae | 2684 | #define CAN_F0R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */ |
bogdanm | 86:04dd9b1680ae | 2685 | #define CAN_F0R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */ |
bogdanm | 86:04dd9b1680ae | 2686 | #define CAN_F0R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */ |
bogdanm | 86:04dd9b1680ae | 2687 | #define CAN_F0R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */ |
bogdanm | 86:04dd9b1680ae | 2688 | #define CAN_F0R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */ |
bogdanm | 86:04dd9b1680ae | 2689 | #define CAN_F0R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */ |
bogdanm | 86:04dd9b1680ae | 2690 | #define CAN_F0R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */ |
bogdanm | 86:04dd9b1680ae | 2691 | #define CAN_F0R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */ |
bogdanm | 86:04dd9b1680ae | 2692 | #define CAN_F0R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */ |
bogdanm | 86:04dd9b1680ae | 2693 | #define CAN_F0R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */ |
bogdanm | 86:04dd9b1680ae | 2694 | #define CAN_F0R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */ |
bogdanm | 86:04dd9b1680ae | 2695 | #define CAN_F0R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */ |
bogdanm | 86:04dd9b1680ae | 2696 | #define CAN_F0R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */ |
bogdanm | 86:04dd9b1680ae | 2697 | |
bogdanm | 86:04dd9b1680ae | 2698 | /******************* Bit definition for CAN_F1R2 register *******************/ |
bogdanm | 86:04dd9b1680ae | 2699 | #define CAN_F1R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */ |
bogdanm | 86:04dd9b1680ae | 2700 | #define CAN_F1R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */ |
bogdanm | 86:04dd9b1680ae | 2701 | #define CAN_F1R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */ |
bogdanm | 86:04dd9b1680ae | 2702 | #define CAN_F1R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */ |
bogdanm | 86:04dd9b1680ae | 2703 | #define CAN_F1R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */ |
bogdanm | 86:04dd9b1680ae | 2704 | #define CAN_F1R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */ |
bogdanm | 86:04dd9b1680ae | 2705 | #define CAN_F1R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */ |
bogdanm | 86:04dd9b1680ae | 2706 | #define CAN_F1R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */ |
bogdanm | 86:04dd9b1680ae | 2707 | #define CAN_F1R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */ |
bogdanm | 86:04dd9b1680ae | 2708 | #define CAN_F1R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */ |
bogdanm | 86:04dd9b1680ae | 2709 | #define CAN_F1R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */ |
bogdanm | 86:04dd9b1680ae | 2710 | #define CAN_F1R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */ |
bogdanm | 86:04dd9b1680ae | 2711 | #define CAN_F1R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */ |
bogdanm | 86:04dd9b1680ae | 2712 | #define CAN_F1R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */ |
bogdanm | 86:04dd9b1680ae | 2713 | #define CAN_F1R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */ |
bogdanm | 86:04dd9b1680ae | 2714 | #define CAN_F1R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */ |
bogdanm | 86:04dd9b1680ae | 2715 | #define CAN_F1R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */ |
bogdanm | 86:04dd9b1680ae | 2716 | #define CAN_F1R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */ |
bogdanm | 86:04dd9b1680ae | 2717 | #define CAN_F1R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */ |
bogdanm | 86:04dd9b1680ae | 2718 | #define CAN_F1R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */ |
bogdanm | 86:04dd9b1680ae | 2719 | #define CAN_F1R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */ |
bogdanm | 86:04dd9b1680ae | 2720 | #define CAN_F1R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */ |
bogdanm | 86:04dd9b1680ae | 2721 | #define CAN_F1R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */ |
bogdanm | 86:04dd9b1680ae | 2722 | #define CAN_F1R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */ |
bogdanm | 86:04dd9b1680ae | 2723 | #define CAN_F1R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */ |
bogdanm | 86:04dd9b1680ae | 2724 | #define CAN_F1R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */ |
bogdanm | 86:04dd9b1680ae | 2725 | #define CAN_F1R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */ |
bogdanm | 86:04dd9b1680ae | 2726 | #define CAN_F1R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */ |
bogdanm | 86:04dd9b1680ae | 2727 | #define CAN_F1R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */ |
bogdanm | 86:04dd9b1680ae | 2728 | #define CAN_F1R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */ |
bogdanm | 86:04dd9b1680ae | 2729 | #define CAN_F1R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */ |
bogdanm | 86:04dd9b1680ae | 2730 | #define CAN_F1R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */ |
bogdanm | 86:04dd9b1680ae | 2731 | |
bogdanm | 86:04dd9b1680ae | 2732 | /******************* Bit definition for CAN_F2R2 register *******************/ |
bogdanm | 86:04dd9b1680ae | 2733 | #define CAN_F2R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */ |
bogdanm | 86:04dd9b1680ae | 2734 | #define CAN_F2R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */ |
bogdanm | 86:04dd9b1680ae | 2735 | #define CAN_F2R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */ |
bogdanm | 86:04dd9b1680ae | 2736 | #define CAN_F2R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */ |
bogdanm | 86:04dd9b1680ae | 2737 | #define CAN_F2R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */ |
bogdanm | 86:04dd9b1680ae | 2738 | #define CAN_F2R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */ |
bogdanm | 86:04dd9b1680ae | 2739 | #define CAN_F2R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */ |
bogdanm | 86:04dd9b1680ae | 2740 | #define CAN_F2R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */ |
bogdanm | 86:04dd9b1680ae | 2741 | #define CAN_F2R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */ |
bogdanm | 86:04dd9b1680ae | 2742 | #define CAN_F2R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */ |
bogdanm | 86:04dd9b1680ae | 2743 | #define CAN_F2R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */ |
bogdanm | 86:04dd9b1680ae | 2744 | #define CAN_F2R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */ |
bogdanm | 86:04dd9b1680ae | 2745 | #define CAN_F2R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */ |
bogdanm | 86:04dd9b1680ae | 2746 | #define CAN_F2R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */ |
bogdanm | 86:04dd9b1680ae | 2747 | #define CAN_F2R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */ |
bogdanm | 86:04dd9b1680ae | 2748 | #define CAN_F2R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */ |
bogdanm | 86:04dd9b1680ae | 2749 | #define CAN_F2R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */ |
bogdanm | 86:04dd9b1680ae | 2750 | #define CAN_F2R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */ |
bogdanm | 86:04dd9b1680ae | 2751 | #define CAN_F2R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */ |
bogdanm | 86:04dd9b1680ae | 2752 | #define CAN_F2R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */ |
bogdanm | 86:04dd9b1680ae | 2753 | #define CAN_F2R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */ |
bogdanm | 86:04dd9b1680ae | 2754 | #define CAN_F2R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */ |
bogdanm | 86:04dd9b1680ae | 2755 | #define CAN_F2R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */ |
bogdanm | 86:04dd9b1680ae | 2756 | #define CAN_F2R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */ |
bogdanm | 86:04dd9b1680ae | 2757 | #define CAN_F2R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */ |
bogdanm | 86:04dd9b1680ae | 2758 | #define CAN_F2R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */ |
bogdanm | 86:04dd9b1680ae | 2759 | #define CAN_F2R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */ |
bogdanm | 86:04dd9b1680ae | 2760 | #define CAN_F2R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */ |
bogdanm | 86:04dd9b1680ae | 2761 | #define CAN_F2R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */ |
bogdanm | 86:04dd9b1680ae | 2762 | #define CAN_F2R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */ |
bogdanm | 86:04dd9b1680ae | 2763 | #define CAN_F2R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */ |
bogdanm | 86:04dd9b1680ae | 2764 | #define CAN_F2R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */ |
bogdanm | 86:04dd9b1680ae | 2765 | |
bogdanm | 86:04dd9b1680ae | 2766 | /******************* Bit definition for CAN_F3R2 register *******************/ |
bogdanm | 86:04dd9b1680ae | 2767 | #define CAN_F3R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */ |
bogdanm | 86:04dd9b1680ae | 2768 | #define CAN_F3R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */ |
bogdanm | 86:04dd9b1680ae | 2769 | #define CAN_F3R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */ |
bogdanm | 86:04dd9b1680ae | 2770 | #define CAN_F3R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */ |
bogdanm | 86:04dd9b1680ae | 2771 | #define CAN_F3R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */ |
bogdanm | 86:04dd9b1680ae | 2772 | #define CAN_F3R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */ |
bogdanm | 86:04dd9b1680ae | 2773 | #define CAN_F3R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */ |
bogdanm | 86:04dd9b1680ae | 2774 | #define CAN_F3R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */ |
bogdanm | 86:04dd9b1680ae | 2775 | #define CAN_F3R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */ |
bogdanm | 86:04dd9b1680ae | 2776 | #define CAN_F3R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */ |
bogdanm | 86:04dd9b1680ae | 2777 | #define CAN_F3R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */ |
bogdanm | 86:04dd9b1680ae | 2778 | #define CAN_F3R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */ |
bogdanm | 86:04dd9b1680ae | 2779 | #define CAN_F3R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */ |
bogdanm | 86:04dd9b1680ae | 2780 | #define CAN_F3R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */ |
bogdanm | 86:04dd9b1680ae | 2781 | #define CAN_F3R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */ |
bogdanm | 86:04dd9b1680ae | 2782 | #define CAN_F3R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */ |
bogdanm | 86:04dd9b1680ae | 2783 | #define CAN_F3R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */ |
bogdanm | 86:04dd9b1680ae | 2784 | #define CAN_F3R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */ |
bogdanm | 86:04dd9b1680ae | 2785 | #define CAN_F3R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */ |
bogdanm | 86:04dd9b1680ae | 2786 | #define CAN_F3R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */ |
bogdanm | 86:04dd9b1680ae | 2787 | #define CAN_F3R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */ |
bogdanm | 86:04dd9b1680ae | 2788 | #define CAN_F3R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */ |
bogdanm | 86:04dd9b1680ae | 2789 | #define CAN_F3R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */ |
bogdanm | 86:04dd9b1680ae | 2790 | #define CAN_F3R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */ |
bogdanm | 86:04dd9b1680ae | 2791 | #define CAN_F3R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */ |
bogdanm | 86:04dd9b1680ae | 2792 | #define CAN_F3R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */ |
bogdanm | 86:04dd9b1680ae | 2793 | #define CAN_F3R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */ |
bogdanm | 86:04dd9b1680ae | 2794 | #define CAN_F3R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */ |
bogdanm | 86:04dd9b1680ae | 2795 | #define CAN_F3R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */ |
bogdanm | 86:04dd9b1680ae | 2796 | #define CAN_F3R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */ |
bogdanm | 86:04dd9b1680ae | 2797 | #define CAN_F3R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */ |
bogdanm | 86:04dd9b1680ae | 2798 | #define CAN_F3R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */ |
bogdanm | 86:04dd9b1680ae | 2799 | |
bogdanm | 86:04dd9b1680ae | 2800 | /******************* Bit definition for CAN_F4R2 register *******************/ |
bogdanm | 86:04dd9b1680ae | 2801 | #define CAN_F4R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */ |
bogdanm | 86:04dd9b1680ae | 2802 | #define CAN_F4R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */ |
bogdanm | 86:04dd9b1680ae | 2803 | #define CAN_F4R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */ |
bogdanm | 86:04dd9b1680ae | 2804 | #define CAN_F4R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */ |
bogdanm | 86:04dd9b1680ae | 2805 | #define CAN_F4R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */ |
bogdanm | 86:04dd9b1680ae | 2806 | #define CAN_F4R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */ |
bogdanm | 86:04dd9b1680ae | 2807 | #define CAN_F4R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */ |
bogdanm | 86:04dd9b1680ae | 2808 | #define CAN_F4R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */ |
bogdanm | 86:04dd9b1680ae | 2809 | #define CAN_F4R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */ |
bogdanm | 86:04dd9b1680ae | 2810 | #define CAN_F4R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */ |
bogdanm | 86:04dd9b1680ae | 2811 | #define CAN_F4R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */ |
bogdanm | 86:04dd9b1680ae | 2812 | #define CAN_F4R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */ |
bogdanm | 86:04dd9b1680ae | 2813 | #define CAN_F4R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */ |
bogdanm | 86:04dd9b1680ae | 2814 | #define CAN_F4R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */ |
bogdanm | 86:04dd9b1680ae | 2815 | #define CAN_F4R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */ |
bogdanm | 86:04dd9b1680ae | 2816 | #define CAN_F4R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */ |
bogdanm | 86:04dd9b1680ae | 2817 | #define CAN_F4R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */ |
bogdanm | 86:04dd9b1680ae | 2818 | #define CAN_F4R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */ |
bogdanm | 86:04dd9b1680ae | 2819 | #define CAN_F4R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */ |
bogdanm | 86:04dd9b1680ae | 2820 | #define CAN_F4R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */ |
bogdanm | 86:04dd9b1680ae | 2821 | #define CAN_F4R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */ |
bogdanm | 86:04dd9b1680ae | 2822 | #define CAN_F4R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */ |
bogdanm | 86:04dd9b1680ae | 2823 | #define CAN_F4R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */ |
bogdanm | 86:04dd9b1680ae | 2824 | #define CAN_F4R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */ |
bogdanm | 86:04dd9b1680ae | 2825 | #define CAN_F4R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */ |
bogdanm | 86:04dd9b1680ae | 2826 | #define CAN_F4R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */ |
bogdanm | 86:04dd9b1680ae | 2827 | #define CAN_F4R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */ |
bogdanm | 86:04dd9b1680ae | 2828 | #define CAN_F4R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */ |
bogdanm | 86:04dd9b1680ae | 2829 | #define CAN_F4R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */ |
bogdanm | 86:04dd9b1680ae | 2830 | #define CAN_F4R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */ |
bogdanm | 86:04dd9b1680ae | 2831 | #define CAN_F4R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */ |
bogdanm | 86:04dd9b1680ae | 2832 | #define CAN_F4R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */ |
bogdanm | 86:04dd9b1680ae | 2833 | |
bogdanm | 86:04dd9b1680ae | 2834 | /******************* Bit definition for CAN_F5R2 register *******************/ |
bogdanm | 86:04dd9b1680ae | 2835 | #define CAN_F5R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */ |
bogdanm | 86:04dd9b1680ae | 2836 | #define CAN_F5R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */ |
bogdanm | 86:04dd9b1680ae | 2837 | #define CAN_F5R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */ |
bogdanm | 86:04dd9b1680ae | 2838 | #define CAN_F5R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */ |
bogdanm | 86:04dd9b1680ae | 2839 | #define CAN_F5R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */ |
bogdanm | 86:04dd9b1680ae | 2840 | #define CAN_F5R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */ |
bogdanm | 86:04dd9b1680ae | 2841 | #define CAN_F5R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */ |
bogdanm | 86:04dd9b1680ae | 2842 | #define CAN_F5R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */ |
bogdanm | 86:04dd9b1680ae | 2843 | #define CAN_F5R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */ |
bogdanm | 86:04dd9b1680ae | 2844 | #define CAN_F5R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */ |
bogdanm | 86:04dd9b1680ae | 2845 | #define CAN_F5R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */ |
bogdanm | 86:04dd9b1680ae | 2846 | #define CAN_F5R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */ |
bogdanm | 86:04dd9b1680ae | 2847 | #define CAN_F5R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */ |
bogdanm | 86:04dd9b1680ae | 2848 | #define CAN_F5R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */ |
bogdanm | 86:04dd9b1680ae | 2849 | #define CAN_F5R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */ |
bogdanm | 86:04dd9b1680ae | 2850 | #define CAN_F5R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */ |
bogdanm | 86:04dd9b1680ae | 2851 | #define CAN_F5R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */ |
bogdanm | 86:04dd9b1680ae | 2852 | #define CAN_F5R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */ |
bogdanm | 86:04dd9b1680ae | 2853 | #define CAN_F5R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */ |
bogdanm | 86:04dd9b1680ae | 2854 | #define CAN_F5R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */ |
bogdanm | 86:04dd9b1680ae | 2855 | #define CAN_F5R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */ |
bogdanm | 86:04dd9b1680ae | 2856 | #define CAN_F5R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */ |
bogdanm | 86:04dd9b1680ae | 2857 | #define CAN_F5R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */ |
bogdanm | 86:04dd9b1680ae | 2858 | #define CAN_F5R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */ |
bogdanm | 86:04dd9b1680ae | 2859 | #define CAN_F5R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */ |
bogdanm | 86:04dd9b1680ae | 2860 | #define CAN_F5R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */ |
bogdanm | 86:04dd9b1680ae | 2861 | #define CAN_F5R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */ |
bogdanm | 86:04dd9b1680ae | 2862 | #define CAN_F5R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */ |
bogdanm | 86:04dd9b1680ae | 2863 | #define CAN_F5R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */ |
bogdanm | 86:04dd9b1680ae | 2864 | #define CAN_F5R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */ |
bogdanm | 86:04dd9b1680ae | 2865 | #define CAN_F5R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */ |
bogdanm | 86:04dd9b1680ae | 2866 | #define CAN_F5R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */ |
bogdanm | 86:04dd9b1680ae | 2867 | |
bogdanm | 86:04dd9b1680ae | 2868 | /******************* Bit definition for CAN_F6R2 register *******************/ |
bogdanm | 86:04dd9b1680ae | 2869 | #define CAN_F6R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */ |
bogdanm | 86:04dd9b1680ae | 2870 | #define CAN_F6R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */ |
bogdanm | 86:04dd9b1680ae | 2871 | #define CAN_F6R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */ |
bogdanm | 86:04dd9b1680ae | 2872 | #define CAN_F6R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */ |
bogdanm | 86:04dd9b1680ae | 2873 | #define CAN_F6R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */ |
bogdanm | 86:04dd9b1680ae | 2874 | #define CAN_F6R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */ |
bogdanm | 86:04dd9b1680ae | 2875 | #define CAN_F6R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */ |
bogdanm | 86:04dd9b1680ae | 2876 | #define CAN_F6R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */ |
bogdanm | 86:04dd9b1680ae | 2877 | #define CAN_F6R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */ |
bogdanm | 86:04dd9b1680ae | 2878 | #define CAN_F6R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */ |
bogdanm | 86:04dd9b1680ae | 2879 | #define CAN_F6R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */ |
bogdanm | 86:04dd9b1680ae | 2880 | #define CAN_F6R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */ |
bogdanm | 86:04dd9b1680ae | 2881 | #define CAN_F6R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */ |
bogdanm | 86:04dd9b1680ae | 2882 | #define CAN_F6R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */ |
bogdanm | 86:04dd9b1680ae | 2883 | #define CAN_F6R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */ |
bogdanm | 86:04dd9b1680ae | 2884 | #define CAN_F6R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */ |
bogdanm | 86:04dd9b1680ae | 2885 | #define CAN_F6R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */ |
bogdanm | 86:04dd9b1680ae | 2886 | #define CAN_F6R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */ |
bogdanm | 86:04dd9b1680ae | 2887 | #define CAN_F6R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */ |
bogdanm | 86:04dd9b1680ae | 2888 | #define CAN_F6R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */ |
bogdanm | 86:04dd9b1680ae | 2889 | #define CAN_F6R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */ |
bogdanm | 86:04dd9b1680ae | 2890 | #define CAN_F6R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */ |
bogdanm | 86:04dd9b1680ae | 2891 | #define CAN_F6R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */ |
bogdanm | 86:04dd9b1680ae | 2892 | #define CAN_F6R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */ |
bogdanm | 86:04dd9b1680ae | 2893 | #define CAN_F6R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */ |
bogdanm | 86:04dd9b1680ae | 2894 | #define CAN_F6R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */ |
bogdanm | 86:04dd9b1680ae | 2895 | #define CAN_F6R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */ |
bogdanm | 86:04dd9b1680ae | 2896 | #define CAN_F6R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */ |
bogdanm | 86:04dd9b1680ae | 2897 | #define CAN_F6R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */ |
bogdanm | 86:04dd9b1680ae | 2898 | #define CAN_F6R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */ |
bogdanm | 86:04dd9b1680ae | 2899 | #define CAN_F6R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */ |
bogdanm | 86:04dd9b1680ae | 2900 | #define CAN_F6R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */ |
bogdanm | 86:04dd9b1680ae | 2901 | |
bogdanm | 86:04dd9b1680ae | 2902 | /******************* Bit definition for CAN_F7R2 register *******************/ |
bogdanm | 86:04dd9b1680ae | 2903 | #define CAN_F7R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */ |
bogdanm | 86:04dd9b1680ae | 2904 | #define CAN_F7R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */ |
bogdanm | 86:04dd9b1680ae | 2905 | #define CAN_F7R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */ |
bogdanm | 86:04dd9b1680ae | 2906 | #define CAN_F7R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */ |
bogdanm | 86:04dd9b1680ae | 2907 | #define CAN_F7R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */ |
bogdanm | 86:04dd9b1680ae | 2908 | #define CAN_F7R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */ |
bogdanm | 86:04dd9b1680ae | 2909 | #define CAN_F7R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */ |
bogdanm | 86:04dd9b1680ae | 2910 | #define CAN_F7R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */ |
bogdanm | 86:04dd9b1680ae | 2911 | #define CAN_F7R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */ |
bogdanm | 86:04dd9b1680ae | 2912 | #define CAN_F7R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */ |
bogdanm | 86:04dd9b1680ae | 2913 | #define CAN_F7R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */ |
bogdanm | 86:04dd9b1680ae | 2914 | #define CAN_F7R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */ |
bogdanm | 86:04dd9b1680ae | 2915 | #define CAN_F7R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */ |
bogdanm | 86:04dd9b1680ae | 2916 | #define CAN_F7R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */ |
bogdanm | 86:04dd9b1680ae | 2917 | #define CAN_F7R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */ |
bogdanm | 86:04dd9b1680ae | 2918 | #define CAN_F7R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */ |
bogdanm | 86:04dd9b1680ae | 2919 | #define CAN_F7R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */ |
bogdanm | 86:04dd9b1680ae | 2920 | #define CAN_F7R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */ |
bogdanm | 86:04dd9b1680ae | 2921 | #define CAN_F7R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */ |
bogdanm | 86:04dd9b1680ae | 2922 | #define CAN_F7R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */ |
bogdanm | 86:04dd9b1680ae | 2923 | #define CAN_F7R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */ |
bogdanm | 86:04dd9b1680ae | 2924 | #define CAN_F7R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */ |
bogdanm | 86:04dd9b1680ae | 2925 | #define CAN_F7R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */ |
bogdanm | 86:04dd9b1680ae | 2926 | #define CAN_F7R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */ |
bogdanm | 86:04dd9b1680ae | 2927 | #define CAN_F7R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */ |
bogdanm | 86:04dd9b1680ae | 2928 | #define CAN_F7R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */ |
bogdanm | 86:04dd9b1680ae | 2929 | #define CAN_F7R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */ |
bogdanm | 86:04dd9b1680ae | 2930 | #define CAN_F7R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */ |
bogdanm | 86:04dd9b1680ae | 2931 | #define CAN_F7R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */ |
bogdanm | 86:04dd9b1680ae | 2932 | #define CAN_F7R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */ |
bogdanm | 86:04dd9b1680ae | 2933 | #define CAN_F7R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */ |
bogdanm | 86:04dd9b1680ae | 2934 | #define CAN_F7R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */ |
bogdanm | 86:04dd9b1680ae | 2935 | |
bogdanm | 86:04dd9b1680ae | 2936 | /******************* Bit definition for CAN_F8R2 register *******************/ |
bogdanm | 86:04dd9b1680ae | 2937 | #define CAN_F8R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */ |
bogdanm | 86:04dd9b1680ae | 2938 | #define CAN_F8R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */ |
bogdanm | 86:04dd9b1680ae | 2939 | #define CAN_F8R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */ |
bogdanm | 86:04dd9b1680ae | 2940 | #define CAN_F8R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */ |
bogdanm | 86:04dd9b1680ae | 2941 | #define CAN_F8R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */ |
bogdanm | 86:04dd9b1680ae | 2942 | #define CAN_F8R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */ |
bogdanm | 86:04dd9b1680ae | 2943 | #define CAN_F8R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */ |
bogdanm | 86:04dd9b1680ae | 2944 | #define CAN_F8R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */ |
bogdanm | 86:04dd9b1680ae | 2945 | #define CAN_F8R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */ |
bogdanm | 86:04dd9b1680ae | 2946 | #define CAN_F8R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */ |
bogdanm | 86:04dd9b1680ae | 2947 | #define CAN_F8R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */ |
bogdanm | 86:04dd9b1680ae | 2948 | #define CAN_F8R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */ |
bogdanm | 86:04dd9b1680ae | 2949 | #define CAN_F8R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */ |
bogdanm | 86:04dd9b1680ae | 2950 | #define CAN_F8R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */ |
bogdanm | 86:04dd9b1680ae | 2951 | #define CAN_F8R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */ |
bogdanm | 86:04dd9b1680ae | 2952 | #define CAN_F8R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */ |
bogdanm | 86:04dd9b1680ae | 2953 | #define CAN_F8R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */ |
bogdanm | 86:04dd9b1680ae | 2954 | #define CAN_F8R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */ |
bogdanm | 86:04dd9b1680ae | 2955 | #define CAN_F8R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */ |
bogdanm | 86:04dd9b1680ae | 2956 | #define CAN_F8R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */ |
bogdanm | 86:04dd9b1680ae | 2957 | #define CAN_F8R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */ |
bogdanm | 86:04dd9b1680ae | 2958 | #define CAN_F8R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */ |
bogdanm | 86:04dd9b1680ae | 2959 | #define CAN_F8R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */ |
bogdanm | 86:04dd9b1680ae | 2960 | #define CAN_F8R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */ |
bogdanm | 86:04dd9b1680ae | 2961 | #define CAN_F8R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */ |
bogdanm | 86:04dd9b1680ae | 2962 | #define CAN_F8R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */ |
bogdanm | 86:04dd9b1680ae | 2963 | #define CAN_F8R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */ |
bogdanm | 86:04dd9b1680ae | 2964 | #define CAN_F8R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */ |
bogdanm | 86:04dd9b1680ae | 2965 | #define CAN_F8R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */ |
bogdanm | 86:04dd9b1680ae | 2966 | #define CAN_F8R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */ |
bogdanm | 86:04dd9b1680ae | 2967 | #define CAN_F8R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */ |
bogdanm | 86:04dd9b1680ae | 2968 | #define CAN_F8R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */ |
bogdanm | 86:04dd9b1680ae | 2969 | |
bogdanm | 86:04dd9b1680ae | 2970 | /******************* Bit definition for CAN_F9R2 register *******************/ |
bogdanm | 86:04dd9b1680ae | 2971 | #define CAN_F9R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */ |
bogdanm | 86:04dd9b1680ae | 2972 | #define CAN_F9R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */ |
bogdanm | 86:04dd9b1680ae | 2973 | #define CAN_F9R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */ |
bogdanm | 86:04dd9b1680ae | 2974 | #define CAN_F9R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */ |
bogdanm | 86:04dd9b1680ae | 2975 | #define CAN_F9R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */ |
bogdanm | 86:04dd9b1680ae | 2976 | #define CAN_F9R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */ |
bogdanm | 86:04dd9b1680ae | 2977 | #define CAN_F9R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */ |
bogdanm | 86:04dd9b1680ae | 2978 | #define CAN_F9R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */ |
bogdanm | 86:04dd9b1680ae | 2979 | #define CAN_F9R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */ |
bogdanm | 86:04dd9b1680ae | 2980 | #define CAN_F9R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */ |
bogdanm | 86:04dd9b1680ae | 2981 | #define CAN_F9R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */ |
bogdanm | 86:04dd9b1680ae | 2982 | #define CAN_F9R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */ |
bogdanm | 86:04dd9b1680ae | 2983 | #define CAN_F9R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */ |
bogdanm | 86:04dd9b1680ae | 2984 | #define CAN_F9R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */ |
bogdanm | 86:04dd9b1680ae | 2985 | #define CAN_F9R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */ |
bogdanm | 86:04dd9b1680ae | 2986 | #define CAN_F9R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */ |
bogdanm | 86:04dd9b1680ae | 2987 | #define CAN_F9R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */ |
bogdanm | 86:04dd9b1680ae | 2988 | #define CAN_F9R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */ |
bogdanm | 86:04dd9b1680ae | 2989 | #define CAN_F9R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */ |
bogdanm | 86:04dd9b1680ae | 2990 | #define CAN_F9R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */ |
bogdanm | 86:04dd9b1680ae | 2991 | #define CAN_F9R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */ |
bogdanm | 86:04dd9b1680ae | 2992 | #define CAN_F9R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */ |
bogdanm | 86:04dd9b1680ae | 2993 | #define CAN_F9R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */ |
bogdanm | 86:04dd9b1680ae | 2994 | #define CAN_F9R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */ |
bogdanm | 86:04dd9b1680ae | 2995 | #define CAN_F9R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */ |
bogdanm | 86:04dd9b1680ae | 2996 | #define CAN_F9R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */ |
bogdanm | 86:04dd9b1680ae | 2997 | #define CAN_F9R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */ |
bogdanm | 86:04dd9b1680ae | 2998 | #define CAN_F9R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */ |
bogdanm | 86:04dd9b1680ae | 2999 | #define CAN_F9R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */ |
bogdanm | 86:04dd9b1680ae | 3000 | #define CAN_F9R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */ |
bogdanm | 86:04dd9b1680ae | 3001 | #define CAN_F9R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */ |
bogdanm | 86:04dd9b1680ae | 3002 | #define CAN_F9R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */ |
bogdanm | 86:04dd9b1680ae | 3003 | |
bogdanm | 86:04dd9b1680ae | 3004 | /******************* Bit definition for CAN_F10R2 register ******************/ |
bogdanm | 86:04dd9b1680ae | 3005 | #define CAN_F10R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */ |
bogdanm | 86:04dd9b1680ae | 3006 | #define CAN_F10R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */ |
bogdanm | 86:04dd9b1680ae | 3007 | #define CAN_F10R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */ |
bogdanm | 86:04dd9b1680ae | 3008 | #define CAN_F10R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */ |
bogdanm | 86:04dd9b1680ae | 3009 | #define CAN_F10R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */ |
bogdanm | 86:04dd9b1680ae | 3010 | #define CAN_F10R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */ |
bogdanm | 86:04dd9b1680ae | 3011 | #define CAN_F10R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */ |
bogdanm | 86:04dd9b1680ae | 3012 | #define CAN_F10R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */ |
bogdanm | 86:04dd9b1680ae | 3013 | #define CAN_F10R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */ |
bogdanm | 86:04dd9b1680ae | 3014 | #define CAN_F10R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */ |
bogdanm | 86:04dd9b1680ae | 3015 | #define CAN_F10R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */ |
bogdanm | 86:04dd9b1680ae | 3016 | #define CAN_F10R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */ |
bogdanm | 86:04dd9b1680ae | 3017 | #define CAN_F10R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */ |
bogdanm | 86:04dd9b1680ae | 3018 | #define CAN_F10R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */ |
bogdanm | 86:04dd9b1680ae | 3019 | #define CAN_F10R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */ |
bogdanm | 86:04dd9b1680ae | 3020 | #define CAN_F10R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */ |
bogdanm | 86:04dd9b1680ae | 3021 | #define CAN_F10R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */ |
bogdanm | 86:04dd9b1680ae | 3022 | #define CAN_F10R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */ |
bogdanm | 86:04dd9b1680ae | 3023 | #define CAN_F10R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */ |
bogdanm | 86:04dd9b1680ae | 3024 | #define CAN_F10R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */ |
bogdanm | 86:04dd9b1680ae | 3025 | #define CAN_F10R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */ |
bogdanm | 86:04dd9b1680ae | 3026 | #define CAN_F10R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */ |
bogdanm | 86:04dd9b1680ae | 3027 | #define CAN_F10R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */ |
bogdanm | 86:04dd9b1680ae | 3028 | #define CAN_F10R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */ |
bogdanm | 86:04dd9b1680ae | 3029 | #define CAN_F10R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */ |
bogdanm | 86:04dd9b1680ae | 3030 | #define CAN_F10R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */ |
bogdanm | 86:04dd9b1680ae | 3031 | #define CAN_F10R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */ |
bogdanm | 86:04dd9b1680ae | 3032 | #define CAN_F10R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */ |
bogdanm | 86:04dd9b1680ae | 3033 | #define CAN_F10R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */ |
bogdanm | 86:04dd9b1680ae | 3034 | #define CAN_F10R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */ |
bogdanm | 86:04dd9b1680ae | 3035 | #define CAN_F10R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */ |
bogdanm | 86:04dd9b1680ae | 3036 | #define CAN_F10R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */ |
bogdanm | 86:04dd9b1680ae | 3037 | |
bogdanm | 86:04dd9b1680ae | 3038 | /******************* Bit definition for CAN_F11R2 register ******************/ |
bogdanm | 86:04dd9b1680ae | 3039 | #define CAN_F11R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */ |
bogdanm | 86:04dd9b1680ae | 3040 | #define CAN_F11R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */ |
bogdanm | 86:04dd9b1680ae | 3041 | #define CAN_F11R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */ |
bogdanm | 86:04dd9b1680ae | 3042 | #define CAN_F11R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */ |
bogdanm | 86:04dd9b1680ae | 3043 | #define CAN_F11R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */ |
bogdanm | 86:04dd9b1680ae | 3044 | #define CAN_F11R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */ |
bogdanm | 86:04dd9b1680ae | 3045 | #define CAN_F11R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */ |
bogdanm | 86:04dd9b1680ae | 3046 | #define CAN_F11R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */ |
bogdanm | 86:04dd9b1680ae | 3047 | #define CAN_F11R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */ |
bogdanm | 86:04dd9b1680ae | 3048 | #define CAN_F11R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */ |
bogdanm | 86:04dd9b1680ae | 3049 | #define CAN_F11R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */ |
bogdanm | 86:04dd9b1680ae | 3050 | #define CAN_F11R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */ |
bogdanm | 86:04dd9b1680ae | 3051 | #define CAN_F11R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */ |
bogdanm | 86:04dd9b1680ae | 3052 | #define CAN_F11R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */ |
bogdanm | 86:04dd9b1680ae | 3053 | #define CAN_F11R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */ |
bogdanm | 86:04dd9b1680ae | 3054 | #define CAN_F11R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */ |
bogdanm | 86:04dd9b1680ae | 3055 | #define CAN_F11R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */ |
bogdanm | 86:04dd9b1680ae | 3056 | #define CAN_F11R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */ |
bogdanm | 86:04dd9b1680ae | 3057 | #define CAN_F11R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */ |
bogdanm | 86:04dd9b1680ae | 3058 | #define CAN_F11R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */ |
bogdanm | 86:04dd9b1680ae | 3059 | #define CAN_F11R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */ |
bogdanm | 86:04dd9b1680ae | 3060 | #define CAN_F11R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */ |
bogdanm | 86:04dd9b1680ae | 3061 | #define CAN_F11R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */ |
bogdanm | 86:04dd9b1680ae | 3062 | #define CAN_F11R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */ |
bogdanm | 86:04dd9b1680ae | 3063 | #define CAN_F11R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */ |
bogdanm | 86:04dd9b1680ae | 3064 | #define CAN_F11R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */ |
bogdanm | 86:04dd9b1680ae | 3065 | #define CAN_F11R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */ |
bogdanm | 86:04dd9b1680ae | 3066 | #define CAN_F11R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */ |
bogdanm | 86:04dd9b1680ae | 3067 | #define CAN_F11R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */ |
bogdanm | 86:04dd9b1680ae | 3068 | #define CAN_F11R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */ |
bogdanm | 86:04dd9b1680ae | 3069 | #define CAN_F11R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */ |
bogdanm | 86:04dd9b1680ae | 3070 | #define CAN_F11R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */ |
bogdanm | 86:04dd9b1680ae | 3071 | |
bogdanm | 86:04dd9b1680ae | 3072 | /******************* Bit definition for CAN_F12R2 register ******************/ |
bogdanm | 86:04dd9b1680ae | 3073 | #define CAN_F12R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */ |
bogdanm | 86:04dd9b1680ae | 3074 | #define CAN_F12R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */ |
bogdanm | 86:04dd9b1680ae | 3075 | #define CAN_F12R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */ |
bogdanm | 86:04dd9b1680ae | 3076 | #define CAN_F12R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */ |
bogdanm | 86:04dd9b1680ae | 3077 | #define CAN_F12R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */ |
bogdanm | 86:04dd9b1680ae | 3078 | #define CAN_F12R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */ |
bogdanm | 86:04dd9b1680ae | 3079 | #define CAN_F12R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */ |
bogdanm | 86:04dd9b1680ae | 3080 | #define CAN_F12R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */ |
bogdanm | 86:04dd9b1680ae | 3081 | #define CAN_F12R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */ |
bogdanm | 86:04dd9b1680ae | 3082 | #define CAN_F12R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */ |
bogdanm | 86:04dd9b1680ae | 3083 | #define CAN_F12R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */ |
bogdanm | 86:04dd9b1680ae | 3084 | #define CAN_F12R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */ |
bogdanm | 86:04dd9b1680ae | 3085 | #define CAN_F12R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */ |
bogdanm | 86:04dd9b1680ae | 3086 | #define CAN_F12R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */ |
bogdanm | 86:04dd9b1680ae | 3087 | #define CAN_F12R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */ |
bogdanm | 86:04dd9b1680ae | 3088 | #define CAN_F12R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */ |
bogdanm | 86:04dd9b1680ae | 3089 | #define CAN_F12R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */ |
bogdanm | 86:04dd9b1680ae | 3090 | #define CAN_F12R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */ |
bogdanm | 86:04dd9b1680ae | 3091 | #define CAN_F12R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */ |
bogdanm | 86:04dd9b1680ae | 3092 | #define CAN_F12R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */ |
bogdanm | 86:04dd9b1680ae | 3093 | #define CAN_F12R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */ |
bogdanm | 86:04dd9b1680ae | 3094 | #define CAN_F12R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */ |
bogdanm | 86:04dd9b1680ae | 3095 | #define CAN_F12R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */ |
bogdanm | 86:04dd9b1680ae | 3096 | #define CAN_F12R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */ |
bogdanm | 86:04dd9b1680ae | 3097 | #define CAN_F12R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */ |
bogdanm | 86:04dd9b1680ae | 3098 | #define CAN_F12R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */ |
bogdanm | 86:04dd9b1680ae | 3099 | #define CAN_F12R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */ |
bogdanm | 86:04dd9b1680ae | 3100 | #define CAN_F12R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */ |
bogdanm | 86:04dd9b1680ae | 3101 | #define CAN_F12R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */ |
bogdanm | 86:04dd9b1680ae | 3102 | #define CAN_F12R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */ |
bogdanm | 86:04dd9b1680ae | 3103 | #define CAN_F12R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */ |
bogdanm | 86:04dd9b1680ae | 3104 | #define CAN_F12R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */ |
bogdanm | 86:04dd9b1680ae | 3105 | |
bogdanm | 86:04dd9b1680ae | 3106 | /******************* Bit definition for CAN_F13R2 register ******************/ |
bogdanm | 86:04dd9b1680ae | 3107 | #define CAN_F13R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */ |
bogdanm | 86:04dd9b1680ae | 3108 | #define CAN_F13R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */ |
bogdanm | 86:04dd9b1680ae | 3109 | #define CAN_F13R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */ |
bogdanm | 86:04dd9b1680ae | 3110 | #define CAN_F13R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */ |
bogdanm | 86:04dd9b1680ae | 3111 | #define CAN_F13R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */ |
bogdanm | 86:04dd9b1680ae | 3112 | #define CAN_F13R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */ |
bogdanm | 86:04dd9b1680ae | 3113 | #define CAN_F13R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */ |
bogdanm | 86:04dd9b1680ae | 3114 | #define CAN_F13R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */ |
bogdanm | 86:04dd9b1680ae | 3115 | #define CAN_F13R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */ |
bogdanm | 86:04dd9b1680ae | 3116 | #define CAN_F13R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */ |
bogdanm | 86:04dd9b1680ae | 3117 | #define CAN_F13R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */ |
bogdanm | 86:04dd9b1680ae | 3118 | #define CAN_F13R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */ |
bogdanm | 86:04dd9b1680ae | 3119 | #define CAN_F13R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */ |
bogdanm | 86:04dd9b1680ae | 3120 | #define CAN_F13R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */ |
bogdanm | 86:04dd9b1680ae | 3121 | #define CAN_F13R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */ |
bogdanm | 86:04dd9b1680ae | 3122 | #define CAN_F13R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */ |
bogdanm | 86:04dd9b1680ae | 3123 | #define CAN_F13R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */ |
bogdanm | 86:04dd9b1680ae | 3124 | #define CAN_F13R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */ |
bogdanm | 86:04dd9b1680ae | 3125 | #define CAN_F13R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */ |
bogdanm | 86:04dd9b1680ae | 3126 | #define CAN_F13R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */ |
bogdanm | 86:04dd9b1680ae | 3127 | #define CAN_F13R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */ |
bogdanm | 86:04dd9b1680ae | 3128 | #define CAN_F13R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */ |
bogdanm | 86:04dd9b1680ae | 3129 | #define CAN_F13R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */ |
bogdanm | 86:04dd9b1680ae | 3130 | #define CAN_F13R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */ |
bogdanm | 86:04dd9b1680ae | 3131 | #define CAN_F13R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */ |
bogdanm | 86:04dd9b1680ae | 3132 | #define CAN_F13R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */ |
bogdanm | 86:04dd9b1680ae | 3133 | #define CAN_F13R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */ |
bogdanm | 86:04dd9b1680ae | 3134 | #define CAN_F13R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */ |
bogdanm | 86:04dd9b1680ae | 3135 | #define CAN_F13R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */ |
bogdanm | 86:04dd9b1680ae | 3136 | #define CAN_F13R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */ |
bogdanm | 86:04dd9b1680ae | 3137 | #define CAN_F13R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */ |
bogdanm | 86:04dd9b1680ae | 3138 | #define CAN_F13R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */ |
bogdanm | 86:04dd9b1680ae | 3139 | |
bogdanm | 86:04dd9b1680ae | 3140 | /******************************************************************************/ |
bogdanm | 86:04dd9b1680ae | 3141 | /* */ |
bogdanm | 86:04dd9b1680ae | 3142 | /* CRC calculation unit (CRC) */ |
bogdanm | 86:04dd9b1680ae | 3143 | /* */ |
bogdanm | 86:04dd9b1680ae | 3144 | /******************************************************************************/ |
bogdanm | 86:04dd9b1680ae | 3145 | /******************* Bit definition for CRC_DR register *********************/ |
bogdanm | 86:04dd9b1680ae | 3146 | #define CRC_DR_DR ((uint32_t)0xFFFFFFFF) /*!< Data register bits */ |
bogdanm | 86:04dd9b1680ae | 3147 | |
bogdanm | 86:04dd9b1680ae | 3148 | /******************* Bit definition for CRC_IDR register ********************/ |
bogdanm | 86:04dd9b1680ae | 3149 | #define CRC_IDR_IDR ((uint32_t)0xFF) /*!< General-purpose 8-bit data register bits */ |
bogdanm | 86:04dd9b1680ae | 3150 | |
bogdanm | 86:04dd9b1680ae | 3151 | /******************** Bit definition for CRC_CR register ********************/ |
bogdanm | 86:04dd9b1680ae | 3152 | #define CRC_CR_RESET ((uint32_t)0x00000001) /*!< RESET the CRC computation unit bit */ |
bogdanm | 86:04dd9b1680ae | 3153 | #define CRC_CR_POLYSIZE ((uint32_t)0x00000018) /*!< Polynomial size bits */ |
bogdanm | 86:04dd9b1680ae | 3154 | #define CRC_CR_POLYSIZE_0 ((uint32_t)0x00000008) /*!< Polynomial size bit 0 */ |
bogdanm | 86:04dd9b1680ae | 3155 | #define CRC_CR_POLYSIZE_1 ((uint32_t)0x00000010) /*!< Polynomial size bit 1 */ |
bogdanm | 86:04dd9b1680ae | 3156 | #define CRC_CR_REV_IN ((uint32_t)0x00000060) /*!< REV_IN Reverse Input Data bits */ |
bogdanm | 86:04dd9b1680ae | 3157 | #define CRC_CR_REV_IN_0 ((uint32_t)0x00000020) /*!< Bit 0 */ |
bogdanm | 86:04dd9b1680ae | 3158 | #define CRC_CR_REV_IN_1 ((uint32_t)0x00000040) /*!< Bit 1 */ |
bogdanm | 86:04dd9b1680ae | 3159 | #define CRC_CR_REV_OUT ((uint32_t)0x00000080) /*!< REV_OUT Reverse Output Data bits */ |
bogdanm | 86:04dd9b1680ae | 3160 | |
bogdanm | 86:04dd9b1680ae | 3161 | /******************* Bit definition for CRC_INIT register *******************/ |
bogdanm | 86:04dd9b1680ae | 3162 | #define CRC_INIT_INIT ((uint32_t)0xFFFFFFFF) /*!< Initial CRC value bits */ |
bogdanm | 86:04dd9b1680ae | 3163 | |
bogdanm | 86:04dd9b1680ae | 3164 | /******************* Bit definition for CRC_POL register ********************/ |
bogdanm | 86:04dd9b1680ae | 3165 | #define CRC_POL_POL ((uint32_t)0xFFFFFFFF) /*!< Coefficients of the polynomial */ |
bogdanm | 86:04dd9b1680ae | 3166 | |
bogdanm | 86:04dd9b1680ae | 3167 | /******************************************************************************/ |
bogdanm | 86:04dd9b1680ae | 3168 | /* */ |
bogdanm | 86:04dd9b1680ae | 3169 | /* Digital to Analog Converter (DAC) */ |
bogdanm | 86:04dd9b1680ae | 3170 | /* */ |
bogdanm | 86:04dd9b1680ae | 3171 | /******************************************************************************/ |
bogdanm | 86:04dd9b1680ae | 3172 | /******************** Bit definition for DAC_CR register ********************/ |
bogdanm | 86:04dd9b1680ae | 3173 | #define DAC_CR_EN1 ((uint32_t)0x00000001) /*!< DAC channel1 enable */ |
bogdanm | 86:04dd9b1680ae | 3174 | #define DAC_CR_BOFF1 ((uint32_t)0x00000002) /*!< DAC channel1 output buffer disable */ |
bogdanm | 86:04dd9b1680ae | 3175 | #define DAC_CR_TEN1 ((uint32_t)0x00000004) /*!< DAC channel1 Trigger enable */ |
bogdanm | 86:04dd9b1680ae | 3176 | |
bogdanm | 86:04dd9b1680ae | 3177 | #define DAC_CR_TSEL1 ((uint32_t)0x00000038) /*!< TSEL1[2:0] (DAC channel1 Trigger selection) */ |
bogdanm | 86:04dd9b1680ae | 3178 | #define DAC_CR_TSEL1_0 ((uint32_t)0x00000008) /*!< Bit 0 */ |
bogdanm | 86:04dd9b1680ae | 3179 | #define DAC_CR_TSEL1_1 ((uint32_t)0x00000010) /*!< Bit 1 */ |
bogdanm | 86:04dd9b1680ae | 3180 | #define DAC_CR_TSEL1_2 ((uint32_t)0x00000020) /*!< Bit 2 */ |
bogdanm | 86:04dd9b1680ae | 3181 | |
bogdanm | 86:04dd9b1680ae | 3182 | #define DAC_CR_WAVE1 ((uint32_t)0x000000C0) /*!< WAVE1[1:0] (DAC channel1 noise/triangle wave generation enable) */ |
bogdanm | 86:04dd9b1680ae | 3183 | #define DAC_CR_WAVE1_0 ((uint32_t)0x00000040) /*!< Bit 0 */ |
bogdanm | 86:04dd9b1680ae | 3184 | #define DAC_CR_WAVE1_1 ((uint32_t)0x00000080) /*!< Bit 1 */ |
bogdanm | 86:04dd9b1680ae | 3185 | |
bogdanm | 86:04dd9b1680ae | 3186 | #define DAC_CR_MAMP1 ((uint32_t)0x00000F00) /*!< MAMP1[3:0] (DAC channel1 Mask/Amplitude selector) */ |
bogdanm | 86:04dd9b1680ae | 3187 | #define DAC_CR_MAMP1_0 ((uint32_t)0x00000100) /*!< Bit 0 */ |
bogdanm | 86:04dd9b1680ae | 3188 | #define DAC_CR_MAMP1_1 ((uint32_t)0x00000200) /*!< Bit 1 */ |
bogdanm | 86:04dd9b1680ae | 3189 | #define DAC_CR_MAMP1_2 ((uint32_t)0x00000400) /*!< Bit 2 */ |
bogdanm | 86:04dd9b1680ae | 3190 | #define DAC_CR_MAMP1_3 ((uint32_t)0x00000800) /*!< Bit 3 */ |
bogdanm | 86:04dd9b1680ae | 3191 | |
bogdanm | 86:04dd9b1680ae | 3192 | #define DAC_CR_DMAEN1 ((uint32_t)0x00001000) /*!< DAC channel1 DMA enable */ |
bogdanm | 86:04dd9b1680ae | 3193 | #define DAC_CR_DMAUDRIE1 ((uint32_t)0x00002000) /*!< DAC channel1 DMA underrun IT enable */ |
bogdanm | 86:04dd9b1680ae | 3194 | #define DAC_CR_EN2 ((uint32_t)0x00010000) /*!< DAC channel2 enable */ |
bogdanm | 86:04dd9b1680ae | 3195 | #define DAC_CR_BOFF2 ((uint32_t)0x00020000) /*!< DAC channel2 output buffer disable */ |
bogdanm | 86:04dd9b1680ae | 3196 | #define DAC_CR_TEN2 ((uint32_t)0x00040000) /*!< DAC channel2 Trigger enable */ |
bogdanm | 86:04dd9b1680ae | 3197 | |
bogdanm | 86:04dd9b1680ae | 3198 | #define DAC_CR_TSEL2 ((uint32_t)0x00380000) /*!< TSEL2[2:0] (DAC channel2 Trigger selection) */ |
bogdanm | 86:04dd9b1680ae | 3199 | #define DAC_CR_TSEL2_0 ((uint32_t)0x00080000) /*!< Bit 0 */ |
bogdanm | 86:04dd9b1680ae | 3200 | #define DAC_CR_TSEL2_1 ((uint32_t)0x00100000) /*!< Bit 1 */ |
bogdanm | 86:04dd9b1680ae | 3201 | #define DAC_CR_TSEL2_2 ((uint32_t)0x00200000) /*!< Bit 2 */ |
bogdanm | 86:04dd9b1680ae | 3202 | |
bogdanm | 86:04dd9b1680ae | 3203 | #define DAC_CR_WAVE2 ((uint32_t)0x00C00000) /*!< WAVE2[1:0] (DAC channel2 noise/triangle wave generation enable) */ |
bogdanm | 86:04dd9b1680ae | 3204 | #define DAC_CR_WAVE2_0 ((uint32_t)0x00400000) /*!< Bit 0 */ |
bogdanm | 86:04dd9b1680ae | 3205 | #define DAC_CR_WAVE2_1 ((uint32_t)0x00800000) /*!< Bit 1 */ |
bogdanm | 86:04dd9b1680ae | 3206 | |
bogdanm | 86:04dd9b1680ae | 3207 | #define DAC_CR_MAMP2 ((uint32_t)0x0F000000) /*!< MAMP2[3:0] (DAC channel2 Mask/Amplitude selector) */ |
bogdanm | 86:04dd9b1680ae | 3208 | #define DAC_CR_MAMP2_0 ((uint32_t)0x01000000) /*!< Bit 0 */ |
bogdanm | 86:04dd9b1680ae | 3209 | #define DAC_CR_MAMP2_1 ((uint32_t)0x02000000) /*!< Bit 1 */ |
bogdanm | 86:04dd9b1680ae | 3210 | #define DAC_CR_MAMP2_2 ((uint32_t)0x04000000) /*!< Bit 2 */ |
bogdanm | 86:04dd9b1680ae | 3211 | #define DAC_CR_MAMP2_3 ((uint32_t)0x08000000) /*!< Bit 3 */ |
bogdanm | 86:04dd9b1680ae | 3212 | |
bogdanm | 86:04dd9b1680ae | 3213 | #define DAC_CR_DMAEN2 ((uint32_t)0x10000000) /*!< DAC channel2 DMA enabled */ |
bogdanm | 86:04dd9b1680ae | 3214 | #define DAC_CR_DMAUDRIE2 ((uint32_t)0x20000000) /*!< DAC channel2 DMA underrun IT enable */ |
bogdanm | 86:04dd9b1680ae | 3215 | |
bogdanm | 86:04dd9b1680ae | 3216 | /***************** Bit definition for DAC_SWTRIGR register ******************/ |
bogdanm | 86:04dd9b1680ae | 3217 | #define DAC_SWTRIGR_SWTRIG1 ((uint32_t)0x00000001) /*!< DAC channel1 software trigger */ |
bogdanm | 86:04dd9b1680ae | 3218 | #define DAC_SWTRIGR_SWTRIG2 ((uint32_t)0x00000002) /*!< DAC channel2 software trigger */ |
bogdanm | 86:04dd9b1680ae | 3219 | |
bogdanm | 86:04dd9b1680ae | 3220 | /***************** Bit definition for DAC_DHR12R1 register ******************/ |
bogdanm | 86:04dd9b1680ae | 3221 | #define DAC_DHR12R1_DACC1DHR ((uint32_t)0x00000FFF) /*!< DAC channel1 12-bit Right aligned data */ |
bogdanm | 86:04dd9b1680ae | 3222 | |
bogdanm | 86:04dd9b1680ae | 3223 | /***************** Bit definition for DAC_DHR12L1 register ******************/ |
bogdanm | 86:04dd9b1680ae | 3224 | #define DAC_DHR12L1_DACC1DHR ((uint32_t)0x0000FFF0) /*!< DAC channel1 12-bit Left aligned data */ |
bogdanm | 86:04dd9b1680ae | 3225 | |
bogdanm | 86:04dd9b1680ae | 3226 | /****************** Bit definition for DAC_DHR8R1 register ******************/ |
bogdanm | 86:04dd9b1680ae | 3227 | #define DAC_DHR8R1_DACC1DHR ((uint32_t)0x000000FF) /*!< DAC channel1 8-bit Right aligned data */ |
bogdanm | 86:04dd9b1680ae | 3228 | |
bogdanm | 86:04dd9b1680ae | 3229 | /***************** Bit definition for DAC_DHR12R2 register ******************/ |
bogdanm | 86:04dd9b1680ae | 3230 | #define DAC_DHR12R2_DACC2DHR ((uint32_t)0x00000FFF) /*!< DAC channel2 12-bit Right aligned data */ |
bogdanm | 86:04dd9b1680ae | 3231 | |
bogdanm | 86:04dd9b1680ae | 3232 | /***************** Bit definition for DAC_DHR12L2 register ******************/ |
bogdanm | 86:04dd9b1680ae | 3233 | #define DAC_DHR12L2_DACC2DHR ((uint32_t)0x0000FFF0) /*!< DAC channel2 12-bit Left aligned data */ |
bogdanm | 86:04dd9b1680ae | 3234 | |
bogdanm | 86:04dd9b1680ae | 3235 | /****************** Bit definition for DAC_DHR8R2 register ******************/ |
bogdanm | 86:04dd9b1680ae | 3236 | #define DAC_DHR8R2_DACC2DHR ((uint32_t)0x000000FF) /*!< DAC channel2 8-bit Right aligned data */ |
bogdanm | 86:04dd9b1680ae | 3237 | |
bogdanm | 86:04dd9b1680ae | 3238 | /***************** Bit definition for DAC_DHR12RD register ******************/ |
bogdanm | 86:04dd9b1680ae | 3239 | #define DAC_DHR12RD_DACC1DHR ((uint32_t)0x00000FFF) /*!< DAC channel1 12-bit Right aligned data */ |
bogdanm | 86:04dd9b1680ae | 3240 | #define DAC_DHR12RD_DACC2DHR ((uint32_t)0x0FFF0000) /*!< DAC channel2 12-bit Right aligned data */ |
bogdanm | 86:04dd9b1680ae | 3241 | |
bogdanm | 86:04dd9b1680ae | 3242 | /***************** Bit definition for DAC_DHR12LD register ******************/ |
bogdanm | 86:04dd9b1680ae | 3243 | #define DAC_DHR12LD_DACC1DHR ((uint32_t)0x0000FFF0) /*!< DAC channel1 12-bit Left aligned data */ |
bogdanm | 86:04dd9b1680ae | 3244 | #define DAC_DHR12LD_DACC2DHR ((uint32_t)0xFFF00000) /*!< DAC channel2 12-bit Left aligned data */ |
bogdanm | 86:04dd9b1680ae | 3245 | |
bogdanm | 86:04dd9b1680ae | 3246 | /****************** Bit definition for DAC_DHR8RD register ******************/ |
bogdanm | 86:04dd9b1680ae | 3247 | #define DAC_DHR8RD_DACC1DHR ((uint32_t)0x000000FF) /*!< DAC channel1 8-bit Right aligned data */ |
bogdanm | 86:04dd9b1680ae | 3248 | #define DAC_DHR8RD_DACC2DHR ((uint32_t)0x0000FF00) /*!< DAC channel2 8-bit Right aligned data */ |
bogdanm | 86:04dd9b1680ae | 3249 | |
bogdanm | 86:04dd9b1680ae | 3250 | /******************* Bit definition for DAC_DOR1 register *******************/ |
bogdanm | 86:04dd9b1680ae | 3251 | #define DAC_DOR1_DACC1DOR ((uint32_t)0x00000FFF) /*!< DAC channel1 data output */ |
bogdanm | 86:04dd9b1680ae | 3252 | |
bogdanm | 86:04dd9b1680ae | 3253 | /******************* Bit definition for DAC_DOR2 register *******************/ |
bogdanm | 86:04dd9b1680ae | 3254 | #define DAC_DOR2_DACC2DOR ((uint32_t)0x00000FFF) /*!< DAC channel2 data output */ |
bogdanm | 86:04dd9b1680ae | 3255 | |
bogdanm | 86:04dd9b1680ae | 3256 | /******************** Bit definition for DAC_SR register ********************/ |
bogdanm | 86:04dd9b1680ae | 3257 | #define DAC_SR_DMAUDR1 ((uint32_t)0x00002000) /*!< DAC channel1 DMA underrun flag */ |
bogdanm | 86:04dd9b1680ae | 3258 | #define DAC_SR_DMAUDR2 ((uint32_t)0x20000000) /*!< DAC channel2 DMA underrun flag */ |
bogdanm | 86:04dd9b1680ae | 3259 | |
bogdanm | 86:04dd9b1680ae | 3260 | /******************************************************************************/ |
bogdanm | 86:04dd9b1680ae | 3261 | /* */ |
bogdanm | 86:04dd9b1680ae | 3262 | /* Debug MCU (DBGMCU) */ |
bogdanm | 86:04dd9b1680ae | 3263 | /* */ |
bogdanm | 86:04dd9b1680ae | 3264 | /******************************************************************************/ |
bogdanm | 86:04dd9b1680ae | 3265 | /******************** Bit definition for DBGMCU_IDCODE register *************/ |
bogdanm | 86:04dd9b1680ae | 3266 | #define DBGMCU_IDCODE_DEV_ID ((uint32_t)0x00000FFF) |
bogdanm | 86:04dd9b1680ae | 3267 | #define DBGMCU_IDCODE_REV_ID ((uint32_t)0xFFFF0000) |
bogdanm | 86:04dd9b1680ae | 3268 | |
bogdanm | 86:04dd9b1680ae | 3269 | /******************** Bit definition for DBGMCU_CR register *****************/ |
bogdanm | 86:04dd9b1680ae | 3270 | #define DBGMCU_CR_DBG_SLEEP ((uint32_t)0x00000001) |
bogdanm | 86:04dd9b1680ae | 3271 | #define DBGMCU_CR_DBG_STOP ((uint32_t)0x00000002) |
bogdanm | 86:04dd9b1680ae | 3272 | #define DBGMCU_CR_DBG_STANDBY ((uint32_t)0x00000004) |
bogdanm | 86:04dd9b1680ae | 3273 | #define DBGMCU_CR_TRACE_IOEN ((uint32_t)0x00000020) |
bogdanm | 86:04dd9b1680ae | 3274 | |
bogdanm | 86:04dd9b1680ae | 3275 | #define DBGMCU_CR_TRACE_MODE ((uint32_t)0x000000C0) |
bogdanm | 86:04dd9b1680ae | 3276 | #define DBGMCU_CR_TRACE_MODE_0 ((uint32_t)0x00000040)/*!<Bit 0 */ |
bogdanm | 86:04dd9b1680ae | 3277 | #define DBGMCU_CR_TRACE_MODE_1 ((uint32_t)0x00000080)/*!<Bit 1 */ |
bogdanm | 86:04dd9b1680ae | 3278 | |
bogdanm | 86:04dd9b1680ae | 3279 | /******************** Bit definition for DBGMCU_APB1_FZ register ************/ |
bogdanm | 86:04dd9b1680ae | 3280 | #define DBGMCU_APB1_FZ_DBG_TIM2_STOP ((uint32_t)0x00000001) |
bogdanm | 86:04dd9b1680ae | 3281 | #define DBGMCU_APB1_FZ_DBG_TIM3_STOP ((uint32_t)0x00000002) |
bogdanm | 86:04dd9b1680ae | 3282 | #define DBGMCU_APB1_FZ_DBG_TIM6_STOP ((uint32_t)0x00000010) |
bogdanm | 86:04dd9b1680ae | 3283 | #define DBGMCU_APB1_FZ_DBG_TIM7_STOP ((uint32_t)0x00000020) |
bogdanm | 86:04dd9b1680ae | 3284 | #define DBGMCU_APB1_FZ_DBG_RTC_STOP ((uint32_t)0x00000400) |
bogdanm | 86:04dd9b1680ae | 3285 | #define DBGMCU_APB1_FZ_DBG_WWDG_STOP ((uint32_t)0x00000800) |
bogdanm | 86:04dd9b1680ae | 3286 | #define DBGMCU_APB1_FZ_DBG_IWDG_STOP ((uint32_t)0x00001000) |
bogdanm | 86:04dd9b1680ae | 3287 | #define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT ((uint32_t)0x00200000) |
bogdanm | 86:04dd9b1680ae | 3288 | #define DBGMCU_APB1_FZ_DBG_CAN_STOP ((uint32_t)0x02000000) |
bogdanm | 86:04dd9b1680ae | 3289 | |
bogdanm | 86:04dd9b1680ae | 3290 | /******************** Bit definition for DBGMCU_APB2_FZ register ************/ |
bogdanm | 86:04dd9b1680ae | 3291 | #define DBGMCU_APB2_FZ_DBG_TIM1_STOP ((uint32_t)0x00000001) |
bogdanm | 86:04dd9b1680ae | 3292 | #define DBGMCU_APB2_FZ_DBG_TIM15_STOP ((uint32_t)0x00000004) |
bogdanm | 86:04dd9b1680ae | 3293 | #define DBGMCU_APB2_FZ_DBG_TIM16_STOP ((uint32_t)0x00000008) |
bogdanm | 86:04dd9b1680ae | 3294 | #define DBGMCU_APB2_FZ_DBG_TIM17_STOP ((uint32_t)0x00000010) |
bogdanm | 86:04dd9b1680ae | 3295 | #define DBGMCU_APB2_FZ_DBG_HRTIM1_STOP ((uint32_t)0x00000100) |
bogdanm | 86:04dd9b1680ae | 3296 | |
bogdanm | 86:04dd9b1680ae | 3297 | /******************************************************************************/ |
bogdanm | 86:04dd9b1680ae | 3298 | /* */ |
bogdanm | 86:04dd9b1680ae | 3299 | /* DMA Controller (DMA) */ |
bogdanm | 86:04dd9b1680ae | 3300 | /* */ |
bogdanm | 86:04dd9b1680ae | 3301 | /******************************************************************************/ |
bogdanm | 86:04dd9b1680ae | 3302 | /******************* Bit definition for DMA_ISR register ********************/ |
bogdanm | 86:04dd9b1680ae | 3303 | #define DMA_ISR_GIF1 ((uint32_t)0x00000001) /*!< Channel 1 Global interrupt flag */ |
bogdanm | 86:04dd9b1680ae | 3304 | #define DMA_ISR_TCIF1 ((uint32_t)0x00000002) /*!< Channel 1 Transfer Complete flag */ |
bogdanm | 86:04dd9b1680ae | 3305 | #define DMA_ISR_HTIF1 ((uint32_t)0x00000004) /*!< Channel 1 Half Transfer flag */ |
bogdanm | 86:04dd9b1680ae | 3306 | #define DMA_ISR_TEIF1 ((uint32_t)0x00000008) /*!< Channel 1 Transfer Error flag */ |
bogdanm | 86:04dd9b1680ae | 3307 | #define DMA_ISR_GIF2 ((uint32_t)0x00000010) /*!< Channel 2 Global interrupt flag */ |
bogdanm | 86:04dd9b1680ae | 3308 | #define DMA_ISR_TCIF2 ((uint32_t)0x00000020) /*!< Channel 2 Transfer Complete flag */ |
bogdanm | 86:04dd9b1680ae | 3309 | #define DMA_ISR_HTIF2 ((uint32_t)0x00000040) /*!< Channel 2 Half Transfer flag */ |
bogdanm | 86:04dd9b1680ae | 3310 | #define DMA_ISR_TEIF2 ((uint32_t)0x00000080) /*!< Channel 2 Transfer Error flag */ |
bogdanm | 86:04dd9b1680ae | 3311 | #define DMA_ISR_GIF3 ((uint32_t)0x00000100) /*!< Channel 3 Global interrupt flag */ |
bogdanm | 86:04dd9b1680ae | 3312 | #define DMA_ISR_TCIF3 ((uint32_t)0x00000200) /*!< Channel 3 Transfer Complete flag */ |
bogdanm | 86:04dd9b1680ae | 3313 | #define DMA_ISR_HTIF3 ((uint32_t)0x00000400) /*!< Channel 3 Half Transfer flag */ |
bogdanm | 86:04dd9b1680ae | 3314 | #define DMA_ISR_TEIF3 ((uint32_t)0x00000800) /*!< Channel 3 Transfer Error flag */ |
bogdanm | 86:04dd9b1680ae | 3315 | #define DMA_ISR_GIF4 ((uint32_t)0x00001000) /*!< Channel 4 Global interrupt flag */ |
bogdanm | 86:04dd9b1680ae | 3316 | #define DMA_ISR_TCIF4 ((uint32_t)0x00002000) /*!< Channel 4 Transfer Complete flag */ |
bogdanm | 86:04dd9b1680ae | 3317 | #define DMA_ISR_HTIF4 ((uint32_t)0x00004000) /*!< Channel 4 Half Transfer flag */ |
bogdanm | 86:04dd9b1680ae | 3318 | #define DMA_ISR_TEIF4 ((uint32_t)0x00008000) /*!< Channel 4 Transfer Error flag */ |
bogdanm | 86:04dd9b1680ae | 3319 | #define DMA_ISR_GIF5 ((uint32_t)0x00010000) /*!< Channel 5 Global interrupt flag */ |
bogdanm | 86:04dd9b1680ae | 3320 | #define DMA_ISR_TCIF5 ((uint32_t)0x00020000) /*!< Channel 5 Transfer Complete flag */ |
bogdanm | 86:04dd9b1680ae | 3321 | #define DMA_ISR_HTIF5 ((uint32_t)0x00040000) /*!< Channel 5 Half Transfer flag */ |
bogdanm | 86:04dd9b1680ae | 3322 | #define DMA_ISR_TEIF5 ((uint32_t)0x00080000) /*!< Channel 5 Transfer Error flag */ |
bogdanm | 86:04dd9b1680ae | 3323 | #define DMA_ISR_GIF6 ((uint32_t)0x00100000) /*!< Channel 6 Global interrupt flag */ |
bogdanm | 86:04dd9b1680ae | 3324 | #define DMA_ISR_TCIF6 ((uint32_t)0x00200000) /*!< Channel 6 Transfer Complete flag */ |
bogdanm | 86:04dd9b1680ae | 3325 | #define DMA_ISR_HTIF6 ((uint32_t)0x00400000) /*!< Channel 6 Half Transfer flag */ |
bogdanm | 86:04dd9b1680ae | 3326 | #define DMA_ISR_TEIF6 ((uint32_t)0x00800000) /*!< Channel 6 Transfer Error flag */ |
bogdanm | 86:04dd9b1680ae | 3327 | #define DMA_ISR_GIF7 ((uint32_t)0x01000000) /*!< Channel 7 Global interrupt flag */ |
bogdanm | 86:04dd9b1680ae | 3328 | #define DMA_ISR_TCIF7 ((uint32_t)0x02000000) /*!< Channel 7 Transfer Complete flag */ |
bogdanm | 86:04dd9b1680ae | 3329 | #define DMA_ISR_HTIF7 ((uint32_t)0x04000000) /*!< Channel 7 Half Transfer flag */ |
bogdanm | 86:04dd9b1680ae | 3330 | #define DMA_ISR_TEIF7 ((uint32_t)0x08000000) /*!< Channel 7 Transfer Error flag */ |
bogdanm | 86:04dd9b1680ae | 3331 | |
bogdanm | 86:04dd9b1680ae | 3332 | /******************* Bit definition for DMA_IFCR register *******************/ |
bogdanm | 86:04dd9b1680ae | 3333 | #define DMA_IFCR_CGIF1 ((uint32_t)0x00000001) /*!< Channel 1 Global interrupt clear */ |
bogdanm | 86:04dd9b1680ae | 3334 | #define DMA_IFCR_CTCIF1 ((uint32_t)0x00000002) /*!< Channel 1 Transfer Complete clear */ |
bogdanm | 86:04dd9b1680ae | 3335 | #define DMA_IFCR_CHTIF1 ((uint32_t)0x00000004) /*!< Channel 1 Half Transfer clear */ |
bogdanm | 86:04dd9b1680ae | 3336 | #define DMA_IFCR_CTEIF1 ((uint32_t)0x00000008) /*!< Channel 1 Transfer Error clear */ |
bogdanm | 86:04dd9b1680ae | 3337 | #define DMA_IFCR_CGIF2 ((uint32_t)0x00000010) /*!< Channel 2 Global interrupt clear */ |
bogdanm | 86:04dd9b1680ae | 3338 | #define DMA_IFCR_CTCIF2 ((uint32_t)0x00000020) /*!< Channel 2 Transfer Complete clear */ |
bogdanm | 86:04dd9b1680ae | 3339 | #define DMA_IFCR_CHTIF2 ((uint32_t)0x00000040) /*!< Channel 2 Half Transfer clear */ |
bogdanm | 86:04dd9b1680ae | 3340 | #define DMA_IFCR_CTEIF2 ((uint32_t)0x00000080) /*!< Channel 2 Transfer Error clear */ |
bogdanm | 86:04dd9b1680ae | 3341 | #define DMA_IFCR_CGIF3 ((uint32_t)0x00000100) /*!< Channel 3 Global interrupt clear */ |
bogdanm | 86:04dd9b1680ae | 3342 | #define DMA_IFCR_CTCIF3 ((uint32_t)0x00000200) /*!< Channel 3 Transfer Complete clear */ |
bogdanm | 86:04dd9b1680ae | 3343 | #define DMA_IFCR_CHTIF3 ((uint32_t)0x00000400) /*!< Channel 3 Half Transfer clear */ |
bogdanm | 86:04dd9b1680ae | 3344 | #define DMA_IFCR_CTEIF3 ((uint32_t)0x00000800) /*!< Channel 3 Transfer Error clear */ |
bogdanm | 86:04dd9b1680ae | 3345 | #define DMA_IFCR_CGIF4 ((uint32_t)0x00001000) /*!< Channel 4 Global interrupt clear */ |
bogdanm | 86:04dd9b1680ae | 3346 | #define DMA_IFCR_CTCIF4 ((uint32_t)0x00002000) /*!< Channel 4 Transfer Complete clear */ |
bogdanm | 86:04dd9b1680ae | 3347 | #define DMA_IFCR_CHTIF4 ((uint32_t)0x00004000) /*!< Channel 4 Half Transfer clear */ |
bogdanm | 86:04dd9b1680ae | 3348 | #define DMA_IFCR_CTEIF4 ((uint32_t)0x00008000) /*!< Channel 4 Transfer Error clear */ |
bogdanm | 86:04dd9b1680ae | 3349 | #define DMA_IFCR_CGIF5 ((uint32_t)0x00010000) /*!< Channel 5 Global interrupt clear */ |
bogdanm | 86:04dd9b1680ae | 3350 | #define DMA_IFCR_CTCIF5 ((uint32_t)0x00020000) /*!< Channel 5 Transfer Complete clear */ |
bogdanm | 86:04dd9b1680ae | 3351 | #define DMA_IFCR_CHTIF5 ((uint32_t)0x00040000) /*!< Channel 5 Half Transfer clear */ |
bogdanm | 86:04dd9b1680ae | 3352 | #define DMA_IFCR_CTEIF5 ((uint32_t)0x00080000) /*!< Channel 5 Transfer Error clear */ |
bogdanm | 86:04dd9b1680ae | 3353 | #define DMA_IFCR_CGIF6 ((uint32_t)0x00100000) /*!< Channel 6 Global interrupt clear */ |
bogdanm | 86:04dd9b1680ae | 3354 | #define DMA_IFCR_CTCIF6 ((uint32_t)0x00200000) /*!< Channel 6 Transfer Complete clear */ |
bogdanm | 86:04dd9b1680ae | 3355 | #define DMA_IFCR_CHTIF6 ((uint32_t)0x00400000) /*!< Channel 6 Half Transfer clear */ |
bogdanm | 86:04dd9b1680ae | 3356 | #define DMA_IFCR_CTEIF6 ((uint32_t)0x00800000) /*!< Channel 6 Transfer Error clear */ |
bogdanm | 86:04dd9b1680ae | 3357 | #define DMA_IFCR_CGIF7 ((uint32_t)0x01000000) /*!< Channel 7 Global interrupt clear */ |
bogdanm | 86:04dd9b1680ae | 3358 | #define DMA_IFCR_CTCIF7 ((uint32_t)0x02000000) /*!< Channel 7 Transfer Complete clear */ |
bogdanm | 86:04dd9b1680ae | 3359 | #define DMA_IFCR_CHTIF7 ((uint32_t)0x04000000) /*!< Channel 7 Half Transfer clear */ |
bogdanm | 86:04dd9b1680ae | 3360 | #define DMA_IFCR_CTEIF7 ((uint32_t)0x08000000) /*!< Channel 7 Transfer Error clear */ |
bogdanm | 86:04dd9b1680ae | 3361 | |
bogdanm | 86:04dd9b1680ae | 3362 | /******************* Bit definition for DMA_CCR register ********************/ |
bogdanm | 86:04dd9b1680ae | 3363 | #define DMA_CCR_EN ((uint32_t)0x00000001) /*!< Channel enable */ |
bogdanm | 86:04dd9b1680ae | 3364 | #define DMA_CCR_TCIE ((uint32_t)0x00000002) /*!< Transfer complete interrupt enable */ |
bogdanm | 86:04dd9b1680ae | 3365 | #define DMA_CCR_HTIE ((uint32_t)0x00000004) /*!< Half Transfer interrupt enable */ |
bogdanm | 86:04dd9b1680ae | 3366 | #define DMA_CCR_TEIE ((uint32_t)0x00000008) /*!< Transfer error interrupt enable */ |
bogdanm | 86:04dd9b1680ae | 3367 | #define DMA_CCR_DIR ((uint32_t)0x00000010) /*!< Data transfer direction */ |
bogdanm | 86:04dd9b1680ae | 3368 | #define DMA_CCR_CIRC ((uint32_t)0x00000020) /*!< Circular mode */ |
bogdanm | 86:04dd9b1680ae | 3369 | #define DMA_CCR_PINC ((uint32_t)0x00000040) /*!< Peripheral increment mode */ |
bogdanm | 86:04dd9b1680ae | 3370 | #define DMA_CCR_MINC ((uint32_t)0x00000080) /*!< Memory increment mode */ |
bogdanm | 86:04dd9b1680ae | 3371 | |
bogdanm | 86:04dd9b1680ae | 3372 | #define DMA_CCR_PSIZE ((uint32_t)0x00000300) /*!< PSIZE[1:0] bits (Peripheral size) */ |
bogdanm | 86:04dd9b1680ae | 3373 | #define DMA_CCR_PSIZE_0 ((uint32_t)0x00000100) /*!< Bit 0 */ |
bogdanm | 86:04dd9b1680ae | 3374 | #define DMA_CCR_PSIZE_1 ((uint32_t)0x00000200) /*!< Bit 1 */ |
bogdanm | 86:04dd9b1680ae | 3375 | |
bogdanm | 86:04dd9b1680ae | 3376 | #define DMA_CCR_MSIZE ((uint32_t)0x00000C00) /*!< MSIZE[1:0] bits (Memory size) */ |
bogdanm | 86:04dd9b1680ae | 3377 | #define DMA_CCR_MSIZE_0 ((uint32_t)0x00000400) /*!< Bit 0 */ |
bogdanm | 86:04dd9b1680ae | 3378 | #define DMA_CCR_MSIZE_1 ((uint32_t)0x00000800) /*!< Bit 1 */ |
bogdanm | 86:04dd9b1680ae | 3379 | |
bogdanm | 86:04dd9b1680ae | 3380 | #define DMA_CCR_PL ((uint32_t)0x00003000) /*!< PL[1:0] bits(Channel Priority level)*/ |
bogdanm | 86:04dd9b1680ae | 3381 | #define DMA_CCR_PL_0 ((uint32_t)0x00001000) /*!< Bit 0 */ |
bogdanm | 86:04dd9b1680ae | 3382 | #define DMA_CCR_PL_1 ((uint32_t)0x00002000) /*!< Bit 1 */ |
bogdanm | 86:04dd9b1680ae | 3383 | |
bogdanm | 86:04dd9b1680ae | 3384 | #define DMA_CCR_MEM2MEM ((uint32_t)0x00004000) /*!< Memory to memory mode */ |
bogdanm | 86:04dd9b1680ae | 3385 | |
bogdanm | 86:04dd9b1680ae | 3386 | /****************** Bit definition for DMA_CNDTR register *******************/ |
bogdanm | 86:04dd9b1680ae | 3387 | #define DMA_CNDTR_NDT ((uint32_t)0x0000FFFF) /*!< Number of data to Transfer */ |
bogdanm | 86:04dd9b1680ae | 3388 | |
bogdanm | 86:04dd9b1680ae | 3389 | /****************** Bit definition for DMA_CPAR register ********************/ |
bogdanm | 86:04dd9b1680ae | 3390 | #define DMA_CPAR_PA ((uint32_t)0xFFFFFFFF) /*!< Peripheral Address */ |
bogdanm | 86:04dd9b1680ae | 3391 | |
bogdanm | 86:04dd9b1680ae | 3392 | /****************** Bit definition for DMA_CMAR register ********************/ |
bogdanm | 86:04dd9b1680ae | 3393 | #define DMA_CMAR_MA ((uint32_t)0xFFFFFFFF) /*!< Memory Address */ |
bogdanm | 86:04dd9b1680ae | 3394 | |
bogdanm | 86:04dd9b1680ae | 3395 | /******************************************************************************/ |
bogdanm | 86:04dd9b1680ae | 3396 | /* */ |
bogdanm | 86:04dd9b1680ae | 3397 | /* External Interrupt/Event Controller (EXTI) */ |
bogdanm | 86:04dd9b1680ae | 3398 | /* */ |
bogdanm | 86:04dd9b1680ae | 3399 | /******************************************************************************/ |
bogdanm | 86:04dd9b1680ae | 3400 | /******************* Bit definition for EXTI_IMR1/EXTI_IMR2 register ********/ |
bogdanm | 86:04dd9b1680ae | 3401 | #define EXTI_IMR_MR0 ((uint32_t)0x00000001) /*!< Interrupt Mask on line 0 */ |
bogdanm | 86:04dd9b1680ae | 3402 | #define EXTI_IMR_MR1 ((uint32_t)0x00000002) /*!< Interrupt Mask on line 1 */ |
bogdanm | 86:04dd9b1680ae | 3403 | #define EXTI_IMR_MR2 ((uint32_t)0x00000004) /*!< Interrupt Mask on line 2 */ |
bogdanm | 86:04dd9b1680ae | 3404 | #define EXTI_IMR_MR3 ((uint32_t)0x00000008) /*!< Interrupt Mask on line 3 */ |
bogdanm | 86:04dd9b1680ae | 3405 | #define EXTI_IMR_MR4 ((uint32_t)0x00000010) /*!< Interrupt Mask on line 4 */ |
bogdanm | 86:04dd9b1680ae | 3406 | #define EXTI_IMR_MR5 ((uint32_t)0x00000020) /*!< Interrupt Mask on line 5 */ |
bogdanm | 86:04dd9b1680ae | 3407 | #define EXTI_IMR_MR6 ((uint32_t)0x00000040) /*!< Interrupt Mask on line 6 */ |
bogdanm | 86:04dd9b1680ae | 3408 | #define EXTI_IMR_MR7 ((uint32_t)0x00000080) /*!< Interrupt Mask on line 7 */ |
bogdanm | 86:04dd9b1680ae | 3409 | #define EXTI_IMR_MR8 ((uint32_t)0x00000100) /*!< Interrupt Mask on line 8 */ |
bogdanm | 86:04dd9b1680ae | 3410 | #define EXTI_IMR_MR9 ((uint32_t)0x00000200) /*!< Interrupt Mask on line 9 */ |
bogdanm | 86:04dd9b1680ae | 3411 | #define EXTI_IMR_MR10 ((uint32_t)0x00000400) /*!< Interrupt Mask on line 10 */ |
bogdanm | 86:04dd9b1680ae | 3412 | #define EXTI_IMR_MR11 ((uint32_t)0x00000800) /*!< Interrupt Mask on line 11 */ |
bogdanm | 86:04dd9b1680ae | 3413 | #define EXTI_IMR_MR12 ((uint32_t)0x00001000) /*!< Interrupt Mask on line 12 */ |
bogdanm | 86:04dd9b1680ae | 3414 | #define EXTI_IMR_MR13 ((uint32_t)0x00002000) /*!< Interrupt Mask on line 13 */ |
bogdanm | 86:04dd9b1680ae | 3415 | #define EXTI_IMR_MR14 ((uint32_t)0x00004000) /*!< Interrupt Mask on line 14 */ |
bogdanm | 86:04dd9b1680ae | 3416 | #define EXTI_IMR_MR15 ((uint32_t)0x00008000) /*!< Interrupt Mask on line 15 */ |
bogdanm | 86:04dd9b1680ae | 3417 | #define EXTI_IMR_MR16 ((uint32_t)0x00010000) /*!< Interrupt Mask on line 16 */ |
bogdanm | 86:04dd9b1680ae | 3418 | #define EXTI_IMR_MR17 ((uint32_t)0x00020000) /*!< Interrupt Mask on line 17 */ |
bogdanm | 86:04dd9b1680ae | 3419 | #define EXTI_IMR_MR18 ((uint32_t)0x00040000) /*!< Interrupt Mask on line 18 */ |
bogdanm | 86:04dd9b1680ae | 3420 | #define EXTI_IMR_MR19 ((uint32_t)0x00080000) /*!< Interrupt Mask on line 19 */ |
bogdanm | 86:04dd9b1680ae | 3421 | #define EXTI_IMR_MR20 ((uint32_t)0x00100000) /*!< Interrupt Mask on line 20 */ |
bogdanm | 86:04dd9b1680ae | 3422 | #define EXTI_IMR_MR21 ((uint32_t)0x00200000) /*!< Interrupt Mask on line 21 */ |
bogdanm | 86:04dd9b1680ae | 3423 | #define EXTI_IMR_MR22 ((uint32_t)0x00400000) /*!< Interrupt Mask on line 22 */ |
bogdanm | 86:04dd9b1680ae | 3424 | #define EXTI_IMR_MR23 ((uint32_t)0x00800000) /*!< Interrupt Mask on line 23 */ |
bogdanm | 86:04dd9b1680ae | 3425 | #define EXTI_IMR_MR24 ((uint32_t)0x01000000) /*!< Interrupt Mask on line 24 */ |
bogdanm | 86:04dd9b1680ae | 3426 | #define EXTI_IMR_MR25 ((uint32_t)0x02000000) /*!< Interrupt Mask on line 25 */ |
bogdanm | 86:04dd9b1680ae | 3427 | #define EXTI_IMR_MR26 ((uint32_t)0x04000000) /*!< Interrupt Mask on line 26 */ |
bogdanm | 86:04dd9b1680ae | 3428 | #define EXTI_IMR_MR27 ((uint32_t)0x08000000) /*!< Interrupt Mask on line 27 */ |
bogdanm | 86:04dd9b1680ae | 3429 | #define EXTI_IMR_MR28 ((uint32_t)0x10000000) /*!< Interrupt Mask on line 28 */ |
bogdanm | 86:04dd9b1680ae | 3430 | |
bogdanm | 86:04dd9b1680ae | 3431 | /******************* Bit definition for EXTI_EMR1/EXTI_EMR2 register ********/ |
bogdanm | 86:04dd9b1680ae | 3432 | #define EXTI_EMR_MR0 ((uint32_t)0x00000001) /*!< Event Mask on line 0 */ |
bogdanm | 86:04dd9b1680ae | 3433 | #define EXTI_EMR_MR1 ((uint32_t)0x00000002) /*!< Event Mask on line 1 */ |
bogdanm | 86:04dd9b1680ae | 3434 | #define EXTI_EMR_MR2 ((uint32_t)0x00000004) /*!< Event Mask on line 2 */ |
bogdanm | 86:04dd9b1680ae | 3435 | #define EXTI_EMR_MR3 ((uint32_t)0x00000008) /*!< Event Mask on line 3 */ |
bogdanm | 86:04dd9b1680ae | 3436 | #define EXTI_EMR_MR4 ((uint32_t)0x00000010) /*!< Event Mask on line 4 */ |
bogdanm | 86:04dd9b1680ae | 3437 | #define EXTI_EMR_MR5 ((uint32_t)0x00000020) /*!< Event Mask on line 5 */ |
bogdanm | 86:04dd9b1680ae | 3438 | #define EXTI_EMR_MR6 ((uint32_t)0x00000040) /*!< Event Mask on line 6 */ |
bogdanm | 86:04dd9b1680ae | 3439 | #define EXTI_EMR_MR7 ((uint32_t)0x00000080) /*!< Event Mask on line 7 */ |
bogdanm | 86:04dd9b1680ae | 3440 | #define EXTI_EMR_MR8 ((uint32_t)0x00000100) /*!< Event Mask on line 8 */ |
bogdanm | 86:04dd9b1680ae | 3441 | #define EXTI_EMR_MR9 ((uint32_t)0x00000200) /*!< Event Mask on line 9 */ |
bogdanm | 86:04dd9b1680ae | 3442 | #define EXTI_EMR_MR10 ((uint32_t)0x00000400) /*!< Event Mask on line 10 */ |
bogdanm | 86:04dd9b1680ae | 3443 | #define EXTI_EMR_MR11 ((uint32_t)0x00000800) /*!< Event Mask on line 11 */ |
bogdanm | 86:04dd9b1680ae | 3444 | #define EXTI_EMR_MR12 ((uint32_t)0x00001000) /*!< Event Mask on line 12 */ |
bogdanm | 86:04dd9b1680ae | 3445 | #define EXTI_EMR_MR13 ((uint32_t)0x00002000) /*!< Event Mask on line 13 */ |
bogdanm | 86:04dd9b1680ae | 3446 | #define EXTI_EMR_MR14 ((uint32_t)0x00004000) /*!< Event Mask on line 14 */ |
bogdanm | 86:04dd9b1680ae | 3447 | #define EXTI_EMR_MR15 ((uint32_t)0x00008000) /*!< Event Mask on line 15 */ |
bogdanm | 86:04dd9b1680ae | 3448 | #define EXTI_EMR_MR16 ((uint32_t)0x00010000) /*!< Event Mask on line 16 */ |
bogdanm | 86:04dd9b1680ae | 3449 | #define EXTI_EMR_MR17 ((uint32_t)0x00020000) /*!< Event Mask on line 17 */ |
bogdanm | 86:04dd9b1680ae | 3450 | #define EXTI_EMR_MR18 ((uint32_t)0x00040000) /*!< Event Mask on line 18 */ |
bogdanm | 86:04dd9b1680ae | 3451 | #define EXTI_EMR_MR19 ((uint32_t)0x00080000) /*!< Event Mask on line 19 */ |
bogdanm | 86:04dd9b1680ae | 3452 | #define EXTI_EMR_MR20 ((uint32_t)0x00100000) /*!< Event Mask on line 20 */ |
bogdanm | 86:04dd9b1680ae | 3453 | #define EXTI_EMR_MR21 ((uint32_t)0x00200000) /*!< Event Mask on line 21 */ |
bogdanm | 86:04dd9b1680ae | 3454 | #define EXTI_EMR_MR22 ((uint32_t)0x00400000) /*!< Event Mask on line 22 */ |
bogdanm | 86:04dd9b1680ae | 3455 | #define EXTI_EMR_MR23 ((uint32_t)0x00800000) /*!< Event Mask on line 23 */ |
bogdanm | 86:04dd9b1680ae | 3456 | #define EXTI_EMR_MR24 ((uint32_t)0x01000000) /*!< Event Mask on line 24 */ |
bogdanm | 86:04dd9b1680ae | 3457 | #define EXTI_EMR_MR25 ((uint32_t)0x02000000) /*!< Event Mask on line 25 */ |
bogdanm | 86:04dd9b1680ae | 3458 | #define EXTI_EMR_MR26 ((uint32_t)0x04000000) /*!< Event Mask on line 26 */ |
bogdanm | 86:04dd9b1680ae | 3459 | #define EXTI_EMR_MR27 ((uint32_t)0x08000000) /*!< Event Mask on line 27 */ |
bogdanm | 86:04dd9b1680ae | 3460 | #define EXTI_EMR_MR28 ((uint32_t)0x10000000) /*!< Event Mask on line 28 */ |
bogdanm | 86:04dd9b1680ae | 3461 | |
bogdanm | 86:04dd9b1680ae | 3462 | /****************** Bit definition for EXTI_RTSR1/EXTI_RTSR2 register *******/ |
bogdanm | 86:04dd9b1680ae | 3463 | #define EXTI_RTSR_TR0 ((uint32_t)0x00000001) /*!< Rising trigger event configuration bit of line 0 */ |
bogdanm | 86:04dd9b1680ae | 3464 | #define EXTI_RTSR_TR1 ((uint32_t)0x00000002) /*!< Rising trigger event configuration bit of line 1 */ |
bogdanm | 86:04dd9b1680ae | 3465 | #define EXTI_RTSR_TR2 ((uint32_t)0x00000004) /*!< Rising trigger event configuration bit of line 2 */ |
bogdanm | 86:04dd9b1680ae | 3466 | #define EXTI_RTSR_TR3 ((uint32_t)0x00000008) /*!< Rising trigger event configuration bit of line 3 */ |
bogdanm | 86:04dd9b1680ae | 3467 | #define EXTI_RTSR_TR4 ((uint32_t)0x00000010) /*!< Rising trigger event configuration bit of line 4 */ |
bogdanm | 86:04dd9b1680ae | 3468 | #define EXTI_RTSR_TR5 ((uint32_t)0x00000020) /*!< Rising trigger event configuration bit of line 5 */ |
bogdanm | 86:04dd9b1680ae | 3469 | #define EXTI_RTSR_TR6 ((uint32_t)0x00000040) /*!< Rising trigger event configuration bit of line 6 */ |
bogdanm | 86:04dd9b1680ae | 3470 | #define EXTI_RTSR_TR7 ((uint32_t)0x00000080) /*!< Rising trigger event configuration bit of line 7 */ |
bogdanm | 86:04dd9b1680ae | 3471 | #define EXTI_RTSR_TR8 ((uint32_t)0x00000100) /*!< Rising trigger event configuration bit of line 8 */ |
bogdanm | 86:04dd9b1680ae | 3472 | #define EXTI_RTSR_TR9 ((uint32_t)0x00000200) /*!< Rising trigger event configuration bit of line 9 */ |
bogdanm | 86:04dd9b1680ae | 3473 | #define EXTI_RTSR_TR10 ((uint32_t)0x00000400) /*!< Rising trigger event configuration bit of line 10 */ |
bogdanm | 86:04dd9b1680ae | 3474 | #define EXTI_RTSR_TR11 ((uint32_t)0x00000800) /*!< Rising trigger event configuration bit of line 11 */ |
bogdanm | 86:04dd9b1680ae | 3475 | #define EXTI_RTSR_TR12 ((uint32_t)0x00001000) /*!< Rising trigger event configuration bit of line 12 */ |
bogdanm | 86:04dd9b1680ae | 3476 | #define EXTI_RTSR_TR13 ((uint32_t)0x00002000) /*!< Rising trigger event configuration bit of line 13 */ |
bogdanm | 86:04dd9b1680ae | 3477 | #define EXTI_RTSR_TR14 ((uint32_t)0x00004000) /*!< Rising trigger event configuration bit of line 14 */ |
bogdanm | 86:04dd9b1680ae | 3478 | #define EXTI_RTSR_TR15 ((uint32_t)0x00008000) /*!< Rising trigger event configuration bit of line 15 */ |
bogdanm | 86:04dd9b1680ae | 3479 | #define EXTI_RTSR_TR16 ((uint32_t)0x00010000) /*!< Rising trigger event configuration bit of line 16 */ |
bogdanm | 86:04dd9b1680ae | 3480 | #define EXTI_RTSR_TR17 ((uint32_t)0x00020000) /*!< Rising trigger event configuration bit of line 17 */ |
bogdanm | 86:04dd9b1680ae | 3481 | #define EXTI_RTSR_TR18 ((uint32_t)0x00040000) /*!< Rising trigger event configuration bit of line 18 */ |
bogdanm | 86:04dd9b1680ae | 3482 | #define EXTI_RTSR_TR19 ((uint32_t)0x00080000) /*!< Rising trigger event configuration bit of line 19 */ |
bogdanm | 86:04dd9b1680ae | 3483 | #define EXTI_RTSR_TR20 ((uint32_t)0x00100000) /*!< Rising trigger event configuration bit of line 20 */ |
bogdanm | 86:04dd9b1680ae | 3484 | #define EXTI_RTSR_TR21 ((uint32_t)0x00200000) /*!< Rising trigger event configuration bit of line 21 */ |
bogdanm | 86:04dd9b1680ae | 3485 | #define EXTI_RTSR_TR22 ((uint32_t)0x00400000) /*!< Rising trigger event configuration bit of line 22 */ |
bogdanm | 86:04dd9b1680ae | 3486 | #define EXTI_RTSR_TR23 ((uint32_t)0x00800000) /*!< Rising trigger event configuration bit of line 23 */ |
bogdanm | 86:04dd9b1680ae | 3487 | #define EXTI_RTSR_TR24 ((uint32_t)0x01000000) /*!< Rising trigger event configuration bit of line 24 */ |
bogdanm | 86:04dd9b1680ae | 3488 | #define EXTI_RTSR_TR25 ((uint32_t)0x02000000) /*!< Rising trigger event configuration bit of line 25 */ |
bogdanm | 86:04dd9b1680ae | 3489 | #define EXTI_RTSR_TR26 ((uint32_t)0x04000000) /*!< Rising trigger event configuration bit of line 26 */ |
bogdanm | 86:04dd9b1680ae | 3490 | #define EXTI_RTSR_TR27 ((uint32_t)0x08000000) /*!< Rising trigger event configuration bit of line 27 */ |
bogdanm | 86:04dd9b1680ae | 3491 | #define EXTI_RTSR_TR28 ((uint32_t)0x10000000) /*!< Rising trigger event configuration bit of line 28 */ |
bogdanm | 86:04dd9b1680ae | 3492 | |
bogdanm | 86:04dd9b1680ae | 3493 | /****************** Bit definition for EXTI_FTSR1/EXTI_FTSR2 register *******/ |
bogdanm | 86:04dd9b1680ae | 3494 | #define EXTI_FTSR_TR0 ((uint32_t)0x00000001) /*!< Falling trigger event configuration bit of line 0 */ |
bogdanm | 86:04dd9b1680ae | 3495 | #define EXTI_FTSR_TR1 ((uint32_t)0x00000002) /*!< Falling trigger event configuration bit of line 1 */ |
bogdanm | 86:04dd9b1680ae | 3496 | #define EXTI_FTSR_TR2 ((uint32_t)0x00000004) /*!< Falling trigger event configuration bit of line 2 */ |
bogdanm | 86:04dd9b1680ae | 3497 | #define EXTI_FTSR_TR3 ((uint32_t)0x00000008) /*!< Falling trigger event configuration bit of line 3 */ |
bogdanm | 86:04dd9b1680ae | 3498 | #define EXTI_FTSR_TR4 ((uint32_t)0x00000010) /*!< Falling trigger event configuration bit of line 4 */ |
bogdanm | 86:04dd9b1680ae | 3499 | #define EXTI_FTSR_TR5 ((uint32_t)0x00000020) /*!< Falling trigger event configuration bit of line 5 */ |
bogdanm | 86:04dd9b1680ae | 3500 | #define EXTI_FTSR_TR6 ((uint32_t)0x00000040) /*!< Falling trigger event configuration bit of line 6 */ |
bogdanm | 86:04dd9b1680ae | 3501 | #define EXTI_FTSR_TR7 ((uint32_t)0x00000080) /*!< Falling trigger event configuration bit of line 7 */ |
bogdanm | 86:04dd9b1680ae | 3502 | #define EXTI_FTSR_TR8 ((uint32_t)0x00000100) /*!< Falling trigger event configuration bit of line 8 */ |
bogdanm | 86:04dd9b1680ae | 3503 | #define EXTI_FTSR_TR9 ((uint32_t)0x00000200) /*!< Falling trigger event configuration bit of line 9 */ |
bogdanm | 86:04dd9b1680ae | 3504 | #define EXTI_FTSR_TR10 ((uint32_t)0x00000400) /*!< Falling trigger event configuration bit of line 10 */ |
bogdanm | 86:04dd9b1680ae | 3505 | #define EXTI_FTSR_TR11 ((uint32_t)0x00000800) /*!< Falling trigger event configuration bit of line 11 */ |
bogdanm | 86:04dd9b1680ae | 3506 | #define EXTI_FTSR_TR12 ((uint32_t)0x00001000) /*!< Falling trigger event configuration bit of line 12 */ |
bogdanm | 86:04dd9b1680ae | 3507 | #define EXTI_FTSR_TR13 ((uint32_t)0x00002000) /*!< Falling trigger event configuration bit of line 13 */ |
bogdanm | 86:04dd9b1680ae | 3508 | #define EXTI_FTSR_TR14 ((uint32_t)0x00004000) /*!< Falling trigger event configuration bit of line 14 */ |
bogdanm | 86:04dd9b1680ae | 3509 | #define EXTI_FTSR_TR15 ((uint32_t)0x00008000) /*!< Falling trigger event configuration bit of line 15 */ |
bogdanm | 86:04dd9b1680ae | 3510 | #define EXTI_FTSR_TR16 ((uint32_t)0x00010000) /*!< Falling trigger event configuration bit of line 16 */ |
bogdanm | 86:04dd9b1680ae | 3511 | #define EXTI_FTSR_TR17 ((uint32_t)0x00020000) /*!< Falling trigger event configuration bit of line 17 */ |
bogdanm | 86:04dd9b1680ae | 3512 | #define EXTI_FTSR_TR18 ((uint32_t)0x00040000) /*!< Falling trigger event configuration bit of line 18 */ |
bogdanm | 86:04dd9b1680ae | 3513 | #define EXTI_FTSR_TR19 ((uint32_t)0x00080000) /*!< Falling trigger event configuration bit of line 19 */ |
bogdanm | 86:04dd9b1680ae | 3514 | #define EXTI_FTSR_TR20 ((uint32_t)0x00100000) /*!< Falling trigger event configuration bit of line 20 */ |
bogdanm | 86:04dd9b1680ae | 3515 | #define EXTI_FTSR_TR21 ((uint32_t)0x00200000) /*!< Falling trigger event configuration bit of line 21 */ |
bogdanm | 86:04dd9b1680ae | 3516 | #define EXTI_FTSR_TR22 ((uint32_t)0x00400000) /*!< Falling trigger event configuration bit of line 22 */ |
bogdanm | 86:04dd9b1680ae | 3517 | #define EXTI_FTSR_TR23 ((uint32_t)0x00800000) /*!< Falling trigger event configuration bit of line 23 */ |
bogdanm | 86:04dd9b1680ae | 3518 | #define EXTI_FTSR_TR24 ((uint32_t)0x01000000) /*!< Falling trigger event configuration bit of line 24 */ |
bogdanm | 86:04dd9b1680ae | 3519 | #define EXTI_FTSR_TR25 ((uint32_t)0x02000000) /*!< Falling trigger event configuration bit of line 25 */ |
bogdanm | 86:04dd9b1680ae | 3520 | #define EXTI_FTSR_TR26 ((uint32_t)0x04000000) /*!< Falling trigger event configuration bit of line 26 */ |
bogdanm | 86:04dd9b1680ae | 3521 | #define EXTI_FTSR_TR27 ((uint32_t)0x08000000) /*!< Falling trigger event configuration bit of line 27 */ |
bogdanm | 86:04dd9b1680ae | 3522 | #define EXTI_FTSR_TR28 ((uint32_t)0x10000000) /*!< Falling trigger event configuration bit of line 28 */ |
bogdanm | 86:04dd9b1680ae | 3523 | |
bogdanm | 86:04dd9b1680ae | 3524 | /****************** Bit definition for EXTI_SWIER1/EXTI_SWIER2 register *****/ |
bogdanm | 86:04dd9b1680ae | 3525 | #define EXTI_SWIER_SWIER0 ((uint32_t)0x00000001) /*!< Software Interrupt on line 0 */ |
bogdanm | 86:04dd9b1680ae | 3526 | #define EXTI_SWIER_SWIER1 ((uint32_t)0x00000002) /*!< Software Interrupt on line 1 */ |
bogdanm | 86:04dd9b1680ae | 3527 | #define EXTI_SWIER_SWIER2 ((uint32_t)0x00000004) /*!< Software Interrupt on line 2 */ |
bogdanm | 86:04dd9b1680ae | 3528 | #define EXTI_SWIER_SWIER3 ((uint32_t)0x00000008) /*!< Software Interrupt on line 3 */ |
bogdanm | 86:04dd9b1680ae | 3529 | #define EXTI_SWIER_SWIER4 ((uint32_t)0x00000010) /*!< Software Interrupt on line 4 */ |
bogdanm | 86:04dd9b1680ae | 3530 | #define EXTI_SWIER_SWIER5 ((uint32_t)0x00000020) /*!< Software Interrupt on line 5 */ |
bogdanm | 86:04dd9b1680ae | 3531 | #define EXTI_SWIER_SWIER6 ((uint32_t)0x00000040) /*!< Software Interrupt on line 6 */ |
bogdanm | 86:04dd9b1680ae | 3532 | #define EXTI_SWIER_SWIER7 ((uint32_t)0x00000080) /*!< Software Interrupt on line 7 */ |
bogdanm | 86:04dd9b1680ae | 3533 | #define EXTI_SWIER_SWIER8 ((uint32_t)0x00000100) /*!< Software Interrupt on line 8 */ |
bogdanm | 86:04dd9b1680ae | 3534 | #define EXTI_SWIER_SWIER9 ((uint32_t)0x00000200) /*!< Software Interrupt on line 9 */ |
bogdanm | 86:04dd9b1680ae | 3535 | #define EXTI_SWIER_SWIER10 ((uint32_t)0x00000400) /*!< Software Interrupt on line 10 */ |
bogdanm | 86:04dd9b1680ae | 3536 | #define EXTI_SWIER_SWIER11 ((uint32_t)0x00000800) /*!< Software Interrupt on line 11 */ |
bogdanm | 86:04dd9b1680ae | 3537 | #define EXTI_SWIER_SWIER12 ((uint32_t)0x00001000) /*!< Software Interrupt on line 12 */ |
bogdanm | 86:04dd9b1680ae | 3538 | #define EXTI_SWIER_SWIER13 ((uint32_t)0x00002000) /*!< Software Interrupt on line 13 */ |
bogdanm | 86:04dd9b1680ae | 3539 | #define EXTI_SWIER_SWIER14 ((uint32_t)0x00004000) /*!< Software Interrupt on line 14 */ |
bogdanm | 86:04dd9b1680ae | 3540 | #define EXTI_SWIER_SWIER15 ((uint32_t)0x00008000) /*!< Software Interrupt on line 15 */ |
bogdanm | 86:04dd9b1680ae | 3541 | #define EXTI_SWIER_SWIER16 ((uint32_t)0x00010000) /*!< Software Interrupt on line 16 */ |
bogdanm | 86:04dd9b1680ae | 3542 | #define EXTI_SWIER_SWIER17 ((uint32_t)0x00020000) /*!< Software Interrupt on line 17 */ |
bogdanm | 86:04dd9b1680ae | 3543 | #define EXTI_SWIER_SWIER18 ((uint32_t)0x00040000) /*!< Software Interrupt on line 18 */ |
bogdanm | 86:04dd9b1680ae | 3544 | #define EXTI_SWIER_SWIER19 ((uint32_t)0x00080000) /*!< Software Interrupt on line 19 */ |
bogdanm | 86:04dd9b1680ae | 3545 | #define EXTI_SWIER_SWIER20 ((uint32_t)0x00100000) /*!< Software Interrupt on line 20 */ |
bogdanm | 86:04dd9b1680ae | 3546 | #define EXTI_SWIER_SWIER21 ((uint32_t)0x00200000) /*!< Software Interrupt on line 21 */ |
bogdanm | 86:04dd9b1680ae | 3547 | #define EXTI_SWIER_SWIER22 ((uint32_t)0x00400000) /*!< Software Interrupt on line 22 */ |
bogdanm | 86:04dd9b1680ae | 3548 | #define EXTI_SWIER_SWIER23 ((uint32_t)0x00800000) /*!< Software Interrupt on line 23 */ |
bogdanm | 86:04dd9b1680ae | 3549 | #define EXTI_SWIER_SWIER24 ((uint32_t)0x01000000) /*!< Software Interrupt on line 24 */ |
bogdanm | 86:04dd9b1680ae | 3550 | #define EXTI_SWIER_SWIER25 ((uint32_t)0x02000000) /*!< Software Interrupt on line 25 */ |
bogdanm | 86:04dd9b1680ae | 3551 | #define EXTI_SWIER_SWIER26 ((uint32_t)0x04000000) /*!< Software Interrupt on line 26 */ |
bogdanm | 86:04dd9b1680ae | 3552 | #define EXTI_SWIER_SWIER27 ((uint32_t)0x08000000) /*!< Software Interrupt on line 27 */ |
bogdanm | 86:04dd9b1680ae | 3553 | #define EXTI_SWIER_SWIER28 ((uint32_t)0x10000000) /*!< Software Interrupt on line 28 */ |
bogdanm | 86:04dd9b1680ae | 3554 | |
bogdanm | 86:04dd9b1680ae | 3555 | /******************* Bit definition for EXTI_PR1/EXTI_PR2 register **********/ |
bogdanm | 86:04dd9b1680ae | 3556 | #define EXTI_PR_PR0 ((uint32_t)0x00000001) /*!< Pending bit for line 0 */ |
bogdanm | 86:04dd9b1680ae | 3557 | #define EXTI_PR_PR1 ((uint32_t)0x00000002) /*!< Pending bit for line 1 */ |
bogdanm | 86:04dd9b1680ae | 3558 | #define EXTI_PR_PR2 ((uint32_t)0x00000004) /*!< Pending bit for line 2 */ |
bogdanm | 86:04dd9b1680ae | 3559 | #define EXTI_PR_PR3 ((uint32_t)0x00000008) /*!< Pending bit for line 3 */ |
bogdanm | 86:04dd9b1680ae | 3560 | #define EXTI_PR_PR4 ((uint32_t)0x00000010) /*!< Pending bit for line 4 */ |
bogdanm | 86:04dd9b1680ae | 3561 | #define EXTI_PR_PR5 ((uint32_t)0x00000020) /*!< Pending bit for line 5 */ |
bogdanm | 86:04dd9b1680ae | 3562 | #define EXTI_PR_PR6 ((uint32_t)0x00000040) /*!< Pending bit for line 6 */ |
bogdanm | 86:04dd9b1680ae | 3563 | #define EXTI_PR_PR7 ((uint32_t)0x00000080) /*!< Pending bit for line 7 */ |
bogdanm | 86:04dd9b1680ae | 3564 | #define EXTI_PR_PR8 ((uint32_t)0x00000100) /*!< Pending bit for line 8 */ |
bogdanm | 86:04dd9b1680ae | 3565 | #define EXTI_PR_PR9 ((uint32_t)0x00000200) /*!< Pending bit for line 9 */ |
bogdanm | 86:04dd9b1680ae | 3566 | #define EXTI_PR_PR10 ((uint32_t)0x00000400) /*!< Pending bit for line 10 */ |
bogdanm | 86:04dd9b1680ae | 3567 | #define EXTI_PR_PR11 ((uint32_t)0x00000800) /*!< Pending bit for line 11 */ |
bogdanm | 86:04dd9b1680ae | 3568 | #define EXTI_PR_PR12 ((uint32_t)0x00001000) /*!< Pending bit for line 12 */ |
bogdanm | 86:04dd9b1680ae | 3569 | #define EXTI_PR_PR13 ((uint32_t)0x00002000) /*!< Pending bit for line 13 */ |
bogdanm | 86:04dd9b1680ae | 3570 | #define EXTI_PR_PR14 ((uint32_t)0x00004000) /*!< Pending bit for line 14 */ |
bogdanm | 86:04dd9b1680ae | 3571 | #define EXTI_PR_PR15 ((uint32_t)0x00008000) /*!< Pending bit for line 15 */ |
bogdanm | 86:04dd9b1680ae | 3572 | #define EXTI_PR_PR16 ((uint32_t)0x00010000) /*!< Pending bit for line 16 */ |
bogdanm | 86:04dd9b1680ae | 3573 | #define EXTI_PR_PR17 ((uint32_t)0x00020000) /*!< Pending bit for line 17 */ |
bogdanm | 86:04dd9b1680ae | 3574 | #define EXTI_PR_PR18 ((uint32_t)0x00040000) /*!< Pending bit for line 18 */ |
bogdanm | 86:04dd9b1680ae | 3575 | #define EXTI_PR_PR19 ((uint32_t)0x00080000) /*!< Pending bit for line 19 */ |
bogdanm | 86:04dd9b1680ae | 3576 | #define EXTI_PR_PR20 ((uint32_t)0x00100000) /*!< Pending bit for line 20 */ |
bogdanm | 86:04dd9b1680ae | 3577 | #define EXTI_PR_PR21 ((uint32_t)0x00200000) /*!< Pending bit for line 21 */ |
bogdanm | 86:04dd9b1680ae | 3578 | #define EXTI_PR_PR22 ((uint32_t)0x00400000) /*!< Pending bit for line 22 */ |
bogdanm | 86:04dd9b1680ae | 3579 | #define EXTI_PR_PR23 ((uint32_t)0x00800000) /*!< Pending bit for line 23 */ |
bogdanm | 86:04dd9b1680ae | 3580 | #define EXTI_PR_PR24 ((uint32_t)0x01000000) /*!< Pending bit for line 24 */ |
bogdanm | 86:04dd9b1680ae | 3581 | #define EXTI_PR_PR25 ((uint32_t)0x02000000) /*!< Pending bit for line 25 */ |
bogdanm | 86:04dd9b1680ae | 3582 | #define EXTI_PR_PR26 ((uint32_t)0x04000000) /*!< Pending bit for line 26 */ |
bogdanm | 86:04dd9b1680ae | 3583 | #define EXTI_PR_PR27 ((uint32_t)0x08000000) /*!< Pending bit for line 27 */ |
bogdanm | 86:04dd9b1680ae | 3584 | #define EXTI_PR_PR28 ((uint32_t)0x10000000) /*!< Pending bit for line 28 */ |
bogdanm | 86:04dd9b1680ae | 3585 | |
bogdanm | 86:04dd9b1680ae | 3586 | /******************************************************************************/ |
bogdanm | 86:04dd9b1680ae | 3587 | /* */ |
bogdanm | 86:04dd9b1680ae | 3588 | /* FLASH */ |
bogdanm | 86:04dd9b1680ae | 3589 | /* */ |
bogdanm | 86:04dd9b1680ae | 3590 | /******************************************************************************/ |
bogdanm | 86:04dd9b1680ae | 3591 | /******************* Bit definition for FLASH_ACR register ******************/ |
bogdanm | 86:04dd9b1680ae | 3592 | #define FLASH_ACR_LATENCY ((uint32_t)0x00000007) /*!< LATENCY[2:0] bits (Latency) */ |
bogdanm | 86:04dd9b1680ae | 3593 | #define FLASH_ACR_LATENCY_0 ((uint32_t)0x00000001) /*!< Bit 0 */ |
bogdanm | 86:04dd9b1680ae | 3594 | #define FLASH_ACR_LATENCY_1 ((uint32_t)0x00000002) /*!< Bit 1 */ |
bogdanm | 86:04dd9b1680ae | 3595 | #define FLASH_ACR_LATENCY_2 ((uint32_t)0x00000004) /*!< Bit 2 */ |
bogdanm | 86:04dd9b1680ae | 3596 | |
bogdanm | 86:04dd9b1680ae | 3597 | #define FLASH_ACR_HLFCYA ((uint32_t)0x00000008) /*!< Flash Half Cycle Access Enable */ |
bogdanm | 86:04dd9b1680ae | 3598 | #define FLASH_ACR_PRFTBE ((uint32_t)0x00000010) /*!< Prefetch Buffer Enable */ |
bogdanm | 86:04dd9b1680ae | 3599 | #define FLASH_ACR_PRFTBS ((uint32_t)0x00000020) /*!< Prefetch Buffer Status */ |
bogdanm | 86:04dd9b1680ae | 3600 | |
bogdanm | 86:04dd9b1680ae | 3601 | /****************** Bit definition for FLASH_KEYR register ******************/ |
bogdanm | 86:04dd9b1680ae | 3602 | #define FLASH_KEYR_FKEYR ((uint32_t)0xFFFFFFFF) /*!< FPEC Key */ |
bogdanm | 86:04dd9b1680ae | 3603 | |
bogdanm | 86:04dd9b1680ae | 3604 | #define RDP_KEY ((uint32_t)0x000000A5) /*!< RDP Key */ |
bogdanm | 86:04dd9b1680ae | 3605 | #define FLASH_KEY1 ((uint32_t)0x45670123) /*!< FPEC Key1 */ |
bogdanm | 86:04dd9b1680ae | 3606 | #define FLASH_KEY2 ((uint32_t)0xCDEF89AB) /*!< FPEC Key2 */ |
bogdanm | 86:04dd9b1680ae | 3607 | |
bogdanm | 86:04dd9b1680ae | 3608 | /***************** Bit definition for FLASH_OPTKEYR register ****************/ |
bogdanm | 86:04dd9b1680ae | 3609 | #define FLASH_OPTKEYR_OPTKEYR ((uint32_t)0xFFFFFFFF) /*!< Option Byte Key */ |
bogdanm | 86:04dd9b1680ae | 3610 | |
bogdanm | 86:04dd9b1680ae | 3611 | #define FLASH_OPTKEY1 FLASH_KEY1 /*!< Option Byte Key1 */ |
bogdanm | 86:04dd9b1680ae | 3612 | #define FLASH_OPTKEY2 FLASH_KEY2 /*!< Option Byte Key2 */ |
bogdanm | 86:04dd9b1680ae | 3613 | |
bogdanm | 86:04dd9b1680ae | 3614 | /****************** Bit definition for FLASH_SR register *******************/ |
bogdanm | 86:04dd9b1680ae | 3615 | #define FLASH_SR_BSY ((uint32_t)0x00000001) /*!< Busy */ |
bogdanm | 86:04dd9b1680ae | 3616 | #define FLASH_SR_PGERR ((uint32_t)0x00000004) /*!< Programming Error */ |
bogdanm | 86:04dd9b1680ae | 3617 | #define FLASH_SR_WRPERR ((uint32_t)0x00000010) /*!< Write Protection Error */ |
bogdanm | 86:04dd9b1680ae | 3618 | #define FLASH_SR_EOP ((uint32_t)0x00000020) /*!< End of operation */ |
bogdanm | 86:04dd9b1680ae | 3619 | |
bogdanm | 86:04dd9b1680ae | 3620 | /******************* Bit definition for FLASH_CR register *******************/ |
bogdanm | 86:04dd9b1680ae | 3621 | #define FLASH_CR_PG ((uint32_t)0x00000001) /*!< Programming */ |
bogdanm | 86:04dd9b1680ae | 3622 | #define FLASH_CR_PER ((uint32_t)0x00000002) /*!< Page Erase */ |
bogdanm | 86:04dd9b1680ae | 3623 | #define FLASH_CR_MER ((uint32_t)0x00000004) /*!< Mass Erase */ |
bogdanm | 86:04dd9b1680ae | 3624 | #define FLASH_CR_OPTPG ((uint32_t)0x00000010) /*!< Option Byte Programming */ |
bogdanm | 86:04dd9b1680ae | 3625 | #define FLASH_CR_OPTER ((uint32_t)0x00000020) /*!< Option Byte Erase */ |
bogdanm | 86:04dd9b1680ae | 3626 | #define FLASH_CR_STRT ((uint32_t)0x00000040) /*!< Start */ |
bogdanm | 86:04dd9b1680ae | 3627 | #define FLASH_CR_LOCK ((uint32_t)0x00000080) /*!< Lock */ |
bogdanm | 86:04dd9b1680ae | 3628 | #define FLASH_CR_OPTWRE ((uint32_t)0x00000200) /*!< Option Bytes Write Enable */ |
bogdanm | 86:04dd9b1680ae | 3629 | #define FLASH_CR_ERRIE ((uint32_t)0x00000400) /*!< Error Interrupt Enable */ |
bogdanm | 86:04dd9b1680ae | 3630 | #define FLASH_CR_EOPIE ((uint32_t)0x00001000) /*!< End of operation interrupt enable */ |
bogdanm | 86:04dd9b1680ae | 3631 | #define FLASH_CR_OBL_LAUNCH ((uint32_t)0x00002000) /*!< OptionBytes Loader Launch */ |
bogdanm | 86:04dd9b1680ae | 3632 | |
bogdanm | 86:04dd9b1680ae | 3633 | /******************* Bit definition for FLASH_AR register *******************/ |
bogdanm | 86:04dd9b1680ae | 3634 | #define FLASH_AR_FAR ((uint32_t)0xFFFFFFFF) /*!< Flash Address */ |
bogdanm | 86:04dd9b1680ae | 3635 | |
bogdanm | 86:04dd9b1680ae | 3636 | /****************** Bit definition for FLASH_OBR register *******************/ |
bogdanm | 86:04dd9b1680ae | 3637 | #define FLASH_OBR_OPTERR ((uint32_t)0x00000001) /*!< Option Byte Error */ |
bogdanm | 86:04dd9b1680ae | 3638 | #define FLASH_OBR_RDPRT ((uint32_t)0x00000006) /*!< Read protection */ |
bogdanm | 86:04dd9b1680ae | 3639 | #define FLASH_OBR_RDPRT_1 ((uint32_t)0x00000002) /*!< Read protection Level 1 */ |
bogdanm | 86:04dd9b1680ae | 3640 | #define FLASH_OBR_RDPRT_2 ((uint32_t)0x00000006) /*!< Read protection Level 2 */ |
bogdanm | 86:04dd9b1680ae | 3641 | |
bogdanm | 86:04dd9b1680ae | 3642 | #define FLASH_OBR_USER ((uint32_t)0x00007700) /*!< User Option Bytes */ |
bogdanm | 86:04dd9b1680ae | 3643 | #define FLASH_OBR_IWDG_SW ((uint32_t)0x00000100) /*!< IWDG SW */ |
bogdanm | 86:04dd9b1680ae | 3644 | #define FLASH_OBR_nRST_STOP ((uint32_t)0x00000200) /*!< nRST_STOP */ |
bogdanm | 86:04dd9b1680ae | 3645 | #define FLASH_OBR_nRST_STDBY ((uint32_t)0x00000400) /*!< nRST_STDBY */ |
bogdanm | 86:04dd9b1680ae | 3646 | #define FLASH_OBR_nBOOT1 ((uint32_t)0x00001000) /*!< nBOOT1 */ |
bogdanm | 86:04dd9b1680ae | 3647 | #define FLASH_OBR_VDDA_MONITOR ((uint32_t)0x00002000) /*!< VDDA_MONITOR */ |
bogdanm | 86:04dd9b1680ae | 3648 | #define FLASH_OBR_SRAM_PE ((uint32_t)0x00004000) /*!< SRAM_PE */ |
bogdanm | 86:04dd9b1680ae | 3649 | |
bogdanm | 86:04dd9b1680ae | 3650 | /****************** Bit definition for FLASH_WRPR register ******************/ |
bogdanm | 86:04dd9b1680ae | 3651 | #define FLASH_WRPR_WRP ((uint32_t)0xFFFFFFFF) /*!< Write Protect */ |
bogdanm | 86:04dd9b1680ae | 3652 | |
bogdanm | 86:04dd9b1680ae | 3653 | /*----------------------------------------------------------------------------*/ |
bogdanm | 86:04dd9b1680ae | 3654 | |
bogdanm | 86:04dd9b1680ae | 3655 | /****************** Bit definition for OB_RDP register **********************/ |
bogdanm | 86:04dd9b1680ae | 3656 | #define OB_RDP_RDP ((uint32_t)0x000000FF) /*!< Read protection option byte */ |
bogdanm | 86:04dd9b1680ae | 3657 | #define OB_RDP_nRDP ((uint32_t)0x0000FF00) /*!< Read protection complemented option byte */ |
bogdanm | 86:04dd9b1680ae | 3658 | |
bogdanm | 86:04dd9b1680ae | 3659 | /****************** Bit definition for OB_USER register *********************/ |
bogdanm | 86:04dd9b1680ae | 3660 | #define OB_USER_USER ((uint32_t)0x00FF0000) /*!< User option byte */ |
bogdanm | 86:04dd9b1680ae | 3661 | #define OB_USER_nUSER ((uint32_t)0xFF000000) /*!< User complemented option byte */ |
bogdanm | 86:04dd9b1680ae | 3662 | |
bogdanm | 86:04dd9b1680ae | 3663 | /****************** Bit definition for FLASH_WRP0 register ******************/ |
bogdanm | 86:04dd9b1680ae | 3664 | #define OB_WRP0_WRP0 ((uint32_t)0x000000FF) /*!< Flash memory write protection option bytes */ |
bogdanm | 86:04dd9b1680ae | 3665 | #define OB_WRP0_nWRP0 ((uint32_t)0x0000FF00) /*!< Flash memory write protection complemented option bytes */ |
bogdanm | 86:04dd9b1680ae | 3666 | |
bogdanm | 86:04dd9b1680ae | 3667 | /****************** Bit definition for FLASH_WRP1 register ******************/ |
bogdanm | 86:04dd9b1680ae | 3668 | #define OB_WRP1_WRP1 ((uint32_t)0x00FF0000) /*!< Flash memory write protection option bytes */ |
bogdanm | 86:04dd9b1680ae | 3669 | #define OB_WRP1_nWRP1 ((uint32_t)0xFF000000) /*!< Flash memory write protection complemented option bytes */ |
bogdanm | 86:04dd9b1680ae | 3670 | |
bogdanm | 86:04dd9b1680ae | 3671 | /****************** Bit definition for FLASH_WRP2 register ******************/ |
bogdanm | 86:04dd9b1680ae | 3672 | #define OB_WRP2_WRP2 ((uint32_t)0x000000FF) /*!< Flash memory write protection option bytes */ |
bogdanm | 86:04dd9b1680ae | 3673 | #define OB_WRP2_nWRP2 ((uint32_t)0x0000FF00) /*!< Flash memory write protection complemented option bytes */ |
bogdanm | 86:04dd9b1680ae | 3674 | |
bogdanm | 86:04dd9b1680ae | 3675 | /****************** Bit definition for FLASH_WRP3 register ******************/ |
bogdanm | 86:04dd9b1680ae | 3676 | #define OB_WRP3_WRP3 ((uint32_t)0x00FF0000) /*!< Flash memory write protection option bytes */ |
bogdanm | 86:04dd9b1680ae | 3677 | #define OB_WRP3_nWRP3 ((uint32_t)0xFF000000) /*!< Flash memory write protection complemented option bytes */ |
bogdanm | 86:04dd9b1680ae | 3678 | /******************************************************************************/ |
bogdanm | 86:04dd9b1680ae | 3679 | /* */ |
bogdanm | 86:04dd9b1680ae | 3680 | /* General Purpose I/O (GPIO) */ |
bogdanm | 86:04dd9b1680ae | 3681 | /* */ |
bogdanm | 86:04dd9b1680ae | 3682 | /******************************************************************************/ |
bogdanm | 86:04dd9b1680ae | 3683 | /******************* Bit definition for GPIO_MODER register *****************/ |
bogdanm | 86:04dd9b1680ae | 3684 | #define GPIO_MODER_MODER0 ((uint32_t)0x00000003) |
bogdanm | 86:04dd9b1680ae | 3685 | #define GPIO_MODER_MODER0_0 ((uint32_t)0x00000001) |
bogdanm | 86:04dd9b1680ae | 3686 | #define GPIO_MODER_MODER0_1 ((uint32_t)0x00000002) |
bogdanm | 86:04dd9b1680ae | 3687 | #define GPIO_MODER_MODER1 ((uint32_t)0x0000000C) |
bogdanm | 86:04dd9b1680ae | 3688 | #define GPIO_MODER_MODER1_0 ((uint32_t)0x00000004) |
bogdanm | 86:04dd9b1680ae | 3689 | #define GPIO_MODER_MODER1_1 ((uint32_t)0x00000008) |
bogdanm | 86:04dd9b1680ae | 3690 | #define GPIO_MODER_MODER2 ((uint32_t)0x00000030) |
bogdanm | 86:04dd9b1680ae | 3691 | #define GPIO_MODER_MODER2_0 ((uint32_t)0x00000010) |
bogdanm | 86:04dd9b1680ae | 3692 | #define GPIO_MODER_MODER2_1 ((uint32_t)0x00000020) |
bogdanm | 86:04dd9b1680ae | 3693 | #define GPIO_MODER_MODER3 ((uint32_t)0x000000C0) |
bogdanm | 86:04dd9b1680ae | 3694 | #define GPIO_MODER_MODER3_0 ((uint32_t)0x00000040) |
bogdanm | 86:04dd9b1680ae | 3695 | #define GPIO_MODER_MODER3_1 ((uint32_t)0x00000080) |
bogdanm | 86:04dd9b1680ae | 3696 | #define GPIO_MODER_MODER4 ((uint32_t)0x00000300) |
bogdanm | 86:04dd9b1680ae | 3697 | #define GPIO_MODER_MODER4_0 ((uint32_t)0x00000100) |
bogdanm | 86:04dd9b1680ae | 3698 | #define GPIO_MODER_MODER4_1 ((uint32_t)0x00000200) |
bogdanm | 86:04dd9b1680ae | 3699 | #define GPIO_MODER_MODER5 ((uint32_t)0x00000C00) |
bogdanm | 86:04dd9b1680ae | 3700 | #define GPIO_MODER_MODER5_0 ((uint32_t)0x00000400) |
bogdanm | 86:04dd9b1680ae | 3701 | #define GPIO_MODER_MODER5_1 ((uint32_t)0x00000800) |
bogdanm | 86:04dd9b1680ae | 3702 | #define GPIO_MODER_MODER6 ((uint32_t)0x00003000) |
bogdanm | 86:04dd9b1680ae | 3703 | #define GPIO_MODER_MODER6_0 ((uint32_t)0x00001000) |
bogdanm | 86:04dd9b1680ae | 3704 | #define GPIO_MODER_MODER6_1 ((uint32_t)0x00002000) |
bogdanm | 86:04dd9b1680ae | 3705 | #define GPIO_MODER_MODER7 ((uint32_t)0x0000C000) |
bogdanm | 86:04dd9b1680ae | 3706 | #define GPIO_MODER_MODER7_0 ((uint32_t)0x00004000) |
bogdanm | 86:04dd9b1680ae | 3707 | #define GPIO_MODER_MODER7_1 ((uint32_t)0x00008000) |
bogdanm | 86:04dd9b1680ae | 3708 | #define GPIO_MODER_MODER8 ((uint32_t)0x00030000) |
bogdanm | 86:04dd9b1680ae | 3709 | #define GPIO_MODER_MODER8_0 ((uint32_t)0x00010000) |
bogdanm | 86:04dd9b1680ae | 3710 | #define GPIO_MODER_MODER8_1 ((uint32_t)0x00020000) |
bogdanm | 86:04dd9b1680ae | 3711 | #define GPIO_MODER_MODER9 ((uint32_t)0x000C0000) |
bogdanm | 86:04dd9b1680ae | 3712 | #define GPIO_MODER_MODER9_0 ((uint32_t)0x00040000) |
bogdanm | 86:04dd9b1680ae | 3713 | #define GPIO_MODER_MODER9_1 ((uint32_t)0x00080000) |
bogdanm | 86:04dd9b1680ae | 3714 | #define GPIO_MODER_MODER10 ((uint32_t)0x00300000) |
bogdanm | 86:04dd9b1680ae | 3715 | #define GPIO_MODER_MODER10_0 ((uint32_t)0x00100000) |
bogdanm | 86:04dd9b1680ae | 3716 | #define GPIO_MODER_MODER10_1 ((uint32_t)0x00200000) |
bogdanm | 86:04dd9b1680ae | 3717 | #define GPIO_MODER_MODER11 ((uint32_t)0x00C00000) |
bogdanm | 86:04dd9b1680ae | 3718 | #define GPIO_MODER_MODER11_0 ((uint32_t)0x00400000) |
bogdanm | 86:04dd9b1680ae | 3719 | #define GPIO_MODER_MODER11_1 ((uint32_t)0x00800000) |
bogdanm | 86:04dd9b1680ae | 3720 | #define GPIO_MODER_MODER12 ((uint32_t)0x03000000) |
bogdanm | 86:04dd9b1680ae | 3721 | #define GPIO_MODER_MODER12_0 ((uint32_t)0x01000000) |
bogdanm | 86:04dd9b1680ae | 3722 | #define GPIO_MODER_MODER12_1 ((uint32_t)0x02000000) |
bogdanm | 86:04dd9b1680ae | 3723 | #define GPIO_MODER_MODER13 ((uint32_t)0x0C000000) |
bogdanm | 86:04dd9b1680ae | 3724 | #define GPIO_MODER_MODER13_0 ((uint32_t)0x04000000) |
bogdanm | 86:04dd9b1680ae | 3725 | #define GPIO_MODER_MODER13_1 ((uint32_t)0x08000000) |
bogdanm | 86:04dd9b1680ae | 3726 | #define GPIO_MODER_MODER14 ((uint32_t)0x30000000) |
bogdanm | 86:04dd9b1680ae | 3727 | #define GPIO_MODER_MODER14_0 ((uint32_t)0x10000000) |
bogdanm | 86:04dd9b1680ae | 3728 | #define GPIO_MODER_MODER14_1 ((uint32_t)0x20000000) |
bogdanm | 86:04dd9b1680ae | 3729 | #define GPIO_MODER_MODER15 ((uint32_t)0xC0000000) |
bogdanm | 86:04dd9b1680ae | 3730 | #define GPIO_MODER_MODER15_0 ((uint32_t)0x40000000) |
bogdanm | 86:04dd9b1680ae | 3731 | #define GPIO_MODER_MODER15_1 ((uint32_t)0x80000000) |
bogdanm | 86:04dd9b1680ae | 3732 | |
bogdanm | 86:04dd9b1680ae | 3733 | /****************** Bit definition for GPIO_OTYPER register *****************/ |
bogdanm | 86:04dd9b1680ae | 3734 | #define GPIO_OTYPER_OT_0 ((uint32_t)0x00000001) |
bogdanm | 86:04dd9b1680ae | 3735 | #define GPIO_OTYPER_OT_1 ((uint32_t)0x00000002) |
bogdanm | 86:04dd9b1680ae | 3736 | #define GPIO_OTYPER_OT_2 ((uint32_t)0x00000004) |
bogdanm | 86:04dd9b1680ae | 3737 | #define GPIO_OTYPER_OT_3 ((uint32_t)0x00000008) |
bogdanm | 86:04dd9b1680ae | 3738 | #define GPIO_OTYPER_OT_4 ((uint32_t)0x00000010) |
bogdanm | 86:04dd9b1680ae | 3739 | #define GPIO_OTYPER_OT_5 ((uint32_t)0x00000020) |
bogdanm | 86:04dd9b1680ae | 3740 | #define GPIO_OTYPER_OT_6 ((uint32_t)0x00000040) |
bogdanm | 86:04dd9b1680ae | 3741 | #define GPIO_OTYPER_OT_7 ((uint32_t)0x00000080) |
bogdanm | 86:04dd9b1680ae | 3742 | #define GPIO_OTYPER_OT_8 ((uint32_t)0x00000100) |
bogdanm | 86:04dd9b1680ae | 3743 | #define GPIO_OTYPER_OT_9 ((uint32_t)0x00000200) |
bogdanm | 86:04dd9b1680ae | 3744 | #define GPIO_OTYPER_OT_10 ((uint32_t)0x00000400) |
bogdanm | 86:04dd9b1680ae | 3745 | #define GPIO_OTYPER_OT_11 ((uint32_t)0x00000800) |
bogdanm | 86:04dd9b1680ae | 3746 | #define GPIO_OTYPER_OT_12 ((uint32_t)0x00001000) |
bogdanm | 86:04dd9b1680ae | 3747 | #define GPIO_OTYPER_OT_13 ((uint32_t)0x00002000) |
bogdanm | 86:04dd9b1680ae | 3748 | #define GPIO_OTYPER_OT_14 ((uint32_t)0x00004000) |
bogdanm | 86:04dd9b1680ae | 3749 | #define GPIO_OTYPER_OT_15 ((uint32_t)0x00008000) |
bogdanm | 86:04dd9b1680ae | 3750 | |
bogdanm | 86:04dd9b1680ae | 3751 | /**************** Bit definition for GPIO_OSPEEDR register ******************/ |
bogdanm | 86:04dd9b1680ae | 3752 | #define GPIO_OSPEEDER_OSPEEDR0 ((uint32_t)0x00000003) |
bogdanm | 86:04dd9b1680ae | 3753 | #define GPIO_OSPEEDER_OSPEEDR0_0 ((uint32_t)0x00000001) |
bogdanm | 86:04dd9b1680ae | 3754 | #define GPIO_OSPEEDER_OSPEEDR0_1 ((uint32_t)0x00000002) |
bogdanm | 86:04dd9b1680ae | 3755 | #define GPIO_OSPEEDER_OSPEEDR1 ((uint32_t)0x0000000C) |
bogdanm | 86:04dd9b1680ae | 3756 | #define GPIO_OSPEEDER_OSPEEDR1_0 ((uint32_t)0x00000004) |
bogdanm | 86:04dd9b1680ae | 3757 | #define GPIO_OSPEEDER_OSPEEDR1_1 ((uint32_t)0x00000008) |
bogdanm | 86:04dd9b1680ae | 3758 | #define GPIO_OSPEEDER_OSPEEDR2 ((uint32_t)0x00000030) |
bogdanm | 86:04dd9b1680ae | 3759 | #define GPIO_OSPEEDER_OSPEEDR2_0 ((uint32_t)0x00000010) |
bogdanm | 86:04dd9b1680ae | 3760 | #define GPIO_OSPEEDER_OSPEEDR2_1 ((uint32_t)0x00000020) |
bogdanm | 86:04dd9b1680ae | 3761 | #define GPIO_OSPEEDER_OSPEEDR3 ((uint32_t)0x000000C0) |
bogdanm | 86:04dd9b1680ae | 3762 | #define GPIO_OSPEEDER_OSPEEDR3_0 ((uint32_t)0x00000040) |
bogdanm | 86:04dd9b1680ae | 3763 | #define GPIO_OSPEEDER_OSPEEDR3_1 ((uint32_t)0x00000080) |
bogdanm | 86:04dd9b1680ae | 3764 | #define GPIO_OSPEEDER_OSPEEDR4 ((uint32_t)0x00000300) |
bogdanm | 86:04dd9b1680ae | 3765 | #define GPIO_OSPEEDER_OSPEEDR4_0 ((uint32_t)0x00000100) |
bogdanm | 86:04dd9b1680ae | 3766 | #define GPIO_OSPEEDER_OSPEEDR4_1 ((uint32_t)0x00000200) |
bogdanm | 86:04dd9b1680ae | 3767 | #define GPIO_OSPEEDER_OSPEEDR5 ((uint32_t)0x00000C00) |
bogdanm | 86:04dd9b1680ae | 3768 | #define GPIO_OSPEEDER_OSPEEDR5_0 ((uint32_t)0x00000400) |
bogdanm | 86:04dd9b1680ae | 3769 | #define GPIO_OSPEEDER_OSPEEDR5_1 ((uint32_t)0x00000800) |
bogdanm | 86:04dd9b1680ae | 3770 | #define GPIO_OSPEEDER_OSPEEDR6 ((uint32_t)0x00003000) |
bogdanm | 86:04dd9b1680ae | 3771 | #define GPIO_OSPEEDER_OSPEEDR6_0 ((uint32_t)0x00001000) |
bogdanm | 86:04dd9b1680ae | 3772 | #define GPIO_OSPEEDER_OSPEEDR6_1 ((uint32_t)0x00002000) |
bogdanm | 86:04dd9b1680ae | 3773 | #define GPIO_OSPEEDER_OSPEEDR7 ((uint32_t)0x0000C000) |
bogdanm | 86:04dd9b1680ae | 3774 | #define GPIO_OSPEEDER_OSPEEDR7_0 ((uint32_t)0x00004000) |
bogdanm | 86:04dd9b1680ae | 3775 | #define GPIO_OSPEEDER_OSPEEDR7_1 ((uint32_t)0x00008000) |
bogdanm | 86:04dd9b1680ae | 3776 | #define GPIO_OSPEEDER_OSPEEDR8 ((uint32_t)0x00030000) |
bogdanm | 86:04dd9b1680ae | 3777 | #define GPIO_OSPEEDER_OSPEEDR8_0 ((uint32_t)0x00010000) |
bogdanm | 86:04dd9b1680ae | 3778 | #define GPIO_OSPEEDER_OSPEEDR8_1 ((uint32_t)0x00020000) |
bogdanm | 86:04dd9b1680ae | 3779 | #define GPIO_OSPEEDER_OSPEEDR9 ((uint32_t)0x000C0000) |
bogdanm | 86:04dd9b1680ae | 3780 | #define GPIO_OSPEEDER_OSPEEDR9_0 ((uint32_t)0x00040000) |
bogdanm | 86:04dd9b1680ae | 3781 | #define GPIO_OSPEEDER_OSPEEDR9_1 ((uint32_t)0x00080000) |
bogdanm | 86:04dd9b1680ae | 3782 | #define GPIO_OSPEEDER_OSPEEDR10 ((uint32_t)0x00300000) |
bogdanm | 86:04dd9b1680ae | 3783 | #define GPIO_OSPEEDER_OSPEEDR10_0 ((uint32_t)0x00100000) |
bogdanm | 86:04dd9b1680ae | 3784 | #define GPIO_OSPEEDER_OSPEEDR10_1 ((uint32_t)0x00200000) |
bogdanm | 86:04dd9b1680ae | 3785 | #define GPIO_OSPEEDER_OSPEEDR11 ((uint32_t)0x00C00000) |
bogdanm | 86:04dd9b1680ae | 3786 | #define GPIO_OSPEEDER_OSPEEDR11_0 ((uint32_t)0x00400000) |
bogdanm | 86:04dd9b1680ae | 3787 | #define GPIO_OSPEEDER_OSPEEDR11_1 ((uint32_t)0x00800000) |
bogdanm | 86:04dd9b1680ae | 3788 | #define GPIO_OSPEEDER_OSPEEDR12 ((uint32_t)0x03000000) |
bogdanm | 86:04dd9b1680ae | 3789 | #define GPIO_OSPEEDER_OSPEEDR12_0 ((uint32_t)0x01000000) |
bogdanm | 86:04dd9b1680ae | 3790 | #define GPIO_OSPEEDER_OSPEEDR12_1 ((uint32_t)0x02000000) |
bogdanm | 86:04dd9b1680ae | 3791 | #define GPIO_OSPEEDER_OSPEEDR13 ((uint32_t)0x0C000000) |
bogdanm | 86:04dd9b1680ae | 3792 | #define GPIO_OSPEEDER_OSPEEDR13_0 ((uint32_t)0x04000000) |
bogdanm | 86:04dd9b1680ae | 3793 | #define GPIO_OSPEEDER_OSPEEDR13_1 ((uint32_t)0x08000000) |
bogdanm | 86:04dd9b1680ae | 3794 | #define GPIO_OSPEEDER_OSPEEDR14 ((uint32_t)0x30000000) |
bogdanm | 86:04dd9b1680ae | 3795 | #define GPIO_OSPEEDER_OSPEEDR14_0 ((uint32_t)0x10000000) |
bogdanm | 86:04dd9b1680ae | 3796 | #define GPIO_OSPEEDER_OSPEEDR14_1 ((uint32_t)0x20000000) |
bogdanm | 86:04dd9b1680ae | 3797 | #define GPIO_OSPEEDER_OSPEEDR15 ((uint32_t)0xC0000000) |
bogdanm | 86:04dd9b1680ae | 3798 | #define GPIO_OSPEEDER_OSPEEDR15_0 ((uint32_t)0x40000000) |
bogdanm | 86:04dd9b1680ae | 3799 | #define GPIO_OSPEEDER_OSPEEDR15_1 ((uint32_t)0x80000000) |
bogdanm | 86:04dd9b1680ae | 3800 | |
bogdanm | 86:04dd9b1680ae | 3801 | /******************* Bit definition for GPIO_PUPDR register ******************/ |
bogdanm | 86:04dd9b1680ae | 3802 | #define GPIO_PUPDR_PUPDR0 ((uint32_t)0x00000003) |
bogdanm | 86:04dd9b1680ae | 3803 | #define GPIO_PUPDR_PUPDR0_0 ((uint32_t)0x00000001) |
bogdanm | 86:04dd9b1680ae | 3804 | #define GPIO_PUPDR_PUPDR0_1 ((uint32_t)0x00000002) |
bogdanm | 86:04dd9b1680ae | 3805 | #define GPIO_PUPDR_PUPDR1 ((uint32_t)0x0000000C) |
bogdanm | 86:04dd9b1680ae | 3806 | #define GPIO_PUPDR_PUPDR1_0 ((uint32_t)0x00000004) |
bogdanm | 86:04dd9b1680ae | 3807 | #define GPIO_PUPDR_PUPDR1_1 ((uint32_t)0x00000008) |
bogdanm | 86:04dd9b1680ae | 3808 | #define GPIO_PUPDR_PUPDR2 ((uint32_t)0x00000030) |
bogdanm | 86:04dd9b1680ae | 3809 | #define GPIO_PUPDR_PUPDR2_0 ((uint32_t)0x00000010) |
bogdanm | 86:04dd9b1680ae | 3810 | #define GPIO_PUPDR_PUPDR2_1 ((uint32_t)0x00000020) |
bogdanm | 86:04dd9b1680ae | 3811 | #define GPIO_PUPDR_PUPDR3 ((uint32_t)0x000000C0) |
bogdanm | 86:04dd9b1680ae | 3812 | #define GPIO_PUPDR_PUPDR3_0 ((uint32_t)0x00000040) |
bogdanm | 86:04dd9b1680ae | 3813 | #define GPIO_PUPDR_PUPDR3_1 ((uint32_t)0x00000080) |
bogdanm | 86:04dd9b1680ae | 3814 | #define GPIO_PUPDR_PUPDR4 ((uint32_t)0x00000300) |
bogdanm | 86:04dd9b1680ae | 3815 | #define GPIO_PUPDR_PUPDR4_0 ((uint32_t)0x00000100) |
bogdanm | 86:04dd9b1680ae | 3816 | #define GPIO_PUPDR_PUPDR4_1 ((uint32_t)0x00000200) |
bogdanm | 86:04dd9b1680ae | 3817 | #define GPIO_PUPDR_PUPDR5 ((uint32_t)0x00000C00) |
bogdanm | 86:04dd9b1680ae | 3818 | #define GPIO_PUPDR_PUPDR5_0 ((uint32_t)0x00000400) |
bogdanm | 86:04dd9b1680ae | 3819 | #define GPIO_PUPDR_PUPDR5_1 ((uint32_t)0x00000800) |
bogdanm | 86:04dd9b1680ae | 3820 | #define GPIO_PUPDR_PUPDR6 ((uint32_t)0x00003000) |
bogdanm | 86:04dd9b1680ae | 3821 | #define GPIO_PUPDR_PUPDR6_0 ((uint32_t)0x00001000) |
bogdanm | 86:04dd9b1680ae | 3822 | #define GPIO_PUPDR_PUPDR6_1 ((uint32_t)0x00002000) |
bogdanm | 86:04dd9b1680ae | 3823 | #define GPIO_PUPDR_PUPDR7 ((uint32_t)0x0000C000) |
bogdanm | 86:04dd9b1680ae | 3824 | #define GPIO_PUPDR_PUPDR7_0 ((uint32_t)0x00004000) |
bogdanm | 86:04dd9b1680ae | 3825 | #define GPIO_PUPDR_PUPDR7_1 ((uint32_t)0x00008000) |
bogdanm | 86:04dd9b1680ae | 3826 | #define GPIO_PUPDR_PUPDR8 ((uint32_t)0x00030000) |
bogdanm | 86:04dd9b1680ae | 3827 | #define GPIO_PUPDR_PUPDR8_0 ((uint32_t)0x00010000) |
bogdanm | 86:04dd9b1680ae | 3828 | #define GPIO_PUPDR_PUPDR8_1 ((uint32_t)0x00020000) |
bogdanm | 86:04dd9b1680ae | 3829 | #define GPIO_PUPDR_PUPDR9 ((uint32_t)0x000C0000) |
bogdanm | 86:04dd9b1680ae | 3830 | #define GPIO_PUPDR_PUPDR9_0 ((uint32_t)0x00040000) |
bogdanm | 86:04dd9b1680ae | 3831 | #define GPIO_PUPDR_PUPDR9_1 ((uint32_t)0x00080000) |
bogdanm | 86:04dd9b1680ae | 3832 | #define GPIO_PUPDR_PUPDR10 ((uint32_t)0x00300000) |
bogdanm | 86:04dd9b1680ae | 3833 | #define GPIO_PUPDR_PUPDR10_0 ((uint32_t)0x00100000) |
bogdanm | 86:04dd9b1680ae | 3834 | #define GPIO_PUPDR_PUPDR10_1 ((uint32_t)0x00200000) |
bogdanm | 86:04dd9b1680ae | 3835 | #define GPIO_PUPDR_PUPDR11 ((uint32_t)0x00C00000) |
bogdanm | 86:04dd9b1680ae | 3836 | #define GPIO_PUPDR_PUPDR11_0 ((uint32_t)0x00400000) |
bogdanm | 86:04dd9b1680ae | 3837 | #define GPIO_PUPDR_PUPDR11_1 ((uint32_t)0x00800000) |
bogdanm | 86:04dd9b1680ae | 3838 | #define GPIO_PUPDR_PUPDR12 ((uint32_t)0x03000000) |
bogdanm | 86:04dd9b1680ae | 3839 | #define GPIO_PUPDR_PUPDR12_0 ((uint32_t)0x01000000) |
bogdanm | 86:04dd9b1680ae | 3840 | #define GPIO_PUPDR_PUPDR12_1 ((uint32_t)0x02000000) |
bogdanm | 86:04dd9b1680ae | 3841 | #define GPIO_PUPDR_PUPDR13 ((uint32_t)0x0C000000) |
bogdanm | 86:04dd9b1680ae | 3842 | #define GPIO_PUPDR_PUPDR13_0 ((uint32_t)0x04000000) |
bogdanm | 86:04dd9b1680ae | 3843 | #define GPIO_PUPDR_PUPDR13_1 ((uint32_t)0x08000000) |
bogdanm | 86:04dd9b1680ae | 3844 | #define GPIO_PUPDR_PUPDR14 ((uint32_t)0x30000000) |
bogdanm | 86:04dd9b1680ae | 3845 | #define GPIO_PUPDR_PUPDR14_0 ((uint32_t)0x10000000) |
bogdanm | 86:04dd9b1680ae | 3846 | #define GPIO_PUPDR_PUPDR14_1 ((uint32_t)0x20000000) |
bogdanm | 86:04dd9b1680ae | 3847 | #define GPIO_PUPDR_PUPDR15 ((uint32_t)0xC0000000) |
bogdanm | 86:04dd9b1680ae | 3848 | #define GPIO_PUPDR_PUPDR15_0 ((uint32_t)0x40000000) |
bogdanm | 86:04dd9b1680ae | 3849 | #define GPIO_PUPDR_PUPDR15_1 ((uint32_t)0x80000000) |
bogdanm | 86:04dd9b1680ae | 3850 | |
bogdanm | 86:04dd9b1680ae | 3851 | /******************* Bit definition for GPIO_IDR register *******************/ |
bogdanm | 86:04dd9b1680ae | 3852 | #define GPIO_IDR_0 ((uint32_t)0x00000001) |
bogdanm | 86:04dd9b1680ae | 3853 | #define GPIO_IDR_1 ((uint32_t)0x00000002) |
bogdanm | 86:04dd9b1680ae | 3854 | #define GPIO_IDR_2 ((uint32_t)0x00000004) |
bogdanm | 86:04dd9b1680ae | 3855 | #define GPIO_IDR_3 ((uint32_t)0x00000008) |
bogdanm | 86:04dd9b1680ae | 3856 | #define GPIO_IDR_4 ((uint32_t)0x00000010) |
bogdanm | 86:04dd9b1680ae | 3857 | #define GPIO_IDR_5 ((uint32_t)0x00000020) |
bogdanm | 86:04dd9b1680ae | 3858 | #define GPIO_IDR_6 ((uint32_t)0x00000040) |
bogdanm | 86:04dd9b1680ae | 3859 | #define GPIO_IDR_7 ((uint32_t)0x00000080) |
bogdanm | 86:04dd9b1680ae | 3860 | #define GPIO_IDR_8 ((uint32_t)0x00000100) |
bogdanm | 86:04dd9b1680ae | 3861 | #define GPIO_IDR_9 ((uint32_t)0x00000200) |
bogdanm | 86:04dd9b1680ae | 3862 | #define GPIO_IDR_10 ((uint32_t)0x00000400) |
bogdanm | 86:04dd9b1680ae | 3863 | #define GPIO_IDR_11 ((uint32_t)0x00000800) |
bogdanm | 86:04dd9b1680ae | 3864 | #define GPIO_IDR_12 ((uint32_t)0x00001000) |
bogdanm | 86:04dd9b1680ae | 3865 | #define GPIO_IDR_13 ((uint32_t)0x00002000) |
bogdanm | 86:04dd9b1680ae | 3866 | #define GPIO_IDR_14 ((uint32_t)0x00004000) |
bogdanm | 86:04dd9b1680ae | 3867 | #define GPIO_IDR_15 ((uint32_t)0x00008000) |
bogdanm | 86:04dd9b1680ae | 3868 | |
bogdanm | 86:04dd9b1680ae | 3869 | /****************** Bit definition for GPIO_ODR register ********************/ |
bogdanm | 86:04dd9b1680ae | 3870 | #define GPIO_ODR_0 ((uint32_t)0x00000001) |
bogdanm | 86:04dd9b1680ae | 3871 | #define GPIO_ODR_1 ((uint32_t)0x00000002) |
bogdanm | 86:04dd9b1680ae | 3872 | #define GPIO_ODR_2 ((uint32_t)0x00000004) |
bogdanm | 86:04dd9b1680ae | 3873 | #define GPIO_ODR_3 ((uint32_t)0x00000008) |
bogdanm | 86:04dd9b1680ae | 3874 | #define GPIO_ODR_4 ((uint32_t)0x00000010) |
bogdanm | 86:04dd9b1680ae | 3875 | #define GPIO_ODR_5 ((uint32_t)0x00000020) |
bogdanm | 86:04dd9b1680ae | 3876 | #define GPIO_ODR_6 ((uint32_t)0x00000040) |
bogdanm | 86:04dd9b1680ae | 3877 | #define GPIO_ODR_7 ((uint32_t)0x00000080) |
bogdanm | 86:04dd9b1680ae | 3878 | #define GPIO_ODR_8 ((uint32_t)0x00000100) |
bogdanm | 86:04dd9b1680ae | 3879 | #define GPIO_ODR_9 ((uint32_t)0x00000200) |
bogdanm | 86:04dd9b1680ae | 3880 | #define GPIO_ODR_10 ((uint32_t)0x00000400) |
bogdanm | 86:04dd9b1680ae | 3881 | #define GPIO_ODR_11 ((uint32_t)0x00000800) |
bogdanm | 86:04dd9b1680ae | 3882 | #define GPIO_ODR_12 ((uint32_t)0x00001000) |
bogdanm | 86:04dd9b1680ae | 3883 | #define GPIO_ODR_13 ((uint32_t)0x00002000) |
bogdanm | 86:04dd9b1680ae | 3884 | #define GPIO_ODR_14 ((uint32_t)0x00004000) |
bogdanm | 86:04dd9b1680ae | 3885 | #define GPIO_ODR_15 ((uint32_t)0x00008000) |
bogdanm | 86:04dd9b1680ae | 3886 | |
bogdanm | 86:04dd9b1680ae | 3887 | /****************** Bit definition for GPIO_BSRR register ********************/ |
bogdanm | 86:04dd9b1680ae | 3888 | #define GPIO_BSRR_BS_0 ((uint32_t)0x00000001) |
bogdanm | 86:04dd9b1680ae | 3889 | #define GPIO_BSRR_BS_1 ((uint32_t)0x00000002) |
bogdanm | 86:04dd9b1680ae | 3890 | #define GPIO_BSRR_BS_2 ((uint32_t)0x00000004) |
bogdanm | 86:04dd9b1680ae | 3891 | #define GPIO_BSRR_BS_3 ((uint32_t)0x00000008) |
bogdanm | 86:04dd9b1680ae | 3892 | #define GPIO_BSRR_BS_4 ((uint32_t)0x00000010) |
bogdanm | 86:04dd9b1680ae | 3893 | #define GPIO_BSRR_BS_5 ((uint32_t)0x00000020) |
bogdanm | 86:04dd9b1680ae | 3894 | #define GPIO_BSRR_BS_6 ((uint32_t)0x00000040) |
bogdanm | 86:04dd9b1680ae | 3895 | #define GPIO_BSRR_BS_7 ((uint32_t)0x00000080) |
bogdanm | 86:04dd9b1680ae | 3896 | #define GPIO_BSRR_BS_8 ((uint32_t)0x00000100) |
bogdanm | 86:04dd9b1680ae | 3897 | #define GPIO_BSRR_BS_9 ((uint32_t)0x00000200) |
bogdanm | 86:04dd9b1680ae | 3898 | #define GPIO_BSRR_BS_10 ((uint32_t)0x00000400) |
bogdanm | 86:04dd9b1680ae | 3899 | #define GPIO_BSRR_BS_11 ((uint32_t)0x00000800) |
bogdanm | 86:04dd9b1680ae | 3900 | #define GPIO_BSRR_BS_12 ((uint32_t)0x00001000) |
bogdanm | 86:04dd9b1680ae | 3901 | #define GPIO_BSRR_BS_13 ((uint32_t)0x00002000) |
bogdanm | 86:04dd9b1680ae | 3902 | #define GPIO_BSRR_BS_14 ((uint32_t)0x00004000) |
bogdanm | 86:04dd9b1680ae | 3903 | #define GPIO_BSRR_BS_15 ((uint32_t)0x00008000) |
bogdanm | 86:04dd9b1680ae | 3904 | #define GPIO_BSRR_BR_0 ((uint32_t)0x00010000) |
bogdanm | 86:04dd9b1680ae | 3905 | #define GPIO_BSRR_BR_1 ((uint32_t)0x00020000) |
bogdanm | 86:04dd9b1680ae | 3906 | #define GPIO_BSRR_BR_2 ((uint32_t)0x00040000) |
bogdanm | 86:04dd9b1680ae | 3907 | #define GPIO_BSRR_BR_3 ((uint32_t)0x00080000) |
bogdanm | 86:04dd9b1680ae | 3908 | #define GPIO_BSRR_BR_4 ((uint32_t)0x00100000) |
bogdanm | 86:04dd9b1680ae | 3909 | #define GPIO_BSRR_BR_5 ((uint32_t)0x00200000) |
bogdanm | 86:04dd9b1680ae | 3910 | #define GPIO_BSRR_BR_6 ((uint32_t)0x00400000) |
bogdanm | 86:04dd9b1680ae | 3911 | #define GPIO_BSRR_BR_7 ((uint32_t)0x00800000) |
bogdanm | 86:04dd9b1680ae | 3912 | #define GPIO_BSRR_BR_8 ((uint32_t)0x01000000) |
bogdanm | 86:04dd9b1680ae | 3913 | #define GPIO_BSRR_BR_9 ((uint32_t)0x02000000) |
bogdanm | 86:04dd9b1680ae | 3914 | #define GPIO_BSRR_BR_10 ((uint32_t)0x04000000) |
bogdanm | 86:04dd9b1680ae | 3915 | #define GPIO_BSRR_BR_11 ((uint32_t)0x08000000) |
bogdanm | 86:04dd9b1680ae | 3916 | #define GPIO_BSRR_BR_12 ((uint32_t)0x10000000) |
bogdanm | 86:04dd9b1680ae | 3917 | #define GPIO_BSRR_BR_13 ((uint32_t)0x20000000) |
bogdanm | 86:04dd9b1680ae | 3918 | #define GPIO_BSRR_BR_14 ((uint32_t)0x40000000) |
bogdanm | 86:04dd9b1680ae | 3919 | #define GPIO_BSRR_BR_15 ((uint32_t)0x80000000) |
bogdanm | 86:04dd9b1680ae | 3920 | |
bogdanm | 86:04dd9b1680ae | 3921 | /****************** Bit definition for GPIO_LCKR register ********************/ |
bogdanm | 86:04dd9b1680ae | 3922 | #define GPIO_LCKR_LCK0 ((uint32_t)0x00000001) |
bogdanm | 86:04dd9b1680ae | 3923 | #define GPIO_LCKR_LCK1 ((uint32_t)0x00000002) |
bogdanm | 86:04dd9b1680ae | 3924 | #define GPIO_LCKR_LCK2 ((uint32_t)0x00000004) |
bogdanm | 86:04dd9b1680ae | 3925 | #define GPIO_LCKR_LCK3 ((uint32_t)0x00000008) |
bogdanm | 86:04dd9b1680ae | 3926 | #define GPIO_LCKR_LCK4 ((uint32_t)0x00000010) |
bogdanm | 86:04dd9b1680ae | 3927 | #define GPIO_LCKR_LCK5 ((uint32_t)0x00000020) |
bogdanm | 86:04dd9b1680ae | 3928 | #define GPIO_LCKR_LCK6 ((uint32_t)0x00000040) |
bogdanm | 86:04dd9b1680ae | 3929 | #define GPIO_LCKR_LCK7 ((uint32_t)0x00000080) |
bogdanm | 86:04dd9b1680ae | 3930 | #define GPIO_LCKR_LCK8 ((uint32_t)0x00000100) |
bogdanm | 86:04dd9b1680ae | 3931 | #define GPIO_LCKR_LCK9 ((uint32_t)0x00000200) |
bogdanm | 86:04dd9b1680ae | 3932 | #define GPIO_LCKR_LCK10 ((uint32_t)0x00000400) |
bogdanm | 86:04dd9b1680ae | 3933 | #define GPIO_LCKR_LCK11 ((uint32_t)0x00000800) |
bogdanm | 86:04dd9b1680ae | 3934 | #define GPIO_LCKR_LCK12 ((uint32_t)0x00001000) |
bogdanm | 86:04dd9b1680ae | 3935 | #define GPIO_LCKR_LCK13 ((uint32_t)0x00002000) |
bogdanm | 86:04dd9b1680ae | 3936 | #define GPIO_LCKR_LCK14 ((uint32_t)0x00004000) |
bogdanm | 86:04dd9b1680ae | 3937 | #define GPIO_LCKR_LCK15 ((uint32_t)0x00008000) |
bogdanm | 86:04dd9b1680ae | 3938 | #define GPIO_LCKR_LCKK ((uint32_t)0x00010000) |
bogdanm | 86:04dd9b1680ae | 3939 | |
bogdanm | 86:04dd9b1680ae | 3940 | /****************** Bit definition for GPIO_AFRL register ********************/ |
bogdanm | 86:04dd9b1680ae | 3941 | #define GPIO_AFRL_AFRL0 ((uint32_t)0x0000000F) |
bogdanm | 86:04dd9b1680ae | 3942 | #define GPIO_AFRL_AFRL1 ((uint32_t)0x000000F0) |
bogdanm | 86:04dd9b1680ae | 3943 | #define GPIO_AFRL_AFRL2 ((uint32_t)0x00000F00) |
bogdanm | 86:04dd9b1680ae | 3944 | #define GPIO_AFRL_AFRL3 ((uint32_t)0x0000F000) |
bogdanm | 86:04dd9b1680ae | 3945 | #define GPIO_AFRL_AFRL4 ((uint32_t)0x000F0000) |
bogdanm | 86:04dd9b1680ae | 3946 | #define GPIO_AFRL_AFRL5 ((uint32_t)0x00F00000) |
bogdanm | 86:04dd9b1680ae | 3947 | #define GPIO_AFRL_AFRL6 ((uint32_t)0x0F000000) |
bogdanm | 86:04dd9b1680ae | 3948 | #define GPIO_AFRL_AFRL7 ((uint32_t)0xF0000000) |
bogdanm | 86:04dd9b1680ae | 3949 | |
bogdanm | 86:04dd9b1680ae | 3950 | /****************** Bit definition for GPIO_AFRH register ********************/ |
bogdanm | 86:04dd9b1680ae | 3951 | #define GPIO_AFRH_AFRH0 ((uint32_t)0x0000000F) |
bogdanm | 86:04dd9b1680ae | 3952 | #define GPIO_AFRH_AFRH1 ((uint32_t)0x000000F0) |
bogdanm | 86:04dd9b1680ae | 3953 | #define GPIO_AFRH_AFRH2 ((uint32_t)0x00000F00) |
bogdanm | 86:04dd9b1680ae | 3954 | #define GPIO_AFRH_AFRH3 ((uint32_t)0x0000F000) |
bogdanm | 86:04dd9b1680ae | 3955 | #define GPIO_AFRH_AFRH4 ((uint32_t)0x000F0000) |
bogdanm | 86:04dd9b1680ae | 3956 | #define GPIO_AFRH_AFRH5 ((uint32_t)0x00F00000) |
bogdanm | 86:04dd9b1680ae | 3957 | #define GPIO_AFRH_AFRH6 ((uint32_t)0x0F000000) |
bogdanm | 86:04dd9b1680ae | 3958 | #define GPIO_AFRH_AFRH7 ((uint32_t)0xF0000000) |
bogdanm | 86:04dd9b1680ae | 3959 | |
bogdanm | 86:04dd9b1680ae | 3960 | /****************** Bit definition for GPIO_BRR register *********************/ |
bogdanm | 86:04dd9b1680ae | 3961 | #define GPIO_BRR_BR_0 ((uint32_t)0x00000001) |
bogdanm | 86:04dd9b1680ae | 3962 | #define GPIO_BRR_BR_1 ((uint32_t)0x00000002) |
bogdanm | 86:04dd9b1680ae | 3963 | #define GPIO_BRR_BR_2 ((uint32_t)0x00000004) |
bogdanm | 86:04dd9b1680ae | 3964 | #define GPIO_BRR_BR_3 ((uint32_t)0x00000008) |
bogdanm | 86:04dd9b1680ae | 3965 | #define GPIO_BRR_BR_4 ((uint32_t)0x00000010) |
bogdanm | 86:04dd9b1680ae | 3966 | #define GPIO_BRR_BR_5 ((uint32_t)0x00000020) |
bogdanm | 86:04dd9b1680ae | 3967 | #define GPIO_BRR_BR_6 ((uint32_t)0x00000040) |
bogdanm | 86:04dd9b1680ae | 3968 | #define GPIO_BRR_BR_7 ((uint32_t)0x00000080) |
bogdanm | 86:04dd9b1680ae | 3969 | #define GPIO_BRR_BR_8 ((uint32_t)0x00000100) |
bogdanm | 86:04dd9b1680ae | 3970 | #define GPIO_BRR_BR_9 ((uint32_t)0x00000200) |
bogdanm | 86:04dd9b1680ae | 3971 | #define GPIO_BRR_BR_10 ((uint32_t)0x00000400) |
bogdanm | 86:04dd9b1680ae | 3972 | #define GPIO_BRR_BR_11 ((uint32_t)0x00000800) |
bogdanm | 86:04dd9b1680ae | 3973 | #define GPIO_BRR_BR_12 ((uint32_t)0x00001000) |
bogdanm | 86:04dd9b1680ae | 3974 | #define GPIO_BRR_BR_13 ((uint32_t)0x00002000) |
bogdanm | 86:04dd9b1680ae | 3975 | #define GPIO_BRR_BR_14 ((uint32_t)0x00004000) |
bogdanm | 86:04dd9b1680ae | 3976 | #define GPIO_BRR_BR_15 ((uint32_t)0x00008000) |
bogdanm | 86:04dd9b1680ae | 3977 | |
bogdanm | 86:04dd9b1680ae | 3978 | /******************************************************************************/ |
bogdanm | 86:04dd9b1680ae | 3979 | /* */ |
bogdanm | 86:04dd9b1680ae | 3980 | /* High Resolution Timer (HRTIM) */ |
bogdanm | 86:04dd9b1680ae | 3981 | /* */ |
bogdanm | 86:04dd9b1680ae | 3982 | /******************************************************************************/ |
bogdanm | 86:04dd9b1680ae | 3983 | /******************** Master Timer control register ***************************/ |
bogdanm | 86:04dd9b1680ae | 3984 | #define HRTIM_MCR_CK_PSC ((uint32_t)0x00000007) /*!< Prescaler mask */ |
bogdanm | 86:04dd9b1680ae | 3985 | #define HRTIM_MCR_CK_PSC_0 ((uint32_t)0x00000001) /*!< Prescaler bit 0 */ |
bogdanm | 86:04dd9b1680ae | 3986 | #define HRTIM_MCR_CK_PSC_1 ((uint32_t)0x00000002) /*!< Prescaler bit 1 */ |
bogdanm | 86:04dd9b1680ae | 3987 | #define HRTIM_MCR_CK_PSC_2 ((uint32_t)0x00000004) /*!< Prescaler bit 2 */ |
bogdanm | 86:04dd9b1680ae | 3988 | |
bogdanm | 86:04dd9b1680ae | 3989 | #define HRTIM_MCR_CONT ((uint32_t)0x00000008) /*!< Continuous mode */ |
bogdanm | 86:04dd9b1680ae | 3990 | #define HRTIM_MCR_RETRIG ((uint32_t)0x00000010) /*!< Rettrigreable mode */ |
bogdanm | 86:04dd9b1680ae | 3991 | #define HRTIM_MCR_HALF ((uint32_t)0x00000020) /*!< Half mode */ |
bogdanm | 86:04dd9b1680ae | 3992 | |
bogdanm | 86:04dd9b1680ae | 3993 | #define HRTIM_MCR_SYNC_IN ((uint32_t)0x00000300) /*!< Synchronization input master */ |
bogdanm | 86:04dd9b1680ae | 3994 | #define HRTIM_MCR_SYNC_IN_0 ((uint32_t)0x00000100) /*!< Synchronization input bit 0 */ |
bogdanm | 86:04dd9b1680ae | 3995 | #define HRTIM_MCR_SYNC_IN_1 ((uint32_t)0x00000200) /*!< Synchronization input bit 1 */ |
bogdanm | 86:04dd9b1680ae | 3996 | #define HRTIM_MCR_SYNCRSTM ((uint32_t)0x00000400) /*!< Synchronization reset master */ |
bogdanm | 86:04dd9b1680ae | 3997 | #define HRTIM_MCR_SYNCSTRTM ((uint32_t)0x00000800) /*!< Synchronization start master */ |
bogdanm | 86:04dd9b1680ae | 3998 | #define HRTIM_MCR_SYNC_OUT ((uint32_t)0x00003000) /*!< Synchronization output master */ |
bogdanm | 86:04dd9b1680ae | 3999 | #define HRTIM_MCR_SYNC_OUT_0 ((uint32_t)0x00001000) /*!< Synchronization output bit 0 */ |
bogdanm | 86:04dd9b1680ae | 4000 | #define HRTIM_MCR_SYNC_OUT_1 ((uint32_t)0x00002000) /*!< Synchronization output bit 1 */ |
bogdanm | 86:04dd9b1680ae | 4001 | #define HRTIM_MCR_SYNC_SRC ((uint32_t)0x0000C000) /*!< Synchronization source */ |
bogdanm | 86:04dd9b1680ae | 4002 | #define HRTIM_MCR_SYNC_SRC_0 ((uint32_t)0x00004000) /*!< Synchronization source bit 0 */ |
bogdanm | 86:04dd9b1680ae | 4003 | #define HRTIM_MCR_SYNC_SRC_1 ((uint32_t)0x00008000) /*!< Synchronization source bit 1 */ |
bogdanm | 86:04dd9b1680ae | 4004 | |
bogdanm | 86:04dd9b1680ae | 4005 | #define HRTIM_MCR_MCEN ((uint32_t)0x00010000) /*!< Master counter enable */ |
bogdanm | 86:04dd9b1680ae | 4006 | #define HRTIM_MCR_TACEN ((uint32_t)0x00020000) /*!< Timer A counter enable */ |
bogdanm | 86:04dd9b1680ae | 4007 | #define HRTIM_MCR_TBCEN ((uint32_t)0x00040000) /*!< Timer B counter enable */ |
bogdanm | 86:04dd9b1680ae | 4008 | #define HRTIM_MCR_TCCEN ((uint32_t)0x00080000) /*!< Timer C counter enable */ |
bogdanm | 86:04dd9b1680ae | 4009 | #define HRTIM_MCR_TDCEN ((uint32_t)0x00100000) /*!< Timer D counter enable */ |
bogdanm | 86:04dd9b1680ae | 4010 | #define HRTIM_MCR_TECEN ((uint32_t)0x00200000) /*!< Timer E counter enable */ |
bogdanm | 86:04dd9b1680ae | 4011 | |
bogdanm | 86:04dd9b1680ae | 4012 | #define HRTIM_MCR_DACSYNC ((uint32_t)0x06000000) /*!< DAC sychronization mask */ |
bogdanm | 86:04dd9b1680ae | 4013 | #define HRTIM_MCR_DACSYNC_0 ((uint32_t)0x02000000) /*!< DAC sychronization bit 0 */ |
bogdanm | 86:04dd9b1680ae | 4014 | #define HRTIM_MCR_DACSYNC_1 ((uint32_t)0x04000000) /*!< DAC sychronization bit 1 */ |
bogdanm | 86:04dd9b1680ae | 4015 | |
bogdanm | 86:04dd9b1680ae | 4016 | #define HRTIM_MCR_PREEN ((uint32_t)0x08000000) /*!< Master preload enable */ |
bogdanm | 86:04dd9b1680ae | 4017 | #define HRTIM_MCR_MREPU ((uint32_t)0x20000000) /*!< Master repetition update */ |
bogdanm | 86:04dd9b1680ae | 4018 | |
bogdanm | 86:04dd9b1680ae | 4019 | #define HRTIM_MCR_BRSTDMA ((uint32_t)0xC0000000) /*!< Burst DMA update */ |
bogdanm | 86:04dd9b1680ae | 4020 | #define HRTIM_MCR_BRSTDMA_0 ((uint32_t)0x40000000) /*!< Burst DMA update bit 0*/ |
bogdanm | 86:04dd9b1680ae | 4021 | #define HRTIM_MCR_BRSTDMA_1 ((uint32_t)0x80000000) /*!< Burst DMA update bit 1 */ |
bogdanm | 86:04dd9b1680ae | 4022 | |
bogdanm | 86:04dd9b1680ae | 4023 | /******************** Master Timer Interrupt status register ******************/ |
bogdanm | 86:04dd9b1680ae | 4024 | #define HRTIM_MISR_MCMP1 ((uint32_t)0x00000001) /*!< Master compare 1 interrupt flag */ |
bogdanm | 86:04dd9b1680ae | 4025 | #define HRTIM_MISR_MCMP2 ((uint32_t)0x00000002) /*!< Master compare 2 interrupt flag */ |
bogdanm | 86:04dd9b1680ae | 4026 | #define HRTIM_MISR_MCMP3 ((uint32_t)0x00000004) /*!< Master compare 3 interrupt flag */ |
bogdanm | 86:04dd9b1680ae | 4027 | #define HRTIM_MISR_MCMP4 ((uint32_t)0x00000008) /*!< Master compare 4 interrupt flag */ |
bogdanm | 86:04dd9b1680ae | 4028 | #define HRTIM_MISR_MREP ((uint32_t)0x00000010) /*!< Master Repetition interrupt flag */ |
bogdanm | 86:04dd9b1680ae | 4029 | #define HRTIM_MISR_SYNC ((uint32_t)0x00000020) /*!< Synchronization input interrupt flag */ |
bogdanm | 86:04dd9b1680ae | 4030 | #define HRTIM_MISR_MUPD ((uint32_t)0x00000040) /*!< Master update interrupt flag */ |
bogdanm | 86:04dd9b1680ae | 4031 | |
bogdanm | 86:04dd9b1680ae | 4032 | /******************** Master Timer Interrupt clear register *******************/ |
bogdanm | 86:04dd9b1680ae | 4033 | #define HRTIM_MICR_MCMP1 ((uint32_t)0x00000001) /*!< Master compare 1 interrupt flag clear */ |
bogdanm | 86:04dd9b1680ae | 4034 | #define HRTIM_MICR_MCMP2 ((uint32_t)0x00000002) /*!< Master compare 2 interrupt flag clear */ |
bogdanm | 86:04dd9b1680ae | 4035 | #define HRTIM_MICR_MCMP3 ((uint32_t)0x00000004) /*!< Master compare 3 interrupt flag clear */ |
bogdanm | 86:04dd9b1680ae | 4036 | #define HRTIM_MICR_MCMP4 ((uint32_t)0x00000008) /*!< Master compare 4 interrupt flag clear */ |
bogdanm | 86:04dd9b1680ae | 4037 | #define HRTIM_MICR_MREP ((uint32_t)0x00000010) /*!< Master Repetition interrupt flag clear */ |
bogdanm | 86:04dd9b1680ae | 4038 | #define HRTIM_MICR_SYNC ((uint32_t)0x00000020) /*!< Synchronization input interrupt flag clear */ |
bogdanm | 86:04dd9b1680ae | 4039 | #define HRTIM_MICR_MUPD ((uint32_t)0x00000040) /*!< Master update interrupt flag clear */ |
bogdanm | 86:04dd9b1680ae | 4040 | |
bogdanm | 86:04dd9b1680ae | 4041 | /******************** Master Timer DMA/Interrupt enable register **************/ |
bogdanm | 86:04dd9b1680ae | 4042 | #define HRTIM_MDIER_MCMP1IE ((uint32_t)0x00000001) /*!< Master compare 1 interrupt enable */ |
bogdanm | 86:04dd9b1680ae | 4043 | #define HRTIM_MDIER_MCMP2IE ((uint32_t)0x00000002) /*!< Master compare 2 interrupt enable */ |
bogdanm | 86:04dd9b1680ae | 4044 | #define HRTIM_MDIER_MCMP3IE ((uint32_t)0x00000004) /*!< Master compare 3 interrupt enable */ |
bogdanm | 86:04dd9b1680ae | 4045 | #define HRTIM_MDIER_MCMP4IE ((uint32_t)0x00000008) /*!< Master compare 4 interrupt enable */ |
bogdanm | 86:04dd9b1680ae | 4046 | #define HRTIM_MDIER_MREPIE ((uint32_t)0x00000010) /*!< Master Repetition interrupt enable */ |
bogdanm | 86:04dd9b1680ae | 4047 | #define HRTIM_MDIER_SYNCIE ((uint32_t)0x00000020) /*!< Synchronization input interrupt enable */ |
bogdanm | 86:04dd9b1680ae | 4048 | #define HRTIM_MDIER_MUPDIE ((uint32_t)0x00000040) /*!< Master update interrupt enable */ |
bogdanm | 86:04dd9b1680ae | 4049 | |
bogdanm | 86:04dd9b1680ae | 4050 | #define HRTIM_MDIER_MCMP1DE ((uint32_t)0x00010000) /*!< Master compare 1 DMA enable */ |
bogdanm | 86:04dd9b1680ae | 4051 | #define HRTIM_MDIER_MCMP2DE ((uint32_t)0x00020000) /*!< Master compare 2 DMA enable */ |
bogdanm | 86:04dd9b1680ae | 4052 | #define HRTIM_MDIER_MCMP3DE ((uint32_t)0x00040000) /*!< Master compare 3 DMA enable */ |
bogdanm | 86:04dd9b1680ae | 4053 | #define HRTIM_MDIER_MCMP4DE ((uint32_t)0x00080000) /*!< Master compare 4 DMA enable */ |
bogdanm | 86:04dd9b1680ae | 4054 | #define HRTIM_MDIER_MREPDE ((uint32_t)0x00100000) /*!< Master Repetition DMA enable */ |
bogdanm | 86:04dd9b1680ae | 4055 | #define HRTIM_MDIER_SYNCDE ((uint32_t)0x00200000) /*!< Synchronization input DMA enable */ |
bogdanm | 86:04dd9b1680ae | 4056 | #define HRTIM_MDIER_MUPDDE ((uint32_t)0x00400000) /*!< Master update DMA enable */ |
bogdanm | 86:04dd9b1680ae | 4057 | |
bogdanm | 86:04dd9b1680ae | 4058 | /******************* Bit definition for HRTIM_MCNTR register ****************/ |
bogdanm | 86:04dd9b1680ae | 4059 | #define HRTIM_MCNTR_MCNTR ((uint32_t)0xFFFFFFFF) /*!<Counter Value */ |
bogdanm | 86:04dd9b1680ae | 4060 | |
bogdanm | 86:04dd9b1680ae | 4061 | /******************* Bit definition for HRTIM_MPER register *****************/ |
bogdanm | 86:04dd9b1680ae | 4062 | #define HRTIM_MPER_MPER ((uint32_t)0xFFFFFFFF) /*!< Period Value */ |
bogdanm | 86:04dd9b1680ae | 4063 | |
bogdanm | 86:04dd9b1680ae | 4064 | /******************* Bit definition for HRTIM_MREP register *****************/ |
bogdanm | 86:04dd9b1680ae | 4065 | #define HRTIM_MREP_MREP ((uint32_t)0xFFFFFFFF) /*!<Repetition Value */ |
bogdanm | 86:04dd9b1680ae | 4066 | |
bogdanm | 86:04dd9b1680ae | 4067 | /******************* Bit definition for HRTIM_MCMP1R register *****************/ |
bogdanm | 86:04dd9b1680ae | 4068 | #define HRTIM_MCMP1R_MCMP1R ((uint32_t)0xFFFFFFFF) /*!<Compare Value */ |
bogdanm | 86:04dd9b1680ae | 4069 | |
bogdanm | 86:04dd9b1680ae | 4070 | /******************* Bit definition for HRTIM_MCMP2R register *****************/ |
bogdanm | 86:04dd9b1680ae | 4071 | #define HRTIM_MCMP1R_MCMP2R ((uint32_t)0xFFFFFFFF) /*!<Compare Value */ |
bogdanm | 86:04dd9b1680ae | 4072 | |
bogdanm | 86:04dd9b1680ae | 4073 | /******************* Bit definition for HRTIM_MCMP3R register *****************/ |
bogdanm | 86:04dd9b1680ae | 4074 | #define HRTIM_MCMP1R_MCMP3R ((uint32_t)0xFFFFFFFF) /*!<Compare Value */ |
bogdanm | 86:04dd9b1680ae | 4075 | |
bogdanm | 86:04dd9b1680ae | 4076 | /******************* Bit definition for HRTIM_MCMP4R register *****************/ |
bogdanm | 86:04dd9b1680ae | 4077 | #define HRTIM_MCMP1R_MCMP4R ((uint32_t)0xFFFFFFFF) /*!<Compare Value */ |
bogdanm | 86:04dd9b1680ae | 4078 | |
bogdanm | 86:04dd9b1680ae | 4079 | /******************** Slave control register **********************************/ |
bogdanm | 86:04dd9b1680ae | 4080 | #define HRTIM_TIMCR_CK_PSC ((uint32_t)0x00000007) /*!< Slave prescaler mask*/ |
bogdanm | 86:04dd9b1680ae | 4081 | #define HRTIM_TIMCR_CK_PSC_0 ((uint32_t)0x00000001) /*!< prescaler bit 0 */ |
bogdanm | 86:04dd9b1680ae | 4082 | #define HRTIM_TIMCR_CK_PSC_1 ((uint32_t)0x00000002) /*!< prescaler bit 1 */ |
bogdanm | 86:04dd9b1680ae | 4083 | #define HRTIM_TIMCR_CK_PSC_2 ((uint32_t)0x00000004) /*!< prescaler bit 2 */ |
bogdanm | 86:04dd9b1680ae | 4084 | |
bogdanm | 86:04dd9b1680ae | 4085 | #define HRTIM_TIMCR_CONT ((uint32_t)0x00000008) /*!< Slave continuous mode */ |
bogdanm | 86:04dd9b1680ae | 4086 | #define HRTIM_TIMCR_RETRIG ((uint32_t)0x00000010) /*!< Slave Retrigreable mode */ |
bogdanm | 86:04dd9b1680ae | 4087 | #define HRTIM_TIMCR_HALF ((uint32_t)0x00000020) /*!< Slave Half mode */ |
bogdanm | 86:04dd9b1680ae | 4088 | #define HRTIM_TIMCR_PSHPLL ((uint32_t)0x00000040) /*!< Slave push-pull mode */ |
bogdanm | 86:04dd9b1680ae | 4089 | |
bogdanm | 86:04dd9b1680ae | 4090 | #define HRTIM_TIMCR_SYNCRST ((uint32_t)0x00000400) /*!< Slave synchronization resets */ |
bogdanm | 86:04dd9b1680ae | 4091 | #define HRTIM_TIMCR_SYNCSTRT ((uint32_t)0x00000800) /*!< Slave synchronization starts */ |
bogdanm | 86:04dd9b1680ae | 4092 | |
bogdanm | 86:04dd9b1680ae | 4093 | #define HRTIM_TIMCR_DELCMP2 ((uint32_t)0x00003000) /*!< Slave delayed compartor 2 mode mask */ |
bogdanm | 86:04dd9b1680ae | 4094 | #define HRTIM_TIMCR_DELCMP2_0 ((uint32_t)0x00001000) /*!< Slave delayed compartor 2 bit 0 */ |
bogdanm | 86:04dd9b1680ae | 4095 | #define HRTIM_TIMCR_DELCMP2_1 ((uint32_t)0x00002000) /*!< Slave delayed compartor 2 bit 1 */ |
bogdanm | 86:04dd9b1680ae | 4096 | #define HRTIM_TIMCR_DELCMP4 ((uint32_t)0x0000C000) /*!< Slave delayed compartor 4 mode mask */ |
bogdanm | 86:04dd9b1680ae | 4097 | #define HRTIM_TIMCR_DELCMP4_0 ((uint32_t)0x00004000) /*!< Slave delayed compartor 4 bit 0 */ |
bogdanm | 86:04dd9b1680ae | 4098 | #define HRTIM_TIMCR_DELCMP4_1 ((uint32_t)0x00008000) /*!< Slave delayed compartor 4 bit 1 */ |
bogdanm | 86:04dd9b1680ae | 4099 | |
bogdanm | 86:04dd9b1680ae | 4100 | #define HRTIM_TIMCR_TREPU ((uint32_t)0x00020000) /*!< Slave repetition update */ |
bogdanm | 86:04dd9b1680ae | 4101 | #define HRTIM_TIMCR_TRSTU ((uint32_t)0x00040000) /*!< Slave reset update */ |
bogdanm | 86:04dd9b1680ae | 4102 | #define HRTIM_TIMCR_TAU ((uint32_t)0x00080000) /*!< Slave Timer A update reserved for TIM A */ |
bogdanm | 86:04dd9b1680ae | 4103 | #define HRTIM_TIMCR_TBU ((uint32_t)0x00100000) /*!< Slave Timer B update reserved for TIM B */ |
bogdanm | 86:04dd9b1680ae | 4104 | #define HRTIM_TIMCR_TCU ((uint32_t)0x00200000) /*!< Slave Timer C update reserved for TIM C */ |
bogdanm | 86:04dd9b1680ae | 4105 | #define HRTIM_TIMCR_TDU ((uint32_t)0x00400000) /*!< Slave Timer D update reserved for TIM D */ |
bogdanm | 86:04dd9b1680ae | 4106 | #define HRTIM_TIMCR_TEU ((uint32_t)0x00800000) /*!< Slave Timer E update reserved for TIM E */ |
bogdanm | 86:04dd9b1680ae | 4107 | #define HRTIM_TIMCR_MSTU ((uint32_t)0x01000000) /*!< Master Update */ |
bogdanm | 86:04dd9b1680ae | 4108 | |
bogdanm | 86:04dd9b1680ae | 4109 | #define HRTIM_TIMCR_DACSYNC ((uint32_t)0x06000000) /*!< DAC sychronization mask */ |
bogdanm | 86:04dd9b1680ae | 4110 | #define HRTIM_TIMCR_DACSYNC_0 ((uint32_t)0x02000000) /*!< DAC sychronization bit 0 */ |
bogdanm | 86:04dd9b1680ae | 4111 | #define HRTIM_TIMCR_DACSYNC_1 ((uint32_t)0x04000000) /*!< DAC sychronization bit 1 */ |
bogdanm | 86:04dd9b1680ae | 4112 | #define HRTIM_TIMCR_PREEN ((uint32_t)0x08000000) /*!< Slave preload enable */ |
bogdanm | 86:04dd9b1680ae | 4113 | |
bogdanm | 86:04dd9b1680ae | 4114 | #define HRTIM_TIMCR_UPDGAT ((uint32_t)0xF0000000) /*!< Slave update gating mask */ |
bogdanm | 86:04dd9b1680ae | 4115 | #define HRTIM_TIMCR_UPDGAT_0 ((uint32_t)0x10000000) /*!< Update gating bit 0 */ |
bogdanm | 86:04dd9b1680ae | 4116 | #define HRTIM_TIMCR_UPDGAT_1 ((uint32_t)0x20000000) /*!< Update gating bit 1 */ |
bogdanm | 86:04dd9b1680ae | 4117 | #define HRTIM_TIMCR_UPDGAT_2 ((uint32_t)0x40000000) /*!< Update gating bit 2 */ |
bogdanm | 86:04dd9b1680ae | 4118 | #define HRTIM_TIMCR_UPDGAT_3 ((uint32_t)0x80000000) /*!< Update gating bit 3 */ |
bogdanm | 86:04dd9b1680ae | 4119 | |
bogdanm | 86:04dd9b1680ae | 4120 | /******************** Slave Interrupt status register **************************/ |
bogdanm | 86:04dd9b1680ae | 4121 | #define HRTIM_TIMISR_CMP1 ((uint32_t)0x00000001) /*!< Slave compare 1 interrupt flag */ |
bogdanm | 86:04dd9b1680ae | 4122 | #define HRTIM_TIMISR_CMP2 ((uint32_t)0x00000002) /*!< Slave compare 2 interrupt flag */ |
bogdanm | 86:04dd9b1680ae | 4123 | #define HRTIM_TIMISR_CMP3 ((uint32_t)0x00000004) /*!< Slave compare 3 interrupt flag */ |
bogdanm | 86:04dd9b1680ae | 4124 | #define HRTIM_TIMISR_CMP4 ((uint32_t)0x00000008) /*!< Slave compare 4 interrupt flag */ |
bogdanm | 86:04dd9b1680ae | 4125 | #define HRTIM_TIMISR_REP ((uint32_t)0x00000010) /*!< Slave repetition interrupt flag */ |
bogdanm | 86:04dd9b1680ae | 4126 | #define HRTIM_TIMISR_UPD ((uint32_t)0x00000040) /*!< Slave update interrupt flag */ |
bogdanm | 86:04dd9b1680ae | 4127 | #define HRTIM_TIMISR_CPT1 ((uint32_t)0x00000080) /*!< Slave capture 1 interrupt flag */ |
bogdanm | 86:04dd9b1680ae | 4128 | #define HRTIM_TIMISR_CPT2 ((uint32_t)0x00000100) /*!< Slave capture 2 interrupt flag */ |
bogdanm | 86:04dd9b1680ae | 4129 | #define HRTIM_TIMISR_SET1 ((uint32_t)0x00000200) /*!< Slave output 1 set interrupt flag */ |
bogdanm | 86:04dd9b1680ae | 4130 | #define HRTIM_TIMISR_RST1 ((uint32_t)0x00000400) /*!< Slave output 1 reset interrupt flag */ |
bogdanm | 86:04dd9b1680ae | 4131 | #define HRTIM_TIMISR_SET2 ((uint32_t)0x00000800) /*!< Slave output 2 set interrupt flag */ |
bogdanm | 86:04dd9b1680ae | 4132 | #define HRTIM_TIMISR_RST2 ((uint32_t)0x00001000) /*!< Slave output 2 reset interrupt flag */ |
bogdanm | 86:04dd9b1680ae | 4133 | #define HRTIM_TIMISR_RST ((uint32_t)0x00002000) /*!< Slave reset interrupt flag */ |
bogdanm | 86:04dd9b1680ae | 4134 | #define HRTIM_TIMISR_DLYPRT ((uint32_t)0x00004000) /*!< Slave output 1 delay protection interrupt flag */ |
bogdanm | 86:04dd9b1680ae | 4135 | #define HRTIM_TIMISR_CPPSTAT ((uint32_t)0x00010000) /*!< Slave current push-pull flag */ |
bogdanm | 86:04dd9b1680ae | 4136 | #define HRTIM_TIMISR_IPPSTAT ((uint32_t)0x00020000) /*!< Slave idle push-pull flag */ |
bogdanm | 86:04dd9b1680ae | 4137 | #define HRTIM_TIMISR_O1STAT ((uint32_t)0x00040000) /*!< Slave output 1 state flag */ |
bogdanm | 86:04dd9b1680ae | 4138 | #define HRTIM_TIMISR_O2STAT ((uint32_t)0x00080000) /*!< Slave output 2 state flag */ |
bogdanm | 86:04dd9b1680ae | 4139 | #define HRTIM_TIMISR_O1CPY ((uint32_t)0x00100000) /*!< Slave output 1 copy flag */ |
bogdanm | 86:04dd9b1680ae | 4140 | #define HRTIM_TIMISR_O2CPY ((uint32_t)0x00200000) /*!< Slave output 2 copy flag */ |
bogdanm | 86:04dd9b1680ae | 4141 | |
bogdanm | 86:04dd9b1680ae | 4142 | /******************** Slave Interrupt clear register **************************/ |
bogdanm | 86:04dd9b1680ae | 4143 | #define HRTIM_TIMICR_CMP1C ((uint32_t)0x00000001) /*!< Slave compare 1 clear flag */ |
bogdanm | 86:04dd9b1680ae | 4144 | #define HRTIM_TIMICR_CMP2C ((uint32_t)0x00000002) /*!< Slave compare 2 clear flag */ |
bogdanm | 86:04dd9b1680ae | 4145 | #define HRTIM_TIMICR_CMP3C ((uint32_t)0x00000004) /*!< Slave compare 3 clear flag */ |
bogdanm | 86:04dd9b1680ae | 4146 | #define HRTIM_TIMICR_CMP4C ((uint32_t)0x00000008) /*!< Slave compare 4 clear flag */ |
bogdanm | 86:04dd9b1680ae | 4147 | #define HRTIM_TIMICR_REPC ((uint32_t)0x00000010) /*!< Slave repetition clear flag */ |
bogdanm | 86:04dd9b1680ae | 4148 | #define HRTIM_TIMICR_UPDC ((uint32_t)0x00000040) /*!< Slave update clear flag */ |
bogdanm | 86:04dd9b1680ae | 4149 | #define HRTIM_TIMICR_CPT1C ((uint32_t)0x00000080) /*!< Slave capture 1 clear flag */ |
bogdanm | 86:04dd9b1680ae | 4150 | #define HRTIM_TIMICR_CPT2C ((uint32_t)0x00000100) /*!< Slave capture 2 clear flag */ |
bogdanm | 86:04dd9b1680ae | 4151 | #define HRTIM_TIMICR_SET1C ((uint32_t)0x00000200) /*!< Slave output 1 set clear flag */ |
bogdanm | 86:04dd9b1680ae | 4152 | #define HRTIM_TIMICR_RST1C ((uint32_t)0x00000400) /*!< Slave output 1 reset clear flag */ |
bogdanm | 86:04dd9b1680ae | 4153 | #define HRTIM_TIMICR_SET2C ((uint32_t)0x00000800) /*!< Slave output 2 set clear flag */ |
bogdanm | 86:04dd9b1680ae | 4154 | #define HRTIM_TIMICR_RST2C ((uint32_t)0x00001000) /*!< Slave output 2 reset clear flag */ |
bogdanm | 86:04dd9b1680ae | 4155 | #define HRTIM_TIMICR_RSTC ((uint32_t)0x00002000) /*!< Slave reset clear flag */ |
bogdanm | 86:04dd9b1680ae | 4156 | #define HRTIM_TIMICR_DLYPRT1C ((uint32_t)0x00004000) /*!< Slave output 1 delay protection clear flag */ |
bogdanm | 86:04dd9b1680ae | 4157 | #define HRTIM_TIMICR_DLYPRT2C ((uint32_t)0x00008000) /*!< Slave output 2 delay protection clear flag */ |
bogdanm | 86:04dd9b1680ae | 4158 | |
bogdanm | 86:04dd9b1680ae | 4159 | /******************** Slave DMA/Interrupt enable register *********************/ |
bogdanm | 86:04dd9b1680ae | 4160 | #define HRTIM_TIMDIER_CMP1IE ((uint32_t)0x00000001) /*!< Slave compare 1 interrupt enable */ |
bogdanm | 86:04dd9b1680ae | 4161 | #define HRTIM_TIMDIER_CMP2IE ((uint32_t)0x00000002) /*!< Slave compare 2 interrupt enable */ |
bogdanm | 86:04dd9b1680ae | 4162 | #define HRTIM_TIMDIER_CMP3IE ((uint32_t)0x00000004) /*!< Slave compare 3 interrupt enable */ |
bogdanm | 86:04dd9b1680ae | 4163 | #define HRTIM_TIMDIER_CMP4IE ((uint32_t)0x00000008) /*!< Slave compare 4 interrupt enable */ |
bogdanm | 86:04dd9b1680ae | 4164 | #define HRTIM_TIMDIER_REPIE ((uint32_t)0x00000010) /*!< Slave repetition interrupt enable */ |
bogdanm | 86:04dd9b1680ae | 4165 | #define HRTIM_TIMDIER_UPDIE ((uint32_t)0x00000040) /*!< Slave update interrupt enable */ |
bogdanm | 86:04dd9b1680ae | 4166 | #define HRTIM_TIMDIER_CPT1IE ((uint32_t)0x00000080) /*!< Slave capture 1 interrupt enable */ |
bogdanm | 86:04dd9b1680ae | 4167 | #define HRTIM_TIMDIER_CPT2IE ((uint32_t)0x00000100) /*!< Slave capture 2 interrupt enable */ |
bogdanm | 86:04dd9b1680ae | 4168 | #define HRTIM_TIMDIER_SET1IE ((uint32_t)0x00000200) /*!< Slave output 1 set interrupt enable */ |
bogdanm | 86:04dd9b1680ae | 4169 | #define HRTIM_TIMDIER_RST1IE ((uint32_t)0x00000400) /*!< Slave output 1 reset interrupt enable */ |
bogdanm | 86:04dd9b1680ae | 4170 | #define HRTIM_TIMDIER_SET2IE ((uint32_t)0x00000800) /*!< Slave output 2 set interrupt enable */ |
bogdanm | 86:04dd9b1680ae | 4171 | #define HRTIM_TIMDIER_RST2IE ((uint32_t)0x00001000) /*!< Slave output 2 reset interrupt enable */ |
bogdanm | 86:04dd9b1680ae | 4172 | #define HRTIM_TIMDIER_RSTIE ((uint32_t)0x00002000) /*!< Slave reset interrupt enable */ |
bogdanm | 86:04dd9b1680ae | 4173 | #define HRTIM_TIMDIER_DLYPRTIE ((uint32_t)0x00004000) /*!< Slave delay protection interrupt enable */ |
bogdanm | 86:04dd9b1680ae | 4174 | |
bogdanm | 86:04dd9b1680ae | 4175 | #define HRTIM_TIMDIER_CMP1DE ((uint32_t)0x00010000) /*!< Slave compare 1 request enable */ |
bogdanm | 86:04dd9b1680ae | 4176 | #define HRTIM_TIMDIER_CMP2DE ((uint32_t)0x00020000) /*!< Slave compare 2 request enable */ |
bogdanm | 86:04dd9b1680ae | 4177 | #define HRTIM_TIMDIER_CMP3DE ((uint32_t)0x00040000) /*!< Slave compare 3 request enable */ |
bogdanm | 86:04dd9b1680ae | 4178 | #define HRTIM_TIMDIER_CMP4DE ((uint32_t)0x00080000) /*!< Slave compare 4 request enable */ |
bogdanm | 86:04dd9b1680ae | 4179 | #define HRTIM_TIMDIER_REPDE ((uint32_t)0x00100000) /*!< Slave repetition request enable */ |
bogdanm | 86:04dd9b1680ae | 4180 | #define HRTIM_TIMDIER_UPDDE ((uint32_t)0x00400000) /*!< Slave update request enable */ |
bogdanm | 86:04dd9b1680ae | 4181 | #define HRTIM_TIMDIER_CPT1DE ((uint32_t)0x00800000) /*!< Slave capture 1 request enable */ |
bogdanm | 86:04dd9b1680ae | 4182 | #define HRTIM_TIMDIER_CPT2DE ((uint32_t)0x01000000) /*!< Slave capture 2 request enable */ |
bogdanm | 86:04dd9b1680ae | 4183 | #define HRTIM_TIMDIER_SET1DE ((uint32_t)0x02000000) /*!< Slave output 1 set request enable */ |
bogdanm | 86:04dd9b1680ae | 4184 | #define HRTIM_TIMDIER_RST1DE ((uint32_t)0x04000000) /*!< Slave output 1 reset request enable */ |
bogdanm | 86:04dd9b1680ae | 4185 | #define HRTIM_TIMDIER_SET2DE ((uint32_t)0x08000000) /*!< Slave output 2 set request enable */ |
bogdanm | 86:04dd9b1680ae | 4186 | #define HRTIM_TIMDIER_RST2DE ((uint32_t)0x10000000) /*!< Slave output 2 reset request enable */ |
bogdanm | 86:04dd9b1680ae | 4187 | #define HRTIM_TIMDIER_RSTDE ((uint32_t)0x20000000) /*!< Slave reset request enable */ |
bogdanm | 86:04dd9b1680ae | 4188 | #define HRTIM_TIMDIER_DLYPRTDE ((uint32_t)0x40000000) /*!< Slavedelay protection request enable */ |
bogdanm | 86:04dd9b1680ae | 4189 | |
bogdanm | 86:04dd9b1680ae | 4190 | /****************** Bit definition for HRTIM_CNTR register ****************/ |
bogdanm | 86:04dd9b1680ae | 4191 | #define HRTIM_CNTR_CNTR ((uint32_t)0xFFFFFFFF) /*!< Counter Value */ |
bogdanm | 86:04dd9b1680ae | 4192 | |
bogdanm | 86:04dd9b1680ae | 4193 | /******************* Bit definition for HRTIM_PER register *****************/ |
bogdanm | 86:04dd9b1680ae | 4194 | #define HRTIM_PER_PER ((uint32_t)0xFFFFFFFF) /*!< Period Value */ |
bogdanm | 86:04dd9b1680ae | 4195 | |
bogdanm | 86:04dd9b1680ae | 4196 | /******************* Bit definition for HRTIM_REP register *****************/ |
bogdanm | 86:04dd9b1680ae | 4197 | #define HRTIM_REP_REP ((uint32_t)0xFFFFFFFF) /*!< Repetition Value */ |
bogdanm | 86:04dd9b1680ae | 4198 | |
bogdanm | 86:04dd9b1680ae | 4199 | /******************* Bit definition for HRTIM_CMP1R register *****************/ |
bogdanm | 86:04dd9b1680ae | 4200 | #define HRTIM_CMP1R_CMP1R ((uint32_t)0xFFFFFFFF) /*!< Compare Value */ |
bogdanm | 86:04dd9b1680ae | 4201 | |
bogdanm | 86:04dd9b1680ae | 4202 | /******************* Bit definition for HRTIM_CMP1CR register *****************/ |
bogdanm | 86:04dd9b1680ae | 4203 | #define HRTIM_CMP1CR_CMP1CR ((uint32_t)0xFFFFFFFF) /*!< Compare Value */ |
bogdanm | 86:04dd9b1680ae | 4204 | |
bogdanm | 86:04dd9b1680ae | 4205 | /******************* Bit definition for HRTIM_CMP2R register *****************/ |
bogdanm | 86:04dd9b1680ae | 4206 | #define HRTIM_CMP2R_CMP2R ((uint32_t)0xFFFFFFFF) /*!< Compare Value */ |
bogdanm | 86:04dd9b1680ae | 4207 | |
bogdanm | 86:04dd9b1680ae | 4208 | /******************* Bit definition for HRTIM_CMP3R register *****************/ |
bogdanm | 86:04dd9b1680ae | 4209 | #define HRTIM_CMP3R_CMP3R ((uint32_t)0xFFFFFFFF) /*!< Compare Value */ |
bogdanm | 86:04dd9b1680ae | 4210 | |
bogdanm | 86:04dd9b1680ae | 4211 | /******************* Bit definition for HRTIM_CMP4R register *****************/ |
bogdanm | 86:04dd9b1680ae | 4212 | #define HRTIM_CMP4R_CMP4R ((uint32_t)0xFFFFFFFF) /*!< Compare Value */ |
bogdanm | 86:04dd9b1680ae | 4213 | |
bogdanm | 86:04dd9b1680ae | 4214 | /******************* Bit definition for HRTIM_CPT1R register ****************/ |
bogdanm | 86:04dd9b1680ae | 4215 | #define HRTIM_CPT1R_CPT1R ((uint32_t)0xFFFFFFFF) /*!< Capture Value */ |
bogdanm | 86:04dd9b1680ae | 4216 | |
bogdanm | 86:04dd9b1680ae | 4217 | /******************* Bit definition for HRTIM_CPT2R register ****************/ |
bogdanm | 86:04dd9b1680ae | 4218 | #define HRTIM_CPT2R_CPT2R ((uint32_t)0xFFFFFFFF) /*!< Capture Value */ |
bogdanm | 86:04dd9b1680ae | 4219 | |
bogdanm | 86:04dd9b1680ae | 4220 | /******************** Bit definition for Slave Deadtime register **************/ |
bogdanm | 86:04dd9b1680ae | 4221 | #define HRTIM_DTR_DTR ((uint32_t)0x000001FF) /*!< Dead time rising value */ |
bogdanm | 86:04dd9b1680ae | 4222 | #define HRTIM_DTR_DTR_0 ((uint32_t)0x00000001) /*!< Dead time rising bit 0 */ |
bogdanm | 86:04dd9b1680ae | 4223 | #define HRTIM_DTR_DTR_1 ((uint32_t)0x00000002) /*!< Dead time rising bit 1 */ |
bogdanm | 86:04dd9b1680ae | 4224 | #define HRTIM_DTR_DTR_2 ((uint32_t)0x00000004) /*!< Dead time rising bit 2 */ |
bogdanm | 86:04dd9b1680ae | 4225 | #define HRTIM_DTR_DTR_3 ((uint32_t)0x00000008) /*!< Dead time rising bit 3 */ |
bogdanm | 86:04dd9b1680ae | 4226 | #define HRTIM_DTR_DTR_4 ((uint32_t)0x00000010) /*!< Dead time rising bit 4 */ |
bogdanm | 86:04dd9b1680ae | 4227 | #define HRTIM_DTR_DTR_5 ((uint32_t)0x00000020) /*!< Dead time rising bit 5 */ |
bogdanm | 86:04dd9b1680ae | 4228 | #define HRTIM_DTR_DTR_6 ((uint32_t)0x00000040) /*!< Dead time rising bit 6 */ |
bogdanm | 86:04dd9b1680ae | 4229 | #define HRTIM_DTR_DTR_7 ((uint32_t)0x00000080) /*!< Dead time rising bit 7 */ |
bogdanm | 86:04dd9b1680ae | 4230 | #define HRTIM_DTR_DTR_8 ((uint32_t)0x00000100) /*!< Dead time rising bit 8 */ |
bogdanm | 86:04dd9b1680ae | 4231 | #define HRTIM_DTR_SDTR ((uint32_t)0x00000200) /*!< Sign dead time rising value */ |
bogdanm | 86:04dd9b1680ae | 4232 | #define HRTIM_DTR_DTPRSC ((uint32_t)0x00001C00) /*!< Dead time prescaler */ |
bogdanm | 86:04dd9b1680ae | 4233 | #define HRTIM_DTR_DTPRSC_0 ((uint32_t)0x00000400) /*!< Dead time prescaler bit 0 */ |
bogdanm | 86:04dd9b1680ae | 4234 | #define HRTIM_DTR_DTPRSC_1 ((uint32_t)0x00000800) /*!< Dead time prescaler bit 1 */ |
bogdanm | 86:04dd9b1680ae | 4235 | #define HRTIM_DTR_DTPRSC_2 ((uint32_t)0x00001000) /*!< Dead time prescaler bit 2 */ |
bogdanm | 86:04dd9b1680ae | 4236 | #define HRTIM_DTR_DTRSLK ((uint32_t)0x00004000) /*!< Dead time rising sign lock */ |
bogdanm | 86:04dd9b1680ae | 4237 | #define HRTIM_DTR_DTRLK ((uint32_t)0x00008000) /*!< Dead time rising lock */ |
bogdanm | 86:04dd9b1680ae | 4238 | #define HRTIM_DTR_DTF ((uint32_t)0x01FF0000) /*!< Dead time falling value */ |
bogdanm | 86:04dd9b1680ae | 4239 | #define HRTIM_DTR_DTF_0 ((uint32_t)0x00010000) /*!< Dead time falling bit 0 */ |
bogdanm | 86:04dd9b1680ae | 4240 | #define HRTIM_DTR_DTF_1 ((uint32_t)0x00020000) /*!< Dead time falling bit 1 */ |
bogdanm | 86:04dd9b1680ae | 4241 | #define HRTIM_DTR_DTF_2 ((uint32_t)0x00040000) /*!< Dead time falling bit 2 */ |
bogdanm | 86:04dd9b1680ae | 4242 | #define HRTIM_DTR_DTF_3 ((uint32_t)0x00080000) /*!< Dead time falling bit 3 */ |
bogdanm | 86:04dd9b1680ae | 4243 | #define HRTIM_DTR_DTF_4 ((uint32_t)0x00100000) /*!< Dead time falling bit 4 */ |
bogdanm | 86:04dd9b1680ae | 4244 | #define HRTIM_DTR_DTF_5 ((uint32_t)0x00200000) /*!< Dead time falling bit 5 */ |
bogdanm | 86:04dd9b1680ae | 4245 | #define HRTIM_DTR_DTF_6 ((uint32_t)0x00400000) /*!< Dead time falling bit 6 */ |
bogdanm | 86:04dd9b1680ae | 4246 | #define HRTIM_DTR_DTF_7 ((uint32_t)0x00800000) /*!< Dead time falling bit 7 */ |
bogdanm | 86:04dd9b1680ae | 4247 | #define HRTIM_DTR_DTF_8 ((uint32_t)0x01000000) /*!< Dead time falling bit 8 */ |
bogdanm | 86:04dd9b1680ae | 4248 | #define HRTIM_DTR_SDTF ((uint32_t)0x02000000) /*!< Sign dead time falling value */ |
bogdanm | 86:04dd9b1680ae | 4249 | #define HRTIM_DTR_DTFSLK ((uint32_t)0x40000000) /*!< Dead time falling sign lock */ |
bogdanm | 86:04dd9b1680ae | 4250 | #define HRTIM_DTR_DTFLK ((uint32_t)0x80000000) /*!< Dead time falling lock */ |
bogdanm | 86:04dd9b1680ae | 4251 | |
bogdanm | 86:04dd9b1680ae | 4252 | /**** Bit definition for Slave Output 1 set register **************************/ |
bogdanm | 86:04dd9b1680ae | 4253 | #define HRTIM_SET1R_SST ((uint32_t)0x00000001) /*!< software set trigger */ |
bogdanm | 86:04dd9b1680ae | 4254 | #define HRTIM_SET1R_RESYNC ((uint32_t)0x00000002) /*!< Timer A resynchronization */ |
bogdanm | 86:04dd9b1680ae | 4255 | #define HRTIM_SET1R_PER ((uint32_t)0x00000004) /*!< Timer A period */ |
bogdanm | 86:04dd9b1680ae | 4256 | #define HRTIM_SET1R_CMP1 ((uint32_t)0x00000008) /*!< Timer A compare 1 */ |
bogdanm | 86:04dd9b1680ae | 4257 | #define HRTIM_SET1R_CMP2 ((uint32_t)0x00000010) /*!< Timer A compare 2 */ |
bogdanm | 86:04dd9b1680ae | 4258 | #define HRTIM_SET1R_CMP3 ((uint32_t)0x00000020) /*!< Timer A compare 3 */ |
bogdanm | 86:04dd9b1680ae | 4259 | #define HRTIM_SET1R_CMP4 ((uint32_t)0x00000040) /*!< Timer A compare 4 */ |
bogdanm | 86:04dd9b1680ae | 4260 | |
bogdanm | 86:04dd9b1680ae | 4261 | #define HRTIM_SET1R_MSTPER ((uint32_t)0x00000080) /*!< Master period */ |
bogdanm | 86:04dd9b1680ae | 4262 | #define HRTIM_SET1R_MSTCMP1 ((uint32_t)0x00000100) /*!< Master compare 1 */ |
bogdanm | 86:04dd9b1680ae | 4263 | #define HRTIM_SET1R_MSTCMP2 ((uint32_t)0x00000200) /*!< Master compare 2 */ |
bogdanm | 86:04dd9b1680ae | 4264 | #define HRTIM_SET1R_MSTCMP3 ((uint32_t)0x00000400) /*!< Master compare 3 */ |
bogdanm | 86:04dd9b1680ae | 4265 | #define HRTIM_SET1R_MSTCMP4 ((uint32_t)0x00000800) /*!< Master compare 4 */ |
bogdanm | 86:04dd9b1680ae | 4266 | |
bogdanm | 86:04dd9b1680ae | 4267 | #define HRTIM_SET1R_TIMEVNT1 ((uint32_t)0x00001000) /*!< Timer event 1 */ |
bogdanm | 86:04dd9b1680ae | 4268 | #define HRTIM_SET1R_TIMEVNT2 ((uint32_t)0x00002000) /*!< Timer event 2 */ |
bogdanm | 86:04dd9b1680ae | 4269 | #define HRTIM_SET1R_TIMEVNT3 ((uint32_t)0x00004000) /*!< Timer event 3 */ |
bogdanm | 86:04dd9b1680ae | 4270 | #define HRTIM_SET1R_TIMEVNT4 ((uint32_t)0x00008000) /*!< Timer event 4 */ |
bogdanm | 86:04dd9b1680ae | 4271 | #define HRTIM_SET1R_TIMEVNT5 ((uint32_t)0x00010000) /*!< Timer event 5 */ |
bogdanm | 86:04dd9b1680ae | 4272 | #define HRTIM_SET1R_TIMEVNT6 ((uint32_t)0x00020000) /*!< Timer event 6 */ |
bogdanm | 86:04dd9b1680ae | 4273 | #define HRTIM_SET1R_TIMEVNT7 ((uint32_t)0x00040000) /*!< Timer event 7 */ |
bogdanm | 86:04dd9b1680ae | 4274 | #define HRTIM_SET1R_TIMEVNT8 ((uint32_t)0x00080000) /*!< Timer event 8 */ |
bogdanm | 86:04dd9b1680ae | 4275 | #define HRTIM_SET1R_TIMEVNT9 ((uint32_t)0x00100000) /*!< Timer event 9 */ |
bogdanm | 86:04dd9b1680ae | 4276 | |
bogdanm | 86:04dd9b1680ae | 4277 | #define HRTIM_SET1R_EXTVNT1 ((uint32_t)0x00200000) /*!< External event 1 */ |
bogdanm | 86:04dd9b1680ae | 4278 | #define HRTIM_SET1R_EXTVNT2 ((uint32_t)0x00400000) /*!< External event 2 */ |
bogdanm | 86:04dd9b1680ae | 4279 | #define HRTIM_SET1R_EXTVNT3 ((uint32_t)0x00800000) /*!< External event 3 */ |
bogdanm | 86:04dd9b1680ae | 4280 | #define HRTIM_SET1R_EXTVNT4 ((uint32_t)0x01000000) /*!< External event 4 */ |
bogdanm | 86:04dd9b1680ae | 4281 | #define HRTIM_SET1R_EXTVNT5 ((uint32_t)0x02000000) /*!< External event 5 */ |
bogdanm | 86:04dd9b1680ae | 4282 | #define HRTIM_SET1R_EXTVNT6 ((uint32_t)0x04000000) /*!< External event 6 */ |
bogdanm | 86:04dd9b1680ae | 4283 | #define HRTIM_SET1R_EXTVNT7 ((uint32_t)0x08000000) /*!< External event 7 */ |
bogdanm | 86:04dd9b1680ae | 4284 | #define HRTIM_SET1R_EXTVNT8 ((uint32_t)0x10000000) /*!< External event 8 */ |
bogdanm | 86:04dd9b1680ae | 4285 | #define HRTIM_SET1R_EXTVNT9 ((uint32_t)0x20000000) /*!< External event 9 */ |
bogdanm | 86:04dd9b1680ae | 4286 | #define HRTIM_SET1R_EXTVNT10 ((uint32_t)0x40000000) /*!< External event 10 */ |
bogdanm | 86:04dd9b1680ae | 4287 | |
bogdanm | 86:04dd9b1680ae | 4288 | #define HRTIM_SET1R_UPDATE ((uint32_t)0x80000000) /*!< Register update (transfer preload to active) */ |
bogdanm | 86:04dd9b1680ae | 4289 | |
bogdanm | 86:04dd9b1680ae | 4290 | /**** Bit definition for Slave Output 1 reset register ************************/ |
bogdanm | 86:04dd9b1680ae | 4291 | #define HRTIM_RST1R_SRT ((uint32_t)0x00000001) /*!< software reset trigger */ |
bogdanm | 86:04dd9b1680ae | 4292 | #define HRTIM_RST1R_RESYNC ((uint32_t)0x00000002) /*!< Timer A resynchronization */ |
bogdanm | 86:04dd9b1680ae | 4293 | #define HRTIM_RST1R_PER ((uint32_t)0x00000004) /*!< Timer A period */ |
bogdanm | 86:04dd9b1680ae | 4294 | #define HRTIM_RST1R_CMP1 ((uint32_t)0x00000008) /*!< Timer A compare 1 */ |
bogdanm | 86:04dd9b1680ae | 4295 | #define HRTIM_RST1R_CMP2 ((uint32_t)0x00000010) /*!< Timer A compare 2 */ |
bogdanm | 86:04dd9b1680ae | 4296 | #define HRTIM_RST1R_CMP3 ((uint32_t)0x00000020) /*!< Timer A compare 3 */ |
bogdanm | 86:04dd9b1680ae | 4297 | #define HRTIM_RST1R_CMP4 ((uint32_t)0x00000040) /*!< Timer A compare 4 */ |
bogdanm | 86:04dd9b1680ae | 4298 | |
bogdanm | 86:04dd9b1680ae | 4299 | #define HRTIM_RST1R_MSTPER ((uint32_t)0x00000080) /*!< Master period */ |
bogdanm | 86:04dd9b1680ae | 4300 | #define HRTIM_RST1R_MSTCMP1 ((uint32_t)0x00000100) /*!< Master compare 1 */ |
bogdanm | 86:04dd9b1680ae | 4301 | #define HRTIM_RST1R_MSTCMP2 ((uint32_t)0x00000200) /*!< Master compare 2 */ |
bogdanm | 86:04dd9b1680ae | 4302 | #define HRTIM_RST1R_MSTCMP3 ((uint32_t)0x00000400) /*!< Master compare 3 */ |
bogdanm | 86:04dd9b1680ae | 4303 | #define HRTIM_RST1R_MSTCMP4 ((uint32_t)0x00000800) /*!< Master compare 4 */ |
bogdanm | 86:04dd9b1680ae | 4304 | |
bogdanm | 86:04dd9b1680ae | 4305 | #define HRTIM_RST1R_TIMEVNT1 ((uint32_t)0x00001000) /*!< Timer event 1 */ |
bogdanm | 86:04dd9b1680ae | 4306 | #define HRTIM_RST1R_TIMEVNT2 ((uint32_t)0x00002000) /*!< Timer event 2 */ |
bogdanm | 86:04dd9b1680ae | 4307 | #define HRTIM_RST1R_TIMEVNT3 ((uint32_t)0x00004000) /*!< Timer event 3 */ |
bogdanm | 86:04dd9b1680ae | 4308 | #define HRTIM_RST1R_TIMEVNT4 ((uint32_t)0x00008000) /*!< Timer event 4 */ |
bogdanm | 86:04dd9b1680ae | 4309 | #define HRTIM_RST1R_TIMEVNT5 ((uint32_t)0x00010000) /*!< Timer event 5 */ |
bogdanm | 86:04dd9b1680ae | 4310 | #define HRTIM_RST1R_TIMEVNT6 ((uint32_t)0x00020000) /*!< Timer event 6 */ |
bogdanm | 86:04dd9b1680ae | 4311 | #define HRTIM_RST1R_TIMEVNT7 ((uint32_t)0x00040000) /*!< Timer event 7 */ |
bogdanm | 86:04dd9b1680ae | 4312 | #define HRTIM_RST1R_TIMEVNT8 ((uint32_t)0x00080000) /*!< Timer event 8 */ |
bogdanm | 86:04dd9b1680ae | 4313 | #define HRTIM_RST1R_TIMEVNT9 ((uint32_t)0x00100000) /*!< Timer event 9 */ |
bogdanm | 86:04dd9b1680ae | 4314 | |
bogdanm | 86:04dd9b1680ae | 4315 | #define HRTIM_RST1R_EXTVNT1 ((uint32_t)0x00200000) /*!< External event 1 */ |
bogdanm | 86:04dd9b1680ae | 4316 | #define HRTIM_RST1R_EXTVNT2 ((uint32_t)0x00400000) /*!< External event 2 */ |
bogdanm | 86:04dd9b1680ae | 4317 | #define HRTIM_RST1R_EXTVNT3 ((uint32_t)0x00800000) /*!< External event 3 */ |
bogdanm | 86:04dd9b1680ae | 4318 | #define HRTIM_RST1R_EXTVNT4 ((uint32_t)0x01000000) /*!< External event 4 */ |
bogdanm | 86:04dd9b1680ae | 4319 | #define HRTIM_RST1R_EXTVNT5 ((uint32_t)0x02000000) /*!< External event 5 */ |
bogdanm | 86:04dd9b1680ae | 4320 | #define HRTIM_RST1R_EXTVNT6 ((uint32_t)0x04000000) /*!< External event 6 */ |
bogdanm | 86:04dd9b1680ae | 4321 | #define HRTIM_RST1R_EXTVNT7 ((uint32_t)0x08000000) /*!< External event 7 */ |
bogdanm | 86:04dd9b1680ae | 4322 | #define HRTIM_RST1R_EXTVNT8 ((uint32_t)0x10000000) /*!< External event 8 */ |
bogdanm | 86:04dd9b1680ae | 4323 | #define HRTIM_RST1R_EXTVNT9 ((uint32_t)0x20000000) /*!< External event 9 */ |
bogdanm | 86:04dd9b1680ae | 4324 | #define HRTIM_RST1R_EXTVNT10 ((uint32_t)0x40000000) /*!< External event 10 */ |
bogdanm | 86:04dd9b1680ae | 4325 | |
bogdanm | 86:04dd9b1680ae | 4326 | #define HRTIM_RST1R_UPDATE ((uint32_t)0x80000000) /*!< Register update (transfer preload to active) */ |
bogdanm | 86:04dd9b1680ae | 4327 | |
bogdanm | 86:04dd9b1680ae | 4328 | |
bogdanm | 86:04dd9b1680ae | 4329 | /**** Bit definition for Slave Output 2 set register **************************/ |
bogdanm | 86:04dd9b1680ae | 4330 | #define HRTIM_SET2R_SST ((uint32_t)0x00000001) /*!< software set trigger */ |
bogdanm | 86:04dd9b1680ae | 4331 | #define HRTIM_SET2R_RESYNC ((uint32_t)0x00000002) /*!< Timer A resynchronization */ |
bogdanm | 86:04dd9b1680ae | 4332 | #define HRTIM_SET2R_PER ((uint32_t)0x00000004) /*!< Timer A period */ |
bogdanm | 86:04dd9b1680ae | 4333 | #define HRTIM_SET2R_CMP1 ((uint32_t)0x00000008) /*!< Timer A compare 1 */ |
bogdanm | 86:04dd9b1680ae | 4334 | #define HRTIM_SET2R_CMP2 ((uint32_t)0x00000010) /*!< Timer A compare 2 */ |
bogdanm | 86:04dd9b1680ae | 4335 | #define HRTIM_SET2R_CMP3 ((uint32_t)0x00000020) /*!< Timer A compare 3 */ |
bogdanm | 86:04dd9b1680ae | 4336 | #define HRTIM_SET2R_CMP4 ((uint32_t)0x00000040) /*!< Timer A compare 4 */ |
bogdanm | 86:04dd9b1680ae | 4337 | |
bogdanm | 86:04dd9b1680ae | 4338 | #define HRTIM_SET2R_MSTPER ((uint32_t)0x00000080) /*!< Master period */ |
bogdanm | 86:04dd9b1680ae | 4339 | #define HRTIM_SET2R_MSTCMP1 ((uint32_t)0x00000100) /*!< Master compare 1 */ |
bogdanm | 86:04dd9b1680ae | 4340 | #define HRTIM_SET2R_MSTCMP2 ((uint32_t)0x00000200) /*!< Master compare 2 */ |
bogdanm | 86:04dd9b1680ae | 4341 | #define HRTIM_SET2R_MSTCMP3 ((uint32_t)0x00000400) /*!< Master compare 3 */ |
bogdanm | 86:04dd9b1680ae | 4342 | #define HRTIM_SET2R_MSTCMP4 ((uint32_t)0x00000800) /*!< Master compare 4 */ |
bogdanm | 86:04dd9b1680ae | 4343 | |
bogdanm | 86:04dd9b1680ae | 4344 | #define HRTIM_SET2R_TIMEVNT1 ((uint32_t)0x00001000) /*!< Timer event 1 */ |
bogdanm | 86:04dd9b1680ae | 4345 | #define HRTIM_SET2R_TIMEVNT2 ((uint32_t)0x00002000) /*!< Timer event 2 */ |
bogdanm | 86:04dd9b1680ae | 4346 | #define HRTIM_SET2R_TIMEVNT3 ((uint32_t)0x00004000) /*!< Timer event 3 */ |
bogdanm | 86:04dd9b1680ae | 4347 | #define HRTIM_SET2R_TIMEVNT4 ((uint32_t)0x00008000) /*!< Timer event 4 */ |
bogdanm | 86:04dd9b1680ae | 4348 | #define HRTIM_SET2R_TIMEVNT5 ((uint32_t)0x00010000) /*!< Timer event 5 */ |
bogdanm | 86:04dd9b1680ae | 4349 | #define HRTIM_SET2R_TIMEVNT6 ((uint32_t)0x00020000) /*!< Timer event 6 */ |
bogdanm | 86:04dd9b1680ae | 4350 | #define HRTIM_SET2R_TIMEVNT7 ((uint32_t)0x00040000) /*!< Timer event 7 */ |
bogdanm | 86:04dd9b1680ae | 4351 | #define HRTIM_SET2R_TIMEVNT8 ((uint32_t)0x00080000) /*!< Timer event 8 */ |
bogdanm | 86:04dd9b1680ae | 4352 | #define HRTIM_SET2R_TIMEVNT9 ((uint32_t)0x00100000) /*!< Timer event 9 */ |
bogdanm | 86:04dd9b1680ae | 4353 | |
bogdanm | 86:04dd9b1680ae | 4354 | #define HRTIM_SET2R_EXTVNT1 ((uint32_t)0x00200000) /*!< External event 1 */ |
bogdanm | 86:04dd9b1680ae | 4355 | #define HRTIM_SET2R_EXTVNT2 ((uint32_t)0x00400000) /*!< External event 2 */ |
bogdanm | 86:04dd9b1680ae | 4356 | #define HRTIM_SET2R_EXTVNT3 ((uint32_t)0x00800000) /*!< External event 3 */ |
bogdanm | 86:04dd9b1680ae | 4357 | #define HRTIM_SET2R_EXTVNT4 ((uint32_t)0x01000000) /*!< External event 4 */ |
bogdanm | 86:04dd9b1680ae | 4358 | #define HRTIM_SET2R_EXTVNT5 ((uint32_t)0x02000000) /*!< External event 5 */ |
bogdanm | 86:04dd9b1680ae | 4359 | #define HRTIM_SET2R_EXTVNT6 ((uint32_t)0x04000000) /*!< External event 6 */ |
bogdanm | 86:04dd9b1680ae | 4360 | #define HRTIM_SET2R_EXTVNT7 ((uint32_t)0x08000000) /*!< External event 7 */ |
bogdanm | 86:04dd9b1680ae | 4361 | #define HRTIM_SET2R_EXTVNT8 ((uint32_t)0x10000000) /*!< External event 8 */ |
bogdanm | 86:04dd9b1680ae | 4362 | #define HRTIM_SET2R_EXTVNT9 ((uint32_t)0x20000000) /*!< External event 9 */ |
bogdanm | 86:04dd9b1680ae | 4363 | #define HRTIM_SET2R_EXTVNT10 ((uint32_t)0x40000000) /*!< External event 10 */ |
bogdanm | 86:04dd9b1680ae | 4364 | |
bogdanm | 86:04dd9b1680ae | 4365 | #define HRTIM_SET2R_UPDATE ((uint32_t)0x80000000) /*!< Register update (transfer preload to active) */ |
bogdanm | 86:04dd9b1680ae | 4366 | |
bogdanm | 86:04dd9b1680ae | 4367 | /**** Bit definition for Slave Output 2 reset register ************************/ |
bogdanm | 86:04dd9b1680ae | 4368 | #define HRTIM_RST2R_SRT ((uint32_t)0x00000001) /*!< software reset trigger */ |
bogdanm | 86:04dd9b1680ae | 4369 | #define HRTIM_RST2R_RESYNC ((uint32_t)0x00000002) /*!< Timer A resynchronization */ |
bogdanm | 86:04dd9b1680ae | 4370 | #define HRTIM_RST2R_PER ((uint32_t)0x00000004) /*!< Timer A period */ |
bogdanm | 86:04dd9b1680ae | 4371 | #define HRTIM_RST2R_CMP1 ((uint32_t)0x00000008) /*!< Timer A compare 1 */ |
bogdanm | 86:04dd9b1680ae | 4372 | #define HRTIM_RST2R_CMP2 ((uint32_t)0x00000010) /*!< Timer A compare 2 */ |
bogdanm | 86:04dd9b1680ae | 4373 | #define HRTIM_RST2R_CMP3 ((uint32_t)0x00000020) /*!< Timer A compare 3 */ |
bogdanm | 86:04dd9b1680ae | 4374 | #define HRTIM_RST2R_CMP4 ((uint32_t)0x00000040) /*!< Timer A compare 4 */ |
bogdanm | 86:04dd9b1680ae | 4375 | |
bogdanm | 86:04dd9b1680ae | 4376 | #define HRTIM_RST2R_MSTPER ((uint32_t)0x00000080) /*!< Master period */ |
bogdanm | 86:04dd9b1680ae | 4377 | #define HRTIM_RST2R_MSTCMP1 ((uint32_t)0x00000100) /*!< Master compare 1 */ |
bogdanm | 86:04dd9b1680ae | 4378 | #define HRTIM_RST2R_MSTCMP2 ((uint32_t)0x00000200) /*!< Master compare 2 */ |
bogdanm | 86:04dd9b1680ae | 4379 | #define HRTIM_RST2R_MSTCMP3 ((uint32_t)0x00000400) /*!< Master compare 3 */ |
bogdanm | 86:04dd9b1680ae | 4380 | #define HRTIM_RST2R_MSTCMP4 ((uint32_t)0x00000800) /*!< Master compare 4 */ |
bogdanm | 86:04dd9b1680ae | 4381 | |
bogdanm | 86:04dd9b1680ae | 4382 | #define HRTIM_RST2R_TIMEVNT1 ((uint32_t)0x00001000) /*!< Timer event 1 */ |
bogdanm | 86:04dd9b1680ae | 4383 | #define HRTIM_RST2R_TIMEVNT2 ((uint32_t)0x00002000) /*!< Timer event 2 */ |
bogdanm | 86:04dd9b1680ae | 4384 | #define HRTIM_RST2R_TIMEVNT3 ((uint32_t)0x00004000) /*!< Timer event 3 */ |
bogdanm | 86:04dd9b1680ae | 4385 | #define HRTIM_RST2R_TIMEVNT4 ((uint32_t)0x00008000) /*!< Timer event 4 */ |
bogdanm | 86:04dd9b1680ae | 4386 | #define HRTIM_RST2R_TIMEVNT5 ((uint32_t)0x00010000) /*!< Timer event 5 */ |
bogdanm | 86:04dd9b1680ae | 4387 | #define HRTIM_RST2R_TIMEVNT6 ((uint32_t)0x00020000) /*!< Timer event 6 */ |
bogdanm | 86:04dd9b1680ae | 4388 | #define HRTIM_RST2R_TIMEVNT7 ((uint32_t)0x00040000) /*!< Timer event 7 */ |
bogdanm | 86:04dd9b1680ae | 4389 | #define HRTIM_RST2R_TIMEVNT8 ((uint32_t)0x00080000) /*!< Timer event 8 */ |
bogdanm | 86:04dd9b1680ae | 4390 | #define HRTIM_RST2R_TIMEVNT9 ((uint32_t)0x00100000) /*!< Timer event 9 */ |
bogdanm | 86:04dd9b1680ae | 4391 | |
bogdanm | 86:04dd9b1680ae | 4392 | #define HRTIM_RST2R_EXTVNT1 ((uint32_t)0x00200000) /*!< External event 1 */ |
bogdanm | 86:04dd9b1680ae | 4393 | #define HRTIM_RST2R_EXTVNT2 ((uint32_t)0x00400000) /*!< External event 2 */ |
bogdanm | 86:04dd9b1680ae | 4394 | #define HRTIM_RST2R_EXTVNT3 ((uint32_t)0x00800000) /*!< External event 3 */ |
bogdanm | 86:04dd9b1680ae | 4395 | #define HRTIM_RST2R_EXTVNT4 ((uint32_t)0x01000000) /*!< External event 4 */ |
bogdanm | 86:04dd9b1680ae | 4396 | #define HRTIM_RST2R_EXTVNT5 ((uint32_t)0x02000000) /*!< External event 5 */ |
bogdanm | 86:04dd9b1680ae | 4397 | #define HRTIM_RST2R_EXTVNT6 ((uint32_t)0x04000000) /*!< External event 6 */ |
bogdanm | 86:04dd9b1680ae | 4398 | #define HRTIM_RST2R_EXTVNT7 ((uint32_t)0x08000000) /*!< External event 7 */ |
bogdanm | 86:04dd9b1680ae | 4399 | #define HRTIM_RST2R_EXTVNT8 ((uint32_t)0x10000000) /*!< External event 8 */ |
bogdanm | 86:04dd9b1680ae | 4400 | #define HRTIM_RST2R_EXTVNT9 ((uint32_t)0x20000000) /*!< External event 9 */ |
bogdanm | 86:04dd9b1680ae | 4401 | #define HRTIM_RST2R_EXTVNT10 ((uint32_t)0x40000000) /*!< External event 10 */ |
bogdanm | 86:04dd9b1680ae | 4402 | |
bogdanm | 86:04dd9b1680ae | 4403 | #define HRTIM_RST2R_UPDATE ((uint32_t)0x80000000) /*!< Register update (transfer preload to active) */ |
bogdanm | 86:04dd9b1680ae | 4404 | |
bogdanm | 86:04dd9b1680ae | 4405 | /**** Bit definition for Slave external event filtering register 1 ***********/ |
bogdanm | 86:04dd9b1680ae | 4406 | #define HRTIM_EEFR1_EE1LTCH ((uint32_t)0x00000001) /*!< External Event 1 latch */ |
bogdanm | 86:04dd9b1680ae | 4407 | #define HRTIM_EEFR1_EE1FLTR ((uint32_t)0x0000001E) /*!< External Event 1 filter mask */ |
bogdanm | 86:04dd9b1680ae | 4408 | #define HRTIM_EEFR1_EE1FLTR_0 ((uint32_t)0x00000002) /*!< External Event 1 bit 0 */ |
bogdanm | 86:04dd9b1680ae | 4409 | #define HRTIM_EEFR1_EE1FLTR_1 ((uint32_t)0x00000004) /*!< External Event 1 bit 1*/ |
bogdanm | 86:04dd9b1680ae | 4410 | #define HRTIM_EEFR1_EE1FLTR_2 ((uint32_t)0x00000008) /*!< External Event 1 bit 2 */ |
bogdanm | 86:04dd9b1680ae | 4411 | #define HRTIM_EEFR1_EE1FLTR_3 ((uint32_t)0x00000010) /*!< External Event 1 bit 3 */ |
bogdanm | 86:04dd9b1680ae | 4412 | |
bogdanm | 86:04dd9b1680ae | 4413 | #define HRTIM_EEFR1_EE2LTCH ((uint32_t)0x00000040) /*!< External Event 2 latch */ |
bogdanm | 86:04dd9b1680ae | 4414 | #define HRTIM_EEFR1_EE2FLTR ((uint32_t)0x00000780) /*!< External Event 2 filter mask */ |
bogdanm | 86:04dd9b1680ae | 4415 | #define HRTIM_EEFR1_EE2FLTR_0 ((uint32_t)0x00000080) /*!< External Event 2 bit 0 */ |
bogdanm | 86:04dd9b1680ae | 4416 | #define HRTIM_EEFR1_EE2FLTR_1 ((uint32_t)0x00000100) /*!< External Event 2 bit 1*/ |
bogdanm | 86:04dd9b1680ae | 4417 | #define HRTIM_EEFR1_EE2FLTR_2 ((uint32_t)0x00000200) /*!< External Event 2 bit 2 */ |
bogdanm | 86:04dd9b1680ae | 4418 | #define HRTIM_EEFR1_EE2FLTR_3 ((uint32_t)0x00000400) /*!< External Event 2 bit 3 */ |
bogdanm | 86:04dd9b1680ae | 4419 | |
bogdanm | 86:04dd9b1680ae | 4420 | #define HRTIM_EEFR1_EE3LTCH ((uint32_t)0x00001000) /*!< External Event 3 latch */ |
bogdanm | 86:04dd9b1680ae | 4421 | #define HRTIM_EEFR1_EE3FLTR ((uint32_t)0x0001E000) /*!< External Event 3 filter mask */ |
bogdanm | 86:04dd9b1680ae | 4422 | #define HRTIM_EEFR1_EE3FLTR_0 ((uint32_t)0x00002000) /*!< External Event 3 bit 0 */ |
bogdanm | 86:04dd9b1680ae | 4423 | #define HRTIM_EEFR1_EE3FLTR_1 ((uint32_t)0x00004000) /*!< External Event 3 bit 1*/ |
bogdanm | 86:04dd9b1680ae | 4424 | #define HRTIM_EEFR1_EE3FLTR_2 ((uint32_t)0x00008000) /*!< External Event 3 bit 2 */ |
bogdanm | 86:04dd9b1680ae | 4425 | #define HRTIM_EEFR1_EE3FLTR_3 ((uint32_t)0x00010000) /*!< External Event 3 bit 3 */ |
bogdanm | 86:04dd9b1680ae | 4426 | |
bogdanm | 86:04dd9b1680ae | 4427 | #define HRTIM_EEFR1_EE4LTCH ((uint32_t)0x00040000) /*!< External Event 4 latch */ |
bogdanm | 86:04dd9b1680ae | 4428 | #define HRTIM_EEFR1_EE4FLTR ((uint32_t)0x00780000) /*!< External Event 4 filter mask */ |
bogdanm | 86:04dd9b1680ae | 4429 | #define HRTIM_EEFR1_EE4FLTR_0 ((uint32_t)0x00080000) /*!< External Event 4 bit 0 */ |
bogdanm | 86:04dd9b1680ae | 4430 | #define HRTIM_EEFR1_EE4FLTR_1 ((uint32_t)0x00100000) /*!< External Event 4 bit 1*/ |
bogdanm | 86:04dd9b1680ae | 4431 | #define HRTIM_EEFR1_EE4FLTR_2 ((uint32_t)0x00200000) /*!< External Event 4 bit 2 */ |
bogdanm | 86:04dd9b1680ae | 4432 | #define HRTIM_EEFR1_EE4FLTR_3 ((uint32_t)0x00400000) /*!< External Event 4 bit 3 */ |
bogdanm | 86:04dd9b1680ae | 4433 | |
bogdanm | 86:04dd9b1680ae | 4434 | #define HRTIM_EEFR1_EE5LTCH ((uint32_t)0x01000000) /*!< External Event 5 latch */ |
bogdanm | 86:04dd9b1680ae | 4435 | #define HRTIM_EEFR1_EE5FLTR ((uint32_t)0x1E000000) /*!< External Event 5 filter mask */ |
bogdanm | 86:04dd9b1680ae | 4436 | #define HRTIM_EEFR1_EE5FLTR_0 ((uint32_t)0x02000000) /*!< External Event 5 bit 0 */ |
bogdanm | 86:04dd9b1680ae | 4437 | #define HRTIM_EEFR1_EE5FLTR_1 ((uint32_t)0x04000000) /*!< External Event 5 bit 1*/ |
bogdanm | 86:04dd9b1680ae | 4438 | #define HRTIM_EEFR1_EE5FLTR_2 ((uint32_t)0x08000000) /*!< External Event 5 bit 2 */ |
bogdanm | 86:04dd9b1680ae | 4439 | #define HRTIM_EEFR1_EE5FLTR_3 ((uint32_t)0x10000000) /*!< External Event 5 bit 3 */ |
bogdanm | 86:04dd9b1680ae | 4440 | |
bogdanm | 86:04dd9b1680ae | 4441 | /**** Bit definition for Slave external event filtering register 2 ***********/ |
bogdanm | 86:04dd9b1680ae | 4442 | #define HRTIM_EEFR2_EE6LTCH ((uint32_t)0x00000001) /*!< External Event 6 latch */ |
bogdanm | 86:04dd9b1680ae | 4443 | #define HRTIM_EEFR2_EE6FLTR ((uint32_t)0x0000001E) /*!< External Event 6 filter mask */ |
bogdanm | 86:04dd9b1680ae | 4444 | #define HRTIM_EEFR2_EE6FLTR_0 ((uint32_t)0x00000002) /*!< External Event 6 bit 0 */ |
bogdanm | 86:04dd9b1680ae | 4445 | #define HRTIM_EEFR2_EE6FLTR_1 ((uint32_t)0x00000004) /*!< External Event 6 bit 1*/ |
bogdanm | 86:04dd9b1680ae | 4446 | #define HRTIM_EEFR2_EE6FLTR_2 ((uint32_t)0x00000008) /*!< External Event 6 bit 2 */ |
bogdanm | 86:04dd9b1680ae | 4447 | #define HRTIM_EEFR2_EE6FLTR_3 ((uint32_t)0x00000010) /*!< External Event 6 bit 3 */ |
bogdanm | 86:04dd9b1680ae | 4448 | |
bogdanm | 86:04dd9b1680ae | 4449 | #define HRTIM_EEFR2_EE7LTCH ((uint32_t)0x00000040) /*!< External Event 7 latch */ |
bogdanm | 86:04dd9b1680ae | 4450 | #define HRTIM_EEFR2_EE7FLTR ((uint32_t)0x00000780) /*!< External Event 7 filter mask */ |
bogdanm | 86:04dd9b1680ae | 4451 | #define HRTIM_EEFR2_EE7FLTR_0 ((uint32_t)0x00000080) /*!< External Event 7 bit 0 */ |
bogdanm | 86:04dd9b1680ae | 4452 | #define HRTIM_EEFR2_EE7FLTR_1 ((uint32_t)0x00000100) /*!< External Event 7 bit 1*/ |
bogdanm | 86:04dd9b1680ae | 4453 | #define HRTIM_EEFR2_EE7FLTR_2 ((uint32_t)0x00000200) /*!< External Event 7 bit 2 */ |
bogdanm | 86:04dd9b1680ae | 4454 | #define HRTIM_EEFR2_EE7FLTR_3 ((uint32_t)0x00000400) /*!< External Event 7 bit 3 */ |
bogdanm | 86:04dd9b1680ae | 4455 | |
bogdanm | 86:04dd9b1680ae | 4456 | #define HRTIM_EEFR2_EE8LTCH ((uint32_t)0x00001000) /*!< External Event 8 latch */ |
bogdanm | 86:04dd9b1680ae | 4457 | #define HRTIM_EEFR2_EE8FLTR ((uint32_t)0x0001E000) /*!< External Event 8 filter mask */ |
bogdanm | 86:04dd9b1680ae | 4458 | #define HRTIM_EEFR2_EE8FLTR_0 ((uint32_t)0x00002000) /*!< External Event 8 bit 0 */ |
bogdanm | 86:04dd9b1680ae | 4459 | #define HRTIM_EEFR2_EE8FLTR_1 ((uint32_t)0x00004000) /*!< External Event 8 bit 1*/ |
bogdanm | 86:04dd9b1680ae | 4460 | #define HRTIM_EEFR2_EE8FLTR_2 ((uint32_t)0x00008000) /*!< External Event 8 bit 2 */ |
bogdanm | 86:04dd9b1680ae | 4461 | #define HRTIM_EEFR2_EE8FLTR_3 ((uint32_t)0x00010000) /*!< External Event 8 bit 3 */ |
bogdanm | 86:04dd9b1680ae | 4462 | |
bogdanm | 86:04dd9b1680ae | 4463 | #define HRTIM_EEFR2_EE9LTCH ((uint32_t)0x00040000) /*!< External Event 9 latch */ |
bogdanm | 86:04dd9b1680ae | 4464 | #define HRTIM_EEFR2_EE9FLTR ((uint32_t)0x00780000) /*!< External Event 9 filter mask */ |
bogdanm | 86:04dd9b1680ae | 4465 | #define HRTIM_EEFR2_EE9FLTR_0 ((uint32_t)0x00080000) /*!< External Event 9 bit 0 */ |
bogdanm | 86:04dd9b1680ae | 4466 | #define HRTIM_EEFR2_EE9FLTR_1 ((uint32_t)0x00100000) /*!< External Event 9 bit 1*/ |
bogdanm | 86:04dd9b1680ae | 4467 | #define HRTIM_EEFR2_EE9FLTR_2 ((uint32_t)0x00200000) /*!< External Event 9 bit 2 */ |
bogdanm | 86:04dd9b1680ae | 4468 | #define HRTIM_EEFR2_EE9FLTR_3 ((uint32_t)0x00400000) /*!< External Event 9 bit 3 */ |
bogdanm | 86:04dd9b1680ae | 4469 | |
bogdanm | 86:04dd9b1680ae | 4470 | #define HRTIM_EEFR2_EE10LTCH ((uint32_t)0x01000000) /*!< External Event 10 latch */ |
bogdanm | 86:04dd9b1680ae | 4471 | #define HRTIM_EEFR2_EE10FLTR ((uint32_t)0x1E000000) /*!< External Event 10 filter mask */ |
bogdanm | 86:04dd9b1680ae | 4472 | #define HRTIM_EEFR2_EE10FLTR_0 ((uint32_t)0x02000000) /*!< External Event 10 bit 0 */ |
bogdanm | 86:04dd9b1680ae | 4473 | #define HRTIM_EEFR2_EE10FLTR_1 ((uint32_t)0x04000000) /*!< External Event 10 bit 1*/ |
bogdanm | 86:04dd9b1680ae | 4474 | #define HRTIM_EEFR2_EE10FLTR_2 ((uint32_t)0x08000000) /*!< External Event 10 bit 2 */ |
bogdanm | 86:04dd9b1680ae | 4475 | #define HRTIM_EEFR2_EE10FLTR_3 ((uint32_t)0x10000000) /*!< External Event 10 bit 3 */ |
bogdanm | 86:04dd9b1680ae | 4476 | |
bogdanm | 86:04dd9b1680ae | 4477 | /**** Bit definition for Slave Timer reset register ***************************/ |
bogdanm | 86:04dd9b1680ae | 4478 | #define HRTIM_RSTR_UPDATE ((uint32_t)0x00000002) /*!< Timer update */ |
bogdanm | 86:04dd9b1680ae | 4479 | #define HRTIM_RSTR_CMP2 ((uint32_t)0x00000004) /*!< Timer compare2 */ |
bogdanm | 86:04dd9b1680ae | 4480 | #define HRTIM_RSTR_CMP4 ((uint32_t)0x00000008) /*!< Timer compare4 */ |
bogdanm | 86:04dd9b1680ae | 4481 | |
bogdanm | 86:04dd9b1680ae | 4482 | #define HRTIM_RSTR_MSTPER ((uint32_t)0x00000010) /*!< Master period */ |
bogdanm | 86:04dd9b1680ae | 4483 | #define HRTIM_RSTR_MSTCMP1 ((uint32_t)0x00000020) /*!< Master compare1 */ |
bogdanm | 86:04dd9b1680ae | 4484 | #define HRTIM_RSTR_MSTCMP2 ((uint32_t)0x00000040) /*!< Master compare2 */ |
bogdanm | 86:04dd9b1680ae | 4485 | #define HRTIM_RSTR_MSTCMP3 ((uint32_t)0x00000080) /*!< Master compare3 */ |
bogdanm | 86:04dd9b1680ae | 4486 | #define HRTIM_RSTR_MSTCMP4 ((uint32_t)0x00000100) /*!< Master compare4 */ |
bogdanm | 86:04dd9b1680ae | 4487 | |
bogdanm | 86:04dd9b1680ae | 4488 | #define HRTIM_RSTR_EXTEVNT1 ((uint32_t)0x00000200) /*!< External event 1 */ |
bogdanm | 86:04dd9b1680ae | 4489 | #define HRTIM_RSTR_EXTEVNT2 ((uint32_t)0x00000400) /*!< External event 2 */ |
bogdanm | 86:04dd9b1680ae | 4490 | #define HRTIM_RSTR_EXTEVNT3 ((uint32_t)0x00000800) /*!< External event 3 */ |
bogdanm | 86:04dd9b1680ae | 4491 | #define HRTIM_RSTR_EXTEVNT4 ((uint32_t)0x00001000) /*!< External event 4 */ |
bogdanm | 86:04dd9b1680ae | 4492 | #define HRTIM_RSTR_EXTEVNT5 ((uint32_t)0x00002000) /*!< External event 5 */ |
bogdanm | 86:04dd9b1680ae | 4493 | #define HRTIM_RSTR_EXTEVNT6 ((uint32_t)0x00004000) /*!< External event 6 */ |
bogdanm | 86:04dd9b1680ae | 4494 | #define HRTIM_RSTR_EXTEVNT7 ((uint32_t)0x00008000) /*!< External event 7 */ |
bogdanm | 86:04dd9b1680ae | 4495 | #define HRTIM_RSTR_EXTEVNT8 ((uint32_t)0x00010000) /*!< External event 8 */ |
bogdanm | 86:04dd9b1680ae | 4496 | #define HRTIM_RSTR_EXTEVNT9 ((uint32_t)0x00020000) /*!< External event 9 */ |
bogdanm | 86:04dd9b1680ae | 4497 | #define HRTIM_RSTR_EXTEVNT10 ((uint32_t)0x00040000) /*!< External event 10 */ |
bogdanm | 86:04dd9b1680ae | 4498 | |
bogdanm | 86:04dd9b1680ae | 4499 | #define HRTIM_RSTR_TIMBCMP1 ((uint32_t)0x00080000) /*!< Timer B compare 1 */ |
bogdanm | 86:04dd9b1680ae | 4500 | #define HRTIM_RSTR_TIMBCMP2 ((uint32_t)0x00100000) /*!< Timer B compare 2 */ |
bogdanm | 86:04dd9b1680ae | 4501 | #define HRTIM_RSTR_TIMBCMP4 ((uint32_t)0x00200000) /*!< Timer B compare 4 */ |
bogdanm | 86:04dd9b1680ae | 4502 | |
bogdanm | 86:04dd9b1680ae | 4503 | #define HRTIM_RSTR_TIMCCMP1 ((uint32_t)0x00400000) /*!< Timer C compare 1 */ |
bogdanm | 86:04dd9b1680ae | 4504 | #define HRTIM_RSTR_TIMCCMP2 ((uint32_t)0x00800000) /*!< Timer C compare 2 */ |
bogdanm | 86:04dd9b1680ae | 4505 | #define HRTIM_RSTR_TIMCCMP4 ((uint32_t)0x01000000) /*!< Timer C compare 4 */ |
bogdanm | 86:04dd9b1680ae | 4506 | |
bogdanm | 86:04dd9b1680ae | 4507 | #define HRTIM_RSTR_TIMDCMP1 ((uint32_t)0x02000000) /*!< Timer D compare 1 */ |
bogdanm | 86:04dd9b1680ae | 4508 | #define HRTIM_RSTR_TIMDCMP2 ((uint32_t)0x04000000) /*!< Timer D compare 2 */ |
bogdanm | 86:04dd9b1680ae | 4509 | #define HRTIM_RSTR_TIMDCMP4 ((uint32_t)0x08000000) /*!< Timer D compare 4 */ |
bogdanm | 86:04dd9b1680ae | 4510 | |
bogdanm | 86:04dd9b1680ae | 4511 | #define HRTIM_RSTR_TIMECMP1 ((uint32_t)0x10000000) /*!< Timer E compare 1 */ |
bogdanm | 86:04dd9b1680ae | 4512 | #define HRTIM_RSTR_TIMECMP2 ((uint32_t)0x20000000) /*!< Timer E compare 2 */ |
bogdanm | 86:04dd9b1680ae | 4513 | #define HRTIM_RSTR_TIMECMP4 ((uint32_t)0x40000000) /*!< Timer E compare 4 */ |
bogdanm | 86:04dd9b1680ae | 4514 | |
bogdanm | 86:04dd9b1680ae | 4515 | /**** Bit definition for Slave Timer Chopper register *************************/ |
bogdanm | 86:04dd9b1680ae | 4516 | #define HRTIM_CHPR_CARFRQ ((uint32_t)0x0000000F) /*!< Timer carrier frequency value */ |
bogdanm | 86:04dd9b1680ae | 4517 | #define HRTIM_CHPR_CARFRQ_0 ((uint32_t)0x00000001) /*!< Timer carrier frequency value bit 0 */ |
bogdanm | 86:04dd9b1680ae | 4518 | #define HRTIM_CHPR_CARFRQ_1 ((uint32_t)0x00000002) /*!< Timer carrier frequency value bit 1 */ |
bogdanm | 86:04dd9b1680ae | 4519 | #define HRTIM_CHPR_CARFRQ_2 ((uint32_t)0x00000004) /*!< Timer carrier frequency value bit 2 */ |
bogdanm | 86:04dd9b1680ae | 4520 | #define HRTIM_CHPR_CARFRQ_3 ((uint32_t)0x00000008) /*!< Timer carrier frequency value bit 3 */ |
bogdanm | 86:04dd9b1680ae | 4521 | |
bogdanm | 86:04dd9b1680ae | 4522 | #define HRTIM_CHPR_CARDTY ((uint32_t)0x00000070) /*!< Timer chopper duty cycle value */ |
bogdanm | 86:04dd9b1680ae | 4523 | #define HRTIM_CHPR_CARDTY_0 ((uint32_t)0x00000010) /*!< Timer chopper duty cycle value bit 0 */ |
bogdanm | 86:04dd9b1680ae | 4524 | #define HRTIM_CHPR_CARDTY_1 ((uint32_t)0x00000020) /*!< Timer chopper duty cycle value bit 1 */ |
bogdanm | 86:04dd9b1680ae | 4525 | #define HRTIM_CHPR_CARDTY_2 ((uint32_t)0x00000040) /*!< Timer chopper duty cycle value bit 2 */ |
bogdanm | 86:04dd9b1680ae | 4526 | |
bogdanm | 86:04dd9b1680ae | 4527 | #define HRTIM_CHPR_STRPW ((uint32_t)0x00000780) /*!< Timer start pulse width value */ |
bogdanm | 86:04dd9b1680ae | 4528 | #define HRTIM_CHPR_STRPW_0 ((uint32_t)0x00000080) /*!< Timer start pulse width value bit 0 */ |
bogdanm | 86:04dd9b1680ae | 4529 | #define HRTIM_CHPR_STRPW_1 ((uint32_t)0x00000100) /*!< Timer start pulse width value bit 1 */ |
bogdanm | 86:04dd9b1680ae | 4530 | #define HRTIM_CHPR_STRPW_2 ((uint32_t)0x00000200) /*!< Timer start pulse width value bit 2 */ |
bogdanm | 86:04dd9b1680ae | 4531 | #define HRTIM_CHPR_STRPW_3 ((uint32_t)0x00000400) /*!< Timer start pulse width value bit 3 */ |
bogdanm | 86:04dd9b1680ae | 4532 | |
bogdanm | 86:04dd9b1680ae | 4533 | /**** Bit definition for Slave Timer Capture 1 control register ***************/ |
bogdanm | 86:04dd9b1680ae | 4534 | #define HRTIM_CPT1CR_SWCPT ((uint32_t)0x00000001) /*!< Software capture */ |
bogdanm | 86:04dd9b1680ae | 4535 | #define HRTIM_CPT1CR_UPDCPT ((uint32_t)0x00000002) /*!< Update capture */ |
bogdanm | 86:04dd9b1680ae | 4536 | #define HRTIM_CPT1CR_EXEV1CPT ((uint32_t)0x00000004) /*!< External event 1 capture */ |
bogdanm | 86:04dd9b1680ae | 4537 | #define HRTIM_CPT1CR_EXEV2CPT ((uint32_t)0x00000008) /*!< External event 2 capture */ |
bogdanm | 86:04dd9b1680ae | 4538 | #define HRTIM_CPT1CR_EXEV3CPT ((uint32_t)0x00000010) /*!< External event 3 capture */ |
bogdanm | 86:04dd9b1680ae | 4539 | #define HRTIM_CPT1CR_EXEV4CPT ((uint32_t)0x00000020) /*!< External event 4 capture */ |
bogdanm | 86:04dd9b1680ae | 4540 | #define HRTIM_CPT1CR_EXEV5CPT ((uint32_t)0x00000040) /*!< External event 5 capture */ |
bogdanm | 86:04dd9b1680ae | 4541 | #define HRTIM_CPT1CR_EXEV6CPT ((uint32_t)0x00000080) /*!< External event 6 capture */ |
bogdanm | 86:04dd9b1680ae | 4542 | #define HRTIM_CPT1CR_EXEV7CPT ((uint32_t)0x00000100) /*!< External event 7 capture */ |
bogdanm | 86:04dd9b1680ae | 4543 | #define HRTIM_CPT1CR_EXEV8CPT ((uint32_t)0x00000200) /*!< External event 8 capture */ |
bogdanm | 86:04dd9b1680ae | 4544 | #define HRTIM_CPT1CR_EXEV9CPT ((uint32_t)0x00000400) /*!< External event 9 capture */ |
bogdanm | 86:04dd9b1680ae | 4545 | #define HRTIM_CPT1CR_EXEV10CPT ((uint32_t)0x00000800) /*!< External event 10 capture */ |
bogdanm | 86:04dd9b1680ae | 4546 | |
bogdanm | 86:04dd9b1680ae | 4547 | #define HRTIM_CPT1CR_TA1SET ((uint32_t)0x00001000) /*!< Timer A output 1 set */ |
bogdanm | 86:04dd9b1680ae | 4548 | #define HRTIM_CPT1CR_TA1RST ((uint32_t)0x00002000) /*!< Timer A output 1 reset */ |
bogdanm | 86:04dd9b1680ae | 4549 | #define HRTIM_CPT1CR_TIMACMP1 ((uint32_t)0x00004000) /*!< Timer A compare 1 */ |
bogdanm | 86:04dd9b1680ae | 4550 | #define HRTIM_CPT1CR_TIMACMP2 ((uint32_t)0x00008000) /*!< Timer A compare 2 */ |
bogdanm | 86:04dd9b1680ae | 4551 | |
bogdanm | 86:04dd9b1680ae | 4552 | #define HRTIM_CPT1CR_TB1SET ((uint32_t)0x00010000) /*!< Timer B output 1 set */ |
bogdanm | 86:04dd9b1680ae | 4553 | #define HRTIM_CPT1CR_TB1RST ((uint32_t)0x00020000) /*!< Timer B output 1 reset */ |
bogdanm | 86:04dd9b1680ae | 4554 | #define HRTIM_CPT1CR_TIMBCMP1 ((uint32_t)0x00040000) /*!< Timer B compare 1 */ |
bogdanm | 86:04dd9b1680ae | 4555 | #define HRTIM_CPT1CR_TIMBCMP2 ((uint32_t)0x00080000) /*!< Timer B compare 2 */ |
bogdanm | 86:04dd9b1680ae | 4556 | |
bogdanm | 86:04dd9b1680ae | 4557 | #define HRTIM_CPT1CR_TC1SET ((uint32_t)0x00100000) /*!< Timer C output 1 set */ |
bogdanm | 86:04dd9b1680ae | 4558 | #define HRTIM_CPT1CR_TC1RST ((uint32_t)0x00200000) /*!< Timer C output 1 reset */ |
bogdanm | 86:04dd9b1680ae | 4559 | #define HRTIM_CPT1CR_TIMCCMP1 ((uint32_t)0x00400000) /*!< Timer C compare 1 */ |
bogdanm | 86:04dd9b1680ae | 4560 | #define HRTIM_CPT1CR_TIMCCMP2 ((uint32_t)0x00800000) /*!< Timer C compare 2 */ |
bogdanm | 86:04dd9b1680ae | 4561 | |
bogdanm | 86:04dd9b1680ae | 4562 | #define HRTIM_CPT1CR_TD1SET ((uint32_t)0x01000000) /*!< Timer D output 1 set */ |
bogdanm | 86:04dd9b1680ae | 4563 | #define HRTIM_CPT1CR_TD1RST ((uint32_t)0x02000000) /*!< Timer D output 1 reset */ |
bogdanm | 86:04dd9b1680ae | 4564 | #define HRTIM_CPT1CR_TIMDCMP1 ((uint32_t)0x04000000) /*!< Timer D compare 1 */ |
bogdanm | 86:04dd9b1680ae | 4565 | #define HRTIM_CPT1CR_TIMDCMP2 ((uint32_t)0x08000000) /*!< Timer D compare 2 */ |
bogdanm | 86:04dd9b1680ae | 4566 | |
bogdanm | 86:04dd9b1680ae | 4567 | #define HRTIM_CPT1CR_TE1SET ((uint32_t)0x10000000) /*!< Timer E output 1 set */ |
bogdanm | 86:04dd9b1680ae | 4568 | #define HRTIM_CPT1CR_TE1RST ((uint32_t)0x20000000) /*!< Timer E output 1 reset */ |
bogdanm | 86:04dd9b1680ae | 4569 | #define HRTIM_CPT1CR_TIMECMP1 ((uint32_t)0x40000000) /*!< Timer E compare 1 */ |
bogdanm | 86:04dd9b1680ae | 4570 | #define HRTIM_CPT1CR_TIMECMP2 ((uint32_t)0x80000000) /*!< Timer E compare 2 */ |
bogdanm | 86:04dd9b1680ae | 4571 | |
bogdanm | 86:04dd9b1680ae | 4572 | /**** Bit definition for Slave Timer Capture 2 control register ***************/ |
bogdanm | 86:04dd9b1680ae | 4573 | #define HRTIM_CPT2CR_SWCPT ((uint32_t)0x00000001) /*!< Software capture */ |
bogdanm | 86:04dd9b1680ae | 4574 | #define HRTIM_CPT2CR_UPDCPT ((uint32_t)0x00000002) /*!< Update capture */ |
bogdanm | 86:04dd9b1680ae | 4575 | #define HRTIM_CPT2CR_EXEV1CPT ((uint32_t)0x00000004) /*!< External event 1 capture */ |
bogdanm | 86:04dd9b1680ae | 4576 | #define HRTIM_CPT2CR_EXEV2CPT ((uint32_t)0x00000008) /*!< External event 2 capture */ |
bogdanm | 86:04dd9b1680ae | 4577 | #define HRTIM_CPT2CR_EXEV3CPT ((uint32_t)0x00000010) /*!< External event 3 capture */ |
bogdanm | 86:04dd9b1680ae | 4578 | #define HRTIM_CPT2CR_EXEV4CPT ((uint32_t)0x00000020) /*!< External event 4 capture */ |
bogdanm | 86:04dd9b1680ae | 4579 | #define HRTIM_CPT2CR_EXEV5CPT ((uint32_t)0x00000040) /*!< External event 5 capture */ |
bogdanm | 86:04dd9b1680ae | 4580 | #define HRTIM_CPT2CR_EXEV6CPT ((uint32_t)0x00000080) /*!< External event 6 capture */ |
bogdanm | 86:04dd9b1680ae | 4581 | #define HRTIM_CPT2CR_EXEV7CPT ((uint32_t)0x00000100) /*!< External event 7 capture */ |
bogdanm | 86:04dd9b1680ae | 4582 | #define HRTIM_CPT2CR_EXEV8CPT ((uint32_t)0x00000200) /*!< External event 8 capture */ |
bogdanm | 86:04dd9b1680ae | 4583 | #define HRTIM_CPT2CR_EXEV9CPT ((uint32_t)0x00000400) /*!< External event 9 capture */ |
bogdanm | 86:04dd9b1680ae | 4584 | #define HRTIM_CPT2CR_EXEV10CPT ((uint32_t)0x00000800) /*!< External event 10 capture */ |
bogdanm | 86:04dd9b1680ae | 4585 | |
bogdanm | 86:04dd9b1680ae | 4586 | #define HRTIM_CPT2CR_TA1SET ((uint32_t)0x00001000) /*!< Timer A output 1 set */ |
bogdanm | 86:04dd9b1680ae | 4587 | #define HRTIM_CPT2CR_TA1RST ((uint32_t)0x00002000) /*!< Timer A output 1 reset */ |
bogdanm | 86:04dd9b1680ae | 4588 | #define HRTIM_CPT2CR_TIMACMP1 ((uint32_t)0x00004000) /*!< Timer A compare 1 */ |
bogdanm | 86:04dd9b1680ae | 4589 | #define HRTIM_CPT2CR_TIMACMP2 ((uint32_t)0x00008000) /*!< Timer A compare 2 */ |
bogdanm | 86:04dd9b1680ae | 4590 | |
bogdanm | 86:04dd9b1680ae | 4591 | #define HRTIM_CPT2CR_TB1SET ((uint32_t)0x00010000) /*!< Timer B output 1 set */ |
bogdanm | 86:04dd9b1680ae | 4592 | #define HRTIM_CPT2CR_TB1RST ((uint32_t)0x00020000) /*!< Timer B output 1 reset */ |
bogdanm | 86:04dd9b1680ae | 4593 | #define HRTIM_CPT2CR_TIMBCMP1 ((uint32_t)0x00040000) /*!< Timer B compare 1 */ |
bogdanm | 86:04dd9b1680ae | 4594 | #define HRTIM_CPT2CR_TIMBCMP2 ((uint32_t)0x00080000) /*!< Timer B compare 2 */ |
bogdanm | 86:04dd9b1680ae | 4595 | |
bogdanm | 86:04dd9b1680ae | 4596 | #define HRTIM_CPT2CR_TC1SET ((uint32_t)0x00100000) /*!< Timer C output 1 set */ |
bogdanm | 86:04dd9b1680ae | 4597 | #define HRTIM_CPT2CR_TC1RST ((uint32_t)0x00200000) /*!< Timer C output 1 reset */ |
bogdanm | 86:04dd9b1680ae | 4598 | #define HRTIM_CPT2CR_TIMCCMP1 ((uint32_t)0x00400000) /*!< Timer C compare 1 */ |
bogdanm | 86:04dd9b1680ae | 4599 | #define HRTIM_CPT2CR_TIMCCMP2 ((uint32_t)0x00800000) /*!< Timer C compare 2 */ |
bogdanm | 86:04dd9b1680ae | 4600 | |
bogdanm | 86:04dd9b1680ae | 4601 | #define HRTIM_CPT2CR_TD1SET ((uint32_t)0x01000000) /*!< Timer D output 1 set */ |
bogdanm | 86:04dd9b1680ae | 4602 | #define HRTIM_CPT2CR_TD1RST ((uint32_t)0x02000000) /*!< Timer D output 1 reset */ |
bogdanm | 86:04dd9b1680ae | 4603 | #define HRTIM_CPT2CR_TIMDCMP1 ((uint32_t)0x04000000) /*!< Timer D compare 1 */ |
bogdanm | 86:04dd9b1680ae | 4604 | #define HRTIM_CPT2CR_TIMDCMP2 ((uint32_t)0x08000000) /*!< Timer D compare 2 */ |
bogdanm | 86:04dd9b1680ae | 4605 | |
bogdanm | 86:04dd9b1680ae | 4606 | #define HRTIM_CPT2CR_TE1SET ((uint32_t)0x10000000) /*!< Timer E output 1 set */ |
bogdanm | 86:04dd9b1680ae | 4607 | #define HRTIM_CPT2CR_TE1RST ((uint32_t)0x20000000) /*!< Timer E output 1 reset */ |
bogdanm | 86:04dd9b1680ae | 4608 | #define HRTIM_CPT2CR_TIMECMP1 ((uint32_t)0x40000000) /*!< Timer E compare 1 */ |
bogdanm | 86:04dd9b1680ae | 4609 | #define HRTIM_CPT2CR_TIMECMP2 ((uint32_t)0x80000000) /*!< Timer E compare 2 */ |
bogdanm | 86:04dd9b1680ae | 4610 | |
bogdanm | 86:04dd9b1680ae | 4611 | /**** Bit definition for Slave Timer Output register **************************/ |
bogdanm | 86:04dd9b1680ae | 4612 | #define HRTIM_OUTR_POL1 ((uint32_t)0x00000002) /*!< Slave output 1 polarity */ |
bogdanm | 86:04dd9b1680ae | 4613 | #define HRTIM_OUTR_IDLM1 ((uint32_t)0x00000004) /*!< Slave output 1 idle mode */ |
bogdanm | 86:04dd9b1680ae | 4614 | #define HRTIM_OUTR_IDLES1 ((uint32_t)0x00000008) /*!< Slave output 1 idle state */ |
bogdanm | 86:04dd9b1680ae | 4615 | #define HRTIM_OUTR_FAULT1 ((uint32_t)0x00000030) /*!< Slave output 1 fault state */ |
bogdanm | 86:04dd9b1680ae | 4616 | #define HRTIM_OUTR_FAULT1_0 ((uint32_t)0x00000010) /*!< Slave output 1 fault state bit 0 */ |
bogdanm | 86:04dd9b1680ae | 4617 | #define HRTIM_OUTR_FAULT1_1 ((uint32_t)0x00000020) /*!< Slave output 1 fault state bit 1 */ |
bogdanm | 86:04dd9b1680ae | 4618 | #define HRTIM_OUTR_CHP1 ((uint32_t)0x00000040) /*!< Slave output 1 chopper enable */ |
bogdanm | 86:04dd9b1680ae | 4619 | #define HRTIM_OUTR_DIDL1 ((uint32_t)0x00000080) /*!< Slave output 1 dead time idle */ |
bogdanm | 86:04dd9b1680ae | 4620 | |
bogdanm | 86:04dd9b1680ae | 4621 | #define HRTIM_OUTR_DTEN ((uint32_t)0x00000100) /*!< Slave output deadtime enable */ |
bogdanm | 86:04dd9b1680ae | 4622 | #define HRTIM_OUTR_DLYPRTEN ((uint32_t)0x00000200) /*!< Slave output delay protection enable */ |
bogdanm | 86:04dd9b1680ae | 4623 | #define HRTIM_OUTR_DLYPRT ((uint32_t)0x00001C00) /*!< Slave output delay protection */ |
bogdanm | 86:04dd9b1680ae | 4624 | #define HRTIM_OUTR_DLYPRT_0 ((uint32_t)0x00000400) /*!< Slave output delay protection bit 0 */ |
bogdanm | 86:04dd9b1680ae | 4625 | #define HRTIM_OUTR_DLYPRT_1 ((uint32_t)0x00000800) /*!< Slave output delay protection bit 1 */ |
bogdanm | 86:04dd9b1680ae | 4626 | #define HRTIM_OUTR_DLYPRT_2 ((uint32_t)0x00001000) /*!< Slave output delay protection bit 2 */ |
bogdanm | 86:04dd9b1680ae | 4627 | |
bogdanm | 86:04dd9b1680ae | 4628 | #define HRTIM_OUTR_POL2 ((uint32_t)0x00020000) /*!< Slave output 2 polarity */ |
bogdanm | 86:04dd9b1680ae | 4629 | #define HRTIM_OUTR_IDLM2 ((uint32_t)0x00040000) /*!< Slave output 2 idle mode */ |
bogdanm | 86:04dd9b1680ae | 4630 | #define HRTIM_OUTR_IDLES2 ((uint32_t)0x00080000) /*!< Slave output 2 idle state */ |
bogdanm | 86:04dd9b1680ae | 4631 | #define HRTIM_OUTR_FAULT2 ((uint32_t)0x00300000) /*!< Slave output 2 fault state */ |
bogdanm | 86:04dd9b1680ae | 4632 | #define HRTIM_OUTR_FAULT2_0 ((uint32_t)0x00100000) /*!< Slave output 2 fault state bit 0 */ |
bogdanm | 86:04dd9b1680ae | 4633 | #define HRTIM_OUTR_FAULT2_1 ((uint32_t)0x00200000) /*!< Slave output 2 fault state bit 1 */ |
bogdanm | 86:04dd9b1680ae | 4634 | #define HRTIM_OUTR_CHP2 ((uint32_t)0x00400000) /*!< Slave output 2 chopper enable */ |
bogdanm | 86:04dd9b1680ae | 4635 | #define HRTIM_OUTR_DIDL2 ((uint32_t)0x00800000) /*!< Slave output 2 dead time idle */ |
bogdanm | 86:04dd9b1680ae | 4636 | |
bogdanm | 86:04dd9b1680ae | 4637 | /**** Bit definition for Slave Timer Fault register ***************************/ |
bogdanm | 86:04dd9b1680ae | 4638 | #define HRTIM_FLTR_FLT1EN ((uint32_t)0x00000001) /*!< Fault 1 enable */ |
bogdanm | 86:04dd9b1680ae | 4639 | #define HRTIM_FLTR_FLT2EN ((uint32_t)0x00000002) /*!< Fault 2 enable */ |
bogdanm | 86:04dd9b1680ae | 4640 | #define HRTIM_FLTR_FLT3EN ((uint32_t)0x00000004) /*!< Fault 3 enable */ |
bogdanm | 86:04dd9b1680ae | 4641 | #define HRTIM_FLTR_FLT4EN ((uint32_t)0x00000008) /*!< Fault 4 enable */ |
bogdanm | 86:04dd9b1680ae | 4642 | #define HRTIM_FLTR_FLT5EN ((uint32_t)0x00000010) /*!< Fault 5 enable */ |
bogdanm | 86:04dd9b1680ae | 4643 | #define HRTIM_FLTR_FLTLCK ((uint32_t)0x80000000) /*!< Fault sources lock */ |
bogdanm | 86:04dd9b1680ae | 4644 | |
bogdanm | 86:04dd9b1680ae | 4645 | /**** Bit definition for Common HRTIM Timer control register 1 ****************/ |
bogdanm | 86:04dd9b1680ae | 4646 | #define HRTIM_CR1_MUDIS ((uint32_t)0x00000001) /*!< Master update disable*/ |
bogdanm | 86:04dd9b1680ae | 4647 | #define HRTIM_CR1_TAUDIS ((uint32_t)0x00000002) /*!< Timer A update disable*/ |
bogdanm | 86:04dd9b1680ae | 4648 | #define HRTIM_CR1_TBUDIS ((uint32_t)0x00000004) /*!< Timer B update disable*/ |
bogdanm | 86:04dd9b1680ae | 4649 | #define HRTIM_CR1_TCUDIS ((uint32_t)0x00000008) /*!< Timer C update disable*/ |
bogdanm | 86:04dd9b1680ae | 4650 | #define HRTIM_CR1_TDUDIS ((uint32_t)0x00000010) /*!< Timer D update disable*/ |
bogdanm | 86:04dd9b1680ae | 4651 | #define HRTIM_CR1_TEUDIS ((uint32_t)0x00000020) /*!< Timer E update disable*/ |
bogdanm | 86:04dd9b1680ae | 4652 | #define HRTIM_CR1_ADC1USRC ((uint32_t)0x00070000) /*!< ADC Trigger 1 update source */ |
bogdanm | 86:04dd9b1680ae | 4653 | #define HRTIM_CR1_ADC1USRC_0 ((uint32_t)0x00010000) /*!< ADC Trigger 1 update source bit 0 */ |
bogdanm | 86:04dd9b1680ae | 4654 | #define HRTIM_CR1_ADC1USRC_1 ((uint32_t)0x00020000) /*!< ADC Trigger 1 update source bit 1 */ |
bogdanm | 86:04dd9b1680ae | 4655 | #define HRTIM_CR1_ADC1USRC_2 ((uint32_t)0x00040000) /*!< ADC Trigger 1 update source bit 2 */ |
bogdanm | 86:04dd9b1680ae | 4656 | #define HRTIM_CR1_ADC2USRC ((uint32_t)0x00380000) /*!< ADC Trigger 2 update source */ |
bogdanm | 86:04dd9b1680ae | 4657 | #define HRTIM_CR1_ADC2USRC_0 ((uint32_t)0x00080000) /*!< ADC Trigger 2 update source bit 0 */ |
bogdanm | 86:04dd9b1680ae | 4658 | #define HRTIM_CR1_ADC2USRC_1 ((uint32_t)0x00100000) /*!< ADC Trigger 2 update source bit 1 */ |
bogdanm | 86:04dd9b1680ae | 4659 | #define HRTIM_CR1_ADC2USRC_2 ((uint32_t)0x00200000) /*!< ADC Trigger 2 update source bit 2 */ |
bogdanm | 86:04dd9b1680ae | 4660 | #define HRTIM_CR1_ADC3USRC ((uint32_t)0x01C00000) /*!< ADC Trigger 3 update source */ |
bogdanm | 86:04dd9b1680ae | 4661 | #define HRTIM_CR1_ADC3USRC_0 ((uint32_t)0x00400000) /*!< ADC Trigger 3 update source bit 0 */ |
bogdanm | 86:04dd9b1680ae | 4662 | #define HRTIM_CR1_ADC3USRC_1 ((uint32_t)0x00800000) /*!< ADC Trigger 3 update source bit 1 */ |
bogdanm | 86:04dd9b1680ae | 4663 | #define HRTIM_CR1_ADC3USRC_2 ((uint32_t)0x01000000) /*!< ADC Trigger 3 update source bit 2 */ |
bogdanm | 86:04dd9b1680ae | 4664 | #define HRTIM_CR1_ADC4USRC ((uint32_t)0x0E000000) /*!< ADC Trigger 4 update source */ |
bogdanm | 86:04dd9b1680ae | 4665 | #define HRTIM_CR1_ADC4USRC_0 ((uint32_t)0x02000000) /*!< ADC Trigger 4 update source bit 0 */ |
bogdanm | 86:04dd9b1680ae | 4666 | #define HRTIM_CR1_ADC4USRC_1 ((uint32_t)0x04000000) /*!< ADC Trigger 4 update source bit 1 */ |
bogdanm | 86:04dd9b1680ae | 4667 | #define HRTIM_CR1_ADC4USRC_2 ((uint32_t)0x0800000) /*!< ADC Trigger 4 update source bit 2 */ |
bogdanm | 86:04dd9b1680ae | 4668 | |
bogdanm | 86:04dd9b1680ae | 4669 | /**** Bit definition for Common HRTIM Timer control register 2 ****************/ |
bogdanm | 86:04dd9b1680ae | 4670 | #define HRTIM_CR2_MSWU ((uint32_t)0x00000001) /*!< Master software update */ |
bogdanm | 86:04dd9b1680ae | 4671 | #define HRTIM_CR2_TASWU ((uint32_t)0x00000002) /*!< Timer A software update */ |
bogdanm | 86:04dd9b1680ae | 4672 | #define HRTIM_CR2_TBSWU ((uint32_t)0x00000004) /*!< Timer B software update */ |
bogdanm | 86:04dd9b1680ae | 4673 | #define HRTIM_CR2_TCSWU ((uint32_t)0x00000008) /*!< Timer C software update */ |
bogdanm | 86:04dd9b1680ae | 4674 | #define HRTIM_CR2_TDSWU ((uint32_t)0x00000010) /*!< Timer D software update */ |
bogdanm | 86:04dd9b1680ae | 4675 | #define HRTIM_CR2_TESWU ((uint32_t)0x00000020) /*!< Timer E software update */ |
bogdanm | 86:04dd9b1680ae | 4676 | #define HRTIM_CR2_MRST ((uint32_t)0x00000100) /*!< Master count software reset */ |
bogdanm | 86:04dd9b1680ae | 4677 | #define HRTIM_CR2_TARST ((uint32_t)0x00000200) /*!< Timer A count software reset */ |
bogdanm | 86:04dd9b1680ae | 4678 | #define HRTIM_CR2_TBRST ((uint32_t)0x00000400) /*!< Timer B count software reset */ |
bogdanm | 86:04dd9b1680ae | 4679 | #define HRTIM_CR2_TCRST ((uint32_t)0x00000800) /*!< Timer C count software reset */ |
bogdanm | 86:04dd9b1680ae | 4680 | #define HRTIM_CR2_TDRST ((uint32_t)0x00001000) /*!< Timer D count software reset */ |
bogdanm | 86:04dd9b1680ae | 4681 | #define HRTIM_CR2_TERST ((uint32_t)0x00002000) /*!< Timer E count software reset */ |
bogdanm | 86:04dd9b1680ae | 4682 | |
bogdanm | 86:04dd9b1680ae | 4683 | /**** Bit definition for Common HRTIM Timer interrupt status register *********/ |
bogdanm | 86:04dd9b1680ae | 4684 | #define HRTIM_ISR_FLT1 ((uint32_t)0x00000001) /*!< Fault 1 interrupt flag */ |
bogdanm | 86:04dd9b1680ae | 4685 | #define HRTIM_ISR_FLT2 ((uint32_t)0x00000002) /*!< Fault 2 interrupt flag */ |
bogdanm | 86:04dd9b1680ae | 4686 | #define HRTIM_ISR_FLT3 ((uint32_t)0x00000004) /*!< Fault 3 interrupt flag */ |
bogdanm | 86:04dd9b1680ae | 4687 | #define HRTIM_ISR_FLT4 ((uint32_t)0x00000008) /*!< Fault 4 interrupt flag */ |
bogdanm | 86:04dd9b1680ae | 4688 | #define HRTIM_ISR_FLT5 ((uint32_t)0x00000010) /*!< Fault 5 interrupt flag */ |
bogdanm | 86:04dd9b1680ae | 4689 | #define HRTIM_ISR_SYSFLT ((uint32_t)0x00000020) /*!< System Fault interrupt flag */ |
bogdanm | 86:04dd9b1680ae | 4690 | #define HRTIM_ISR_DLLRDY ((uint32_t)0x00010000) /*!< DLL ready interrupt flag */ |
bogdanm | 86:04dd9b1680ae | 4691 | #define HRTIM_ISR_BMPER ((uint32_t)0x00020000) /*!< Burst mode period interrupt flag */ |
bogdanm | 86:04dd9b1680ae | 4692 | |
bogdanm | 86:04dd9b1680ae | 4693 | /**** Bit definition for Common HRTIM Timer interrupt clear register **********/ |
bogdanm | 86:04dd9b1680ae | 4694 | #define HRTIM_ICR_FLT1C ((uint32_t)0x00000001) /*!< Fault 1 interrupt flag clear */ |
bogdanm | 86:04dd9b1680ae | 4695 | #define HRTIM_ICR_FLT2C ((uint32_t)0x00000002) /*!< Fault 2 interrupt flag clear */ |
bogdanm | 86:04dd9b1680ae | 4696 | #define HRTIM_ICR_FLT3C ((uint32_t)0x00000004) /*!< Fault 3 interrupt flag clear */ |
bogdanm | 86:04dd9b1680ae | 4697 | #define HRTIM_ICR_FLT4C ((uint32_t)0x00000008) /*!< Fault 4 interrupt flag clear */ |
bogdanm | 86:04dd9b1680ae | 4698 | #define HRTIM_ICR_FLT5C ((uint32_t)0x00000010) /*!< Fault 5 interrupt flag clear */ |
bogdanm | 86:04dd9b1680ae | 4699 | #define HRTIM_ICR_SYSFLTC ((uint32_t)0x00000020) /*!< System Fault interrupt flag clear */ |
bogdanm | 86:04dd9b1680ae | 4700 | #define HRTIM_ICR_DLLRDYC ((uint32_t)0x00010000) /*!< DLL ready interrupt flag clear */ |
bogdanm | 86:04dd9b1680ae | 4701 | #define HRTIM_ICR_BMPERC ((uint32_t)0x00020000) /*!< Burst mode period interrupt flag clear */ |
bogdanm | 86:04dd9b1680ae | 4702 | |
bogdanm | 86:04dd9b1680ae | 4703 | /**** Bit definition for Common HRTIM Timer interrupt enable register *********/ |
bogdanm | 86:04dd9b1680ae | 4704 | #define HRTIM_IER_FLT1 ((uint32_t)0x00000001) /*!< Fault 1 interrupt enable */ |
bogdanm | 86:04dd9b1680ae | 4705 | #define HRTIM_IER_FLT2 ((uint32_t)0x00000002) /*!< Fault 2 interrupt enable */ |
bogdanm | 86:04dd9b1680ae | 4706 | #define HRTIM_IER_FLT3 ((uint32_t)0x00000004) /*!< Fault 3 interrupt enable */ |
bogdanm | 86:04dd9b1680ae | 4707 | #define HRTIM_IER_FLT4 ((uint32_t)0x00000008) /*!< Fault 4 interrupt enable */ |
bogdanm | 86:04dd9b1680ae | 4708 | #define HRTIM_IER_FLT5 ((uint32_t)0x00000010) /*!< Fault 5 interrupt enable */ |
bogdanm | 86:04dd9b1680ae | 4709 | #define HRTIM_IER_SYSFLT ((uint32_t)0x00000020) /*!< System Fault interrupt enable */ |
bogdanm | 86:04dd9b1680ae | 4710 | #define HRTIM_IER_DLLRDY ((uint32_t)0x00010000) /*!< DLL ready interrupt enable */ |
bogdanm | 86:04dd9b1680ae | 4711 | #define HRTIM_IER_BMPER ((uint32_t)0x00020000) /*!< Burst mode period interrupt enable */ |
bogdanm | 86:04dd9b1680ae | 4712 | |
bogdanm | 86:04dd9b1680ae | 4713 | /**** Bit definition for Common HRTIM Timer output enable register ************/ |
bogdanm | 86:04dd9b1680ae | 4714 | #define HRTIM_OENR_TA1OEN ((uint32_t)0x00000001) /*!< Timer A Output 1 enable */ |
bogdanm | 86:04dd9b1680ae | 4715 | #define HRTIM_OENR_TA2OEN ((uint32_t)0x00000002) /*!< Timer A Output 2 enable */ |
bogdanm | 86:04dd9b1680ae | 4716 | #define HRTIM_OENR_TB1OEN ((uint32_t)0x00000004) /*!< Timer B Output 1 enable */ |
bogdanm | 86:04dd9b1680ae | 4717 | #define HRTIM_OENR_TB2OEN ((uint32_t)0x00000008) /*!< Timer B Output 2 enable */ |
bogdanm | 86:04dd9b1680ae | 4718 | #define HRTIM_OENR_TC1OEN ((uint32_t)0x00000010) /*!< Timer C Output 1 enable */ |
bogdanm | 86:04dd9b1680ae | 4719 | #define HRTIM_OENR_TC2OEN ((uint32_t)0x00000020) /*!< Timer C Output 2 enable */ |
bogdanm | 86:04dd9b1680ae | 4720 | #define HRTIM_OENR_TD1OEN ((uint32_t)0x00000040) /*!< Timer D Output 1 enable */ |
bogdanm | 86:04dd9b1680ae | 4721 | #define HRTIM_OENR_TD2OEN ((uint32_t)0x00000080) /*!< Timer D Output 2 enable */ |
bogdanm | 86:04dd9b1680ae | 4722 | #define HRTIM_OENR_TE1OEN ((uint32_t)0x00000100) /*!< Timer E Output 1 enable */ |
bogdanm | 86:04dd9b1680ae | 4723 | #define HRTIM_OENR_TE2OEN ((uint32_t)0x00000200) /*!< Timer E Output 2 enable */ |
bogdanm | 86:04dd9b1680ae | 4724 | |
bogdanm | 86:04dd9b1680ae | 4725 | /**** Bit definition for Common HRTIM Timer output disable register ***********/ |
bogdanm | 86:04dd9b1680ae | 4726 | #define HRTIM_ODISR_TA1ODIS ((uint32_t)0x00000001) /*!< Timer A Output 1 disable */ |
bogdanm | 86:04dd9b1680ae | 4727 | #define HRTIM_ODISR_TA2ODIS ((uint32_t)0x00000002) /*!< Timer A Output 2 disable */ |
bogdanm | 86:04dd9b1680ae | 4728 | #define HRTIM_ODISR_TB1ODIS ((uint32_t)0x00000004) /*!< Timer B Output 1 disable */ |
bogdanm | 86:04dd9b1680ae | 4729 | #define HRTIM_ODISR_TB2ODIS ((uint32_t)0x00000008) /*!< Timer B Output 2 disable */ |
bogdanm | 86:04dd9b1680ae | 4730 | #define HRTIM_ODISR_TC1ODIS ((uint32_t)0x00000010) /*!< Timer C Output 1 disable */ |
bogdanm | 86:04dd9b1680ae | 4731 | #define HRTIM_ODISR_TC2ODIS ((uint32_t)0x00000020) /*!< Timer C Output 2 disable */ |
bogdanm | 86:04dd9b1680ae | 4732 | #define HRTIM_ODISR_TD1ODIS ((uint32_t)0x00000040) /*!< Timer D Output 1 disable */ |
bogdanm | 86:04dd9b1680ae | 4733 | #define HRTIM_ODISR_TD2ODIS ((uint32_t)0x00000080) /*!< Timer D Output 2 disable */ |
bogdanm | 86:04dd9b1680ae | 4734 | #define HRTIM_ODISR_TE1ODIS ((uint32_t)0x00000100) /*!< Timer E Output 1 disable */ |
bogdanm | 86:04dd9b1680ae | 4735 | #define HRTIM_ODISR_TE2ODIS ((uint32_t)0x00000200) /*!< Timer E Output 2 disable */ |
bogdanm | 86:04dd9b1680ae | 4736 | |
bogdanm | 86:04dd9b1680ae | 4737 | /**** Bit definition for Common HRTIM Timer output disable status register *****/ |
bogdanm | 86:04dd9b1680ae | 4738 | #define HRTIM_ODSR_TA1ODS ((uint32_t)0x00000001) /*!< Timer A Output 1 disable status */ |
bogdanm | 86:04dd9b1680ae | 4739 | #define HRTIM_ODSR_TA2ODS ((uint32_t)0x00000002) /*!< Timer A Output 2 disable status */ |
bogdanm | 86:04dd9b1680ae | 4740 | #define HRTIM_ODSR_TB1ODS ((uint32_t)0x00000004) /*!< Timer B Output 1 disable status */ |
bogdanm | 86:04dd9b1680ae | 4741 | #define HRTIM_ODSR_TB2ODS ((uint32_t)0x00000008) /*!< Timer B Output 2 disable status */ |
bogdanm | 86:04dd9b1680ae | 4742 | #define HRTIM_ODSR_TC1ODS ((uint32_t)0x00000010) /*!< Timer C Output 1 disable status */ |
bogdanm | 86:04dd9b1680ae | 4743 | #define HRTIM_ODSR_TC2ODS ((uint32_t)0x00000020) /*!< Timer C Output 2 disable status */ |
bogdanm | 86:04dd9b1680ae | 4744 | #define HRTIM_ODSR_TD1ODS ((uint32_t)0x00000040) /*!< Timer D Output 1 disable status */ |
bogdanm | 86:04dd9b1680ae | 4745 | #define HRTIM_ODSR_TD2ODS ((uint32_t)0x00000080) /*!< Timer D Output 2 disable status */ |
bogdanm | 86:04dd9b1680ae | 4746 | #define HRTIM_ODSR_TE1ODS ((uint32_t)0x00000100) /*!< Timer E Output 1 disable status */ |
bogdanm | 86:04dd9b1680ae | 4747 | #define HRTIM_ODSR_TE2ODS ((uint32_t)0x00000200) /*!< Timer E Output 2 disable status */ |
bogdanm | 86:04dd9b1680ae | 4748 | |
bogdanm | 86:04dd9b1680ae | 4749 | /**** Bit definition for Common HRTIM Timer Burst mode control register ********/ |
bogdanm | 86:04dd9b1680ae | 4750 | #define HRTIM_BMCR_BME ((uint32_t)0x00000001) /*!< Burst mode enbale */ |
bogdanm | 86:04dd9b1680ae | 4751 | #define HRTIM_BMCR_BMOM ((uint32_t)0x00000002) /*!< Burst mode operating mode */ |
bogdanm | 86:04dd9b1680ae | 4752 | #define HRTIM_BMCR_BMCLK ((uint32_t)0x0000003C) /*!< Burst mode clock source */ |
bogdanm | 86:04dd9b1680ae | 4753 | #define HRTIM_BMCR_BMCLK_0 ((uint32_t)0x00000004) /*!< Burst mode clock source bit 0 */ |
bogdanm | 86:04dd9b1680ae | 4754 | #define HRTIM_BMCR_BMCLK_1 ((uint32_t)0x00000008) /*!< Burst mode clock source bit 1 */ |
bogdanm | 86:04dd9b1680ae | 4755 | #define HRTIM_BMCR_BMCLK_2 ((uint32_t)0x00000010) /*!< Burst mode clock source bit 2 */ |
bogdanm | 86:04dd9b1680ae | 4756 | #define HRTIM_BMCR_BMCLK_3 ((uint32_t)0x00000020) /*!< Burst mode clock source bit 3 */ |
bogdanm | 86:04dd9b1680ae | 4757 | #define HRTIM_BMCR_BMPRSC ((uint32_t)0x000003C0) /*!< Burst mode prescaler */ |
bogdanm | 86:04dd9b1680ae | 4758 | #define HRTIM_BMCR_BMPRSC_0 ((uint32_t)0x00000040) /*!< Burst mode prescaler bit 0 */ |
bogdanm | 86:04dd9b1680ae | 4759 | #define HRTIM_BMCR_BMPRSC_1 ((uint32_t)0x00000080) /*!< Burst mode prescaler bit 1 */ |
bogdanm | 86:04dd9b1680ae | 4760 | #define HRTIM_BMCR_BMPRSC_2 ((uint32_t)0x00000100) /*!< Burst mode prescaler bit 2 */ |
bogdanm | 86:04dd9b1680ae | 4761 | #define HRTIM_BMCR_BMPRSC_3 ((uint32_t)0x00000200) /*!< Burst mode prescaler bit 3 */ |
bogdanm | 86:04dd9b1680ae | 4762 | #define HRTIM_BMCR_BMPREN ((uint32_t)0x00000400) /*!< Burst mode Preload bit */ |
bogdanm | 86:04dd9b1680ae | 4763 | #define HRTIM_BMCR_MTBM ((uint32_t)0x00010000) /*!< Master Timer Burst mode */ |
bogdanm | 86:04dd9b1680ae | 4764 | #define HRTIM_BMCR_TABM ((uint32_t)0x00020000) /*!< Timer A Burst mode */ |
bogdanm | 86:04dd9b1680ae | 4765 | #define HRTIM_BMCR_TBBM ((uint32_t)0x00040000) /*!< Timer B Burst mode */ |
bogdanm | 86:04dd9b1680ae | 4766 | #define HRTIM_BMCR_TCBM ((uint32_t)0x00080000) /*!< Timer C Burst mode */ |
bogdanm | 86:04dd9b1680ae | 4767 | #define HRTIM_BMCR_TDBM ((uint32_t)0x00100000) /*!< Timer D Burst mode */ |
bogdanm | 86:04dd9b1680ae | 4768 | #define HRTIM_BMCR_TEBM ((uint32_t)0x00200000) /*!< Timer E Burst mode */ |
bogdanm | 86:04dd9b1680ae | 4769 | #define HRTIM_BMCR_BMSTAT ((uint32_t)0x80000000) /*!< Burst mode status */ |
bogdanm | 86:04dd9b1680ae | 4770 | |
bogdanm | 86:04dd9b1680ae | 4771 | /**** Bit definition for Common HRTIM Timer Burst mode Trigger register *******/ |
bogdanm | 86:04dd9b1680ae | 4772 | #define HRTIM_BMTRGR_SW ((uint32_t)0x00000001) /*!< Software start */ |
bogdanm | 86:04dd9b1680ae | 4773 | #define HRTIM_BMTRGR_MSTRST ((uint32_t)0x00000002) /*!< Master reset */ |
bogdanm | 86:04dd9b1680ae | 4774 | #define HRTIM_BMTRGR_MSTREP ((uint32_t)0x00000004) /*!< Master repetition */ |
bogdanm | 86:04dd9b1680ae | 4775 | #define HRTIM_BMTRGR_MSTCMP1 ((uint32_t)0x00000008) /*!< Master compare 1 */ |
bogdanm | 86:04dd9b1680ae | 4776 | #define HRTIM_BMTRGR_MSTCMP2 ((uint32_t)0x00000010) /*!< Master compare 2 */ |
bogdanm | 86:04dd9b1680ae | 4777 | #define HRTIM_BMTRGR_MSTCMP3 ((uint32_t)0x00000020) /*!< Master compare 3 */ |
bogdanm | 86:04dd9b1680ae | 4778 | #define HRTIM_BMTRGR_MSTCMP4 ((uint32_t)0x00000040) /*!< Master compare 4 */ |
bogdanm | 86:04dd9b1680ae | 4779 | #define HRTIM_BMTRGR_TARST ((uint32_t)0x00000080) /*!< Timer A reset */ |
bogdanm | 86:04dd9b1680ae | 4780 | #define HRTIM_BMTRGR_TAREP ((uint32_t)0x00000100) /*!< Timer A repetition */ |
bogdanm | 86:04dd9b1680ae | 4781 | #define HRTIM_BMTRGR_TACMP1 ((uint32_t)0x00000200) /*!< Timer A compare 1 */ |
bogdanm | 86:04dd9b1680ae | 4782 | #define HRTIM_BMTRGR_TACMP2 ((uint32_t)0x00000400) /*!< Timer A compare 2 */ |
bogdanm | 86:04dd9b1680ae | 4783 | #define HRTIM_BMTRGR_TBRST ((uint32_t)0x00000800) /*!< Timer B reset */ |
bogdanm | 86:04dd9b1680ae | 4784 | #define HRTIM_BMTRGR_TBREP ((uint32_t)0x00001000) /*!< Timer B repetition */ |
bogdanm | 86:04dd9b1680ae | 4785 | #define HRTIM_BMTRGR_TBCMP1 ((uint32_t)0x00002000) /*!< Timer B compare 1 */ |
bogdanm | 86:04dd9b1680ae | 4786 | #define HRTIM_BMTRGR_TBCMP2 ((uint32_t)0x00004000) /*!< Timer B compare 2 */ |
bogdanm | 86:04dd9b1680ae | 4787 | #define HRTIM_BMTRGR_TCRST ((uint32_t)0x00008000) /*!< Timer C reset */ |
bogdanm | 86:04dd9b1680ae | 4788 | #define HRTIM_BMTRGR_TCREP ((uint32_t)0x00010000) /*!< Timer C repetition */ |
bogdanm | 86:04dd9b1680ae | 4789 | #define HRTIM_BMTRGR_TCCMP1 ((uint32_t)0x00020000) /*!< Timer C compare 1 */ |
bogdanm | 86:04dd9b1680ae | 4790 | #define HRTIM_BMTRGR_TCCMP2 ((uint32_t)0x00040000) /*!< Timer C compare 2 */ |
bogdanm | 86:04dd9b1680ae | 4791 | #define HRTIM_BMTRGR_TDRST ((uint32_t)0x00080000) /*!< Timer D reset */ |
bogdanm | 86:04dd9b1680ae | 4792 | #define HRTIM_BMTRGR_TDREP ((uint32_t)0x00100000) /*!< Timer D repetition */ |
bogdanm | 86:04dd9b1680ae | 4793 | #define HRTIM_BMTRGR_TDCMP1 ((uint32_t)0x00200000) /*!< Timer D compare 1 */ |
bogdanm | 86:04dd9b1680ae | 4794 | #define HRTIM_BMTRGR_TDCMP2 ((uint32_t)0x00400000) /*!< Timer D compare 2 */ |
bogdanm | 86:04dd9b1680ae | 4795 | #define HRTIM_BMTRGR_TERST ((uint32_t)0x00800000) /*!< Timer E reset */ |
bogdanm | 86:04dd9b1680ae | 4796 | #define HRTIM_BMTRGR_TEREP ((uint32_t)0x01000000) /*!< Timer E repetition */ |
bogdanm | 86:04dd9b1680ae | 4797 | #define HRTIM_BMTRGR_TECMP1 ((uint32_t)0x02000000) /*!< Timer E compare 1 */ |
bogdanm | 86:04dd9b1680ae | 4798 | #define HRTIM_BMTRGR_TECMP2 ((uint32_t)0x04000000) /*!< Timer E compare 2 */ |
bogdanm | 86:04dd9b1680ae | 4799 | #define HRTIM_BMTRGR_TAEEV7 ((uint32_t)0x08000000) /*!< Timer A period following External Event7 */ |
bogdanm | 86:04dd9b1680ae | 4800 | #define HRTIM_BMTRGR_TDEEV8 ((uint32_t)0x10000000) /*!< Timer D period following External Event8 */ |
bogdanm | 86:04dd9b1680ae | 4801 | #define HRTIM_BMTRGR_EEV7 ((uint32_t)0x20000000) /*!< External Event 7 */ |
bogdanm | 86:04dd9b1680ae | 4802 | #define HRTIM_BMTRGR_EEV8 ((uint32_t)0x40000000) /*!< External Event 8 */ |
bogdanm | 86:04dd9b1680ae | 4803 | #define HRTIM_BMTRGR_OCHPEV ((uint32_t)0x80000000) /*!< on-chip Event */ |
bogdanm | 86:04dd9b1680ae | 4804 | |
bogdanm | 86:04dd9b1680ae | 4805 | /******************* Bit definition for HRTIM_BMCMPR register ***************/ |
bogdanm | 86:04dd9b1680ae | 4806 | #define HRTIM_BMCMPR_BMCMPR ((uint32_t)0x0000FFFF) /*!<!<Burst Compare Value */ |
bogdanm | 86:04dd9b1680ae | 4807 | |
bogdanm | 86:04dd9b1680ae | 4808 | /******************* Bit definition for HRTIM_BMPER register ****************/ |
bogdanm | 86:04dd9b1680ae | 4809 | #define HRTIM_BMPER_BMPER ((uint32_t)0x0000FFFF) /*!<!<Burst period Value */ |
bogdanm | 86:04dd9b1680ae | 4810 | |
bogdanm | 86:04dd9b1680ae | 4811 | /******************* Bit definition for HRTIM_EECR1 register ****************/ |
bogdanm | 86:04dd9b1680ae | 4812 | #define HRTIM_EECR1_EE1SRC ((uint32_t)0x00000003) /*!< External event 1 source */ |
bogdanm | 86:04dd9b1680ae | 4813 | #define HRTIM_EECR1_EE1SRC_0 ((uint32_t)0x00000001) /*!< External event 1 source bit 0 */ |
bogdanm | 86:04dd9b1680ae | 4814 | #define HRTIM_EECR1_EE1SRC_1 ((uint32_t)0x00000002) /*!< External event 1 source bit 1 */ |
bogdanm | 86:04dd9b1680ae | 4815 | #define HRTIM_EECR1_EE1POL ((uint32_t)0x00000004) /*!< External event 1 Polarity */ |
bogdanm | 86:04dd9b1680ae | 4816 | #define HRTIM_EECR1_EE1SNS ((uint32_t)0x00000018) /*!< External event 1 sensitivity */ |
bogdanm | 86:04dd9b1680ae | 4817 | #define HRTIM_EECR1_EE1SNS_0 ((uint32_t)0x00000008) /*!< External event 1 sensitivity bit 0 */ |
bogdanm | 86:04dd9b1680ae | 4818 | #define HRTIM_EECR1_EE1SNS_1 ((uint32_t)0x00000010) /*!< External event 1 sensitivity bit 1 */ |
bogdanm | 86:04dd9b1680ae | 4819 | #define HRTIM_EECR1_EE1FAST ((uint32_t)0x00000020) /*!< External event 1 Fast mode */ |
bogdanm | 86:04dd9b1680ae | 4820 | |
bogdanm | 86:04dd9b1680ae | 4821 | #define HRTIM_EECR1_EE2SRC ((uint32_t)0x000000C0) /*!< External event 2 source */ |
bogdanm | 86:04dd9b1680ae | 4822 | #define HRTIM_EECR1_EE2SRC_0 ((uint32_t)0x00000040) /*!< External event 2 source bit 0 */ |
bogdanm | 86:04dd9b1680ae | 4823 | #define HRTIM_EECR1_EE2SRC_1 ((uint32_t)0x00000080) /*!< External event 2 source bit 1 */ |
bogdanm | 86:04dd9b1680ae | 4824 | #define HRTIM_EECR1_EE2POL ((uint32_t)0x00000100) /*!< External event 2 Polarity */ |
bogdanm | 86:04dd9b1680ae | 4825 | #define HRTIM_EECR1_EE2SNS ((uint32_t)0x00000600) /*!< External event 2 sensitivity */ |
bogdanm | 86:04dd9b1680ae | 4826 | #define HRTIM_EECR1_EE2SNS_0 ((uint32_t)0x00000200) /*!< External event 2 sensitivity bit 0 */ |
bogdanm | 86:04dd9b1680ae | 4827 | #define HRTIM_EECR1_EE2SNS_1 ((uint32_t)0x00000400) /*!< External event 2 sensitivity bit 1 */ |
bogdanm | 86:04dd9b1680ae | 4828 | #define HRTIM_EECR1_EE2FAST ((uint32_t)0x00000800) /*!< External event 2 Fast mode */ |
bogdanm | 86:04dd9b1680ae | 4829 | |
bogdanm | 86:04dd9b1680ae | 4830 | #define HRTIM_EECR1_EE3SRC ((uint32_t)0x00003000) /*!< External event 3 source */ |
bogdanm | 86:04dd9b1680ae | 4831 | #define HRTIM_EECR1_EE3SRC_0 ((uint32_t)0x00001000) /*!< External event 3 source bit 0 */ |
bogdanm | 86:04dd9b1680ae | 4832 | #define HRTIM_EECR1_EE3SRC_1 ((uint32_t)0x00002000) /*!< External event 3 source bit 1 */ |
bogdanm | 86:04dd9b1680ae | 4833 | #define HRTIM_EECR1_EE3POL ((uint32_t)0x00004000) /*!< External event 3 Polarity */ |
bogdanm | 86:04dd9b1680ae | 4834 | #define HRTIM_EECR1_EE3SNS ((uint32_t)0x00018000) /*!< External event 3 sensitivity */ |
bogdanm | 86:04dd9b1680ae | 4835 | #define HRTIM_EECR1_EE3SNS_0 ((uint32_t)0x00008000) /*!< External event 3 sensitivity bit 0 */ |
bogdanm | 86:04dd9b1680ae | 4836 | #define HRTIM_EECR1_EE3SNS_1 ((uint32_t)0x00010000) /*!< External event 3 sensitivity bit 1 */ |
bogdanm | 86:04dd9b1680ae | 4837 | #define HRTIM_EECR1_EE3FAST ((uint32_t)0x00020000) /*!< External event 3 Fast mode */ |
bogdanm | 86:04dd9b1680ae | 4838 | |
bogdanm | 86:04dd9b1680ae | 4839 | #define HRTIM_EECR1_EE4SRC ((uint32_t)0x000C0000) /*!< External event 4 source */ |
bogdanm | 86:04dd9b1680ae | 4840 | #define HRTIM_EECR1_EE4SRC_0 ((uint32_t)0x00040000) /*!< External event 4 source bit 0 */ |
bogdanm | 86:04dd9b1680ae | 4841 | #define HRTIM_EECR1_EE4SRC_1 ((uint32_t)0x00080000) /*!< External event 4 source bit 1 */ |
bogdanm | 86:04dd9b1680ae | 4842 | #define HRTIM_EECR1_EE4POL ((uint32_t)0x00100000) /*!< External event 4 Polarity */ |
bogdanm | 86:04dd9b1680ae | 4843 | #define HRTIM_EECR1_EE4SNS ((uint32_t)0x00600000) /*!< External event 4 sensitivity */ |
bogdanm | 86:04dd9b1680ae | 4844 | #define HRTIM_EECR1_EE4SNS_0 ((uint32_t)0x00200000) /*!< External event 4 sensitivity bit 0 */ |
bogdanm | 86:04dd9b1680ae | 4845 | #define HRTIM_EECR1_EE4SNS_1 ((uint32_t)0x00400000) /*!< External event 4 sensitivity bit 1 */ |
bogdanm | 86:04dd9b1680ae | 4846 | #define HRTIM_EECR1_EE4FAST ((uint32_t)0x00800000) /*!< External event 4 Fast mode */ |
bogdanm | 86:04dd9b1680ae | 4847 | |
bogdanm | 86:04dd9b1680ae | 4848 | #define HRTIM_EECR1_EE5SRC ((uint32_t)0x03000000) /*!< External event 5 source */ |
bogdanm | 86:04dd9b1680ae | 4849 | #define HRTIM_EECR1_EE5SRC_0 ((uint32_t)0x01000000) /*!< External event 5 source bit 0 */ |
bogdanm | 86:04dd9b1680ae | 4850 | #define HRTIM_EECR1_EE5SRC_1 ((uint32_t)0x02000000) /*!< External event 5 source bit 1 */ |
bogdanm | 86:04dd9b1680ae | 4851 | #define HRTIM_EECR1_EE5POL ((uint32_t)0x04000000) /*!< External event 5 Polarity */ |
bogdanm | 86:04dd9b1680ae | 4852 | #define HRTIM_EECR1_EE5SNS ((uint32_t)0x18000000) /*!< External event 5 sensitivity */ |
bogdanm | 86:04dd9b1680ae | 4853 | #define HRTIM_EECR1_EE5SNS_0 ((uint32_t)0x08000000) /*!< External event 5 sensitivity bit 0 */ |
bogdanm | 86:04dd9b1680ae | 4854 | #define HRTIM_EECR1_EE5SNS_1 ((uint32_t)0x10000000) /*!< External event 5 sensitivity bit 1 */ |
bogdanm | 86:04dd9b1680ae | 4855 | #define HRTIM_EECR1_EE5FAST ((uint32_t)0x20000000) /*!< External event 5 Fast mode */ |
bogdanm | 86:04dd9b1680ae | 4856 | |
bogdanm | 86:04dd9b1680ae | 4857 | /******************* Bit definition for HRTIM_EECR2 register ****************/ |
bogdanm | 86:04dd9b1680ae | 4858 | #define HRTIM_EECR2_EE6SRC ((uint32_t)0x00000003) /*!< External event 6 source */ |
bogdanm | 86:04dd9b1680ae | 4859 | #define HRTIM_EECR2_EE6SRC_0 ((uint32_t)0x00000001) /*!< External event 6 source bit 0 */ |
bogdanm | 86:04dd9b1680ae | 4860 | #define HRTIM_EECR2_EE6SRC_1 ((uint32_t)0x00000002) /*!< External event 6 source bit 1 */ |
bogdanm | 86:04dd9b1680ae | 4861 | #define HRTIM_EECR2_EE6POL ((uint32_t)0x00000004) /*!< External event 6 Polarity */ |
bogdanm | 86:04dd9b1680ae | 4862 | #define HRTIM_EECR2_EE6SNS ((uint32_t)0x00000018) /*!< External event 6 sensitivity */ |
bogdanm | 86:04dd9b1680ae | 4863 | #define HRTIM_EECR2_EE6SNS_0 ((uint32_t)0x00000008) /*!< External event 6 sensitivity bit 0 */ |
bogdanm | 86:04dd9b1680ae | 4864 | #define HRTIM_EECR2_EE6SNS_1 ((uint32_t)0x00000010) /*!< External event 6 sensitivity bit 1 */ |
bogdanm | 86:04dd9b1680ae | 4865 | |
bogdanm | 86:04dd9b1680ae | 4866 | #define HRTIM_EECR2_EE7SRC ((uint32_t)0x000000C0) /*!< External event 7 source */ |
bogdanm | 86:04dd9b1680ae | 4867 | #define HRTIM_EECR2_EE7SRC_0 ((uint32_t)0x00000040) /*!< External event 7 source bit 0 */ |
bogdanm | 86:04dd9b1680ae | 4868 | #define HRTIM_EECR2_EE7SRC_1 ((uint32_t)0x00000080) /*!< External event 7 source bit 1 */ |
bogdanm | 86:04dd9b1680ae | 4869 | #define HRTIM_EECR2_EE7POL ((uint32_t)0x00000100) /*!< External event 7 Polarity */ |
bogdanm | 86:04dd9b1680ae | 4870 | #define HRTIM_EECR2_EE7SNS ((uint32_t)0x00000600) /*!< External event 7 sensitivity */ |
bogdanm | 86:04dd9b1680ae | 4871 | #define HRTIM_EECR2_EE7SNS_0 ((uint32_t)0x00000200) /*!< External event 7 sensitivity bit 0 */ |
bogdanm | 86:04dd9b1680ae | 4872 | #define HRTIM_EECR2_EE7SNS_1 ((uint32_t)0x00000400) /*!< External event 7 sensitivity bit 1 */ |
bogdanm | 86:04dd9b1680ae | 4873 | |
bogdanm | 86:04dd9b1680ae | 4874 | #define HRTIM_EECR2_EE8SRC ((uint32_t)0x00003000) /*!< External event 8 source */ |
bogdanm | 86:04dd9b1680ae | 4875 | #define HRTIM_EECR2_EE8SRC_0 ((uint32_t)0x00001000) /*!< External event 8 source bit 0 */ |
bogdanm | 86:04dd9b1680ae | 4876 | #define HRTIM_EECR2_EE8SRC_1 ((uint32_t)0x00002000) /*!< External event 8 source bit 1 */ |
bogdanm | 86:04dd9b1680ae | 4877 | #define HRTIM_EECR2_EE8POL ((uint32_t)0x00004000) /*!< External event 8 Polarity */ |
bogdanm | 86:04dd9b1680ae | 4878 | #define HRTIM_EECR2_EE8SNS ((uint32_t)0x00018000) /*!< External event 8 sensitivity */ |
bogdanm | 86:04dd9b1680ae | 4879 | #define HRTIM_EECR2_EE8SNS_0 ((uint32_t)0x00008000) /*!< External event 8 sensitivity bit 0 */ |
bogdanm | 86:04dd9b1680ae | 4880 | #define HRTIM_EECR2_EE8SNS_1 ((uint32_t)0x00010000) /*!< External event 8 sensitivity bit 1 */ |
bogdanm | 86:04dd9b1680ae | 4881 | |
bogdanm | 86:04dd9b1680ae | 4882 | #define HRTIM_EECR2_EE9SRC ((uint32_t)0x000C0000) /*!< External event 9 source */ |
bogdanm | 86:04dd9b1680ae | 4883 | #define HRTIM_EECR2_EE9SRC_0 ((uint32_t)0x00040000) /*!< External event 9 source bit 0 */ |
bogdanm | 86:04dd9b1680ae | 4884 | #define HRTIM_EECR2_EE9SRC_1 ((uint32_t)0x00080000) /*!< External event 9 source bit 1 */ |
bogdanm | 86:04dd9b1680ae | 4885 | #define HRTIM_EECR2_EE9POL ((uint32_t)0x00100000) /*!< External event 9 Polarity */ |
bogdanm | 86:04dd9b1680ae | 4886 | #define HRTIM_EECR2_EE9SNS ((uint32_t)0x00600000) /*!< External event 9 sensitivity */ |
bogdanm | 86:04dd9b1680ae | 4887 | #define HRTIM_EECR2_EE9SNS_0 ((uint32_t)0x00200000) /*!< External event 9 sensitivity bit 0 */ |
bogdanm | 86:04dd9b1680ae | 4888 | #define HRTIM_EECR2_EE9SNS_1 ((uint32_t)0x00400000) /*!< External event 9 sensitivity bit 1 */ |
bogdanm | 86:04dd9b1680ae | 4889 | |
bogdanm | 86:04dd9b1680ae | 4890 | #define HRTIM_EECR2_EE10SRC ((uint32_t)0x03000000) /*!< External event 10 source */ |
bogdanm | 86:04dd9b1680ae | 4891 | #define HRTIM_EECR2_EE10SRC_0 ((uint32_t)0x01000000) /*!< External event 10 source bit 0 */ |
bogdanm | 86:04dd9b1680ae | 4892 | #define HRTIM_EECR2_EE10SRC_1 ((uint32_t)0x02000000) /*!< External event 10 source bit 1 */ |
bogdanm | 86:04dd9b1680ae | 4893 | #define HRTIM_EECR2_EE10POL ((uint32_t)0x04000000) /*!< External event 10 Polarity */ |
bogdanm | 86:04dd9b1680ae | 4894 | #define HRTIM_EECR2_EE10SNS ((uint32_t)0x18000000) /*!< External event 10 sensitivity */ |
bogdanm | 86:04dd9b1680ae | 4895 | #define HRTIM_EECR2_EE10SNS_0 ((uint32_t)0x08000000) /*!< External event 10 sensitivity bit 0 */ |
bogdanm | 86:04dd9b1680ae | 4896 | #define HRTIM_EECR2_EE10SNS_1 ((uint32_t)0x10000000) /*!< External event 10 sensitivity bit 1 */ |
bogdanm | 86:04dd9b1680ae | 4897 | |
bogdanm | 86:04dd9b1680ae | 4898 | /******************* Bit definition for HRTIM_EECR3 register ****************/ |
bogdanm | 86:04dd9b1680ae | 4899 | #define HRTIM_EECR3_EE6F ((uint32_t)0x0000000F) /*!< External event 6 filter */ |
bogdanm | 86:04dd9b1680ae | 4900 | #define HRTIM_EECR3_EE6F_0 ((uint32_t)0x00000001) /*!< External event 6 filter bit 0 */ |
bogdanm | 86:04dd9b1680ae | 4901 | #define HRTIM_EECR3_EE6F_1 ((uint32_t)0x00000002) /*!< External event 6 filter bit 1 */ |
bogdanm | 86:04dd9b1680ae | 4902 | #define HRTIM_EECR3_EE6F_2 ((uint32_t)0x00000004) /*!< External event 6 filter bit 2 */ |
bogdanm | 86:04dd9b1680ae | 4903 | #define HRTIM_EECR3_EE6F_3 ((uint32_t)0x00000008) /*!< External event 6 filter bit 3 */ |
bogdanm | 86:04dd9b1680ae | 4904 | #define HRTIM_EECR3_EE7F ((uint32_t)0x000003C0) /*!< External event 7 filter */ |
bogdanm | 86:04dd9b1680ae | 4905 | #define HRTIM_EECR3_EE7F_0 ((uint32_t)0x00000040) /*!< External event 7 filter bit 0 */ |
bogdanm | 86:04dd9b1680ae | 4906 | #define HRTIM_EECR3_EE7F_1 ((uint32_t)0x00000080) /*!< External event 7 filter bit 1 */ |
bogdanm | 86:04dd9b1680ae | 4907 | #define HRTIM_EECR3_EE7F_2 ((uint32_t)0x00000100) /*!< External event 7 filter bit 2 */ |
bogdanm | 86:04dd9b1680ae | 4908 | #define HRTIM_EECR3_EE7F_3 ((uint32_t)0x00000200) /*!< External event 7 filter bit 3 */ |
bogdanm | 86:04dd9b1680ae | 4909 | #define HRTIM_EECR3_EE8F ((uint32_t)0x0000F000) /*!< External event 8 filter */ |
bogdanm | 86:04dd9b1680ae | 4910 | #define HRTIM_EECR3_EE8F_0 ((uint32_t)0x00001000) /*!< External event 8 filter bit 0 */ |
bogdanm | 86:04dd9b1680ae | 4911 | #define HRTIM_EECR3_EE8F_1 ((uint32_t)0x00002000) /*!< External event 8 filter bit 1 */ |
bogdanm | 86:04dd9b1680ae | 4912 | #define HRTIM_EECR3_EE8F_2 ((uint32_t)0x00004000) /*!< External event 8 filter bit 2 */ |
bogdanm | 86:04dd9b1680ae | 4913 | #define HRTIM_EECR3_EE8F_3 ((uint32_t)0x00008000) /*!< External event 8 filter bit 3 */ |
bogdanm | 86:04dd9b1680ae | 4914 | #define HRTIM_EECR3_EE9F ((uint32_t)0x003C0000) /*!< External event 9 filter */ |
bogdanm | 86:04dd9b1680ae | 4915 | #define HRTIM_EECR3_EE9F_0 ((uint32_t)0x00040000) /*!< External event 9 filter bit 0 */ |
bogdanm | 86:04dd9b1680ae | 4916 | #define HRTIM_EECR3_EE9F_1 ((uint32_t)0x00080000) /*!< External event 9 filter bit 1 */ |
bogdanm | 86:04dd9b1680ae | 4917 | #define HRTIM_EECR3_EE9F_2 ((uint32_t)0x00100000) /*!< External event 9 filter bit 2 */ |
bogdanm | 86:04dd9b1680ae | 4918 | #define HRTIM_EECR3_EE9F_3 ((uint32_t)0x00200000) /*!< External event 9 filter bit 3 */ |
bogdanm | 86:04dd9b1680ae | 4919 | #define HRTIM_EECR3_EE10F ((uint32_t)0x0F000000) /*!< External event 10 filter */ |
bogdanm | 86:04dd9b1680ae | 4920 | #define HRTIM_EECR3_EE10F_0 ((uint32_t)0x01000000) /*!< External event 10 filter bit 0 */ |
bogdanm | 86:04dd9b1680ae | 4921 | #define HRTIM_EECR3_EE10F_1 ((uint32_t)0x02000000) /*!< External event 10 filter bit 1 */ |
bogdanm | 86:04dd9b1680ae | 4922 | #define HRTIM_EECR3_EE10F_2 ((uint32_t)0x04000000) /*!< External event 10 filter bit 2 */ |
bogdanm | 86:04dd9b1680ae | 4923 | #define HRTIM_EECR3_EE10F_3 ((uint32_t)0x08000000) /*!< External event 10 filter bit 3 */ |
bogdanm | 86:04dd9b1680ae | 4924 | #define HRTIM_EECR3_EEVSD ((uint32_t)0xC0000000) /*!< External event sampling clock division */ |
bogdanm | 86:04dd9b1680ae | 4925 | #define HRTIM_EECR3_EEVSD_0 ((uint32_t)0x40000000) /*!< External event sampling clock division bit 0 */ |
bogdanm | 86:04dd9b1680ae | 4926 | #define HRTIM_EECR3_EEVSD_1 ((uint32_t)0x80000000) /*!< External event sampling clock division bit 1 */ |
bogdanm | 86:04dd9b1680ae | 4927 | |
bogdanm | 86:04dd9b1680ae | 4928 | /******************* Bit definition for HRTIM_ADC1R register ****************/ |
bogdanm | 86:04dd9b1680ae | 4929 | #define HRTIM_ADC1R_AD1MC1 ((uint32_t)0x00000001) /*!< ADC Trigger 1 on master compare 1 */ |
bogdanm | 86:04dd9b1680ae | 4930 | #define HRTIM_ADC1R_AD1MC2 ((uint32_t)0x00000002) /*!< ADC Trigger 1 on master compare 2 */ |
bogdanm | 86:04dd9b1680ae | 4931 | #define HRTIM_ADC1R_AD1MC3 ((uint32_t)0x00000004) /*!< ADC Trigger 1 on master compare 3 */ |
bogdanm | 86:04dd9b1680ae | 4932 | #define HRTIM_ADC1R_AD1MC4 ((uint32_t)0x00000008) /*!< ADC Trigger 1 on master compare 4 */ |
bogdanm | 86:04dd9b1680ae | 4933 | #define HRTIM_ADC1R_AD1MPER ((uint32_t)0x00000010) /*!< ADC Trigger 1 on master period */ |
bogdanm | 86:04dd9b1680ae | 4934 | #define HRTIM_ADC1R_AD1EEV1 ((uint32_t)0x00000020) /*!< ADC Trigger 1 on external event 1 */ |
bogdanm | 86:04dd9b1680ae | 4935 | #define HRTIM_ADC1R_AD1EEV2 ((uint32_t)0x00000040) /*!< ADC Trigger 1 on external event 2 */ |
bogdanm | 86:04dd9b1680ae | 4936 | #define HRTIM_ADC1R_AD1EEV3 ((uint32_t)0x00000080) /*!< ADC Trigger 1 on external event 3 */ |
bogdanm | 86:04dd9b1680ae | 4937 | #define HRTIM_ADC1R_AD1EEV4 ((uint32_t)0x00000100) /*!< ADC Trigger 1 on external event 4 */ |
bogdanm | 86:04dd9b1680ae | 4938 | #define HRTIM_ADC1R_AD1EEV5 ((uint32_t)0x00000200) /*!< ADC Trigger 1 on external event 5 */ |
bogdanm | 86:04dd9b1680ae | 4939 | #define HRTIM_ADC1R_AD1TAC2 ((uint32_t)0x00000400) /*!< ADC Trigger 1 on Timer A compare 2 */ |
bogdanm | 86:04dd9b1680ae | 4940 | #define HRTIM_ADC1R_AD1TAC3 ((uint32_t)0x00000800) /*!< ADC Trigger 1 on Timer A compare 3 */ |
bogdanm | 86:04dd9b1680ae | 4941 | #define HRTIM_ADC1R_AD1TAC4 ((uint32_t)0x00001000) /*!< ADC Trigger 1 on Timer A compare 4 */ |
bogdanm | 86:04dd9b1680ae | 4942 | #define HRTIM_ADC1R_AD1TAPER ((uint32_t)0x00002000) /*!< ADC Trigger 1 on Timer A period */ |
bogdanm | 86:04dd9b1680ae | 4943 | #define HRTIM_ADC1R_AD1TARST ((uint32_t)0x00004000) /*!< ADC Trigger 1 on Timer A reset */ |
bogdanm | 86:04dd9b1680ae | 4944 | #define HRTIM_ADC1R_AD1TBC2 ((uint32_t)0x00008000) /*!< ADC Trigger 1 on Timer B compare 2 */ |
bogdanm | 86:04dd9b1680ae | 4945 | #define HRTIM_ADC1R_AD1TBC3 ((uint32_t)0x00010000) /*!< ADC Trigger 1 on Timer B compare 3 */ |
bogdanm | 86:04dd9b1680ae | 4946 | #define HRTIM_ADC1R_AD1TBC4 ((uint32_t)0x00020000) /*!< ADC Trigger 1 on Timer B compare 4 */ |
bogdanm | 86:04dd9b1680ae | 4947 | #define HRTIM_ADC1R_AD1TBPER ((uint32_t)0x00040000) /*!< ADC Trigger 1 on Timer B period */ |
bogdanm | 86:04dd9b1680ae | 4948 | #define HRTIM_ADC1R_AD1TBRST ((uint32_t)0x00080000) /*!< ADC Trigger 1 on Timer B reset */ |
bogdanm | 86:04dd9b1680ae | 4949 | #define HRTIM_ADC1R_AD1TCC2 ((uint32_t)0x00100000) /*!< ADC Trigger 1 on Timer C compare 2 */ |
bogdanm | 86:04dd9b1680ae | 4950 | #define HRTIM_ADC1R_AD1TCC3 ((uint32_t)0x00200000) /*!< ADC Trigger 1 on Timer C compare 3 */ |
bogdanm | 86:04dd9b1680ae | 4951 | #define HRTIM_ADC1R_AD1TCC4 ((uint32_t)0x00400000) /*!< ADC Trigger 1 on Timer C compare 4 */ |
bogdanm | 86:04dd9b1680ae | 4952 | #define HRTIM_ADC1R_AD1TCPER ((uint32_t)0x00800000) /*!< ADC Trigger 1 on Timer C period */ |
bogdanm | 86:04dd9b1680ae | 4953 | #define HRTIM_ADC1R_AD1TDC2 ((uint32_t)0x01000000) /*!< ADC Trigger 1 on Timer D compare 2 */ |
bogdanm | 86:04dd9b1680ae | 4954 | #define HRTIM_ADC1R_AD1TDC3 ((uint32_t)0x02000000) /*!< ADC Trigger 1 on Timer D compare 3 */ |
bogdanm | 86:04dd9b1680ae | 4955 | #define HRTIM_ADC1R_AD1TDC4 ((uint32_t)0x04000000) /*!< ADC Trigger 1 on Timer D compare 4 */ |
bogdanm | 86:04dd9b1680ae | 4956 | #define HRTIM_ADC1R_AD1TDPER ((uint32_t)0x08000000) /*!< ADC Trigger 1 on Timer D period */ |
bogdanm | 86:04dd9b1680ae | 4957 | #define HRTIM_ADC1R_AD1TEC2 ((uint32_t)0x10000000) /*!< ADC Trigger 1 on Timer E compare 2 */ |
bogdanm | 86:04dd9b1680ae | 4958 | #define HRTIM_ADC1R_AD1TEC3 ((uint32_t)0x20000000) /*!< ADC Trigger 1 on Timer E compare 3 */ |
bogdanm | 86:04dd9b1680ae | 4959 | #define HRTIM_ADC1R_AD1TEC4 ((uint32_t)0x40000000) /*!< ADC Trigger 1 on Timer E compare 4 */ |
bogdanm | 86:04dd9b1680ae | 4960 | #define HRTIM_ADC1R_AD1TEPER ((uint32_t)0x80000000) /*!< ADC Trigger 1 on Timer E period */ |
bogdanm | 86:04dd9b1680ae | 4961 | |
bogdanm | 86:04dd9b1680ae | 4962 | /******************* Bit definition for HRTIM_ADC2R register ****************/ |
bogdanm | 86:04dd9b1680ae | 4963 | #define HRTIM_ADC2R_AD2MC1 ((uint32_t)0x00000001) /*!< ADC Trigger 2 on master compare 1 */ |
bogdanm | 86:04dd9b1680ae | 4964 | #define HRTIM_ADC2R_AD2MC2 ((uint32_t)0x00000002) /*!< ADC Trigger 2 on master compare 2 */ |
bogdanm | 86:04dd9b1680ae | 4965 | #define HRTIM_ADC2R_AD2MC3 ((uint32_t)0x00000004) /*!< ADC Trigger 2 on master compare 3 */ |
bogdanm | 86:04dd9b1680ae | 4966 | #define HRTIM_ADC2R_AD2MC4 ((uint32_t)0x00000008) /*!< ADC Trigger 2 on master compare 4 */ |
bogdanm | 86:04dd9b1680ae | 4967 | #define HRTIM_ADC2R_AD2MPER ((uint32_t)0x00000010) /*!< ADC Trigger 2 on master period */ |
bogdanm | 86:04dd9b1680ae | 4968 | #define HRTIM_ADC2R_AD2EEV6 ((uint32_t)0x00000020) /*!< ADC Trigger 2 on external event 6 */ |
bogdanm | 86:04dd9b1680ae | 4969 | #define HRTIM_ADC2R_AD2EEV7 ((uint32_t)0x00000040) /*!< ADC Trigger 2 on external event 7 */ |
bogdanm | 86:04dd9b1680ae | 4970 | #define HRTIM_ADC2R_AD2EEV8 ((uint32_t)0x00000080) /*!< ADC Trigger 2 on external event 8 */ |
bogdanm | 86:04dd9b1680ae | 4971 | #define HRTIM_ADC2R_AD2EEV9 ((uint32_t)0x00000100) /*!< ADC Trigger 2 on external event 9 */ |
bogdanm | 86:04dd9b1680ae | 4972 | #define HRTIM_ADC2R_AD2EEV10 ((uint32_t)0x00000200) /*!< ADC Trigger 2 on external event 10 */ |
bogdanm | 86:04dd9b1680ae | 4973 | #define HRTIM_ADC2R_AD2TAC2 ((uint32_t)0x00000400) /*!< ADC Trigger 2 on Timer A compare 2 */ |
bogdanm | 86:04dd9b1680ae | 4974 | #define HRTIM_ADC2R_AD2TAC3 ((uint32_t)0x00000800) /*!< ADC Trigger 2 on Timer A compare 3 */ |
bogdanm | 86:04dd9b1680ae | 4975 | #define HRTIM_ADC2R_AD2TAC4 ((uint32_t)0x00001000) /*!< ADC Trigger 2 on Timer A compare 4*/ |
bogdanm | 86:04dd9b1680ae | 4976 | #define HRTIM_ADC2R_AD2TAPER ((uint32_t)0x00002000) /*!< ADC Trigger 2 on Timer A period */ |
bogdanm | 86:04dd9b1680ae | 4977 | #define HRTIM_ADC2R_AD2TBC2 ((uint32_t)0x00004000) /*!< ADC Trigger 2 on Timer B compare 2 */ |
bogdanm | 86:04dd9b1680ae | 4978 | #define HRTIM_ADC2R_AD2TBC3 ((uint32_t)0x00008000) /*!< ADC Trigger 2 on Timer B compare 3 */ |
bogdanm | 86:04dd9b1680ae | 4979 | #define HRTIM_ADC2R_AD2TBC4 ((uint32_t)0x00010000) /*!< ADC Trigger 2 on Timer B compare 4 */ |
bogdanm | 86:04dd9b1680ae | 4980 | #define HRTIM_ADC2R_AD2TBPER ((uint32_t)0x00020000) /*!< ADC Trigger 2 on Timer B period */ |
bogdanm | 86:04dd9b1680ae | 4981 | #define HRTIM_ADC2R_AD2TCC2 ((uint32_t)0x00040000) /*!< ADC Trigger 2 on Timer C compare 2 */ |
bogdanm | 86:04dd9b1680ae | 4982 | #define HRTIM_ADC2R_AD2TCC3 ((uint32_t)0x00080000) /*!< ADC Trigger 2 on Timer C compare 3 */ |
bogdanm | 86:04dd9b1680ae | 4983 | #define HRTIM_ADC2R_AD2TCC4 ((uint32_t)0x00100000) /*!< ADC Trigger 2 on Timer C compare 4 */ |
bogdanm | 86:04dd9b1680ae | 4984 | #define HRTIM_ADC2R_AD2TCPER ((uint32_t)0x00200000) /*!< ADC Trigger 2 on Timer C period */ |
bogdanm | 86:04dd9b1680ae | 4985 | #define HRTIM_ADC2R_AD2TCRST ((uint32_t)0x00400000) /*!< ADC Trigger 2 on Timer C reset */ |
bogdanm | 86:04dd9b1680ae | 4986 | #define HRTIM_ADC2R_AD2TDC2 ((uint32_t)0x00800000) /*!< ADC Trigger 2 on Timer D compare 2 */ |
bogdanm | 86:04dd9b1680ae | 4987 | #define HRTIM_ADC2R_AD2TDC3 ((uint32_t)0x01000000) /*!< ADC Trigger 2 on Timer D compare 3 */ |
bogdanm | 86:04dd9b1680ae | 4988 | #define HRTIM_ADC2R_AD2TDC4 ((uint32_t)0x02000000) /*!< ADC Trigger 2 on Timer D compare 4*/ |
bogdanm | 86:04dd9b1680ae | 4989 | #define HRTIM_ADC2R_AD2TDPER ((uint32_t)0x04000000) /*!< ADC Trigger 2 on Timer D period */ |
bogdanm | 86:04dd9b1680ae | 4990 | #define HRTIM_ADC2R_AD2TDRST ((uint32_t)0x08000000) /*!< ADC Trigger 2 on Timer D reset */ |
bogdanm | 86:04dd9b1680ae | 4991 | #define HRTIM_ADC2R_AD2TEC2 ((uint32_t)0x10000000) /*!< ADC Trigger 2 on Timer E compare 2 */ |
bogdanm | 86:04dd9b1680ae | 4992 | #define HRTIM_ADC2R_AD2TEC3 ((uint32_t)0x20000000) /*!< ADC Trigger 2 on Timer E compare 3 */ |
bogdanm | 86:04dd9b1680ae | 4993 | #define HRTIM_ADC2R_AD2TEC4 ((uint32_t)0x40000000) /*!< ADC Trigger 2 on Timer E compare 4 */ |
bogdanm | 86:04dd9b1680ae | 4994 | #define HRTIM_ADC2R_AD2TERST ((uint32_t)0x80000000) /*!< ADC Trigger 2 on Timer E reset */ |
bogdanm | 86:04dd9b1680ae | 4995 | |
bogdanm | 86:04dd9b1680ae | 4996 | /******************* Bit definition for HRTIM_ADC3R register ****************/ |
bogdanm | 86:04dd9b1680ae | 4997 | #define HRTIM_ADC3R_AD3MC1 ((uint32_t)0x00000001) /*!< ADC Trigger 3 on master compare 1 */ |
bogdanm | 86:04dd9b1680ae | 4998 | #define HRTIM_ADC3R_AD3MC2 ((uint32_t)0x00000002) /*!< ADC Trigger 3 on master compare 2 */ |
bogdanm | 86:04dd9b1680ae | 4999 | #define HRTIM_ADC3R_AD3MC3 ((uint32_t)0x00000004) /*!< ADC Trigger 3 on master compare 3 */ |
bogdanm | 86:04dd9b1680ae | 5000 | #define HRTIM_ADC3R_AD3MC4 ((uint32_t)0x00000008) /*!< ADC Trigger 3 on master compare 4 */ |
bogdanm | 86:04dd9b1680ae | 5001 | #define HRTIM_ADC3R_AD3MPER ((uint32_t)0x00000010) /*!< ADC Trigger 3 on master period */ |
bogdanm | 86:04dd9b1680ae | 5002 | #define HRTIM_ADC3R_AD3EEV1 ((uint32_t)0x00000020) /*!< ADC Trigger 3 on external event 1 */ |
bogdanm | 86:04dd9b1680ae | 5003 | #define HRTIM_ADC3R_AD3EEV2 ((uint32_t)0x00000040) /*!< ADC Trigger 3 on external event 2 */ |
bogdanm | 86:04dd9b1680ae | 5004 | #define HRTIM_ADC3R_AD3EEV3 ((uint32_t)0x00000080) /*!< ADC Trigger 3 on external event 3 */ |
bogdanm | 86:04dd9b1680ae | 5005 | #define HRTIM_ADC3R_AD3EEV4 ((uint32_t)0x00000100) /*!< ADC Trigger 3 on external event 4 */ |
bogdanm | 86:04dd9b1680ae | 5006 | #define HRTIM_ADC3R_AD3EEV5 ((uint32_t)0x00000200) /*!< ADC Trigger 3 on external event 5 */ |
bogdanm | 86:04dd9b1680ae | 5007 | #define HRTIM_ADC3R_AD3TAC2 ((uint32_t)0x00000400) /*!< ADC Trigger 3 on Timer A compare 2 */ |
bogdanm | 86:04dd9b1680ae | 5008 | #define HRTIM_ADC3R_AD3TAC3 ((uint32_t)0x00000800) /*!< ADC Trigger 3 on Timer A compare 3 */ |
bogdanm | 86:04dd9b1680ae | 5009 | #define HRTIM_ADC3R_AD3TAC4 ((uint32_t)0x00001000) /*!< ADC Trigger 3 on Timer A compare 4 */ |
bogdanm | 86:04dd9b1680ae | 5010 | #define HRTIM_ADC3R_AD3TAPER ((uint32_t)0x00002000) /*!< ADC Trigger 3 on Timer A period */ |
bogdanm | 86:04dd9b1680ae | 5011 | #define HRTIM_ADC3R_AD3TARST ((uint32_t)0x00004000) /*!< ADC Trigger 3 on Timer A reset */ |
bogdanm | 86:04dd9b1680ae | 5012 | #define HRTIM_ADC3R_AD3TBC2 ((uint32_t)0x00008000) /*!< ADC Trigger 3 on Timer B compare 2 */ |
bogdanm | 86:04dd9b1680ae | 5013 | #define HRTIM_ADC3R_AD3TBC3 ((uint32_t)0x00010000) /*!< ADC Trigger 3 on Timer B compare 3 */ |
bogdanm | 86:04dd9b1680ae | 5014 | #define HRTIM_ADC3R_AD3TBC4 ((uint32_t)0x00020000) /*!< ADC Trigger 3 on Timer B compare 4 */ |
bogdanm | 86:04dd9b1680ae | 5015 | #define HRTIM_ADC3R_AD3TBPER ((uint32_t)0x00040000) /*!< ADC Trigger 3 on Timer B period */ |
bogdanm | 86:04dd9b1680ae | 5016 | #define HRTIM_ADC3R_AD3TBRST ((uint32_t)0x00080000) /*!< ADC Trigger 3 on Timer B reset */ |
bogdanm | 86:04dd9b1680ae | 5017 | #define HRTIM_ADC3R_AD3TCC2 ((uint32_t)0x00100000) /*!< ADC Trigger 3 on Timer C compare 2 */ |
bogdanm | 86:04dd9b1680ae | 5018 | #define HRTIM_ADC3R_AD3TCC3 ((uint32_t)0x00200000) /*!< ADC Trigger 3 on Timer C compare 3 */ |
bogdanm | 86:04dd9b1680ae | 5019 | #define HRTIM_ADC3R_AD3TCC4 ((uint32_t)0x00400000) /*!< ADC Trigger 3 on Timer C compare 4 */ |
bogdanm | 86:04dd9b1680ae | 5020 | #define HRTIM_ADC3R_AD3TCPER ((uint32_t)0x00800000) /*!< ADC Trigger 3 on Timer C period */ |
bogdanm | 86:04dd9b1680ae | 5021 | #define HRTIM_ADC3R_AD3TDC2 ((uint32_t)0x01000000) /*!< ADC Trigger 3 on Timer D compare 2 */ |
bogdanm | 86:04dd9b1680ae | 5022 | #define HRTIM_ADC3R_AD3TDC3 ((uint32_t)0x02000000) /*!< ADC Trigger 3 on Timer D compare 3 */ |
bogdanm | 86:04dd9b1680ae | 5023 | #define HRTIM_ADC3R_AD3TDC4 ((uint32_t)0x04000000) /*!< ADC Trigger 3 on Timer D compare 4 */ |
bogdanm | 86:04dd9b1680ae | 5024 | #define HRTIM_ADC3R_AD3TDPER ((uint32_t)0x08000000) /*!< ADC Trigger 3 on Timer D period */ |
bogdanm | 86:04dd9b1680ae | 5025 | #define HRTIM_ADC3R_AD3TEC2 ((uint32_t)0x10000000) /*!< ADC Trigger 3 on Timer E compare 2 */ |
bogdanm | 86:04dd9b1680ae | 5026 | #define HRTIM_ADC3R_AD3TEC3 ((uint32_t)0x20000000) /*!< ADC Trigger 3 on Timer E compare 3 */ |
bogdanm | 86:04dd9b1680ae | 5027 | #define HRTIM_ADC3R_AD3TEC4 ((uint32_t)0x40000000) /*!< ADC Trigger 3 on Timer E compare 4 */ |
bogdanm | 86:04dd9b1680ae | 5028 | #define HRTIM_ADC3R_AD3TEPER ((uint32_t)0x80000000) /*!< ADC Trigger 3 on Timer E period */ |
bogdanm | 86:04dd9b1680ae | 5029 | |
bogdanm | 86:04dd9b1680ae | 5030 | /******************* Bit definition for HRTIM_ADC4R register ****************/ |
bogdanm | 86:04dd9b1680ae | 5031 | #define HRTIM_ADC4R_AD4MC1 ((uint32_t)0x00000001) /*!< ADC Trigger 4 on master compare 1 */ |
bogdanm | 86:04dd9b1680ae | 5032 | #define HRTIM_ADC4R_AD4MC2 ((uint32_t)0x00000002) /*!< ADC Trigger 4 on master compare 2 */ |
bogdanm | 86:04dd9b1680ae | 5033 | #define HRTIM_ADC4R_AD4MC3 ((uint32_t)0x00000004) /*!< ADC Trigger 4 on master compare 3 */ |
bogdanm | 86:04dd9b1680ae | 5034 | #define HRTIM_ADC4R_AD4MC4 ((uint32_t)0x00000008) /*!< ADC Trigger 4 on master compare 4 */ |
bogdanm | 86:04dd9b1680ae | 5035 | #define HRTIM_ADC4R_AD4MPER ((uint32_t)0x00000010) /*!< ADC Trigger 4 on master period */ |
bogdanm | 86:04dd9b1680ae | 5036 | #define HRTIM_ADC4R_AD4EEV6 ((uint32_t)0x00000020) /*!< ADC Trigger 4 on external event 6 */ |
bogdanm | 86:04dd9b1680ae | 5037 | #define HRTIM_ADC4R_AD4EEV7 ((uint32_t)0x00000040) /*!< ADC Trigger 4 on external event 7 */ |
bogdanm | 86:04dd9b1680ae | 5038 | #define HRTIM_ADC4R_AD4EEV8 ((uint32_t)0x00000080) /*!< ADC Trigger 4 on external event 8 */ |
bogdanm | 86:04dd9b1680ae | 5039 | #define HRTIM_ADC4R_AD4EEV9 ((uint32_t)0x00000100) /*!< ADC Trigger 4 on external event 9 */ |
bogdanm | 86:04dd9b1680ae | 5040 | #define HRTIM_ADC4R_AD4EEV10 ((uint32_t)0x00000200) /*!< ADC Trigger 4 on external event 10 */ |
bogdanm | 86:04dd9b1680ae | 5041 | #define HRTIM_ADC4R_AD4TAC2 ((uint32_t)0x00000400) /*!< ADC Trigger 4 on Timer A compare 2 */ |
bogdanm | 86:04dd9b1680ae | 5042 | #define HRTIM_ADC4R_AD4TAC3 ((uint32_t)0x00000800) /*!< ADC Trigger 4 on Timer A compare 3 */ |
bogdanm | 86:04dd9b1680ae | 5043 | #define HRTIM_ADC4R_AD4TAC4 ((uint32_t)0x00001000) /*!< ADC Trigger 4 on Timer A compare 4*/ |
bogdanm | 86:04dd9b1680ae | 5044 | #define HRTIM_ADC4R_AD4TAPER ((uint32_t)0x00002000) /*!< ADC Trigger 4 on Timer A period */ |
bogdanm | 86:04dd9b1680ae | 5045 | #define HRTIM_ADC4R_AD4TBC2 ((uint32_t)0x00004000) /*!< ADC Trigger 4 on Timer B compare 2 */ |
bogdanm | 86:04dd9b1680ae | 5046 | #define HRTIM_ADC4R_AD4TBC3 ((uint32_t)0x00008000) /*!< ADC Trigger 4 on Timer B compare 3 */ |
bogdanm | 86:04dd9b1680ae | 5047 | #define HRTIM_ADC4R_AD4TBC4 ((uint32_t)0x00010000) /*!< ADC Trigger 4 on Timer B compare 4 */ |
bogdanm | 86:04dd9b1680ae | 5048 | #define HRTIM_ADC4R_AD4TBPER ((uint32_t)0x00020000) /*!< ADC Trigger 4 on Timer B period */ |
bogdanm | 86:04dd9b1680ae | 5049 | #define HRTIM_ADC4R_AD4TCC2 ((uint32_t)0x00040000) /*!< ADC Trigger 4 on Timer C compare 2 */ |
bogdanm | 86:04dd9b1680ae | 5050 | #define HRTIM_ADC4R_AD4TCC3 ((uint32_t)0x00080000) /*!< ADC Trigger 4 on Timer C compare 3 */ |
bogdanm | 86:04dd9b1680ae | 5051 | #define HRTIM_ADC4R_AD4TCC4 ((uint32_t)0x00100000) /*!< ADC Trigger 4 on Timer C compare 4 */ |
bogdanm | 86:04dd9b1680ae | 5052 | #define HRTIM_ADC4R_AD4TCPER ((uint32_t)0x00200000) /*!< ADC Trigger 4 on Timer C period */ |
bogdanm | 86:04dd9b1680ae | 5053 | #define HRTIM_ADC4R_AD4TCRST ((uint32_t)0x00400000) /*!< ADC Trigger 4 on Timer C reset */ |
bogdanm | 86:04dd9b1680ae | 5054 | #define HRTIM_ADC4R_AD4TDC2 ((uint32_t)0x00800000) /*!< ADC Trigger 4 on Timer D compare 2 */ |
bogdanm | 86:04dd9b1680ae | 5055 | #define HRTIM_ADC4R_AD4TDC3 ((uint32_t)0x01000000) /*!< ADC Trigger 4 on Timer D compare 3 */ |
bogdanm | 86:04dd9b1680ae | 5056 | #define HRTIM_ADC4R_AD4TDC4 ((uint32_t)0x02000000) /*!< ADC Trigger 4 on Timer D compare 4*/ |
bogdanm | 86:04dd9b1680ae | 5057 | #define HRTIM_ADC4R_AD4TDPER ((uint32_t)0x04000000) /*!< ADC Trigger 4 on Timer D period */ |
bogdanm | 86:04dd9b1680ae | 5058 | #define HRTIM_ADC4R_AD4TDRST ((uint32_t)0x08000000) /*!< ADC Trigger 4 on Timer D reset */ |
bogdanm | 86:04dd9b1680ae | 5059 | #define HRTIM_ADC4R_AD4TEC2 ((uint32_t)0x10000000) /*!< ADC Trigger 4 on Timer E compare 2 */ |
bogdanm | 86:04dd9b1680ae | 5060 | #define HRTIM_ADC4R_AD4TEC3 ((uint32_t)0x20000000) /*!< ADC Trigger 4 on Timer E compare 3 */ |
bogdanm | 86:04dd9b1680ae | 5061 | #define HRTIM_ADC4R_AD4TEC4 ((uint32_t)0x40000000) /*!< ADC Trigger 4 on Timer E compare 4 */ |
bogdanm | 86:04dd9b1680ae | 5062 | #define HRTIM_ADC4R_AD4TERST ((uint32_t)0x80000000) /*!< ADC Trigger 4 on Timer E reset */ |
bogdanm | 86:04dd9b1680ae | 5063 | |
bogdanm | 86:04dd9b1680ae | 5064 | /******************* Bit definition for HRTIM_DLLCR register ****************/ |
bogdanm | 86:04dd9b1680ae | 5065 | #define HRTIM_DLLCR_CAL ((uint32_t)0x00000001) /*!< DLL calibration start */ |
bogdanm | 86:04dd9b1680ae | 5066 | #define HRTIM_DLLCR_CALEN ((uint32_t)0x00000002) /*!< DLL calibration enable */ |
bogdanm | 86:04dd9b1680ae | 5067 | #define HRTIM_DLLCR_CALRTE ((uint32_t)0x0000000C) /*!< DLL calibration rate */ |
bogdanm | 86:04dd9b1680ae | 5068 | #define HRTIM_DLLCR_CALRTE_0 ((uint32_t)0x00000004) /*!< DLL calibration rate bit 0 */ |
bogdanm | 86:04dd9b1680ae | 5069 | #define HRTIM_DLLCR_CALRTE_1 ((uint32_t)0x00000008) /*!< DLL calibration rate bit 1 */ |
bogdanm | 86:04dd9b1680ae | 5070 | |
bogdanm | 86:04dd9b1680ae | 5071 | /******************* Bit definition for HRTIM_FLTINR1 register ***************/ |
bogdanm | 86:04dd9b1680ae | 5072 | #define HRTIM_FLTINR1_FLT1E ((uint32_t)0x00000001) /*!< Fault 1 enable */ |
bogdanm | 86:04dd9b1680ae | 5073 | #define HRTIM_FLTINR1_FLT1P ((uint32_t)0x00000002) /*!< Fault 1 polarity */ |
bogdanm | 86:04dd9b1680ae | 5074 | #define HRTIM_FLTINR1_FLT1SRC ((uint32_t)0x00000004) /*!< Fault 1 source */ |
bogdanm | 86:04dd9b1680ae | 5075 | #define HRTIM_FLTINR1_FLT1F ((uint32_t)0x00000078) /*!< Fault 1 filter */ |
bogdanm | 86:04dd9b1680ae | 5076 | #define HRTIM_FLTINR1_FLT1F_0 ((uint32_t)0x00000008) /*!< Fault 1 filter bit 0 */ |
bogdanm | 86:04dd9b1680ae | 5077 | #define HRTIM_FLTINR1_FLT1F_1 ((uint32_t)0x00000010) /*!< Fault 1 filter bit 1 */ |
bogdanm | 86:04dd9b1680ae | 5078 | #define HRTIM_FLTINR1_FLT1F_2 ((uint32_t)0x00000020) /*!< Fault 1 filter bit 2 */ |
bogdanm | 86:04dd9b1680ae | 5079 | #define HRTIM_FLTINR1_FLT1F_3 ((uint32_t)0x00000040) /*!< Fault 1 filter bit 3 */ |
bogdanm | 86:04dd9b1680ae | 5080 | #define HRTIM_FLTINR1_FLT1LCK ((uint32_t)0x00000080) /*!< Fault 1 lock */ |
bogdanm | 86:04dd9b1680ae | 5081 | |
bogdanm | 86:04dd9b1680ae | 5082 | #define HRTIM_FLTINR1_FLT2E ((uint32_t)0x00000100) /*!< Fault 2 enable */ |
bogdanm | 86:04dd9b1680ae | 5083 | #define HRTIM_FLTINR1_FLT2P ((uint32_t)0x00000200) /*!< Fault 2 polarity */ |
bogdanm | 86:04dd9b1680ae | 5084 | #define HRTIM_FLTINR1_FLT2SRC ((uint32_t)0x00000400) /*!< Fault 2 source */ |
bogdanm | 86:04dd9b1680ae | 5085 | #define HRTIM_FLTINR1_FLT2F ((uint32_t)0x00007800) /*!< Fault 2 filter */ |
bogdanm | 86:04dd9b1680ae | 5086 | #define HRTIM_FLTINR1_FLT2F_0 ((uint32_t)0x00000800) /*!< Fault 2 filter bit 0 */ |
bogdanm | 86:04dd9b1680ae | 5087 | #define HRTIM_FLTINR1_FLT2F_1 ((uint32_t)0x00001000) /*!< Fault 2 filter bit 1 */ |
bogdanm | 86:04dd9b1680ae | 5088 | #define HRTIM_FLTINR1_FLT2F_2 ((uint32_t)0x00002000) /*!< Fault 2 filter bit 2 */ |
bogdanm | 86:04dd9b1680ae | 5089 | #define HRTIM_FLTINR1_FLT2F_3 ((uint32_t)0x00004000) /*!< Fault 2 filter bit 3 */ |
bogdanm | 86:04dd9b1680ae | 5090 | #define HRTIM_FLTINR1_FLT2LCK ((uint32_t)0x00008000) /*!< Fault 2 lock */ |
bogdanm | 86:04dd9b1680ae | 5091 | |
bogdanm | 86:04dd9b1680ae | 5092 | #define HRTIM_FLTINR1_FLT3E ((uint32_t)0x00010000) /*!< Fault 3 enable */ |
bogdanm | 86:04dd9b1680ae | 5093 | #define HRTIM_FLTINR1_FLT3P ((uint32_t)0x00020000) /*!< Fault 3 polarity */ |
bogdanm | 86:04dd9b1680ae | 5094 | #define HRTIM_FLTINR1_FLT3SRC ((uint32_t)0x00040000) /*!< Fault 3 source */ |
bogdanm | 86:04dd9b1680ae | 5095 | #define HRTIM_FLTINR1_FLT3F ((uint32_t)0x00780000) /*!< Fault 3 filter */ |
bogdanm | 86:04dd9b1680ae | 5096 | #define HRTIM_FLTINR1_FLT3F_0 ((uint32_t)0x00080000) /*!< Fault 3 filter bit 0 */ |
bogdanm | 86:04dd9b1680ae | 5097 | #define HRTIM_FLTINR1_FLT3F_1 ((uint32_t)0x00100000) /*!< Fault 3 filter bit 1 */ |
bogdanm | 86:04dd9b1680ae | 5098 | #define HRTIM_FLTINR1_FLT3F_2 ((uint32_t)0x00200000) /*!< Fault 3 filter bit 2 */ |
bogdanm | 86:04dd9b1680ae | 5099 | #define HRTIM_FLTINR1_FLT3F_3 ((uint32_t)0x00400000) /*!< Fault 3 filter bit 3 */ |
bogdanm | 86:04dd9b1680ae | 5100 | #define HRTIM_FLTINR1_FLT3LCK ((uint32_t)0x00800000) /*!< Fault 3 lock */ |
bogdanm | 86:04dd9b1680ae | 5101 | |
bogdanm | 86:04dd9b1680ae | 5102 | #define HRTIM_FLTINR1_FLT4E ((uint32_t)0x01000000) /*!< Fault 4 enable */ |
bogdanm | 86:04dd9b1680ae | 5103 | #define HRTIM_FLTINR1_FLT4P ((uint32_t)0x02000000) /*!< Fault 4 polarity */ |
bogdanm | 86:04dd9b1680ae | 5104 | #define HRTIM_FLTINR1_FLT4SRC ((uint32_t)0x04000000) /*!< Fault 4 source */ |
bogdanm | 86:04dd9b1680ae | 5105 | #define HRTIM_FLTINR1_FLT4F ((uint32_t)0x78000000) /*!< Fault 4 filter */ |
bogdanm | 86:04dd9b1680ae | 5106 | #define HRTIM_FLTINR1_FLT4F_0 ((uint32_t)0x08000000) /*!< Fault 4 filter bit 0 */ |
bogdanm | 86:04dd9b1680ae | 5107 | #define HRTIM_FLTINR1_FLT4F_1 ((uint32_t)0x10000000) /*!< Fault 4 filter bit 1 */ |
bogdanm | 86:04dd9b1680ae | 5108 | #define HRTIM_FLTINR1_FLT4F_2 ((uint32_t)0x20000000) /*!< Fault 4 filter bit 2 */ |
bogdanm | 86:04dd9b1680ae | 5109 | #define HRTIM_FLTINR1_FLT4F_3 ((uint32_t)0x40000000) /*!< Fault 4 filter bit 3 */ |
bogdanm | 86:04dd9b1680ae | 5110 | #define HRTIM_FLTINR1_FLT4LCK ((uint32_t)0x80000000) /*!< Fault 4 lock */ |
bogdanm | 86:04dd9b1680ae | 5111 | |
bogdanm | 86:04dd9b1680ae | 5112 | /******************* Bit definition for HRTIM_FLTINR2 register ***************/ |
bogdanm | 86:04dd9b1680ae | 5113 | #define HRTIM_FLTINR2_FLT5E ((uint32_t)0x00000001) /*!< Fault 5 enable */ |
bogdanm | 86:04dd9b1680ae | 5114 | #define HRTIM_FLTINR2_FLT5P ((uint32_t)0x00000002) /*!< Fault 5 polarity */ |
bogdanm | 86:04dd9b1680ae | 5115 | #define HRTIM_FLTINR2_FLT5SRC ((uint32_t)0x00000004) /*!< Fault 5 source */ |
bogdanm | 86:04dd9b1680ae | 5116 | #define HRTIM_FLTINR2_FLT5F ((uint32_t)0x00000078) /*!< Fault 5 filter */ |
bogdanm | 86:04dd9b1680ae | 5117 | #define HRTIM_FLTINR2_FLT5F_0 ((uint32_t)0x00000008) /*!< Fault 5 filter bit 0 */ |
bogdanm | 86:04dd9b1680ae | 5118 | #define HRTIM_FLTINR2_FLT5F_1 ((uint32_t)0x00000010) /*!< Fault 5 filter bit 1 */ |
bogdanm | 86:04dd9b1680ae | 5119 | #define HRTIM_FLTINR2_FLT5F_2 ((uint32_t)0x00000020) /*!< Fault 5 filter bit 2 */ |
bogdanm | 86:04dd9b1680ae | 5120 | #define HRTIM_FLTINR2_FLT5F_3 ((uint32_t)0x00000040) /*!< Fault 5 filter bit 3 */ |
bogdanm | 86:04dd9b1680ae | 5121 | #define HRTIM_FLTINR2_FLT5LCK ((uint32_t)0x00000080) /*!< Fault 5 lock */ |
bogdanm | 86:04dd9b1680ae | 5122 | #define HRTIM_FLTINR2_FLTSD ((uint32_t)0x03000000) /*!< Fault sampling clock division */ |
bogdanm | 86:04dd9b1680ae | 5123 | #define HRTIM_FLTINR2_FLTSD_0 ((uint32_t)0x01000000) /*!< Fault sampling clock division bit 0 */ |
bogdanm | 86:04dd9b1680ae | 5124 | #define HRTIM_FLTINR2_FLTSD_1 ((uint32_t)0x02000000) /*!< Fault sampling clock division bit 1 */ |
bogdanm | 86:04dd9b1680ae | 5125 | |
bogdanm | 86:04dd9b1680ae | 5126 | /******************* Bit definition for HRTIM_BDMUPR register ***************/ |
bogdanm | 86:04dd9b1680ae | 5127 | #define HRTIM_BDMUPR_MCR ((uint32_t)0x00000001) /*!< MCR register update enable */ |
bogdanm | 86:04dd9b1680ae | 5128 | #define HRTIM_BDMUPR_MICR ((uint32_t)0x00000002) /*!< MICR register update enable */ |
bogdanm | 86:04dd9b1680ae | 5129 | #define HRTIM_BDMUPR_MDIER ((uint32_t)0x00000004) /*!< MDIER register update enable */ |
bogdanm | 86:04dd9b1680ae | 5130 | #define HRTIM_BDMUPR_MCNT ((uint32_t)0x00000008) /*!< MCNT register update enable */ |
bogdanm | 86:04dd9b1680ae | 5131 | #define HRTIM_BDMUPR_MPER ((uint32_t)0x00000010) /*!< MPER register update enable */ |
bogdanm | 86:04dd9b1680ae | 5132 | #define HRTIM_BDMUPR_MREP ((uint32_t)0x00000020) /*!< MREP register update enable */ |
bogdanm | 86:04dd9b1680ae | 5133 | #define HRTIM_BDMUPR_MCMP1 ((uint32_t)0x00000040) /*!< MCMP1 register update enable */ |
bogdanm | 86:04dd9b1680ae | 5134 | #define HRTIM_BDMUPR_MCMP2 ((uint32_t)0x00000080) /*!< MCMP2 register update enable */ |
bogdanm | 86:04dd9b1680ae | 5135 | #define HRTIM_BDMUPR_MCMP3 ((uint32_t)0x00000100) /*!< MCMP3 register update enable */ |
bogdanm | 86:04dd9b1680ae | 5136 | #define HRTIM_BDMUPR_MCMP4 ((uint32_t)0x00000200) /*!< MPCMP4 register update enable */ |
bogdanm | 86:04dd9b1680ae | 5137 | |
bogdanm | 86:04dd9b1680ae | 5138 | /******************* Bit definition for HRTIM_BDTUPR register ***************/ |
bogdanm | 86:04dd9b1680ae | 5139 | #define HRTIM_BDTUPR_TIMCR ((uint32_t)0x00000001) /*!< TIMCR register update enable */ |
bogdanm | 86:04dd9b1680ae | 5140 | #define HRTIM_BDTUPR_TIMICR ((uint32_t)0x00000002) /*!< TIMICR register update enable */ |
bogdanm | 86:04dd9b1680ae | 5141 | #define HRTIM_BDTUPR_TIMDIER ((uint32_t)0x00000004) /*!< TIMDIER register update enable */ |
bogdanm | 86:04dd9b1680ae | 5142 | #define HRTIM_BDTUPR_TIMCNT ((uint32_t)0x00000008) /*!< TIMCNT register update enable */ |
bogdanm | 86:04dd9b1680ae | 5143 | #define HRTIM_BDTUPR_TIMPER ((uint32_t)0x00000010) /*!< TIMPER register update enable */ |
bogdanm | 86:04dd9b1680ae | 5144 | #define HRTIM_BDTUPR_TIMREP ((uint32_t)0x00000020) /*!< TIMREP register update enable */ |
bogdanm | 86:04dd9b1680ae | 5145 | #define HRTIM_BDTUPR_TIMCMP1 ((uint32_t)0x00000040) /*!< TIMCMP1 register update enable */ |
bogdanm | 86:04dd9b1680ae | 5146 | #define HRTIM_BDTUPR_TIMCMP2 ((uint32_t)0x00000080) /*!< TIMCMP2 register update enable */ |
bogdanm | 86:04dd9b1680ae | 5147 | #define HRTIM_BDTUPR_TIMCMP3 ((uint32_t)0x00000100) /*!< TIMCMP3 register update enable */ |
bogdanm | 86:04dd9b1680ae | 5148 | #define HRTIM_BDTUPR_TIMCMP4 ((uint32_t)0x00000200) /*!< TIMCMP4 register update enable */ |
bogdanm | 86:04dd9b1680ae | 5149 | #define HRTIM_BDTUPR_TIMDTR ((uint32_t)0x00000400) /*!< TIMDTR register update enable */ |
bogdanm | 86:04dd9b1680ae | 5150 | #define HRTIM_BDTUPR_TIMSET1R ((uint32_t)0x00000800) /*!< TIMSET1R register update enable */ |
bogdanm | 86:04dd9b1680ae | 5151 | #define HRTIM_BDTUPR_TIMRST1R ((uint32_t)0x00001000) /*!< TIMRST1R register update enable */ |
bogdanm | 86:04dd9b1680ae | 5152 | #define HRTIM_BDTUPR_TIMSET2R ((uint32_t)0x00002000) /*!< TIMSET2R register update enable */ |
bogdanm | 86:04dd9b1680ae | 5153 | #define HRTIM_BDTUPR_TIMRST2R ((uint32_t)0x00004000) /*!< TIMRST2R register update enable */ |
bogdanm | 86:04dd9b1680ae | 5154 | #define HRTIM_BDTUPR_TIMEEFR1 ((uint32_t)0x00008000) /*!< TIMEEFR1 register update enable */ |
bogdanm | 86:04dd9b1680ae | 5155 | #define HRTIM_BDTUPR_TIMEEFR2 ((uint32_t)0x00010000) /*!< TIMEEFR2 register update enable */ |
bogdanm | 86:04dd9b1680ae | 5156 | #define HRTIM_BDTUPR_TIMRSTR ((uint32_t)0x00020000) /*!< TIMRSTR register update enable */ |
bogdanm | 86:04dd9b1680ae | 5157 | #define HRTIM_BDTUPR_TIMCHPR ((uint32_t)0x00040000) /*!< TIMCHPR register update enable */ |
bogdanm | 86:04dd9b1680ae | 5158 | #define HRTIM_BDTUPR_TIMOUTR ((uint32_t)0x00080000) /*!< TIMOUTR register update enable */ |
bogdanm | 86:04dd9b1680ae | 5159 | #define HRTIM_BDTUPR_TIMFLTR ((uint32_t)0x00100000) /*!< TIMFLTR register update enable */ |
bogdanm | 86:04dd9b1680ae | 5160 | |
bogdanm | 86:04dd9b1680ae | 5161 | /******************* Bit definition for HRTIM_BDMADR register ***************/ |
bogdanm | 86:04dd9b1680ae | 5162 | #define HRTIM_BDMADR_BDMADR ((uint32_t)0xFFFFFFFF) /*!< Burst DMA Data register */ |
bogdanm | 86:04dd9b1680ae | 5163 | |
bogdanm | 86:04dd9b1680ae | 5164 | /******************************************************************************/ |
bogdanm | 86:04dd9b1680ae | 5165 | /* */ |
bogdanm | 86:04dd9b1680ae | 5166 | /* Inter-integrated Circuit Interface (I2C) */ |
bogdanm | 86:04dd9b1680ae | 5167 | /* */ |
bogdanm | 86:04dd9b1680ae | 5168 | /******************************************************************************/ |
bogdanm | 86:04dd9b1680ae | 5169 | /******************* Bit definition for I2C_CR1 register *******************/ |
bogdanm | 86:04dd9b1680ae | 5170 | #define I2C_CR1_PE ((uint32_t)0x00000001) /*!< Peripheral enable */ |
bogdanm | 86:04dd9b1680ae | 5171 | #define I2C_CR1_TXIE ((uint32_t)0x00000002) /*!< TX interrupt enable */ |
bogdanm | 86:04dd9b1680ae | 5172 | #define I2C_CR1_RXIE ((uint32_t)0x00000004) /*!< RX interrupt enable */ |
bogdanm | 86:04dd9b1680ae | 5173 | #define I2C_CR1_ADDRIE ((uint32_t)0x00000008) /*!< Address match interrupt enable */ |
bogdanm | 86:04dd9b1680ae | 5174 | #define I2C_CR1_NACKIE ((uint32_t)0x00000010) /*!< NACK received interrupt enable */ |
bogdanm | 86:04dd9b1680ae | 5175 | #define I2C_CR1_STOPIE ((uint32_t)0x00000020) /*!< STOP detection interrupt enable */ |
bogdanm | 86:04dd9b1680ae | 5176 | #define I2C_CR1_TCIE ((uint32_t)0x00000040) /*!< Transfer complete interrupt enable */ |
bogdanm | 86:04dd9b1680ae | 5177 | #define I2C_CR1_ERRIE ((uint32_t)0x00000080) /*!< Errors interrupt enable */ |
bogdanm | 86:04dd9b1680ae | 5178 | #define I2C_CR1_DFN ((uint32_t)0x00000F00) /*!< Digital noise filter */ |
bogdanm | 86:04dd9b1680ae | 5179 | #define I2C_CR1_ANFOFF ((uint32_t)0x00001000) /*!< Analog noise filter OFF */ |
bogdanm | 86:04dd9b1680ae | 5180 | #define I2C_CR1_SWRST ((uint32_t)0x00002000) /*!< Software reset */ |
bogdanm | 86:04dd9b1680ae | 5181 | #define I2C_CR1_TXDMAEN ((uint32_t)0x00004000) /*!< DMA transmission requests enable */ |
bogdanm | 86:04dd9b1680ae | 5182 | #define I2C_CR1_RXDMAEN ((uint32_t)0x00008000) /*!< DMA reception requests enable */ |
bogdanm | 86:04dd9b1680ae | 5183 | #define I2C_CR1_SBC ((uint32_t)0x00010000) /*!< Slave byte control */ |
bogdanm | 86:04dd9b1680ae | 5184 | #define I2C_CR1_NOSTRETCH ((uint32_t)0x00020000) /*!< Clock stretching disable */ |
bogdanm | 86:04dd9b1680ae | 5185 | #define I2C_CR1_WUPEN ((uint32_t)0x00040000) /*!< Wakeup from STOP enable */ |
bogdanm | 86:04dd9b1680ae | 5186 | #define I2C_CR1_GCEN ((uint32_t)0x00080000) /*!< General call enable */ |
bogdanm | 86:04dd9b1680ae | 5187 | #define I2C_CR1_SMBHEN ((uint32_t)0x00100000) /*!< SMBus host address enable */ |
bogdanm | 86:04dd9b1680ae | 5188 | #define I2C_CR1_SMBDEN ((uint32_t)0x00200000) /*!< SMBus device default address enable */ |
bogdanm | 86:04dd9b1680ae | 5189 | #define I2C_CR1_ALERTEN ((uint32_t)0x00400000) /*!< SMBus alert enable */ |
bogdanm | 86:04dd9b1680ae | 5190 | #define I2C_CR1_PECEN ((uint32_t)0x00800000) /*!< PEC enable */ |
bogdanm | 86:04dd9b1680ae | 5191 | |
bogdanm | 86:04dd9b1680ae | 5192 | /****************** Bit definition for I2C_CR2 register ********************/ |
bogdanm | 86:04dd9b1680ae | 5193 | #define I2C_CR2_SADD ((uint32_t)0x000003FF) /*!< Slave address (master mode) */ |
bogdanm | 86:04dd9b1680ae | 5194 | #define I2C_CR2_RD_WRN ((uint32_t)0x00000400) /*!< Transfer direction (master mode) */ |
bogdanm | 86:04dd9b1680ae | 5195 | #define I2C_CR2_ADD10 ((uint32_t)0x00000800) /*!< 10-bit addressing mode (master mode) */ |
bogdanm | 86:04dd9b1680ae | 5196 | #define I2C_CR2_HEAD10R ((uint32_t)0x00001000) /*!< 10-bit address header only read direction (master mode) */ |
bogdanm | 86:04dd9b1680ae | 5197 | #define I2C_CR2_START ((uint32_t)0x00002000) /*!< START generation */ |
bogdanm | 86:04dd9b1680ae | 5198 | #define I2C_CR2_STOP ((uint32_t)0x00004000) /*!< STOP generation (master mode) */ |
bogdanm | 86:04dd9b1680ae | 5199 | #define I2C_CR2_NACK ((uint32_t)0x00008000) /*!< NACK generation (slave mode) */ |
bogdanm | 86:04dd9b1680ae | 5200 | #define I2C_CR2_NBYTES ((uint32_t)0x00FF0000) /*!< Number of bytes */ |
bogdanm | 86:04dd9b1680ae | 5201 | #define I2C_CR2_RELOAD ((uint32_t)0x01000000) /*!< NBYTES reload mode */ |
bogdanm | 86:04dd9b1680ae | 5202 | #define I2C_CR2_AUTOEND ((uint32_t)0x02000000) /*!< Automatic end mode (master mode) */ |
bogdanm | 86:04dd9b1680ae | 5203 | #define I2C_CR2_PECBYTE ((uint32_t)0x04000000) /*!< Packet error checking byte */ |
bogdanm | 86:04dd9b1680ae | 5204 | |
bogdanm | 86:04dd9b1680ae | 5205 | /******************* Bit definition for I2C_OAR1 register ******************/ |
bogdanm | 86:04dd9b1680ae | 5206 | #define I2C_OAR1_OA1 ((uint32_t)0x000003FF) /*!< Interface own address 1 */ |
bogdanm | 86:04dd9b1680ae | 5207 | #define I2C_OAR1_OA1MODE ((uint32_t)0x00000400) /*!< Own address 1 10-bit mode */ |
bogdanm | 86:04dd9b1680ae | 5208 | #define I2C_OAR1_OA1EN ((uint32_t)0x00008000) /*!< Own address 1 enable */ |
bogdanm | 86:04dd9b1680ae | 5209 | |
bogdanm | 86:04dd9b1680ae | 5210 | /******************* Bit definition for I2C_OAR2 register *******************/ |
bogdanm | 86:04dd9b1680ae | 5211 | #define I2C_OAR2_OA2 ((uint32_t)0x000000FE) /*!< Interface own address 2 */ |
bogdanm | 86:04dd9b1680ae | 5212 | #define I2C_OAR2_OA2MSK ((uint32_t)0x00000700) /*!< Own address 2 masks */ |
bogdanm | 86:04dd9b1680ae | 5213 | #define I2C_OAR2_OA2EN ((uint32_t)0x00008000) /*!< Own address 2 enable */ |
bogdanm | 86:04dd9b1680ae | 5214 | |
bogdanm | 86:04dd9b1680ae | 5215 | /******************* Bit definition for I2C_TIMINGR register *****************/ |
bogdanm | 86:04dd9b1680ae | 5216 | #define I2C_TIMINGR_SCLL ((uint32_t)0x000000FF) /*!< SCL low period (master mode) */ |
bogdanm | 86:04dd9b1680ae | 5217 | #define I2C_TIMINGR_SCLH ((uint32_t)0x0000FF00) /*!< SCL high period (master mode) */ |
bogdanm | 86:04dd9b1680ae | 5218 | #define I2C_TIMINGR_SDADEL ((uint32_t)0x000F0000) /*!< Data hold time */ |
bogdanm | 86:04dd9b1680ae | 5219 | #define I2C_TIMINGR_SCLDEL ((uint32_t)0x00F00000) /*!< Data setup time */ |
bogdanm | 86:04dd9b1680ae | 5220 | #define I2C_TIMINGR_PRESC ((uint32_t)0xF0000000) /*!< Timings prescaler */ |
bogdanm | 86:04dd9b1680ae | 5221 | |
bogdanm | 86:04dd9b1680ae | 5222 | /******************* Bit definition for I2C_TIMEOUTR register *****************/ |
bogdanm | 86:04dd9b1680ae | 5223 | #define I2C_TIMEOUTR_TIMEOUTA ((uint32_t)0x00000FFF) /*!< Bus timeout A */ |
bogdanm | 86:04dd9b1680ae | 5224 | #define I2C_TIMEOUTR_TIDLE ((uint32_t)0x00001000) /*!< Idle clock timeout detection */ |
bogdanm | 86:04dd9b1680ae | 5225 | #define I2C_TIMEOUTR_TIMOUTEN ((uint32_t)0x00008000) /*!< Clock timeout enable */ |
bogdanm | 86:04dd9b1680ae | 5226 | #define I2C_TIMEOUTR_TIMEOUTB ((uint32_t)0x0FFF0000) /*!< Bus timeout B*/ |
bogdanm | 86:04dd9b1680ae | 5227 | #define I2C_TIMEOUTR_TEXTEN ((uint32_t)0x80000000) /*!< Extended clock timeout enable */ |
bogdanm | 86:04dd9b1680ae | 5228 | |
bogdanm | 86:04dd9b1680ae | 5229 | /****************** Bit definition for I2C_ISR register *********************/ |
bogdanm | 86:04dd9b1680ae | 5230 | #define I2C_ISR_TXE ((uint32_t)0x00000001) /*!< Transmit data register empty */ |
bogdanm | 86:04dd9b1680ae | 5231 | #define I2C_ISR_TXIS ((uint32_t)0x00000002) /*!< Transmit interrupt status */ |
bogdanm | 86:04dd9b1680ae | 5232 | #define I2C_ISR_RXNE ((uint32_t)0x00000004) /*!< Receive data register not empty */ |
bogdanm | 86:04dd9b1680ae | 5233 | #define I2C_ISR_ADDR ((uint32_t)0x00000008) /*!< Address matched (slave mode)*/ |
bogdanm | 86:04dd9b1680ae | 5234 | #define I2C_ISR_NACKF ((uint32_t)0x00000010) /*!< NACK received flag */ |
bogdanm | 86:04dd9b1680ae | 5235 | #define I2C_ISR_STOPF ((uint32_t)0x00000020) /*!< STOP detection flag */ |
bogdanm | 86:04dd9b1680ae | 5236 | #define I2C_ISR_TC ((uint32_t)0x00000040) /*!< Transfer complete (master mode) */ |
bogdanm | 86:04dd9b1680ae | 5237 | #define I2C_ISR_TCR ((uint32_t)0x00000080) /*!< Transfer complete reload */ |
bogdanm | 86:04dd9b1680ae | 5238 | #define I2C_ISR_BERR ((uint32_t)0x00000100) /*!< Bus error */ |
bogdanm | 86:04dd9b1680ae | 5239 | #define I2C_ISR_ARLO ((uint32_t)0x00000200) /*!< Arbitration lost */ |
bogdanm | 86:04dd9b1680ae | 5240 | #define I2C_ISR_OVR ((uint32_t)0x00000400) /*!< Overrun/Underrun */ |
bogdanm | 86:04dd9b1680ae | 5241 | #define I2C_ISR_PECERR ((uint32_t)0x00000800) /*!< PEC error in reception */ |
bogdanm | 86:04dd9b1680ae | 5242 | #define I2C_ISR_TIMEOUT ((uint32_t)0x00001000) /*!< Timeout or Tlow detection flag */ |
bogdanm | 86:04dd9b1680ae | 5243 | #define I2C_ISR_ALERT ((uint32_t)0x00002000) /*!< SMBus alert */ |
bogdanm | 86:04dd9b1680ae | 5244 | #define I2C_ISR_BUSY ((uint32_t)0x00008000) /*!< Bus busy */ |
bogdanm | 86:04dd9b1680ae | 5245 | #define I2C_ISR_DIR ((uint32_t)0x00010000) /*!< Transfer direction (slave mode) */ |
bogdanm | 86:04dd9b1680ae | 5246 | #define I2C_ISR_ADDCODE ((uint32_t)0x00FE0000) /*!< Address match code (slave mode) */ |
bogdanm | 86:04dd9b1680ae | 5247 | |
bogdanm | 86:04dd9b1680ae | 5248 | /****************** Bit definition for I2C_ICR register *********************/ |
bogdanm | 86:04dd9b1680ae | 5249 | #define I2C_ICR_ADDRCF ((uint32_t)0x00000008) /*!< Address matched clear flag */ |
bogdanm | 86:04dd9b1680ae | 5250 | #define I2C_ICR_NACKCF ((uint32_t)0x00000010) /*!< NACK clear flag */ |
bogdanm | 86:04dd9b1680ae | 5251 | #define I2C_ICR_STOPCF ((uint32_t)0x00000020) /*!< STOP detection clear flag */ |
bogdanm | 86:04dd9b1680ae | 5252 | #define I2C_ICR_BERRCF ((uint32_t)0x00000100) /*!< Bus error clear flag */ |
bogdanm | 86:04dd9b1680ae | 5253 | #define I2C_ICR_ARLOCF ((uint32_t)0x00000200) /*!< Arbitration lost clear flag */ |
bogdanm | 86:04dd9b1680ae | 5254 | #define I2C_ICR_OVRCF ((uint32_t)0x00000400) /*!< Overrun/Underrun clear flag */ |
bogdanm | 86:04dd9b1680ae | 5255 | #define I2C_ICR_PECCF ((uint32_t)0x00000800) /*!< PAC error clear flag */ |
bogdanm | 86:04dd9b1680ae | 5256 | #define I2C_ICR_TIMOUTCF ((uint32_t)0x00001000) /*!< Timeout clear flag */ |
bogdanm | 86:04dd9b1680ae | 5257 | #define I2C_ICR_ALERTCF ((uint32_t)0x00002000) /*!< Alert clear flag */ |
bogdanm | 86:04dd9b1680ae | 5258 | |
bogdanm | 86:04dd9b1680ae | 5259 | /****************** Bit definition for I2C_PECR register ********************/ |
bogdanm | 86:04dd9b1680ae | 5260 | #define I2C_PECR_PEC ((uint32_t)0x000000FF) /*!< PEC register */ |
bogdanm | 86:04dd9b1680ae | 5261 | |
bogdanm | 86:04dd9b1680ae | 5262 | /****************** Bit definition for I2C_RXDR register *********************/ |
bogdanm | 86:04dd9b1680ae | 5263 | #define I2C_RXDR_RXDATA ((uint32_t)0x000000FF) /*!< 8-bit receive data */ |
bogdanm | 86:04dd9b1680ae | 5264 | |
bogdanm | 86:04dd9b1680ae | 5265 | /****************** Bit definition for I2C_TXDR register *********************/ |
bogdanm | 86:04dd9b1680ae | 5266 | #define I2C_TXDR_TXDATA ((uint32_t)0x000000FF) /*!< 8-bit transmit data */ |
bogdanm | 86:04dd9b1680ae | 5267 | |
bogdanm | 86:04dd9b1680ae | 5268 | |
bogdanm | 86:04dd9b1680ae | 5269 | /******************************************************************************/ |
bogdanm | 86:04dd9b1680ae | 5270 | /* */ |
bogdanm | 86:04dd9b1680ae | 5271 | /* Independent WATCHDOG (IWDG) */ |
bogdanm | 86:04dd9b1680ae | 5272 | /* */ |
bogdanm | 86:04dd9b1680ae | 5273 | /******************************************************************************/ |
bogdanm | 86:04dd9b1680ae | 5274 | /******************* Bit definition for IWDG_KR register ********************/ |
bogdanm | 86:04dd9b1680ae | 5275 | #define IWDG_KR_KEY ((uint32_t)0x0000FFFF) /*!< Key value (write only, read 0000h) */ |
bogdanm | 86:04dd9b1680ae | 5276 | |
bogdanm | 86:04dd9b1680ae | 5277 | /******************* Bit definition for IWDG_PR register ********************/ |
bogdanm | 86:04dd9b1680ae | 5278 | #define IWDG_PR_PR ((uint32_t)0x00000007) /*!< PR[2:0] (Prescaler divider) */ |
bogdanm | 86:04dd9b1680ae | 5279 | #define IWDG_PR_PR_0 ((uint32_t)0x00000001) /*!< Bit 0 */ |
bogdanm | 86:04dd9b1680ae | 5280 | #define IWDG_PR_PR_1 ((uint32_t)0x00000002) /*!< Bit 1 */ |
bogdanm | 86:04dd9b1680ae | 5281 | #define IWDG_PR_PR_2 ((uint32_t)0x00000004) /*!< Bit 2 */ |
bogdanm | 86:04dd9b1680ae | 5282 | |
bogdanm | 86:04dd9b1680ae | 5283 | /******************* Bit definition for IWDG_RLR register *******************/ |
bogdanm | 86:04dd9b1680ae | 5284 | #define IWDG_RLR_RL ((uint32_t)0x00000FFF) /*!< Watchdog counter reload value */ |
bogdanm | 86:04dd9b1680ae | 5285 | |
bogdanm | 86:04dd9b1680ae | 5286 | /******************* Bit definition for IWDG_SR register ********************/ |
bogdanm | 86:04dd9b1680ae | 5287 | #define IWDG_SR_PVU ((uint32_t)0x00000001) /*!< Watchdog prescaler value update */ |
bogdanm | 86:04dd9b1680ae | 5288 | #define IWDG_SR_RVU ((uint32_t)0x00000002) /*!< Watchdog counter reload value update */ |
bogdanm | 86:04dd9b1680ae | 5289 | #define IWDG_SR_WVU ((uint32_t)0x00000004) /*!< Watchdog counter window value update */ |
bogdanm | 86:04dd9b1680ae | 5290 | |
bogdanm | 86:04dd9b1680ae | 5291 | /******************* Bit definition for IWDG_KR register ********************/ |
bogdanm | 86:04dd9b1680ae | 5292 | #define IWDG_WINR_WIN ((uint32_t)0x00000FFF) /*!< Watchdog counter window value */ |
bogdanm | 86:04dd9b1680ae | 5293 | |
bogdanm | 86:04dd9b1680ae | 5294 | /******************************************************************************/ |
bogdanm | 86:04dd9b1680ae | 5295 | /* */ |
bogdanm | 86:04dd9b1680ae | 5296 | /* Power Control */ |
bogdanm | 86:04dd9b1680ae | 5297 | /* */ |
bogdanm | 86:04dd9b1680ae | 5298 | /******************************************************************************/ |
bogdanm | 86:04dd9b1680ae | 5299 | /******************** Bit definition for PWR_CR register ********************/ |
bogdanm | 86:04dd9b1680ae | 5300 | #define PWR_CR_LPDS ((uint32_t)0x00000001) /*!< Low-power Deepsleep */ |
bogdanm | 86:04dd9b1680ae | 5301 | #define PWR_CR_PDDS ((uint32_t)0x00000002) /*!< Power Down Deepsleep */ |
bogdanm | 86:04dd9b1680ae | 5302 | #define PWR_CR_CWUF ((uint32_t)0x00000004) /*!< Clear Wakeup Flag */ |
bogdanm | 86:04dd9b1680ae | 5303 | #define PWR_CR_CSBF ((uint32_t)0x00000008) /*!< Clear Standby Flag */ |
bogdanm | 86:04dd9b1680ae | 5304 | #define PWR_CR_PVDE ((uint32_t)0x00000010) /*!< Power Voltage Detector Enable */ |
bogdanm | 86:04dd9b1680ae | 5305 | |
bogdanm | 86:04dd9b1680ae | 5306 | #define PWR_CR_PLS ((uint32_t)0x000000E0) /*!< PLS[2:0] bits (PVD Level Selection) */ |
bogdanm | 86:04dd9b1680ae | 5307 | #define PWR_CR_PLS_0 ((uint32_t)0x00000020) /*!< Bit 0 */ |
bogdanm | 86:04dd9b1680ae | 5308 | #define PWR_CR_PLS_1 ((uint32_t)0x00000040) /*!< Bit 1 */ |
bogdanm | 86:04dd9b1680ae | 5309 | #define PWR_CR_PLS_2 ((uint32_t)0x00000080) /*!< Bit 2 */ |
bogdanm | 86:04dd9b1680ae | 5310 | |
bogdanm | 86:04dd9b1680ae | 5311 | /*!< PVD level configuration */ |
bogdanm | 86:04dd9b1680ae | 5312 | #define PWR_CR_PLS_LEV0 ((uint32_t)0x00000000) /*!< PVD level 0 */ |
bogdanm | 86:04dd9b1680ae | 5313 | #define PWR_CR_PLS_LEV1 ((uint32_t)0x00000020) /*!< PVD level 1 */ |
bogdanm | 86:04dd9b1680ae | 5314 | #define PWR_CR_PLS_LEV2 ((uint32_t)0x00000040) /*!< PVD level 2 */ |
bogdanm | 86:04dd9b1680ae | 5315 | #define PWR_CR_PLS_LEV3 ((uint32_t)0x00000060) /*!< PVD level 3 */ |
bogdanm | 86:04dd9b1680ae | 5316 | #define PWR_CR_PLS_LEV4 ((uint32_t)0x00000080) /*!< PVD level 4 */ |
bogdanm | 86:04dd9b1680ae | 5317 | #define PWR_CR_PLS_LEV5 ((uint32_t)0x000000A0) /*!< PVD level 5 */ |
bogdanm | 86:04dd9b1680ae | 5318 | #define PWR_CR_PLS_LEV6 ((uint32_t)0x000000C0) /*!< PVD level 6 */ |
bogdanm | 86:04dd9b1680ae | 5319 | #define PWR_CR_PLS_LEV7 ((uint32_t)0x000000E0) /*!< PVD level 7 */ |
bogdanm | 86:04dd9b1680ae | 5320 | |
bogdanm | 86:04dd9b1680ae | 5321 | #define PWR_CR_DBP ((uint32_t)0x00000100) /*!< Disable Backup Domain write protection */ |
bogdanm | 86:04dd9b1680ae | 5322 | |
bogdanm | 86:04dd9b1680ae | 5323 | /******************* Bit definition for PWR_CSR register ********************/ |
bogdanm | 86:04dd9b1680ae | 5324 | #define PWR_CSR_WUF ((uint32_t)0x00000001) /*!< Wakeup Flag */ |
bogdanm | 86:04dd9b1680ae | 5325 | #define PWR_CSR_SBF ((uint32_t)0x00000002) /*!< Standby Flag */ |
bogdanm | 86:04dd9b1680ae | 5326 | #define PWR_CSR_PVDO ((uint32_t)0x00000004) /*!< PVD Output */ |
bogdanm | 86:04dd9b1680ae | 5327 | |
bogdanm | 86:04dd9b1680ae | 5328 | #define PWR_CSR_EWUP1 ((uint32_t)0x00000100) /*!< Enable WKUP pin 1 */ |
bogdanm | 86:04dd9b1680ae | 5329 | #define PWR_CSR_EWUP2 ((uint32_t)0x00000200) /*!< Enable WKUP pin 2 */ |
bogdanm | 86:04dd9b1680ae | 5330 | #define PWR_CSR_EWUP3 ((uint32_t)0x00000400) /*!< Enable WKUP pin 3 */ |
bogdanm | 86:04dd9b1680ae | 5331 | |
bogdanm | 86:04dd9b1680ae | 5332 | /******************************************************************************/ |
bogdanm | 86:04dd9b1680ae | 5333 | /* */ |
bogdanm | 86:04dd9b1680ae | 5334 | /* Reset and Clock Control */ |
bogdanm | 86:04dd9b1680ae | 5335 | /* */ |
bogdanm | 86:04dd9b1680ae | 5336 | /******************************************************************************/ |
bogdanm | 86:04dd9b1680ae | 5337 | /******************** Bit definition for RCC_CR register ********************/ |
bogdanm | 86:04dd9b1680ae | 5338 | #define RCC_CR_HSION ((uint32_t)0x00000001) |
bogdanm | 86:04dd9b1680ae | 5339 | #define RCC_CR_HSIRDY ((uint32_t)0x00000002) |
bogdanm | 86:04dd9b1680ae | 5340 | |
bogdanm | 86:04dd9b1680ae | 5341 | #define RCC_CR_HSITRIM ((uint32_t)0x000000F8) |
bogdanm | 86:04dd9b1680ae | 5342 | #define RCC_CR_HSITRIM_0 ((uint32_t)0x00000008)/*!<Bit 0 */ |
bogdanm | 86:04dd9b1680ae | 5343 | #define RCC_CR_HSITRIM_1 ((uint32_t)0x00000010)/*!<Bit 1 */ |
bogdanm | 86:04dd9b1680ae | 5344 | #define RCC_CR_HSITRIM_2 ((uint32_t)0x00000020)/*!<Bit 2 */ |
bogdanm | 86:04dd9b1680ae | 5345 | #define RCC_CR_HSITRIM_3 ((uint32_t)0x00000040)/*!<Bit 3 */ |
bogdanm | 86:04dd9b1680ae | 5346 | #define RCC_CR_HSITRIM_4 ((uint32_t)0x00000080)/*!<Bit 4 */ |
bogdanm | 86:04dd9b1680ae | 5347 | |
bogdanm | 86:04dd9b1680ae | 5348 | #define RCC_CR_HSICAL ((uint32_t)0x0000FF00) |
bogdanm | 86:04dd9b1680ae | 5349 | #define RCC_CR_HSICAL_0 ((uint32_t)0x00000100)/*!<Bit 0 */ |
bogdanm | 86:04dd9b1680ae | 5350 | #define RCC_CR_HSICAL_1 ((uint32_t)0x00000200)/*!<Bit 1 */ |
bogdanm | 86:04dd9b1680ae | 5351 | #define RCC_CR_HSICAL_2 ((uint32_t)0x00000400)/*!<Bit 2 */ |
bogdanm | 86:04dd9b1680ae | 5352 | #define RCC_CR_HSICAL_3 ((uint32_t)0x00000800)/*!<Bit 3 */ |
bogdanm | 86:04dd9b1680ae | 5353 | #define RCC_CR_HSICAL_4 ((uint32_t)0x00001000)/*!<Bit 4 */ |
bogdanm | 86:04dd9b1680ae | 5354 | #define RCC_CR_HSICAL_5 ((uint32_t)0x00002000)/*!<Bit 5 */ |
bogdanm | 86:04dd9b1680ae | 5355 | #define RCC_CR_HSICAL_6 ((uint32_t)0x00004000)/*!<Bit 6 */ |
bogdanm | 86:04dd9b1680ae | 5356 | #define RCC_CR_HSICAL_7 ((uint32_t)0x00008000)/*!<Bit 7 */ |
bogdanm | 86:04dd9b1680ae | 5357 | |
bogdanm | 86:04dd9b1680ae | 5358 | #define RCC_CR_HSEON ((uint32_t)0x00010000) |
bogdanm | 86:04dd9b1680ae | 5359 | #define RCC_CR_HSERDY ((uint32_t)0x00020000) |
bogdanm | 86:04dd9b1680ae | 5360 | #define RCC_CR_HSEBYP ((uint32_t)0x00040000) |
bogdanm | 86:04dd9b1680ae | 5361 | #define RCC_CR_CSSON ((uint32_t)0x00080000) |
bogdanm | 86:04dd9b1680ae | 5362 | #define RCC_CR_PLLON ((uint32_t)0x01000000) |
bogdanm | 86:04dd9b1680ae | 5363 | #define RCC_CR_PLLRDY ((uint32_t)0x02000000) |
bogdanm | 86:04dd9b1680ae | 5364 | |
bogdanm | 86:04dd9b1680ae | 5365 | /******************** Bit definition for RCC_CFGR register ******************/ |
bogdanm | 86:04dd9b1680ae | 5366 | /*!< SW configuration */ |
bogdanm | 86:04dd9b1680ae | 5367 | #define RCC_CFGR_SW ((uint32_t)0x00000003) /*!< SW[1:0] bits (System clock Switch) */ |
bogdanm | 86:04dd9b1680ae | 5368 | #define RCC_CFGR_SW_0 ((uint32_t)0x00000001) /*!< Bit 0 */ |
bogdanm | 86:04dd9b1680ae | 5369 | #define RCC_CFGR_SW_1 ((uint32_t)0x00000002) /*!< Bit 1 */ |
bogdanm | 86:04dd9b1680ae | 5370 | |
bogdanm | 86:04dd9b1680ae | 5371 | #define RCC_CFGR_SW_HSI ((uint32_t)0x00000000) /*!< HSI selected as system clock */ |
bogdanm | 86:04dd9b1680ae | 5372 | #define RCC_CFGR_SW_HSE ((uint32_t)0x00000001) /*!< HSE selected as system clock */ |
bogdanm | 86:04dd9b1680ae | 5373 | #define RCC_CFGR_SW_PLL ((uint32_t)0x00000002) /*!< PLL selected as system clock */ |
bogdanm | 86:04dd9b1680ae | 5374 | |
bogdanm | 86:04dd9b1680ae | 5375 | /*!< SWS configuration */ |
bogdanm | 86:04dd9b1680ae | 5376 | #define RCC_CFGR_SWS ((uint32_t)0x0000000C) /*!< SWS[1:0] bits (System Clock Switch Status) */ |
bogdanm | 86:04dd9b1680ae | 5377 | #define RCC_CFGR_SWS_0 ((uint32_t)0x00000004) /*!< Bit 0 */ |
bogdanm | 86:04dd9b1680ae | 5378 | #define RCC_CFGR_SWS_1 ((uint32_t)0x00000008) /*!< Bit 1 */ |
bogdanm | 86:04dd9b1680ae | 5379 | |
bogdanm | 86:04dd9b1680ae | 5380 | #define RCC_CFGR_SWS_HSI ((uint32_t)0x00000000) /*!< HSI oscillator used as system clock */ |
bogdanm | 86:04dd9b1680ae | 5381 | #define RCC_CFGR_SWS_HSE ((uint32_t)0x00000004) /*!< HSE oscillator used as system clock */ |
bogdanm | 86:04dd9b1680ae | 5382 | #define RCC_CFGR_SWS_PLL ((uint32_t)0x00000008) /*!< PLL used as system clock */ |
bogdanm | 86:04dd9b1680ae | 5383 | |
bogdanm | 86:04dd9b1680ae | 5384 | /*!< HPRE configuration */ |
bogdanm | 86:04dd9b1680ae | 5385 | #define RCC_CFGR_HPRE ((uint32_t)0x000000F0) /*!< HPRE[3:0] bits (AHB prescaler) */ |
bogdanm | 86:04dd9b1680ae | 5386 | #define RCC_CFGR_HPRE_0 ((uint32_t)0x00000010) /*!< Bit 0 */ |
bogdanm | 86:04dd9b1680ae | 5387 | #define RCC_CFGR_HPRE_1 ((uint32_t)0x00000020) /*!< Bit 1 */ |
bogdanm | 86:04dd9b1680ae | 5388 | #define RCC_CFGR_HPRE_2 ((uint32_t)0x00000040) /*!< Bit 2 */ |
bogdanm | 86:04dd9b1680ae | 5389 | #define RCC_CFGR_HPRE_3 ((uint32_t)0x00000080) /*!< Bit 3 */ |
bogdanm | 86:04dd9b1680ae | 5390 | |
bogdanm | 86:04dd9b1680ae | 5391 | #define RCC_CFGR_HPRE_DIV1 ((uint32_t)0x00000000) /*!< SYSCLK not divided */ |
bogdanm | 86:04dd9b1680ae | 5392 | #define RCC_CFGR_HPRE_DIV2 ((uint32_t)0x00000080) /*!< SYSCLK divided by 2 */ |
bogdanm | 86:04dd9b1680ae | 5393 | #define RCC_CFGR_HPRE_DIV4 ((uint32_t)0x00000090) /*!< SYSCLK divided by 4 */ |
bogdanm | 86:04dd9b1680ae | 5394 | #define RCC_CFGR_HPRE_DIV8 ((uint32_t)0x000000A0) /*!< SYSCLK divided by 8 */ |
bogdanm | 86:04dd9b1680ae | 5395 | #define RCC_CFGR_HPRE_DIV16 ((uint32_t)0x000000B0) /*!< SYSCLK divided by 16 */ |
bogdanm | 86:04dd9b1680ae | 5396 | #define RCC_CFGR_HPRE_DIV64 ((uint32_t)0x000000C0) /*!< SYSCLK divided by 64 */ |
bogdanm | 86:04dd9b1680ae | 5397 | #define RCC_CFGR_HPRE_DIV128 ((uint32_t)0x000000D0) /*!< SYSCLK divided by 128 */ |
bogdanm | 86:04dd9b1680ae | 5398 | #define RCC_CFGR_HPRE_DIV256 ((uint32_t)0x000000E0) /*!< SYSCLK divided by 256 */ |
bogdanm | 86:04dd9b1680ae | 5399 | #define RCC_CFGR_HPRE_DIV512 ((uint32_t)0x000000F0) /*!< SYSCLK divided by 512 */ |
bogdanm | 86:04dd9b1680ae | 5400 | |
bogdanm | 86:04dd9b1680ae | 5401 | /*!< PPRE1 configuration */ |
bogdanm | 86:04dd9b1680ae | 5402 | #define RCC_CFGR_PPRE1 ((uint32_t)0x00000700) /*!< PRE1[2:0] bits (APB1 prescaler) */ |
bogdanm | 86:04dd9b1680ae | 5403 | #define RCC_CFGR_PPRE1_0 ((uint32_t)0x00000100) /*!< Bit 0 */ |
bogdanm | 86:04dd9b1680ae | 5404 | #define RCC_CFGR_PPRE1_1 ((uint32_t)0x00000200) /*!< Bit 1 */ |
bogdanm | 86:04dd9b1680ae | 5405 | #define RCC_CFGR_PPRE1_2 ((uint32_t)0x00000400) /*!< Bit 2 */ |
bogdanm | 86:04dd9b1680ae | 5406 | |
bogdanm | 86:04dd9b1680ae | 5407 | #define RCC_CFGR_PPRE1_DIV1 ((uint32_t)0x00000000) /*!< HCLK not divided */ |
bogdanm | 86:04dd9b1680ae | 5408 | #define RCC_CFGR_PPRE1_DIV2 ((uint32_t)0x00000400) /*!< HCLK divided by 2 */ |
bogdanm | 86:04dd9b1680ae | 5409 | #define RCC_CFGR_PPRE1_DIV4 ((uint32_t)0x00000500) /*!< HCLK divided by 4 */ |
bogdanm | 86:04dd9b1680ae | 5410 | #define RCC_CFGR_PPRE1_DIV8 ((uint32_t)0x00000600) /*!< HCLK divided by 8 */ |
bogdanm | 86:04dd9b1680ae | 5411 | #define RCC_CFGR_PPRE1_DIV16 ((uint32_t)0x00000700) /*!< HCLK divided by 16 */ |
bogdanm | 86:04dd9b1680ae | 5412 | |
bogdanm | 86:04dd9b1680ae | 5413 | /*!< PPRE2 configuration */ |
bogdanm | 86:04dd9b1680ae | 5414 | #define RCC_CFGR_PPRE2 ((uint32_t)0x00003800) /*!< PRE2[2:0] bits (APB2 prescaler) */ |
bogdanm | 86:04dd9b1680ae | 5415 | #define RCC_CFGR_PPRE2_0 ((uint32_t)0x00000800) /*!< Bit 0 */ |
bogdanm | 86:04dd9b1680ae | 5416 | #define RCC_CFGR_PPRE2_1 ((uint32_t)0x00001000) /*!< Bit 1 */ |
bogdanm | 86:04dd9b1680ae | 5417 | #define RCC_CFGR_PPRE2_2 ((uint32_t)0x00002000) /*!< Bit 2 */ |
bogdanm | 86:04dd9b1680ae | 5418 | |
bogdanm | 86:04dd9b1680ae | 5419 | #define RCC_CFGR_PPRE2_DIV1 ((uint32_t)0x00000000) /*!< HCLK not divided */ |
bogdanm | 86:04dd9b1680ae | 5420 | #define RCC_CFGR_PPRE2_DIV2 ((uint32_t)0x00002000) /*!< HCLK divided by 2 */ |
bogdanm | 86:04dd9b1680ae | 5421 | #define RCC_CFGR_PPRE2_DIV4 ((uint32_t)0x00002800) /*!< HCLK divided by 4 */ |
bogdanm | 86:04dd9b1680ae | 5422 | #define RCC_CFGR_PPRE2_DIV8 ((uint32_t)0x00003000) /*!< HCLK divided by 8 */ |
bogdanm | 86:04dd9b1680ae | 5423 | #define RCC_CFGR_PPRE2_DIV16 ((uint32_t)0x00003800) /*!< HCLK divided by 16 */ |
bogdanm | 86:04dd9b1680ae | 5424 | |
bogdanm | 86:04dd9b1680ae | 5425 | #define RCC_CFGR_PLLSRC ((uint32_t)0x00010000) /*!< PLL entry clock source */ |
bogdanm | 86:04dd9b1680ae | 5426 | #define RCC_CFGR_PLLSRC_HSI_DIV2 ((uint32_t)0x00000000) /*!< HSI clock divided by 2 selected as PLL entry clock source */ |
bogdanm | 86:04dd9b1680ae | 5427 | #define RCC_CFGR_PLLSRC_HSE_PREDIV ((uint32_t)0x00010000) /*!< HSE/PREDIV clock selected as PLL entry clock source */ |
bogdanm | 86:04dd9b1680ae | 5428 | |
bogdanm | 86:04dd9b1680ae | 5429 | #define RCC_CFGR_PLLXTPRE ((uint32_t)0x00020000) /*!< HSE divider for PLL entry */ |
bogdanm | 86:04dd9b1680ae | 5430 | #define RCC_CFGR_PLLXTPRE_HSE_PREDIV_DIV1 ((uint32_t)0x00000000) /*!< HSE/PREDIV clock not divided for PLL entry */ |
bogdanm | 86:04dd9b1680ae | 5431 | #define RCC_CFGR_PLLXTPRE_HSE_PREDIV_DIV2 ((uint32_t)0x00020000) /*!< HSE/PREDIV clock divided by 2 for PLL entry */ |
bogdanm | 86:04dd9b1680ae | 5432 | |
bogdanm | 86:04dd9b1680ae | 5433 | /*!< PLLMUL configuration */ |
bogdanm | 86:04dd9b1680ae | 5434 | #define RCC_CFGR_PLLMUL ((uint32_t)0x003C0000) /*!< PLLMUL[3:0] bits (PLL multiplication factor) */ |
bogdanm | 86:04dd9b1680ae | 5435 | #define RCC_CFGR_PLLMUL_0 ((uint32_t)0x00040000) /*!< Bit 0 */ |
bogdanm | 86:04dd9b1680ae | 5436 | #define RCC_CFGR_PLLMUL_1 ((uint32_t)0x00080000) /*!< Bit 1 */ |
bogdanm | 86:04dd9b1680ae | 5437 | #define RCC_CFGR_PLLMUL_2 ((uint32_t)0x00100000) /*!< Bit 2 */ |
bogdanm | 86:04dd9b1680ae | 5438 | #define RCC_CFGR_PLLMUL_3 ((uint32_t)0x00200000) /*!< Bit 3 */ |
bogdanm | 86:04dd9b1680ae | 5439 | |
bogdanm | 86:04dd9b1680ae | 5440 | #define RCC_CFGR_PLLMUL2 ((uint32_t)0x00000000) /*!< PLL input clock*2 */ |
bogdanm | 86:04dd9b1680ae | 5441 | #define RCC_CFGR_PLLMUL3 ((uint32_t)0x00040000) /*!< PLL input clock*3 */ |
bogdanm | 86:04dd9b1680ae | 5442 | #define RCC_CFGR_PLLMUL4 ((uint32_t)0x00080000) /*!< PLL input clock*4 */ |
bogdanm | 86:04dd9b1680ae | 5443 | #define RCC_CFGR_PLLMUL5 ((uint32_t)0x000C0000) /*!< PLL input clock*5 */ |
bogdanm | 86:04dd9b1680ae | 5444 | #define RCC_CFGR_PLLMUL6 ((uint32_t)0x00100000) /*!< PLL input clock*6 */ |
bogdanm | 86:04dd9b1680ae | 5445 | #define RCC_CFGR_PLLMUL7 ((uint32_t)0x00140000) /*!< PLL input clock*7 */ |
bogdanm | 86:04dd9b1680ae | 5446 | #define RCC_CFGR_PLLMUL8 ((uint32_t)0x00180000) /*!< PLL input clock*8 */ |
bogdanm | 86:04dd9b1680ae | 5447 | #define RCC_CFGR_PLLMUL9 ((uint32_t)0x001C0000) /*!< PLL input clock*9 */ |
bogdanm | 86:04dd9b1680ae | 5448 | #define RCC_CFGR_PLLMUL10 ((uint32_t)0x00200000) /*!< PLL input clock10 */ |
bogdanm | 86:04dd9b1680ae | 5449 | #define RCC_CFGR_PLLMUL11 ((uint32_t)0x00240000) /*!< PLL input clock*11 */ |
bogdanm | 86:04dd9b1680ae | 5450 | #define RCC_CFGR_PLLMUL12 ((uint32_t)0x00280000) /*!< PLL input clock*12 */ |
bogdanm | 86:04dd9b1680ae | 5451 | #define RCC_CFGR_PLLMUL13 ((uint32_t)0x002C0000) /*!< PLL input clock*13 */ |
bogdanm | 86:04dd9b1680ae | 5452 | #define RCC_CFGR_PLLMUL14 ((uint32_t)0x00300000) /*!< PLL input clock*14 */ |
bogdanm | 86:04dd9b1680ae | 5453 | #define RCC_CFGR_PLLMUL15 ((uint32_t)0x00340000) /*!< PLL input clock*15 */ |
bogdanm | 86:04dd9b1680ae | 5454 | #define RCC_CFGR_PLLMUL16 ((uint32_t)0x00380000) /*!< PLL input clock*16 */ |
bogdanm | 86:04dd9b1680ae | 5455 | |
bogdanm | 86:04dd9b1680ae | 5456 | /*!< MCO configuration */ |
bogdanm | 86:04dd9b1680ae | 5457 | #define RCC_CFGR_MCO ((uint32_t)0x07000000) /*!< MCO[2:0] bits (Microcontroller Clock Output) */ |
bogdanm | 86:04dd9b1680ae | 5458 | #define RCC_CFGR_MCO_0 ((uint32_t)0x01000000) /*!< Bit 0 */ |
bogdanm | 86:04dd9b1680ae | 5459 | #define RCC_CFGR_MCO_1 ((uint32_t)0x02000000) /*!< Bit 1 */ |
bogdanm | 86:04dd9b1680ae | 5460 | #define RCC_CFGR_MCO_2 ((uint32_t)0x04000000) /*!< Bit 2 */ |
bogdanm | 86:04dd9b1680ae | 5461 | |
bogdanm | 86:04dd9b1680ae | 5462 | #define RCC_CFGR_MCO_NOCLOCK ((uint32_t)0x00000000) /*!< No clock */ |
bogdanm | 86:04dd9b1680ae | 5463 | #define RCC_CFGR_MCO_LSI ((uint32_t)0x02000000) /*!< LSI clock selected as MCO source */ |
bogdanm | 86:04dd9b1680ae | 5464 | #define RCC_CFGR_MCO_LSE ((uint32_t)0x03000000) /*!< LSE clock selected as MCO source */ |
bogdanm | 86:04dd9b1680ae | 5465 | #define RCC_CFGR_MCO_SYSCLK ((uint32_t)0x04000000) /*!< System clock selected as MCO source */ |
bogdanm | 86:04dd9b1680ae | 5466 | #define RCC_CFGR_MCO_HSI ((uint32_t)0x05000000) /*!< HSI clock selected as MCO source */ |
bogdanm | 86:04dd9b1680ae | 5467 | #define RCC_CFGR_MCO_HSE ((uint32_t)0x06000000) /*!< HSE clock selected as MCO source */ |
bogdanm | 86:04dd9b1680ae | 5468 | #define RCC_CFGR_MCO_PLL ((uint32_t)0x07000000) /*!< PLL clock divided by 2 selected as MCO source */ |
bogdanm | 86:04dd9b1680ae | 5469 | |
bogdanm | 86:04dd9b1680ae | 5470 | #define RCC_CFGR_MCOPRE ((uint32_t)0x70000000) /*!< MCO prescaler */ |
bogdanm | 86:04dd9b1680ae | 5471 | #define RCC_CFGR_MCOPRE_DIV1 ((uint32_t)0x00000000) /*!< MCO is divided by 1 */ |
bogdanm | 86:04dd9b1680ae | 5472 | #define RCC_CFGR_MCOPRE_DIV2 ((uint32_t)0x10000000) /*!< MCO is divided by 2 */ |
bogdanm | 86:04dd9b1680ae | 5473 | #define RCC_CFGR_MCOPRE_DIV4 ((uint32_t)0x20000000) /*!< MCO is divided by 4 */ |
bogdanm | 86:04dd9b1680ae | 5474 | #define RCC_CFGR_MCOPRE_DIV8 ((uint32_t)0x30000000) /*!< MCO is divided by 8 */ |
bogdanm | 86:04dd9b1680ae | 5475 | #define RCC_CFGR_MCOPRE_DIV16 ((uint32_t)0x40000000) /*!< MCO is divided by 16 */ |
bogdanm | 86:04dd9b1680ae | 5476 | #define RCC_CFGR_MCOPRE_DIV32 ((uint32_t)0x50000000) /*!< MCO is divided by 32 */ |
bogdanm | 86:04dd9b1680ae | 5477 | #define RCC_CFGR_MCOPRE_DIV64 ((uint32_t)0x60000000) /*!< MCO is divided by 64 */ |
bogdanm | 86:04dd9b1680ae | 5478 | #define RCC_CFGR_MCOPRE_DIV128 ((uint32_t)0x70000000) /*!< MCO is divided by 128 */ |
bogdanm | 86:04dd9b1680ae | 5479 | |
bogdanm | 86:04dd9b1680ae | 5480 | #define RCC_CFGR_PLLNODIV ((uint32_t)0x80000000) /*!< PLL is not divided to MCO */ |
bogdanm | 86:04dd9b1680ae | 5481 | |
bogdanm | 86:04dd9b1680ae | 5482 | /********************* Bit definition for RCC_CIR register ********************/ |
bogdanm | 86:04dd9b1680ae | 5483 | #define RCC_CIR_LSIRDYF ((uint32_t)0x00000001) /*!< LSI Ready Interrupt flag */ |
bogdanm | 86:04dd9b1680ae | 5484 | #define RCC_CIR_LSERDYF ((uint32_t)0x00000002) /*!< LSE Ready Interrupt flag */ |
bogdanm | 86:04dd9b1680ae | 5485 | #define RCC_CIR_HSIRDYF ((uint32_t)0x00000004) /*!< HSI Ready Interrupt flag */ |
bogdanm | 86:04dd9b1680ae | 5486 | #define RCC_CIR_HSERDYF ((uint32_t)0x00000008) /*!< HSE Ready Interrupt flag */ |
bogdanm | 86:04dd9b1680ae | 5487 | #define RCC_CIR_PLLRDYF ((uint32_t)0x00000010) /*!< PLL Ready Interrupt flag */ |
bogdanm | 86:04dd9b1680ae | 5488 | #define RCC_CIR_CSSF ((uint32_t)0x00000080) /*!< Clock Security System Interrupt flag */ |
bogdanm | 86:04dd9b1680ae | 5489 | #define RCC_CIR_LSIRDYIE ((uint32_t)0x00000100) /*!< LSI Ready Interrupt Enable */ |
bogdanm | 86:04dd9b1680ae | 5490 | #define RCC_CIR_LSERDYIE ((uint32_t)0x00000200) /*!< LSE Ready Interrupt Enable */ |
bogdanm | 86:04dd9b1680ae | 5491 | #define RCC_CIR_HSIRDYIE ((uint32_t)0x00000400) /*!< HSI Ready Interrupt Enable */ |
bogdanm | 86:04dd9b1680ae | 5492 | #define RCC_CIR_HSERDYIE ((uint32_t)0x00000800) /*!< HSE Ready Interrupt Enable */ |
bogdanm | 86:04dd9b1680ae | 5493 | #define RCC_CIR_PLLRDYIE ((uint32_t)0x00001000) /*!< PLL Ready Interrupt Enable */ |
bogdanm | 86:04dd9b1680ae | 5494 | #define RCC_CIR_LSIRDYC ((uint32_t)0x00010000) /*!< LSI Ready Interrupt Clear */ |
bogdanm | 86:04dd9b1680ae | 5495 | #define RCC_CIR_LSERDYC ((uint32_t)0x00020000) /*!< LSE Ready Interrupt Clear */ |
bogdanm | 86:04dd9b1680ae | 5496 | #define RCC_CIR_HSIRDYC ((uint32_t)0x00040000) /*!< HSI Ready Interrupt Clear */ |
bogdanm | 86:04dd9b1680ae | 5497 | #define RCC_CIR_HSERDYC ((uint32_t)0x00080000) /*!< HSE Ready Interrupt Clear */ |
bogdanm | 86:04dd9b1680ae | 5498 | #define RCC_CIR_PLLRDYC ((uint32_t)0x00100000) /*!< PLL Ready Interrupt Clear */ |
bogdanm | 86:04dd9b1680ae | 5499 | #define RCC_CIR_CSSC ((uint32_t)0x00800000) /*!< Clock Security System Interrupt Clear */ |
bogdanm | 86:04dd9b1680ae | 5500 | |
bogdanm | 86:04dd9b1680ae | 5501 | /****************** Bit definition for RCC_APB2RSTR register *****************/ |
bogdanm | 86:04dd9b1680ae | 5502 | #define RCC_APB2RSTR_SYSCFGRST ((uint32_t)0x00000001) /*!< SYSCFG reset */ |
bogdanm | 86:04dd9b1680ae | 5503 | #define RCC_APB2RSTR_TIM1RST ((uint32_t)0x00000800) /*!< TIM1 reset */ |
bogdanm | 86:04dd9b1680ae | 5504 | #define RCC_APB2RSTR_SPI1RST ((uint32_t)0x00001000) /*!< SPI1 reset */ |
bogdanm | 86:04dd9b1680ae | 5505 | #define RCC_APB2RSTR_USART1RST ((uint32_t)0x00004000) /*!< USART1 reset */ |
bogdanm | 86:04dd9b1680ae | 5506 | #define RCC_APB2RSTR_TIM15RST ((uint32_t)0x00010000) /*!< TIM15 reset */ |
bogdanm | 86:04dd9b1680ae | 5507 | #define RCC_APB2RSTR_TIM16RST ((uint32_t)0x00020000) /*!< TIM16 reset */ |
bogdanm | 86:04dd9b1680ae | 5508 | #define RCC_APB2RSTR_TIM17RST ((uint32_t)0x00040000) /*!< TIM17 reset */ |
bogdanm | 86:04dd9b1680ae | 5509 | #define RCC_APB2RSTR_HRTIM1RST ((uint32_t)0x20000000) /*!< TIM17 reset */ |
bogdanm | 86:04dd9b1680ae | 5510 | |
bogdanm | 86:04dd9b1680ae | 5511 | /****************** Bit definition for RCC_APB1RSTR register ******************/ |
bogdanm | 86:04dd9b1680ae | 5512 | #define RCC_APB1RSTR_TIM2RST ((uint32_t)0x00000001) /*!< Timer 2 reset */ |
bogdanm | 86:04dd9b1680ae | 5513 | #define RCC_APB1RSTR_TIM3RST ((uint32_t)0x00000002) /*!< Timer 3 reset */ |
bogdanm | 86:04dd9b1680ae | 5514 | #define RCC_APB1RSTR_TIM6RST ((uint32_t)0x00000010) /*!< Timer 6 reset */ |
bogdanm | 86:04dd9b1680ae | 5515 | #define RCC_APB1RSTR_TIM7RST ((uint32_t)0x00000020) /*!< Timer 7 reset */ |
bogdanm | 86:04dd9b1680ae | 5516 | #define RCC_APB1RSTR_WWDGRST ((uint32_t)0x00000800) /*!< Window Watchdog reset */ |
bogdanm | 86:04dd9b1680ae | 5517 | #define RCC_APB1RSTR_USART2RST ((uint32_t)0x00020000) /*!< USART 2 reset */ |
bogdanm | 86:04dd9b1680ae | 5518 | #define RCC_APB1RSTR_USART3RST ((uint32_t)0x00040000) /*!< USART 3 reset */ |
bogdanm | 86:04dd9b1680ae | 5519 | #define RCC_APB1RSTR_I2C1RST ((uint32_t)0x00200000) /*!< I2C 1 reset */ |
bogdanm | 86:04dd9b1680ae | 5520 | #define RCC_APB1RSTR_CANRST ((uint32_t)0x02000000) /*!< CAN reset */ |
bogdanm | 86:04dd9b1680ae | 5521 | #define RCC_APB1RSTR_DAC2RST ((uint32_t)0x04000000) /*!< DAC 2 reset */ |
bogdanm | 86:04dd9b1680ae | 5522 | #define RCC_APB1RSTR_PWRRST ((uint32_t)0x10000000) /*!< PWR reset */ |
bogdanm | 86:04dd9b1680ae | 5523 | #define RCC_APB1RSTR_DAC1RST ((uint32_t)0x20000000) /*!< DAC 1 reset */ |
bogdanm | 86:04dd9b1680ae | 5524 | |
bogdanm | 86:04dd9b1680ae | 5525 | /****************** Bit definition for RCC_AHBENR register ******************/ |
bogdanm | 86:04dd9b1680ae | 5526 | #define RCC_AHBENR_DMA1EN ((uint32_t)0x00000001) /*!< DMA1 clock enable */ |
bogdanm | 86:04dd9b1680ae | 5527 | #define RCC_AHBENR_SRAMEN ((uint32_t)0x00000004) /*!< SRAM interface clock enable */ |
bogdanm | 86:04dd9b1680ae | 5528 | #define RCC_AHBENR_FLITFEN ((uint32_t)0x00000010) /*!< FLITF clock enable */ |
bogdanm | 86:04dd9b1680ae | 5529 | #define RCC_AHBENR_CRCEN ((uint32_t)0x00000040) /*!< CRC clock enable */ |
bogdanm | 86:04dd9b1680ae | 5530 | #define RCC_AHBENR_GPIOAEN ((uint32_t)0x00020000) /*!< GPIOA clock enable */ |
bogdanm | 86:04dd9b1680ae | 5531 | #define RCC_AHBENR_GPIOBEN ((uint32_t)0x00040000) /*!< GPIOB clock enable */ |
bogdanm | 86:04dd9b1680ae | 5532 | #define RCC_AHBENR_GPIOCEN ((uint32_t)0x00080000) /*!< GPIOC clock enable */ |
bogdanm | 86:04dd9b1680ae | 5533 | #define RCC_AHBENR_GPIODEN ((uint32_t)0x00100000) /*!< GPIOD clock enable */ |
bogdanm | 86:04dd9b1680ae | 5534 | #define RCC_AHBENR_GPIOFEN ((uint32_t)0x00400000) /*!< GPIOF clock enable */ |
bogdanm | 86:04dd9b1680ae | 5535 | #define RCC_AHBENR_TSCEN ((uint32_t)0x01000000) /*!< TS clock enable */ |
bogdanm | 86:04dd9b1680ae | 5536 | #define RCC_AHBENR_ADC12EN ((uint32_t)0x10000000) /*!< ADC1/ ADC2 clock enable */ |
bogdanm | 86:04dd9b1680ae | 5537 | |
bogdanm | 86:04dd9b1680ae | 5538 | /***************** Bit definition for RCC_APB2ENR register ******************/ |
bogdanm | 86:04dd9b1680ae | 5539 | #define RCC_APB2ENR_SYSCFGEN ((uint32_t)0x00000001) /*!< SYSCFG clock enable */ |
bogdanm | 86:04dd9b1680ae | 5540 | #define RCC_APB2ENR_TIM1EN ((uint32_t)0x00000800) /*!< TIM1 clock enable */ |
bogdanm | 86:04dd9b1680ae | 5541 | #define RCC_APB2ENR_SPI1EN ((uint32_t)0x00001000) /*!< SPI1 clock enable */ |
bogdanm | 86:04dd9b1680ae | 5542 | #define RCC_APB2ENR_USART1EN ((uint32_t)0x00004000) /*!< USART1 clock enable */ |
bogdanm | 86:04dd9b1680ae | 5543 | #define RCC_APB2ENR_TIM15EN ((uint32_t)0x00010000) /*!< TIM15 clock enable */ |
bogdanm | 86:04dd9b1680ae | 5544 | #define RCC_APB2ENR_TIM16EN ((uint32_t)0x00020000) /*!< TIM16 clock enable */ |
bogdanm | 86:04dd9b1680ae | 5545 | #define RCC_APB2ENR_TIM17EN ((uint32_t)0x00040000) /*!< TIM17 clock enable */ |
bogdanm | 86:04dd9b1680ae | 5546 | #define RCC_APB2ENR_HRTIM1EN ((uint32_t)0x20000000) /*!< TIM17 reset */ |
bogdanm | 86:04dd9b1680ae | 5547 | |
bogdanm | 86:04dd9b1680ae | 5548 | /****************** Bit definition for RCC_APB1ENR register ******************/ |
bogdanm | 86:04dd9b1680ae | 5549 | #define RCC_APB1ENR_TIM2EN ((uint32_t)0x00000001) /*!< Timer 2 clock enable */ |
bogdanm | 86:04dd9b1680ae | 5550 | #define RCC_APB1ENR_TIM3EN ((uint32_t)0x00000002) /*!< Timer 3 clock enable */ |
bogdanm | 86:04dd9b1680ae | 5551 | #define RCC_APB1ENR_TIM6EN ((uint32_t)0x00000010) /*!< Timer 6 clock enable */ |
bogdanm | 86:04dd9b1680ae | 5552 | #define RCC_APB1ENR_TIM7EN ((uint32_t)0x00000020) /*!< Timer 7 clock enable */ |
bogdanm | 86:04dd9b1680ae | 5553 | #define RCC_APB1ENR_WWDGEN ((uint32_t)0x00000800) /*!< Window Watchdog clock enable */ |
bogdanm | 86:04dd9b1680ae | 5554 | #define RCC_APB1ENR_USART2EN ((uint32_t)0x00020000) /*!< USART 2 clock enable */ |
bogdanm | 86:04dd9b1680ae | 5555 | #define RCC_APB1ENR_USART3EN ((uint32_t)0x00040000) /*!< USART 3 clock enable */ |
bogdanm | 86:04dd9b1680ae | 5556 | #define RCC_APB1ENR_I2C1EN ((uint32_t)0x00200000) /*!< I2C 1 clock enable */ |
bogdanm | 86:04dd9b1680ae | 5557 | #define RCC_APB1ENR_CANEN ((uint32_t)0x02000000) /*!< CAN clock enable */ |
bogdanm | 86:04dd9b1680ae | 5558 | #define RCC_APB1ENR_DAC2EN ((uint32_t)0x04000000) /*!< DAC 2 clock enable */ |
bogdanm | 86:04dd9b1680ae | 5559 | #define RCC_APB1ENR_PWREN ((uint32_t)0x10000000) /*!< PWR clock enable */ |
bogdanm | 86:04dd9b1680ae | 5560 | #define RCC_APB1ENR_DAC1EN ((uint32_t)0x20000000) /*!< DAC 1 clock enable */ |
bogdanm | 86:04dd9b1680ae | 5561 | |
bogdanm | 86:04dd9b1680ae | 5562 | /******************** Bit definition for RCC_BDCR register ******************/ |
bogdanm | 86:04dd9b1680ae | 5563 | #define RCC_BDCR_LSE ((uint32_t)0x00000007) /*!< External Low Speed oscillator [2:0] bits */ |
bogdanm | 86:04dd9b1680ae | 5564 | #define RCC_BDCR_LSEON ((uint32_t)0x00000001) /*!< External Low Speed oscillator enable */ |
bogdanm | 86:04dd9b1680ae | 5565 | #define RCC_BDCR_LSERDY ((uint32_t)0x00000002) /*!< External Low Speed oscillator Ready */ |
bogdanm | 86:04dd9b1680ae | 5566 | #define RCC_BDCR_LSEBYP ((uint32_t)0x00000004) /*!< External Low Speed oscillator Bypass */ |
bogdanm | 86:04dd9b1680ae | 5567 | |
bogdanm | 86:04dd9b1680ae | 5568 | #define RCC_BDCR_LSEDRV ((uint32_t)0x00000018) /*!< LSEDRV[1:0] bits (LSE Osc. drive capability) */ |
bogdanm | 86:04dd9b1680ae | 5569 | #define RCC_BDCR_LSEDRV_0 ((uint32_t)0x00000008) /*!< Bit 0 */ |
bogdanm | 86:04dd9b1680ae | 5570 | #define RCC_BDCR_LSEDRV_1 ((uint32_t)0x00000010) /*!< Bit 1 */ |
bogdanm | 86:04dd9b1680ae | 5571 | |
bogdanm | 86:04dd9b1680ae | 5572 | #define RCC_BDCR_RTCSEL ((uint32_t)0x00000300) /*!< RTCSEL[1:0] bits (RTC clock source selection) */ |
bogdanm | 86:04dd9b1680ae | 5573 | #define RCC_BDCR_RTCSEL_0 ((uint32_t)0x00000100) /*!< Bit 0 */ |
bogdanm | 86:04dd9b1680ae | 5574 | #define RCC_BDCR_RTCSEL_1 ((uint32_t)0x00000200) /*!< Bit 1 */ |
bogdanm | 86:04dd9b1680ae | 5575 | |
bogdanm | 86:04dd9b1680ae | 5576 | /*!< RTC configuration */ |
bogdanm | 86:04dd9b1680ae | 5577 | #define RCC_BDCR_RTCSEL_NOCLOCK ((uint32_t)0x00000000) /*!< No clock */ |
bogdanm | 86:04dd9b1680ae | 5578 | #define RCC_BDCR_RTCSEL_LSE ((uint32_t)0x00000100) /*!< LSE oscillator clock used as RTC clock */ |
bogdanm | 86:04dd9b1680ae | 5579 | #define RCC_BDCR_RTCSEL_LSI ((uint32_t)0x00000200) /*!< LSI oscillator clock used as RTC clock */ |
bogdanm | 86:04dd9b1680ae | 5580 | #define RCC_BDCR_RTCSEL_HSE ((uint32_t)0x00000300) /*!< HSE oscillator clock divided by 32 used as RTC clock */ |
bogdanm | 86:04dd9b1680ae | 5581 | |
bogdanm | 86:04dd9b1680ae | 5582 | #define RCC_BDCR_RTCEN ((uint32_t)0x00008000) /*!< RTC clock enable */ |
bogdanm | 86:04dd9b1680ae | 5583 | #define RCC_BDCR_BDRST ((uint32_t)0x00010000) /*!< Backup domain software reset */ |
bogdanm | 86:04dd9b1680ae | 5584 | |
bogdanm | 86:04dd9b1680ae | 5585 | /******************** Bit definition for RCC_CSR register *******************/ |
bogdanm | 86:04dd9b1680ae | 5586 | #define RCC_CSR_LSION ((uint32_t)0x00000001) /*!< Internal Low Speed oscillator enable */ |
bogdanm | 86:04dd9b1680ae | 5587 | #define RCC_CSR_LSIRDY ((uint32_t)0x00000002) /*!< Internal Low Speed oscillator Ready */ |
bogdanm | 86:04dd9b1680ae | 5588 | #define RCC_CSR_RMVF ((uint32_t)0x01000000) /*!< Remove reset flag */ |
bogdanm | 86:04dd9b1680ae | 5589 | #define RCC_CSR_OBLRSTF ((uint32_t)0x02000000) /*!< OBL reset flag */ |
bogdanm | 86:04dd9b1680ae | 5590 | #define RCC_CSR_PINRSTF ((uint32_t)0x04000000) /*!< PIN reset flag */ |
bogdanm | 86:04dd9b1680ae | 5591 | #define RCC_CSR_PORRSTF ((uint32_t)0x08000000) /*!< POR/PDR reset flag */ |
bogdanm | 86:04dd9b1680ae | 5592 | #define RCC_CSR_SFTRSTF ((uint32_t)0x10000000) /*!< Software Reset flag */ |
bogdanm | 86:04dd9b1680ae | 5593 | #define RCC_CSR_IWDGRSTF ((uint32_t)0x20000000) /*!< Independent Watchdog reset flag */ |
bogdanm | 86:04dd9b1680ae | 5594 | #define RCC_CSR_WWDGRSTF ((uint32_t)0x40000000) /*!< Window watchdog reset flag */ |
bogdanm | 86:04dd9b1680ae | 5595 | #define RCC_CSR_LPWRRSTF ((uint32_t)0x80000000) /*!< Low-Power reset flag */ |
bogdanm | 86:04dd9b1680ae | 5596 | |
bogdanm | 86:04dd9b1680ae | 5597 | /******************* Bit definition for RCC_AHBRSTR register ****************/ |
bogdanm | 86:04dd9b1680ae | 5598 | #define RCC_AHBRSTR_GPIOARST ((uint32_t)0x00020000) /*!< GPIOA reset */ |
bogdanm | 86:04dd9b1680ae | 5599 | #define RCC_AHBRSTR_GPIOBRST ((uint32_t)0x00040000) /*!< GPIOB reset */ |
bogdanm | 86:04dd9b1680ae | 5600 | #define RCC_AHBRSTR_GPIOCRST ((uint32_t)0x00080000) /*!< GPIOC reset */ |
bogdanm | 86:04dd9b1680ae | 5601 | #define RCC_AHBRSTR_GPIODRST ((uint32_t)0x00100000) /*!< GPIOD reset */ |
bogdanm | 86:04dd9b1680ae | 5602 | #define RCC_AHBRSTR_GPIOFRST ((uint32_t)0x00400000) /*!< GPIOF reset */ |
bogdanm | 86:04dd9b1680ae | 5603 | #define RCC_AHBRSTR_TSCRST ((uint32_t)0x01000000) /*!< TSC reset */ |
bogdanm | 86:04dd9b1680ae | 5604 | #define RCC_AHBRSTR_ADC12RST ((uint32_t)0x10000000) /*!< ADC1 & ADC2 reset */ |
bogdanm | 86:04dd9b1680ae | 5605 | |
bogdanm | 86:04dd9b1680ae | 5606 | /******************* Bit definition for RCC_CFGR2 register ******************/ |
bogdanm | 86:04dd9b1680ae | 5607 | /*!< PREDIV configuration */ |
bogdanm | 86:04dd9b1680ae | 5608 | #define RCC_CFGR2_PREDIV ((uint32_t)0x0000000F) /*!< PREDIV[3:0] bits */ |
bogdanm | 86:04dd9b1680ae | 5609 | #define RCC_CFGR2_PREDIV_0 ((uint32_t)0x00000001) /*!< Bit 0 */ |
bogdanm | 86:04dd9b1680ae | 5610 | #define RCC_CFGR2_PREDIV_1 ((uint32_t)0x00000002) /*!< Bit 1 */ |
bogdanm | 86:04dd9b1680ae | 5611 | #define RCC_CFGR2_PREDIV_2 ((uint32_t)0x00000004) /*!< Bit 2 */ |
bogdanm | 86:04dd9b1680ae | 5612 | #define RCC_CFGR2_PREDIV_3 ((uint32_t)0x00000008) /*!< Bit 3 */ |
bogdanm | 86:04dd9b1680ae | 5613 | |
bogdanm | 86:04dd9b1680ae | 5614 | #define RCC_CFGR2_PREDIV_DIV1 ((uint32_t)0x00000000) /*!< PREDIV input clock not divided */ |
bogdanm | 86:04dd9b1680ae | 5615 | #define RCC_CFGR2_PREDIV_DIV2 ((uint32_t)0x00000001) /*!< PREDIV input clock divided by 2 */ |
bogdanm | 86:04dd9b1680ae | 5616 | #define RCC_CFGR2_PREDIV_DIV3 ((uint32_t)0x00000002) /*!< PREDIV input clock divided by 3 */ |
bogdanm | 86:04dd9b1680ae | 5617 | #define RCC_CFGR2_PREDIV_DIV4 ((uint32_t)0x00000003) /*!< PREDIV input clock divided by 4 */ |
bogdanm | 86:04dd9b1680ae | 5618 | #define RCC_CFGR2_PREDIV_DIV5 ((uint32_t)0x00000004) /*!< PREDIV input clock divided by 5 */ |
bogdanm | 86:04dd9b1680ae | 5619 | #define RCC_CFGR2_PREDIV_DIV6 ((uint32_t)0x00000005) /*!< PREDIV input clock divided by 6 */ |
bogdanm | 86:04dd9b1680ae | 5620 | #define RCC_CFGR2_PREDIV_DIV7 ((uint32_t)0x00000006) /*!< PREDIV input clock divided by 7 */ |
bogdanm | 86:04dd9b1680ae | 5621 | #define RCC_CFGR2_PREDIV_DIV8 ((uint32_t)0x00000007) /*!< PREDIV input clock divided by 8 */ |
bogdanm | 86:04dd9b1680ae | 5622 | #define RCC_CFGR2_PREDIV_DIV9 ((uint32_t)0x00000008) /*!< PREDIV input clock divided by 9 */ |
bogdanm | 86:04dd9b1680ae | 5623 | #define RCC_CFGR2_PREDIV_DIV10 ((uint32_t)0x00000009) /*!< PREDIV input clock divided by 10 */ |
bogdanm | 86:04dd9b1680ae | 5624 | #define RCC_CFGR2_PREDIV_DIV11 ((uint32_t)0x0000000A) /*!< PREDIV input clock divided by 11 */ |
bogdanm | 86:04dd9b1680ae | 5625 | #define RCC_CFGR2_PREDIV_DIV12 ((uint32_t)0x0000000B) /*!< PREDIV input clock divided by 12 */ |
bogdanm | 86:04dd9b1680ae | 5626 | #define RCC_CFGR2_PREDIV_DIV13 ((uint32_t)0x0000000C) /*!< PREDIV input clock divided by 13 */ |
bogdanm | 86:04dd9b1680ae | 5627 | #define RCC_CFGR2_PREDIV_DIV14 ((uint32_t)0x0000000D) /*!< PREDIV input clock divided by 14 */ |
bogdanm | 86:04dd9b1680ae | 5628 | #define RCC_CFGR2_PREDIV_DIV15 ((uint32_t)0x0000000E) /*!< PREDIV input clock divided by 15 */ |
bogdanm | 86:04dd9b1680ae | 5629 | #define RCC_CFGR2_PREDIV_DIV16 ((uint32_t)0x0000000F) /*!< PREDIV input clock divided by 16 */ |
bogdanm | 86:04dd9b1680ae | 5630 | |
bogdanm | 86:04dd9b1680ae | 5631 | /*!< ADCPRE12 configuration */ |
bogdanm | 86:04dd9b1680ae | 5632 | #define RCC_CFGR2_ADCPRE12 ((uint32_t)0x000001F0) /*!< ADCPRE12[8:4] bits */ |
bogdanm | 86:04dd9b1680ae | 5633 | #define RCC_CFGR2_ADCPRE12_0 ((uint32_t)0x00000010) /*!< Bit 0 */ |
bogdanm | 86:04dd9b1680ae | 5634 | #define RCC_CFGR2_ADCPRE12_1 ((uint32_t)0x00000020) /*!< Bit 1 */ |
bogdanm | 86:04dd9b1680ae | 5635 | #define RCC_CFGR2_ADCPRE12_2 ((uint32_t)0x00000040) /*!< Bit 2 */ |
bogdanm | 86:04dd9b1680ae | 5636 | #define RCC_CFGR2_ADCPRE12_3 ((uint32_t)0x00000080) /*!< Bit 3 */ |
bogdanm | 86:04dd9b1680ae | 5637 | #define RCC_CFGR2_ADCPRE12_4 ((uint32_t)0x00000100) /*!< Bit 4 */ |
bogdanm | 86:04dd9b1680ae | 5638 | |
bogdanm | 86:04dd9b1680ae | 5639 | #define RCC_CFGR2_ADCPRE12_NO ((uint32_t)0x00000000) /*!< ADC12 clock disabled, ADC12 can use AHB clock */ |
bogdanm | 86:04dd9b1680ae | 5640 | #define RCC_CFGR2_ADCPRE12_DIV1 ((uint32_t)0x00000100) /*!< ADC12 PLL clock divided by 1 */ |
bogdanm | 86:04dd9b1680ae | 5641 | #define RCC_CFGR2_ADCPRE12_DIV2 ((uint32_t)0x00000110) /*!< ADC12 PLL clock divided by 2 */ |
bogdanm | 86:04dd9b1680ae | 5642 | #define RCC_CFGR2_ADCPRE12_DIV4 ((uint32_t)0x00000120) /*!< ADC12 PLL clock divided by 4 */ |
bogdanm | 86:04dd9b1680ae | 5643 | #define RCC_CFGR2_ADCPRE12_DIV6 ((uint32_t)0x00000130) /*!< ADC12 PLL clock divided by 6 */ |
bogdanm | 86:04dd9b1680ae | 5644 | #define RCC_CFGR2_ADCPRE12_DIV8 ((uint32_t)0x00000140) /*!< ADC12 PLL clock divided by 8 */ |
bogdanm | 86:04dd9b1680ae | 5645 | #define RCC_CFGR2_ADCPRE12_DIV10 ((uint32_t)0x00000150) /*!< ADC12 PLL clock divided by 10 */ |
bogdanm | 86:04dd9b1680ae | 5646 | #define RCC_CFGR2_ADCPRE12_DIV12 ((uint32_t)0x00000160) /*!< ADC12 PLL clock divided by 12 */ |
bogdanm | 86:04dd9b1680ae | 5647 | #define RCC_CFGR2_ADCPRE12_DIV16 ((uint32_t)0x00000170) /*!< ADC12 PLL clock divided by 16 */ |
bogdanm | 86:04dd9b1680ae | 5648 | #define RCC_CFGR2_ADCPRE12_DIV32 ((uint32_t)0x00000180) /*!< ADC12 PLL clock divided by 32 */ |
bogdanm | 86:04dd9b1680ae | 5649 | #define RCC_CFGR2_ADCPRE12_DIV64 ((uint32_t)0x00000190) /*!< ADC12 PLL clock divided by 64 */ |
bogdanm | 86:04dd9b1680ae | 5650 | #define RCC_CFGR2_ADCPRE12_DIV128 ((uint32_t)0x000001A0) /*!< ADC12 PLL clock divided by 128 */ |
bogdanm | 86:04dd9b1680ae | 5651 | #define RCC_CFGR2_ADCPRE12_DIV256 ((uint32_t)0x000001B0) /*!< ADC12 PLL clock divided by 256 */ |
bogdanm | 86:04dd9b1680ae | 5652 | |
bogdanm | 86:04dd9b1680ae | 5653 | /******************* Bit definition for RCC_CFGR3 register ******************/ |
bogdanm | 86:04dd9b1680ae | 5654 | #define RCC_CFGR3_USART1SW ((uint32_t)0x00000003) /*!< USART1SW[1:0] bits */ |
bogdanm | 86:04dd9b1680ae | 5655 | #define RCC_CFGR3_USART1SW_0 ((uint32_t)0x00000001) /*!< Bit 0 */ |
bogdanm | 86:04dd9b1680ae | 5656 | #define RCC_CFGR3_USART1SW_1 ((uint32_t)0x00000002) /*!< Bit 1 */ |
bogdanm | 86:04dd9b1680ae | 5657 | |
bogdanm | 86:04dd9b1680ae | 5658 | #define RCC_CFGR3_USART1SW_PCLK ((uint32_t)0x00000000) /*!< PCLK1 clock used as USART1 clock source */ |
bogdanm | 86:04dd9b1680ae | 5659 | #define RCC_CFGR3_USART1SW_SYSCLK ((uint32_t)0x00000001) /*!< System clock selected as USART1 clock source */ |
bogdanm | 86:04dd9b1680ae | 5660 | #define RCC_CFGR3_USART1SW_LSE ((uint32_t)0x00000002) /*!< LSE oscillator clock used as USART1 clock source */ |
bogdanm | 86:04dd9b1680ae | 5661 | #define RCC_CFGR3_USART1SW_HSI ((uint32_t)0x00000003) /*!< HSI oscillator clock used as USART1 clock source */ |
bogdanm | 86:04dd9b1680ae | 5662 | |
bogdanm | 86:04dd9b1680ae | 5663 | #define RCC_CFGR3_I2CSW ((uint32_t)0x00000010) /*!< I2CSW bits */ |
bogdanm | 86:04dd9b1680ae | 5664 | #define RCC_CFGR3_I2C1SW ((uint32_t)0x00000010) /*!< I2C1SW bits */ |
bogdanm | 86:04dd9b1680ae | 5665 | |
bogdanm | 86:04dd9b1680ae | 5666 | #define RCC_CFGR3_I2C1SW_HSI ((uint32_t)0x00000000) /*!< HSI oscillator clock used as I2C1 clock source */ |
bogdanm | 86:04dd9b1680ae | 5667 | #define RCC_CFGR3_I2C1SW_SYSCLK ((uint32_t)0x00000010) /*!< System clock selected as I2C1 clock source */ |
bogdanm | 86:04dd9b1680ae | 5668 | |
bogdanm | 86:04dd9b1680ae | 5669 | #define RCC_CFGR3_TIMSW ((uint32_t)0x00000100) /*!< TIMSW bits */ |
bogdanm | 86:04dd9b1680ae | 5670 | #define RCC_CFGR3_TIM1SW ((uint32_t)0x00000100) /*!< TIM1SW bits */ |
bogdanm | 86:04dd9b1680ae | 5671 | |
bogdanm | 86:04dd9b1680ae | 5672 | #define RCC_CFGR3_TIM1SW_HCLK ((uint32_t)0x00000000) /*!< HCLK used as TIM1 clock source */ |
bogdanm | 86:04dd9b1680ae | 5673 | #define RCC_CFGR3_TIM1SW_PLL ((uint32_t)0x00000100) /*!< PLL clock used as TIM1 clock source */ |
bogdanm | 86:04dd9b1680ae | 5674 | |
bogdanm | 86:04dd9b1680ae | 5675 | #define RCC_CFGR3_HRTIMSW ((uint32_t)0x00001000) /*!< TIMSW bits */ |
bogdanm | 86:04dd9b1680ae | 5676 | #define RCC_CFGR3_HRTIM1SW ((uint32_t)0x00001000) /*!< TIM1SW bits */ |
bogdanm | 86:04dd9b1680ae | 5677 | |
bogdanm | 86:04dd9b1680ae | 5678 | #define RCC_CFGR3_HRTIM1SW_HCLK ((uint32_t)0x00000000) /*!< HCLK used as TIM1 clock source */ |
bogdanm | 86:04dd9b1680ae | 5679 | #define RCC_CFGR3_HRTIM1SW_PLL ((uint32_t)0x00001000) /*!< PLL clock used as TIM1 clock source */ |
bogdanm | 86:04dd9b1680ae | 5680 | |
bogdanm | 86:04dd9b1680ae | 5681 | #define RCC_CFGR3_USART2SW ((uint32_t)0x00030000) /*!< USART2SW[1:0] bits */ |
bogdanm | 86:04dd9b1680ae | 5682 | #define RCC_CFGR3_USART2SW_0 ((uint32_t)0x00010000) /*!< Bit 0 */ |
bogdanm | 86:04dd9b1680ae | 5683 | #define RCC_CFGR3_USART2SW_1 ((uint32_t)0x00020000) /*!< Bit 1 */ |
bogdanm | 86:04dd9b1680ae | 5684 | |
bogdanm | 86:04dd9b1680ae | 5685 | #define RCC_CFGR3_USART2SW_PCLK ((uint32_t)0x00000000) /*!< PCLK2 clock used as USART2 clock source */ |
bogdanm | 86:04dd9b1680ae | 5686 | #define RCC_CFGR3_USART2SW_SYSCLK ((uint32_t)0x00010000) /*!< System clock selected as USART2 clock source */ |
bogdanm | 86:04dd9b1680ae | 5687 | #define RCC_CFGR3_USART2SW_LSE ((uint32_t)0x00020000) /*!< LSE oscillator clock used as USART2 clock source */ |
bogdanm | 86:04dd9b1680ae | 5688 | #define RCC_CFGR3_USART2SW_HSI ((uint32_t)0x00030000) /*!< HSI oscillator clock used as USART2 clock source */ |
bogdanm | 86:04dd9b1680ae | 5689 | |
bogdanm | 86:04dd9b1680ae | 5690 | #define RCC_CFGR3_USART3SW ((uint32_t)0x000C0000) /*!< USART3SW[1:0] bits */ |
bogdanm | 86:04dd9b1680ae | 5691 | #define RCC_CFGR3_USART3SW_0 ((uint32_t)0x00040000) /*!< Bit 0 */ |
bogdanm | 86:04dd9b1680ae | 5692 | #define RCC_CFGR3_USART3SW_1 ((uint32_t)0x00080000) /*!< Bit 1 */ |
bogdanm | 86:04dd9b1680ae | 5693 | |
bogdanm | 86:04dd9b1680ae | 5694 | #define RCC_CFGR3_USART3SW_PCLK ((uint32_t)0x00000000) /*!< PCLK2 clock used as USART3 clock source */ |
bogdanm | 86:04dd9b1680ae | 5695 | #define RCC_CFGR3_USART3SW_SYSCLK ((uint32_t)0x00040000) /*!< System clock selected as USART3 clock source */ |
bogdanm | 86:04dd9b1680ae | 5696 | #define RCC_CFGR3_USART3SW_LSE ((uint32_t)0x00080000) /*!< LSE oscillator clock used as USART3 clock source */ |
bogdanm | 86:04dd9b1680ae | 5697 | #define RCC_CFGR3_USART3SW_HSI ((uint32_t)0x000C0000) /*!< HSI oscillator clock used as USART3 clock source */ |
bogdanm | 86:04dd9b1680ae | 5698 | |
bogdanm | 86:04dd9b1680ae | 5699 | /******************************************************************************/ |
bogdanm | 86:04dd9b1680ae | 5700 | /* */ |
bogdanm | 86:04dd9b1680ae | 5701 | /* Real-Time Clock (RTC) */ |
bogdanm | 86:04dd9b1680ae | 5702 | /* */ |
bogdanm | 86:04dd9b1680ae | 5703 | /******************************************************************************/ |
bogdanm | 86:04dd9b1680ae | 5704 | /******************** Bits definition for RTC_TR register *******************/ |
bogdanm | 86:04dd9b1680ae | 5705 | #define RTC_TR_PM ((uint32_t)0x00400000) |
bogdanm | 86:04dd9b1680ae | 5706 | #define RTC_TR_HT ((uint32_t)0x00300000) |
bogdanm | 86:04dd9b1680ae | 5707 | #define RTC_TR_HT_0 ((uint32_t)0x00100000) |
bogdanm | 86:04dd9b1680ae | 5708 | #define RTC_TR_HT_1 ((uint32_t)0x00200000) |
bogdanm | 86:04dd9b1680ae | 5709 | #define RTC_TR_HU ((uint32_t)0x000F0000) |
bogdanm | 86:04dd9b1680ae | 5710 | #define RTC_TR_HU_0 ((uint32_t)0x00010000) |
bogdanm | 86:04dd9b1680ae | 5711 | #define RTC_TR_HU_1 ((uint32_t)0x00020000) |
bogdanm | 86:04dd9b1680ae | 5712 | #define RTC_TR_HU_2 ((uint32_t)0x00040000) |
bogdanm | 86:04dd9b1680ae | 5713 | #define RTC_TR_HU_3 ((uint32_t)0x00080000) |
bogdanm | 86:04dd9b1680ae | 5714 | #define RTC_TR_MNT ((uint32_t)0x00007000) |
bogdanm | 86:04dd9b1680ae | 5715 | #define RTC_TR_MNT_0 ((uint32_t)0x00001000) |
bogdanm | 86:04dd9b1680ae | 5716 | #define RTC_TR_MNT_1 ((uint32_t)0x00002000) |
bogdanm | 86:04dd9b1680ae | 5717 | #define RTC_TR_MNT_2 ((uint32_t)0x00004000) |
bogdanm | 86:04dd9b1680ae | 5718 | #define RTC_TR_MNU ((uint32_t)0x00000F00) |
bogdanm | 86:04dd9b1680ae | 5719 | #define RTC_TR_MNU_0 ((uint32_t)0x00000100) |
bogdanm | 86:04dd9b1680ae | 5720 | #define RTC_TR_MNU_1 ((uint32_t)0x00000200) |
bogdanm | 86:04dd9b1680ae | 5721 | #define RTC_TR_MNU_2 ((uint32_t)0x00000400) |
bogdanm | 86:04dd9b1680ae | 5722 | #define RTC_TR_MNU_3 ((uint32_t)0x00000800) |
bogdanm | 86:04dd9b1680ae | 5723 | #define RTC_TR_ST ((uint32_t)0x00000070) |
bogdanm | 86:04dd9b1680ae | 5724 | #define RTC_TR_ST_0 ((uint32_t)0x00000010) |
bogdanm | 86:04dd9b1680ae | 5725 | #define RTC_TR_ST_1 ((uint32_t)0x00000020) |
bogdanm | 86:04dd9b1680ae | 5726 | #define RTC_TR_ST_2 ((uint32_t)0x00000040) |
bogdanm | 86:04dd9b1680ae | 5727 | #define RTC_TR_SU ((uint32_t)0x0000000F) |
bogdanm | 86:04dd9b1680ae | 5728 | #define RTC_TR_SU_0 ((uint32_t)0x00000001) |
bogdanm | 86:04dd9b1680ae | 5729 | #define RTC_TR_SU_1 ((uint32_t)0x00000002) |
bogdanm | 86:04dd9b1680ae | 5730 | #define RTC_TR_SU_2 ((uint32_t)0x00000004) |
bogdanm | 86:04dd9b1680ae | 5731 | #define RTC_TR_SU_3 ((uint32_t)0x00000008) |
bogdanm | 86:04dd9b1680ae | 5732 | |
bogdanm | 86:04dd9b1680ae | 5733 | /******************** Bits definition for RTC_DR register *******************/ |
bogdanm | 86:04dd9b1680ae | 5734 | #define RTC_DR_YT ((uint32_t)0x00F00000) |
bogdanm | 86:04dd9b1680ae | 5735 | #define RTC_DR_YT_0 ((uint32_t)0x00100000) |
bogdanm | 86:04dd9b1680ae | 5736 | #define RTC_DR_YT_1 ((uint32_t)0x00200000) |
bogdanm | 86:04dd9b1680ae | 5737 | #define RTC_DR_YT_2 ((uint32_t)0x00400000) |
bogdanm | 86:04dd9b1680ae | 5738 | #define RTC_DR_YT_3 ((uint32_t)0x00800000) |
bogdanm | 86:04dd9b1680ae | 5739 | #define RTC_DR_YU ((uint32_t)0x000F0000) |
bogdanm | 86:04dd9b1680ae | 5740 | #define RTC_DR_YU_0 ((uint32_t)0x00010000) |
bogdanm | 86:04dd9b1680ae | 5741 | #define RTC_DR_YU_1 ((uint32_t)0x00020000) |
bogdanm | 86:04dd9b1680ae | 5742 | #define RTC_DR_YU_2 ((uint32_t)0x00040000) |
bogdanm | 86:04dd9b1680ae | 5743 | #define RTC_DR_YU_3 ((uint32_t)0x00080000) |
bogdanm | 86:04dd9b1680ae | 5744 | #define RTC_DR_WDU ((uint32_t)0x0000E000) |
bogdanm | 86:04dd9b1680ae | 5745 | #define RTC_DR_WDU_0 ((uint32_t)0x00002000) |
bogdanm | 86:04dd9b1680ae | 5746 | #define RTC_DR_WDU_1 ((uint32_t)0x00004000) |
bogdanm | 86:04dd9b1680ae | 5747 | #define RTC_DR_WDU_2 ((uint32_t)0x00008000) |
bogdanm | 86:04dd9b1680ae | 5748 | #define RTC_DR_MT ((uint32_t)0x00001000) |
bogdanm | 86:04dd9b1680ae | 5749 | #define RTC_DR_MU ((uint32_t)0x00000F00) |
bogdanm | 86:04dd9b1680ae | 5750 | #define RTC_DR_MU_0 ((uint32_t)0x00000100) |
bogdanm | 86:04dd9b1680ae | 5751 | #define RTC_DR_MU_1 ((uint32_t)0x00000200) |
bogdanm | 86:04dd9b1680ae | 5752 | #define RTC_DR_MU_2 ((uint32_t)0x00000400) |
bogdanm | 86:04dd9b1680ae | 5753 | #define RTC_DR_MU_3 ((uint32_t)0x00000800) |
bogdanm | 86:04dd9b1680ae | 5754 | #define RTC_DR_DT ((uint32_t)0x00000030) |
bogdanm | 86:04dd9b1680ae | 5755 | #define RTC_DR_DT_0 ((uint32_t)0x00000010) |
bogdanm | 86:04dd9b1680ae | 5756 | #define RTC_DR_DT_1 ((uint32_t)0x00000020) |
bogdanm | 86:04dd9b1680ae | 5757 | #define RTC_DR_DU ((uint32_t)0x0000000F) |
bogdanm | 86:04dd9b1680ae | 5758 | #define RTC_DR_DU_0 ((uint32_t)0x00000001) |
bogdanm | 86:04dd9b1680ae | 5759 | #define RTC_DR_DU_1 ((uint32_t)0x00000002) |
bogdanm | 86:04dd9b1680ae | 5760 | #define RTC_DR_DU_2 ((uint32_t)0x00000004) |
bogdanm | 86:04dd9b1680ae | 5761 | #define RTC_DR_DU_3 ((uint32_t)0x00000008) |
bogdanm | 86:04dd9b1680ae | 5762 | |
bogdanm | 86:04dd9b1680ae | 5763 | /******************** Bits definition for RTC_CR register *******************/ |
bogdanm | 86:04dd9b1680ae | 5764 | #define RTC_CR_COE ((uint32_t)0x00800000) |
bogdanm | 86:04dd9b1680ae | 5765 | #define RTC_CR_OSEL ((uint32_t)0x00600000) |
bogdanm | 86:04dd9b1680ae | 5766 | #define RTC_CR_OSEL_0 ((uint32_t)0x00200000) |
bogdanm | 86:04dd9b1680ae | 5767 | #define RTC_CR_OSEL_1 ((uint32_t)0x00400000) |
bogdanm | 86:04dd9b1680ae | 5768 | #define RTC_CR_POL ((uint32_t)0x00100000) |
bogdanm | 86:04dd9b1680ae | 5769 | #define RTC_CR_COSEL ((uint32_t)0x00080000) |
bogdanm | 86:04dd9b1680ae | 5770 | #define RTC_CR_BCK ((uint32_t)0x00040000) |
bogdanm | 86:04dd9b1680ae | 5771 | #define RTC_CR_SUB1H ((uint32_t)0x00020000) |
bogdanm | 86:04dd9b1680ae | 5772 | #define RTC_CR_ADD1H ((uint32_t)0x00010000) |
bogdanm | 86:04dd9b1680ae | 5773 | #define RTC_CR_TSIE ((uint32_t)0x00008000) |
bogdanm | 86:04dd9b1680ae | 5774 | #define RTC_CR_WUTIE ((uint32_t)0x00004000) |
bogdanm | 86:04dd9b1680ae | 5775 | #define RTC_CR_ALRBIE ((uint32_t)0x00002000) |
bogdanm | 86:04dd9b1680ae | 5776 | #define RTC_CR_ALRAIE ((uint32_t)0x00001000) |
bogdanm | 86:04dd9b1680ae | 5777 | #define RTC_CR_TSE ((uint32_t)0x00000800) |
bogdanm | 86:04dd9b1680ae | 5778 | #define RTC_CR_WUTE ((uint32_t)0x00000400) |
bogdanm | 86:04dd9b1680ae | 5779 | #define RTC_CR_ALRBE ((uint32_t)0x00000200) |
bogdanm | 86:04dd9b1680ae | 5780 | #define RTC_CR_ALRAE ((uint32_t)0x00000100) |
bogdanm | 86:04dd9b1680ae | 5781 | #define RTC_CR_FMT ((uint32_t)0x00000040) |
bogdanm | 86:04dd9b1680ae | 5782 | #define RTC_CR_BYPSHAD ((uint32_t)0x00000020) |
bogdanm | 86:04dd9b1680ae | 5783 | #define RTC_CR_REFCKON ((uint32_t)0x00000010) |
bogdanm | 86:04dd9b1680ae | 5784 | #define RTC_CR_TSEDGE ((uint32_t)0x00000008) |
bogdanm | 86:04dd9b1680ae | 5785 | #define RTC_CR_WUCKSEL ((uint32_t)0x00000007) |
bogdanm | 86:04dd9b1680ae | 5786 | #define RTC_CR_WUCKSEL_0 ((uint32_t)0x00000001) |
bogdanm | 86:04dd9b1680ae | 5787 | #define RTC_CR_WUCKSEL_1 ((uint32_t)0x00000002) |
bogdanm | 86:04dd9b1680ae | 5788 | #define RTC_CR_WUCKSEL_2 ((uint32_t)0x00000004) |
bogdanm | 86:04dd9b1680ae | 5789 | |
bogdanm | 86:04dd9b1680ae | 5790 | /******************** Bits definition for RTC_ISR register ******************/ |
bogdanm | 86:04dd9b1680ae | 5791 | #define RTC_ISR_RECALPF ((uint32_t)0x00010000) |
bogdanm | 86:04dd9b1680ae | 5792 | #define RTC_ISR_TAMP3F ((uint32_t)0x00008000) |
bogdanm | 86:04dd9b1680ae | 5793 | #define RTC_ISR_TAMP2F ((uint32_t)0x00004000) |
bogdanm | 86:04dd9b1680ae | 5794 | #define RTC_ISR_TAMP1F ((uint32_t)0x00002000) |
bogdanm | 86:04dd9b1680ae | 5795 | #define RTC_ISR_TSOVF ((uint32_t)0x00001000) |
bogdanm | 86:04dd9b1680ae | 5796 | #define RTC_ISR_TSF ((uint32_t)0x00000800) |
bogdanm | 86:04dd9b1680ae | 5797 | #define RTC_ISR_WUTF ((uint32_t)0x00000400) |
bogdanm | 86:04dd9b1680ae | 5798 | #define RTC_ISR_ALRBF ((uint32_t)0x00000200) |
bogdanm | 86:04dd9b1680ae | 5799 | #define RTC_ISR_ALRAF ((uint32_t)0x00000100) |
bogdanm | 86:04dd9b1680ae | 5800 | #define RTC_ISR_INIT ((uint32_t)0x00000080) |
bogdanm | 86:04dd9b1680ae | 5801 | #define RTC_ISR_INITF ((uint32_t)0x00000040) |
bogdanm | 86:04dd9b1680ae | 5802 | #define RTC_ISR_RSF ((uint32_t)0x00000020) |
bogdanm | 86:04dd9b1680ae | 5803 | #define RTC_ISR_INITS ((uint32_t)0x00000010) |
bogdanm | 86:04dd9b1680ae | 5804 | #define RTC_ISR_SHPF ((uint32_t)0x00000008) |
bogdanm | 86:04dd9b1680ae | 5805 | #define RTC_ISR_WUTWF ((uint32_t)0x00000004) |
bogdanm | 86:04dd9b1680ae | 5806 | #define RTC_ISR_ALRBWF ((uint32_t)0x00000002) |
bogdanm | 86:04dd9b1680ae | 5807 | #define RTC_ISR_ALRAWF ((uint32_t)0x00000001) |
bogdanm | 86:04dd9b1680ae | 5808 | |
bogdanm | 86:04dd9b1680ae | 5809 | /******************** Bits definition for RTC_PRER register *****************/ |
bogdanm | 86:04dd9b1680ae | 5810 | #define RTC_PRER_PREDIV_A ((uint32_t)0x007F0000) |
bogdanm | 86:04dd9b1680ae | 5811 | #define RTC_PRER_PREDIV_S ((uint32_t)0x00007FFF) |
bogdanm | 86:04dd9b1680ae | 5812 | |
bogdanm | 86:04dd9b1680ae | 5813 | /******************** Bits definition for RTC_WUTR register *****************/ |
bogdanm | 86:04dd9b1680ae | 5814 | #define RTC_WUTR_WUT ((uint32_t)0x0000FFFF) |
bogdanm | 86:04dd9b1680ae | 5815 | |
bogdanm | 86:04dd9b1680ae | 5816 | /******************** Bits definition for RTC_ALRMAR register ***************/ |
bogdanm | 86:04dd9b1680ae | 5817 | #define RTC_ALRMAR_MSK4 ((uint32_t)0x80000000) |
bogdanm | 86:04dd9b1680ae | 5818 | #define RTC_ALRMAR_WDSEL ((uint32_t)0x40000000) |
bogdanm | 86:04dd9b1680ae | 5819 | #define RTC_ALRMAR_DT ((uint32_t)0x30000000) |
bogdanm | 86:04dd9b1680ae | 5820 | #define RTC_ALRMAR_DT_0 ((uint32_t)0x10000000) |
bogdanm | 86:04dd9b1680ae | 5821 | #define RTC_ALRMAR_DT_1 ((uint32_t)0x20000000) |
bogdanm | 86:04dd9b1680ae | 5822 | #define RTC_ALRMAR_DU ((uint32_t)0x0F000000) |
bogdanm | 86:04dd9b1680ae | 5823 | #define RTC_ALRMAR_DU_0 ((uint32_t)0x01000000) |
bogdanm | 86:04dd9b1680ae | 5824 | #define RTC_ALRMAR_DU_1 ((uint32_t)0x02000000) |
bogdanm | 86:04dd9b1680ae | 5825 | #define RTC_ALRMAR_DU_2 ((uint32_t)0x04000000) |
bogdanm | 86:04dd9b1680ae | 5826 | #define RTC_ALRMAR_DU_3 ((uint32_t)0x08000000) |
bogdanm | 86:04dd9b1680ae | 5827 | #define RTC_ALRMAR_MSK3 ((uint32_t)0x00800000) |
bogdanm | 86:04dd9b1680ae | 5828 | #define RTC_ALRMAR_PM ((uint32_t)0x00400000) |
bogdanm | 86:04dd9b1680ae | 5829 | #define RTC_ALRMAR_HT ((uint32_t)0x00300000) |
bogdanm | 86:04dd9b1680ae | 5830 | #define RTC_ALRMAR_HT_0 ((uint32_t)0x00100000) |
bogdanm | 86:04dd9b1680ae | 5831 | #define RTC_ALRMAR_HT_1 ((uint32_t)0x00200000) |
bogdanm | 86:04dd9b1680ae | 5832 | #define RTC_ALRMAR_HU ((uint32_t)0x000F0000) |
bogdanm | 86:04dd9b1680ae | 5833 | #define RTC_ALRMAR_HU_0 ((uint32_t)0x00010000) |
bogdanm | 86:04dd9b1680ae | 5834 | #define RTC_ALRMAR_HU_1 ((uint32_t)0x00020000) |
bogdanm | 86:04dd9b1680ae | 5835 | #define RTC_ALRMAR_HU_2 ((uint32_t)0x00040000) |
bogdanm | 86:04dd9b1680ae | 5836 | #define RTC_ALRMAR_HU_3 ((uint32_t)0x00080000) |
bogdanm | 86:04dd9b1680ae | 5837 | #define RTC_ALRMAR_MSK2 ((uint32_t)0x00008000) |
bogdanm | 86:04dd9b1680ae | 5838 | #define RTC_ALRMAR_MNT ((uint32_t)0x00007000) |
bogdanm | 86:04dd9b1680ae | 5839 | #define RTC_ALRMAR_MNT_0 ((uint32_t)0x00001000) |
bogdanm | 86:04dd9b1680ae | 5840 | #define RTC_ALRMAR_MNT_1 ((uint32_t)0x00002000) |
bogdanm | 86:04dd9b1680ae | 5841 | #define RTC_ALRMAR_MNT_2 ((uint32_t)0x00004000) |
bogdanm | 86:04dd9b1680ae | 5842 | #define RTC_ALRMAR_MNU ((uint32_t)0x00000F00) |
bogdanm | 86:04dd9b1680ae | 5843 | #define RTC_ALRMAR_MNU_0 ((uint32_t)0x00000100) |
bogdanm | 86:04dd9b1680ae | 5844 | #define RTC_ALRMAR_MNU_1 ((uint32_t)0x00000200) |
bogdanm | 86:04dd9b1680ae | 5845 | #define RTC_ALRMAR_MNU_2 ((uint32_t)0x00000400) |
bogdanm | 86:04dd9b1680ae | 5846 | #define RTC_ALRMAR_MNU_3 ((uint32_t)0x00000800) |
bogdanm | 86:04dd9b1680ae | 5847 | #define RTC_ALRMAR_MSK1 ((uint32_t)0x00000080) |
bogdanm | 86:04dd9b1680ae | 5848 | #define RTC_ALRMAR_ST ((uint32_t)0x00000070) |
bogdanm | 86:04dd9b1680ae | 5849 | #define RTC_ALRMAR_ST_0 ((uint32_t)0x00000010) |
bogdanm | 86:04dd9b1680ae | 5850 | #define RTC_ALRMAR_ST_1 ((uint32_t)0x00000020) |
bogdanm | 86:04dd9b1680ae | 5851 | #define RTC_ALRMAR_ST_2 ((uint32_t)0x00000040) |
bogdanm | 86:04dd9b1680ae | 5852 | #define RTC_ALRMAR_SU ((uint32_t)0x0000000F) |
bogdanm | 86:04dd9b1680ae | 5853 | #define RTC_ALRMAR_SU_0 ((uint32_t)0x00000001) |
bogdanm | 86:04dd9b1680ae | 5854 | #define RTC_ALRMAR_SU_1 ((uint32_t)0x00000002) |
bogdanm | 86:04dd9b1680ae | 5855 | #define RTC_ALRMAR_SU_2 ((uint32_t)0x00000004) |
bogdanm | 86:04dd9b1680ae | 5856 | #define RTC_ALRMAR_SU_3 ((uint32_t)0x00000008) |
bogdanm | 86:04dd9b1680ae | 5857 | |
bogdanm | 86:04dd9b1680ae | 5858 | /******************** Bits definition for RTC_ALRMBR register ***************/ |
bogdanm | 86:04dd9b1680ae | 5859 | #define RTC_ALRMBR_MSK4 ((uint32_t)0x80000000) |
bogdanm | 86:04dd9b1680ae | 5860 | #define RTC_ALRMBR_WDSEL ((uint32_t)0x40000000) |
bogdanm | 86:04dd9b1680ae | 5861 | #define RTC_ALRMBR_DT ((uint32_t)0x30000000) |
bogdanm | 86:04dd9b1680ae | 5862 | #define RTC_ALRMBR_DT_0 ((uint32_t)0x10000000) |
bogdanm | 86:04dd9b1680ae | 5863 | #define RTC_ALRMBR_DT_1 ((uint32_t)0x20000000) |
bogdanm | 86:04dd9b1680ae | 5864 | #define RTC_ALRMBR_DU ((uint32_t)0x0F000000) |
bogdanm | 86:04dd9b1680ae | 5865 | #define RTC_ALRMBR_DU_0 ((uint32_t)0x01000000) |
bogdanm | 86:04dd9b1680ae | 5866 | #define RTC_ALRMBR_DU_1 ((uint32_t)0x02000000) |
bogdanm | 86:04dd9b1680ae | 5867 | #define RTC_ALRMBR_DU_2 ((uint32_t)0x04000000) |
bogdanm | 86:04dd9b1680ae | 5868 | #define RTC_ALRMBR_DU_3 ((uint32_t)0x08000000) |
bogdanm | 86:04dd9b1680ae | 5869 | #define RTC_ALRMBR_MSK3 ((uint32_t)0x00800000) |
bogdanm | 86:04dd9b1680ae | 5870 | #define RTC_ALRMBR_PM ((uint32_t)0x00400000) |
bogdanm | 86:04dd9b1680ae | 5871 | #define RTC_ALRMBR_HT ((uint32_t)0x00300000) |
bogdanm | 86:04dd9b1680ae | 5872 | #define RTC_ALRMBR_HT_0 ((uint32_t)0x00100000) |
bogdanm | 86:04dd9b1680ae | 5873 | #define RTC_ALRMBR_HT_1 ((uint32_t)0x00200000) |
bogdanm | 86:04dd9b1680ae | 5874 | #define RTC_ALRMBR_HU ((uint32_t)0x000F0000) |
bogdanm | 86:04dd9b1680ae | 5875 | #define RTC_ALRMBR_HU_0 ((uint32_t)0x00010000) |
bogdanm | 86:04dd9b1680ae | 5876 | #define RTC_ALRMBR_HU_1 ((uint32_t)0x00020000) |
bogdanm | 86:04dd9b1680ae | 5877 | #define RTC_ALRMBR_HU_2 ((uint32_t)0x00040000) |
bogdanm | 86:04dd9b1680ae | 5878 | #define RTC_ALRMBR_HU_3 ((uint32_t)0x00080000) |
bogdanm | 86:04dd9b1680ae | 5879 | #define RTC_ALRMBR_MSK2 ((uint32_t)0x00008000) |
bogdanm | 86:04dd9b1680ae | 5880 | #define RTC_ALRMBR_MNT ((uint32_t)0x00007000) |
bogdanm | 86:04dd9b1680ae | 5881 | #define RTC_ALRMBR_MNT_0 ((uint32_t)0x00001000) |
bogdanm | 86:04dd9b1680ae | 5882 | #define RTC_ALRMBR_MNT_1 ((uint32_t)0x00002000) |
bogdanm | 86:04dd9b1680ae | 5883 | #define RTC_ALRMBR_MNT_2 ((uint32_t)0x00004000) |
bogdanm | 86:04dd9b1680ae | 5884 | #define RTC_ALRMBR_MNU ((uint32_t)0x00000F00) |
bogdanm | 86:04dd9b1680ae | 5885 | #define RTC_ALRMBR_MNU_0 ((uint32_t)0x00000100) |
bogdanm | 86:04dd9b1680ae | 5886 | #define RTC_ALRMBR_MNU_1 ((uint32_t)0x00000200) |
bogdanm | 86:04dd9b1680ae | 5887 | #define RTC_ALRMBR_MNU_2 ((uint32_t)0x00000400) |
bogdanm | 86:04dd9b1680ae | 5888 | #define RTC_ALRMBR_MNU_3 ((uint32_t)0x00000800) |
bogdanm | 86:04dd9b1680ae | 5889 | #define RTC_ALRMBR_MSK1 ((uint32_t)0x00000080) |
bogdanm | 86:04dd9b1680ae | 5890 | #define RTC_ALRMBR_ST ((uint32_t)0x00000070) |
bogdanm | 86:04dd9b1680ae | 5891 | #define RTC_ALRMBR_ST_0 ((uint32_t)0x00000010) |
bogdanm | 86:04dd9b1680ae | 5892 | #define RTC_ALRMBR_ST_1 ((uint32_t)0x00000020) |
bogdanm | 86:04dd9b1680ae | 5893 | #define RTC_ALRMBR_ST_2 ((uint32_t)0x00000040) |
bogdanm | 86:04dd9b1680ae | 5894 | #define RTC_ALRMBR_SU ((uint32_t)0x0000000F) |
bogdanm | 86:04dd9b1680ae | 5895 | #define RTC_ALRMBR_SU_0 ((uint32_t)0x00000001) |
bogdanm | 86:04dd9b1680ae | 5896 | #define RTC_ALRMBR_SU_1 ((uint32_t)0x00000002) |
bogdanm | 86:04dd9b1680ae | 5897 | #define RTC_ALRMBR_SU_2 ((uint32_t)0x00000004) |
bogdanm | 86:04dd9b1680ae | 5898 | #define RTC_ALRMBR_SU_3 ((uint32_t)0x00000008) |
bogdanm | 86:04dd9b1680ae | 5899 | |
bogdanm | 86:04dd9b1680ae | 5900 | /******************** Bits definition for RTC_WPR register ******************/ |
bogdanm | 86:04dd9b1680ae | 5901 | #define RTC_WPR_KEY ((uint32_t)0x000000FF) |
bogdanm | 86:04dd9b1680ae | 5902 | |
bogdanm | 86:04dd9b1680ae | 5903 | /******************** Bits definition for RTC_SSR register ******************/ |
bogdanm | 86:04dd9b1680ae | 5904 | #define RTC_SSR_SS ((uint32_t)0x0000FFFF) |
bogdanm | 86:04dd9b1680ae | 5905 | |
bogdanm | 86:04dd9b1680ae | 5906 | /******************** Bits definition for RTC_SHIFTR register ***************/ |
bogdanm | 86:04dd9b1680ae | 5907 | #define RTC_SHIFTR_SUBFS ((uint32_t)0x00007FFF) |
bogdanm | 86:04dd9b1680ae | 5908 | #define RTC_SHIFTR_ADD1S ((uint32_t)0x80000000) |
bogdanm | 86:04dd9b1680ae | 5909 | |
bogdanm | 86:04dd9b1680ae | 5910 | /******************** Bits definition for RTC_TSTR register *****************/ |
bogdanm | 86:04dd9b1680ae | 5911 | #define RTC_TSTR_PM ((uint32_t)0x00400000) |
bogdanm | 86:04dd9b1680ae | 5912 | #define RTC_TSTR_HT ((uint32_t)0x00300000) |
bogdanm | 86:04dd9b1680ae | 5913 | #define RTC_TSTR_HT_0 ((uint32_t)0x00100000) |
bogdanm | 86:04dd9b1680ae | 5914 | #define RTC_TSTR_HT_1 ((uint32_t)0x00200000) |
bogdanm | 86:04dd9b1680ae | 5915 | #define RTC_TSTR_HU ((uint32_t)0x000F0000) |
bogdanm | 86:04dd9b1680ae | 5916 | #define RTC_TSTR_HU_0 ((uint32_t)0x00010000) |
bogdanm | 86:04dd9b1680ae | 5917 | #define RTC_TSTR_HU_1 ((uint32_t)0x00020000) |
bogdanm | 86:04dd9b1680ae | 5918 | #define RTC_TSTR_HU_2 ((uint32_t)0x00040000) |
bogdanm | 86:04dd9b1680ae | 5919 | #define RTC_TSTR_HU_3 ((uint32_t)0x00080000) |
bogdanm | 86:04dd9b1680ae | 5920 | #define RTC_TSTR_MNT ((uint32_t)0x00007000) |
bogdanm | 86:04dd9b1680ae | 5921 | #define RTC_TSTR_MNT_0 ((uint32_t)0x00001000) |
bogdanm | 86:04dd9b1680ae | 5922 | #define RTC_TSTR_MNT_1 ((uint32_t)0x00002000) |
bogdanm | 86:04dd9b1680ae | 5923 | #define RTC_TSTR_MNT_2 ((uint32_t)0x00004000) |
bogdanm | 86:04dd9b1680ae | 5924 | #define RTC_TSTR_MNU ((uint32_t)0x00000F00) |
bogdanm | 86:04dd9b1680ae | 5925 | #define RTC_TSTR_MNU_0 ((uint32_t)0x00000100) |
bogdanm | 86:04dd9b1680ae | 5926 | #define RTC_TSTR_MNU_1 ((uint32_t)0x00000200) |
bogdanm | 86:04dd9b1680ae | 5927 | #define RTC_TSTR_MNU_2 ((uint32_t)0x00000400) |
bogdanm | 86:04dd9b1680ae | 5928 | #define RTC_TSTR_MNU_3 ((uint32_t)0x00000800) |
bogdanm | 86:04dd9b1680ae | 5929 | #define RTC_TSTR_ST ((uint32_t)0x00000070) |
bogdanm | 86:04dd9b1680ae | 5930 | #define RTC_TSTR_ST_0 ((uint32_t)0x00000010) |
bogdanm | 86:04dd9b1680ae | 5931 | #define RTC_TSTR_ST_1 ((uint32_t)0x00000020) |
bogdanm | 86:04dd9b1680ae | 5932 | #define RTC_TSTR_ST_2 ((uint32_t)0x00000040) |
bogdanm | 86:04dd9b1680ae | 5933 | #define RTC_TSTR_SU ((uint32_t)0x0000000F) |
bogdanm | 86:04dd9b1680ae | 5934 | #define RTC_TSTR_SU_0 ((uint32_t)0x00000001) |
bogdanm | 86:04dd9b1680ae | 5935 | #define RTC_TSTR_SU_1 ((uint32_t)0x00000002) |
bogdanm | 86:04dd9b1680ae | 5936 | #define RTC_TSTR_SU_2 ((uint32_t)0x00000004) |
bogdanm | 86:04dd9b1680ae | 5937 | #define RTC_TSTR_SU_3 ((uint32_t)0x00000008) |
bogdanm | 86:04dd9b1680ae | 5938 | |
bogdanm | 86:04dd9b1680ae | 5939 | /******************** Bits definition for RTC_TSDR register *****************/ |
bogdanm | 86:04dd9b1680ae | 5940 | #define RTC_TSDR_WDU ((uint32_t)0x0000E000) |
bogdanm | 86:04dd9b1680ae | 5941 | #define RTC_TSDR_WDU_0 ((uint32_t)0x00002000) |
bogdanm | 86:04dd9b1680ae | 5942 | #define RTC_TSDR_WDU_1 ((uint32_t)0x00004000) |
bogdanm | 86:04dd9b1680ae | 5943 | #define RTC_TSDR_WDU_2 ((uint32_t)0x00008000) |
bogdanm | 86:04dd9b1680ae | 5944 | #define RTC_TSDR_MT ((uint32_t)0x00001000) |
bogdanm | 86:04dd9b1680ae | 5945 | #define RTC_TSDR_MU ((uint32_t)0x00000F00) |
bogdanm | 86:04dd9b1680ae | 5946 | #define RTC_TSDR_MU_0 ((uint32_t)0x00000100) |
bogdanm | 86:04dd9b1680ae | 5947 | #define RTC_TSDR_MU_1 ((uint32_t)0x00000200) |
bogdanm | 86:04dd9b1680ae | 5948 | #define RTC_TSDR_MU_2 ((uint32_t)0x00000400) |
bogdanm | 86:04dd9b1680ae | 5949 | #define RTC_TSDR_MU_3 ((uint32_t)0x00000800) |
bogdanm | 86:04dd9b1680ae | 5950 | #define RTC_TSDR_DT ((uint32_t)0x00000030) |
bogdanm | 86:04dd9b1680ae | 5951 | #define RTC_TSDR_DT_0 ((uint32_t)0x00000010) |
bogdanm | 86:04dd9b1680ae | 5952 | #define RTC_TSDR_DT_1 ((uint32_t)0x00000020) |
bogdanm | 86:04dd9b1680ae | 5953 | #define RTC_TSDR_DU ((uint32_t)0x0000000F) |
bogdanm | 86:04dd9b1680ae | 5954 | #define RTC_TSDR_DU_0 ((uint32_t)0x00000001) |
bogdanm | 86:04dd9b1680ae | 5955 | #define RTC_TSDR_DU_1 ((uint32_t)0x00000002) |
bogdanm | 86:04dd9b1680ae | 5956 | #define RTC_TSDR_DU_2 ((uint32_t)0x00000004) |
bogdanm | 86:04dd9b1680ae | 5957 | #define RTC_TSDR_DU_3 ((uint32_t)0x00000008) |
bogdanm | 86:04dd9b1680ae | 5958 | |
bogdanm | 86:04dd9b1680ae | 5959 | /******************** Bits definition for RTC_TSSSR register ****************/ |
bogdanm | 86:04dd9b1680ae | 5960 | #define RTC_TSSSR_SS ((uint32_t)0x0000FFFF) |
bogdanm | 86:04dd9b1680ae | 5961 | |
bogdanm | 86:04dd9b1680ae | 5962 | /******************** Bits definition for RTC_CAL register *****************/ |
bogdanm | 86:04dd9b1680ae | 5963 | #define RTC_CALR_CALP ((uint32_t)0x00008000) |
bogdanm | 86:04dd9b1680ae | 5964 | #define RTC_CALR_CALW8 ((uint32_t)0x00004000) |
bogdanm | 86:04dd9b1680ae | 5965 | #define RTC_CALR_CALW16 ((uint32_t)0x00002000) |
bogdanm | 86:04dd9b1680ae | 5966 | #define RTC_CALR_CALM ((uint32_t)0x000001FF) |
bogdanm | 86:04dd9b1680ae | 5967 | #define RTC_CALR_CALM_0 ((uint32_t)0x00000001) |
bogdanm | 86:04dd9b1680ae | 5968 | #define RTC_CALR_CALM_1 ((uint32_t)0x00000002) |
bogdanm | 86:04dd9b1680ae | 5969 | #define RTC_CALR_CALM_2 ((uint32_t)0x00000004) |
bogdanm | 86:04dd9b1680ae | 5970 | #define RTC_CALR_CALM_3 ((uint32_t)0x00000008) |
bogdanm | 86:04dd9b1680ae | 5971 | #define RTC_CALR_CALM_4 ((uint32_t)0x00000010) |
bogdanm | 86:04dd9b1680ae | 5972 | #define RTC_CALR_CALM_5 ((uint32_t)0x00000020) |
bogdanm | 86:04dd9b1680ae | 5973 | #define RTC_CALR_CALM_6 ((uint32_t)0x00000040) |
bogdanm | 86:04dd9b1680ae | 5974 | #define RTC_CALR_CALM_7 ((uint32_t)0x00000080) |
bogdanm | 86:04dd9b1680ae | 5975 | #define RTC_CALR_CALM_8 ((uint32_t)0x00000100) |
bogdanm | 86:04dd9b1680ae | 5976 | |
bogdanm | 86:04dd9b1680ae | 5977 | /******************** Bits definition for RTC_TAFCR register ****************/ |
bogdanm | 86:04dd9b1680ae | 5978 | #define RTC_TAFCR_ALARMOUTTYPE ((uint32_t)0x00040000) |
bogdanm | 86:04dd9b1680ae | 5979 | #define RTC_TAFCR_TAMPPUDIS ((uint32_t)0x00008000) |
bogdanm | 86:04dd9b1680ae | 5980 | #define RTC_TAFCR_TAMPPRCH ((uint32_t)0x00006000) |
bogdanm | 86:04dd9b1680ae | 5981 | #define RTC_TAFCR_TAMPPRCH_0 ((uint32_t)0x00002000) |
bogdanm | 86:04dd9b1680ae | 5982 | #define RTC_TAFCR_TAMPPRCH_1 ((uint32_t)0x00004000) |
bogdanm | 86:04dd9b1680ae | 5983 | #define RTC_TAFCR_TAMPFLT ((uint32_t)0x00001800) |
bogdanm | 86:04dd9b1680ae | 5984 | #define RTC_TAFCR_TAMPFLT_0 ((uint32_t)0x00000800) |
bogdanm | 86:04dd9b1680ae | 5985 | #define RTC_TAFCR_TAMPFLT_1 ((uint32_t)0x00001000) |
bogdanm | 86:04dd9b1680ae | 5986 | #define RTC_TAFCR_TAMPFREQ ((uint32_t)0x00000700) |
bogdanm | 86:04dd9b1680ae | 5987 | #define RTC_TAFCR_TAMPFREQ_0 ((uint32_t)0x00000100) |
bogdanm | 86:04dd9b1680ae | 5988 | #define RTC_TAFCR_TAMPFREQ_1 ((uint32_t)0x00000200) |
bogdanm | 86:04dd9b1680ae | 5989 | #define RTC_TAFCR_TAMPFREQ_2 ((uint32_t)0x00000400) |
bogdanm | 86:04dd9b1680ae | 5990 | #define RTC_TAFCR_TAMPTS ((uint32_t)0x00000080) |
bogdanm | 86:04dd9b1680ae | 5991 | #define RTC_TAFCR_TAMP3TRG ((uint32_t)0x00000040) |
bogdanm | 86:04dd9b1680ae | 5992 | #define RTC_TAFCR_TAMP3E ((uint32_t)0x00000020) |
bogdanm | 86:04dd9b1680ae | 5993 | #define RTC_TAFCR_TAMP2TRG ((uint32_t)0x00000010) |
bogdanm | 86:04dd9b1680ae | 5994 | #define RTC_TAFCR_TAMP2E ((uint32_t)0x00000008) |
bogdanm | 86:04dd9b1680ae | 5995 | #define RTC_TAFCR_TAMPIE ((uint32_t)0x00000004) |
bogdanm | 86:04dd9b1680ae | 5996 | #define RTC_TAFCR_TAMP1TRG ((uint32_t)0x00000002) |
bogdanm | 86:04dd9b1680ae | 5997 | #define RTC_TAFCR_TAMP1E ((uint32_t)0x00000001) |
bogdanm | 86:04dd9b1680ae | 5998 | |
bogdanm | 86:04dd9b1680ae | 5999 | /******************** Bits definition for RTC_ALRMASSR register *************/ |
bogdanm | 86:04dd9b1680ae | 6000 | #define RTC_ALRMASSR_MASKSS ((uint32_t)0x0F000000) |
bogdanm | 86:04dd9b1680ae | 6001 | #define RTC_ALRMASSR_MASKSS_0 ((uint32_t)0x01000000) |
bogdanm | 86:04dd9b1680ae | 6002 | #define RTC_ALRMASSR_MASKSS_1 ((uint32_t)0x02000000) |
bogdanm | 86:04dd9b1680ae | 6003 | #define RTC_ALRMASSR_MASKSS_2 ((uint32_t)0x04000000) |
bogdanm | 86:04dd9b1680ae | 6004 | #define RTC_ALRMASSR_MASKSS_3 ((uint32_t)0x08000000) |
bogdanm | 86:04dd9b1680ae | 6005 | #define RTC_ALRMASSR_SS ((uint32_t)0x00007FFF) |
bogdanm | 86:04dd9b1680ae | 6006 | |
bogdanm | 86:04dd9b1680ae | 6007 | /******************** Bits definition for RTC_ALRMBSSR register *************/ |
bogdanm | 86:04dd9b1680ae | 6008 | #define RTC_ALRMBSSR_MASKSS ((uint32_t)0x0F000000) |
bogdanm | 86:04dd9b1680ae | 6009 | #define RTC_ALRMBSSR_MASKSS_0 ((uint32_t)0x01000000) |
bogdanm | 86:04dd9b1680ae | 6010 | #define RTC_ALRMBSSR_MASKSS_1 ((uint32_t)0x02000000) |
bogdanm | 86:04dd9b1680ae | 6011 | #define RTC_ALRMBSSR_MASKSS_2 ((uint32_t)0x04000000) |
bogdanm | 86:04dd9b1680ae | 6012 | #define RTC_ALRMBSSR_MASKSS_3 ((uint32_t)0x08000000) |
bogdanm | 86:04dd9b1680ae | 6013 | #define RTC_ALRMBSSR_SS ((uint32_t)0x00007FFF) |
bogdanm | 86:04dd9b1680ae | 6014 | |
bogdanm | 86:04dd9b1680ae | 6015 | /******************** Bits definition for RTC_BKP0R register ****************/ |
bogdanm | 86:04dd9b1680ae | 6016 | #define RTC_BKP0R ((uint32_t)0xFFFFFFFF) |
bogdanm | 86:04dd9b1680ae | 6017 | |
bogdanm | 86:04dd9b1680ae | 6018 | /******************** Bits definition for RTC_BKP1R register ****************/ |
bogdanm | 86:04dd9b1680ae | 6019 | #define RTC_BKP1R ((uint32_t)0xFFFFFFFF) |
bogdanm | 86:04dd9b1680ae | 6020 | |
bogdanm | 86:04dd9b1680ae | 6021 | /******************** Bits definition for RTC_BKP2R register ****************/ |
bogdanm | 86:04dd9b1680ae | 6022 | #define RTC_BKP2R ((uint32_t)0xFFFFFFFF) |
bogdanm | 86:04dd9b1680ae | 6023 | |
bogdanm | 86:04dd9b1680ae | 6024 | /******************** Bits definition for RTC_BKP3R register ****************/ |
bogdanm | 86:04dd9b1680ae | 6025 | #define RTC_BKP3R ((uint32_t)0xFFFFFFFF) |
bogdanm | 86:04dd9b1680ae | 6026 | |
bogdanm | 86:04dd9b1680ae | 6027 | /******************** Bits definition for RTC_BKP4R register ****************/ |
bogdanm | 86:04dd9b1680ae | 6028 | #define RTC_BKP4R ((uint32_t)0xFFFFFFFF) |
bogdanm | 86:04dd9b1680ae | 6029 | |
bogdanm | 86:04dd9b1680ae | 6030 | /******************** Bits definition for RTC_BKP5R register ****************/ |
bogdanm | 86:04dd9b1680ae | 6031 | #define RTC_BKP5R ((uint32_t)0xFFFFFFFF) |
bogdanm | 86:04dd9b1680ae | 6032 | |
bogdanm | 86:04dd9b1680ae | 6033 | /******************** Bits definition for RTC_BKP6R register ****************/ |
bogdanm | 86:04dd9b1680ae | 6034 | #define RTC_BKP6R ((uint32_t)0xFFFFFFFF) |
bogdanm | 86:04dd9b1680ae | 6035 | |
bogdanm | 86:04dd9b1680ae | 6036 | /******************** Bits definition for RTC_BKP7R register ****************/ |
bogdanm | 86:04dd9b1680ae | 6037 | #define RTC_BKP7R ((uint32_t)0xFFFFFFFF) |
bogdanm | 86:04dd9b1680ae | 6038 | |
bogdanm | 86:04dd9b1680ae | 6039 | /******************** Bits definition for RTC_BKP8R register ****************/ |
bogdanm | 86:04dd9b1680ae | 6040 | #define RTC_BKP8R ((uint32_t)0xFFFFFFFF) |
bogdanm | 86:04dd9b1680ae | 6041 | |
bogdanm | 86:04dd9b1680ae | 6042 | /******************** Bits definition for RTC_BKP9R register ****************/ |
bogdanm | 86:04dd9b1680ae | 6043 | #define RTC_BKP9R ((uint32_t)0xFFFFFFFF) |
bogdanm | 86:04dd9b1680ae | 6044 | |
bogdanm | 86:04dd9b1680ae | 6045 | /******************** Bits definition for RTC_BKP10R register ***************/ |
bogdanm | 86:04dd9b1680ae | 6046 | #define RTC_BKP10R ((uint32_t)0xFFFFFFFF) |
bogdanm | 86:04dd9b1680ae | 6047 | |
bogdanm | 86:04dd9b1680ae | 6048 | /******************** Bits definition for RTC_BKP11R register ***************/ |
bogdanm | 86:04dd9b1680ae | 6049 | #define RTC_BKP11R ((uint32_t)0xFFFFFFFF) |
bogdanm | 86:04dd9b1680ae | 6050 | |
bogdanm | 86:04dd9b1680ae | 6051 | /******************** Bits definition for RTC_BKP12R register ***************/ |
bogdanm | 86:04dd9b1680ae | 6052 | #define RTC_BKP12R ((uint32_t)0xFFFFFFFF) |
bogdanm | 86:04dd9b1680ae | 6053 | |
bogdanm | 86:04dd9b1680ae | 6054 | /******************** Bits definition for RTC_BKP13R register ***************/ |
bogdanm | 86:04dd9b1680ae | 6055 | #define RTC_BKP13R ((uint32_t)0xFFFFFFFF) |
bogdanm | 86:04dd9b1680ae | 6056 | |
bogdanm | 86:04dd9b1680ae | 6057 | /******************** Bits definition for RTC_BKP14R register ***************/ |
bogdanm | 86:04dd9b1680ae | 6058 | #define RTC_BKP14R ((uint32_t)0xFFFFFFFF) |
bogdanm | 86:04dd9b1680ae | 6059 | |
bogdanm | 86:04dd9b1680ae | 6060 | /******************** Bits definition for RTC_BKP15R register ***************/ |
bogdanm | 86:04dd9b1680ae | 6061 | #define RTC_BKP15R ((uint32_t)0xFFFFFFFF) |
bogdanm | 86:04dd9b1680ae | 6062 | |
bogdanm | 86:04dd9b1680ae | 6063 | /******************** Number of backup registers ******************************/ |
bogdanm | 86:04dd9b1680ae | 6064 | #define RTC_BKP_NUMBER ((uint32_t)0x00000010) |
bogdanm | 86:04dd9b1680ae | 6065 | |
bogdanm | 86:04dd9b1680ae | 6066 | /******************************************************************************/ |
bogdanm | 86:04dd9b1680ae | 6067 | /* */ |
bogdanm | 86:04dd9b1680ae | 6068 | /* Serial Peripheral Interface (SPI) */ |
bogdanm | 86:04dd9b1680ae | 6069 | /* */ |
bogdanm | 86:04dd9b1680ae | 6070 | /******************************************************************************/ |
bogdanm | 86:04dd9b1680ae | 6071 | /******************* Bit definition for SPI_CR1 register ********************/ |
bogdanm | 86:04dd9b1680ae | 6072 | #define SPI_CR1_CPHA ((uint32_t)0x00000001) /*!< Clock Phase */ |
bogdanm | 86:04dd9b1680ae | 6073 | #define SPI_CR1_CPOL ((uint32_t)0x00000002) /*!< Clock Polarity */ |
bogdanm | 86:04dd9b1680ae | 6074 | #define SPI_CR1_MSTR ((uint32_t)0x00000004) /*!< Master Selection */ |
bogdanm | 86:04dd9b1680ae | 6075 | #define SPI_CR1_BR ((uint32_t)0x00000038) /*!< BR[2:0] bits (Baud Rate Control) */ |
bogdanm | 86:04dd9b1680ae | 6076 | #define SPI_CR1_BR_0 ((uint32_t)0x00000008) /*!< Bit 0 */ |
bogdanm | 86:04dd9b1680ae | 6077 | #define SPI_CR1_BR_1 ((uint32_t)0x00000010) /*!< Bit 1 */ |
bogdanm | 86:04dd9b1680ae | 6078 | #define SPI_CR1_BR_2 ((uint32_t)0x00000020) /*!< Bit 2 */ |
bogdanm | 86:04dd9b1680ae | 6079 | #define SPI_CR1_SPE ((uint32_t)0x00000040) /*!< SPI Enable */ |
bogdanm | 86:04dd9b1680ae | 6080 | #define SPI_CR1_LSBFIRST ((uint32_t)0x00000080) /*!< Frame Format */ |
bogdanm | 86:04dd9b1680ae | 6081 | #define SPI_CR1_SSI ((uint32_t)0x00000100) /*!< Internal slave select */ |
bogdanm | 86:04dd9b1680ae | 6082 | #define SPI_CR1_SSM ((uint32_t)0x00000200) /*!< Software slave management */ |
bogdanm | 86:04dd9b1680ae | 6083 | #define SPI_CR1_RXONLY ((uint32_t)0x00000400) /*!< Receive only */ |
bogdanm | 86:04dd9b1680ae | 6084 | #define SPI_CR1_CRCL ((uint32_t)0x00000800) /*!< CRC Length */ |
bogdanm | 86:04dd9b1680ae | 6085 | #define SPI_CR1_CRCNEXT ((uint32_t)0x00001000) /*!< Transmit CRC next */ |
bogdanm | 86:04dd9b1680ae | 6086 | #define SPI_CR1_CRCEN ((uint32_t)0x00002000) /*!< Hardware CRC calculation enable */ |
bogdanm | 86:04dd9b1680ae | 6087 | #define SPI_CR1_BIDIOE ((uint32_t)0x00004000) /*!< Output enable in bidirectional mode */ |
bogdanm | 86:04dd9b1680ae | 6088 | #define SPI_CR1_BIDIMODE ((uint32_t)0x00008000) /*!< Bidirectional data mode enable */ |
bogdanm | 86:04dd9b1680ae | 6089 | |
bogdanm | 86:04dd9b1680ae | 6090 | /******************* Bit definition for SPI_CR2 register ********************/ |
bogdanm | 86:04dd9b1680ae | 6091 | #define SPI_CR2_RXDMAEN ((uint32_t)0x00000001) /*!< Rx Buffer DMA Enable */ |
bogdanm | 86:04dd9b1680ae | 6092 | #define SPI_CR2_TXDMAEN ((uint32_t)0x00000002) /*!< Tx Buffer DMA Enable */ |
bogdanm | 86:04dd9b1680ae | 6093 | #define SPI_CR2_SSOE ((uint32_t)0x00000004) /*!< SS Output Enable */ |
bogdanm | 86:04dd9b1680ae | 6094 | #define SPI_CR2_NSSP ((uint32_t)0x00000008) /*!< NSS pulse management Enable */ |
bogdanm | 86:04dd9b1680ae | 6095 | #define SPI_CR2_FRF ((uint32_t)0x00000010) /*!< Frame Format Enable */ |
bogdanm | 86:04dd9b1680ae | 6096 | #define SPI_CR2_ERRIE ((uint32_t)0x00000020) /*!< Error Interrupt Enable */ |
bogdanm | 86:04dd9b1680ae | 6097 | #define SPI_CR2_RXNEIE ((uint32_t)0x00000040) /*!< RX buffer Not Empty Interrupt Enable */ |
bogdanm | 86:04dd9b1680ae | 6098 | #define SPI_CR2_TXEIE ((uint32_t)0x00000080) /*!< Tx buffer Empty Interrupt Enable */ |
bogdanm | 86:04dd9b1680ae | 6099 | #define SPI_CR2_DS ((uint32_t)0x00000F00) /*!< DS[3:0] Data Size */ |
bogdanm | 86:04dd9b1680ae | 6100 | #define SPI_CR2_DS_0 ((uint32_t)0x00000100) /*!< Bit 0 */ |
bogdanm | 86:04dd9b1680ae | 6101 | #define SPI_CR2_DS_1 ((uint32_t)0x00000200) /*!< Bit 1 */ |
bogdanm | 86:04dd9b1680ae | 6102 | #define SPI_CR2_DS_2 ((uint32_t)0x00000400) /*!< Bit 2 */ |
bogdanm | 86:04dd9b1680ae | 6103 | #define SPI_CR2_DS_3 ((uint32_t)0x00000800) /*!< Bit 3 */ |
bogdanm | 86:04dd9b1680ae | 6104 | #define SPI_CR2_FRXTH ((uint32_t)0x00001000) /*!< FIFO reception Threshold */ |
bogdanm | 86:04dd9b1680ae | 6105 | #define SPI_CR2_LDMARX ((uint32_t)0x00002000) /*!< Last DMA transfer for reception */ |
bogdanm | 86:04dd9b1680ae | 6106 | #define SPI_CR2_LDMATX ((uint32_t)0x00004000) /*!< Last DMA transfer for transmission */ |
bogdanm | 86:04dd9b1680ae | 6107 | |
bogdanm | 86:04dd9b1680ae | 6108 | /******************** Bit definition for SPI_SR register ********************/ |
bogdanm | 86:04dd9b1680ae | 6109 | #define SPI_SR_RXNE ((uint32_t)0x00000001) /*!< Receive buffer Not Empty */ |
bogdanm | 86:04dd9b1680ae | 6110 | #define SPI_SR_TXE ((uint32_t)0x00000002) /*!< Transmit buffer Empty */ |
bogdanm | 86:04dd9b1680ae | 6111 | #define SPI_SR_CHSIDE ((uint32_t)0x00000004) /*!< Channel side */ |
bogdanm | 86:04dd9b1680ae | 6112 | #define SPI_SR_UDR ((uint32_t)0x00000008) /*!< Underrun flag */ |
bogdanm | 86:04dd9b1680ae | 6113 | #define SPI_SR_CRCERR ((uint32_t)0x00000010) /*!< CRC Error flag */ |
bogdanm | 86:04dd9b1680ae | 6114 | #define SPI_SR_MODF ((uint32_t)0x00000020) /*!< Mode fault */ |
bogdanm | 86:04dd9b1680ae | 6115 | #define SPI_SR_OVR ((uint32_t)0x00000040) /*!< Overrun flag */ |
bogdanm | 86:04dd9b1680ae | 6116 | #define SPI_SR_BSY ((uint32_t)0x00000080) /*!< Busy flag */ |
bogdanm | 86:04dd9b1680ae | 6117 | #define SPI_SR_FRE ((uint32_t)0x00000100) /*!< TI frame format error */ |
bogdanm | 86:04dd9b1680ae | 6118 | #define SPI_SR_FRLVL ((uint32_t)0x00000600) /*!< FIFO Reception Level */ |
bogdanm | 86:04dd9b1680ae | 6119 | #define SPI_SR_FRLVL_0 ((uint32_t)0x00000200) /*!< Bit 0 */ |
bogdanm | 86:04dd9b1680ae | 6120 | #define SPI_SR_FRLVL_1 ((uint32_t)0x00000400) /*!< Bit 1 */ |
bogdanm | 86:04dd9b1680ae | 6121 | #define SPI_SR_FTLVL ((uint32_t)0x00001800) /*!< FIFO Transmission Level */ |
bogdanm | 86:04dd9b1680ae | 6122 | #define SPI_SR_FTLVL_0 ((uint32_t)0x00000800) /*!< Bit 0 */ |
bogdanm | 86:04dd9b1680ae | 6123 | #define SPI_SR_FTLVL_1 ((uint32_t)0x00001000) /*!< Bit 1 */ |
bogdanm | 86:04dd9b1680ae | 6124 | |
bogdanm | 86:04dd9b1680ae | 6125 | /******************** Bit definition for SPI_DR register ********************/ |
bogdanm | 86:04dd9b1680ae | 6126 | #define SPI_DR_DR ((uint32_t)0x0000FFFF) /*!< Data Register */ |
bogdanm | 86:04dd9b1680ae | 6127 | |
bogdanm | 86:04dd9b1680ae | 6128 | /******************* Bit definition for SPI_CRCPR register ******************/ |
bogdanm | 86:04dd9b1680ae | 6129 | #define SPI_CRCPR_CRCPOLY ((uint32_t)0x0000FFFF) /*!< CRC polynomial register */ |
bogdanm | 86:04dd9b1680ae | 6130 | |
bogdanm | 86:04dd9b1680ae | 6131 | /****************** Bit definition for SPI_RXCRCR register ******************/ |
bogdanm | 86:04dd9b1680ae | 6132 | #define SPI_RXCRCR_RXCRC ((uint32_t)0x0000FFFF) /*!< Rx CRC Register */ |
bogdanm | 86:04dd9b1680ae | 6133 | |
bogdanm | 86:04dd9b1680ae | 6134 | /****************** Bit definition for SPI_TXCRCR register ******************/ |
bogdanm | 86:04dd9b1680ae | 6135 | #define SPI_TXCRCR_TXCRC ((uint32_t)0x0000FFFF) /*!< Tx CRC Register */ |
bogdanm | 86:04dd9b1680ae | 6136 | |
bogdanm | 86:04dd9b1680ae | 6137 | /******************************************************************************/ |
bogdanm | 86:04dd9b1680ae | 6138 | /* */ |
bogdanm | 86:04dd9b1680ae | 6139 | /* System Configuration(SYSCFG) */ |
bogdanm | 86:04dd9b1680ae | 6140 | /* */ |
bogdanm | 86:04dd9b1680ae | 6141 | /******************************************************************************/ |
bogdanm | 86:04dd9b1680ae | 6142 | /***************** Bit definition for SYSCFG_CFGR1 register *****************/ |
bogdanm | 86:04dd9b1680ae | 6143 | #define SYSCFG_CFGR1_MEM_MODE ((uint32_t)0x00000003) /*!< SYSCFG_Memory Remap Config */ |
bogdanm | 86:04dd9b1680ae | 6144 | #define SYSCFG_CFGR1_MEM_MODE_0 ((uint32_t)0x00000001) /*!< Bit 0 */ |
bogdanm | 86:04dd9b1680ae | 6145 | #define SYSCFG_CFGR1_MEM_MODE_1 ((uint32_t)0x00000002) /*!< Bit 1 */ |
bogdanm | 86:04dd9b1680ae | 6146 | #define SYSCFG_CFGR1_TIM1_ITR3_RMP ((uint32_t)0x00000040) /*!< Timer 1 ITR3 selection */ |
bogdanm | 86:04dd9b1680ae | 6147 | #define SYSCFG_CFGR1_DAC1_TRIG1_RMP ((uint32_t)0x00000080) /*!< DAC1 Trigger1 remap */ |
bogdanm | 86:04dd9b1680ae | 6148 | #define SYSCFG_CFGR1_DMA_RMP ((uint32_t)0x0000F800) /*!< DMA remap mask */ |
bogdanm | 86:04dd9b1680ae | 6149 | #define SYSCFG_CFGR1_TIM16_DMA_RMP ((uint32_t)0x00000800) /*!< Timer 16 DMA remap */ |
bogdanm | 86:04dd9b1680ae | 6150 | #define SYSCFG_CFGR1_TIM17_DMA_RMP ((uint32_t)0x00001000) /*!< Timer 17 DMA remap */ |
bogdanm | 86:04dd9b1680ae | 6151 | #define SYSCFG_CFGR1_TIM6DAC1Ch1_DMA_RMP ((uint32_t)0x00002000) /*!< Timer 6 / DAC1 CH1 DMA remap */ |
bogdanm | 86:04dd9b1680ae | 6152 | #define SYSCFG_CFGR1_TIM7DAC1Ch2_DMA_RMP ((uint32_t)0x00004000) /*!< Timer 7 / DAC1 CH2 DMA remap */ |
bogdanm | 86:04dd9b1680ae | 6153 | #define SYSCFG_CFGR1_DAC2Ch1_DMA_RMP ((uint32_t)0x00008000) /*!< DAC2 CH1 DMA remap */ |
bogdanm | 86:04dd9b1680ae | 6154 | #define SYSCFG_CFGR1_I2C_PB6_FMP ((uint32_t)0x00010000) /*!< I2C PB6 Fast mode plus */ |
bogdanm | 86:04dd9b1680ae | 6155 | #define SYSCFG_CFGR1_I2C_PB7_FMP ((uint32_t)0x00020000) /*!< I2C PB7 Fast mode plus */ |
bogdanm | 86:04dd9b1680ae | 6156 | #define SYSCFG_CFGR1_I2C_PB8_FMP ((uint32_t)0x00040000) /*!< I2C PB8 Fast mode plus */ |
bogdanm | 86:04dd9b1680ae | 6157 | #define SYSCFG_CFGR1_I2C_PB9_FMP ((uint32_t)0x00080000) /*!< I2C PB9 Fast mode plus */ |
bogdanm | 86:04dd9b1680ae | 6158 | #define SYSCFG_CFGR1_I2C1_FMP ((uint32_t)0x00100000) /*!< I2C1 Fast mode plus */ |
bogdanm | 86:04dd9b1680ae | 6159 | #define SYSCFG_CFGR1_ENCODER_MODE ((uint32_t)0x00C00000) /*!< Encoder Mode */ |
bogdanm | 86:04dd9b1680ae | 6160 | #define SYSCFG_CFGR1_ENCODER_MODE_0 ((uint32_t)0x00400000) /*!< Encoder Mode 0 */ |
bogdanm | 86:04dd9b1680ae | 6161 | #define SYSCFG_CFGR1_ENCODER_MODE_1 ((uint32_t)0x00800000) /*!< Encoder Mode 1 */ |
bogdanm | 86:04dd9b1680ae | 6162 | #define SYSCFG_CFGR1_FPU_IE ((uint32_t)0xFC000000) /*!< Floating Point Unit Interrupt Enable */ |
bogdanm | 86:04dd9b1680ae | 6163 | #define SYSCFG_CFGR1_FPU_IE_0 ((uint32_t)0x04000000) /*!< Floating Point Unit Interrupt Enable 0 */ |
bogdanm | 86:04dd9b1680ae | 6164 | #define SYSCFG_CFGR1_FPU_IE_1 ((uint32_t)0x08000000) /*!< Floating Point Unit Interrupt Enable 1 */ |
bogdanm | 86:04dd9b1680ae | 6165 | #define SYSCFG_CFGR1_FPU_IE_2 ((uint32_t)0x10000000) /*!< Floating Point Unit Interrupt Enable 2 */ |
bogdanm | 86:04dd9b1680ae | 6166 | #define SYSCFG_CFGR1_FPU_IE_3 ((uint32_t)0x20000000) /*!< Floating Point Unit Interrupt Enable 3 */ |
bogdanm | 86:04dd9b1680ae | 6167 | #define SYSCFG_CFGR1_FPU_IE_4 ((uint32_t)0x40000000) /*!< Floating Point Unit Interrupt Enable 4 */ |
bogdanm | 86:04dd9b1680ae | 6168 | #define SYSCFG_CFGR1_FPU_IE_5 ((uint32_t)0x80000000) /*!< Floating Point Unit Interrupt Enable 5 */ |
bogdanm | 86:04dd9b1680ae | 6169 | |
bogdanm | 86:04dd9b1680ae | 6170 | /***************** Bit definition for SYSCFG_RCR register *******************/ |
bogdanm | 86:04dd9b1680ae | 6171 | #define SYSCFG_RCR_PAGE0 ((uint32_t)0x00000001) /*!< ICODE SRAM Write protection page 0 */ |
bogdanm | 86:04dd9b1680ae | 6172 | #define SYSCFG_RCR_PAGE1 ((uint32_t)0x00000002) /*!< ICODE SRAM Write protection page 1 */ |
bogdanm | 86:04dd9b1680ae | 6173 | #define SYSCFG_RCR_PAGE2 ((uint32_t)0x00000004) /*!< ICODE SRAM Write protection page 2 */ |
bogdanm | 86:04dd9b1680ae | 6174 | #define SYSCFG_RCR_PAGE3 ((uint32_t)0x00000008) /*!< ICODE SRAM Write protection page 3 */ |
bogdanm | 86:04dd9b1680ae | 6175 | |
bogdanm | 86:04dd9b1680ae | 6176 | /***************** Bit definition for SYSCFG_EXTICR1 register ***************/ |
bogdanm | 86:04dd9b1680ae | 6177 | #define SYSCFG_EXTICR1_EXTI0 ((uint32_t)0x0000000F) /*!< EXTI 0 configuration */ |
bogdanm | 86:04dd9b1680ae | 6178 | #define SYSCFG_EXTICR1_EXTI1 ((uint32_t)0x000000F0) /*!< EXTI 1 configuration */ |
bogdanm | 86:04dd9b1680ae | 6179 | #define SYSCFG_EXTICR1_EXTI2 ((uint32_t)0x00000F00) /*!< EXTI 2 configuration */ |
bogdanm | 86:04dd9b1680ae | 6180 | #define SYSCFG_EXTICR1_EXTI3 ((uint32_t)0x0000F000) /*!< EXTI 3 configuration */ |
bogdanm | 86:04dd9b1680ae | 6181 | |
bogdanm | 86:04dd9b1680ae | 6182 | /*!<* |
bogdanm | 86:04dd9b1680ae | 6183 | * @brief EXTI0 configuration |
bogdanm | 86:04dd9b1680ae | 6184 | */ |
bogdanm | 86:04dd9b1680ae | 6185 | #define SYSCFG_EXTICR1_EXTI0_PA ((uint32_t)0x00000000) /*!< PA[0] pin */ |
bogdanm | 86:04dd9b1680ae | 6186 | #define SYSCFG_EXTICR1_EXTI0_PB ((uint32_t)0x00000001) /*!< PB[0] pin */ |
bogdanm | 86:04dd9b1680ae | 6187 | #define SYSCFG_EXTICR1_EXTI0_PC ((uint32_t)0x00000002) /*!< PC[0] pin */ |
bogdanm | 86:04dd9b1680ae | 6188 | #define SYSCFG_EXTICR1_EXTI0_PD ((uint32_t)0x00000003) /*!< PD[0] pin */ |
bogdanm | 86:04dd9b1680ae | 6189 | #define SYSCFG_EXTICR1_EXTI0_PE ((uint32_t)0x00000004) /*!< PE[0] pin */ |
bogdanm | 86:04dd9b1680ae | 6190 | #define SYSCFG_EXTICR1_EXTI0_PF ((uint32_t)0x00000005) /*!< PF[0] pin */ |
bogdanm | 86:04dd9b1680ae | 6191 | |
bogdanm | 86:04dd9b1680ae | 6192 | /*!<* |
bogdanm | 86:04dd9b1680ae | 6193 | * @brief EXTI1 configuration |
bogdanm | 86:04dd9b1680ae | 6194 | */ |
bogdanm | 86:04dd9b1680ae | 6195 | #define SYSCFG_EXTICR1_EXTI1_PA ((uint32_t)0x00000000) /*!< PA[1] pin */ |
bogdanm | 86:04dd9b1680ae | 6196 | #define SYSCFG_EXTICR1_EXTI1_PB ((uint32_t)0x00000010) /*!< PB[1] pin */ |
bogdanm | 86:04dd9b1680ae | 6197 | #define SYSCFG_EXTICR1_EXTI1_PC ((uint32_t)0x00000020) /*!< PC[1] pin */ |
bogdanm | 86:04dd9b1680ae | 6198 | #define SYSCFG_EXTICR1_EXTI1_PD ((uint32_t)0x00000030) /*!< PD[1] pin */ |
bogdanm | 86:04dd9b1680ae | 6199 | #define SYSCFG_EXTICR1_EXTI1_PE ((uint32_t)0x00000040) /*!< PE[1] pin */ |
bogdanm | 86:04dd9b1680ae | 6200 | #define SYSCFG_EXTICR1_EXTI1_PF ((uint32_t)0x00000050) /*!< PF[1] pin */ |
bogdanm | 86:04dd9b1680ae | 6201 | |
bogdanm | 86:04dd9b1680ae | 6202 | /*!<* |
bogdanm | 86:04dd9b1680ae | 6203 | * @brief EXTI2 configuration |
bogdanm | 86:04dd9b1680ae | 6204 | */ |
bogdanm | 86:04dd9b1680ae | 6205 | #define SYSCFG_EXTICR1_EXTI2_PA ((uint32_t)0x00000000) /*!< PA[2] pin */ |
bogdanm | 86:04dd9b1680ae | 6206 | #define SYSCFG_EXTICR1_EXTI2_PB ((uint32_t)0x00000100) /*!< PB[2] pin */ |
bogdanm | 86:04dd9b1680ae | 6207 | #define SYSCFG_EXTICR1_EXTI2_PC ((uint32_t)0x00000200) /*!< PC[2] pin */ |
bogdanm | 86:04dd9b1680ae | 6208 | #define SYSCFG_EXTICR1_EXTI2_PD ((uint32_t)0x00000300) /*!< PD[2] pin */ |
bogdanm | 86:04dd9b1680ae | 6209 | #define SYSCFG_EXTICR1_EXTI2_PE ((uint32_t)0x00000400) /*!< PE[2] pin */ |
bogdanm | 86:04dd9b1680ae | 6210 | #define SYSCFG_EXTICR1_EXTI2_PF ((uint32_t)0x00000500) /*!< PF[2] pin */ |
bogdanm | 86:04dd9b1680ae | 6211 | |
bogdanm | 86:04dd9b1680ae | 6212 | /*!<* |
bogdanm | 86:04dd9b1680ae | 6213 | * @brief EXTI3 configuration |
bogdanm | 86:04dd9b1680ae | 6214 | */ |
bogdanm | 86:04dd9b1680ae | 6215 | #define SYSCFG_EXTICR1_EXTI3_PA ((uint32_t)0x00000000) /*!< PA[3] pin */ |
bogdanm | 86:04dd9b1680ae | 6216 | #define SYSCFG_EXTICR1_EXTI3_PB ((uint32_t)0x00001000) /*!< PB[3] pin */ |
bogdanm | 86:04dd9b1680ae | 6217 | #define SYSCFG_EXTICR1_EXTI3_PC ((uint32_t)0x00002000) /*!< PC[3] pin */ |
bogdanm | 86:04dd9b1680ae | 6218 | #define SYSCFG_EXTICR1_EXTI3_PD ((uint32_t)0x00003000) /*!< PD[3] pin */ |
bogdanm | 86:04dd9b1680ae | 6219 | #define SYSCFG_EXTICR1_EXTI3_PE ((uint32_t)0x00004000) /*!< PE[3] pin */ |
bogdanm | 86:04dd9b1680ae | 6220 | |
bogdanm | 86:04dd9b1680ae | 6221 | /***************** Bit definition for SYSCFG_EXTICR2 register ***************/ |
bogdanm | 86:04dd9b1680ae | 6222 | #define SYSCFG_EXTICR2_EXTI4 ((uint32_t)0x0000000F) /*!< EXTI 4 configuration */ |
bogdanm | 86:04dd9b1680ae | 6223 | #define SYSCFG_EXTICR2_EXTI5 ((uint32_t)0x000000F0) /*!< EXTI 5 configuration */ |
bogdanm | 86:04dd9b1680ae | 6224 | #define SYSCFG_EXTICR2_EXTI6 ((uint32_t)0x00000F00) /*!< EXTI 6 configuration */ |
bogdanm | 86:04dd9b1680ae | 6225 | #define SYSCFG_EXTICR2_EXTI7 ((uint32_t)0x0000F000) /*!< EXTI 7 configuration */ |
bogdanm | 86:04dd9b1680ae | 6226 | |
bogdanm | 86:04dd9b1680ae | 6227 | /*!<* |
bogdanm | 86:04dd9b1680ae | 6228 | * @brief EXTI4 configuration |
bogdanm | 86:04dd9b1680ae | 6229 | */ |
bogdanm | 86:04dd9b1680ae | 6230 | #define SYSCFG_EXTICR2_EXTI4_PA ((uint32_t)0x00000000) /*!< PA[4] pin */ |
bogdanm | 86:04dd9b1680ae | 6231 | #define SYSCFG_EXTICR2_EXTI4_PB ((uint32_t)0x00000001) /*!< PB[4] pin */ |
bogdanm | 86:04dd9b1680ae | 6232 | #define SYSCFG_EXTICR2_EXTI4_PC ((uint32_t)0x00000002) /*!< PC[4] pin */ |
bogdanm | 86:04dd9b1680ae | 6233 | #define SYSCFG_EXTICR2_EXTI4_PD ((uint32_t)0x00000003) /*!< PD[4] pin */ |
bogdanm | 86:04dd9b1680ae | 6234 | #define SYSCFG_EXTICR2_EXTI4_PE ((uint32_t)0x00000004) /*!< PE[4] pin */ |
bogdanm | 86:04dd9b1680ae | 6235 | #define SYSCFG_EXTICR2_EXTI4_PF ((uint32_t)0x00000005) /*!< PF[4] pin */ |
bogdanm | 86:04dd9b1680ae | 6236 | |
bogdanm | 86:04dd9b1680ae | 6237 | /*!<* |
bogdanm | 86:04dd9b1680ae | 6238 | * @brief EXTI5 configuration |
bogdanm | 86:04dd9b1680ae | 6239 | */ |
bogdanm | 86:04dd9b1680ae | 6240 | #define SYSCFG_EXTICR2_EXTI5_PA ((uint32_t)0x00000000) /*!< PA[5] pin */ |
bogdanm | 86:04dd9b1680ae | 6241 | #define SYSCFG_EXTICR2_EXTI5_PB ((uint32_t)0x00000010) /*!< PB[5] pin */ |
bogdanm | 86:04dd9b1680ae | 6242 | #define SYSCFG_EXTICR2_EXTI5_PC ((uint32_t)0x00000020) /*!< PC[5] pin */ |
bogdanm | 86:04dd9b1680ae | 6243 | #define SYSCFG_EXTICR2_EXTI5_PD ((uint32_t)0x00000030) /*!< PD[5] pin */ |
bogdanm | 86:04dd9b1680ae | 6244 | #define SYSCFG_EXTICR2_EXTI5_PE ((uint32_t)0x00000040) /*!< PE[5] pin */ |
bogdanm | 86:04dd9b1680ae | 6245 | #define SYSCFG_EXTICR2_EXTI5_PF ((uint32_t)0x00000050) /*!< PF[5] pin */ |
bogdanm | 86:04dd9b1680ae | 6246 | |
bogdanm | 86:04dd9b1680ae | 6247 | /*!<* |
bogdanm | 86:04dd9b1680ae | 6248 | * @brief EXTI6 configuration |
bogdanm | 86:04dd9b1680ae | 6249 | */ |
bogdanm | 86:04dd9b1680ae | 6250 | #define SYSCFG_EXTICR2_EXTI6_PA ((uint32_t)0x00000000) /*!< PA[6] pin */ |
bogdanm | 86:04dd9b1680ae | 6251 | #define SYSCFG_EXTICR2_EXTI6_PB ((uint32_t)0x00000100) /*!< PB[6] pin */ |
bogdanm | 86:04dd9b1680ae | 6252 | #define SYSCFG_EXTICR2_EXTI6_PC ((uint32_t)0x00000200) /*!< PC[6] pin */ |
bogdanm | 86:04dd9b1680ae | 6253 | #define SYSCFG_EXTICR2_EXTI6_PD ((uint32_t)0x00000300) /*!< PD[6] pin */ |
bogdanm | 86:04dd9b1680ae | 6254 | #define SYSCFG_EXTICR2_EXTI6_PE ((uint32_t)0x00000400) /*!< PE[6] pin */ |
bogdanm | 86:04dd9b1680ae | 6255 | #define SYSCFG_EXTICR2_EXTI6_PF ((uint32_t)0x00000500) /*!< PF[6] pin */ |
bogdanm | 86:04dd9b1680ae | 6256 | |
bogdanm | 86:04dd9b1680ae | 6257 | /*!<* |
bogdanm | 86:04dd9b1680ae | 6258 | * @brief EXTI7 configuration |
bogdanm | 86:04dd9b1680ae | 6259 | */ |
bogdanm | 86:04dd9b1680ae | 6260 | #define SYSCFG_EXTICR2_EXTI7_PA ((uint32_t)0x00000000) /*!< PA[7] pin */ |
bogdanm | 86:04dd9b1680ae | 6261 | #define SYSCFG_EXTICR2_EXTI7_PB ((uint32_t)0x00001000) /*!< PB[7] pin */ |
bogdanm | 86:04dd9b1680ae | 6262 | #define SYSCFG_EXTICR2_EXTI7_PC ((uint32_t)0x00002000) /*!< PC[7] pin */ |
bogdanm | 86:04dd9b1680ae | 6263 | #define SYSCFG_EXTICR2_EXTI7_PD ((uint32_t)0x00003000) /*!< PD[7] pin */ |
bogdanm | 86:04dd9b1680ae | 6264 | #define SYSCFG_EXTICR2_EXTI7_PE ((uint32_t)0x00004000) /*!< PE[7] pin */ |
bogdanm | 86:04dd9b1680ae | 6265 | |
bogdanm | 86:04dd9b1680ae | 6266 | /***************** Bit definition for SYSCFG_EXTICR3 register ***************/ |
bogdanm | 86:04dd9b1680ae | 6267 | #define SYSCFG_EXTICR3_EXTI8 ((uint32_t)0x0000000F) /*!< EXTI 8 configuration */ |
bogdanm | 86:04dd9b1680ae | 6268 | #define SYSCFG_EXTICR3_EXTI9 ((uint32_t)0x000000F0) /*!< EXTI 9 configuration */ |
bogdanm | 86:04dd9b1680ae | 6269 | #define SYSCFG_EXTICR3_EXTI10 ((uint32_t)0x00000F00) /*!< EXTI 10 configuration */ |
bogdanm | 86:04dd9b1680ae | 6270 | #define SYSCFG_EXTICR3_EXTI11 ((uint32_t)0x0000F000) /*!< EXTI 11 configuration */ |
bogdanm | 86:04dd9b1680ae | 6271 | |
bogdanm | 86:04dd9b1680ae | 6272 | /*!<* |
bogdanm | 86:04dd9b1680ae | 6273 | * @brief EXTI8 configuration |
bogdanm | 86:04dd9b1680ae | 6274 | */ |
bogdanm | 86:04dd9b1680ae | 6275 | #define SYSCFG_EXTICR3_EXTI8_PA ((uint32_t)0x00000000) /*!< PA[8] pin */ |
bogdanm | 86:04dd9b1680ae | 6276 | #define SYSCFG_EXTICR3_EXTI8_PB ((uint32_t)0x00000001) /*!< PB[8] pin */ |
bogdanm | 86:04dd9b1680ae | 6277 | #define SYSCFG_EXTICR3_EXTI8_PC ((uint32_t)0x00000002) /*!< PC[8] pin */ |
bogdanm | 86:04dd9b1680ae | 6278 | #define SYSCFG_EXTICR3_EXTI8_PD ((uint32_t)0x00000003) /*!< PD[8] pin */ |
bogdanm | 86:04dd9b1680ae | 6279 | #define SYSCFG_EXTICR3_EXTI8_PE ((uint32_t)0x00000004) /*!< PE[8] pin */ |
bogdanm | 86:04dd9b1680ae | 6280 | |
bogdanm | 86:04dd9b1680ae | 6281 | /*!<* |
bogdanm | 86:04dd9b1680ae | 6282 | * @brief EXTI9 configuration |
bogdanm | 86:04dd9b1680ae | 6283 | */ |
bogdanm | 86:04dd9b1680ae | 6284 | #define SYSCFG_EXTICR3_EXTI9_PA ((uint32_t)0x00000000) /*!< PA[9] pin */ |
bogdanm | 86:04dd9b1680ae | 6285 | #define SYSCFG_EXTICR3_EXTI9_PB ((uint32_t)0x00000010) /*!< PB[9] pin */ |
bogdanm | 86:04dd9b1680ae | 6286 | #define SYSCFG_EXTICR3_EXTI9_PC ((uint32_t)0x00000020) /*!< PC[9] pin */ |
bogdanm | 86:04dd9b1680ae | 6287 | #define SYSCFG_EXTICR3_EXTI9_PD ((uint32_t)0x00000030) /*!< PD[9] pin */ |
bogdanm | 86:04dd9b1680ae | 6288 | #define SYSCFG_EXTICR3_EXTI9_PE ((uint32_t)0x00000040) /*!< PE[9] pin */ |
bogdanm | 86:04dd9b1680ae | 6289 | #define SYSCFG_EXTICR3_EXTI9_PF ((uint32_t)0x00000050) /*!< PF[9] pin */ |
bogdanm | 86:04dd9b1680ae | 6290 | |
bogdanm | 86:04dd9b1680ae | 6291 | /*!<* |
bogdanm | 86:04dd9b1680ae | 6292 | * @brief EXTI10 configuration |
bogdanm | 86:04dd9b1680ae | 6293 | */ |
bogdanm | 86:04dd9b1680ae | 6294 | #define SYSCFG_EXTICR3_EXTI10_PA ((uint32_t)0x00000000) /*!< PA[10] pin */ |
bogdanm | 86:04dd9b1680ae | 6295 | #define SYSCFG_EXTICR3_EXTI10_PB ((uint32_t)0x00000100) /*!< PB[10] pin */ |
bogdanm | 86:04dd9b1680ae | 6296 | #define SYSCFG_EXTICR3_EXTI10_PC ((uint32_t)0x00000200) /*!< PC[10] pin */ |
bogdanm | 86:04dd9b1680ae | 6297 | #define SYSCFG_EXTICR3_EXTI10_PD ((uint32_t)0x00000300) /*!< PD[10] pin */ |
bogdanm | 86:04dd9b1680ae | 6298 | #define SYSCFG_EXTICR3_EXTI10_PE ((uint32_t)0x00000400) /*!< PE[10] pin */ |
bogdanm | 86:04dd9b1680ae | 6299 | #define SYSCFG_EXTICR3_EXTI10_PF ((uint32_t)0x00000500) /*!< PF[10] pin */ |
bogdanm | 86:04dd9b1680ae | 6300 | |
bogdanm | 86:04dd9b1680ae | 6301 | /*!<* |
bogdanm | 86:04dd9b1680ae | 6302 | * @brief EXTI11 configuration |
bogdanm | 86:04dd9b1680ae | 6303 | */ |
bogdanm | 86:04dd9b1680ae | 6304 | #define SYSCFG_EXTICR3_EXTI11_PA ((uint32_t)0x00000000) /*!< PA[11] pin */ |
bogdanm | 86:04dd9b1680ae | 6305 | #define SYSCFG_EXTICR3_EXTI11_PB ((uint32_t)0x00001000) /*!< PB[11] pin */ |
bogdanm | 86:04dd9b1680ae | 6306 | #define SYSCFG_EXTICR3_EXTI11_PC ((uint32_t)0x00002000) /*!< PC[11] pin */ |
bogdanm | 86:04dd9b1680ae | 6307 | #define SYSCFG_EXTICR3_EXTI11_PD ((uint32_t)0x00003000) /*!< PD[11] pin */ |
bogdanm | 86:04dd9b1680ae | 6308 | #define SYSCFG_EXTICR3_EXTI11_PE ((uint32_t)0x00004000) /*!< PE[11] pin */ |
bogdanm | 86:04dd9b1680ae | 6309 | |
bogdanm | 86:04dd9b1680ae | 6310 | /***************** Bit definition for SYSCFG_EXTICR4 register *****************/ |
bogdanm | 86:04dd9b1680ae | 6311 | #define SYSCFG_EXTICR4_EXTI12 ((uint32_t)0x0000000F) /*!< EXTI 12 configuration */ |
bogdanm | 86:04dd9b1680ae | 6312 | #define SYSCFG_EXTICR4_EXTI13 ((uint32_t)0x000000F0) /*!< EXTI 13 configuration */ |
bogdanm | 86:04dd9b1680ae | 6313 | #define SYSCFG_EXTICR4_EXTI14 ((uint32_t)0x00000F00) /*!< EXTI 14 configuration */ |
bogdanm | 86:04dd9b1680ae | 6314 | #define SYSCFG_EXTICR4_EXTI15 ((uint32_t)0x0000F000) /*!< EXTI 15 configuration */ |
bogdanm | 86:04dd9b1680ae | 6315 | |
bogdanm | 86:04dd9b1680ae | 6316 | /*!<* |
bogdanm | 86:04dd9b1680ae | 6317 | * @brief EXTI12 configuration |
bogdanm | 86:04dd9b1680ae | 6318 | */ |
bogdanm | 86:04dd9b1680ae | 6319 | #define SYSCFG_EXTICR4_EXTI12_PA ((uint32_t)0x00000000) /*!< PA[12] pin */ |
bogdanm | 86:04dd9b1680ae | 6320 | #define SYSCFG_EXTICR4_EXTI12_PB ((uint32_t)0x00000001) /*!< PB[12] pin */ |
bogdanm | 86:04dd9b1680ae | 6321 | #define SYSCFG_EXTICR4_EXTI12_PC ((uint32_t)0x00000002) /*!< PC[12] pin */ |
bogdanm | 86:04dd9b1680ae | 6322 | #define SYSCFG_EXTICR4_EXTI12_PD ((uint32_t)0x00000003) /*!< PD[12] pin */ |
bogdanm | 86:04dd9b1680ae | 6323 | #define SYSCFG_EXTICR4_EXTI12_PE ((uint32_t)0x00000004) /*!< PE[12] pin */ |
bogdanm | 86:04dd9b1680ae | 6324 | |
bogdanm | 86:04dd9b1680ae | 6325 | /*!<* |
bogdanm | 86:04dd9b1680ae | 6326 | * @brief EXTI13 configuration |
bogdanm | 86:04dd9b1680ae | 6327 | */ |
bogdanm | 86:04dd9b1680ae | 6328 | #define SYSCFG_EXTICR4_EXTI13_PA ((uint32_t)0x00000000) /*!< PA[13] pin */ |
bogdanm | 86:04dd9b1680ae | 6329 | #define SYSCFG_EXTICR4_EXTI13_PB ((uint32_t)0x00000010) /*!< PB[13] pin */ |
bogdanm | 86:04dd9b1680ae | 6330 | #define SYSCFG_EXTICR4_EXTI13_PC ((uint32_t)0x00000020) /*!< PC[13] pin */ |
bogdanm | 86:04dd9b1680ae | 6331 | #define SYSCFG_EXTICR4_EXTI13_PD ((uint32_t)0x00000030) /*!< PD[13] pin */ |
bogdanm | 86:04dd9b1680ae | 6332 | #define SYSCFG_EXTICR4_EXTI13_PE ((uint32_t)0x00000040) /*!< PE[13] pin */ |
bogdanm | 86:04dd9b1680ae | 6333 | |
bogdanm | 86:04dd9b1680ae | 6334 | /*!<* |
bogdanm | 86:04dd9b1680ae | 6335 | * @brief EXTI14 configuration |
bogdanm | 86:04dd9b1680ae | 6336 | */ |
bogdanm | 86:04dd9b1680ae | 6337 | #define SYSCFG_EXTICR4_EXTI14_PA ((uint32_t)0x00000000) /*!< PA[14] pin */ |
bogdanm | 86:04dd9b1680ae | 6338 | #define SYSCFG_EXTICR4_EXTI14_PB ((uint32_t)0x00000100) /*!< PB[14] pin */ |
bogdanm | 86:04dd9b1680ae | 6339 | #define SYSCFG_EXTICR4_EXTI14_PC ((uint32_t)0x00000200) /*!< PC[14] pin */ |
bogdanm | 86:04dd9b1680ae | 6340 | #define SYSCFG_EXTICR4_EXTI14_PD ((uint32_t)0x00000300) /*!< PD[14] pin */ |
bogdanm | 86:04dd9b1680ae | 6341 | #define SYSCFG_EXTICR4_EXTI14_PE ((uint32_t)0x00000400) /*!< PE[14] pin */ |
bogdanm | 86:04dd9b1680ae | 6342 | |
bogdanm | 86:04dd9b1680ae | 6343 | /*!<* |
bogdanm | 86:04dd9b1680ae | 6344 | * @brief EXTI15 configuration |
bogdanm | 86:04dd9b1680ae | 6345 | */ |
bogdanm | 86:04dd9b1680ae | 6346 | #define SYSCFG_EXTICR4_EXTI15_PA ((uint32_t)0x00000000) /*!< PA[15] pin */ |
bogdanm | 86:04dd9b1680ae | 6347 | #define SYSCFG_EXTICR4_EXTI15_PB ((uint32_t)0x00001000) /*!< PB[15] pin */ |
bogdanm | 86:04dd9b1680ae | 6348 | #define SYSCFG_EXTICR4_EXTI15_PC ((uint32_t)0x00002000) /*!< PC[15] pin */ |
bogdanm | 86:04dd9b1680ae | 6349 | #define SYSCFG_EXTICR4_EXTI15_PD ((uint32_t)0x00003000) /*!< PD[15] pin */ |
bogdanm | 86:04dd9b1680ae | 6350 | #define SYSCFG_EXTICR4_EXTI15_PE ((uint32_t)0x00004000) /*!< PE[15] pin */ |
bogdanm | 86:04dd9b1680ae | 6351 | |
bogdanm | 86:04dd9b1680ae | 6352 | /***************** Bit definition for SYSCFG_CFGR2 register *****************/ |
bogdanm | 86:04dd9b1680ae | 6353 | #define SYSCFG_CFGR2_LOCKUP_LOCK ((uint32_t)0x00000001) /*!< Enables and locks the LOCKUP (Hardfault) output of CortexM4 with Break Input of TIM1/15/16/17 */ |
bogdanm | 86:04dd9b1680ae | 6354 | #define SYSCFG_CFGR2_SRAM_PARITY_LOCK ((uint32_t)0x00000002) /*!< Enables and locks the SRAM_PARITY error signal with Break Input of TIM1/15/16/17 */ |
bogdanm | 86:04dd9b1680ae | 6355 | #define SYSCFG_CFGR2_PVD_LOCK ((uint32_t)0x00000004) /*!< Enables and locks the PVD connection with TIM1/15/16/17 Break Input, as well as the PVDE and PLS[2:0] in the PWR_CR register */ |
bogdanm | 86:04dd9b1680ae | 6356 | #define SYSCFG_CFGR2_BYP_ADDR_PAR ((uint32_t)0x00000010) /*!< Disables the adddress parity check on RAM */ |
bogdanm | 86:04dd9b1680ae | 6357 | #define SYSCFG_CFGR2_SRAM_PE ((uint32_t)0x00000100) /*!< SRAM Parity error flag */ |
bogdanm | 86:04dd9b1680ae | 6358 | |
bogdanm | 86:04dd9b1680ae | 6359 | /***************** Bit definition for SYSCFG_CFGR3 register *****************/ |
bogdanm | 86:04dd9b1680ae | 6360 | #define SYSCFG_CFGR3_DMA_RMP ((uint32_t)0x000003FF) /*!< DMA remap mask */ |
bogdanm | 86:04dd9b1680ae | 6361 | #define SYSCFG_CFGR3_SPI1_RX_DMA_RMP ((uint32_t)0x00000003) /*!< SPI1 RX DMA remap */ |
bogdanm | 86:04dd9b1680ae | 6362 | #define SYSCFG_CFGR3_SPI1_RX_DMA_RMP_0 ((uint32_t)0x00000001) /*!< SPI1 RX DMA remap bit 0 */ |
bogdanm | 86:04dd9b1680ae | 6363 | #define SYSCFG_CFGR3_SPI1_RX_DMA_RMP_1 ((uint32_t)0x00000002) /*!< SPI1 RX DMA remap bit 1 */ |
bogdanm | 86:04dd9b1680ae | 6364 | #define SYSCFG_CFGR3_SPI1_TX_DMA_RMP ((uint32_t)0x0000000C) /*!< SPI1 TX DMA remap */ |
bogdanm | 86:04dd9b1680ae | 6365 | #define SYSCFG_CFGR3_SPI1_TX_DMA_RMP_0 ((uint32_t)0x00000004) /*!< SPI1 TX DMA remap bit 0 */ |
bogdanm | 86:04dd9b1680ae | 6366 | #define SYSCFG_CFGR3_SPI1_TX_DMA_RMP_1 ((uint32_t)0x00000008) /*!< SPI1 TX DMA remap bit 1 */ |
bogdanm | 86:04dd9b1680ae | 6367 | #define SYSCFG_CFGR3_I2C1_RX_DMA_RMP ((uint32_t)0x00000030) /*!< I2C1 RX DMA remap */ |
bogdanm | 86:04dd9b1680ae | 6368 | #define SYSCFG_CFGR3_I2C1_RX_DMA_RMP_0 ((uint32_t)0x00000010) /*!< I2C1 RX DMA remap bit 0 */ |
bogdanm | 86:04dd9b1680ae | 6369 | #define SYSCFG_CFGR3_I2C1_RX_DMA_RMP_1 ((uint32_t)0x00000020) /*!< I2C1 RX DMA remap bit 1 */ |
bogdanm | 86:04dd9b1680ae | 6370 | #define SYSCFG_CFGR3_I2C1_TX_DMA_RMP ((uint32_t)0x000000C0) /*!< I2C1 RX DMA remap */ |
bogdanm | 86:04dd9b1680ae | 6371 | #define SYSCFG_CFGR3_I2C1_TX_DMA_RMP_0 ((uint32_t)0x00000040) /*!< I2C1 TX DMA remap bit 0 */ |
bogdanm | 86:04dd9b1680ae | 6372 | #define SYSCFG_CFGR3_I2C1_TX_DMA_RMP_1 ((uint32_t)0x00000080) /*!< I2C1 TX DMA remap bit 1 */ |
bogdanm | 86:04dd9b1680ae | 6373 | #define SYSCFG_CFGR3_ADC2_DMA_RMP ((uint32_t)0x00000300) /*!< ADC2 DMA remap */ |
bogdanm | 86:04dd9b1680ae | 6374 | #define SYSCFG_CFGR3_ADC2_DMA_RMP_0 ((uint32_t)0x00000100) /*!< ADC2 DMA remap bit 0 */ |
bogdanm | 86:04dd9b1680ae | 6375 | #define SYSCFG_CFGR3_ADC2_DMA_RMP_1 ((uint32_t)0x00000200) /*!< ADC2 DMA remap bit 1 */ |
bogdanm | 86:04dd9b1680ae | 6376 | #define SYSCFG_CFGR3_TRIGGER_RMP ((uint32_t)0x00030000) /*!< Trigger remap mask */ |
bogdanm | 86:04dd9b1680ae | 6377 | #define SYSCFG_CFGR3_DAC1_TRG3_RMP ((uint32_t)0x00010000) /*!< DAC1 TRG3 remap */ |
bogdanm | 86:04dd9b1680ae | 6378 | #define SYSCFG_CFGR3_DAC1_TRG5_RMP ((uint32_t)0x00020000) /*!< DAC1 TRG5 remap */ |
bogdanm | 86:04dd9b1680ae | 6379 | |
bogdanm | 86:04dd9b1680ae | 6380 | /******************************************************************************/ |
bogdanm | 86:04dd9b1680ae | 6381 | /* */ |
bogdanm | 86:04dd9b1680ae | 6382 | /* TIM */ |
bogdanm | 86:04dd9b1680ae | 6383 | /* */ |
bogdanm | 86:04dd9b1680ae | 6384 | /******************************************************************************/ |
bogdanm | 86:04dd9b1680ae | 6385 | /******************* Bit definition for TIM_CR1 register ********************/ |
bogdanm | 86:04dd9b1680ae | 6386 | #define TIM_CR1_CEN ((uint32_t)0x00000001) /*!<Counter enable */ |
bogdanm | 86:04dd9b1680ae | 6387 | #define TIM_CR1_UDIS ((uint32_t)0x00000002) /*!<Update disable */ |
bogdanm | 86:04dd9b1680ae | 6388 | #define TIM_CR1_URS ((uint32_t)0x00000004) /*!<Update request source */ |
bogdanm | 86:04dd9b1680ae | 6389 | #define TIM_CR1_OPM ((uint32_t)0x00000008) /*!<One pulse mode */ |
bogdanm | 86:04dd9b1680ae | 6390 | #define TIM_CR1_DIR ((uint32_t)0x00000010) /*!<Direction */ |
bogdanm | 86:04dd9b1680ae | 6391 | |
bogdanm | 86:04dd9b1680ae | 6392 | #define TIM_CR1_CMS ((uint32_t)0x00000060) /*!<CMS[1:0] bits (Center-aligned mode selection) */ |
bogdanm | 86:04dd9b1680ae | 6393 | #define TIM_CR1_CMS_0 ((uint32_t)0x00000020) /*!<Bit 0 */ |
bogdanm | 86:04dd9b1680ae | 6394 | #define TIM_CR1_CMS_1 ((uint32_t)0x00000040) /*!<Bit 1 */ |
bogdanm | 86:04dd9b1680ae | 6395 | |
bogdanm | 86:04dd9b1680ae | 6396 | #define TIM_CR1_ARPE ((uint32_t)0x00000080) /*!<Auto-reload preload enable */ |
bogdanm | 86:04dd9b1680ae | 6397 | |
bogdanm | 86:04dd9b1680ae | 6398 | #define TIM_CR1_CKD ((uint32_t)0x00000300) /*!<CKD[1:0] bits (clock division) */ |
bogdanm | 86:04dd9b1680ae | 6399 | #define TIM_CR1_CKD_0 ((uint32_t)0x00000100) /*!<Bit 0 */ |
bogdanm | 86:04dd9b1680ae | 6400 | #define TIM_CR1_CKD_1 ((uint32_t)0x00000200) /*!<Bit 1 */ |
bogdanm | 86:04dd9b1680ae | 6401 | |
bogdanm | 86:04dd9b1680ae | 6402 | #define TIM_CR1_UIFREMAP ((uint32_t)0x00000800) /*!<Update interrupt flag remap */ |
bogdanm | 86:04dd9b1680ae | 6403 | |
bogdanm | 86:04dd9b1680ae | 6404 | /******************* Bit definition for TIM_CR2 register ********************/ |
bogdanm | 86:04dd9b1680ae | 6405 | #define TIM_CR2_CCPC ((uint32_t)0x00000001) /*!<Capture/Compare Preloaded Control */ |
bogdanm | 86:04dd9b1680ae | 6406 | #define TIM_CR2_CCUS ((uint32_t)0x00000004) /*!<Capture/Compare Control Update Selection */ |
bogdanm | 86:04dd9b1680ae | 6407 | #define TIM_CR2_CCDS ((uint32_t)0x00000008) /*!<Capture/Compare DMA Selection */ |
bogdanm | 86:04dd9b1680ae | 6408 | |
bogdanm | 86:04dd9b1680ae | 6409 | #define TIM_CR2_MMS ((uint32_t)0x00000070) /*!<MMS[2:0] bits (Master Mode Selection) */ |
bogdanm | 86:04dd9b1680ae | 6410 | #define TIM_CR2_MMS_0 ((uint32_t)0x00000010) /*!<Bit 0 */ |
bogdanm | 86:04dd9b1680ae | 6411 | #define TIM_CR2_MMS_1 ((uint32_t)0x00000020) /*!<Bit 1 */ |
bogdanm | 86:04dd9b1680ae | 6412 | #define TIM_CR2_MMS_2 ((uint32_t)0x00000040) /*!<Bit 2 */ |
bogdanm | 86:04dd9b1680ae | 6413 | |
bogdanm | 86:04dd9b1680ae | 6414 | #define TIM_CR2_TI1S ((uint32_t)0x00000080) /*!<TI1 Selection */ |
bogdanm | 86:04dd9b1680ae | 6415 | #define TIM_CR2_OIS1 ((uint32_t)0x00000100) /*!<Output Idle state 1 (OC1 output) */ |
bogdanm | 86:04dd9b1680ae | 6416 | #define TIM_CR2_OIS1N ((uint32_t)0x00000200) /*!<Output Idle state 1 (OC1N output) */ |
bogdanm | 86:04dd9b1680ae | 6417 | #define TIM_CR2_OIS2 ((uint32_t)0x00000400) /*!<Output Idle state 2 (OC2 output) */ |
bogdanm | 86:04dd9b1680ae | 6418 | #define TIM_CR2_OIS2N ((uint32_t)0x00000800) /*!<Output Idle state 2 (OC2N output) */ |
bogdanm | 86:04dd9b1680ae | 6419 | #define TIM_CR2_OIS3 ((uint32_t)0x00001000) /*!<Output Idle state 3 (OC3 output) */ |
bogdanm | 86:04dd9b1680ae | 6420 | #define TIM_CR2_OIS3N ((uint32_t)0x00002000) /*!<Output Idle state 3 (OC3N output) */ |
bogdanm | 86:04dd9b1680ae | 6421 | #define TIM_CR2_OIS4 ((uint32_t)0x00004000) /*!<Output Idle state 4 (OC4 output) */ |
bogdanm | 86:04dd9b1680ae | 6422 | #define TIM_CR2_OIS5 ((uint32_t)0x00010000) /*!<Output Idle state 4 (OC4 output) */ |
bogdanm | 86:04dd9b1680ae | 6423 | #define TIM_CR2_OIS6 ((uint32_t)0x00040000) /*!<Output Idle state 4 (OC4 output) */ |
bogdanm | 86:04dd9b1680ae | 6424 | |
bogdanm | 86:04dd9b1680ae | 6425 | #define TIM_CR2_MMS2 ((uint32_t)0x00F00000) /*!<MMS[2:0] bits (Master Mode Selection) */ |
bogdanm | 86:04dd9b1680ae | 6426 | #define TIM_CR2_MMS2_0 ((uint32_t)0x00100000) /*!<Bit 0 */ |
bogdanm | 86:04dd9b1680ae | 6427 | #define TIM_CR2_MMS2_1 ((uint32_t)0x00200000) /*!<Bit 1 */ |
bogdanm | 86:04dd9b1680ae | 6428 | #define TIM_CR2_MMS2_2 ((uint32_t)0x00400000) /*!<Bit 2 */ |
bogdanm | 86:04dd9b1680ae | 6429 | #define TIM_CR2_MMS2_3 ((uint32_t)0x00800000) /*!<Bit 2 */ |
bogdanm | 86:04dd9b1680ae | 6430 | |
bogdanm | 86:04dd9b1680ae | 6431 | /******************* Bit definition for TIM_SMCR register *******************/ |
bogdanm | 86:04dd9b1680ae | 6432 | #define TIM_SMCR_SMS ((uint32_t)0x00010007) /*!<SMS[2:0] bits (Slave mode selection) */ |
bogdanm | 86:04dd9b1680ae | 6433 | #define TIM_SMCR_SMS_0 ((uint32_t)0x00000001) /*!<Bit 0 */ |
bogdanm | 86:04dd9b1680ae | 6434 | #define TIM_SMCR_SMS_1 ((uint32_t)0x00000002) /*!<Bit 1 */ |
bogdanm | 86:04dd9b1680ae | 6435 | #define TIM_SMCR_SMS_2 ((uint32_t)0x00000004) /*!<Bit 2 */ |
bogdanm | 86:04dd9b1680ae | 6436 | #define TIM_SMCR_SMS_3 ((uint32_t)0x00010000) /*!<Bit 3 */ |
bogdanm | 86:04dd9b1680ae | 6437 | |
bogdanm | 86:04dd9b1680ae | 6438 | #define TIM_SMCR_OCCS ((uint32_t)0x00000008) /*!< OCREF clear selection */ |
bogdanm | 86:04dd9b1680ae | 6439 | |
bogdanm | 86:04dd9b1680ae | 6440 | #define TIM_SMCR_TS ((uint32_t)0x00000070) /*!<TS[2:0] bits (Trigger selection) */ |
bogdanm | 86:04dd9b1680ae | 6441 | #define TIM_SMCR_TS_0 ((uint32_t)0x00000010) /*!<Bit 0 */ |
bogdanm | 86:04dd9b1680ae | 6442 | #define TIM_SMCR_TS_1 ((uint32_t)0x00000020) /*!<Bit 1 */ |
bogdanm | 86:04dd9b1680ae | 6443 | #define TIM_SMCR_TS_2 ((uint32_t)0x00000040) /*!<Bit 2 */ |
bogdanm | 86:04dd9b1680ae | 6444 | |
bogdanm | 86:04dd9b1680ae | 6445 | #define TIM_SMCR_MSM ((uint32_t)0x00000080) /*!<Master/slave mode */ |
bogdanm | 86:04dd9b1680ae | 6446 | |
bogdanm | 86:04dd9b1680ae | 6447 | #define TIM_SMCR_ETF ((uint32_t)0x00000F00) /*!<ETF[3:0] bits (External trigger filter) */ |
bogdanm | 86:04dd9b1680ae | 6448 | #define TIM_SMCR_ETF_0 ((uint32_t)0x00000100) /*!<Bit 0 */ |
bogdanm | 86:04dd9b1680ae | 6449 | #define TIM_SMCR_ETF_1 ((uint32_t)0x00000200) /*!<Bit 1 */ |
bogdanm | 86:04dd9b1680ae | 6450 | #define TIM_SMCR_ETF_2 ((uint32_t)0x00000400) /*!<Bit 2 */ |
bogdanm | 86:04dd9b1680ae | 6451 | #define TIM_SMCR_ETF_3 ((uint32_t)0x00000800) /*!<Bit 3 */ |
bogdanm | 86:04dd9b1680ae | 6452 | |
bogdanm | 86:04dd9b1680ae | 6453 | #define TIM_SMCR_ETPS ((uint32_t)0x00003000) /*!<ETPS[1:0] bits (External trigger prescaler) */ |
bogdanm | 86:04dd9b1680ae | 6454 | #define TIM_SMCR_ETPS_0 ((uint32_t)0x00001000) /*!<Bit 0 */ |
bogdanm | 86:04dd9b1680ae | 6455 | #define TIM_SMCR_ETPS_1 ((uint32_t)0x00002000) /*!<Bit 1 */ |
bogdanm | 86:04dd9b1680ae | 6456 | |
bogdanm | 86:04dd9b1680ae | 6457 | #define TIM_SMCR_ECE ((uint32_t)0x00004000) /*!<External clock enable */ |
bogdanm | 86:04dd9b1680ae | 6458 | #define TIM_SMCR_ETP ((uint32_t)0x00008000) /*!<External trigger polarity */ |
bogdanm | 86:04dd9b1680ae | 6459 | |
bogdanm | 86:04dd9b1680ae | 6460 | /******************* Bit definition for TIM_DIER register *******************/ |
bogdanm | 86:04dd9b1680ae | 6461 | #define TIM_DIER_UIE ((uint32_t)0x00000001) /*!<Update interrupt enable */ |
bogdanm | 86:04dd9b1680ae | 6462 | #define TIM_DIER_CC1IE ((uint32_t)0x00000002) /*!<Capture/Compare 1 interrupt enable */ |
bogdanm | 86:04dd9b1680ae | 6463 | #define TIM_DIER_CC2IE ((uint32_t)0x00000004) /*!<Capture/Compare 2 interrupt enable */ |
bogdanm | 86:04dd9b1680ae | 6464 | #define TIM_DIER_CC3IE ((uint32_t)0x00000008) /*!<Capture/Compare 3 interrupt enable */ |
bogdanm | 86:04dd9b1680ae | 6465 | #define TIM_DIER_CC4IE ((uint32_t)0x00000010) /*!<Capture/Compare 4 interrupt enable */ |
bogdanm | 86:04dd9b1680ae | 6466 | #define TIM_DIER_COMIE ((uint32_t)0x00000020) /*!<COM interrupt enable */ |
bogdanm | 86:04dd9b1680ae | 6467 | #define TIM_DIER_TIE ((uint32_t)0x00000040) /*!<Trigger interrupt enable */ |
bogdanm | 86:04dd9b1680ae | 6468 | #define TIM_DIER_BIE ((uint32_t)0x00000080) /*!<Break interrupt enable */ |
bogdanm | 86:04dd9b1680ae | 6469 | #define TIM_DIER_UDE ((uint32_t)0x00000100) /*!<Update DMA request enable */ |
bogdanm | 86:04dd9b1680ae | 6470 | #define TIM_DIER_CC1DE ((uint32_t)0x00000200) /*!<Capture/Compare 1 DMA request enable */ |
bogdanm | 86:04dd9b1680ae | 6471 | #define TIM_DIER_CC2DE ((uint32_t)0x00000400) /*!<Capture/Compare 2 DMA request enable */ |
bogdanm | 86:04dd9b1680ae | 6472 | #define TIM_DIER_CC3DE ((uint32_t)0x00000800) /*!<Capture/Compare 3 DMA request enable */ |
bogdanm | 86:04dd9b1680ae | 6473 | #define TIM_DIER_CC4DE ((uint32_t)0x00001000) /*!<Capture/Compare 4 DMA request enable */ |
bogdanm | 86:04dd9b1680ae | 6474 | #define TIM_DIER_COMDE ((uint32_t)0x00002000) /*!<COM DMA request enable */ |
bogdanm | 86:04dd9b1680ae | 6475 | #define TIM_DIER_TDE ((uint32_t)0x00004000) /*!<Trigger DMA request enable */ |
bogdanm | 86:04dd9b1680ae | 6476 | |
bogdanm | 86:04dd9b1680ae | 6477 | /******************** Bit definition for TIM_SR register ********************/ |
bogdanm | 86:04dd9b1680ae | 6478 | #define TIM_SR_UIF ((uint32_t)0x00000001) /*!<Update interrupt Flag */ |
bogdanm | 86:04dd9b1680ae | 6479 | #define TIM_SR_CC1IF ((uint32_t)0x00000002) /*!<Capture/Compare 1 interrupt Flag */ |
bogdanm | 86:04dd9b1680ae | 6480 | #define TIM_SR_CC2IF ((uint32_t)0x00000004) /*!<Capture/Compare 2 interrupt Flag */ |
bogdanm | 86:04dd9b1680ae | 6481 | #define TIM_SR_CC3IF ((uint32_t)0x00000008) /*!<Capture/Compare 3 interrupt Flag */ |
bogdanm | 86:04dd9b1680ae | 6482 | #define TIM_SR_CC4IF ((uint32_t)0x00000010) /*!<Capture/Compare 4 interrupt Flag */ |
bogdanm | 86:04dd9b1680ae | 6483 | #define TIM_SR_COMIF ((uint32_t)0x00000020) /*!<COM interrupt Flag */ |
bogdanm | 86:04dd9b1680ae | 6484 | #define TIM_SR_TIF ((uint32_t)0x00000040) /*!<Trigger interrupt Flag */ |
bogdanm | 86:04dd9b1680ae | 6485 | #define TIM_SR_BIF ((uint32_t)0x00000080) /*!<Break interrupt Flag */ |
bogdanm | 86:04dd9b1680ae | 6486 | #define TIM_SR_B2IF ((uint32_t)0x00000100) /*!<Break2 interrupt Flag */ |
bogdanm | 86:04dd9b1680ae | 6487 | #define TIM_SR_CC1OF ((uint32_t)0x00000200) /*!<Capture/Compare 1 Overcapture Flag */ |
bogdanm | 86:04dd9b1680ae | 6488 | #define TIM_SR_CC2OF ((uint32_t)0x00000400) /*!<Capture/Compare 2 Overcapture Flag */ |
bogdanm | 86:04dd9b1680ae | 6489 | #define TIM_SR_CC3OF ((uint32_t)0x00000800) /*!<Capture/Compare 3 Overcapture Flag */ |
bogdanm | 86:04dd9b1680ae | 6490 | #define TIM_SR_CC4OF ((uint32_t)0x00001000) /*!<Capture/Compare 4 Overcapture Flag */ |
bogdanm | 86:04dd9b1680ae | 6491 | #define TIM_SR_CC5IF ((uint32_t)0x00010000) /*!<Capture/Compare 5 interrupt Flag */ |
bogdanm | 86:04dd9b1680ae | 6492 | #define TIM_SR_CC6IF ((uint32_t)0x00020000) /*!<Capture/Compare 6 interrupt Flag */ |
bogdanm | 86:04dd9b1680ae | 6493 | |
bogdanm | 86:04dd9b1680ae | 6494 | /******************* Bit definition for TIM_EGR register ********************/ |
bogdanm | 86:04dd9b1680ae | 6495 | #define TIM_EGR_UG ((uint32_t)0x00000001) /*!<Update Generation */ |
bogdanm | 86:04dd9b1680ae | 6496 | #define TIM_EGR_CC1G ((uint32_t)0x00000002) /*!<Capture/Compare 1 Generation */ |
bogdanm | 86:04dd9b1680ae | 6497 | #define TIM_EGR_CC2G ((uint32_t)0x00000004) /*!<Capture/Compare 2 Generation */ |
bogdanm | 86:04dd9b1680ae | 6498 | #define TIM_EGR_CC3G ((uint32_t)0x00000008) /*!<Capture/Compare 3 Generation */ |
bogdanm | 86:04dd9b1680ae | 6499 | #define TIM_EGR_CC4G ((uint32_t)0x00000010) /*!<Capture/Compare 4 Generation */ |
bogdanm | 86:04dd9b1680ae | 6500 | #define TIM_EGR_COMG ((uint32_t)0x00000020) /*!<Capture/Compare Control Update Generation */ |
bogdanm | 86:04dd9b1680ae | 6501 | #define TIM_EGR_TG ((uint32_t)0x00000040) /*!<Trigger Generation */ |
bogdanm | 86:04dd9b1680ae | 6502 | #define TIM_EGR_BG ((uint32_t)0x00000080) /*!<Break Generation */ |
bogdanm | 86:04dd9b1680ae | 6503 | #define TIM_EGR_B2G ((uint32_t)0x00000100) /*!<Break Generation */ |
bogdanm | 86:04dd9b1680ae | 6504 | |
bogdanm | 86:04dd9b1680ae | 6505 | /****************** Bit definition for TIM_CCMR1 register *******************/ |
bogdanm | 86:04dd9b1680ae | 6506 | #define TIM_CCMR1_CC1S ((uint32_t)0x00000003) /*!<CC1S[1:0] bits (Capture/Compare 1 Selection) */ |
bogdanm | 86:04dd9b1680ae | 6507 | #define TIM_CCMR1_CC1S_0 ((uint32_t)0x00000001) /*!<Bit 0 */ |
bogdanm | 86:04dd9b1680ae | 6508 | #define TIM_CCMR1_CC1S_1 ((uint32_t)0x00000002) /*!<Bit 1 */ |
bogdanm | 86:04dd9b1680ae | 6509 | |
bogdanm | 86:04dd9b1680ae | 6510 | #define TIM_CCMR1_OC1FE ((uint32_t)0x00000004) /*!<Output Compare 1 Fast enable */ |
bogdanm | 86:04dd9b1680ae | 6511 | #define TIM_CCMR1_OC1PE ((uint32_t)0x00000008) /*!<Output Compare 1 Preload enable */ |
bogdanm | 86:04dd9b1680ae | 6512 | |
bogdanm | 86:04dd9b1680ae | 6513 | #define TIM_CCMR1_OC1M ((uint32_t)0x00010070) /*!<OC1M[2:0] bits (Output Compare 1 Mode) */ |
bogdanm | 86:04dd9b1680ae | 6514 | #define TIM_CCMR1_OC1M_0 ((uint32_t)0x00000010) /*!<Bit 0 */ |
bogdanm | 86:04dd9b1680ae | 6515 | #define TIM_CCMR1_OC1M_1 ((uint32_t)0x00000020) /*!<Bit 1 */ |
bogdanm | 86:04dd9b1680ae | 6516 | #define TIM_CCMR1_OC1M_2 ((uint32_t)0x00000040) /*!<Bit 2 */ |
bogdanm | 86:04dd9b1680ae | 6517 | #define TIM_CCMR1_OC1M_3 ((uint32_t)0x00010000) /*!<Bit 3 */ |
bogdanm | 86:04dd9b1680ae | 6518 | |
bogdanm | 86:04dd9b1680ae | 6519 | #define TIM_CCMR1_OC1CE ((uint32_t)0x00000080) /*!<Output Compare 1Clear Enable */ |
bogdanm | 86:04dd9b1680ae | 6520 | |
bogdanm | 86:04dd9b1680ae | 6521 | #define TIM_CCMR1_CC2S ((uint32_t)0x00000300) /*!<CC2S[1:0] bits (Capture/Compare 2 Selection) */ |
bogdanm | 86:04dd9b1680ae | 6522 | #define TIM_CCMR1_CC2S_0 ((uint32_t)0x00000100) /*!<Bit 0 */ |
bogdanm | 86:04dd9b1680ae | 6523 | #define TIM_CCMR1_CC2S_1 ((uint32_t)0x00000200) /*!<Bit 1 */ |
bogdanm | 86:04dd9b1680ae | 6524 | |
bogdanm | 86:04dd9b1680ae | 6525 | #define TIM_CCMR1_OC2FE ((uint32_t)0x00000400) /*!<Output Compare 2 Fast enable */ |
bogdanm | 86:04dd9b1680ae | 6526 | #define TIM_CCMR1_OC2PE ((uint32_t)0x00000800) /*!<Output Compare 2 Preload enable */ |
bogdanm | 86:04dd9b1680ae | 6527 | |
bogdanm | 86:04dd9b1680ae | 6528 | #define TIM_CCMR1_OC2M ((uint32_t)0x01007000) /*!<OC2M[2:0] bits (Output Compare 2 Mode) */ |
bogdanm | 86:04dd9b1680ae | 6529 | #define TIM_CCMR1_OC2M_0 ((uint32_t)0x00001000) /*!<Bit 0 */ |
bogdanm | 86:04dd9b1680ae | 6530 | #define TIM_CCMR1_OC2M_1 ((uint32_t)0x00002000) /*!<Bit 1 */ |
bogdanm | 86:04dd9b1680ae | 6531 | #define TIM_CCMR1_OC2M_2 ((uint32_t)0x00004000) /*!<Bit 2 */ |
bogdanm | 86:04dd9b1680ae | 6532 | #define TIM_CCMR1_OC2M_3 ((uint32_t)0x01000000) /*!<Bit 3 */ |
bogdanm | 86:04dd9b1680ae | 6533 | |
bogdanm | 86:04dd9b1680ae | 6534 | #define TIM_CCMR1_OC2CE ((uint32_t)0x00008000) /*!<Output Compare 2 Clear Enable */ |
bogdanm | 86:04dd9b1680ae | 6535 | |
bogdanm | 86:04dd9b1680ae | 6536 | /*----------------------------------------------------------------------------*/ |
bogdanm | 86:04dd9b1680ae | 6537 | |
bogdanm | 86:04dd9b1680ae | 6538 | #define TIM_CCMR1_IC1PSC ((uint32_t)0x0000000C) /*!<IC1PSC[1:0] bits (Input Capture 1 Prescaler) */ |
bogdanm | 86:04dd9b1680ae | 6539 | #define TIM_CCMR1_IC1PSC_0 ((uint32_t)0x00000004) /*!<Bit 0 */ |
bogdanm | 86:04dd9b1680ae | 6540 | #define TIM_CCMR1_IC1PSC_1 ((uint32_t)0x00000008) /*!<Bit 1 */ |
bogdanm | 86:04dd9b1680ae | 6541 | |
bogdanm | 86:04dd9b1680ae | 6542 | #define TIM_CCMR1_IC1F ((uint32_t)0x000000F0) /*!<IC1F[3:0] bits (Input Capture 1 Filter) */ |
bogdanm | 86:04dd9b1680ae | 6543 | #define TIM_CCMR1_IC1F_0 ((uint32_t)0x00000010) /*!<Bit 0 */ |
bogdanm | 86:04dd9b1680ae | 6544 | #define TIM_CCMR1_IC1F_1 ((uint32_t)0x00000020) /*!<Bit 1 */ |
bogdanm | 86:04dd9b1680ae | 6545 | #define TIM_CCMR1_IC1F_2 ((uint32_t)0x00000040) /*!<Bit 2 */ |
bogdanm | 86:04dd9b1680ae | 6546 | #define TIM_CCMR1_IC1F_3 ((uint32_t)0x00000080) /*!<Bit 3 */ |
bogdanm | 86:04dd9b1680ae | 6547 | |
bogdanm | 86:04dd9b1680ae | 6548 | #define TIM_CCMR1_IC2PSC ((uint32_t)0x00000C00) /*!<IC2PSC[1:0] bits (Input Capture 2 Prescaler) */ |
bogdanm | 86:04dd9b1680ae | 6549 | #define TIM_CCMR1_IC2PSC_0 ((uint32_t)0x00000400) /*!<Bit 0 */ |
bogdanm | 86:04dd9b1680ae | 6550 | #define TIM_CCMR1_IC2PSC_1 ((uint32_t)0x00000800) /*!<Bit 1 */ |
bogdanm | 86:04dd9b1680ae | 6551 | |
bogdanm | 86:04dd9b1680ae | 6552 | #define TIM_CCMR1_IC2F ((uint32_t)0x0000F000) /*!<IC2F[3:0] bits (Input Capture 2 Filter) */ |
bogdanm | 86:04dd9b1680ae | 6553 | #define TIM_CCMR1_IC2F_0 ((uint32_t)0x00001000) /*!<Bit 0 */ |
bogdanm | 86:04dd9b1680ae | 6554 | #define TIM_CCMR1_IC2F_1 ((uint32_t)0x00002000) /*!<Bit 1 */ |
bogdanm | 86:04dd9b1680ae | 6555 | #define TIM_CCMR1_IC2F_2 ((uint32_t)0x00004000) /*!<Bit 2 */ |
bogdanm | 86:04dd9b1680ae | 6556 | #define TIM_CCMR1_IC2F_3 ((uint32_t)0x00008000) /*!<Bit 3 */ |
bogdanm | 86:04dd9b1680ae | 6557 | |
bogdanm | 86:04dd9b1680ae | 6558 | /****************** Bit definition for TIM_CCMR2 register *******************/ |
bogdanm | 86:04dd9b1680ae | 6559 | #define TIM_CCMR2_CC3S ((uint32_t)0x00000003) /*!<CC3S[1:0] bits (Capture/Compare 3 Selection) */ |
bogdanm | 86:04dd9b1680ae | 6560 | #define TIM_CCMR2_CC3S_0 ((uint32_t)0x00000001) /*!<Bit 0 */ |
bogdanm | 86:04dd9b1680ae | 6561 | #define TIM_CCMR2_CC3S_1 ((uint32_t)0x00000002) /*!<Bit 1 */ |
bogdanm | 86:04dd9b1680ae | 6562 | |
bogdanm | 86:04dd9b1680ae | 6563 | #define TIM_CCMR2_OC3FE ((uint32_t)0x00000004) /*!<Output Compare 3 Fast enable */ |
bogdanm | 86:04dd9b1680ae | 6564 | #define TIM_CCMR2_OC3PE ((uint32_t)0x00000008) /*!<Output Compare 3 Preload enable */ |
bogdanm | 86:04dd9b1680ae | 6565 | |
bogdanm | 86:04dd9b1680ae | 6566 | #define TIM_CCMR2_OC3M ((uint32_t)0x00010070) /*!<OC3M[2:0] bits (Output Compare 3 Mode) */ |
bogdanm | 86:04dd9b1680ae | 6567 | #define TIM_CCMR2_OC3M_0 ((uint32_t)0x00000010) /*!<Bit 0 */ |
bogdanm | 86:04dd9b1680ae | 6568 | #define TIM_CCMR2_OC3M_1 ((uint32_t)0x00000020) /*!<Bit 1 */ |
bogdanm | 86:04dd9b1680ae | 6569 | #define TIM_CCMR2_OC3M_2 ((uint32_t)0x00000040) /*!<Bit 2 */ |
bogdanm | 86:04dd9b1680ae | 6570 | #define TIM_CCMR2_OC3M_3 ((uint32_t)0x00010000) /*!<Bit 3 */ |
bogdanm | 86:04dd9b1680ae | 6571 | |
bogdanm | 86:04dd9b1680ae | 6572 | #define TIM_CCMR2_OC3CE ((uint32_t)0x00000080) /*!<Output Compare 3 Clear Enable */ |
bogdanm | 86:04dd9b1680ae | 6573 | |
bogdanm | 86:04dd9b1680ae | 6574 | #define TIM_CCMR2_CC4S ((uint32_t)0x00000300) /*!<CC4S[1:0] bits (Capture/Compare 4 Selection) */ |
bogdanm | 86:04dd9b1680ae | 6575 | #define TIM_CCMR2_CC4S_0 ((uint32_t)0x00000100) /*!<Bit 0 */ |
bogdanm | 86:04dd9b1680ae | 6576 | #define TIM_CCMR2_CC4S_1 ((uint32_t)0x00000200) /*!<Bit 1 */ |
bogdanm | 86:04dd9b1680ae | 6577 | |
bogdanm | 86:04dd9b1680ae | 6578 | #define TIM_CCMR2_OC4FE ((uint32_t)0x00000400) /*!<Output Compare 4 Fast enable */ |
bogdanm | 86:04dd9b1680ae | 6579 | #define TIM_CCMR2_OC4PE ((uint32_t)0x00000800) /*!<Output Compare 4 Preload enable */ |
bogdanm | 86:04dd9b1680ae | 6580 | |
bogdanm | 86:04dd9b1680ae | 6581 | #define TIM_CCMR2_OC4M ((uint32_t)0x01007000) /*!<OC4M[2:0] bits (Output Compare 4 Mode) */ |
bogdanm | 86:04dd9b1680ae | 6582 | #define TIM_CCMR2_OC4M_0 ((uint32_t)0x00001000) /*!<Bit 0 */ |
bogdanm | 86:04dd9b1680ae | 6583 | #define TIM_CCMR2_OC4M_1 ((uint32_t)0x00002000) /*!<Bit 1 */ |
bogdanm | 86:04dd9b1680ae | 6584 | #define TIM_CCMR2_OC4M_2 ((uint32_t)0x00004000) /*!<Bit 2 */ |
bogdanm | 86:04dd9b1680ae | 6585 | #define TIM_CCMR2_OC4M_3 ((uint32_t)0x01000000) /*!<Bit 3 */ |
bogdanm | 86:04dd9b1680ae | 6586 | |
bogdanm | 86:04dd9b1680ae | 6587 | #define TIM_CCMR2_OC4CE ((uint32_t)0x00008000) /*!<Output Compare 4 Clear Enable */ |
bogdanm | 86:04dd9b1680ae | 6588 | |
bogdanm | 86:04dd9b1680ae | 6589 | /*----------------------------------------------------------------------------*/ |
bogdanm | 86:04dd9b1680ae | 6590 | |
bogdanm | 86:04dd9b1680ae | 6591 | #define TIM_CCMR2_IC3PSC ((uint32_t)0x00000000000C) /*!<IC3PSC[1:0] bits (Input Capture 3 Prescaler) */ |
bogdanm | 86:04dd9b1680ae | 6592 | #define TIM_CCMR2_IC3PSC_0 ((uint32_t)0x000000000004) /*!<Bit 0 */ |
bogdanm | 86:04dd9b1680ae | 6593 | #define TIM_CCMR2_IC3PSC_1 ((uint32_t)0x000000000008) /*!<Bit 1 */ |
bogdanm | 86:04dd9b1680ae | 6594 | |
bogdanm | 86:04dd9b1680ae | 6595 | #define TIM_CCMR2_IC3F ((uint32_t)0x0000000000F0) /*!<IC3F[3:0] bits (Input Capture 3 Filter) */ |
bogdanm | 86:04dd9b1680ae | 6596 | #define TIM_CCMR2_IC3F_0 ((uint32_t)0x000000000010) /*!<Bit 0 */ |
bogdanm | 86:04dd9b1680ae | 6597 | #define TIM_CCMR2_IC3F_1 ((uint32_t)0x000000000020) /*!<Bit 1 */ |
bogdanm | 86:04dd9b1680ae | 6598 | #define TIM_CCMR2_IC3F_2 ((uint32_t)0x000000000040) /*!<Bit 2 */ |
bogdanm | 86:04dd9b1680ae | 6599 | #define TIM_CCMR2_IC3F_3 ((uint32_t)0x000000000080) /*!<Bit 3 */ |
bogdanm | 86:04dd9b1680ae | 6600 | |
bogdanm | 86:04dd9b1680ae | 6601 | #define TIM_CCMR2_IC4PSC ((uint32_t)0x000000000C00) /*!<IC4PSC[1:0] bits (Input Capture 4 Prescaler) */ |
bogdanm | 86:04dd9b1680ae | 6602 | #define TIM_CCMR2_IC4PSC_0 ((uint32_t)0x000000000400) /*!<Bit 0 */ |
bogdanm | 86:04dd9b1680ae | 6603 | #define TIM_CCMR2_IC4PSC_1 ((uint32_t)0x000000000800) /*!<Bit 1 */ |
bogdanm | 86:04dd9b1680ae | 6604 | |
bogdanm | 86:04dd9b1680ae | 6605 | #define TIM_CCMR2_IC4F ((uint32_t)0x00000000F000) /*!<IC4F[3:0] bits (Input Capture 4 Filter) */ |
bogdanm | 86:04dd9b1680ae | 6606 | #define TIM_CCMR2_IC4F_0 ((uint32_t)0x000000001000) /*!<Bit 0 */ |
bogdanm | 86:04dd9b1680ae | 6607 | #define TIM_CCMR2_IC4F_1 ((uint32_t)0x000000002000) /*!<Bit 1 */ |
bogdanm | 86:04dd9b1680ae | 6608 | #define TIM_CCMR2_IC4F_2 ((uint32_t)0x000000004000) /*!<Bit 2 */ |
bogdanm | 86:04dd9b1680ae | 6609 | #define TIM_CCMR2_IC4F_3 ((uint32_t)0x000000008000) /*!<Bit 3 */ |
bogdanm | 86:04dd9b1680ae | 6610 | |
bogdanm | 86:04dd9b1680ae | 6611 | /******************* Bit definition for TIM_CCER register *******************/ |
bogdanm | 86:04dd9b1680ae | 6612 | #define TIM_CCER_CC1E ((uint32_t)0x00000001) /*!<Capture/Compare 1 output enable */ |
bogdanm | 86:04dd9b1680ae | 6613 | #define TIM_CCER_CC1P ((uint32_t)0x00000002) /*!<Capture/Compare 1 output Polarity */ |
bogdanm | 86:04dd9b1680ae | 6614 | #define TIM_CCER_CC1NE ((uint32_t)0x00000004) /*!<Capture/Compare 1 Complementary output enable */ |
bogdanm | 86:04dd9b1680ae | 6615 | #define TIM_CCER_CC1NP ((uint32_t)0x00000008) /*!<Capture/Compare 1 Complementary output Polarity */ |
bogdanm | 86:04dd9b1680ae | 6616 | #define TIM_CCER_CC2E ((uint32_t)0x00000010) /*!<Capture/Compare 2 output enable */ |
bogdanm | 86:04dd9b1680ae | 6617 | #define TIM_CCER_CC2P ((uint32_t)0x00000020) /*!<Capture/Compare 2 output Polarity */ |
bogdanm | 86:04dd9b1680ae | 6618 | #define TIM_CCER_CC2NE ((uint32_t)0x00000040) /*!<Capture/Compare 2 Complementary output enable */ |
bogdanm | 86:04dd9b1680ae | 6619 | #define TIM_CCER_CC2NP ((uint32_t)0x00000080) /*!<Capture/Compare 2 Complementary output Polarity */ |
bogdanm | 86:04dd9b1680ae | 6620 | #define TIM_CCER_CC3E ((uint32_t)0x00000100) /*!<Capture/Compare 3 output enable */ |
bogdanm | 86:04dd9b1680ae | 6621 | #define TIM_CCER_CC3P ((uint32_t)0x00000200) /*!<Capture/Compare 3 output Polarity */ |
bogdanm | 86:04dd9b1680ae | 6622 | #define TIM_CCER_CC3NE ((uint32_t)0x00000400) /*!<Capture/Compare 3 Complementary output enable */ |
bogdanm | 86:04dd9b1680ae | 6623 | #define TIM_CCER_CC3NP ((uint32_t)0x00000800) /*!<Capture/Compare 3 Complementary output Polarity */ |
bogdanm | 86:04dd9b1680ae | 6624 | #define TIM_CCER_CC4E ((uint32_t)0x00001000) /*!<Capture/Compare 4 output enable */ |
bogdanm | 86:04dd9b1680ae | 6625 | #define TIM_CCER_CC4P ((uint32_t)0x00002000) /*!<Capture/Compare 4 output Polarity */ |
bogdanm | 86:04dd9b1680ae | 6626 | #define TIM_CCER_CC4NP ((uint32_t)0x00008000) /*!<Capture/Compare 4 Complementary output Polarity */ |
bogdanm | 86:04dd9b1680ae | 6627 | #define TIM_CCER_CC5E ((uint32_t)0x00010000) /*!<Capture/Compare 5 output enable */ |
bogdanm | 86:04dd9b1680ae | 6628 | #define TIM_CCER_CC5P ((uint32_t)0x00020000) /*!<Capture/Compare 5 output Polarity */ |
bogdanm | 86:04dd9b1680ae | 6629 | #define TIM_CCER_CC6E ((uint32_t)0x00100000) /*!<Capture/Compare 6 output enable */ |
bogdanm | 86:04dd9b1680ae | 6630 | #define TIM_CCER_CC6P ((uint32_t)0x00200000) /*!<Capture/Compare 6 output Polarity */ |
bogdanm | 86:04dd9b1680ae | 6631 | |
bogdanm | 86:04dd9b1680ae | 6632 | /******************* Bit definition for TIM_CNT register ********************/ |
bogdanm | 86:04dd9b1680ae | 6633 | #define TIM_CNT_CNT ((uint32_t)0xFFFFFFFF) /*!<Counter Value */ |
bogdanm | 86:04dd9b1680ae | 6634 | #define TIM_CNT_UIFCPY ((uint32_t)0x80000000) /*!<Update interrupt flag copy */ |
bogdanm | 86:04dd9b1680ae | 6635 | |
bogdanm | 86:04dd9b1680ae | 6636 | /******************* Bit definition for TIM_PSC register ********************/ |
bogdanm | 86:04dd9b1680ae | 6637 | #define TIM_PSC_PSC ((uint32_t)0x0000FFFF) /*!<Prescaler Value */ |
bogdanm | 86:04dd9b1680ae | 6638 | |
bogdanm | 86:04dd9b1680ae | 6639 | /******************* Bit definition for TIM_ARR register ********************/ |
bogdanm | 86:04dd9b1680ae | 6640 | #define TIM_ARR_ARR ((uint32_t)0xFFFFFFFF) /*!<actual auto-reload Value */ |
bogdanm | 86:04dd9b1680ae | 6641 | |
bogdanm | 86:04dd9b1680ae | 6642 | /******************* Bit definition for TIM_RCR register ********************/ |
bogdanm | 86:04dd9b1680ae | 6643 | #define TIM_RCR_REP ((uint32_t)0x000000FF) /*!<Repetition Counter Value */ |
bogdanm | 86:04dd9b1680ae | 6644 | |
bogdanm | 86:04dd9b1680ae | 6645 | /******************* Bit definition for TIM_CCR1 register *******************/ |
bogdanm | 86:04dd9b1680ae | 6646 | #define TIM_CCR1_CCR1 ((uint32_t)0x0000FFFF) /*!<Capture/Compare 1 Value */ |
bogdanm | 86:04dd9b1680ae | 6647 | |
bogdanm | 86:04dd9b1680ae | 6648 | /******************* Bit definition for TIM_CCR2 register *******************/ |
bogdanm | 86:04dd9b1680ae | 6649 | #define TIM_CCR2_CCR2 ((uint32_t)0x0000FFFF) /*!<Capture/Compare 2 Value */ |
bogdanm | 86:04dd9b1680ae | 6650 | |
bogdanm | 86:04dd9b1680ae | 6651 | /******************* Bit definition for TIM_CCR3 register *******************/ |
bogdanm | 86:04dd9b1680ae | 6652 | #define TIM_CCR3_CCR3 ((uint32_t)0x0000FFFF) /*!<Capture/Compare 3 Value */ |
bogdanm | 86:04dd9b1680ae | 6653 | |
bogdanm | 86:04dd9b1680ae | 6654 | /******************* Bit definition for TIM_CCR4 register *******************/ |
bogdanm | 86:04dd9b1680ae | 6655 | #define TIM_CCR4_CCR4 ((uint32_t)0x0000FFFF) /*!<Capture/Compare 4 Value */ |
bogdanm | 86:04dd9b1680ae | 6656 | |
bogdanm | 86:04dd9b1680ae | 6657 | /******************* Bit definition for TIM_CCR5 register *******************/ |
bogdanm | 86:04dd9b1680ae | 6658 | #define TIM_CCR5_CCR5 ((uint32_t)0xFFFFFFFF) /*!<Capture/Compare 5 Value */ |
bogdanm | 86:04dd9b1680ae | 6659 | #define TIM_CCR5_GC5C1 ((uint32_t)0x20000000) /*!<Group Channel 5 and Channel 1 */ |
bogdanm | 86:04dd9b1680ae | 6660 | #define TIM_CCR5_GC5C2 ((uint32_t)0x40000000) /*!<Group Channel 5 and Channel 2 */ |
bogdanm | 86:04dd9b1680ae | 6661 | #define TIM_CCR5_GC5C3 ((uint32_t)0x80000000) /*!<Group Channel 5 and Channel 3 */ |
bogdanm | 86:04dd9b1680ae | 6662 | |
bogdanm | 86:04dd9b1680ae | 6663 | /******************* Bit definition for TIM_CCR6 register *******************/ |
bogdanm | 86:04dd9b1680ae | 6664 | #define TIM_CCR6_CCR6 ((uint32_t)0x0000FFFF) /*!<Capture/Compare 6 Value */ |
bogdanm | 86:04dd9b1680ae | 6665 | |
bogdanm | 86:04dd9b1680ae | 6666 | /******************* Bit definition for TIM_BDTR register *******************/ |
bogdanm | 86:04dd9b1680ae | 6667 | #define TIM_BDTR_DTG ((uint32_t)0x000000FF) /*!<DTG[0:7] bits (Dead-Time Generator set-up) */ |
bogdanm | 86:04dd9b1680ae | 6668 | #define TIM_BDTR_DTG_0 ((uint32_t)0x00000001) /*!<Bit 0 */ |
bogdanm | 86:04dd9b1680ae | 6669 | #define TIM_BDTR_DTG_1 ((uint32_t)0x00000002) /*!<Bit 1 */ |
bogdanm | 86:04dd9b1680ae | 6670 | #define TIM_BDTR_DTG_2 ((uint32_t)0x00000004) /*!<Bit 2 */ |
bogdanm | 86:04dd9b1680ae | 6671 | #define TIM_BDTR_DTG_3 ((uint32_t)0x00000008) /*!<Bit 3 */ |
bogdanm | 86:04dd9b1680ae | 6672 | #define TIM_BDTR_DTG_4 ((uint32_t)0x00000010) /*!<Bit 4 */ |
bogdanm | 86:04dd9b1680ae | 6673 | #define TIM_BDTR_DTG_5 ((uint32_t)0x00000020) /*!<Bit 5 */ |
bogdanm | 86:04dd9b1680ae | 6674 | #define TIM_BDTR_DTG_6 ((uint32_t)0x00000040) /*!<Bit 6 */ |
bogdanm | 86:04dd9b1680ae | 6675 | #define TIM_BDTR_DTG_7 ((uint32_t)0x00000080) /*!<Bit 7 */ |
bogdanm | 86:04dd9b1680ae | 6676 | |
bogdanm | 86:04dd9b1680ae | 6677 | #define TIM_BDTR_LOCK ((uint32_t)0x00000300) /*!<LOCK[1:0] bits (Lock Configuration) */ |
bogdanm | 86:04dd9b1680ae | 6678 | #define TIM_BDTR_LOCK_0 ((uint32_t)0x00000100) /*!<Bit 0 */ |
bogdanm | 86:04dd9b1680ae | 6679 | #define TIM_BDTR_LOCK_1 ((uint32_t)0x00000200) /*!<Bit 1 */ |
bogdanm | 86:04dd9b1680ae | 6680 | |
bogdanm | 86:04dd9b1680ae | 6681 | #define TIM_BDTR_OSSI ((uint32_t)0x00000400) /*!<Off-State Selection for Idle mode */ |
bogdanm | 86:04dd9b1680ae | 6682 | #define TIM_BDTR_OSSR ((uint32_t)0x00000800) /*!<Off-State Selection for Run mode */ |
bogdanm | 86:04dd9b1680ae | 6683 | #define TIM_BDTR_BKE ((uint32_t)0x00001000) /*!<Break enable for Break1 */ |
bogdanm | 86:04dd9b1680ae | 6684 | #define TIM_BDTR_BKP ((uint32_t)0x00002000) /*!<Break Polarity for Break1 */ |
bogdanm | 86:04dd9b1680ae | 6685 | #define TIM_BDTR_AOE ((uint32_t)0x00004000) /*!<Automatic Output enable */ |
bogdanm | 86:04dd9b1680ae | 6686 | #define TIM_BDTR_MOE ((uint32_t)0x00008000) /*!<Main Output enable */ |
bogdanm | 86:04dd9b1680ae | 6687 | |
bogdanm | 86:04dd9b1680ae | 6688 | #define TIM_BDTR_BKF ((uint32_t)0x000F0000) /*!<Break Filter for Break1 */ |
bogdanm | 86:04dd9b1680ae | 6689 | #define TIM_BDTR_BK2F ((uint32_t)0x00F00000) /*!<Break Filter for Break2 */ |
bogdanm | 86:04dd9b1680ae | 6690 | |
bogdanm | 86:04dd9b1680ae | 6691 | #define TIM_BDTR_BK2E ((uint32_t)0x01000000) /*!<Break enable for Break2 */ |
bogdanm | 86:04dd9b1680ae | 6692 | #define TIM_BDTR_BK2P ((uint32_t)0x02000000) /*!<Break Polarity for Break2 */ |
bogdanm | 86:04dd9b1680ae | 6693 | |
bogdanm | 86:04dd9b1680ae | 6694 | /******************* Bit definition for TIM_DCR register ********************/ |
bogdanm | 86:04dd9b1680ae | 6695 | #define TIM_DCR_DBA ((uint32_t)0x0000001F) /*!<DBA[4:0] bits (DMA Base Address) */ |
bogdanm | 86:04dd9b1680ae | 6696 | #define TIM_DCR_DBA_0 ((uint32_t)0x00000001) /*!<Bit 0 */ |
bogdanm | 86:04dd9b1680ae | 6697 | #define TIM_DCR_DBA_1 ((uint32_t)0x00000002) /*!<Bit 1 */ |
bogdanm | 86:04dd9b1680ae | 6698 | #define TIM_DCR_DBA_2 ((uint32_t)0x00000004) /*!<Bit 2 */ |
bogdanm | 86:04dd9b1680ae | 6699 | #define TIM_DCR_DBA_3 ((uint32_t)0x00000008) /*!<Bit 3 */ |
bogdanm | 86:04dd9b1680ae | 6700 | #define TIM_DCR_DBA_4 ((uint32_t)0x00000010) /*!<Bit 4 */ |
bogdanm | 86:04dd9b1680ae | 6701 | |
bogdanm | 86:04dd9b1680ae | 6702 | #define TIM_DCR_DBL ((uint32_t)0x00001F00) /*!<DBL[4:0] bits (DMA Burst Length) */ |
bogdanm | 86:04dd9b1680ae | 6703 | #define TIM_DCR_DBL_0 ((uint32_t)0x00000100) /*!<Bit 0 */ |
bogdanm | 86:04dd9b1680ae | 6704 | #define TIM_DCR_DBL_1 ((uint32_t)0x00000200) /*!<Bit 1 */ |
bogdanm | 86:04dd9b1680ae | 6705 | #define TIM_DCR_DBL_2 ((uint32_t)0x00000400) /*!<Bit 2 */ |
bogdanm | 86:04dd9b1680ae | 6706 | #define TIM_DCR_DBL_3 ((uint32_t)0x00000800) /*!<Bit 3 */ |
bogdanm | 86:04dd9b1680ae | 6707 | #define TIM_DCR_DBL_4 ((uint32_t)0x00001000) /*!<Bit 4 */ |
bogdanm | 86:04dd9b1680ae | 6708 | |
bogdanm | 86:04dd9b1680ae | 6709 | /******************* Bit definition for TIM_DMAR register *******************/ |
bogdanm | 86:04dd9b1680ae | 6710 | #define TIM_DMAR_DMAB ((uint32_t)0x0000FFFF) /*!<DMA register for burst accesses */ |
bogdanm | 86:04dd9b1680ae | 6711 | |
bogdanm | 86:04dd9b1680ae | 6712 | /******************* Bit definition for TIM16_OR register *********************/ |
bogdanm | 86:04dd9b1680ae | 6713 | #define TIM16_OR_TI1_RMP ((uint32_t)0x000000C0) /*!<TI1_RMP[1:0] bits (TIM16 Input 1 remap) */ |
bogdanm | 86:04dd9b1680ae | 6714 | #define TIM16_OR_TI1_RMP_0 ((uint32_t)0x00000040) /*!<Bit 0 */ |
bogdanm | 86:04dd9b1680ae | 6715 | #define TIM16_OR_TI1_RMP_1 ((uint32_t)0x00000080) /*!<Bit 1 */ |
bogdanm | 86:04dd9b1680ae | 6716 | |
bogdanm | 86:04dd9b1680ae | 6717 | /******************* Bit definition for TIM1_OR register *********************/ |
bogdanm | 86:04dd9b1680ae | 6718 | #define TIM1_OR_ETR_RMP ((uint32_t)0x0000000F) /*!<ETR_RMP[3:0] bits (TIM1 ETR remap) */ |
bogdanm | 86:04dd9b1680ae | 6719 | #define TIM1_OR_ETR_RMP_0 ((uint32_t)0x00000001) /*!<Bit 0 */ |
bogdanm | 86:04dd9b1680ae | 6720 | #define TIM1_OR_ETR_RMP_1 ((uint32_t)0x00000002) /*!<Bit 1 */ |
bogdanm | 86:04dd9b1680ae | 6721 | #define TIM1_OR_ETR_RMP_2 ((uint32_t)0x00000004) /*!<Bit 2 */ |
bogdanm | 86:04dd9b1680ae | 6722 | #define TIM1_OR_ETR_RMP_3 ((uint32_t)0x00000008) /*!<Bit 3 */ |
bogdanm | 86:04dd9b1680ae | 6723 | |
bogdanm | 86:04dd9b1680ae | 6724 | /****************** Bit definition for TIM_CCMR3 register *******************/ |
bogdanm | 86:04dd9b1680ae | 6725 | #define TIM_CCMR3_OC5FE ((uint32_t)0x00000004) /*!<Output Compare 5 Fast enable */ |
bogdanm | 86:04dd9b1680ae | 6726 | #define TIM_CCMR3_OC5PE ((uint32_t)0x00000008) /*!<Output Compare 5 Preload enable */ |
bogdanm | 86:04dd9b1680ae | 6727 | |
bogdanm | 86:04dd9b1680ae | 6728 | #define TIM_CCMR3_OC5M ((uint32_t)0x00010070) /*!<OC5M[2:0] bits (Output Compare 5 Mode) */ |
bogdanm | 86:04dd9b1680ae | 6729 | #define TIM_CCMR3_OC5M_0 ((uint32_t)0x00000010) /*!<Bit 0 */ |
bogdanm | 86:04dd9b1680ae | 6730 | #define TIM_CCMR3_OC5M_1 ((uint32_t)0x00000020) /*!<Bit 1 */ |
bogdanm | 86:04dd9b1680ae | 6731 | #define TIM_CCMR3_OC5M_2 ((uint32_t)0x00000040) /*!<Bit 2 */ |
bogdanm | 86:04dd9b1680ae | 6732 | #define TIM_CCMR3_OC5M_3 ((uint32_t)0x00010000) /*!<Bit 3 */ |
bogdanm | 86:04dd9b1680ae | 6733 | |
bogdanm | 86:04dd9b1680ae | 6734 | #define TIM_CCMR3_OC5CE ((uint32_t)0x00000080) /*!<Output Compare 5 Clear Enable */ |
bogdanm | 86:04dd9b1680ae | 6735 | |
bogdanm | 86:04dd9b1680ae | 6736 | #define TIM_CCMR3_OC6FE ((uint32_t)0x00000400) /*!<Output Compare 6 Fast enable */ |
bogdanm | 86:04dd9b1680ae | 6737 | #define TIM_CCMR3_OC6PE ((uint32_t)0x00000800) /*!<Output Compare 6 Preload enable */ |
bogdanm | 86:04dd9b1680ae | 6738 | |
bogdanm | 86:04dd9b1680ae | 6739 | #define TIM_CCMR3_OC6M ((uint32_t)0x01007000) /*!<OC6M[2:0] bits (Output Compare 6 Mode) */ |
bogdanm | 86:04dd9b1680ae | 6740 | #define TIM_CCMR3_OC6M_0 ((uint32_t)0x00001000) /*!<Bit 0 */ |
bogdanm | 86:04dd9b1680ae | 6741 | #define TIM_CCMR3_OC6M_1 ((uint32_t)0x00002000) /*!<Bit 1 */ |
bogdanm | 86:04dd9b1680ae | 6742 | #define TIM_CCMR3_OC6M_2 ((uint32_t)0x00004000) /*!<Bit 2 */ |
bogdanm | 86:04dd9b1680ae | 6743 | #define TIM_CCMR3_OC6M_3 ((uint32_t)0x01000000) /*!<Bit 3 */ |
bogdanm | 86:04dd9b1680ae | 6744 | |
bogdanm | 86:04dd9b1680ae | 6745 | #define TIM_CCMR3_OC6CE ((uint32_t)0x00008000) /*!<Output Compare 6 Clear Enable */ |
bogdanm | 86:04dd9b1680ae | 6746 | |
bogdanm | 86:04dd9b1680ae | 6747 | /******************************************************************************/ |
bogdanm | 86:04dd9b1680ae | 6748 | /* */ |
bogdanm | 86:04dd9b1680ae | 6749 | /* Touch Sensing Controller (TSC) */ |
bogdanm | 86:04dd9b1680ae | 6750 | /* */ |
bogdanm | 86:04dd9b1680ae | 6751 | /******************************************************************************/ |
bogdanm | 86:04dd9b1680ae | 6752 | /******************* Bit definition for TSC_CR register *********************/ |
bogdanm | 86:04dd9b1680ae | 6753 | #define TSC_CR_TSCE ((uint32_t)0x00000001) /*!<Touch sensing controller enable */ |
bogdanm | 86:04dd9b1680ae | 6754 | #define TSC_CR_START ((uint32_t)0x00000002) /*!<Start acquisition */ |
bogdanm | 86:04dd9b1680ae | 6755 | #define TSC_CR_AM ((uint32_t)0x00000004) /*!<Acquisition mode */ |
bogdanm | 86:04dd9b1680ae | 6756 | #define TSC_CR_SYNCPOL ((uint32_t)0x00000008) /*!<Synchronization pin polarity */ |
bogdanm | 86:04dd9b1680ae | 6757 | #define TSC_CR_IODEF ((uint32_t)0x00000010) /*!<IO default mode */ |
bogdanm | 86:04dd9b1680ae | 6758 | |
bogdanm | 86:04dd9b1680ae | 6759 | #define TSC_CR_MCV ((uint32_t)0x000000E0) /*!<MCV[2:0] bits (Max Count Value) */ |
bogdanm | 86:04dd9b1680ae | 6760 | #define TSC_CR_MCV_0 ((uint32_t)0x00000020) /*!<Bit 0 */ |
bogdanm | 86:04dd9b1680ae | 6761 | #define TSC_CR_MCV_1 ((uint32_t)0x00000040) /*!<Bit 1 */ |
bogdanm | 86:04dd9b1680ae | 6762 | #define TSC_CR_MCV_2 ((uint32_t)0x00000080) /*!<Bit 2 */ |
bogdanm | 86:04dd9b1680ae | 6763 | |
bogdanm | 86:04dd9b1680ae | 6764 | #define TSC_CR_PGPSC ((uint32_t)0x00007000) /*!<PGPSC[2:0] bits (Pulse Generator Prescaler) */ |
bogdanm | 86:04dd9b1680ae | 6765 | #define TSC_CR_PGPSC_0 ((uint32_t)0x00001000) /*!<Bit 0 */ |
bogdanm | 86:04dd9b1680ae | 6766 | #define TSC_CR_PGPSC_1 ((uint32_t)0x00002000) /*!<Bit 1 */ |
bogdanm | 86:04dd9b1680ae | 6767 | #define TSC_CR_PGPSC_2 ((uint32_t)0x00004000) /*!<Bit 2 */ |
bogdanm | 86:04dd9b1680ae | 6768 | |
bogdanm | 86:04dd9b1680ae | 6769 | #define TSC_CR_SSPSC ((uint32_t)0x00008000) /*!<Spread Spectrum Prescaler */ |
bogdanm | 86:04dd9b1680ae | 6770 | #define TSC_CR_SSE ((uint32_t)0x00010000) /*!<Spread Spectrum Enable */ |
bogdanm | 86:04dd9b1680ae | 6771 | |
bogdanm | 86:04dd9b1680ae | 6772 | #define TSC_CR_SSD ((uint32_t)0x00FE0000) /*!<SSD[6:0] bits (Spread Spectrum Deviation) */ |
bogdanm | 86:04dd9b1680ae | 6773 | #define TSC_CR_SSD_0 ((uint32_t)0x00020000) /*!<Bit 0 */ |
bogdanm | 86:04dd9b1680ae | 6774 | #define TSC_CR_SSD_1 ((uint32_t)0x00040000) /*!<Bit 1 */ |
bogdanm | 86:04dd9b1680ae | 6775 | #define TSC_CR_SSD_2 ((uint32_t)0x00080000) /*!<Bit 2 */ |
bogdanm | 86:04dd9b1680ae | 6776 | #define TSC_CR_SSD_3 ((uint32_t)0x00100000) /*!<Bit 3 */ |
bogdanm | 86:04dd9b1680ae | 6777 | #define TSC_CR_SSD_4 ((uint32_t)0x00200000) /*!<Bit 4 */ |
bogdanm | 86:04dd9b1680ae | 6778 | #define TSC_CR_SSD_5 ((uint32_t)0x00400000) /*!<Bit 5 */ |
bogdanm | 86:04dd9b1680ae | 6779 | #define TSC_CR_SSD_6 ((uint32_t)0x00800000) /*!<Bit 6 */ |
bogdanm | 86:04dd9b1680ae | 6780 | |
bogdanm | 86:04dd9b1680ae | 6781 | #define TSC_CR_CTPL ((uint32_t)0x0F000000) /*!<CTPL[3:0] bits (Charge Transfer pulse low) */ |
bogdanm | 86:04dd9b1680ae | 6782 | #define TSC_CR_CTPL_0 ((uint32_t)0x01000000) /*!<Bit 0 */ |
bogdanm | 86:04dd9b1680ae | 6783 | #define TSC_CR_CTPL_1 ((uint32_t)0x02000000) /*!<Bit 1 */ |
bogdanm | 86:04dd9b1680ae | 6784 | #define TSC_CR_CTPL_2 ((uint32_t)0x04000000) /*!<Bit 2 */ |
bogdanm | 86:04dd9b1680ae | 6785 | #define TSC_CR_CTPL_3 ((uint32_t)0x08000000) /*!<Bit 3 */ |
bogdanm | 86:04dd9b1680ae | 6786 | |
bogdanm | 86:04dd9b1680ae | 6787 | #define TSC_CR_CTPH ((uint32_t)0xF0000000) /*!<CTPH[3:0] bits (Charge Transfer pulse high) */ |
bogdanm | 86:04dd9b1680ae | 6788 | #define TSC_CR_CTPH_0 ((uint32_t)0x10000000) /*!<Bit 0 */ |
bogdanm | 86:04dd9b1680ae | 6789 | #define TSC_CR_CTPH_1 ((uint32_t)0x20000000) /*!<Bit 1 */ |
bogdanm | 86:04dd9b1680ae | 6790 | #define TSC_CR_CTPH_2 ((uint32_t)0x40000000) /*!<Bit 2 */ |
bogdanm | 86:04dd9b1680ae | 6791 | #define TSC_CR_CTPH_3 ((uint32_t)0x80000000) /*!<Bit 3 */ |
bogdanm | 86:04dd9b1680ae | 6792 | |
bogdanm | 86:04dd9b1680ae | 6793 | /******************* Bit definition for TSC_IER register ********************/ |
bogdanm | 86:04dd9b1680ae | 6794 | #define TSC_IER_EOAIE ((uint32_t)0x00000001) /*!<End of acquisition interrupt enable */ |
bogdanm | 86:04dd9b1680ae | 6795 | #define TSC_IER_MCEIE ((uint32_t)0x00000002) /*!<Max count error interrupt enable */ |
bogdanm | 86:04dd9b1680ae | 6796 | |
bogdanm | 86:04dd9b1680ae | 6797 | /******************* Bit definition for TSC_ICR register ********************/ |
bogdanm | 86:04dd9b1680ae | 6798 | #define TSC_ICR_EOAIC ((uint32_t)0x00000001) /*!<End of acquisition interrupt clear */ |
bogdanm | 86:04dd9b1680ae | 6799 | #define TSC_ICR_MCEIC ((uint32_t)0x00000002) /*!<Max count error interrupt clear */ |
bogdanm | 86:04dd9b1680ae | 6800 | |
bogdanm | 86:04dd9b1680ae | 6801 | /******************* Bit definition for TSC_ISR register ********************/ |
bogdanm | 86:04dd9b1680ae | 6802 | #define TSC_ISR_EOAF ((uint32_t)0x00000001) /*!<End of acquisition flag */ |
bogdanm | 86:04dd9b1680ae | 6803 | #define TSC_ISR_MCEF ((uint32_t)0x00000002) /*!<Max count error flag */ |
bogdanm | 86:04dd9b1680ae | 6804 | |
bogdanm | 86:04dd9b1680ae | 6805 | /******************* Bit definition for TSC_IOHCR register ******************/ |
bogdanm | 86:04dd9b1680ae | 6806 | #define TSC_IOHCR_G1_IO1 ((uint32_t)0x00000001) /*!<GROUP1_IO1 schmitt trigger hysteresis mode */ |
bogdanm | 86:04dd9b1680ae | 6807 | #define TSC_IOHCR_G1_IO2 ((uint32_t)0x00000002) /*!<GROUP1_IO2 schmitt trigger hysteresis mode */ |
bogdanm | 86:04dd9b1680ae | 6808 | #define TSC_IOHCR_G1_IO3 ((uint32_t)0x00000004) /*!<GROUP1_IO3 schmitt trigger hysteresis mode */ |
bogdanm | 86:04dd9b1680ae | 6809 | #define TSC_IOHCR_G1_IO4 ((uint32_t)0x00000008) /*!<GROUP1_IO4 schmitt trigger hysteresis mode */ |
bogdanm | 86:04dd9b1680ae | 6810 | #define TSC_IOHCR_G2_IO1 ((uint32_t)0x00000010) /*!<GROUP2_IO1 schmitt trigger hysteresis mode */ |
bogdanm | 86:04dd9b1680ae | 6811 | #define TSC_IOHCR_G2_IO2 ((uint32_t)0x00000020) /*!<GROUP2_IO2 schmitt trigger hysteresis mode */ |
bogdanm | 86:04dd9b1680ae | 6812 | #define TSC_IOHCR_G2_IO3 ((uint32_t)0x00000040) /*!<GROUP2_IO3 schmitt trigger hysteresis mode */ |
bogdanm | 86:04dd9b1680ae | 6813 | #define TSC_IOHCR_G2_IO4 ((uint32_t)0x00000080) /*!<GROUP2_IO4 schmitt trigger hysteresis mode */ |
bogdanm | 86:04dd9b1680ae | 6814 | #define TSC_IOHCR_G3_IO1 ((uint32_t)0x00000100) /*!<GROUP3_IO1 schmitt trigger hysteresis mode */ |
bogdanm | 86:04dd9b1680ae | 6815 | #define TSC_IOHCR_G3_IO2 ((uint32_t)0x00000200) /*!<GROUP3_IO2 schmitt trigger hysteresis mode */ |
bogdanm | 86:04dd9b1680ae | 6816 | #define TSC_IOHCR_G3_IO3 ((uint32_t)0x00000400) /*!<GROUP3_IO3 schmitt trigger hysteresis mode */ |
bogdanm | 86:04dd9b1680ae | 6817 | #define TSC_IOHCR_G3_IO4 ((uint32_t)0x00000800) /*!<GROUP3_IO4 schmitt trigger hysteresis mode */ |
bogdanm | 86:04dd9b1680ae | 6818 | #define TSC_IOHCR_G4_IO1 ((uint32_t)0x00001000) /*!<GROUP4_IO1 schmitt trigger hysteresis mode */ |
bogdanm | 86:04dd9b1680ae | 6819 | #define TSC_IOHCR_G4_IO2 ((uint32_t)0x00002000) /*!<GROUP4_IO2 schmitt trigger hysteresis mode */ |
bogdanm | 86:04dd9b1680ae | 6820 | #define TSC_IOHCR_G4_IO3 ((uint32_t)0x00004000) /*!<GROUP4_IO3 schmitt trigger hysteresis mode */ |
bogdanm | 86:04dd9b1680ae | 6821 | #define TSC_IOHCR_G4_IO4 ((uint32_t)0x00008000) /*!<GROUP4_IO4 schmitt trigger hysteresis mode */ |
bogdanm | 86:04dd9b1680ae | 6822 | #define TSC_IOHCR_G5_IO1 ((uint32_t)0x00010000) /*!<GROUP5_IO1 schmitt trigger hysteresis mode */ |
bogdanm | 86:04dd9b1680ae | 6823 | #define TSC_IOHCR_G5_IO2 ((uint32_t)0x00020000) /*!<GROUP5_IO2 schmitt trigger hysteresis mode */ |
bogdanm | 86:04dd9b1680ae | 6824 | #define TSC_IOHCR_G5_IO3 ((uint32_t)0x00040000) /*!<GROUP5_IO3 schmitt trigger hysteresis mode */ |
bogdanm | 86:04dd9b1680ae | 6825 | #define TSC_IOHCR_G5_IO4 ((uint32_t)0x00080000) /*!<GROUP5_IO4 schmitt trigger hysteresis mode */ |
bogdanm | 86:04dd9b1680ae | 6826 | #define TSC_IOHCR_G6_IO1 ((uint32_t)0x00100000) /*!<GROUP6_IO1 schmitt trigger hysteresis mode */ |
bogdanm | 86:04dd9b1680ae | 6827 | #define TSC_IOHCR_G6_IO2 ((uint32_t)0x00200000) /*!<GROUP6_IO2 schmitt trigger hysteresis mode */ |
bogdanm | 86:04dd9b1680ae | 6828 | #define TSC_IOHCR_G6_IO3 ((uint32_t)0x00400000) /*!<GROUP6_IO3 schmitt trigger hysteresis mode */ |
bogdanm | 86:04dd9b1680ae | 6829 | #define TSC_IOHCR_G6_IO4 ((uint32_t)0x00800000) /*!<GROUP6_IO4 schmitt trigger hysteresis mode */ |
bogdanm | 86:04dd9b1680ae | 6830 | #define TSC_IOHCR_G7_IO1 ((uint32_t)0x01000000) /*!<GROUP7_IO1 schmitt trigger hysteresis mode */ |
bogdanm | 86:04dd9b1680ae | 6831 | #define TSC_IOHCR_G7_IO2 ((uint32_t)0x02000000) /*!<GROUP7_IO2 schmitt trigger hysteresis mode */ |
bogdanm | 86:04dd9b1680ae | 6832 | #define TSC_IOHCR_G7_IO3 ((uint32_t)0x04000000) /*!<GROUP7_IO3 schmitt trigger hysteresis mode */ |
bogdanm | 86:04dd9b1680ae | 6833 | #define TSC_IOHCR_G7_IO4 ((uint32_t)0x08000000) /*!<GROUP7_IO4 schmitt trigger hysteresis mode */ |
bogdanm | 86:04dd9b1680ae | 6834 | #define TSC_IOHCR_G8_IO1 ((uint32_t)0x10000000) /*!<GROUP8_IO1 schmitt trigger hysteresis mode */ |
bogdanm | 86:04dd9b1680ae | 6835 | #define TSC_IOHCR_G8_IO2 ((uint32_t)0x20000000) /*!<GROUP8_IO2 schmitt trigger hysteresis mode */ |
bogdanm | 86:04dd9b1680ae | 6836 | #define TSC_IOHCR_G8_IO3 ((uint32_t)0x40000000) /*!<GROUP8_IO3 schmitt trigger hysteresis mode */ |
bogdanm | 86:04dd9b1680ae | 6837 | #define TSC_IOHCR_G8_IO4 ((uint32_t)0x80000000) /*!<GROUP8_IO4 schmitt trigger hysteresis mode */ |
bogdanm | 86:04dd9b1680ae | 6838 | |
bogdanm | 86:04dd9b1680ae | 6839 | /******************* Bit definition for TSC_IOASCR register *****************/ |
bogdanm | 86:04dd9b1680ae | 6840 | #define TSC_IOASCR_G1_IO1 ((uint32_t)0x00000001) /*!<GROUP1_IO1 analog switch enable */ |
bogdanm | 86:04dd9b1680ae | 6841 | #define TSC_IOASCR_G1_IO2 ((uint32_t)0x00000002) /*!<GROUP1_IO2 analog switch enable */ |
bogdanm | 86:04dd9b1680ae | 6842 | #define TSC_IOASCR_G1_IO3 ((uint32_t)0x00000004) /*!<GROUP1_IO3 analog switch enable */ |
bogdanm | 86:04dd9b1680ae | 6843 | #define TSC_IOASCR_G1_IO4 ((uint32_t)0x00000008) /*!<GROUP1_IO4 analog switch enable */ |
bogdanm | 86:04dd9b1680ae | 6844 | #define TSC_IOASCR_G2_IO1 ((uint32_t)0x00000010) /*!<GROUP2_IO1 analog switch enable */ |
bogdanm | 86:04dd9b1680ae | 6845 | #define TSC_IOASCR_G2_IO2 ((uint32_t)0x00000020) /*!<GROUP2_IO2 analog switch enable */ |
bogdanm | 86:04dd9b1680ae | 6846 | #define TSC_IOASCR_G2_IO3 ((uint32_t)0x00000040) /*!<GROUP2_IO3 analog switch enable */ |
bogdanm | 86:04dd9b1680ae | 6847 | #define TSC_IOASCR_G2_IO4 ((uint32_t)0x00000080) /*!<GROUP2_IO4 analog switch enable */ |
bogdanm | 86:04dd9b1680ae | 6848 | #define TSC_IOASCR_G3_IO1 ((uint32_t)0x00000100) /*!<GROUP3_IO1 analog switch enable */ |
bogdanm | 86:04dd9b1680ae | 6849 | #define TSC_IOASCR_G3_IO2 ((uint32_t)0x00000200) /*!<GROUP3_IO2 analog switch enable */ |
bogdanm | 86:04dd9b1680ae | 6850 | #define TSC_IOASCR_G3_IO3 ((uint32_t)0x00000400) /*!<GROUP3_IO3 analog switch enable */ |
bogdanm | 86:04dd9b1680ae | 6851 | #define TSC_IOASCR_G3_IO4 ((uint32_t)0x00000800) /*!<GROUP3_IO4 analog switch enable */ |
bogdanm | 86:04dd9b1680ae | 6852 | #define TSC_IOASCR_G4_IO1 ((uint32_t)0x00001000) /*!<GROUP4_IO1 analog switch enable */ |
bogdanm | 86:04dd9b1680ae | 6853 | #define TSC_IOASCR_G4_IO2 ((uint32_t)0x00002000) /*!<GROUP4_IO2 analog switch enable */ |
bogdanm | 86:04dd9b1680ae | 6854 | #define TSC_IOASCR_G4_IO3 ((uint32_t)0x00004000) /*!<GROUP4_IO3 analog switch enable */ |
bogdanm | 86:04dd9b1680ae | 6855 | #define TSC_IOASCR_G4_IO4 ((uint32_t)0x00008000) /*!<GROUP4_IO4 analog switch enable */ |
bogdanm | 86:04dd9b1680ae | 6856 | #define TSC_IOASCR_G5_IO1 ((uint32_t)0x00010000) /*!<GROUP5_IO1 analog switch enable */ |
bogdanm | 86:04dd9b1680ae | 6857 | #define TSC_IOASCR_G5_IO2 ((uint32_t)0x00020000) /*!<GROUP5_IO2 analog switch enable */ |
bogdanm | 86:04dd9b1680ae | 6858 | #define TSC_IOASCR_G5_IO3 ((uint32_t)0x00040000) /*!<GROUP5_IO3 analog switch enable */ |
bogdanm | 86:04dd9b1680ae | 6859 | #define TSC_IOASCR_G5_IO4 ((uint32_t)0x00080000) /*!<GROUP5_IO4 analog switch enable */ |
bogdanm | 86:04dd9b1680ae | 6860 | #define TSC_IOASCR_G6_IO1 ((uint32_t)0x00100000) /*!<GROUP6_IO1 analog switch enable */ |
bogdanm | 86:04dd9b1680ae | 6861 | #define TSC_IOASCR_G6_IO2 ((uint32_t)0x00200000) /*!<GROUP6_IO2 analog switch enable */ |
bogdanm | 86:04dd9b1680ae | 6862 | #define TSC_IOASCR_G6_IO3 ((uint32_t)0x00400000) /*!<GROUP6_IO3 analog switch enable */ |
bogdanm | 86:04dd9b1680ae | 6863 | #define TSC_IOASCR_G6_IO4 ((uint32_t)0x00800000) /*!<GROUP6_IO4 analog switch enable */ |
bogdanm | 86:04dd9b1680ae | 6864 | #define TSC_IOASCR_G7_IO1 ((uint32_t)0x01000000) /*!<GROUP7_IO1 analog switch enable */ |
bogdanm | 86:04dd9b1680ae | 6865 | #define TSC_IOASCR_G7_IO2 ((uint32_t)0x02000000) /*!<GROUP7_IO2 analog switch enable */ |
bogdanm | 86:04dd9b1680ae | 6866 | #define TSC_IOASCR_G7_IO3 ((uint32_t)0x04000000) /*!<GROUP7_IO3 analog switch enable */ |
bogdanm | 86:04dd9b1680ae | 6867 | #define TSC_IOASCR_G7_IO4 ((uint32_t)0x08000000) /*!<GROUP7_IO4 analog switch enable */ |
bogdanm | 86:04dd9b1680ae | 6868 | #define TSC_IOASCR_G8_IO1 ((uint32_t)0x10000000) /*!<GROUP8_IO1 analog switch enable */ |
bogdanm | 86:04dd9b1680ae | 6869 | #define TSC_IOASCR_G8_IO2 ((uint32_t)0x20000000) /*!<GROUP8_IO2 analog switch enable */ |
bogdanm | 86:04dd9b1680ae | 6870 | #define TSC_IOASCR_G8_IO3 ((uint32_t)0x40000000) /*!<GROUP8_IO3 analog switch enable */ |
bogdanm | 86:04dd9b1680ae | 6871 | #define TSC_IOASCR_G8_IO4 ((uint32_t)0x80000000) /*!<GROUP8_IO4 analog switch enable */ |
bogdanm | 86:04dd9b1680ae | 6872 | |
bogdanm | 86:04dd9b1680ae | 6873 | /******************* Bit definition for TSC_IOSCR register ******************/ |
bogdanm | 86:04dd9b1680ae | 6874 | #define TSC_IOSCR_G1_IO1 ((uint32_t)0x00000001) /*!<GROUP1_IO1 sampling mode */ |
bogdanm | 86:04dd9b1680ae | 6875 | #define TSC_IOSCR_G1_IO2 ((uint32_t)0x00000002) /*!<GROUP1_IO2 sampling mode */ |
bogdanm | 86:04dd9b1680ae | 6876 | #define TSC_IOSCR_G1_IO3 ((uint32_t)0x00000004) /*!<GROUP1_IO3 sampling mode */ |
bogdanm | 86:04dd9b1680ae | 6877 | #define TSC_IOSCR_G1_IO4 ((uint32_t)0x00000008) /*!<GROUP1_IO4 sampling mode */ |
bogdanm | 86:04dd9b1680ae | 6878 | #define TSC_IOSCR_G2_IO1 ((uint32_t)0x00000010) /*!<GROUP2_IO1 sampling mode */ |
bogdanm | 86:04dd9b1680ae | 6879 | #define TSC_IOSCR_G2_IO2 ((uint32_t)0x00000020) /*!<GROUP2_IO2 sampling mode */ |
bogdanm | 86:04dd9b1680ae | 6880 | #define TSC_IOSCR_G2_IO3 ((uint32_t)0x00000040) /*!<GROUP2_IO3 sampling mode */ |
bogdanm | 86:04dd9b1680ae | 6881 | #define TSC_IOSCR_G2_IO4 ((uint32_t)0x00000080) /*!<GROUP2_IO4 sampling mode */ |
bogdanm | 86:04dd9b1680ae | 6882 | #define TSC_IOSCR_G3_IO1 ((uint32_t)0x00000100) /*!<GROUP3_IO1 sampling mode */ |
bogdanm | 86:04dd9b1680ae | 6883 | #define TSC_IOSCR_G3_IO2 ((uint32_t)0x00000200) /*!<GROUP3_IO2 sampling mode */ |
bogdanm | 86:04dd9b1680ae | 6884 | #define TSC_IOSCR_G3_IO3 ((uint32_t)0x00000400) /*!<GROUP3_IO3 sampling mode */ |
bogdanm | 86:04dd9b1680ae | 6885 | #define TSC_IOSCR_G3_IO4 ((uint32_t)0x00000800) /*!<GROUP3_IO4 sampling mode */ |
bogdanm | 86:04dd9b1680ae | 6886 | #define TSC_IOSCR_G4_IO1 ((uint32_t)0x00001000) /*!<GROUP4_IO1 sampling mode */ |
bogdanm | 86:04dd9b1680ae | 6887 | #define TSC_IOSCR_G4_IO2 ((uint32_t)0x00002000) /*!<GROUP4_IO2 sampling mode */ |
bogdanm | 86:04dd9b1680ae | 6888 | #define TSC_IOSCR_G4_IO3 ((uint32_t)0x00004000) /*!<GROUP4_IO3 sampling mode */ |
bogdanm | 86:04dd9b1680ae | 6889 | #define TSC_IOSCR_G4_IO4 ((uint32_t)0x00008000) /*!<GROUP4_IO4 sampling mode */ |
bogdanm | 86:04dd9b1680ae | 6890 | #define TSC_IOSCR_G5_IO1 ((uint32_t)0x00010000) /*!<GROUP5_IO1 sampling mode */ |
bogdanm | 86:04dd9b1680ae | 6891 | #define TSC_IOSCR_G5_IO2 ((uint32_t)0x00020000) /*!<GROUP5_IO2 sampling mode */ |
bogdanm | 86:04dd9b1680ae | 6892 | #define TSC_IOSCR_G5_IO3 ((uint32_t)0x00040000) /*!<GROUP5_IO3 sampling mode */ |
bogdanm | 86:04dd9b1680ae | 6893 | #define TSC_IOSCR_G5_IO4 ((uint32_t)0x00080000) /*!<GROUP5_IO4 sampling mode */ |
bogdanm | 86:04dd9b1680ae | 6894 | #define TSC_IOSCR_G6_IO1 ((uint32_t)0x00100000) /*!<GROUP6_IO1 sampling mode */ |
bogdanm | 86:04dd9b1680ae | 6895 | #define TSC_IOSCR_G6_IO2 ((uint32_t)0x00200000) /*!<GROUP6_IO2 sampling mode */ |
bogdanm | 86:04dd9b1680ae | 6896 | #define TSC_IOSCR_G6_IO3 ((uint32_t)0x00400000) /*!<GROUP6_IO3 sampling mode */ |
bogdanm | 86:04dd9b1680ae | 6897 | #define TSC_IOSCR_G6_IO4 ((uint32_t)0x00800000) /*!<GROUP6_IO4 sampling mode */ |
bogdanm | 86:04dd9b1680ae | 6898 | #define TSC_IOSCR_G7_IO1 ((uint32_t)0x01000000) /*!<GROUP7_IO1 sampling mode */ |
bogdanm | 86:04dd9b1680ae | 6899 | #define TSC_IOSCR_G7_IO2 ((uint32_t)0x02000000) /*!<GROUP7_IO2 sampling mode */ |
bogdanm | 86:04dd9b1680ae | 6900 | #define TSC_IOSCR_G7_IO3 ((uint32_t)0x04000000) /*!<GROUP7_IO3 sampling mode */ |
bogdanm | 86:04dd9b1680ae | 6901 | #define TSC_IOSCR_G7_IO4 ((uint32_t)0x08000000) /*!<GROUP7_IO4 sampling mode */ |
bogdanm | 86:04dd9b1680ae | 6902 | #define TSC_IOSCR_G8_IO1 ((uint32_t)0x10000000) /*!<GROUP8_IO1 sampling mode */ |
bogdanm | 86:04dd9b1680ae | 6903 | #define TSC_IOSCR_G8_IO2 ((uint32_t)0x20000000) /*!<GROUP8_IO2 sampling mode */ |
bogdanm | 86:04dd9b1680ae | 6904 | #define TSC_IOSCR_G8_IO3 ((uint32_t)0x40000000) /*!<GROUP8_IO3 sampling mode */ |
bogdanm | 86:04dd9b1680ae | 6905 | #define TSC_IOSCR_G8_IO4 ((uint32_t)0x80000000) /*!<GROUP8_IO4 sampling mode */ |
bogdanm | 86:04dd9b1680ae | 6906 | |
bogdanm | 86:04dd9b1680ae | 6907 | /******************* Bit definition for TSC_IOCCR register ******************/ |
bogdanm | 86:04dd9b1680ae | 6908 | #define TSC_IOCCR_G1_IO1 ((uint32_t)0x00000001) /*!<GROUP1_IO1 channel mode */ |
bogdanm | 86:04dd9b1680ae | 6909 | #define TSC_IOCCR_G1_IO2 ((uint32_t)0x00000002) /*!<GROUP1_IO2 channel mode */ |
bogdanm | 86:04dd9b1680ae | 6910 | #define TSC_IOCCR_G1_IO3 ((uint32_t)0x00000004) /*!<GROUP1_IO3 channel mode */ |
bogdanm | 86:04dd9b1680ae | 6911 | #define TSC_IOCCR_G1_IO4 ((uint32_t)0x00000008) /*!<GROUP1_IO4 channel mode */ |
bogdanm | 86:04dd9b1680ae | 6912 | #define TSC_IOCCR_G2_IO1 ((uint32_t)0x00000010) /*!<GROUP2_IO1 channel mode */ |
bogdanm | 86:04dd9b1680ae | 6913 | #define TSC_IOCCR_G2_IO2 ((uint32_t)0x00000020) /*!<GROUP2_IO2 channel mode */ |
bogdanm | 86:04dd9b1680ae | 6914 | #define TSC_IOCCR_G2_IO3 ((uint32_t)0x00000040) /*!<GROUP2_IO3 channel mode */ |
bogdanm | 86:04dd9b1680ae | 6915 | #define TSC_IOCCR_G2_IO4 ((uint32_t)0x00000080) /*!<GROUP2_IO4 channel mode */ |
bogdanm | 86:04dd9b1680ae | 6916 | #define TSC_IOCCR_G3_IO1 ((uint32_t)0x00000100) /*!<GROUP3_IO1 channel mode */ |
bogdanm | 86:04dd9b1680ae | 6917 | #define TSC_IOCCR_G3_IO2 ((uint32_t)0x00000200) /*!<GROUP3_IO2 channel mode */ |
bogdanm | 86:04dd9b1680ae | 6918 | #define TSC_IOCCR_G3_IO3 ((uint32_t)0x00000400) /*!<GROUP3_IO3 channel mode */ |
bogdanm | 86:04dd9b1680ae | 6919 | #define TSC_IOCCR_G3_IO4 ((uint32_t)0x00000800) /*!<GROUP3_IO4 channel mode */ |
bogdanm | 86:04dd9b1680ae | 6920 | #define TSC_IOCCR_G4_IO1 ((uint32_t)0x00001000) /*!<GROUP4_IO1 channel mode */ |
bogdanm | 86:04dd9b1680ae | 6921 | #define TSC_IOCCR_G4_IO2 ((uint32_t)0x00002000) /*!<GROUP4_IO2 channel mode */ |
bogdanm | 86:04dd9b1680ae | 6922 | #define TSC_IOCCR_G4_IO3 ((uint32_t)0x00004000) /*!<GROUP4_IO3 channel mode */ |
bogdanm | 86:04dd9b1680ae | 6923 | #define TSC_IOCCR_G4_IO4 ((uint32_t)0x00008000) /*!<GROUP4_IO4 channel mode */ |
bogdanm | 86:04dd9b1680ae | 6924 | #define TSC_IOCCR_G5_IO1 ((uint32_t)0x00010000) /*!<GROUP5_IO1 channel mode */ |
bogdanm | 86:04dd9b1680ae | 6925 | #define TSC_IOCCR_G5_IO2 ((uint32_t)0x00020000) /*!<GROUP5_IO2 channel mode */ |
bogdanm | 86:04dd9b1680ae | 6926 | #define TSC_IOCCR_G5_IO3 ((uint32_t)0x00040000) /*!<GROUP5_IO3 channel mode */ |
bogdanm | 86:04dd9b1680ae | 6927 | #define TSC_IOCCR_G5_IO4 ((uint32_t)0x00080000) /*!<GROUP5_IO4 channel mode */ |
bogdanm | 86:04dd9b1680ae | 6928 | #define TSC_IOCCR_G6_IO1 ((uint32_t)0x00100000) /*!<GROUP6_IO1 channel mode */ |
bogdanm | 86:04dd9b1680ae | 6929 | #define TSC_IOCCR_G6_IO2 ((uint32_t)0x00200000) /*!<GROUP6_IO2 channel mode */ |
bogdanm | 86:04dd9b1680ae | 6930 | #define TSC_IOCCR_G6_IO3 ((uint32_t)0x00400000) /*!<GROUP6_IO3 channel mode */ |
bogdanm | 86:04dd9b1680ae | 6931 | #define TSC_IOCCR_G6_IO4 ((uint32_t)0x00800000) /*!<GROUP6_IO4 channel mode */ |
bogdanm | 86:04dd9b1680ae | 6932 | #define TSC_IOCCR_G7_IO1 ((uint32_t)0x01000000) /*!<GROUP7_IO1 channel mode */ |
bogdanm | 86:04dd9b1680ae | 6933 | #define TSC_IOCCR_G7_IO2 ((uint32_t)0x02000000) /*!<GROUP7_IO2 channel mode */ |
bogdanm | 86:04dd9b1680ae | 6934 | #define TSC_IOCCR_G7_IO3 ((uint32_t)0x04000000) /*!<GROUP7_IO3 channel mode */ |
bogdanm | 86:04dd9b1680ae | 6935 | #define TSC_IOCCR_G7_IO4 ((uint32_t)0x08000000) /*!<GROUP7_IO4 channel mode */ |
bogdanm | 86:04dd9b1680ae | 6936 | #define TSC_IOCCR_G8_IO1 ((uint32_t)0x10000000) /*!<GROUP8_IO1 channel mode */ |
bogdanm | 86:04dd9b1680ae | 6937 | #define TSC_IOCCR_G8_IO2 ((uint32_t)0x20000000) /*!<GROUP8_IO2 channel mode */ |
bogdanm | 86:04dd9b1680ae | 6938 | #define TSC_IOCCR_G8_IO3 ((uint32_t)0x40000000) /*!<GROUP8_IO3 channel mode */ |
bogdanm | 86:04dd9b1680ae | 6939 | #define TSC_IOCCR_G8_IO4 ((uint32_t)0x80000000) /*!<GROUP8_IO4 channel mode */ |
bogdanm | 86:04dd9b1680ae | 6940 | |
bogdanm | 86:04dd9b1680ae | 6941 | /******************* Bit definition for TSC_IOGCSR register *****************/ |
bogdanm | 86:04dd9b1680ae | 6942 | #define TSC_IOGCSR_G1E ((uint32_t)0x00000001) /*!<Analog IO GROUP1 enable */ |
bogdanm | 86:04dd9b1680ae | 6943 | #define TSC_IOGCSR_G2E ((uint32_t)0x00000002) /*!<Analog IO GROUP2 enable */ |
bogdanm | 86:04dd9b1680ae | 6944 | #define TSC_IOGCSR_G3E ((uint32_t)0x00000004) /*!<Analog IO GROUP3 enable */ |
bogdanm | 86:04dd9b1680ae | 6945 | #define TSC_IOGCSR_G4E ((uint32_t)0x00000008) /*!<Analog IO GROUP4 enable */ |
bogdanm | 86:04dd9b1680ae | 6946 | #define TSC_IOGCSR_G5E ((uint32_t)0x00000010) /*!<Analog IO GROUP5 enable */ |
bogdanm | 86:04dd9b1680ae | 6947 | #define TSC_IOGCSR_G6E ((uint32_t)0x00000020) /*!<Analog IO GROUP6 enable */ |
bogdanm | 86:04dd9b1680ae | 6948 | #define TSC_IOGCSR_G7E ((uint32_t)0x00000040) /*!<Analog IO GROUP7 enable */ |
bogdanm | 86:04dd9b1680ae | 6949 | #define TSC_IOGCSR_G8E ((uint32_t)0x00000080) /*!<Analog IO GROUP8 enable */ |
bogdanm | 86:04dd9b1680ae | 6950 | #define TSC_IOGCSR_G1S ((uint32_t)0x00010000) /*!<Analog IO GROUP1 status */ |
bogdanm | 86:04dd9b1680ae | 6951 | #define TSC_IOGCSR_G2S ((uint32_t)0x00020000) /*!<Analog IO GROUP2 status */ |
bogdanm | 86:04dd9b1680ae | 6952 | #define TSC_IOGCSR_G3S ((uint32_t)0x00040000) /*!<Analog IO GROUP3 status */ |
bogdanm | 86:04dd9b1680ae | 6953 | #define TSC_IOGCSR_G4S ((uint32_t)0x00080000) /*!<Analog IO GROUP4 status */ |
bogdanm | 86:04dd9b1680ae | 6954 | #define TSC_IOGCSR_G5S ((uint32_t)0x00100000) /*!<Analog IO GROUP5 status */ |
bogdanm | 86:04dd9b1680ae | 6955 | #define TSC_IOGCSR_G6S ((uint32_t)0x00200000) /*!<Analog IO GROUP6 status */ |
bogdanm | 86:04dd9b1680ae | 6956 | #define TSC_IOGCSR_G7S ((uint32_t)0x00400000) /*!<Analog IO GROUP7 status */ |
bogdanm | 86:04dd9b1680ae | 6957 | #define TSC_IOGCSR_G8S ((uint32_t)0x00800000) /*!<Analog IO GROUP8 status */ |
bogdanm | 86:04dd9b1680ae | 6958 | |
bogdanm | 86:04dd9b1680ae | 6959 | /******************* Bit definition for TSC_IOGXCR register *****************/ |
bogdanm | 86:04dd9b1680ae | 6960 | #define TSC_IOGXCR_CNT ((uint32_t)0x00003FFF) /*!<CNT[13:0] bits (Counter value) */ |
bogdanm | 86:04dd9b1680ae | 6961 | |
bogdanm | 86:04dd9b1680ae | 6962 | /******************************************************************************/ |
bogdanm | 86:04dd9b1680ae | 6963 | /* */ |
bogdanm | 86:04dd9b1680ae | 6964 | /* Universal Synchronous Asynchronous Receiver Transmitter (USART) */ |
bogdanm | 86:04dd9b1680ae | 6965 | /* */ |
bogdanm | 86:04dd9b1680ae | 6966 | /******************************************************************************/ |
bogdanm | 86:04dd9b1680ae | 6967 | /****************** Bit definition for USART_CR1 register *******************/ |
bogdanm | 86:04dd9b1680ae | 6968 | #define USART_CR1_UE ((uint32_t)0x00000001) /*!< USART Enable */ |
bogdanm | 86:04dd9b1680ae | 6969 | #define USART_CR1_UESM ((uint32_t)0x00000002) /*!< USART Enable in STOP Mode */ |
bogdanm | 86:04dd9b1680ae | 6970 | #define USART_CR1_RE ((uint32_t)0x00000004) /*!< Receiver Enable */ |
bogdanm | 86:04dd9b1680ae | 6971 | #define USART_CR1_TE ((uint32_t)0x00000008) /*!< Transmitter Enable */ |
bogdanm | 86:04dd9b1680ae | 6972 | #define USART_CR1_IDLEIE ((uint32_t)0x00000010) /*!< IDLE Interrupt Enable */ |
bogdanm | 86:04dd9b1680ae | 6973 | #define USART_CR1_RXNEIE ((uint32_t)0x00000020) /*!< RXNE Interrupt Enable */ |
bogdanm | 86:04dd9b1680ae | 6974 | #define USART_CR1_TCIE ((uint32_t)0x00000040) /*!< Transmission Complete Interrupt Enable */ |
bogdanm | 86:04dd9b1680ae | 6975 | #define USART_CR1_TXEIE ((uint32_t)0x00000080) /*!< TXE Interrupt Enable */ |
bogdanm | 86:04dd9b1680ae | 6976 | #define USART_CR1_PEIE ((uint32_t)0x00000100) /*!< PE Interrupt Enable */ |
bogdanm | 86:04dd9b1680ae | 6977 | #define USART_CR1_PS ((uint32_t)0x00000200) /*!< Parity Selection */ |
bogdanm | 86:04dd9b1680ae | 6978 | #define USART_CR1_PCE ((uint32_t)0x00000400) /*!< Parity Control Enable */ |
bogdanm | 86:04dd9b1680ae | 6979 | #define USART_CR1_WAKE ((uint32_t)0x00000800) /*!< Receiver Wakeup method */ |
bogdanm | 86:04dd9b1680ae | 6980 | #define USART_CR1_M0 ((uint32_t)0x00001000) /*!< Word length bit 0 */ |
bogdanm | 86:04dd9b1680ae | 6981 | #define USART_CR1_MME ((uint32_t)0x00002000) /*!< Mute Mode Enable */ |
bogdanm | 86:04dd9b1680ae | 6982 | #define USART_CR1_CMIE ((uint32_t)0x00004000) /*!< Character match interrupt enable */ |
bogdanm | 86:04dd9b1680ae | 6983 | #define USART_CR1_OVER8 ((uint32_t)0x00008000) /*!< Oversampling by 8-bit or 16-bit mode */ |
bogdanm | 86:04dd9b1680ae | 6984 | #define USART_CR1_DEDT ((uint32_t)0x001F0000) /*!< DEDT[4:0] bits (Driver Enable Deassertion Time) */ |
bogdanm | 86:04dd9b1680ae | 6985 | #define USART_CR1_DEDT_0 ((uint32_t)0x00010000) /*!< Bit 0 */ |
bogdanm | 86:04dd9b1680ae | 6986 | #define USART_CR1_DEDT_1 ((uint32_t)0x00020000) /*!< Bit 1 */ |
bogdanm | 86:04dd9b1680ae | 6987 | #define USART_CR1_DEDT_2 ((uint32_t)0x00040000) /*!< Bit 2 */ |
bogdanm | 86:04dd9b1680ae | 6988 | #define USART_CR1_DEDT_3 ((uint32_t)0x00080000) /*!< Bit 3 */ |
bogdanm | 86:04dd9b1680ae | 6989 | #define USART_CR1_DEDT_4 ((uint32_t)0x00100000) /*!< Bit 4 */ |
bogdanm | 86:04dd9b1680ae | 6990 | #define USART_CR1_DEAT ((uint32_t)0x03E00000) /*!< DEAT[4:0] bits (Driver Enable Assertion Time) */ |
bogdanm | 86:04dd9b1680ae | 6991 | #define USART_CR1_DEAT_0 ((uint32_t)0x00200000) /*!< Bit 0 */ |
bogdanm | 86:04dd9b1680ae | 6992 | #define USART_CR1_DEAT_1 ((uint32_t)0x00400000) /*!< Bit 1 */ |
bogdanm | 86:04dd9b1680ae | 6993 | #define USART_CR1_DEAT_2 ((uint32_t)0x00800000) /*!< Bit 2 */ |
bogdanm | 86:04dd9b1680ae | 6994 | #define USART_CR1_DEAT_3 ((uint32_t)0x01000000) /*!< Bit 3 */ |
bogdanm | 86:04dd9b1680ae | 6995 | #define USART_CR1_DEAT_4 ((uint32_t)0x02000000) /*!< Bit 4 */ |
bogdanm | 86:04dd9b1680ae | 6996 | #define USART_CR1_RTOIE ((uint32_t)0x04000000) /*!< Receive Time Out interrupt enable */ |
bogdanm | 86:04dd9b1680ae | 6997 | #define USART_CR1_EOBIE ((uint32_t)0x08000000) /*!< End of Block interrupt enable */ |
bogdanm | 86:04dd9b1680ae | 6998 | #define USART_CR1_M1 ((uint32_t)0x10000000) /*!< Word length bit 1 */ |
bogdanm | 86:04dd9b1680ae | 6999 | #define USART_CR1_M ((uint32_t)0x10001000) /*!< [M1:M0] Word length */ |
bogdanm | 86:04dd9b1680ae | 7000 | |
bogdanm | 86:04dd9b1680ae | 7001 | /****************** Bit definition for USART_CR2 register *******************/ |
bogdanm | 86:04dd9b1680ae | 7002 | #define USART_CR2_ADDM7 ((uint32_t)0x00000010) /*!< 7-bit or 4-bit Address Detection */ |
bogdanm | 86:04dd9b1680ae | 7003 | #define USART_CR2_LBDL ((uint32_t)0x00000020) /*!< LIN Break Detection Length */ |
bogdanm | 86:04dd9b1680ae | 7004 | #define USART_CR2_LBDIE ((uint32_t)0x00000040) /*!< LIN Break Detection Interrupt Enable */ |
bogdanm | 86:04dd9b1680ae | 7005 | #define USART_CR2_LBCL ((uint32_t)0x00000100) /*!< Last Bit Clock pulse */ |
bogdanm | 86:04dd9b1680ae | 7006 | #define USART_CR2_CPHA ((uint32_t)0x00000200) /*!< Clock Phase */ |
bogdanm | 86:04dd9b1680ae | 7007 | #define USART_CR2_CPOL ((uint32_t)0x00000400) /*!< Clock Polarity */ |
bogdanm | 86:04dd9b1680ae | 7008 | #define USART_CR2_CLKEN ((uint32_t)0x00000800) /*!< Clock Enable */ |
bogdanm | 86:04dd9b1680ae | 7009 | #define USART_CR2_STOP ((uint32_t)0x00003000) /*!< STOP[1:0] bits (STOP bits) */ |
bogdanm | 86:04dd9b1680ae | 7010 | #define USART_CR2_STOP_0 ((uint32_t)0x00001000) /*!< Bit 0 */ |
bogdanm | 86:04dd9b1680ae | 7011 | #define USART_CR2_STOP_1 ((uint32_t)0x00002000) /*!< Bit 1 */ |
bogdanm | 86:04dd9b1680ae | 7012 | #define USART_CR2_LINEN ((uint32_t)0x00004000) /*!< LIN mode enable */ |
bogdanm | 86:04dd9b1680ae | 7013 | #define USART_CR2_SWAP ((uint32_t)0x00008000) /*!< SWAP TX/RX pins */ |
bogdanm | 86:04dd9b1680ae | 7014 | #define USART_CR2_RXINV ((uint32_t)0x00010000) /*!< RX pin active level inversion */ |
bogdanm | 86:04dd9b1680ae | 7015 | #define USART_CR2_TXINV ((uint32_t)0x00020000) /*!< TX pin active level inversion */ |
bogdanm | 86:04dd9b1680ae | 7016 | #define USART_CR2_DATAINV ((uint32_t)0x00040000) /*!< Binary data inversion */ |
bogdanm | 86:04dd9b1680ae | 7017 | #define USART_CR2_MSBFIRST ((uint32_t)0x00080000) /*!< Most Significant Bit First */ |
bogdanm | 86:04dd9b1680ae | 7018 | #define USART_CR2_ABREN ((uint32_t)0x00100000) /*!< Auto Baud-Rate Enable*/ |
bogdanm | 86:04dd9b1680ae | 7019 | #define USART_CR2_ABRMODE ((uint32_t)0x00600000) /*!< ABRMOD[1:0] bits (Auto Baud-Rate Mode) */ |
bogdanm | 86:04dd9b1680ae | 7020 | #define USART_CR2_ABRMODE_0 ((uint32_t)0x00200000) /*!< Bit 0 */ |
bogdanm | 86:04dd9b1680ae | 7021 | #define USART_CR2_ABRMODE_1 ((uint32_t)0x00400000) /*!< Bit 1 */ |
bogdanm | 86:04dd9b1680ae | 7022 | #define USART_CR2_RTOEN ((uint32_t)0x00800000) /*!< Receiver Time-Out enable */ |
bogdanm | 86:04dd9b1680ae | 7023 | #define USART_CR2_ADD ((uint32_t)0xFF000000) /*!< Address of the USART node */ |
bogdanm | 86:04dd9b1680ae | 7024 | |
bogdanm | 86:04dd9b1680ae | 7025 | /****************** Bit definition for USART_CR3 register *******************/ |
bogdanm | 86:04dd9b1680ae | 7026 | #define USART_CR3_EIE ((uint32_t)0x00000001) /*!< Error Interrupt Enable */ |
bogdanm | 86:04dd9b1680ae | 7027 | #define USART_CR3_IREN ((uint32_t)0x00000002) /*!< IrDA mode Enable */ |
bogdanm | 86:04dd9b1680ae | 7028 | #define USART_CR3_IRLP ((uint32_t)0x00000004) /*!< IrDA Low-Power */ |
bogdanm | 86:04dd9b1680ae | 7029 | #define USART_CR3_HDSEL ((uint32_t)0x00000008) /*!< Half-Duplex Selection */ |
bogdanm | 86:04dd9b1680ae | 7030 | #define USART_CR3_NACK ((uint32_t)0x00000010) /*!< SmartCard NACK enable */ |
bogdanm | 86:04dd9b1680ae | 7031 | #define USART_CR3_SCEN ((uint32_t)0x00000020) /*!< SmartCard mode enable */ |
bogdanm | 86:04dd9b1680ae | 7032 | #define USART_CR3_DMAR ((uint32_t)0x00000040) /*!< DMA Enable Receiver */ |
bogdanm | 86:04dd9b1680ae | 7033 | #define USART_CR3_DMAT ((uint32_t)0x00000080) /*!< DMA Enable Transmitter */ |
bogdanm | 86:04dd9b1680ae | 7034 | #define USART_CR3_RTSE ((uint32_t)0x00000100) /*!< RTS Enable */ |
bogdanm | 86:04dd9b1680ae | 7035 | #define USART_CR3_CTSE ((uint32_t)0x00000200) /*!< CTS Enable */ |
bogdanm | 86:04dd9b1680ae | 7036 | #define USART_CR3_CTSIE ((uint32_t)0x00000400) /*!< CTS Interrupt Enable */ |
bogdanm | 86:04dd9b1680ae | 7037 | #define USART_CR3_ONEBIT ((uint32_t)0x00000800) /*!< One sample bit method enable */ |
bogdanm | 86:04dd9b1680ae | 7038 | #define USART_CR3_OVRDIS ((uint32_t)0x00001000) /*!< Overrun Disable */ |
bogdanm | 86:04dd9b1680ae | 7039 | #define USART_CR3_DDRE ((uint32_t)0x00002000) /*!< DMA Disable on Reception Error */ |
bogdanm | 86:04dd9b1680ae | 7040 | #define USART_CR3_DEM ((uint32_t)0x00004000) /*!< Driver Enable Mode */ |
bogdanm | 86:04dd9b1680ae | 7041 | #define USART_CR3_DEP ((uint32_t)0x00008000) /*!< Driver Enable Polarity Selection */ |
bogdanm | 86:04dd9b1680ae | 7042 | #define USART_CR3_SCARCNT ((uint32_t)0x000E0000) /*!< SCARCNT[2:0] bits (SmartCard Auto-Retry Count) */ |
bogdanm | 86:04dd9b1680ae | 7043 | #define USART_CR3_SCARCNT_0 ((uint32_t)0x00020000) /*!< Bit 0 */ |
bogdanm | 86:04dd9b1680ae | 7044 | #define USART_CR3_SCARCNT_1 ((uint32_t)0x00040000) /*!< Bit 1 */ |
bogdanm | 86:04dd9b1680ae | 7045 | #define USART_CR3_SCARCNT_2 ((uint32_t)0x00080000) /*!< Bit 2 */ |
bogdanm | 86:04dd9b1680ae | 7046 | #define USART_CR3_WUS ((uint32_t)0x00300000) /*!< WUS[1:0] bits (Wake UP Interrupt Flag Selection) */ |
bogdanm | 86:04dd9b1680ae | 7047 | #define USART_CR3_WUS_0 ((uint32_t)0x00100000) /*!< Bit 0 */ |
bogdanm | 86:04dd9b1680ae | 7048 | #define USART_CR3_WUS_1 ((uint32_t)0x00200000) /*!< Bit 1 */ |
bogdanm | 86:04dd9b1680ae | 7049 | #define USART_CR3_WUFIE ((uint32_t)0x00400000) /*!< Wake Up Interrupt Enable */ |
bogdanm | 86:04dd9b1680ae | 7050 | |
bogdanm | 86:04dd9b1680ae | 7051 | /****************** Bit definition for USART_BRR register *******************/ |
bogdanm | 86:04dd9b1680ae | 7052 | #define USART_BRR_DIV_FRACTION ((uint32_t)0x0000000F) /*!< Fraction of USARTDIV */ |
bogdanm | 86:04dd9b1680ae | 7053 | #define USART_BRR_DIV_MANTISSA ((uint32_t)0x0000FFF0) /*!< Mantissa of USARTDIV */ |
bogdanm | 86:04dd9b1680ae | 7054 | |
bogdanm | 86:04dd9b1680ae | 7055 | /****************** Bit definition for USART_GTPR register ******************/ |
bogdanm | 86:04dd9b1680ae | 7056 | #define USART_GTPR_PSC ((uint32_t)0x000000FF) /*!< PSC[7:0] bits (Prescaler value) */ |
bogdanm | 86:04dd9b1680ae | 7057 | #define USART_GTPR_GT ((uint32_t)0x0000FF00) /*!< GT[7:0] bits (Guard time value) */ |
bogdanm | 86:04dd9b1680ae | 7058 | |
bogdanm | 86:04dd9b1680ae | 7059 | |
bogdanm | 86:04dd9b1680ae | 7060 | /******************* Bit definition for USART_RTOR register *****************/ |
bogdanm | 86:04dd9b1680ae | 7061 | #define USART_RTOR_RTO ((uint32_t)0x00FFFFFF) /*!< Receiver Time Out Value */ |
bogdanm | 86:04dd9b1680ae | 7062 | #define USART_RTOR_BLEN ((uint32_t)0xFF000000) /*!< Block Length */ |
bogdanm | 86:04dd9b1680ae | 7063 | |
bogdanm | 86:04dd9b1680ae | 7064 | /******************* Bit definition for USART_RQR register ******************/ |
bogdanm | 86:04dd9b1680ae | 7065 | #define USART_RQR_ABRRQ ((uint32_t)0x00000001) /*!< Auto-Baud Rate Request */ |
bogdanm | 86:04dd9b1680ae | 7066 | #define USART_RQR_SBKRQ ((uint32_t)0x00000002) /*!< Send Break Request */ |
bogdanm | 86:04dd9b1680ae | 7067 | #define USART_RQR_MMRQ ((uint32_t)0x00000004) /*!< Mute Mode Request */ |
bogdanm | 86:04dd9b1680ae | 7068 | #define USART_RQR_RXFRQ ((uint32_t)0x00000008) /*!< Receive Data flush Request */ |
bogdanm | 86:04dd9b1680ae | 7069 | #define USART_RQR_TXFRQ ((uint32_t)0x00000010) /*!< Transmit data flush Request */ |
bogdanm | 86:04dd9b1680ae | 7070 | |
bogdanm | 86:04dd9b1680ae | 7071 | /******************* Bit definition for USART_ISR register ******************/ |
bogdanm | 86:04dd9b1680ae | 7072 | #define USART_ISR_PE ((uint32_t)0x00000001) /*!< Parity Error */ |
bogdanm | 86:04dd9b1680ae | 7073 | #define USART_ISR_FE ((uint32_t)0x00000002) /*!< Framing Error */ |
bogdanm | 86:04dd9b1680ae | 7074 | #define USART_ISR_NE ((uint32_t)0x00000004) /*!< Noise detected Flag */ |
bogdanm | 86:04dd9b1680ae | 7075 | #define USART_ISR_ORE ((uint32_t)0x00000008) /*!< OverRun Error */ |
bogdanm | 86:04dd9b1680ae | 7076 | #define USART_ISR_IDLE ((uint32_t)0x00000010) /*!< IDLE line detected */ |
bogdanm | 86:04dd9b1680ae | 7077 | #define USART_ISR_RXNE ((uint32_t)0x00000020) /*!< Read Data Register Not Empty */ |
bogdanm | 86:04dd9b1680ae | 7078 | #define USART_ISR_TC ((uint32_t)0x00000040) /*!< Transmission Complete */ |
bogdanm | 86:04dd9b1680ae | 7079 | #define USART_ISR_TXE ((uint32_t)0x00000080) /*!< Transmit Data Register Empty */ |
bogdanm | 86:04dd9b1680ae | 7080 | #define USART_ISR_LBDF ((uint32_t)0x00000100) /*!< LIN Break Detection Flag */ |
bogdanm | 86:04dd9b1680ae | 7081 | #define USART_ISR_CTSIF ((uint32_t)0x00000200) /*!< CTS interrupt flag */ |
bogdanm | 86:04dd9b1680ae | 7082 | #define USART_ISR_CTS ((uint32_t)0x00000400) /*!< CTS flag */ |
bogdanm | 86:04dd9b1680ae | 7083 | #define USART_ISR_RTOF ((uint32_t)0x00000800) /*!< Receiver Time Out */ |
bogdanm | 86:04dd9b1680ae | 7084 | #define USART_ISR_EOBF ((uint32_t)0x00001000) /*!< End Of Block Flag */ |
bogdanm | 86:04dd9b1680ae | 7085 | #define USART_ISR_ABRE ((uint32_t)0x00004000) /*!< Auto-Baud Rate Error */ |
bogdanm | 86:04dd9b1680ae | 7086 | #define USART_ISR_ABRF ((uint32_t)0x00008000) /*!< Auto-Baud Rate Flag */ |
bogdanm | 86:04dd9b1680ae | 7087 | #define USART_ISR_BUSY ((uint32_t)0x00010000) /*!< Busy Flag */ |
bogdanm | 86:04dd9b1680ae | 7088 | #define USART_ISR_CMF ((uint32_t)0x00020000) /*!< Character Match Flag */ |
bogdanm | 86:04dd9b1680ae | 7089 | #define USART_ISR_SBKF ((uint32_t)0x00040000) /*!< Send Break Flag */ |
bogdanm | 86:04dd9b1680ae | 7090 | #define USART_ISR_RWU ((uint32_t)0x00080000) /*!< Receive Wake Up from mute mode Flag */ |
bogdanm | 86:04dd9b1680ae | 7091 | #define USART_ISR_WUF ((uint32_t)0x00100000) /*!< Wake Up from stop mode Flag */ |
bogdanm | 86:04dd9b1680ae | 7092 | #define USART_ISR_TEACK ((uint32_t)0x00200000) /*!< Transmit Enable Acknowledge Flag */ |
bogdanm | 86:04dd9b1680ae | 7093 | #define USART_ISR_REACK ((uint32_t)0x00400000) /*!< Receive Enable Acknowledge Flag */ |
bogdanm | 86:04dd9b1680ae | 7094 | |
bogdanm | 86:04dd9b1680ae | 7095 | /******************* Bit definition for USART_ICR register ******************/ |
bogdanm | 86:04dd9b1680ae | 7096 | #define USART_ICR_PECF ((uint32_t)0x00000001) /*!< Parity Error Clear Flag */ |
bogdanm | 86:04dd9b1680ae | 7097 | #define USART_ICR_FECF ((uint32_t)0x00000002) /*!< Framing Error Clear Flag */ |
bogdanm | 86:04dd9b1680ae | 7098 | #define USART_ICR_NCF ((uint32_t)0x00000004) /*!< Noise detected Clear Flag */ |
bogdanm | 86:04dd9b1680ae | 7099 | #define USART_ICR_ORECF ((uint32_t)0x00000008) /*!< OverRun Error Clear Flag */ |
bogdanm | 86:04dd9b1680ae | 7100 | #define USART_ICR_IDLECF ((uint32_t)0x00000010) /*!< IDLE line detected Clear Flag */ |
bogdanm | 86:04dd9b1680ae | 7101 | #define USART_ICR_TCCF ((uint32_t)0x00000040) /*!< Transmission Complete Clear Flag */ |
bogdanm | 86:04dd9b1680ae | 7102 | #define USART_ICR_LBDCF ((uint32_t)0x00000100) /*!< LIN Break Detection Clear Flag */ |
bogdanm | 86:04dd9b1680ae | 7103 | #define USART_ICR_CTSCF ((uint32_t)0x00000200) /*!< CTS Interrupt Clear Flag */ |
bogdanm | 86:04dd9b1680ae | 7104 | #define USART_ICR_RTOCF ((uint32_t)0x00000800) /*!< Receiver Time Out Clear Flag */ |
bogdanm | 86:04dd9b1680ae | 7105 | #define USART_ICR_EOBCF ((uint32_t)0x00001000) /*!< End Of Block Clear Flag */ |
bogdanm | 86:04dd9b1680ae | 7106 | #define USART_ICR_CMCF ((uint32_t)0x00020000) /*!< Character Match Clear Flag */ |
bogdanm | 86:04dd9b1680ae | 7107 | #define USART_ICR_WUCF ((uint32_t)0x00100000) /*!< Wake Up from stop mode Clear Flag */ |
bogdanm | 86:04dd9b1680ae | 7108 | |
bogdanm | 86:04dd9b1680ae | 7109 | /******************* Bit definition for USART_RDR register ******************/ |
bogdanm | 86:04dd9b1680ae | 7110 | #define USART_RDR_RDR ((uint32_t)0x000001FF) /*!< RDR[8:0] bits (Receive Data value) */ |
bogdanm | 86:04dd9b1680ae | 7111 | |
bogdanm | 86:04dd9b1680ae | 7112 | /******************* Bit definition for USART_TDR register ******************/ |
bogdanm | 86:04dd9b1680ae | 7113 | #define USART_TDR_TDR ((uint32_t)0x000001FF) /*!< TDR[8:0] bits (Transmit Data value) */ |
bogdanm | 86:04dd9b1680ae | 7114 | |
bogdanm | 86:04dd9b1680ae | 7115 | /******************************************************************************/ |
bogdanm | 86:04dd9b1680ae | 7116 | /* */ |
bogdanm | 86:04dd9b1680ae | 7117 | /* Window WATCHDOG */ |
bogdanm | 86:04dd9b1680ae | 7118 | /* */ |
bogdanm | 86:04dd9b1680ae | 7119 | /******************************************************************************/ |
bogdanm | 86:04dd9b1680ae | 7120 | /******************* Bit definition for WWDG_CR register ********************/ |
bogdanm | 86:04dd9b1680ae | 7121 | #define WWDG_CR_T ((uint32_t)0x0000007F) /*!<T[6:0] bits (7-Bit counter (MSB to LSB)) */ |
bogdanm | 86:04dd9b1680ae | 7122 | #define WWDG_CR_T0 ((uint32_t)0x00000001) /*!<Bit 0 */ |
bogdanm | 86:04dd9b1680ae | 7123 | #define WWDG_CR_T1 ((uint32_t)0x00000002) /*!<Bit 1 */ |
bogdanm | 86:04dd9b1680ae | 7124 | #define WWDG_CR_T2 ((uint32_t)0x00000004) /*!<Bit 2 */ |
bogdanm | 86:04dd9b1680ae | 7125 | #define WWDG_CR_T3 ((uint32_t)0x00000008) /*!<Bit 3 */ |
bogdanm | 86:04dd9b1680ae | 7126 | #define WWDG_CR_T4 ((uint32_t)0x00000010) /*!<Bit 4 */ |
bogdanm | 86:04dd9b1680ae | 7127 | #define WWDG_CR_T5 ((uint32_t)0x00000020) /*!<Bit 5 */ |
bogdanm | 86:04dd9b1680ae | 7128 | #define WWDG_CR_T6 ((uint32_t)0x00000040) /*!<Bit 6 */ |
bogdanm | 86:04dd9b1680ae | 7129 | |
bogdanm | 86:04dd9b1680ae | 7130 | #define WWDG_CR_WDGA ((uint32_t)0x00000080) /*!<Activation bit */ |
bogdanm | 86:04dd9b1680ae | 7131 | |
bogdanm | 86:04dd9b1680ae | 7132 | /******************* Bit definition for WWDG_CFR register *******************/ |
bogdanm | 86:04dd9b1680ae | 7133 | #define WWDG_CFR_W ((uint32_t)0x0000007F) /*!<W[6:0] bits (7-bit window value) */ |
bogdanm | 86:04dd9b1680ae | 7134 | #define WWDG_CFR_W0 ((uint32_t)0x00000001) /*!<Bit 0 */ |
bogdanm | 86:04dd9b1680ae | 7135 | #define WWDG_CFR_W1 ((uint32_t)0x00000002) /*!<Bit 1 */ |
bogdanm | 86:04dd9b1680ae | 7136 | #define WWDG_CFR_W2 ((uint32_t)0x00000004) /*!<Bit 2 */ |
bogdanm | 86:04dd9b1680ae | 7137 | #define WWDG_CFR_W3 ((uint32_t)0x00000008) /*!<Bit 3 */ |
bogdanm | 86:04dd9b1680ae | 7138 | #define WWDG_CFR_W4 ((uint32_t)0x00000010) /*!<Bit 4 */ |
bogdanm | 86:04dd9b1680ae | 7139 | #define WWDG_CFR_W5 ((uint32_t)0x00000020) /*!<Bit 5 */ |
bogdanm | 86:04dd9b1680ae | 7140 | #define WWDG_CFR_W6 ((uint32_t)0x00000040) /*!<Bit 6 */ |
bogdanm | 86:04dd9b1680ae | 7141 | |
bogdanm | 86:04dd9b1680ae | 7142 | #define WWDG_CFR_WDGTB ((uint32_t)0x00000180) /*!<WDGTB[1:0] bits (Timer Base) */ |
bogdanm | 86:04dd9b1680ae | 7143 | #define WWDG_CFR_WDGTB0 ((uint32_t)0x00000080) /*!<Bit 0 */ |
bogdanm | 86:04dd9b1680ae | 7144 | #define WWDG_CFR_WDGTB1 ((uint32_t)0x00000100) /*!<Bit 1 */ |
bogdanm | 86:04dd9b1680ae | 7145 | |
bogdanm | 86:04dd9b1680ae | 7146 | #define WWDG_CFR_EWI ((uint32_t)0x00000200) /*!<Early Wakeup Interrupt */ |
bogdanm | 86:04dd9b1680ae | 7147 | |
bogdanm | 86:04dd9b1680ae | 7148 | /******************* Bit definition for WWDG_SR register ********************/ |
bogdanm | 86:04dd9b1680ae | 7149 | #define WWDG_SR_EWIF ((uint32_t)0x00000001) /*!<Early Wakeup Interrupt Flag */ |
bogdanm | 86:04dd9b1680ae | 7150 | |
bogdanm | 86:04dd9b1680ae | 7151 | /** |
bogdanm | 86:04dd9b1680ae | 7152 | * @} |
bogdanm | 86:04dd9b1680ae | 7153 | */ |
bogdanm | 86:04dd9b1680ae | 7154 | |
bogdanm | 86:04dd9b1680ae | 7155 | /** |
bogdanm | 86:04dd9b1680ae | 7156 | * @} |
bogdanm | 86:04dd9b1680ae | 7157 | */ |
bogdanm | 86:04dd9b1680ae | 7158 | |
bogdanm | 86:04dd9b1680ae | 7159 | /** @addtogroup Exported_macros |
bogdanm | 86:04dd9b1680ae | 7160 | * @{ |
bogdanm | 86:04dd9b1680ae | 7161 | */ |
bogdanm | 86:04dd9b1680ae | 7162 | |
bogdanm | 86:04dd9b1680ae | 7163 | /****************************** ADC Instances *********************************/ |
bogdanm | 86:04dd9b1680ae | 7164 | #define IS_ADC_ALL_INSTANCE(INSTANCE) (((INSTANCE) == ADC1) || \ |
bogdanm | 86:04dd9b1680ae | 7165 | ((INSTANCE) == ADC2)) |
bogdanm | 86:04dd9b1680ae | 7166 | |
bogdanm | 86:04dd9b1680ae | 7167 | #define IS_ADC_MULTIMODE_MASTER_INSTANCE(INSTANCE) (((INSTANCE) == ADC1)) |
bogdanm | 86:04dd9b1680ae | 7168 | |
bogdanm | 86:04dd9b1680ae | 7169 | #define IS_ADC_COMMON_INSTANCE(INSTANCE) (((INSTANCE) == ADC1_2_COMMON)) |
bogdanm | 86:04dd9b1680ae | 7170 | |
bogdanm | 86:04dd9b1680ae | 7171 | /****************************** CAN Instances *********************************/ |
bogdanm | 86:04dd9b1680ae | 7172 | #define IS_CAN_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CAN) |
bogdanm | 86:04dd9b1680ae | 7173 | |
bogdanm | 86:04dd9b1680ae | 7174 | /****************************** COMP Instances ********************************/ |
bogdanm | 86:04dd9b1680ae | 7175 | #define IS_COMP_ALL_INSTANCE(INSTANCE) (((INSTANCE) == COMP2) || \ |
bogdanm | 86:04dd9b1680ae | 7176 | ((INSTANCE) == COMP4) || \ |
bogdanm | 86:04dd9b1680ae | 7177 | ((INSTANCE) == COMP6)) |
bogdanm | 86:04dd9b1680ae | 7178 | |
bogdanm | 86:04dd9b1680ae | 7179 | /******************** COMP Instances with switch on DAC1 Channel1 output ******/ |
bogdanm | 86:04dd9b1680ae | 7180 | #define IS_COMP_DAC1SWITCH_INSTANCE(INSTANCE) (0) |
bogdanm | 86:04dd9b1680ae | 7181 | |
bogdanm | 86:04dd9b1680ae | 7182 | /******************** COMP Instances with window mode capability **************/ |
bogdanm | 86:04dd9b1680ae | 7183 | #define IS_COMP_WINDOWMODE_INSTANCE(INSTANCE) (0) |
bogdanm | 86:04dd9b1680ae | 7184 | |
bogdanm | 86:04dd9b1680ae | 7185 | /****************************** CRC Instances *********************************/ |
bogdanm | 86:04dd9b1680ae | 7186 | #define IS_CRC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CRC) |
bogdanm | 86:04dd9b1680ae | 7187 | |
bogdanm | 86:04dd9b1680ae | 7188 | /****************************** DAC Instances *********************************/ |
bogdanm | 86:04dd9b1680ae | 7189 | #define IS_DAC_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DAC1) || \ |
bogdanm | 86:04dd9b1680ae | 7190 | ((INSTANCE) == DAC2)) |
bogdanm | 86:04dd9b1680ae | 7191 | |
bogdanm | 86:04dd9b1680ae | 7192 | #define IS_DAC_CHANNEL_INSTANCE(INSTANCE, CHANNEL) \ |
bogdanm | 86:04dd9b1680ae | 7193 | ((((INSTANCE) == DAC1) && \ |
bogdanm | 86:04dd9b1680ae | 7194 | (((CHANNEL) == DAC_CHANNEL_1) || \ |
bogdanm | 86:04dd9b1680ae | 7195 | ((CHANNEL) == DAC_CHANNEL_2))) \ |
bogdanm | 86:04dd9b1680ae | 7196 | || \ |
bogdanm | 86:04dd9b1680ae | 7197 | (((INSTANCE) == DAC2) && \ |
bogdanm | 86:04dd9b1680ae | 7198 | (((CHANNEL) == DAC_CHANNEL_1)))) |
bogdanm | 86:04dd9b1680ae | 7199 | |
bogdanm | 86:04dd9b1680ae | 7200 | /****************************** DMA Instances *********************************/ |
bogdanm | 86:04dd9b1680ae | 7201 | #define IS_DMA_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMA1_Channel1) || \ |
bogdanm | 86:04dd9b1680ae | 7202 | ((INSTANCE) == DMA1_Channel2) || \ |
bogdanm | 86:04dd9b1680ae | 7203 | ((INSTANCE) == DMA1_Channel3) || \ |
bogdanm | 86:04dd9b1680ae | 7204 | ((INSTANCE) == DMA1_Channel4) || \ |
bogdanm | 86:04dd9b1680ae | 7205 | ((INSTANCE) == DMA1_Channel5) || \ |
bogdanm | 86:04dd9b1680ae | 7206 | ((INSTANCE) == DMA1_Channel6) || \ |
bogdanm | 86:04dd9b1680ae | 7207 | ((INSTANCE) == DMA1_Channel7)) |
bogdanm | 86:04dd9b1680ae | 7208 | |
bogdanm | 86:04dd9b1680ae | 7209 | /****************************** GPIO Instances ********************************/ |
bogdanm | 86:04dd9b1680ae | 7210 | #define IS_GPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \ |
bogdanm | 86:04dd9b1680ae | 7211 | ((INSTANCE) == GPIOB) || \ |
bogdanm | 86:04dd9b1680ae | 7212 | ((INSTANCE) == GPIOC) || \ |
bogdanm | 86:04dd9b1680ae | 7213 | ((INSTANCE) == GPIOD) || \ |
bogdanm | 86:04dd9b1680ae | 7214 | ((INSTANCE) == GPIOF)) |
bogdanm | 86:04dd9b1680ae | 7215 | |
bogdanm | 86:04dd9b1680ae | 7216 | /****************************** HRTIM Instances *********************************/ |
bogdanm | 86:04dd9b1680ae | 7217 | #define IS_HRTIM_ALL_INSTANCE(INSTANCE) (((INSTANCE) == HRTIM1)) |
bogdanm | 86:04dd9b1680ae | 7218 | |
bogdanm | 86:04dd9b1680ae | 7219 | /****************************** I2C Instances *********************************/ |
bogdanm | 86:04dd9b1680ae | 7220 | #define IS_I2C_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1)) |
bogdanm | 86:04dd9b1680ae | 7221 | |
bogdanm | 86:04dd9b1680ae | 7222 | /****************************** IWDG Instances ********************************/ |
bogdanm | 86:04dd9b1680ae | 7223 | #define IS_IWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == IWDG) |
bogdanm | 86:04dd9b1680ae | 7224 | |
bogdanm | 86:04dd9b1680ae | 7225 | /****************************** OPAMP Instances *******************************/ |
bogdanm | 86:04dd9b1680ae | 7226 | #define IS_OPAMP_ALL_INSTANCE(INSTANCE) ((INSTANCE) == OPAMP2) |
bogdanm | 86:04dd9b1680ae | 7227 | |
bogdanm | 86:04dd9b1680ae | 7228 | /****************************** RTC Instances *********************************/ |
bogdanm | 86:04dd9b1680ae | 7229 | #define IS_RTC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == RTC) |
bogdanm | 86:04dd9b1680ae | 7230 | |
bogdanm | 86:04dd9b1680ae | 7231 | /****************************** SMBUS Instances *******************************/ |
bogdanm | 86:04dd9b1680ae | 7232 | #define IS_SMBUS_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1)) |
bogdanm | 86:04dd9b1680ae | 7233 | |
bogdanm | 86:04dd9b1680ae | 7234 | /****************************** SPI Instances *********************************/ |
bogdanm | 86:04dd9b1680ae | 7235 | #define IS_SPI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1)) |
bogdanm | 86:04dd9b1680ae | 7236 | |
bogdanm | 86:04dd9b1680ae | 7237 | /******************* TIM Instances : All supported instances ******************/ |
bogdanm | 86:04dd9b1680ae | 7238 | #define IS_TIM_INSTANCE(INSTANCE)\ |
bogdanm | 86:04dd9b1680ae | 7239 | (((INSTANCE) == TIM1) || \ |
bogdanm | 86:04dd9b1680ae | 7240 | ((INSTANCE) == TIM2) || \ |
bogdanm | 86:04dd9b1680ae | 7241 | ((INSTANCE) == TIM3) || \ |
bogdanm | 86:04dd9b1680ae | 7242 | ((INSTANCE) == TIM6) || \ |
bogdanm | 86:04dd9b1680ae | 7243 | ((INSTANCE) == TIM7) || \ |
bogdanm | 86:04dd9b1680ae | 7244 | ((INSTANCE) == TIM15) || \ |
bogdanm | 86:04dd9b1680ae | 7245 | ((INSTANCE) == TIM16) || \ |
bogdanm | 86:04dd9b1680ae | 7246 | ((INSTANCE) == TIM17)) |
bogdanm | 86:04dd9b1680ae | 7247 | |
bogdanm | 86:04dd9b1680ae | 7248 | /******************* TIM Instances : at least 1 capture/compare channel *******/ |
bogdanm | 86:04dd9b1680ae | 7249 | #define IS_TIM_CC1_INSTANCE(INSTANCE)\ |
bogdanm | 86:04dd9b1680ae | 7250 | (((INSTANCE) == TIM1) || \ |
bogdanm | 86:04dd9b1680ae | 7251 | ((INSTANCE) == TIM2) || \ |
bogdanm | 86:04dd9b1680ae | 7252 | ((INSTANCE) == TIM3) || \ |
bogdanm | 86:04dd9b1680ae | 7253 | ((INSTANCE) == TIM15) || \ |
bogdanm | 86:04dd9b1680ae | 7254 | ((INSTANCE) == TIM16) || \ |
bogdanm | 86:04dd9b1680ae | 7255 | ((INSTANCE) == TIM17)) |
bogdanm | 86:04dd9b1680ae | 7256 | |
bogdanm | 86:04dd9b1680ae | 7257 | /****************** TIM Instances : at least 2 capture/compare channels *******/ |
bogdanm | 86:04dd9b1680ae | 7258 | #define IS_TIM_CC2_INSTANCE(INSTANCE)\ |
bogdanm | 86:04dd9b1680ae | 7259 | (((INSTANCE) == TIM1) || \ |
bogdanm | 86:04dd9b1680ae | 7260 | ((INSTANCE) == TIM2) || \ |
bogdanm | 86:04dd9b1680ae | 7261 | ((INSTANCE) == TIM3) || \ |
bogdanm | 86:04dd9b1680ae | 7262 | ((INSTANCE) == TIM15)) |
bogdanm | 86:04dd9b1680ae | 7263 | |
bogdanm | 86:04dd9b1680ae | 7264 | /****************** TIM Instances : at least 3 capture/compare channels *******/ |
bogdanm | 86:04dd9b1680ae | 7265 | #define IS_TIM_CC3_INSTANCE(INSTANCE)\ |
bogdanm | 86:04dd9b1680ae | 7266 | (((INSTANCE) == TIM1) || \ |
bogdanm | 86:04dd9b1680ae | 7267 | ((INSTANCE) == TIM2) || \ |
bogdanm | 86:04dd9b1680ae | 7268 | ((INSTANCE) == TIM3)) |
bogdanm | 86:04dd9b1680ae | 7269 | |
bogdanm | 86:04dd9b1680ae | 7270 | /****************** TIM Instances : at least 4 capture/compare channels *******/ |
bogdanm | 86:04dd9b1680ae | 7271 | #define IS_TIM_CC4_INSTANCE(INSTANCE)\ |
bogdanm | 86:04dd9b1680ae | 7272 | (((INSTANCE) == TIM1) || \ |
bogdanm | 86:04dd9b1680ae | 7273 | ((INSTANCE) == TIM2) || \ |
bogdanm | 86:04dd9b1680ae | 7274 | ((INSTANCE) == TIM3)) |
bogdanm | 86:04dd9b1680ae | 7275 | |
bogdanm | 86:04dd9b1680ae | 7276 | /****************** TIM Instances : at least 5 capture/compare channels *******/ |
bogdanm | 86:04dd9b1680ae | 7277 | #define IS_TIM_CC5_INSTANCE(INSTANCE)\ |
bogdanm | 86:04dd9b1680ae | 7278 | (((INSTANCE) == TIM1)) |
bogdanm | 86:04dd9b1680ae | 7279 | |
bogdanm | 86:04dd9b1680ae | 7280 | /****************** TIM Instances : at least 6 capture/compare channels *******/ |
bogdanm | 86:04dd9b1680ae | 7281 | #define IS_TIM_CC6_INSTANCE(INSTANCE)\ |
bogdanm | 86:04dd9b1680ae | 7282 | (((INSTANCE) == TIM1)) |
bogdanm | 86:04dd9b1680ae | 7283 | |
bogdanm | 86:04dd9b1680ae | 7284 | /************************** TIM Instances : Advanced-control timers ***********/ |
bogdanm | 86:04dd9b1680ae | 7285 | |
bogdanm | 86:04dd9b1680ae | 7286 | /****************** TIM Instances : supporting clock selection ****************/ |
bogdanm | 86:04dd9b1680ae | 7287 | #define IS_TIM_CLOCK_SELECT_INSTANCE(INSTANCE)\ |
bogdanm | 86:04dd9b1680ae | 7288 | (((INSTANCE) == TIM1) || \ |
bogdanm | 86:04dd9b1680ae | 7289 | ((INSTANCE) == TIM2) || \ |
bogdanm | 86:04dd9b1680ae | 7290 | ((INSTANCE) == TIM3) || \ |
bogdanm | 86:04dd9b1680ae | 7291 | ((INSTANCE) == TIM15)) |
bogdanm | 86:04dd9b1680ae | 7292 | |
bogdanm | 86:04dd9b1680ae | 7293 | /****************** TIM Instances : supporting external clock mode 1 for ETRF input */ |
bogdanm | 86:04dd9b1680ae | 7294 | #define IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(INSTANCE)\ |
bogdanm | 86:04dd9b1680ae | 7295 | (((INSTANCE) == TIM1) || \ |
bogdanm | 86:04dd9b1680ae | 7296 | ((INSTANCE) == TIM2) || \ |
bogdanm | 86:04dd9b1680ae | 7297 | ((INSTANCE) == TIM3)) |
bogdanm | 86:04dd9b1680ae | 7298 | |
bogdanm | 86:04dd9b1680ae | 7299 | /****************** TIM Instances : supporting external clock mode 2 **********/ |
bogdanm | 86:04dd9b1680ae | 7300 | #define IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(INSTANCE)\ |
bogdanm | 86:04dd9b1680ae | 7301 | (((INSTANCE) == TIM1) || \ |
bogdanm | 86:04dd9b1680ae | 7302 | ((INSTANCE) == TIM2) || \ |
bogdanm | 86:04dd9b1680ae | 7303 | ((INSTANCE) == TIM3)) |
bogdanm | 86:04dd9b1680ae | 7304 | |
bogdanm | 86:04dd9b1680ae | 7305 | /****************** TIM Instances : supporting external clock mode 1 for TIX inputs*/ |
bogdanm | 86:04dd9b1680ae | 7306 | #define IS_TIM_CLOCKSOURCE_TIX_INSTANCE(INSTANCE)\ |
bogdanm | 86:04dd9b1680ae | 7307 | (((INSTANCE) == TIM1) || \ |
bogdanm | 86:04dd9b1680ae | 7308 | ((INSTANCE) == TIM2) || \ |
bogdanm | 86:04dd9b1680ae | 7309 | ((INSTANCE) == TIM3) || \ |
bogdanm | 86:04dd9b1680ae | 7310 | ((INSTANCE) == TIM15)) |
bogdanm | 86:04dd9b1680ae | 7311 | |
bogdanm | 86:04dd9b1680ae | 7312 | /****************** TIM Instances : supporting internal trigger inputs(ITRX) *******/ |
bogdanm | 86:04dd9b1680ae | 7313 | #define IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(INSTANCE)\ |
bogdanm | 86:04dd9b1680ae | 7314 | (((INSTANCE) == TIM1) || \ |
bogdanm | 86:04dd9b1680ae | 7315 | ((INSTANCE) == TIM2) || \ |
bogdanm | 86:04dd9b1680ae | 7316 | ((INSTANCE) == TIM3) || \ |
bogdanm | 86:04dd9b1680ae | 7317 | ((INSTANCE) == TIM15)) |
bogdanm | 86:04dd9b1680ae | 7318 | |
bogdanm | 86:04dd9b1680ae | 7319 | /****************** TIM Instances : supporting OCxREF clear *******************/ |
bogdanm | 86:04dd9b1680ae | 7320 | #define IS_TIM_OCXREF_CLEAR_INSTANCE(INSTANCE)\ |
bogdanm | 86:04dd9b1680ae | 7321 | (((INSTANCE) == TIM1) || \ |
bogdanm | 86:04dd9b1680ae | 7322 | ((INSTANCE) == TIM2) || \ |
bogdanm | 86:04dd9b1680ae | 7323 | ((INSTANCE) == TIM3)) |
bogdanm | 86:04dd9b1680ae | 7324 | |
bogdanm | 86:04dd9b1680ae | 7325 | /****************** TIM Instances : supporting encoder interface **************/ |
bogdanm | 86:04dd9b1680ae | 7326 | #define IS_TIM_ENCODER_INTERFACE_INSTANCE(INSTANCE)\ |
bogdanm | 86:04dd9b1680ae | 7327 | (((INSTANCE) == TIM1) || \ |
bogdanm | 86:04dd9b1680ae | 7328 | ((INSTANCE) == TIM2) || \ |
bogdanm | 86:04dd9b1680ae | 7329 | ((INSTANCE) == TIM3)) |
bogdanm | 86:04dd9b1680ae | 7330 | |
bogdanm | 86:04dd9b1680ae | 7331 | /****************** TIM Instances : supporting Hall interface *****************/ |
bogdanm | 86:04dd9b1680ae | 7332 | #define IS_TIM_HALL_INTERFACE_INSTANCE(INSTANCE)\ |
bogdanm | 86:04dd9b1680ae | 7333 | (((INSTANCE) == TIM1)) |
bogdanm | 86:04dd9b1680ae | 7334 | |
bogdanm | 86:04dd9b1680ae | 7335 | /****************** TIM Instances : supporting input XOR function *************/ |
bogdanm | 86:04dd9b1680ae | 7336 | #define IS_TIM_XOR_INSTANCE(INSTANCE)\ |
bogdanm | 86:04dd9b1680ae | 7337 | (((INSTANCE) == TIM1) || \ |
bogdanm | 86:04dd9b1680ae | 7338 | ((INSTANCE) == TIM2) || \ |
bogdanm | 86:04dd9b1680ae | 7339 | ((INSTANCE) == TIM3) || \ |
bogdanm | 86:04dd9b1680ae | 7340 | ((INSTANCE) == TIM15)) |
bogdanm | 86:04dd9b1680ae | 7341 | |
bogdanm | 86:04dd9b1680ae | 7342 | /****************** TIM Instances : supporting master mode ********************/ |
bogdanm | 86:04dd9b1680ae | 7343 | #define IS_TIM_MASTER_INSTANCE(INSTANCE)\ |
bogdanm | 86:04dd9b1680ae | 7344 | (((INSTANCE) == TIM1) || \ |
bogdanm | 86:04dd9b1680ae | 7345 | ((INSTANCE) == TIM2) || \ |
bogdanm | 86:04dd9b1680ae | 7346 | ((INSTANCE) == TIM3) || \ |
bogdanm | 86:04dd9b1680ae | 7347 | ((INSTANCE) == TIM6) || \ |
bogdanm | 86:04dd9b1680ae | 7348 | ((INSTANCE) == TIM7) || \ |
bogdanm | 86:04dd9b1680ae | 7349 | ((INSTANCE) == TIM15)) |
bogdanm | 86:04dd9b1680ae | 7350 | |
bogdanm | 86:04dd9b1680ae | 7351 | /****************** TIM Instances : supporting slave mode *********************/ |
bogdanm | 86:04dd9b1680ae | 7352 | #define IS_TIM_SLAVE_INSTANCE(INSTANCE)\ |
bogdanm | 86:04dd9b1680ae | 7353 | (((INSTANCE) == TIM1) || \ |
bogdanm | 86:04dd9b1680ae | 7354 | ((INSTANCE) == TIM2) || \ |
bogdanm | 86:04dd9b1680ae | 7355 | ((INSTANCE) == TIM3) || \ |
bogdanm | 86:04dd9b1680ae | 7356 | ((INSTANCE) == TIM15)) |
bogdanm | 86:04dd9b1680ae | 7357 | |
bogdanm | 86:04dd9b1680ae | 7358 | /****************** TIM Instances : supporting synchronization ****************/ |
bogdanm | 86:04dd9b1680ae | 7359 | #define IS_TIM_SYNCHRO_INSTANCE(INSTANCE)\ |
bogdanm | 86:04dd9b1680ae | 7360 | (((INSTANCE) == TIM1) || \ |
bogdanm | 86:04dd9b1680ae | 7361 | ((INSTANCE) == TIM2) || \ |
bogdanm | 86:04dd9b1680ae | 7362 | ((INSTANCE) == TIM3) || \ |
bogdanm | 86:04dd9b1680ae | 7363 | ((INSTANCE) == TIM6) || \ |
bogdanm | 86:04dd9b1680ae | 7364 | ((INSTANCE) == TIM7) || \ |
bogdanm | 86:04dd9b1680ae | 7365 | ((INSTANCE) == TIM15)) |
bogdanm | 86:04dd9b1680ae | 7366 | |
bogdanm | 86:04dd9b1680ae | 7367 | /****************** TIM Instances : supporting 32 bits counter ****************/ |
bogdanm | 86:04dd9b1680ae | 7368 | #define IS_TIM_32B_COUNTER_INSTANCE(INSTANCE)\ |
bogdanm | 86:04dd9b1680ae | 7369 | ((INSTANCE) == TIM2) |
bogdanm | 86:04dd9b1680ae | 7370 | |
bogdanm | 86:04dd9b1680ae | 7371 | /****************** TIM Instances : supporting DMA burst **********************/ |
bogdanm | 86:04dd9b1680ae | 7372 | #define IS_TIM_DMABURST_INSTANCE(INSTANCE)\ |
bogdanm | 86:04dd9b1680ae | 7373 | (((INSTANCE) == TIM1) || \ |
bogdanm | 86:04dd9b1680ae | 7374 | ((INSTANCE) == TIM2) || \ |
bogdanm | 86:04dd9b1680ae | 7375 | ((INSTANCE) == TIM3) || \ |
bogdanm | 86:04dd9b1680ae | 7376 | ((INSTANCE) == TIM15) || \ |
bogdanm | 86:04dd9b1680ae | 7377 | ((INSTANCE) == TIM16) || \ |
bogdanm | 86:04dd9b1680ae | 7378 | ((INSTANCE) == TIM17)) |
bogdanm | 86:04dd9b1680ae | 7379 | |
bogdanm | 86:04dd9b1680ae | 7380 | /****************** TIM Instances : supporting the break function *************/ |
bogdanm | 86:04dd9b1680ae | 7381 | #define IS_TIM_BREAK_INSTANCE(INSTANCE)\ |
bogdanm | 86:04dd9b1680ae | 7382 | (((INSTANCE) == TIM1) || \ |
bogdanm | 86:04dd9b1680ae | 7383 | ((INSTANCE) == TIM15) || \ |
bogdanm | 86:04dd9b1680ae | 7384 | ((INSTANCE) == TIM16) || \ |
bogdanm | 86:04dd9b1680ae | 7385 | ((INSTANCE) == TIM17)) |
bogdanm | 86:04dd9b1680ae | 7386 | |
bogdanm | 86:04dd9b1680ae | 7387 | /****************** TIM Instances : supporting input/output channel(s) ********/ |
bogdanm | 86:04dd9b1680ae | 7388 | #define IS_TIM_CCX_INSTANCE(INSTANCE, CHANNEL) \ |
bogdanm | 86:04dd9b1680ae | 7389 | ((((INSTANCE) == TIM1) && \ |
bogdanm | 86:04dd9b1680ae | 7390 | (((CHANNEL) == TIM_CHANNEL_1) || \ |
bogdanm | 86:04dd9b1680ae | 7391 | ((CHANNEL) == TIM_CHANNEL_2) || \ |
bogdanm | 86:04dd9b1680ae | 7392 | ((CHANNEL) == TIM_CHANNEL_3) || \ |
bogdanm | 86:04dd9b1680ae | 7393 | ((CHANNEL) == TIM_CHANNEL_4) || \ |
bogdanm | 86:04dd9b1680ae | 7394 | ((CHANNEL) == TIM_CHANNEL_5) || \ |
bogdanm | 86:04dd9b1680ae | 7395 | ((CHANNEL) == TIM_CHANNEL_6))) \ |
bogdanm | 86:04dd9b1680ae | 7396 | || \ |
bogdanm | 86:04dd9b1680ae | 7397 | (((INSTANCE) == TIM2) && \ |
bogdanm | 86:04dd9b1680ae | 7398 | (((CHANNEL) == TIM_CHANNEL_1) || \ |
bogdanm | 86:04dd9b1680ae | 7399 | ((CHANNEL) == TIM_CHANNEL_2) || \ |
bogdanm | 86:04dd9b1680ae | 7400 | ((CHANNEL) == TIM_CHANNEL_3) || \ |
bogdanm | 86:04dd9b1680ae | 7401 | ((CHANNEL) == TIM_CHANNEL_4))) \ |
bogdanm | 86:04dd9b1680ae | 7402 | || \ |
bogdanm | 86:04dd9b1680ae | 7403 | (((INSTANCE) == TIM3) && \ |
bogdanm | 86:04dd9b1680ae | 7404 | (((CHANNEL) == TIM_CHANNEL_1) || \ |
bogdanm | 86:04dd9b1680ae | 7405 | ((CHANNEL) == TIM_CHANNEL_2) || \ |
bogdanm | 86:04dd9b1680ae | 7406 | ((CHANNEL) == TIM_CHANNEL_3) || \ |
bogdanm | 86:04dd9b1680ae | 7407 | ((CHANNEL) == TIM_CHANNEL_4))) \ |
bogdanm | 86:04dd9b1680ae | 7408 | || \ |
bogdanm | 86:04dd9b1680ae | 7409 | (((INSTANCE) == TIM15) && \ |
bogdanm | 86:04dd9b1680ae | 7410 | (((CHANNEL) == TIM_CHANNEL_1) || \ |
bogdanm | 86:04dd9b1680ae | 7411 | ((CHANNEL) == TIM_CHANNEL_2))) \ |
bogdanm | 86:04dd9b1680ae | 7412 | || \ |
bogdanm | 86:04dd9b1680ae | 7413 | (((INSTANCE) == TIM16) && \ |
bogdanm | 86:04dd9b1680ae | 7414 | (((CHANNEL) == TIM_CHANNEL_1))) \ |
bogdanm | 86:04dd9b1680ae | 7415 | || \ |
bogdanm | 86:04dd9b1680ae | 7416 | (((INSTANCE) == TIM17) && \ |
bogdanm | 86:04dd9b1680ae | 7417 | (((CHANNEL) == TIM_CHANNEL_1)))) |
bogdanm | 86:04dd9b1680ae | 7418 | |
bogdanm | 86:04dd9b1680ae | 7419 | /****************** TIM Instances : supporting complementary output(s) ********/ |
bogdanm | 86:04dd9b1680ae | 7420 | #define IS_TIM_CCXN_INSTANCE(INSTANCE, CHANNEL) \ |
bogdanm | 86:04dd9b1680ae | 7421 | ((((INSTANCE) == TIM1) && \ |
bogdanm | 86:04dd9b1680ae | 7422 | (((CHANNEL) == TIM_CHANNEL_1) || \ |
bogdanm | 86:04dd9b1680ae | 7423 | ((CHANNEL) == TIM_CHANNEL_2) || \ |
bogdanm | 86:04dd9b1680ae | 7424 | ((CHANNEL) == TIM_CHANNEL_3))) \ |
bogdanm | 86:04dd9b1680ae | 7425 | || \ |
bogdanm | 86:04dd9b1680ae | 7426 | (((INSTANCE) == TIM15) && \ |
bogdanm | 86:04dd9b1680ae | 7427 | ((CHANNEL) == TIM_CHANNEL_1)) \ |
bogdanm | 86:04dd9b1680ae | 7428 | || \ |
bogdanm | 86:04dd9b1680ae | 7429 | (((INSTANCE) == TIM16) && \ |
bogdanm | 86:04dd9b1680ae | 7430 | ((CHANNEL) == TIM_CHANNEL_1)) \ |
bogdanm | 86:04dd9b1680ae | 7431 | || \ |
bogdanm | 86:04dd9b1680ae | 7432 | (((INSTANCE) == TIM17) && \ |
bogdanm | 86:04dd9b1680ae | 7433 | ((CHANNEL) == TIM_CHANNEL_1))) |
bogdanm | 86:04dd9b1680ae | 7434 | |
bogdanm | 86:04dd9b1680ae | 7435 | /****************** TIM Instances : supporting counting mode selection ********/ |
bogdanm | 86:04dd9b1680ae | 7436 | #define IS_TIM_COUNTER_MODE_SELECT_INSTANCE(INSTANCE)\ |
bogdanm | 86:04dd9b1680ae | 7437 | (((INSTANCE) == TIM1) || \ |
bogdanm | 86:04dd9b1680ae | 7438 | ((INSTANCE) == TIM2) || \ |
bogdanm | 86:04dd9b1680ae | 7439 | ((INSTANCE) == TIM3)) |
bogdanm | 86:04dd9b1680ae | 7440 | |
bogdanm | 86:04dd9b1680ae | 7441 | /****************** TIM Instances : supporting repetition counter *************/ |
bogdanm | 86:04dd9b1680ae | 7442 | #define IS_TIM_REPETITION_COUNTER_INSTANCE(INSTANCE)\ |
bogdanm | 86:04dd9b1680ae | 7443 | (((INSTANCE) == TIM1) || \ |
bogdanm | 86:04dd9b1680ae | 7444 | ((INSTANCE) == TIM15) || \ |
bogdanm | 86:04dd9b1680ae | 7445 | ((INSTANCE) == TIM16) || \ |
bogdanm | 86:04dd9b1680ae | 7446 | ((INSTANCE) == TIM17)) |
bogdanm | 86:04dd9b1680ae | 7447 | |
bogdanm | 86:04dd9b1680ae | 7448 | /****************** TIM Instances : supporting clock division *****************/ |
bogdanm | 86:04dd9b1680ae | 7449 | #define IS_TIM_CLOCK_DIVISION_INSTANCE(INSTANCE)\ |
bogdanm | 86:04dd9b1680ae | 7450 | (((INSTANCE) == TIM1) || \ |
bogdanm | 86:04dd9b1680ae | 7451 | ((INSTANCE) == TIM2) || \ |
bogdanm | 86:04dd9b1680ae | 7452 | ((INSTANCE) == TIM3) || \ |
bogdanm | 86:04dd9b1680ae | 7453 | ((INSTANCE) == TIM15) || \ |
bogdanm | 86:04dd9b1680ae | 7454 | ((INSTANCE) == TIM16) || \ |
bogdanm | 86:04dd9b1680ae | 7455 | ((INSTANCE) == TIM17)) |
bogdanm | 86:04dd9b1680ae | 7456 | |
bogdanm | 86:04dd9b1680ae | 7457 | /****************** TIM Instances : supporting 2 break inputs *****************/ |
bogdanm | 86:04dd9b1680ae | 7458 | #define IS_TIM_BKIN2_INSTANCE(INSTANCE)\ |
bogdanm | 86:04dd9b1680ae | 7459 | (((INSTANCE) == TIM1)) |
bogdanm | 86:04dd9b1680ae | 7460 | |
bogdanm | 86:04dd9b1680ae | 7461 | /****************** TIM Instances : supporting ADC triggering through TRGO2 ***/ |
bogdanm | 86:04dd9b1680ae | 7462 | #define IS_TIM_TRGO2_INSTANCE(INSTANCE)\ |
bogdanm | 86:04dd9b1680ae | 7463 | (((INSTANCE) == TIM1)) |
bogdanm | 86:04dd9b1680ae | 7464 | |
bogdanm | 86:04dd9b1680ae | 7465 | /****************** TIM Instances : supporting DMA generation on Update events*/ |
bogdanm | 86:04dd9b1680ae | 7466 | #define IS_TIM_DMA_INSTANCE(INSTANCE)\ |
bogdanm | 86:04dd9b1680ae | 7467 | (((INSTANCE) == TIM1) || \ |
bogdanm | 86:04dd9b1680ae | 7468 | ((INSTANCE) == TIM2) || \ |
bogdanm | 86:04dd9b1680ae | 7469 | ((INSTANCE) == TIM3) || \ |
bogdanm | 86:04dd9b1680ae | 7470 | ((INSTANCE) == TIM6) || \ |
bogdanm | 86:04dd9b1680ae | 7471 | ((INSTANCE) == TIM7) || \ |
bogdanm | 86:04dd9b1680ae | 7472 | ((INSTANCE) == TIM15) || \ |
bogdanm | 86:04dd9b1680ae | 7473 | ((INSTANCE) == TIM16) || \ |
bogdanm | 86:04dd9b1680ae | 7474 | ((INSTANCE) == TIM17)) |
bogdanm | 86:04dd9b1680ae | 7475 | |
bogdanm | 86:04dd9b1680ae | 7476 | /****************** TIM Instances : supporting DMA generation on Capture/Compare events */ |
bogdanm | 86:04dd9b1680ae | 7477 | #define IS_TIM_DMA_CC_INSTANCE(INSTANCE)\ |
bogdanm | 86:04dd9b1680ae | 7478 | (((INSTANCE) == TIM1) || \ |
bogdanm | 86:04dd9b1680ae | 7479 | ((INSTANCE) == TIM2) || \ |
bogdanm | 86:04dd9b1680ae | 7480 | ((INSTANCE) == TIM3) || \ |
bogdanm | 86:04dd9b1680ae | 7481 | ((INSTANCE) == TIM15) || \ |
bogdanm | 86:04dd9b1680ae | 7482 | ((INSTANCE) == TIM16) || \ |
bogdanm | 86:04dd9b1680ae | 7483 | ((INSTANCE) == TIM17)) |
bogdanm | 86:04dd9b1680ae | 7484 | |
bogdanm | 86:04dd9b1680ae | 7485 | /****************** TIM Instances : supporting commutation event generation ***/ |
bogdanm | 86:04dd9b1680ae | 7486 | #define IS_TIM_COMMUTATION_EVENT_INSTANCE(INSTANCE)\ |
bogdanm | 86:04dd9b1680ae | 7487 | (((INSTANCE) == TIM1) || \ |
bogdanm | 86:04dd9b1680ae | 7488 | ((INSTANCE) == TIM15) || \ |
bogdanm | 86:04dd9b1680ae | 7489 | ((INSTANCE) == TIM16) || \ |
bogdanm | 86:04dd9b1680ae | 7490 | ((INSTANCE) == TIM17)) |
bogdanm | 86:04dd9b1680ae | 7491 | |
bogdanm | 86:04dd9b1680ae | 7492 | /****************** TIM Instances : supporting remapping capability ***********/ |
bogdanm | 86:04dd9b1680ae | 7493 | #define IS_TIM_REMAP_INSTANCE(INSTANCE)\ |
bogdanm | 86:04dd9b1680ae | 7494 | (((INSTANCE) == TIM1) || \ |
bogdanm | 86:04dd9b1680ae | 7495 | ((INSTANCE) == TIM16)) |
bogdanm | 86:04dd9b1680ae | 7496 | |
bogdanm | 86:04dd9b1680ae | 7497 | /****************** TIM Instances : supporting combined 3-phase PWM mode ******/ |
bogdanm | 86:04dd9b1680ae | 7498 | #define IS_TIM_COMBINED3PHASEPWM_INSTANCE(INSTANCE) \ |
bogdanm | 86:04dd9b1680ae | 7499 | (((INSTANCE) == TIM1)) |
bogdanm | 86:04dd9b1680ae | 7500 | |
bogdanm | 86:04dd9b1680ae | 7501 | /****************************** TSC Instances *********************************/ |
bogdanm | 86:04dd9b1680ae | 7502 | #define IS_TSC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == TSC) |
bogdanm | 86:04dd9b1680ae | 7503 | |
bogdanm | 86:04dd9b1680ae | 7504 | /******************** USART Instances : Synchronous mode **********************/ |
bogdanm | 86:04dd9b1680ae | 7505 | #define IS_USART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \ |
bogdanm | 86:04dd9b1680ae | 7506 | ((INSTANCE) == USART2) || \ |
bogdanm | 86:04dd9b1680ae | 7507 | ((INSTANCE) == USART3)) |
bogdanm | 86:04dd9b1680ae | 7508 | |
bogdanm | 86:04dd9b1680ae | 7509 | /****************** USART Instances : Auto Baud Rate detection ****************/ |
bogdanm | 86:04dd9b1680ae | 7510 | #define IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(INSTANCE) ((INSTANCE) == USART1) |
bogdanm | 86:04dd9b1680ae | 7511 | |
bogdanm | 86:04dd9b1680ae | 7512 | /******************** UART Instances : Asynchronous mode **********************/ |
bogdanm | 86:04dd9b1680ae | 7513 | #define IS_UART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \ |
bogdanm | 86:04dd9b1680ae | 7514 | ((INSTANCE) == USART2) || \ |
bogdanm | 86:04dd9b1680ae | 7515 | ((INSTANCE) == USART3)) |
bogdanm | 86:04dd9b1680ae | 7516 | |
bogdanm | 86:04dd9b1680ae | 7517 | /******************** UART Instances : Half-Duplex mode **********************/ |
bogdanm | 86:04dd9b1680ae | 7518 | #define IS_UART_HALFDUPLEX_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \ |
bogdanm | 86:04dd9b1680ae | 7519 | ((INSTANCE) == USART2) || \ |
bogdanm | 86:04dd9b1680ae | 7520 | ((INSTANCE) == USART3)) |
bogdanm | 86:04dd9b1680ae | 7521 | |
bogdanm | 86:04dd9b1680ae | 7522 | /******************** UART Instances : LIN mode **********************/ |
bogdanm | 86:04dd9b1680ae | 7523 | #define IS_UART_LIN_INSTANCE(INSTANCE) ((INSTANCE) == USART1) |
bogdanm | 86:04dd9b1680ae | 7524 | |
bogdanm | 86:04dd9b1680ae | 7525 | /******************** UART Instances : Wake-up from Stop mode **********************/ |
bogdanm | 86:04dd9b1680ae | 7526 | #define IS_UART_WAKEUP_FROMSTOP_INSTANCE(INSTANCE) ((INSTANCE) == USART1) |
bogdanm | 86:04dd9b1680ae | 7527 | |
bogdanm | 86:04dd9b1680ae | 7528 | /****************** UART Instances : Hardware Flow control ********************/ |
bogdanm | 86:04dd9b1680ae | 7529 | #define IS_UART_HWFLOW_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \ |
bogdanm | 86:04dd9b1680ae | 7530 | ((INSTANCE) == USART2) || \ |
bogdanm | 86:04dd9b1680ae | 7531 | ((INSTANCE) == USART3)) |
bogdanm | 86:04dd9b1680ae | 7532 | |
bogdanm | 86:04dd9b1680ae | 7533 | /****************** UART Instances : Auto Baud Rate detection *****************/ |
bogdanm | 86:04dd9b1680ae | 7534 | #define IS_UART_AUTOBAUDRATE_DETECTION_INSTANCE(INSTANCE) ((INSTANCE) == USART1) |
bogdanm | 86:04dd9b1680ae | 7535 | |
bogdanm | 86:04dd9b1680ae | 7536 | /****************** UART Instances : Driver Enable ****************************/ |
bogdanm | 86:04dd9b1680ae | 7537 | #define IS_UART_DRIVER_ENABLE_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \ |
bogdanm | 86:04dd9b1680ae | 7538 | ((INSTANCE) == USART2) || \ |
bogdanm | 86:04dd9b1680ae | 7539 | ((INSTANCE) == USART3)) |
bogdanm | 86:04dd9b1680ae | 7540 | |
bogdanm | 86:04dd9b1680ae | 7541 | /********************* UART Instances : Smard card mode ***********************/ |
bogdanm | 86:04dd9b1680ae | 7542 | #define IS_SMARTCARD_INSTANCE(INSTANCE) ((INSTANCE) == USART1) |
bogdanm | 86:04dd9b1680ae | 7543 | |
bogdanm | 86:04dd9b1680ae | 7544 | /*********************** UART Instances : IRDA mode ***************************/ |
bogdanm | 86:04dd9b1680ae | 7545 | #define IS_IRDA_INSTANCE(INSTANCE) ((INSTANCE) == USART1) |
bogdanm | 86:04dd9b1680ae | 7546 | |
bogdanm | 86:04dd9b1680ae | 7547 | /****************************** WWDG Instances ********************************/ |
bogdanm | 86:04dd9b1680ae | 7548 | #define IS_WWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == WWDG) |
bogdanm | 86:04dd9b1680ae | 7549 | |
bogdanm | 86:04dd9b1680ae | 7550 | /** |
bogdanm | 86:04dd9b1680ae | 7551 | * @} |
bogdanm | 86:04dd9b1680ae | 7552 | */ |
bogdanm | 86:04dd9b1680ae | 7553 | |
bogdanm | 86:04dd9b1680ae | 7554 | |
bogdanm | 86:04dd9b1680ae | 7555 | /******************************************************************************/ |
bogdanm | 86:04dd9b1680ae | 7556 | /* For a painless codes migration between the STM32F3xx device product */ |
bogdanm | 86:04dd9b1680ae | 7557 | /* lines, the aliases defined below are put in place to overcome the */ |
bogdanm | 86:04dd9b1680ae | 7558 | /* differences in the interrupt handlers and IRQn definitions. */ |
bogdanm | 86:04dd9b1680ae | 7559 | /* No need to update developed interrupt code when moving across */ |
bogdanm | 86:04dd9b1680ae | 7560 | /* product lines within the same STM32F3 Family */ |
bogdanm | 86:04dd9b1680ae | 7561 | /******************************************************************************/ |
bogdanm | 86:04dd9b1680ae | 7562 | |
bogdanm | 86:04dd9b1680ae | 7563 | /* Aliases for __IRQn */ |
bogdanm | 86:04dd9b1680ae | 7564 | |
bogdanm | 86:04dd9b1680ae | 7565 | #define ADC1_IRQn ADC1_2_IRQn |
bogdanm | 86:04dd9b1680ae | 7566 | #define USB_HP_CAN_TX_IRQn CAN_TX_IRQn |
bogdanm | 86:04dd9b1680ae | 7567 | #define USB_LP_CAN_RX0_IRQn CAN_RX0_IRQn |
bogdanm | 86:04dd9b1680ae | 7568 | #define TIM15_IRQn TIM1_BRK_TIM15_IRQn |
bogdanm | 86:04dd9b1680ae | 7569 | #define TIM16_IRQn TIM1_UP_TIM16_IRQn |
bogdanm | 86:04dd9b1680ae | 7570 | #define TIM17_IRQn TIM1_TRG_COM_TIM17_IRQn |
bogdanm | 86:04dd9b1680ae | 7571 | #define COMP_IRQn COMP2_IRQn |
bogdanm | 86:04dd9b1680ae | 7572 | #define COMP1_2_3_IRQn COMP2_IRQn |
bogdanm | 86:04dd9b1680ae | 7573 | #define COMP1_2_IRQn COMP2_IRQn |
bogdanm | 86:04dd9b1680ae | 7574 | #define COMP4_5_6_IRQn COMP4_6_IRQn |
bogdanm | 86:04dd9b1680ae | 7575 | #define TIM6_DAC_IRQn TIM6_DAC1_IRQn |
bogdanm | 86:04dd9b1680ae | 7576 | |
bogdanm | 86:04dd9b1680ae | 7577 | /* Aliases for __IRQHandler */ |
bogdanm | 86:04dd9b1680ae | 7578 | #define ADC1_IRQHandler ADC1_2_IRQHandler |
bogdanm | 86:04dd9b1680ae | 7579 | #define USB_HP_CAN_TX_IRQHandler CAN_TX_IRQHandler |
bogdanm | 86:04dd9b1680ae | 7580 | #define USB_LP_CAN_RX0_IRQHandler CAN_RX0_IRQHandler |
bogdanm | 86:04dd9b1680ae | 7581 | #define TIM15_IRQHandler TIM1_BRK_TIM15_IRQHandler |
bogdanm | 86:04dd9b1680ae | 7582 | #define TIM16_IRQHandler TIM1_UP_TIM16_IRQHandler |
bogdanm | 86:04dd9b1680ae | 7583 | #define TIM17_IRQHandler TIM1_TRG_COM_TIM17_IRQHandler |
bogdanm | 86:04dd9b1680ae | 7584 | #define COMP_IRQHandler COMP2_IRQHandler |
bogdanm | 86:04dd9b1680ae | 7585 | #define COMP1_2_3_IRQHandler COMP2_IRQHandler |
bogdanm | 86:04dd9b1680ae | 7586 | #define COMP1_2_IRQHandler COMP2_IRQHandler |
bogdanm | 86:04dd9b1680ae | 7587 | #define COMP4_5_6_IRQHandler COMP4_6_IRQHandler |
bogdanm | 86:04dd9b1680ae | 7588 | #define TIM6_DAC_IRQHandler TIM6_DAC1_IRQHandler |
bogdanm | 86:04dd9b1680ae | 7589 | |
bogdanm | 86:04dd9b1680ae | 7590 | #ifdef __cplusplus |
bogdanm | 86:04dd9b1680ae | 7591 | } |
bogdanm | 86:04dd9b1680ae | 7592 | #endif /* __cplusplus */ |
bogdanm | 86:04dd9b1680ae | 7593 | |
bogdanm | 86:04dd9b1680ae | 7594 | #endif /* __STM32F334x8_H */ |
bogdanm | 86:04dd9b1680ae | 7595 | |
bogdanm | 86:04dd9b1680ae | 7596 | /** |
bogdanm | 86:04dd9b1680ae | 7597 | * @} |
bogdanm | 86:04dd9b1680ae | 7598 | */ |
bogdanm | 86:04dd9b1680ae | 7599 | |
bogdanm | 86:04dd9b1680ae | 7600 | /** |
bogdanm | 86:04dd9b1680ae | 7601 | * @} |
bogdanm | 86:04dd9b1680ae | 7602 | */ |
bogdanm | 86:04dd9b1680ae | 7603 | |
bogdanm | 86:04dd9b1680ae | 7604 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |