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TARGET_NUCLEO_F103RB/stm32f1xx_ll_sdmmc.h@98:01a414ca7d6d, 2015-04-08 (annotated)
- Committer:
- yusuke_kyo
- Date:
- Wed Apr 08 08:04:18 2015 +0000
- Revision:
- 98:01a414ca7d6d
- Parent:
- 96:487b796308b0
remove SerialHalfDuplex.h
Who changed what in which revision?
| User | Revision | Line number | New contents of line |
|---|---|---|---|
| Kojto | 96:487b796308b0 | 1 | /** |
| Kojto | 96:487b796308b0 | 2 | ****************************************************************************** |
| Kojto | 96:487b796308b0 | 3 | * @file stm32f1xx_ll_sdmmc.h |
| Kojto | 96:487b796308b0 | 4 | * @author MCD Application Team |
| Kojto | 96:487b796308b0 | 5 | * @version V1.0.0 |
| Kojto | 96:487b796308b0 | 6 | * @date 15-December-2014 |
| Kojto | 96:487b796308b0 | 7 | * @brief Header file of low layer SDMMC HAL module. |
| Kojto | 96:487b796308b0 | 8 | ****************************************************************************** |
| Kojto | 96:487b796308b0 | 9 | * @attention |
| Kojto | 96:487b796308b0 | 10 | * |
| Kojto | 96:487b796308b0 | 11 | * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2> |
| Kojto | 96:487b796308b0 | 12 | * |
| Kojto | 96:487b796308b0 | 13 | * Redistribution and use in source and binary forms, with or without modification, |
| Kojto | 96:487b796308b0 | 14 | * are permitted provided that the following conditions are met: |
| Kojto | 96:487b796308b0 | 15 | * 1. Redistributions of source code must retain the above copyright notice, |
| Kojto | 96:487b796308b0 | 16 | * this list of conditions and the following disclaimer. |
| Kojto | 96:487b796308b0 | 17 | * 2. Redistributions in binary form must reproduce the above copyright notice, |
| Kojto | 96:487b796308b0 | 18 | * this list of conditions and the following disclaimer in the documentation |
| Kojto | 96:487b796308b0 | 19 | * and/or other materials provided with the distribution. |
| Kojto | 96:487b796308b0 | 20 | * 3. Neither the name of STMicroelectronics nor the names of its contributors |
| Kojto | 96:487b796308b0 | 21 | * may be used to endorse or promote products derived from this software |
| Kojto | 96:487b796308b0 | 22 | * without specific prior written permission. |
| Kojto | 96:487b796308b0 | 23 | * |
| Kojto | 96:487b796308b0 | 24 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
| Kojto | 96:487b796308b0 | 25 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
| Kojto | 96:487b796308b0 | 26 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
| Kojto | 96:487b796308b0 | 27 | * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE |
| Kojto | 96:487b796308b0 | 28 | * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
| Kojto | 96:487b796308b0 | 29 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR |
| Kojto | 96:487b796308b0 | 30 | * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER |
| Kojto | 96:487b796308b0 | 31 | * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, |
| Kojto | 96:487b796308b0 | 32 | * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE |
| Kojto | 96:487b796308b0 | 33 | * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
| Kojto | 96:487b796308b0 | 34 | * |
| Kojto | 96:487b796308b0 | 35 | ****************************************************************************** |
| Kojto | 96:487b796308b0 | 36 | */ |
| Kojto | 96:487b796308b0 | 37 | |
| Kojto | 96:487b796308b0 | 38 | /* Define to prevent recursive inclusion -------------------------------------*/ |
| Kojto | 96:487b796308b0 | 39 | #ifndef __stm32f1xx_LL_SD_H |
| Kojto | 96:487b796308b0 | 40 | #define __stm32f1xx_LL_SD_H |
| Kojto | 96:487b796308b0 | 41 | |
| Kojto | 96:487b796308b0 | 42 | #if defined(STM32F103xE) || defined(STM32F103xG) |
| Kojto | 96:487b796308b0 | 43 | |
| Kojto | 96:487b796308b0 | 44 | #ifdef __cplusplus |
| Kojto | 96:487b796308b0 | 45 | extern "C" { |
| Kojto | 96:487b796308b0 | 46 | #endif |
| Kojto | 96:487b796308b0 | 47 | |
| Kojto | 96:487b796308b0 | 48 | /* Includes ------------------------------------------------------------------*/ |
| Kojto | 96:487b796308b0 | 49 | #include "stm32f1xx_hal_def.h" |
| Kojto | 96:487b796308b0 | 50 | |
| Kojto | 96:487b796308b0 | 51 | /** @addtogroup STM32F1xx_HAL_Driver |
| Kojto | 96:487b796308b0 | 52 | * @{ |
| Kojto | 96:487b796308b0 | 53 | */ |
| Kojto | 96:487b796308b0 | 54 | |
| Kojto | 96:487b796308b0 | 55 | /** @addtogroup SDMMC_LL |
| Kojto | 96:487b796308b0 | 56 | * @{ |
| Kojto | 96:487b796308b0 | 57 | */ |
| Kojto | 96:487b796308b0 | 58 | |
| Kojto | 96:487b796308b0 | 59 | /* Exported types ------------------------------------------------------------*/ |
| Kojto | 96:487b796308b0 | 60 | /** @defgroup SDMMC_LL_Exported_Types SDMMC_LL Exported Types |
| Kojto | 96:487b796308b0 | 61 | * @{ |
| Kojto | 96:487b796308b0 | 62 | */ |
| Kojto | 96:487b796308b0 | 63 | |
| Kojto | 96:487b796308b0 | 64 | /** |
| Kojto | 96:487b796308b0 | 65 | * @brief SDMMC Configuration Structure definition |
| Kojto | 96:487b796308b0 | 66 | */ |
| Kojto | 96:487b796308b0 | 67 | typedef struct |
| Kojto | 96:487b796308b0 | 68 | { |
| Kojto | 96:487b796308b0 | 69 | uint32_t ClockEdge; /*!< Specifies the clock transition on which the bit capture is made. |
| Kojto | 96:487b796308b0 | 70 | This parameter can be a value of @ref SDMMC_LL_Clock_Edge */ |
| Kojto | 96:487b796308b0 | 71 | |
| Kojto | 96:487b796308b0 | 72 | uint32_t ClockBypass; /*!< Specifies whether the SDIO Clock divider bypass is |
| Kojto | 96:487b796308b0 | 73 | enabled or disabled. |
| Kojto | 96:487b796308b0 | 74 | This parameter can be a value of @ref SDMMC_LL_Clock_Bypass */ |
| Kojto | 96:487b796308b0 | 75 | |
| Kojto | 96:487b796308b0 | 76 | uint32_t ClockPowerSave; /*!< Specifies whether SDIO Clock output is enabled or |
| Kojto | 96:487b796308b0 | 77 | disabled when the bus is idle. |
| Kojto | 96:487b796308b0 | 78 | This parameter can be a value of @ref SDMMC_LL_Clock_Power_Save */ |
| Kojto | 96:487b796308b0 | 79 | |
| Kojto | 96:487b796308b0 | 80 | uint32_t BusWide; /*!< Specifies the SDIO bus width. |
| Kojto | 96:487b796308b0 | 81 | This parameter can be a value of @ref SDMMC_LL_Bus_Wide */ |
| Kojto | 96:487b796308b0 | 82 | |
| Kojto | 96:487b796308b0 | 83 | uint32_t HardwareFlowControl; /*!< Specifies whether the SDIO hardware flow control is enabled or disabled. |
| Kojto | 96:487b796308b0 | 84 | This parameter can be a value of @ref SDMMC_LL_Hardware_Flow_Control */ |
| Kojto | 96:487b796308b0 | 85 | |
| Kojto | 96:487b796308b0 | 86 | uint32_t ClockDiv; /*!< Specifies the clock frequency of the SDIO controller. |
| Kojto | 96:487b796308b0 | 87 | This parameter can be a value between Min_Data = 0 and Max_Data = 255 */ |
| Kojto | 96:487b796308b0 | 88 | |
| Kojto | 96:487b796308b0 | 89 | }SDIO_InitTypeDef; |
| Kojto | 96:487b796308b0 | 90 | |
| Kojto | 96:487b796308b0 | 91 | |
| Kojto | 96:487b796308b0 | 92 | /** |
| Kojto | 96:487b796308b0 | 93 | * @brief SDIO Command Control structure |
| Kojto | 96:487b796308b0 | 94 | */ |
| Kojto | 96:487b796308b0 | 95 | typedef struct |
| Kojto | 96:487b796308b0 | 96 | { |
| Kojto | 96:487b796308b0 | 97 | uint32_t Argument; /*!< Specifies the SDIO command argument which is sent |
| Kojto | 96:487b796308b0 | 98 | to a card as part of a command message. If a command |
| Kojto | 96:487b796308b0 | 99 | contains an argument, it must be loaded into this register |
| Kojto | 96:487b796308b0 | 100 | before writing the command to the command register. */ |
| Kojto | 96:487b796308b0 | 101 | |
| Kojto | 96:487b796308b0 | 102 | uint32_t CmdIndex; /*!< Specifies the SDIO command index. It must be Min_Data = 0 and |
| Kojto | 96:487b796308b0 | 103 | Max_Data = 64 */ |
| Kojto | 96:487b796308b0 | 104 | |
| Kojto | 96:487b796308b0 | 105 | uint32_t Response; /*!< Specifies the SDIO response type. |
| Kojto | 96:487b796308b0 | 106 | This parameter can be a value of @ref SDMMC_LL_Response_Type */ |
| Kojto | 96:487b796308b0 | 107 | |
| Kojto | 96:487b796308b0 | 108 | uint32_t WaitForInterrupt; /*!< Specifies whether SDIO wait for interrupt request is |
| Kojto | 96:487b796308b0 | 109 | enabled or disabled. |
| Kojto | 96:487b796308b0 | 110 | This parameter can be a value of @ref SDMMC_LL_Wait_Interrupt_State */ |
| Kojto | 96:487b796308b0 | 111 | |
| Kojto | 96:487b796308b0 | 112 | uint32_t CPSM; /*!< Specifies whether SDIO Command path state machine (CPSM) |
| Kojto | 96:487b796308b0 | 113 | is enabled or disabled. |
| Kojto | 96:487b796308b0 | 114 | This parameter can be a value of @ref SDMMC_LL_CPSM_State */ |
| Kojto | 96:487b796308b0 | 115 | }SDIO_CmdInitTypeDef; |
| Kojto | 96:487b796308b0 | 116 | |
| Kojto | 96:487b796308b0 | 117 | |
| Kojto | 96:487b796308b0 | 118 | /** |
| Kojto | 96:487b796308b0 | 119 | * @brief SDIO Data Control structure |
| Kojto | 96:487b796308b0 | 120 | */ |
| Kojto | 96:487b796308b0 | 121 | typedef struct |
| Kojto | 96:487b796308b0 | 122 | { |
| Kojto | 96:487b796308b0 | 123 | uint32_t DataTimeOut; /*!< Specifies the data timeout period in card bus clock periods. */ |
| Kojto | 96:487b796308b0 | 124 | |
| Kojto | 96:487b796308b0 | 125 | uint32_t DataLength; /*!< Specifies the number of data bytes to be transferred. */ |
| Kojto | 96:487b796308b0 | 126 | |
| Kojto | 96:487b796308b0 | 127 | uint32_t DataBlockSize; /*!< Specifies the data block size for block transfer. |
| Kojto | 96:487b796308b0 | 128 | This parameter can be a value of @ref SDMMC_LL_Data_Block_Size */ |
| Kojto | 96:487b796308b0 | 129 | |
| Kojto | 96:487b796308b0 | 130 | uint32_t TransferDir; /*!< Specifies the data transfer direction, whether the transfer |
| Kojto | 96:487b796308b0 | 131 | is a read or write. |
| Kojto | 96:487b796308b0 | 132 | This parameter can be a value of @ref SDMMC_LL_Transfer_Direction */ |
| Kojto | 96:487b796308b0 | 133 | |
| Kojto | 96:487b796308b0 | 134 | uint32_t TransferMode; /*!< Specifies whether data transfer is in stream or block mode. |
| Kojto | 96:487b796308b0 | 135 | This parameter can be a value of @ref SDMMC_LL_Transfer_Type */ |
| Kojto | 96:487b796308b0 | 136 | |
| Kojto | 96:487b796308b0 | 137 | uint32_t DPSM; /*!< Specifies whether SDIO Data path state machine (DPSM) |
| Kojto | 96:487b796308b0 | 138 | is enabled or disabled. |
| Kojto | 96:487b796308b0 | 139 | This parameter can be a value of @ref SDMMC_LL_DPSM_State */ |
| Kojto | 96:487b796308b0 | 140 | }SDIO_DataInitTypeDef; |
| Kojto | 96:487b796308b0 | 141 | |
| Kojto | 96:487b796308b0 | 142 | /** |
| Kojto | 96:487b796308b0 | 143 | * @} |
| Kojto | 96:487b796308b0 | 144 | */ |
| Kojto | 96:487b796308b0 | 145 | |
| Kojto | 96:487b796308b0 | 146 | /* Exported constants --------------------------------------------------------*/ |
| Kojto | 96:487b796308b0 | 147 | /** @defgroup SDMMC_LL_Exported_Constants SDMMC_LL Exported Constants |
| Kojto | 96:487b796308b0 | 148 | * @{ |
| Kojto | 96:487b796308b0 | 149 | */ |
| Kojto | 96:487b796308b0 | 150 | |
| Kojto | 96:487b796308b0 | 151 | /** @defgroup SDMMC_LL_Clock_Edge Clock Edge |
| Kojto | 96:487b796308b0 | 152 | * @{ |
| Kojto | 96:487b796308b0 | 153 | */ |
| Kojto | 96:487b796308b0 | 154 | #define SDIO_CLOCK_EDGE_RISING ((uint32_t)0x00000000) |
| Kojto | 96:487b796308b0 | 155 | #define SDIO_CLOCK_EDGE_FALLING SDIO_CLKCR_NEGEDGE |
| Kojto | 96:487b796308b0 | 156 | |
| Kojto | 96:487b796308b0 | 157 | #define IS_SDIO_CLOCK_EDGE(EDGE) (((EDGE) == SDIO_CLOCK_EDGE_RISING) || \ |
| Kojto | 96:487b796308b0 | 158 | ((EDGE) == SDIO_CLOCK_EDGE_FALLING)) |
| Kojto | 96:487b796308b0 | 159 | /** |
| Kojto | 96:487b796308b0 | 160 | * @} |
| Kojto | 96:487b796308b0 | 161 | */ |
| Kojto | 96:487b796308b0 | 162 | |
| Kojto | 96:487b796308b0 | 163 | /** @defgroup SDMMC_LL_Clock_Bypass Clock Bypass |
| Kojto | 96:487b796308b0 | 164 | * @{ |
| Kojto | 96:487b796308b0 | 165 | */ |
| Kojto | 96:487b796308b0 | 166 | #define SDIO_CLOCK_BYPASS_DISABLE ((uint32_t)0x00000000) |
| Kojto | 96:487b796308b0 | 167 | #define SDIO_CLOCK_BYPASS_ENABLE SDIO_CLKCR_BYPASS |
| Kojto | 96:487b796308b0 | 168 | |
| Kojto | 96:487b796308b0 | 169 | #define IS_SDIO_CLOCK_BYPASS(BYPASS) (((BYPASS) == SDIO_CLOCK_BYPASS_DISABLE) || \ |
| Kojto | 96:487b796308b0 | 170 | ((BYPASS) == SDIO_CLOCK_BYPASS_ENABLE)) |
| Kojto | 96:487b796308b0 | 171 | /** |
| Kojto | 96:487b796308b0 | 172 | * @} |
| Kojto | 96:487b796308b0 | 173 | */ |
| Kojto | 96:487b796308b0 | 174 | |
| Kojto | 96:487b796308b0 | 175 | /** @defgroup SDMMC_LL_Clock_Power_Save Clock Power Saving |
| Kojto | 96:487b796308b0 | 176 | * @{ |
| Kojto | 96:487b796308b0 | 177 | */ |
| Kojto | 96:487b796308b0 | 178 | #define SDIO_CLOCK_POWER_SAVE_DISABLE ((uint32_t)0x00000000) |
| Kojto | 96:487b796308b0 | 179 | #define SDIO_CLOCK_POWER_SAVE_ENABLE SDIO_CLKCR_PWRSAV |
| Kojto | 96:487b796308b0 | 180 | |
| Kojto | 96:487b796308b0 | 181 | #define IS_SDIO_CLOCK_POWER_SAVE(SAVE) (((SAVE) == SDIO_CLOCK_POWER_SAVE_DISABLE) || \ |
| Kojto | 96:487b796308b0 | 182 | ((SAVE) == SDIO_CLOCK_POWER_SAVE_ENABLE)) |
| Kojto | 96:487b796308b0 | 183 | /** |
| Kojto | 96:487b796308b0 | 184 | * @} |
| Kojto | 96:487b796308b0 | 185 | */ |
| Kojto | 96:487b796308b0 | 186 | |
| Kojto | 96:487b796308b0 | 187 | /** @defgroup SDMMC_LL_Bus_Wide Bus Width |
| Kojto | 96:487b796308b0 | 188 | * @{ |
| Kojto | 96:487b796308b0 | 189 | */ |
| Kojto | 96:487b796308b0 | 190 | #define SDIO_BUS_WIDE_1B ((uint32_t)0x00000000) |
| Kojto | 96:487b796308b0 | 191 | #define SDIO_BUS_WIDE_4B SDIO_CLKCR_WIDBUS_0 |
| Kojto | 96:487b796308b0 | 192 | #define SDIO_BUS_WIDE_8B SDIO_CLKCR_WIDBUS_1 |
| Kojto | 96:487b796308b0 | 193 | |
| Kojto | 96:487b796308b0 | 194 | #define IS_SDIO_BUS_WIDE(WIDE) (((WIDE) == SDIO_BUS_WIDE_1B) || \ |
| Kojto | 96:487b796308b0 | 195 | ((WIDE) == SDIO_BUS_WIDE_4B) || \ |
| Kojto | 96:487b796308b0 | 196 | ((WIDE) == SDIO_BUS_WIDE_8B)) |
| Kojto | 96:487b796308b0 | 197 | /** |
| Kojto | 96:487b796308b0 | 198 | * @} |
| Kojto | 96:487b796308b0 | 199 | */ |
| Kojto | 96:487b796308b0 | 200 | |
| Kojto | 96:487b796308b0 | 201 | /** @defgroup SDMMC_LL_Hardware_Flow_Control Hardware Flow Control |
| Kojto | 96:487b796308b0 | 202 | * @{ |
| Kojto | 96:487b796308b0 | 203 | */ |
| Kojto | 96:487b796308b0 | 204 | #define SDIO_HARDWARE_FLOW_CONTROL_DISABLE ((uint32_t)0x00000000) |
| Kojto | 96:487b796308b0 | 205 | #define SDIO_HARDWARE_FLOW_CONTROL_ENABLE SDIO_CLKCR_HWFC_EN |
| Kojto | 96:487b796308b0 | 206 | |
| Kojto | 96:487b796308b0 | 207 | #define IS_SDIO_HARDWARE_FLOW_CONTROL(CONTROL) (((CONTROL) == SDIO_HARDWARE_FLOW_CONTROL_DISABLE) || \ |
| Kojto | 96:487b796308b0 | 208 | ((CONTROL) == SDIO_HARDWARE_FLOW_CONTROL_ENABLE)) |
| Kojto | 96:487b796308b0 | 209 | /** |
| Kojto | 96:487b796308b0 | 210 | * @} |
| Kojto | 96:487b796308b0 | 211 | */ |
| Kojto | 96:487b796308b0 | 212 | |
| Kojto | 96:487b796308b0 | 213 | /** @defgroup SDMMC_LL_Clock_Division Clock Division |
| Kojto | 96:487b796308b0 | 214 | * @{ |
| Kojto | 96:487b796308b0 | 215 | */ |
| Kojto | 96:487b796308b0 | 216 | #define IS_SDIO_CLKDIV(DIV) ((DIV) <= 0xFF) |
| Kojto | 96:487b796308b0 | 217 | /** |
| Kojto | 96:487b796308b0 | 218 | * @} |
| Kojto | 96:487b796308b0 | 219 | */ |
| Kojto | 96:487b796308b0 | 220 | |
| Kojto | 96:487b796308b0 | 221 | /** @defgroup SDMMC_LL_Command_Index Command Index |
| Kojto | 96:487b796308b0 | 222 | * @{ |
| Kojto | 96:487b796308b0 | 223 | */ |
| Kojto | 96:487b796308b0 | 224 | #define IS_SDIO_CMD_INDEX(INDEX) ((INDEX) < 0x40) |
| Kojto | 96:487b796308b0 | 225 | /** |
| Kojto | 96:487b796308b0 | 226 | * @} |
| Kojto | 96:487b796308b0 | 227 | */ |
| Kojto | 96:487b796308b0 | 228 | |
| Kojto | 96:487b796308b0 | 229 | /** @defgroup SDMMC_LL_Response_Type Response Type |
| Kojto | 96:487b796308b0 | 230 | * @{ |
| Kojto | 96:487b796308b0 | 231 | */ |
| Kojto | 96:487b796308b0 | 232 | #define SDIO_RESPONSE_NO ((uint32_t)0x00000000) |
| Kojto | 96:487b796308b0 | 233 | #define SDIO_RESPONSE_SHORT SDIO_CMD_WAITRESP_0 |
| Kojto | 96:487b796308b0 | 234 | #define SDIO_RESPONSE_LONG SDIO_CMD_WAITRESP |
| Kojto | 96:487b796308b0 | 235 | |
| Kojto | 96:487b796308b0 | 236 | #define IS_SDIO_RESPONSE(RESPONSE) (((RESPONSE) == SDIO_RESPONSE_NO) || \ |
| Kojto | 96:487b796308b0 | 237 | ((RESPONSE) == SDIO_RESPONSE_SHORT) || \ |
| Kojto | 96:487b796308b0 | 238 | ((RESPONSE) == SDIO_RESPONSE_LONG)) |
| Kojto | 96:487b796308b0 | 239 | /** |
| Kojto | 96:487b796308b0 | 240 | * @} |
| Kojto | 96:487b796308b0 | 241 | */ |
| Kojto | 96:487b796308b0 | 242 | |
| Kojto | 96:487b796308b0 | 243 | /** @defgroup SDMMC_LL_Wait_Interrupt_State Wait Interrupt |
| Kojto | 96:487b796308b0 | 244 | * @{ |
| Kojto | 96:487b796308b0 | 245 | */ |
| Kojto | 96:487b796308b0 | 246 | #define SDIO_WAIT_NO ((uint32_t)0x00000000) |
| Kojto | 96:487b796308b0 | 247 | #define SDIO_WAIT_IT SDIO_CMD_WAITINT |
| Kojto | 96:487b796308b0 | 248 | #define SDIO_WAIT_PEND SDIO_CMD_WAITPEND |
| Kojto | 96:487b796308b0 | 249 | |
| Kojto | 96:487b796308b0 | 250 | #define IS_SDIO_WAIT(WAIT) (((WAIT) == SDIO_WAIT_NO) || \ |
| Kojto | 96:487b796308b0 | 251 | ((WAIT) == SDIO_WAIT_IT) || \ |
| Kojto | 96:487b796308b0 | 252 | ((WAIT) == SDIO_WAIT_PEND)) |
| Kojto | 96:487b796308b0 | 253 | /** |
| Kojto | 96:487b796308b0 | 254 | * @} |
| Kojto | 96:487b796308b0 | 255 | */ |
| Kojto | 96:487b796308b0 | 256 | |
| Kojto | 96:487b796308b0 | 257 | /** @defgroup SDMMC_LL_CPSM_State CPSM State |
| Kojto | 96:487b796308b0 | 258 | * @{ |
| Kojto | 96:487b796308b0 | 259 | */ |
| Kojto | 96:487b796308b0 | 260 | #define SDIO_CPSM_DISABLE ((uint32_t)0x00000000) |
| Kojto | 96:487b796308b0 | 261 | #define SDIO_CPSM_ENABLE SDIO_CMD_CPSMEN |
| Kojto | 96:487b796308b0 | 262 | |
| Kojto | 96:487b796308b0 | 263 | #define IS_SDIO_CPSM(CPSM) (((CPSM) == SDIO_CPSM_DISABLE) || \ |
| Kojto | 96:487b796308b0 | 264 | ((CPSM) == SDIO_CPSM_ENABLE)) |
| Kojto | 96:487b796308b0 | 265 | /** |
| Kojto | 96:487b796308b0 | 266 | * @} |
| Kojto | 96:487b796308b0 | 267 | */ |
| Kojto | 96:487b796308b0 | 268 | |
| Kojto | 96:487b796308b0 | 269 | /** @defgroup SDMMC_LL_Response_Registers Response Register |
| Kojto | 96:487b796308b0 | 270 | * @{ |
| Kojto | 96:487b796308b0 | 271 | */ |
| Kojto | 96:487b796308b0 | 272 | #define SDIO_RESP1 ((uint32_t)0x00000000) |
| Kojto | 96:487b796308b0 | 273 | #define SDIO_RESP2 ((uint32_t)0x00000004) |
| Kojto | 96:487b796308b0 | 274 | #define SDIO_RESP3 ((uint32_t)0x00000008) |
| Kojto | 96:487b796308b0 | 275 | #define SDIO_RESP4 ((uint32_t)0x0000000C) |
| Kojto | 96:487b796308b0 | 276 | |
| Kojto | 96:487b796308b0 | 277 | #define IS_SDIO_RESP(RESP) (((RESP) == SDIO_RESP1) || \ |
| Kojto | 96:487b796308b0 | 278 | ((RESP) == SDIO_RESP2) || \ |
| Kojto | 96:487b796308b0 | 279 | ((RESP) == SDIO_RESP3) || \ |
| Kojto | 96:487b796308b0 | 280 | ((RESP) == SDIO_RESP4)) |
| Kojto | 96:487b796308b0 | 281 | /** |
| Kojto | 96:487b796308b0 | 282 | * @} |
| Kojto | 96:487b796308b0 | 283 | */ |
| Kojto | 96:487b796308b0 | 284 | |
| Kojto | 96:487b796308b0 | 285 | /** @defgroup SDMMC_LL_Data_Length Data Lenght |
| Kojto | 96:487b796308b0 | 286 | * @{ |
| Kojto | 96:487b796308b0 | 287 | */ |
| Kojto | 96:487b796308b0 | 288 | #define IS_SDIO_DATA_LENGTH(LENGTH) ((LENGTH) <= 0x01FFFFFF) |
| Kojto | 96:487b796308b0 | 289 | /** |
| Kojto | 96:487b796308b0 | 290 | * @} |
| Kojto | 96:487b796308b0 | 291 | */ |
| Kojto | 96:487b796308b0 | 292 | |
| Kojto | 96:487b796308b0 | 293 | /** @defgroup SDMMC_LL_Data_Block_Size Data Block Size |
| Kojto | 96:487b796308b0 | 294 | * @{ |
| Kojto | 96:487b796308b0 | 295 | */ |
| Kojto | 96:487b796308b0 | 296 | #define SDIO_DATABLOCK_SIZE_1B ((uint32_t)0x00000000) |
| Kojto | 96:487b796308b0 | 297 | #define SDIO_DATABLOCK_SIZE_2B SDIO_DCTRL_DBLOCKSIZE_0 |
| Kojto | 96:487b796308b0 | 298 | #define SDIO_DATABLOCK_SIZE_4B SDIO_DCTRL_DBLOCKSIZE_1 |
| Kojto | 96:487b796308b0 | 299 | #define SDIO_DATABLOCK_SIZE_8B (SDIO_DCTRL_DBLOCKSIZE_0|SDIO_DCTRL_DBLOCKSIZE_1) |
| Kojto | 96:487b796308b0 | 300 | #define SDIO_DATABLOCK_SIZE_16B SDIO_DCTRL_DBLOCKSIZE_2 |
| Kojto | 96:487b796308b0 | 301 | #define SDIO_DATABLOCK_SIZE_32B (SDIO_DCTRL_DBLOCKSIZE_0|SDIO_DCTRL_DBLOCKSIZE_2) |
| Kojto | 96:487b796308b0 | 302 | #define SDIO_DATABLOCK_SIZE_64B (SDIO_DCTRL_DBLOCKSIZE_1|SDIO_DCTRL_DBLOCKSIZE_2) |
| Kojto | 96:487b796308b0 | 303 | #define SDIO_DATABLOCK_SIZE_128B (SDIO_DCTRL_DBLOCKSIZE_0|SDIO_DCTRL_DBLOCKSIZE_1|SDIO_DCTRL_DBLOCKSIZE_2) |
| Kojto | 96:487b796308b0 | 304 | #define SDIO_DATABLOCK_SIZE_256B SDIO_DCTRL_DBLOCKSIZE_3 |
| Kojto | 96:487b796308b0 | 305 | #define SDIO_DATABLOCK_SIZE_512B (SDIO_DCTRL_DBLOCKSIZE_0|SDIO_DCTRL_DBLOCKSIZE_3) |
| Kojto | 96:487b796308b0 | 306 | #define SDIO_DATABLOCK_SIZE_1024B (SDIO_DCTRL_DBLOCKSIZE_1|SDIO_DCTRL_DBLOCKSIZE_3) |
| Kojto | 96:487b796308b0 | 307 | #define SDIO_DATABLOCK_SIZE_2048B (SDIO_DCTRL_DBLOCKSIZE_0|SDIO_DCTRL_DBLOCKSIZE_1|SDIO_DCTRL_DBLOCKSIZE_3) |
| Kojto | 96:487b796308b0 | 308 | #define SDIO_DATABLOCK_SIZE_4096B (SDIO_DCTRL_DBLOCKSIZE_2|SDIO_DCTRL_DBLOCKSIZE_3) |
| Kojto | 96:487b796308b0 | 309 | #define SDIO_DATABLOCK_SIZE_8192B (SDIO_DCTRL_DBLOCKSIZE_0|SDIO_DCTRL_DBLOCKSIZE_2|SDIO_DCTRL_DBLOCKSIZE_3) |
| Kojto | 96:487b796308b0 | 310 | #define SDIO_DATABLOCK_SIZE_16384B (SDIO_DCTRL_DBLOCKSIZE_1|SDIO_DCTRL_DBLOCKSIZE_2|SDIO_DCTRL_DBLOCKSIZE_3) |
| Kojto | 96:487b796308b0 | 311 | |
| Kojto | 96:487b796308b0 | 312 | #define IS_SDIO_BLOCK_SIZE(SIZE) (((SIZE) == SDIO_DATABLOCK_SIZE_1B) || \ |
| Kojto | 96:487b796308b0 | 313 | ((SIZE) == SDIO_DATABLOCK_SIZE_2B) || \ |
| Kojto | 96:487b796308b0 | 314 | ((SIZE) == SDIO_DATABLOCK_SIZE_4B) || \ |
| Kojto | 96:487b796308b0 | 315 | ((SIZE) == SDIO_DATABLOCK_SIZE_8B) || \ |
| Kojto | 96:487b796308b0 | 316 | ((SIZE) == SDIO_DATABLOCK_SIZE_16B) || \ |
| Kojto | 96:487b796308b0 | 317 | ((SIZE) == SDIO_DATABLOCK_SIZE_32B) || \ |
| Kojto | 96:487b796308b0 | 318 | ((SIZE) == SDIO_DATABLOCK_SIZE_64B) || \ |
| Kojto | 96:487b796308b0 | 319 | ((SIZE) == SDIO_DATABLOCK_SIZE_128B) || \ |
| Kojto | 96:487b796308b0 | 320 | ((SIZE) == SDIO_DATABLOCK_SIZE_256B) || \ |
| Kojto | 96:487b796308b0 | 321 | ((SIZE) == SDIO_DATABLOCK_SIZE_512B) || \ |
| Kojto | 96:487b796308b0 | 322 | ((SIZE) == SDIO_DATABLOCK_SIZE_1024B) || \ |
| Kojto | 96:487b796308b0 | 323 | ((SIZE) == SDIO_DATABLOCK_SIZE_2048B) || \ |
| Kojto | 96:487b796308b0 | 324 | ((SIZE) == SDIO_DATABLOCK_SIZE_4096B) || \ |
| Kojto | 96:487b796308b0 | 325 | ((SIZE) == SDIO_DATABLOCK_SIZE_8192B) || \ |
| Kojto | 96:487b796308b0 | 326 | ((SIZE) == SDIO_DATABLOCK_SIZE_16384B)) |
| Kojto | 96:487b796308b0 | 327 | /** |
| Kojto | 96:487b796308b0 | 328 | * @} |
| Kojto | 96:487b796308b0 | 329 | */ |
| Kojto | 96:487b796308b0 | 330 | |
| Kojto | 96:487b796308b0 | 331 | /** @defgroup SDMMC_LL_Transfer_Direction Transfer Direction |
| Kojto | 96:487b796308b0 | 332 | * @{ |
| Kojto | 96:487b796308b0 | 333 | */ |
| Kojto | 96:487b796308b0 | 334 | #define SDIO_TRANSFER_DIR_TO_CARD ((uint32_t)0x00000000) |
| Kojto | 96:487b796308b0 | 335 | #define SDIO_TRANSFER_DIR_TO_SDIO SDIO_DCTRL_DTDIR |
| Kojto | 96:487b796308b0 | 336 | |
| Kojto | 96:487b796308b0 | 337 | #define IS_SDIO_TRANSFER_DIR(DIR) (((DIR) == SDIO_TRANSFER_DIR_TO_CARD) || \ |
| Kojto | 96:487b796308b0 | 338 | ((DIR) == SDIO_TRANSFER_DIR_TO_SDIO)) |
| Kojto | 96:487b796308b0 | 339 | /** |
| Kojto | 96:487b796308b0 | 340 | * @} |
| Kojto | 96:487b796308b0 | 341 | */ |
| Kojto | 96:487b796308b0 | 342 | |
| Kojto | 96:487b796308b0 | 343 | /** @defgroup SDMMC_LL_Transfer_Type Transfer Type |
| Kojto | 96:487b796308b0 | 344 | * @{ |
| Kojto | 96:487b796308b0 | 345 | */ |
| Kojto | 96:487b796308b0 | 346 | #define SDIO_TRANSFER_MODE_BLOCK ((uint32_t)0x00000000) |
| Kojto | 96:487b796308b0 | 347 | #define SDIO_TRANSFER_MODE_STREAM SDIO_DCTRL_DTMODE |
| Kojto | 96:487b796308b0 | 348 | |
| Kojto | 96:487b796308b0 | 349 | #define IS_SDIO_TRANSFER_MODE(MODE) (((MODE) == SDIO_TRANSFER_MODE_BLOCK) || \ |
| Kojto | 96:487b796308b0 | 350 | ((MODE) == SDIO_TRANSFER_MODE_STREAM)) |
| Kojto | 96:487b796308b0 | 351 | /** |
| Kojto | 96:487b796308b0 | 352 | * @} |
| Kojto | 96:487b796308b0 | 353 | */ |
| Kojto | 96:487b796308b0 | 354 | |
| Kojto | 96:487b796308b0 | 355 | /** @defgroup SDMMC_LL_DPSM_State DPSM State |
| Kojto | 96:487b796308b0 | 356 | * @{ |
| Kojto | 96:487b796308b0 | 357 | */ |
| Kojto | 96:487b796308b0 | 358 | #define SDIO_DPSM_DISABLE ((uint32_t)0x00000000) |
| Kojto | 96:487b796308b0 | 359 | #define SDIO_DPSM_ENABLE SDIO_DCTRL_DTEN |
| Kojto | 96:487b796308b0 | 360 | |
| Kojto | 96:487b796308b0 | 361 | #define IS_SDIO_DPSM(DPSM) (((DPSM) == SDIO_DPSM_DISABLE) ||\ |
| Kojto | 96:487b796308b0 | 362 | ((DPSM) == SDIO_DPSM_ENABLE)) |
| Kojto | 96:487b796308b0 | 363 | /** |
| Kojto | 96:487b796308b0 | 364 | * @} |
| Kojto | 96:487b796308b0 | 365 | */ |
| Kojto | 96:487b796308b0 | 366 | |
| Kojto | 96:487b796308b0 | 367 | /** @defgroup SDMMC_LL_Read_Wait_Mode Read Wait Mode |
| Kojto | 96:487b796308b0 | 368 | * @{ |
| Kojto | 96:487b796308b0 | 369 | */ |
| Kojto | 96:487b796308b0 | 370 | #define SDIO_READ_WAIT_MODE_DATA2 ((uint32_t)0x00000000) |
| Kojto | 96:487b796308b0 | 371 | #define SDIO_READ_WAIT_MODE_CLK (SDIO_DCTRL_RWMOD) |
| Kojto | 96:487b796308b0 | 372 | |
| Kojto | 96:487b796308b0 | 373 | #define IS_SDIO_READWAIT_MODE(MODE) (((MODE) == SDIO_READ_WAIT_MODE_CLK) || \ |
| Kojto | 96:487b796308b0 | 374 | ((MODE) == SDIO_READ_WAIT_MODE_DATA2)) |
| Kojto | 96:487b796308b0 | 375 | /** |
| Kojto | 96:487b796308b0 | 376 | * @} |
| Kojto | 96:487b796308b0 | 377 | */ |
| Kojto | 96:487b796308b0 | 378 | |
| Kojto | 96:487b796308b0 | 379 | /** @defgroup SDMMC_LL_Interrupt_sources Interrupt Sources |
| Kojto | 96:487b796308b0 | 380 | * @{ |
| Kojto | 96:487b796308b0 | 381 | */ |
| Kojto | 96:487b796308b0 | 382 | #define SDIO_IT_CCRCFAIL SDIO_STA_CCRCFAIL |
| Kojto | 96:487b796308b0 | 383 | #define SDIO_IT_DCRCFAIL SDIO_STA_DCRCFAIL |
| Kojto | 96:487b796308b0 | 384 | #define SDIO_IT_CTIMEOUT SDIO_STA_CTIMEOUT |
| Kojto | 96:487b796308b0 | 385 | #define SDIO_IT_DTIMEOUT SDIO_STA_DTIMEOUT |
| Kojto | 96:487b796308b0 | 386 | #define SDIO_IT_TXUNDERR SDIO_STA_TXUNDERR |
| Kojto | 96:487b796308b0 | 387 | #define SDIO_IT_RXOVERR SDIO_STA_RXOVERR |
| Kojto | 96:487b796308b0 | 388 | #define SDIO_IT_CMDREND SDIO_STA_CMDREND |
| Kojto | 96:487b796308b0 | 389 | #define SDIO_IT_CMDSENT SDIO_STA_CMDSENT |
| Kojto | 96:487b796308b0 | 390 | #define SDIO_IT_DATAEND SDIO_STA_DATAEND |
| Kojto | 96:487b796308b0 | 391 | #define SDIO_IT_STBITERR SDIO_STA_STBITERR |
| Kojto | 96:487b796308b0 | 392 | #define SDIO_IT_DBCKEND SDIO_STA_DBCKEND |
| Kojto | 96:487b796308b0 | 393 | #define SDIO_IT_CMDACT SDIO_STA_CMDACT |
| Kojto | 96:487b796308b0 | 394 | #define SDIO_IT_TXACT SDIO_STA_TXACT |
| Kojto | 96:487b796308b0 | 395 | #define SDIO_IT_RXACT SDIO_STA_RXACT |
| Kojto | 96:487b796308b0 | 396 | #define SDIO_IT_TXFIFOHE SDIO_STA_TXFIFOHE |
| Kojto | 96:487b796308b0 | 397 | #define SDIO_IT_RXFIFOHF SDIO_STA_RXFIFOHF |
| Kojto | 96:487b796308b0 | 398 | #define SDIO_IT_TXFIFOF SDIO_STA_TXFIFOF |
| Kojto | 96:487b796308b0 | 399 | #define SDIO_IT_RXFIFOF SDIO_STA_RXFIFOF |
| Kojto | 96:487b796308b0 | 400 | #define SDIO_IT_TXFIFOE SDIO_STA_TXFIFOE |
| Kojto | 96:487b796308b0 | 401 | #define SDIO_IT_RXFIFOE SDIO_STA_RXFIFOE |
| Kojto | 96:487b796308b0 | 402 | #define SDIO_IT_TXDAVL SDIO_STA_TXDAVL |
| Kojto | 96:487b796308b0 | 403 | #define SDIO_IT_RXDAVL SDIO_STA_RXDAVL |
| Kojto | 96:487b796308b0 | 404 | #define SDIO_IT_SDIOIT SDIO_STA_SDIOIT |
| Kojto | 96:487b796308b0 | 405 | #define SDIO_IT_CEATAEND SDIO_STA_CEATAEND |
| Kojto | 96:487b796308b0 | 406 | |
| Kojto | 96:487b796308b0 | 407 | /** |
| Kojto | 96:487b796308b0 | 408 | * @} |
| Kojto | 96:487b796308b0 | 409 | */ |
| Kojto | 96:487b796308b0 | 410 | |
| Kojto | 96:487b796308b0 | 411 | /** @defgroup SDMMC_LL_Flags Flags |
| Kojto | 96:487b796308b0 | 412 | * @{ |
| Kojto | 96:487b796308b0 | 413 | */ |
| Kojto | 96:487b796308b0 | 414 | #define SDIO_FLAG_CCRCFAIL SDIO_STA_CCRCFAIL |
| Kojto | 96:487b796308b0 | 415 | #define SDIO_FLAG_DCRCFAIL SDIO_STA_DCRCFAIL |
| Kojto | 96:487b796308b0 | 416 | #define SDIO_FLAG_CTIMEOUT SDIO_STA_CTIMEOUT |
| Kojto | 96:487b796308b0 | 417 | #define SDIO_FLAG_DTIMEOUT SDIO_STA_DTIMEOUT |
| Kojto | 96:487b796308b0 | 418 | #define SDIO_FLAG_TXUNDERR SDIO_STA_TXUNDERR |
| Kojto | 96:487b796308b0 | 419 | #define SDIO_FLAG_RXOVERR SDIO_STA_RXOVERR |
| Kojto | 96:487b796308b0 | 420 | #define SDIO_FLAG_CMDREND SDIO_STA_CMDREND |
| Kojto | 96:487b796308b0 | 421 | #define SDIO_FLAG_CMDSENT SDIO_STA_CMDSENT |
| Kojto | 96:487b796308b0 | 422 | #define SDIO_FLAG_DATAEND SDIO_STA_DATAEND |
| Kojto | 96:487b796308b0 | 423 | #define SDIO_FLAG_STBITERR SDIO_STA_STBITERR |
| Kojto | 96:487b796308b0 | 424 | #define SDIO_FLAG_DBCKEND SDIO_STA_DBCKEND |
| Kojto | 96:487b796308b0 | 425 | #define SDIO_FLAG_CMDACT SDIO_STA_CMDACT |
| Kojto | 96:487b796308b0 | 426 | #define SDIO_FLAG_TXACT SDIO_STA_TXACT |
| Kojto | 96:487b796308b0 | 427 | #define SDIO_FLAG_RXACT SDIO_STA_RXACT |
| Kojto | 96:487b796308b0 | 428 | #define SDIO_FLAG_TXFIFOHE SDIO_STA_TXFIFOHE |
| Kojto | 96:487b796308b0 | 429 | #define SDIO_FLAG_RXFIFOHF SDIO_STA_RXFIFOHF |
| Kojto | 96:487b796308b0 | 430 | #define SDIO_FLAG_TXFIFOF SDIO_STA_TXFIFOF |
| Kojto | 96:487b796308b0 | 431 | #define SDIO_FLAG_RXFIFOF SDIO_STA_RXFIFOF |
| Kojto | 96:487b796308b0 | 432 | #define SDIO_FLAG_TXFIFOE SDIO_STA_TXFIFOE |
| Kojto | 96:487b796308b0 | 433 | #define SDIO_FLAG_RXFIFOE SDIO_STA_RXFIFOE |
| Kojto | 96:487b796308b0 | 434 | #define SDIO_FLAG_TXDAVL SDIO_STA_TXDAVL |
| Kojto | 96:487b796308b0 | 435 | #define SDIO_FLAG_RXDAVL SDIO_STA_RXDAVL |
| Kojto | 96:487b796308b0 | 436 | #define SDIO_FLAG_SDIOIT SDIO_STA_SDIOIT |
| Kojto | 96:487b796308b0 | 437 | #define SDIO_FLAG_CEATAEND SDIO_STA_CEATAEND |
| Kojto | 96:487b796308b0 | 438 | |
| Kojto | 96:487b796308b0 | 439 | /** |
| Kojto | 96:487b796308b0 | 440 | * @} |
| Kojto | 96:487b796308b0 | 441 | */ |
| Kojto | 96:487b796308b0 | 442 | |
| Kojto | 96:487b796308b0 | 443 | /** |
| Kojto | 96:487b796308b0 | 444 | * @} |
| Kojto | 96:487b796308b0 | 445 | */ |
| Kojto | 96:487b796308b0 | 446 | |
| Kojto | 96:487b796308b0 | 447 | /* Exported macro ------------------------------------------------------------*/ |
| Kojto | 96:487b796308b0 | 448 | /** @defgroup SDMMC_LL_Exported_macros SDMMC_LL Exported Macros |
| Kojto | 96:487b796308b0 | 449 | * @{ |
| Kojto | 96:487b796308b0 | 450 | */ |
| Kojto | 96:487b796308b0 | 451 | |
| Kojto | 96:487b796308b0 | 452 | /** @defgroup SDMMC_LL_Register Bits And Addresses Definitions |
| Kojto | 96:487b796308b0 | 453 | * @brief SDMMC_LL registers bit address in the alias region |
| Kojto | 96:487b796308b0 | 454 | * @{ |
| Kojto | 96:487b796308b0 | 455 | */ |
| Kojto | 96:487b796308b0 | 456 | |
| Kojto | 96:487b796308b0 | 457 | /* ---------------------- SDIO registers bit mask --------------------------- */ |
| Kojto | 96:487b796308b0 | 458 | /* --- CLKCR Register ---*/ |
| Kojto | 96:487b796308b0 | 459 | /* CLKCR register clear mask */ |
| Kojto | 96:487b796308b0 | 460 | #define CLKCR_CLEAR_MASK ((uint32_t)(SDIO_CLKCR_CLKDIV | SDIO_CLKCR_PWRSAV |\ |
| Kojto | 96:487b796308b0 | 461 | SDIO_CLKCR_BYPASS | SDIO_CLKCR_WIDBUS |\ |
| Kojto | 96:487b796308b0 | 462 | SDIO_CLKCR_NEGEDGE | SDIO_CLKCR_HWFC_EN)) |
| Kojto | 96:487b796308b0 | 463 | |
| Kojto | 96:487b796308b0 | 464 | /* --- DCTRL Register ---*/ |
| Kojto | 96:487b796308b0 | 465 | /* SDIO DCTRL Clear Mask */ |
| Kojto | 96:487b796308b0 | 466 | #define DCTRL_CLEAR_MASK ((uint32_t)(SDIO_DCTRL_DTEN | SDIO_DCTRL_DTDIR |\ |
| Kojto | 96:487b796308b0 | 467 | SDIO_DCTRL_DTMODE | SDIO_DCTRL_DBLOCKSIZE)) |
| Kojto | 96:487b796308b0 | 468 | |
| Kojto | 96:487b796308b0 | 469 | /* --- CMD Register ---*/ |
| Kojto | 96:487b796308b0 | 470 | /* CMD Register clear mask */ |
| Kojto | 96:487b796308b0 | 471 | #define CMD_CLEAR_MASK ((uint32_t)(SDIO_CMD_CMDINDEX | SDIO_CMD_WAITRESP |\ |
| Kojto | 96:487b796308b0 | 472 | SDIO_CMD_WAITINT | SDIO_CMD_WAITPEND |\ |
| Kojto | 96:487b796308b0 | 473 | SDIO_CMD_CPSMEN | SDIO_CMD_SDIOSUSPEND)) |
| Kojto | 96:487b796308b0 | 474 | |
| Kojto | 96:487b796308b0 | 475 | /* SDIO RESP Registers Address */ |
| Kojto | 96:487b796308b0 | 476 | #define SDIO_RESP_ADDR ((uint32_t)(SDIO_BASE + 0x14)) |
| Kojto | 96:487b796308b0 | 477 | |
| Kojto | 96:487b796308b0 | 478 | /* SDIO Intialization Frequency (400KHz max) */ |
| Kojto | 96:487b796308b0 | 479 | #define SDIO_INIT_CLK_DIV ((uint8_t)0xC3) |
| Kojto | 96:487b796308b0 | 480 | |
| Kojto | 96:487b796308b0 | 481 | /* SDIO Data Transfer Frequency */ |
| Kojto | 96:487b796308b0 | 482 | #define SDIO_TRANSFER_CLK_DIV ((uint8_t)0x9) |
| Kojto | 96:487b796308b0 | 483 | |
| Kojto | 96:487b796308b0 | 484 | /** |
| Kojto | 96:487b796308b0 | 485 | * @} |
| Kojto | 96:487b796308b0 | 486 | */ |
| Kojto | 96:487b796308b0 | 487 | |
| Kojto | 96:487b796308b0 | 488 | /** @defgroup SDMMC_LL_Interrupt_Clock Interrupt And Clock Configuration |
| Kojto | 96:487b796308b0 | 489 | * @brief macros to handle interrupts and specific clock configurations |
| Kojto | 96:487b796308b0 | 490 | * @{ |
| Kojto | 96:487b796308b0 | 491 | */ |
| Kojto | 96:487b796308b0 | 492 | |
| Kojto | 96:487b796308b0 | 493 | /** |
| Kojto | 96:487b796308b0 | 494 | * @brief Enable the SDIO device. |
| Kojto | 96:487b796308b0 | 495 | * @param __INSTANCE__: SDIO Instance |
| Kojto | 96:487b796308b0 | 496 | * @retval None |
| Kojto | 96:487b796308b0 | 497 | */ |
| Kojto | 96:487b796308b0 | 498 | #define __SDIO_ENABLE(__INSTANCE__) ((__INSTANCE__)->CLKCR |= SDIO_CLKCR_CLKEN) |
| Kojto | 96:487b796308b0 | 499 | |
| Kojto | 96:487b796308b0 | 500 | /** |
| Kojto | 96:487b796308b0 | 501 | * @brief Disable the SDIO device. |
| Kojto | 96:487b796308b0 | 502 | * @param __INSTANCE__: SDIO Instance |
| Kojto | 96:487b796308b0 | 503 | * @retval None |
| Kojto | 96:487b796308b0 | 504 | */ |
| Kojto | 96:487b796308b0 | 505 | #define __SDIO_DISABLE(__INSTANCE__) ((__INSTANCE__)->CLKCR &= ~SDIO_CLKCR_CLKEN) |
| Kojto | 96:487b796308b0 | 506 | |
| Kojto | 96:487b796308b0 | 507 | /** |
| Kojto | 96:487b796308b0 | 508 | * @brief Enable the SDIO DMA transfer. |
| Kojto | 96:487b796308b0 | 509 | * @param None |
| Kojto | 96:487b796308b0 | 510 | * @retval None |
| Kojto | 96:487b796308b0 | 511 | */ |
| Kojto | 96:487b796308b0 | 512 | #define __SDIO_DMA_ENABLE(__INSTANCE__) ((__INSTANCE__)->DCTRL |= SDIO_DCTRL_DMAEN) |
| Kojto | 96:487b796308b0 | 513 | /** |
| Kojto | 96:487b796308b0 | 514 | * @brief Disable the SDIO DMA transfer. |
| Kojto | 96:487b796308b0 | 515 | * @param None |
| Kojto | 96:487b796308b0 | 516 | * @retval None |
| Kojto | 96:487b796308b0 | 517 | */ |
| Kojto | 96:487b796308b0 | 518 | #define __SDIO_DMA_DISABLE(__INSTANCE__) ((__INSTANCE__)->DCTRL &= ~SDIO_DCTRL_DMAEN) |
| Kojto | 96:487b796308b0 | 519 | |
| Kojto | 96:487b796308b0 | 520 | /** |
| Kojto | 96:487b796308b0 | 521 | * @brief Enable the SDIO device interrupt. |
| Kojto | 96:487b796308b0 | 522 | * @param __INSTANCE__ : Pointer to SDIO register base |
| Kojto | 96:487b796308b0 | 523 | * @param __INTERRUPT__ : specifies the SDIO interrupt sources to be enabled. |
| Kojto | 96:487b796308b0 | 524 | * This parameter can be one or a combination of the following values: |
| Kojto | 96:487b796308b0 | 525 | * @arg SDIO_IT_CCRCFAIL: Command response received (CRC check failed) interrupt |
| Kojto | 96:487b796308b0 | 526 | * @arg SDIO_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt |
| Kojto | 96:487b796308b0 | 527 | * @arg SDIO_IT_CTIMEOUT: Command response timeout interrupt |
| Kojto | 96:487b796308b0 | 528 | * @arg SDIO_IT_DTIMEOUT: Data timeout interrupt |
| Kojto | 96:487b796308b0 | 529 | * @arg SDIO_IT_TXUNDERR: Transmit FIFO underrun error interrupt |
| Kojto | 96:487b796308b0 | 530 | * @arg SDIO_IT_RXOVERR: Received FIFO overrun error interrupt |
| Kojto | 96:487b796308b0 | 531 | * @arg SDIO_IT_CMDREND: Command response received (CRC check passed) interrupt |
| Kojto | 96:487b796308b0 | 532 | * @arg SDIO_IT_CMDSENT: Command sent (no response required) interrupt |
| Kojto | 96:487b796308b0 | 533 | * @arg SDIO_IT_DATAEND: Data end (data counter, SDIDCOUNT, is zero) interrupt |
| Kojto | 96:487b796308b0 | 534 | * @arg SDIO_IT_STBITERR: Start bit not detected on all data signals in wide |
| Kojto | 96:487b796308b0 | 535 | * bus mode interrupt |
| Kojto | 96:487b796308b0 | 536 | * @arg SDIO_IT_DBCKEND: Data block sent/received (CRC check passed) interrupt |
| Kojto | 96:487b796308b0 | 537 | * @arg SDIO_IT_CMDACT: Command transfer in progress interrupt |
| Kojto | 96:487b796308b0 | 538 | * @arg SDIO_IT_TXACT: Data transmit in progress interrupt |
| Kojto | 96:487b796308b0 | 539 | * @arg SDIO_IT_RXACT: Data receive in progress interrupt |
| Kojto | 96:487b796308b0 | 540 | * @arg SDIO_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt |
| Kojto | 96:487b796308b0 | 541 | * @arg SDIO_IT_RXFIFOHF: Receive FIFO Half Full interrupt |
| Kojto | 96:487b796308b0 | 542 | * @arg SDIO_IT_TXFIFOF: Transmit FIFO full interrupt |
| Kojto | 96:487b796308b0 | 543 | * @arg SDIO_IT_RXFIFOF: Receive FIFO full interrupt |
| Kojto | 96:487b796308b0 | 544 | * @arg SDIO_IT_TXFIFOE: Transmit FIFO empty interrupt |
| Kojto | 96:487b796308b0 | 545 | * @arg SDIO_IT_RXFIFOE: Receive FIFO empty interrupt |
| Kojto | 96:487b796308b0 | 546 | * @arg SDIO_IT_TXDAVL: Data available in transmit FIFO interrupt |
| Kojto | 96:487b796308b0 | 547 | * @arg SDIO_IT_RXDAVL: Data available in receive FIFO interrupt |
| Kojto | 96:487b796308b0 | 548 | * @arg SDIO_IT_SDIOIT: SD I/O interrupt received interrupt |
| Kojto | 96:487b796308b0 | 549 | * @arg SDIO_IT_CEATAEND: CE-ATA command completion signal received for CMD61 interrupt |
| Kojto | 96:487b796308b0 | 550 | * @retval None |
| Kojto | 96:487b796308b0 | 551 | */ |
| Kojto | 96:487b796308b0 | 552 | #define __SDIO_ENABLE_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->MASK |= (__INTERRUPT__)) |
| Kojto | 96:487b796308b0 | 553 | |
| Kojto | 96:487b796308b0 | 554 | /** |
| Kojto | 96:487b796308b0 | 555 | * @brief Disable the SDIO device interrupt. |
| Kojto | 96:487b796308b0 | 556 | * @param __INSTANCE__ : Pointer to SDIO register base |
| Kojto | 96:487b796308b0 | 557 | * @param __INTERRUPT__ : specifies the SDIO interrupt sources to be disabled. |
| Kojto | 96:487b796308b0 | 558 | * This parameter can be one or a combination of the following values: |
| Kojto | 96:487b796308b0 | 559 | * @arg SDIO_IT_CCRCFAIL: Command response received (CRC check failed) interrupt |
| Kojto | 96:487b796308b0 | 560 | * @arg SDIO_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt |
| Kojto | 96:487b796308b0 | 561 | * @arg SDIO_IT_CTIMEOUT: Command response timeout interrupt |
| Kojto | 96:487b796308b0 | 562 | * @arg SDIO_IT_DTIMEOUT: Data timeout interrupt |
| Kojto | 96:487b796308b0 | 563 | * @arg SDIO_IT_TXUNDERR: Transmit FIFO underrun error interrupt |
| Kojto | 96:487b796308b0 | 564 | * @arg SDIO_IT_RXOVERR: Received FIFO overrun error interrupt |
| Kojto | 96:487b796308b0 | 565 | * @arg SDIO_IT_CMDREND: Command response received (CRC check passed) interrupt |
| Kojto | 96:487b796308b0 | 566 | * @arg SDIO_IT_CMDSENT: Command sent (no response required) interrupt |
| Kojto | 96:487b796308b0 | 567 | * @arg SDIO_IT_DATAEND: Data end (data counter, SDIDCOUNT, is zero) interrupt |
| Kojto | 96:487b796308b0 | 568 | * @arg SDIO_IT_STBITERR: Start bit not detected on all data signals in wide |
| Kojto | 96:487b796308b0 | 569 | * bus mode interrupt |
| Kojto | 96:487b796308b0 | 570 | * @arg SDIO_IT_DBCKEND: Data block sent/received (CRC check passed) interrupt |
| Kojto | 96:487b796308b0 | 571 | * @arg SDIO_IT_CMDACT: Command transfer in progress interrupt |
| Kojto | 96:487b796308b0 | 572 | * @arg SDIO_IT_TXACT: Data transmit in progress interrupt |
| Kojto | 96:487b796308b0 | 573 | * @arg SDIO_IT_RXACT: Data receive in progress interrupt |
| Kojto | 96:487b796308b0 | 574 | * @arg SDIO_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt |
| Kojto | 96:487b796308b0 | 575 | * @arg SDIO_IT_RXFIFOHF: Receive FIFO Half Full interrupt |
| Kojto | 96:487b796308b0 | 576 | * @arg SDIO_IT_TXFIFOF: Transmit FIFO full interrupt |
| Kojto | 96:487b796308b0 | 577 | * @arg SDIO_IT_RXFIFOF: Receive FIFO full interrupt |
| Kojto | 96:487b796308b0 | 578 | * @arg SDIO_IT_TXFIFOE: Transmit FIFO empty interrupt |
| Kojto | 96:487b796308b0 | 579 | * @arg SDIO_IT_RXFIFOE: Receive FIFO empty interrupt |
| Kojto | 96:487b796308b0 | 580 | * @arg SDIO_IT_TXDAVL: Data available in transmit FIFO interrupt |
| Kojto | 96:487b796308b0 | 581 | * @arg SDIO_IT_RXDAVL: Data available in receive FIFO interrupt |
| Kojto | 96:487b796308b0 | 582 | * @arg SDIO_IT_SDIOIT: SD I/O interrupt received interrupt |
| Kojto | 96:487b796308b0 | 583 | * @arg SDIO_IT_CEATAEND: CE-ATA command completion signal received for CMD61 interrupt |
| Kojto | 96:487b796308b0 | 584 | * @retval None |
| Kojto | 96:487b796308b0 | 585 | */ |
| Kojto | 96:487b796308b0 | 586 | #define __SDIO_DISABLE_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->MASK &= ~(__INTERRUPT__)) |
| Kojto | 96:487b796308b0 | 587 | |
| Kojto | 96:487b796308b0 | 588 | /** |
| Kojto | 96:487b796308b0 | 589 | * @brief Checks whether the specified SDIO flag is set or not. |
| Kojto | 96:487b796308b0 | 590 | * @param __INSTANCE__ : Pointer to SDIO register base |
| Kojto | 96:487b796308b0 | 591 | * @param __FLAG__: specifies the flag to check. |
| Kojto | 96:487b796308b0 | 592 | * This parameter can be one of the following values: |
| Kojto | 96:487b796308b0 | 593 | * @arg SDIO_FLAG_CCRCFAIL: Command response received (CRC check failed) |
| Kojto | 96:487b796308b0 | 594 | * @arg SDIO_FLAG_DCRCFAIL: Data block sent/received (CRC check failed) |
| Kojto | 96:487b796308b0 | 595 | * @arg SDIO_FLAG_CTIMEOUT: Command response timeout |
| Kojto | 96:487b796308b0 | 596 | * @arg SDIO_FLAG_DTIMEOUT: Data timeout |
| Kojto | 96:487b796308b0 | 597 | * @arg SDIO_FLAG_TXUNDERR: Transmit FIFO underrun error |
| Kojto | 96:487b796308b0 | 598 | * @arg SDIO_FLAG_RXOVERR: Received FIFO overrun error |
| Kojto | 96:487b796308b0 | 599 | * @arg SDIO_FLAG_CMDREND: Command response received (CRC check passed) |
| Kojto | 96:487b796308b0 | 600 | * @arg SDIO_FLAG_CMDSENT: Command sent (no response required) |
| Kojto | 96:487b796308b0 | 601 | * @arg SDIO_FLAG_DATAEND: Data end (data counter, SDIDCOUNT, is zero) |
| Kojto | 96:487b796308b0 | 602 | * @arg SDIO_FLAG_STBITERR: Start bit not detected on all data signals in wide bus mode. |
| Kojto | 96:487b796308b0 | 603 | * @arg SDIO_FLAG_DBCKEND: Data block sent/received (CRC check passed) |
| Kojto | 96:487b796308b0 | 604 | * @arg SDIO_FLAG_CMDACT: Command transfer in progress |
| Kojto | 96:487b796308b0 | 605 | * @arg SDIO_FLAG_TXACT: Data transmit in progress |
| Kojto | 96:487b796308b0 | 606 | * @arg SDIO_FLAG_RXACT: Data receive in progress |
| Kojto | 96:487b796308b0 | 607 | * @arg SDIO_FLAG_TXFIFOHE: Transmit FIFO Half Empty |
| Kojto | 96:487b796308b0 | 608 | * @arg SDIO_FLAG_RXFIFOHF: Receive FIFO Half Full |
| Kojto | 96:487b796308b0 | 609 | * @arg SDIO_FLAG_TXFIFOF: Transmit FIFO full |
| Kojto | 96:487b796308b0 | 610 | * @arg SDIO_FLAG_RXFIFOF: Receive FIFO full |
| Kojto | 96:487b796308b0 | 611 | * @arg SDIO_FLAG_TXFIFOE: Transmit FIFO empty |
| Kojto | 96:487b796308b0 | 612 | * @arg SDIO_FLAG_RXFIFOE: Receive FIFO empty |
| Kojto | 96:487b796308b0 | 613 | * @arg SDIO_FLAG_TXDAVL: Data available in transmit FIFO |
| Kojto | 96:487b796308b0 | 614 | * @arg SDIO_FLAG_RXDAVL: Data available in receive FIFO |
| Kojto | 96:487b796308b0 | 615 | * @arg SDIO_FLAG_SDIOIT: SD I/O interrupt received |
| Kojto | 96:487b796308b0 | 616 | * @arg SDIO_FLAG_CEATAEND: CE-ATA command completion signal received for CMD61 |
| Kojto | 96:487b796308b0 | 617 | * @retval The new state of SDIO_FLAG (SET or RESET). |
| Kojto | 96:487b796308b0 | 618 | */ |
| Kojto | 96:487b796308b0 | 619 | #define __SDIO_GET_FLAG(__INSTANCE__, __FLAG__) (((__INSTANCE__)->STA &(__FLAG__)) != RESET) |
| Kojto | 96:487b796308b0 | 620 | |
| Kojto | 96:487b796308b0 | 621 | |
| Kojto | 96:487b796308b0 | 622 | /** |
| Kojto | 96:487b796308b0 | 623 | * @brief Clears the SDIO pending flags. |
| Kojto | 96:487b796308b0 | 624 | * @param __INSTANCE__ : Pointer to SDIO register base |
| Kojto | 96:487b796308b0 | 625 | * @param __FLAG__: specifies the flag to clear. |
| Kojto | 96:487b796308b0 | 626 | * This parameter can be one or a combination of the following values: |
| Kojto | 96:487b796308b0 | 627 | * @arg SDIO_FLAG_CCRCFAIL: Command response received (CRC check failed) |
| Kojto | 96:487b796308b0 | 628 | * @arg SDIO_FLAG_DCRCFAIL: Data block sent/received (CRC check failed) |
| Kojto | 96:487b796308b0 | 629 | * @arg SDIO_FLAG_CTIMEOUT: Command response timeout |
| Kojto | 96:487b796308b0 | 630 | * @arg SDIO_FLAG_DTIMEOUT: Data timeout |
| Kojto | 96:487b796308b0 | 631 | * @arg SDIO_FLAG_TXUNDERR: Transmit FIFO underrun error |
| Kojto | 96:487b796308b0 | 632 | * @arg SDIO_FLAG_RXOVERR: Received FIFO overrun error |
| Kojto | 96:487b796308b0 | 633 | * @arg SDIO_FLAG_CMDREND: Command response received (CRC check passed) |
| Kojto | 96:487b796308b0 | 634 | * @arg SDIO_FLAG_CMDSENT: Command sent (no response required) |
| Kojto | 96:487b796308b0 | 635 | * @arg SDIO_FLAG_DATAEND: Data end (data counter, SDIDCOUNT, is zero) |
| Kojto | 96:487b796308b0 | 636 | * @arg SDIO_FLAG_STBITERR: Start bit not detected on all data signals in wide bus mode |
| Kojto | 96:487b796308b0 | 637 | * @arg SDIO_FLAG_DBCKEND: Data block sent/received (CRC check passed) |
| Kojto | 96:487b796308b0 | 638 | * @arg SDIO_FLAG_SDIOIT: SD I/O interrupt received |
| Kojto | 96:487b796308b0 | 639 | * @arg SDIO_FLAG_CEATAEND: CE-ATA command completion signal received for CMD61 |
| Kojto | 96:487b796308b0 | 640 | * @retval None |
| Kojto | 96:487b796308b0 | 641 | */ |
| Kojto | 96:487b796308b0 | 642 | #define __SDIO_CLEAR_FLAG(__INSTANCE__, __FLAG__) ((__INSTANCE__)->ICR = (__FLAG__)) |
| Kojto | 96:487b796308b0 | 643 | |
| Kojto | 96:487b796308b0 | 644 | /** |
| Kojto | 96:487b796308b0 | 645 | * @brief Checks whether the specified SDIO interrupt has occurred or not. |
| Kojto | 96:487b796308b0 | 646 | * @param __INSTANCE__ : Pointer to SDIO register base |
| Kojto | 96:487b796308b0 | 647 | * @param __INTERRUPT__: specifies the SDIO interrupt source to check. |
| Kojto | 96:487b796308b0 | 648 | * This parameter can be one of the following values: |
| Kojto | 96:487b796308b0 | 649 | * @arg SDIO_IT_CCRCFAIL: Command response received (CRC check failed) interrupt |
| Kojto | 96:487b796308b0 | 650 | * @arg SDIO_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt |
| Kojto | 96:487b796308b0 | 651 | * @arg SDIO_IT_CTIMEOUT: Command response timeout interrupt |
| Kojto | 96:487b796308b0 | 652 | * @arg SDIO_IT_DTIMEOUT: Data timeout interrupt |
| Kojto | 96:487b796308b0 | 653 | * @arg SDIO_IT_TXUNDERR: Transmit FIFO underrun error interrupt |
| Kojto | 96:487b796308b0 | 654 | * @arg SDIO_IT_RXOVERR: Received FIFO overrun error interrupt |
| Kojto | 96:487b796308b0 | 655 | * @arg SDIO_IT_CMDREND: Command response received (CRC check passed) interrupt |
| Kojto | 96:487b796308b0 | 656 | * @arg SDIO_IT_CMDSENT: Command sent (no response required) interrupt |
| Kojto | 96:487b796308b0 | 657 | * @arg SDIO_IT_DATAEND: Data end (data counter, SDIDCOUNT, is zero) interrupt |
| Kojto | 96:487b796308b0 | 658 | * @arg SDIO_IT_STBITERR: Start bit not detected on all data signals in wide |
| Kojto | 96:487b796308b0 | 659 | * bus mode interrupt |
| Kojto | 96:487b796308b0 | 660 | * @arg SDIO_IT_DBCKEND: Data block sent/received (CRC check passed) interrupt |
| Kojto | 96:487b796308b0 | 661 | * @arg SDIO_IT_CMDACT: Command transfer in progress interrupt |
| Kojto | 96:487b796308b0 | 662 | * @arg SDIO_IT_TXACT: Data transmit in progress interrupt |
| Kojto | 96:487b796308b0 | 663 | * @arg SDIO_IT_RXACT: Data receive in progress interrupt |
| Kojto | 96:487b796308b0 | 664 | * @arg SDIO_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt |
| Kojto | 96:487b796308b0 | 665 | * @arg SDIO_IT_RXFIFOHF: Receive FIFO Half Full interrupt |
| Kojto | 96:487b796308b0 | 666 | * @arg SDIO_IT_TXFIFOF: Transmit FIFO full interrupt |
| Kojto | 96:487b796308b0 | 667 | * @arg SDIO_IT_RXFIFOF: Receive FIFO full interrupt |
| Kojto | 96:487b796308b0 | 668 | * @arg SDIO_IT_TXFIFOE: Transmit FIFO empty interrupt |
| Kojto | 96:487b796308b0 | 669 | * @arg SDIO_IT_RXFIFOE: Receive FIFO empty interrupt |
| Kojto | 96:487b796308b0 | 670 | * @arg SDIO_IT_TXDAVL: Data available in transmit FIFO interrupt |
| Kojto | 96:487b796308b0 | 671 | * @arg SDIO_IT_RXDAVL: Data available in receive FIFO interrupt |
| Kojto | 96:487b796308b0 | 672 | * @arg SDIO_IT_SDIOIT: SD I/O interrupt received interrupt |
| Kojto | 96:487b796308b0 | 673 | * @arg SDIO_IT_CEATAEND: CE-ATA command completion signal received for CMD61 interrupt |
| Kojto | 96:487b796308b0 | 674 | * @retval The new state of SDIO_IT (SET or RESET). |
| Kojto | 96:487b796308b0 | 675 | */ |
| Kojto | 96:487b796308b0 | 676 | #define __SDIO_GET_IT (__INSTANCE__, __INTERRUPT__) (((__INSTANCE__)->STA &(__INTERRUPT__)) == (__INTERRUPT__)) |
| Kojto | 96:487b796308b0 | 677 | |
| Kojto | 96:487b796308b0 | 678 | /** |
| Kojto | 96:487b796308b0 | 679 | * @brief Clears the SDIO's interrupt pending bits. |
| Kojto | 96:487b796308b0 | 680 | * @param __INSTANCE__ : Pointer to SDIO register base |
| Kojto | 96:487b796308b0 | 681 | * @param __INTERRUPT__: specifies the interrupt pending bit to clear. |
| Kojto | 96:487b796308b0 | 682 | * This parameter can be one or a combination of the following values: |
| Kojto | 96:487b796308b0 | 683 | * @arg SDIO_IT_CCRCFAIL: Command response received (CRC check failed) interrupt |
| Kojto | 96:487b796308b0 | 684 | * @arg SDIO_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt |
| Kojto | 96:487b796308b0 | 685 | * @arg SDIO_IT_CTIMEOUT: Command response timeout interrupt |
| Kojto | 96:487b796308b0 | 686 | * @arg SDIO_IT_DTIMEOUT: Data timeout interrupt |
| Kojto | 96:487b796308b0 | 687 | * @arg SDIO_IT_TXUNDERR: Transmit FIFO underrun error interrupt |
| Kojto | 96:487b796308b0 | 688 | * @arg SDIO_IT_RXOVERR: Received FIFO overrun error interrupt |
| Kojto | 96:487b796308b0 | 689 | * @arg SDIO_IT_CMDREND: Command response received (CRC check passed) interrupt |
| Kojto | 96:487b796308b0 | 690 | * @arg SDIO_IT_CMDSENT: Command sent (no response required) interrupt |
| Kojto | 96:487b796308b0 | 691 | * @arg SDIO_IT_DATAEND: Data end (data counter, SDIO_DCOUNT, is zero) interrupt |
| Kojto | 96:487b796308b0 | 692 | * @arg SDIO_IT_STBITERR: Start bit not detected on all data signals in wide |
| Kojto | 96:487b796308b0 | 693 | * bus mode interrupt |
| Kojto | 96:487b796308b0 | 694 | * @arg SDIO_IT_SDIOIT: SD I/O interrupt received interrupt |
| Kojto | 96:487b796308b0 | 695 | * @arg SDIO_IT_CEATAEND: CE-ATA command completion signal received for CMD61 |
| Kojto | 96:487b796308b0 | 696 | * @retval None |
| Kojto | 96:487b796308b0 | 697 | */ |
| Kojto | 96:487b796308b0 | 698 | #define __SDIO_CLEAR_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->ICR = (__INTERRUPT__)) |
| Kojto | 96:487b796308b0 | 699 | |
| Kojto | 96:487b796308b0 | 700 | /** |
| Kojto | 96:487b796308b0 | 701 | * @brief Enable Start the SD I/O Read Wait operation. |
| Kojto | 96:487b796308b0 | 702 | * @param __INSTANCE__ : Pointer to SDIO register base |
| Kojto | 96:487b796308b0 | 703 | * @retval None |
| Kojto | 96:487b796308b0 | 704 | */ |
| Kojto | 96:487b796308b0 | 705 | #define __SDIO_START_READWAIT_ENABLE(__INSTANCE__) ((__INSTANCE__)->DCTRL |= SDIO_DCTRL_RWSTART) |
| Kojto | 96:487b796308b0 | 706 | |
| Kojto | 96:487b796308b0 | 707 | /** |
| Kojto | 96:487b796308b0 | 708 | * @brief Disable Start the SD I/O Read Wait operations. |
| Kojto | 96:487b796308b0 | 709 | * @param __INSTANCE__ : Pointer to SDIO register base |
| Kojto | 96:487b796308b0 | 710 | * @retval None |
| Kojto | 96:487b796308b0 | 711 | */ |
| Kojto | 96:487b796308b0 | 712 | #define __SDIO_START_READWAIT_DISABLE(__INSTANCE__) ((__INSTANCE__)->DCTRL &= ~SDIO_DCTRL_RWSTART) |
| Kojto | 96:487b796308b0 | 713 | |
| Kojto | 96:487b796308b0 | 714 | /** |
| Kojto | 96:487b796308b0 | 715 | * @brief Enable Start the SD I/O Read Wait operation. |
| Kojto | 96:487b796308b0 | 716 | * @param __INSTANCE__ : Pointer to SDIO register base |
| Kojto | 96:487b796308b0 | 717 | * @retval None |
| Kojto | 96:487b796308b0 | 718 | */ |
| Kojto | 96:487b796308b0 | 719 | #define __SDIO_STOP_READWAIT_ENABLE(__INSTANCE__) ((__INSTANCE__)->DCTRL |= SDIO_DCTRL_RWSTOP) |
| Kojto | 96:487b796308b0 | 720 | |
| Kojto | 96:487b796308b0 | 721 | /** |
| Kojto | 96:487b796308b0 | 722 | * @brief Disable Stop the SD I/O Read Wait operations. |
| Kojto | 96:487b796308b0 | 723 | * @param __INSTANCE__ : Pointer to SDIO register base |
| Kojto | 96:487b796308b0 | 724 | * @retval None |
| Kojto | 96:487b796308b0 | 725 | */ |
| Kojto | 96:487b796308b0 | 726 | #define __SDIO_STOP_READWAIT_DISABLE(__INSTANCE__) ((__INSTANCE__)->DCTRL &= ~SDIO_DCTRL_RWSTOP) |
| Kojto | 96:487b796308b0 | 727 | |
| Kojto | 96:487b796308b0 | 728 | /** |
| Kojto | 96:487b796308b0 | 729 | * @brief Enable the SD I/O Mode Operation. |
| Kojto | 96:487b796308b0 | 730 | * @param __INSTANCE__ : Pointer to SDIO register base |
| Kojto | 96:487b796308b0 | 731 | * @retval None |
| Kojto | 96:487b796308b0 | 732 | */ |
| Kojto | 96:487b796308b0 | 733 | #define __SDIO_OPERATION_ENABLE(__INSTANCE__) ((__INSTANCE__)->DCTRL |= SDIO_DCTRL_SDIOEN) |
| Kojto | 96:487b796308b0 | 734 | |
| Kojto | 96:487b796308b0 | 735 | /** |
| Kojto | 96:487b796308b0 | 736 | * @brief Disable the SD I/O Mode Operation. |
| Kojto | 96:487b796308b0 | 737 | * @param __INSTANCE__ : Pointer to SDIO register base |
| Kojto | 96:487b796308b0 | 738 | * @retval None |
| Kojto | 96:487b796308b0 | 739 | */ |
| Kojto | 96:487b796308b0 | 740 | #define __SDIO_OPERATION_DISABLE(__INSTANCE__) ((__INSTANCE__)->DCTRL &= ~SDIO_DCTRL_SDIOEN) |
| Kojto | 96:487b796308b0 | 741 | |
| Kojto | 96:487b796308b0 | 742 | /** |
| Kojto | 96:487b796308b0 | 743 | * @brief Enable the SD I/O Suspend command sending. |
| Kojto | 96:487b796308b0 | 744 | * @param __INSTANCE__ : Pointer to SDIO register base |
| Kojto | 96:487b796308b0 | 745 | * @retval None |
| Kojto | 96:487b796308b0 | 746 | */ |
| Kojto | 96:487b796308b0 | 747 | #define __SDIO_SUSPEND_CMD_ENABLE(__INSTANCE__) ((__INSTANCE__)->CMD |= SDIO_CMD_SDIOSUSPEND) |
| Kojto | 96:487b796308b0 | 748 | |
| Kojto | 96:487b796308b0 | 749 | /** |
| Kojto | 96:487b796308b0 | 750 | * @brief Disable the SD I/O Suspend command sending. |
| Kojto | 96:487b796308b0 | 751 | * @param __INSTANCE__ : Pointer to SDIO register base |
| Kojto | 96:487b796308b0 | 752 | * @retval None |
| Kojto | 96:487b796308b0 | 753 | */ |
| Kojto | 96:487b796308b0 | 754 | #define __SDIO_SUSPEND_CMD_DISABLE(__INSTANCE__) ((__INSTANCE__)->CMD &= ~SDIO_CMD_SDIOSUSPEND) |
| Kojto | 96:487b796308b0 | 755 | |
| Kojto | 96:487b796308b0 | 756 | /** |
| Kojto | 96:487b796308b0 | 757 | * @brief Enable the command completion signal. |
| Kojto | 96:487b796308b0 | 758 | * @param __INSTANCE__ : Pointer to SDIO register base |
| Kojto | 96:487b796308b0 | 759 | * @retval None |
| Kojto | 96:487b796308b0 | 760 | */ |
| Kojto | 96:487b796308b0 | 761 | #define __SDIO_CEATA_CMD_COMPLETION_ENABLE(__INSTANCE__) ((__INSTANCE__)->CMD |= SDIO_CMD_ENCMDCOMPL) |
| Kojto | 96:487b796308b0 | 762 | |
| Kojto | 96:487b796308b0 | 763 | /** |
| Kojto | 96:487b796308b0 | 764 | * @brief Disable the command completion signal. |
| Kojto | 96:487b796308b0 | 765 | * @param __INSTANCE__ : Pointer to SDIO register base |
| Kojto | 96:487b796308b0 | 766 | * @retval None |
| Kojto | 96:487b796308b0 | 767 | */ |
| Kojto | 96:487b796308b0 | 768 | #define __SDIO_CEATA_CMD_COMPLETION_DISABLE(__INSTANCE__) ((__INSTANCE__)->CMD &= ~SDIO_CMD_ENCMDCOMPL) |
| Kojto | 96:487b796308b0 | 769 | |
| Kojto | 96:487b796308b0 | 770 | /** |
| Kojto | 96:487b796308b0 | 771 | * @brief Enable the CE-ATA interrupt. |
| Kojto | 96:487b796308b0 | 772 | * @param __INSTANCE__ : Pointer to SDIO register base |
| Kojto | 96:487b796308b0 | 773 | * @retval None |
| Kojto | 96:487b796308b0 | 774 | */ |
| Kojto | 96:487b796308b0 | 775 | #define __SDIO_CEATA_ENABLE_IT(__INSTANCE__) ((__INSTANCE__)->CMD &= ~SDIO_CMD_NIEN) |
| Kojto | 96:487b796308b0 | 776 | |
| Kojto | 96:487b796308b0 | 777 | /** |
| Kojto | 96:487b796308b0 | 778 | * @brief Disable the CE-ATA interrupt. |
| Kojto | 96:487b796308b0 | 779 | * @param __INSTANCE__ : Pointer to SDIO register base |
| Kojto | 96:487b796308b0 | 780 | * @retval None |
| Kojto | 96:487b796308b0 | 781 | */ |
| Kojto | 96:487b796308b0 | 782 | #define __SDIO_CEATA_DISABLE_IT(__INSTANCE__) ((__INSTANCE__)->CMD |= SDIO_CMD_NIEN) |
| Kojto | 96:487b796308b0 | 783 | |
| Kojto | 96:487b796308b0 | 784 | /** |
| Kojto | 96:487b796308b0 | 785 | * @brief Enable send CE-ATA command (CMD61). |
| Kojto | 96:487b796308b0 | 786 | * @param __INSTANCE__ : Pointer to SDIO register base |
| Kojto | 96:487b796308b0 | 787 | * @retval None |
| Kojto | 96:487b796308b0 | 788 | */ |
| Kojto | 96:487b796308b0 | 789 | #define __SDIO_CEATA_SENDCMD_ENABLE(__INSTANCE__) ((__INSTANCE__)->CMD |= SDIO_CMD_CEATACMD) |
| Kojto | 96:487b796308b0 | 790 | |
| Kojto | 96:487b796308b0 | 791 | /** |
| Kojto | 96:487b796308b0 | 792 | * @brief Disable send CE-ATA command (CMD61). |
| Kojto | 96:487b796308b0 | 793 | * @param __INSTANCE__ : Pointer to SDIO register base |
| Kojto | 96:487b796308b0 | 794 | * @retval None |
| Kojto | 96:487b796308b0 | 795 | */ |
| Kojto | 96:487b796308b0 | 796 | #define __SDIO_CEATA_SENDCMD_DISABLE(__INSTANCE__) ((__INSTANCE__)->CMD &= ~SDIO_CMD_CEATACMD) |
| Kojto | 96:487b796308b0 | 797 | |
| Kojto | 96:487b796308b0 | 798 | /** |
| Kojto | 96:487b796308b0 | 799 | * @} |
| Kojto | 96:487b796308b0 | 800 | */ |
| Kojto | 96:487b796308b0 | 801 | |
| Kojto | 96:487b796308b0 | 802 | /** |
| Kojto | 96:487b796308b0 | 803 | * @} |
| Kojto | 96:487b796308b0 | 804 | */ |
| Kojto | 96:487b796308b0 | 805 | |
| Kojto | 96:487b796308b0 | 806 | /* Exported functions --------------------------------------------------------*/ |
| Kojto | 96:487b796308b0 | 807 | /** @addtogroup SDMMC_LL_Exported_Functions |
| Kojto | 96:487b796308b0 | 808 | * @{ |
| Kojto | 96:487b796308b0 | 809 | */ |
| Kojto | 96:487b796308b0 | 810 | |
| Kojto | 96:487b796308b0 | 811 | /* Initialization/de-initialization functions **********************************/ |
| Kojto | 96:487b796308b0 | 812 | /** @addtogroup HAL_SDMMC_LL_Group1 |
| Kojto | 96:487b796308b0 | 813 | * @{ |
| Kojto | 96:487b796308b0 | 814 | */ |
| Kojto | 96:487b796308b0 | 815 | HAL_StatusTypeDef SDIO_Init(SDIO_TypeDef *SDIOx, SDIO_InitTypeDef Init); |
| Kojto | 96:487b796308b0 | 816 | /** |
| Kojto | 96:487b796308b0 | 817 | * @} |
| Kojto | 96:487b796308b0 | 818 | */ |
| Kojto | 96:487b796308b0 | 819 | |
| Kojto | 96:487b796308b0 | 820 | /* I/O operation functions *****************************************************/ |
| Kojto | 96:487b796308b0 | 821 | /** @addtogroup HAL_SDMMC_LL_Group2 |
| Kojto | 96:487b796308b0 | 822 | * @{ |
| Kojto | 96:487b796308b0 | 823 | */ |
| Kojto | 96:487b796308b0 | 824 | /* Blocking mode: Polling */ |
| Kojto | 96:487b796308b0 | 825 | uint32_t SDIO_ReadFIFO(SDIO_TypeDef *SDIOx); |
| Kojto | 96:487b796308b0 | 826 | HAL_StatusTypeDef SDIO_WriteFIFO(SDIO_TypeDef *SDIOx, uint32_t *pWriteData); |
| Kojto | 96:487b796308b0 | 827 | /** |
| Kojto | 96:487b796308b0 | 828 | * @} |
| Kojto | 96:487b796308b0 | 829 | */ |
| Kojto | 96:487b796308b0 | 830 | |
| Kojto | 96:487b796308b0 | 831 | /* Peripheral Control functions ************************************************/ |
| Kojto | 96:487b796308b0 | 832 | /** @addtogroup HAL_SDMMC_LL_Group3 |
| Kojto | 96:487b796308b0 | 833 | * @{ |
| Kojto | 96:487b796308b0 | 834 | */ |
| Kojto | 96:487b796308b0 | 835 | HAL_StatusTypeDef SDIO_PowerState_ON(SDIO_TypeDef *SDIOx); |
| Kojto | 96:487b796308b0 | 836 | HAL_StatusTypeDef SDIO_PowerState_OFF(SDIO_TypeDef *SDIOx); |
| Kojto | 96:487b796308b0 | 837 | uint32_t SDIO_GetPowerState(SDIO_TypeDef *SDIOx); |
| Kojto | 96:487b796308b0 | 838 | |
| Kojto | 96:487b796308b0 | 839 | /* Command path state machine (CPSM) management functions */ |
| Kojto | 96:487b796308b0 | 840 | HAL_StatusTypeDef SDIO_SendCommand(SDIO_TypeDef *SDIOx, SDIO_CmdInitTypeDef *Command); |
| Kojto | 96:487b796308b0 | 841 | uint8_t SDIO_GetCommandResponse(SDIO_TypeDef *SDIOx); |
| Kojto | 96:487b796308b0 | 842 | uint32_t SDIO_GetResponse(SDIO_TypeDef *SDIOx, uint32_t Response); |
| Kojto | 96:487b796308b0 | 843 | |
| Kojto | 96:487b796308b0 | 844 | /* Data path state machine (DPSM) management functions */ |
| Kojto | 96:487b796308b0 | 845 | HAL_StatusTypeDef SDIO_DataConfig(SDIO_TypeDef *SDIOx, SDIO_DataInitTypeDef* Data); |
| Kojto | 96:487b796308b0 | 846 | uint32_t SDIO_GetDataCounter(SDIO_TypeDef *SDIOx); |
| Kojto | 96:487b796308b0 | 847 | uint32_t SDIO_GetFIFOCount(SDIO_TypeDef *SDIOx); |
| Kojto | 96:487b796308b0 | 848 | |
| Kojto | 96:487b796308b0 | 849 | /* SDIO Cards mode management functions */ |
| Kojto | 96:487b796308b0 | 850 | HAL_StatusTypeDef SDIO_SetSDIOReadWaitMode(SDIO_TypeDef *SDIOx, uint32_t SDIO_ReadWaitMode); |
| Kojto | 96:487b796308b0 | 851 | |
| Kojto | 96:487b796308b0 | 852 | /** |
| Kojto | 96:487b796308b0 | 853 | * @} |
| Kojto | 96:487b796308b0 | 854 | */ |
| Kojto | 96:487b796308b0 | 855 | |
| Kojto | 96:487b796308b0 | 856 | /** |
| Kojto | 96:487b796308b0 | 857 | * @} |
| Kojto | 96:487b796308b0 | 858 | */ |
| Kojto | 96:487b796308b0 | 859 | |
| Kojto | 96:487b796308b0 | 860 | /** |
| Kojto | 96:487b796308b0 | 861 | * @} |
| Kojto | 96:487b796308b0 | 862 | */ |
| Kojto | 96:487b796308b0 | 863 | |
| Kojto | 96:487b796308b0 | 864 | /** |
| Kojto | 96:487b796308b0 | 865 | * @} |
| Kojto | 96:487b796308b0 | 866 | */ |
| Kojto | 96:487b796308b0 | 867 | |
| Kojto | 96:487b796308b0 | 868 | #ifdef __cplusplus |
| Kojto | 96:487b796308b0 | 869 | } |
| Kojto | 96:487b796308b0 | 870 | #endif |
| Kojto | 96:487b796308b0 | 871 | |
| Kojto | 96:487b796308b0 | 872 | #endif /* STM32F103xE || STM32F103xG */ |
| Kojto | 96:487b796308b0 | 873 | |
| Kojto | 96:487b796308b0 | 874 | #endif /* __stm32f1xx_LL_SD_H */ |
| Kojto | 96:487b796308b0 | 875 | |
| Kojto | 96:487b796308b0 | 876 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |