Diff: TARGET_ARCH_MAX/stm32f4xx_hal_rcc.h

Revision:

93:e188a91d3eaa

Parent:

92:4fc01daae5a5

--- a/TARGET_ARCH_MAX/stm32f4xx_hal_rcc.h	Thu Nov 27 13:33:22 2014 +0000
+++ b/TARGET_ARCH_MAX/stm32f4xx_hal_rcc.h	Tue Feb 03 15:31:20 2015 +0000
@@ -530,6 +530,8 @@
 #define __GPIOC_CLK_ENABLE()         (RCC->AHB1ENR |= (RCC_AHB1ENR_GPIOCEN))
 #define __GPIOD_CLK_ENABLE()         (RCC->AHB1ENR |= (RCC_AHB1ENR_GPIODEN))
 #define __GPIOE_CLK_ENABLE()         (RCC->AHB1ENR |= (RCC_AHB1ENR_GPIOEEN))
+#define __GPIOF_CLK_ENABLE()         (RCC->AHB1ENR |= (RCC_AHB1ENR_GPIOFEN))
+#define __GPIOG_CLK_ENABLE()         (RCC->AHB1ENR |= (RCC_AHB1ENR_GPIOGEN))
 #define __GPIOH_CLK_ENABLE()         (RCC->AHB1ENR |= (RCC_AHB1ENR_GPIOHEN))
 #define __CRC_CLK_ENABLE()           (RCC->AHB1ENR |= (RCC_AHB1ENR_CRCEN))
 #define __BKPSRAM_CLK_ENABLE()       (RCC->AHB1ENR |= (RCC_AHB1ENR_BKPSRAMEN))
@@ -542,6 +544,8 @@
 #define __GPIOC_CLK_DISABLE()        (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOCEN))
 #define __GPIOD_CLK_DISABLE()        (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIODEN))
 #define __GPIOE_CLK_DISABLE()        (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOEEN))
+#define __GPIOF_CLK_DISABLE()        (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOFEN))
+#define __GPIOG_CLK_DISABLE()        (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOGEN))
 #define __GPIOH_CLK_DISABLE()        (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOHEN))
 #define __CRC_CLK_DISABLE()          (RCC->AHB1ENR &= ~(RCC_AHB1ENR_CRCEN))
 #define __BKPSRAM_CLK_DISABLE()      (RCC->AHB1ENR &= ~(RCC_AHB1ENR_BKPSRAMEN))