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mbed(SerialHalfDuplex入り)

TARGET_NUCLEO_F302R8/stm32f3xx_hal_rcc.h@90:cb3d968589d8, 2014-10-28 (annotated)

Committer:: Kojto
Date:: Tue Oct 28 16:40:41 2014 +0000
Revision:: 90:cb3d968589d8

Release 90 of the mbed library



Changes:



- Freescale KSDK update (v1.0)

- K22 - new target addition

- KL43Z - new target addition

- Nucleo F091RC - new target addition

- Nucleo L152RE - STM32Cube driver

- Nordic - Softdevice v7.1.0

- Nvic files - BSD License

- LPC824 - various HAL fixes

- Nucleo F411RE - CMSIS - IAR files

Who changed what in which revision?

User	Revision	Line number	New contents of line
Kojto	90:cb3d968589d8	1	/**
Kojto	90:cb3d968589d8	2	******************************************************************************
Kojto	90:cb3d968589d8	3	* @file stm32f3xx_hal_rcc.h
Kojto	90:cb3d968589d8	4	* @author MCD Application Team
Kojto	90:cb3d968589d8	5	* @version V1.1.0
Kojto	90:cb3d968589d8	6	* @date 12-Sept-2014
Kojto	90:cb3d968589d8	7	* @brief Header file of RCC HAL module.
Kojto	90:cb3d968589d8	8	******************************************************************************
Kojto	90:cb3d968589d8	9	* @attention
Kojto	90:cb3d968589d8	10	*
Kojto	90:cb3d968589d8	11	* <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
Kojto	90:cb3d968589d8	12	*
Kojto	90:cb3d968589d8	13	* Redistribution and use in source and binary forms, with or without modification,
Kojto	90:cb3d968589d8	14	* are permitted provided that the following conditions are met:
Kojto	90:cb3d968589d8	15	* 1. Redistributions of source code must retain the above copyright notice,
Kojto	90:cb3d968589d8	16	* this list of conditions and the following disclaimer.
Kojto	90:cb3d968589d8	17	* 2. Redistributions in binary form must reproduce the above copyright notice,
Kojto	90:cb3d968589d8	18	* this list of conditions and the following disclaimer in the documentation
Kojto	90:cb3d968589d8	19	* and/or other materials provided with the distribution.
Kojto	90:cb3d968589d8	20	* 3. Neither the name of STMicroelectronics nor the names of its contributors
Kojto	90:cb3d968589d8	21	* may be used to endorse or promote products derived from this software
Kojto	90:cb3d968589d8	22	* without specific prior written permission.
Kojto	90:cb3d968589d8	23	*
Kojto	90:cb3d968589d8	24	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
Kojto	90:cb3d968589d8	25	* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
Kojto	90:cb3d968589d8	26	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
Kojto	90:cb3d968589d8	27	* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
Kojto	90:cb3d968589d8	28	* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
Kojto	90:cb3d968589d8	29	* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
Kojto	90:cb3d968589d8	30	* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
Kojto	90:cb3d968589d8	31	* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
Kojto	90:cb3d968589d8	32	* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
Kojto	90:cb3d968589d8	33	* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
Kojto	90:cb3d968589d8	34	*
Kojto	90:cb3d968589d8	35	******************************************************************************
Kojto	90:cb3d968589d8	36	*/
Kojto	90:cb3d968589d8	37
Kojto	90:cb3d968589d8	38	/* Define to prevent recursive inclusion -------------------------------------*/
Kojto	90:cb3d968589d8	39	#ifndef __STM32F3xx_HAL_RCC_H
Kojto	90:cb3d968589d8	40	#define __STM32F3xx_HAL_RCC_H
Kojto	90:cb3d968589d8	41
Kojto	90:cb3d968589d8	42	#ifdef __cplusplus
Kojto	90:cb3d968589d8	43	extern "C" {
Kojto	90:cb3d968589d8	44	#endif
Kojto	90:cb3d968589d8	45
Kojto	90:cb3d968589d8	46	/* Includes ------------------------------------------------------------------*/
Kojto	90:cb3d968589d8	47	#include "stm32f3xx_hal_def.h"
Kojto	90:cb3d968589d8	48
Kojto	90:cb3d968589d8	49	/** @addtogroup STM32F3xx_HAL_Driver
Kojto	90:cb3d968589d8	50	* @{
Kojto	90:cb3d968589d8	51	*/
Kojto	90:cb3d968589d8	52
Kojto	90:cb3d968589d8	53	/** @addtogroup RCC
Kojto	90:cb3d968589d8	54	* @{
Kojto	90:cb3d968589d8	55	*/
Kojto	90:cb3d968589d8	56
Kojto	90:cb3d968589d8	57	/* Exported types ------------------------------------------------------------*/
Kojto	90:cb3d968589d8	58
Kojto	90:cb3d968589d8	59	/** @defgroup RCC_Exported_Types RCC Exported Types
Kojto	90:cb3d968589d8	60	* @{
Kojto	90:cb3d968589d8	61	*/
Kojto	90:cb3d968589d8	62
Kojto	90:cb3d968589d8	63	/**
Kojto	90:cb3d968589d8	64	* @brief RCC System, AHB and APB busses clock configuration structure definition
Kojto	90:cb3d968589d8	65	*/
Kojto	90:cb3d968589d8	66	typedef struct
Kojto	90:cb3d968589d8	67	{
Kojto	90:cb3d968589d8	68	uint32_t ClockType; /*!< The clock to be configured.
Kojto	90:cb3d968589d8	69	This parameter can be a value of @ref RCC_System_Clock_Type */
Kojto	90:cb3d968589d8	70
Kojto	90:cb3d968589d8	71	uint32_t SYSCLKSource; /*!< The clock source (SYSCLKS) used as system clock.
Kojto	90:cb3d968589d8	72	This parameter can be a value of @ref RCC_System_Clock_Source */
Kojto	90:cb3d968589d8	73
Kojto	90:cb3d968589d8	74	uint32_t AHBCLKDivider; /*!< The AHB clock (HCLK) divider. This clock is derived from the system clock (SYSCLK).
Kojto	90:cb3d968589d8	75	This parameter can be a value of @ref RCC_AHB_Clock_Source */
Kojto	90:cb3d968589d8	76
Kojto	90:cb3d968589d8	77	uint32_t APB1CLKDivider; /*!< The APB1 clock (PCLK1) divider. This clock is derived from the AHB clock (HCLK).
Kojto	90:cb3d968589d8	78	This parameter can be a value of @ref RCC_APB1_APB2_Clock_Source */
Kojto	90:cb3d968589d8	79
Kojto	90:cb3d968589d8	80	uint32_t APB2CLKDivider; /*!< The APB2 clock (PCLK2) divider. This clock is derived from the AHB clock (HCLK).
Kojto	90:cb3d968589d8	81	This parameter can be a value of @ref RCC_APB1_APB2_Clock_Source */
Kojto	90:cb3d968589d8	82
Kojto	90:cb3d968589d8	83	}RCC_ClkInitTypeDef;
Kojto	90:cb3d968589d8	84
Kojto	90:cb3d968589d8	85	/**
Kojto	90:cb3d968589d8	86	* @}
Kojto	90:cb3d968589d8	87	*/
Kojto	90:cb3d968589d8	88
Kojto	90:cb3d968589d8	89	/* Exported constants --------------------------------------------------------*/
Kojto	90:cb3d968589d8	90	/** @defgroup RCC_Exported_Constants RCC Exported Constants
Kojto	90:cb3d968589d8	91	* @{
Kojto	90:cb3d968589d8	92	*/
Kojto	90:cb3d968589d8	93
Kojto	90:cb3d968589d8	94	/** @defgroup RCC_BitAddress_AliasRegion RCC BitAddress AliasRegion
Kojto	90:cb3d968589d8	95	* @brief RCC registers bit address in the alias region
Kojto	90:cb3d968589d8	96	* @{
Kojto	90:cb3d968589d8	97	*/
Kojto	90:cb3d968589d8	98	#define RCC_OFFSET (RCC_BASE - PERIPH_BASE)
Kojto	90:cb3d968589d8	99	/* --- CR Register ---*/
Kojto	90:cb3d968589d8	100	#define RCC_CR_OFFSET (RCC_OFFSET + 0x00)
Kojto	90:cb3d968589d8	101	/* Alias word address of HSION bit */
Kojto	90:cb3d968589d8	102	#define HSION_BitNumber 0
Kojto	90:cb3d968589d8	103	#define CR_HSION_BB (PERIPH_BB_BASE + (RCC_CR_OFFSET * 32) + (HSION_BitNumber * 4))
Kojto	90:cb3d968589d8	104	/* Alias word address of HSEON bit */
Kojto	90:cb3d968589d8	105	#define HSEON_BitNumber 16
Kojto	90:cb3d968589d8	106	#define CR_HSEON_BB (PERIPH_BB_BASE + (RCC_CR_OFFSET * 32) + (HSEON_BitNumber * 4))
Kojto	90:cb3d968589d8	107	/* Alias word address of CSSON bit */
Kojto	90:cb3d968589d8	108	#define CSSON_BitNumber 19
Kojto	90:cb3d968589d8	109	#define CR_CSSON_BB (PERIPH_BB_BASE + (RCC_CR_OFFSET * 32) + (CSSON_BitNumber * 4))
Kojto	90:cb3d968589d8	110	/* Alias word address of PLLON bit */
Kojto	90:cb3d968589d8	111	#define PLLON_BitNumber 24
Kojto	90:cb3d968589d8	112	#define CR_PLLON_BB (PERIPH_BB_BASE + (RCC_CR_OFFSET * 32) + (PLLON_BitNumber * 4))
Kojto	90:cb3d968589d8	113
Kojto	90:cb3d968589d8	114	/* --- CFGR Register ---*/
Kojto	90:cb3d968589d8	115	#define RCC_CFGR_OFFSET (RCC_OFFSET + 0x04)
Kojto	90:cb3d968589d8	116	/* Alias word address of PLLSRC bit */
Kojto	90:cb3d968589d8	117	#define PLLSRC_BitNumber 16
Kojto	90:cb3d968589d8	118	#define CFGR_PLLSRC_BB (PERIPH_BB_BASE + (RCC_CFGR_OFFSET * 32) + (PLLSRC_BitNumber * 4))
Kojto	90:cb3d968589d8	119
Kojto	90:cb3d968589d8	120	/* --- CIR Register ---*/
Kojto	90:cb3d968589d8	121	#define RCC_CIR_OFFSET (RCC_OFFSET + 0x08)
Kojto	90:cb3d968589d8	122
Kojto	90:cb3d968589d8	123	/* --- BDCR Register ---*/
Kojto	90:cb3d968589d8	124	#define RCC_BDCR_OFFSET (RCC_OFFSET + 0x20)
Kojto	90:cb3d968589d8	125	/* Alias word address of LSEON bit */
Kojto	90:cb3d968589d8	126	#define LSEON_BitNumber 0
Kojto	90:cb3d968589d8	127	#define BDCR_LSEON_BB (PERIPH_BB_BASE + (RCC_BDCR_OFFSET * 32) + (LSEON_BitNumber * 4))
Kojto	90:cb3d968589d8	128	/* Alias word address of RTCEN bit */
Kojto	90:cb3d968589d8	129	#define RTCEN_BitNumber 15
Kojto	90:cb3d968589d8	130	#define BDCR_RTCEN_BB (PERIPH_BB_BASE + (RCC_BDCR_OFFSET * 32) + (RTCEN_BitNumber * 4))
Kojto	90:cb3d968589d8	131	/* Alias word address of BDRST bit */
Kojto	90:cb3d968589d8	132	#define BDRST_BitNumber 16
Kojto	90:cb3d968589d8	133	#define BDCR_BDRST_BB (PERIPH_BB_BASE + (RCC_BDCR_OFFSET * 32) + (BDRST_BitNumber * 4))
Kojto	90:cb3d968589d8	134
Kojto	90:cb3d968589d8	135	/* --- CSR Register ---*/
Kojto	90:cb3d968589d8	136	#define RCC_CSR_OFFSET (RCC_OFFSET + 0x24)
Kojto	90:cb3d968589d8	137	/* Alias word address of LSION bit */
Kojto	90:cb3d968589d8	138	#define LSION_BitNumber 0
Kojto	90:cb3d968589d8	139	#define CSR_LSION_BB (PERIPH_BB_BASE + (RCC_CSR_OFFSET * 32) + (LSION_BitNumber * 4))
Kojto	90:cb3d968589d8	140	/* Alias word address of RMVF bit */
Kojto	90:cb3d968589d8	141	#define RMVF_BitNumber 24
Kojto	90:cb3d968589d8	142	#define CSR_RMVF_BB (PERIPH_BB_BASE + (RCC_CSR_OFFSET * 32) + (RMVF_BitNumber * 4))
Kojto	90:cb3d968589d8	143
Kojto	90:cb3d968589d8	144	/* CR register byte 2 (Bits[23:16]) base address */
Kojto	90:cb3d968589d8	145	#define CR_BYTE2_ADDRESS (PERIPH_BASE + RCC_CR_OFFSET + 0x02)
Kojto	90:cb3d968589d8	146
Kojto	90:cb3d968589d8	147	/* CIR register byte 1 (Bits[15:8]) base address */
Kojto	90:cb3d968589d8	148	#define CIR_BYTE1_ADDRESS (PERIPH_BASE + RCC_CIR_OFFSET + 0x01)
Kojto	90:cb3d968589d8	149
Kojto	90:cb3d968589d8	150	/* CIR register byte 2 (Bits[23:16]) base address */
Kojto	90:cb3d968589d8	151	#define CIR_BYTE2_ADDRESS (PERIPH_BASE + RCC_CIR_OFFSET + 0x02)
Kojto	90:cb3d968589d8	152
Kojto	90:cb3d968589d8	153	/* CSR register byte 1 (Bits[15:8]) base address */
Kojto	90:cb3d968589d8	154	#define CSR_BYTE1_ADDRESS (PERIPH_BASE + RCC_CSR_OFFSET + 0x01)
Kojto	90:cb3d968589d8	155
Kojto	90:cb3d968589d8	156	/* BDCR register byte 0 (Bits[7:0] base address */
Kojto	90:cb3d968589d8	157	#define BDCR_BYTE0_ADDRESS (PERIPH_BASE + RCC_BDCR_OFFSET)
Kojto	90:cb3d968589d8	158
Kojto	90:cb3d968589d8	159	/**
Kojto	90:cb3d968589d8	160	* @}
Kojto	90:cb3d968589d8	161	*/
Kojto	90:cb3d968589d8	162
Kojto	90:cb3d968589d8	163	/** @defgroup RCC_Timeout RCC Timeout
Kojto	90:cb3d968589d8	164	* @{
Kojto	90:cb3d968589d8	165	*/
Kojto	90:cb3d968589d8	166	/* LSE state change timeout */
Kojto	90:cb3d968589d8	167	#define LSE_TIMEOUT_VALUE ((uint32_t)5000) /* 5 s */
Kojto	90:cb3d968589d8	168
Kojto	90:cb3d968589d8	169	/* Disable Backup domain write protection state change timeout */
Kojto	90:cb3d968589d8	170	#define DBP_TIMEOUT_VALUE ((uint32_t)100) /* 100 ms */
Kojto	90:cb3d968589d8	171	/**
Kojto	90:cb3d968589d8	172	* @}
Kojto	90:cb3d968589d8	173	*/
Kojto	90:cb3d968589d8	174
Kojto	90:cb3d968589d8	175	/** @defgroup RCC_Oscillator_Type RCC Oscillator Type
Kojto	90:cb3d968589d8	176	* @{
Kojto	90:cb3d968589d8	177	*/
Kojto	90:cb3d968589d8	178	#define RCC_OSCILLATORTYPE_NONE ((uint32_t)0x00000000)
Kojto	90:cb3d968589d8	179	#define RCC_OSCILLATORTYPE_HSE ((uint32_t)0x00000001)
Kojto	90:cb3d968589d8	180	#define RCC_OSCILLATORTYPE_HSI ((uint32_t)0x00000002)
Kojto	90:cb3d968589d8	181	#define RCC_OSCILLATORTYPE_LSE ((uint32_t)0x00000004)
Kojto	90:cb3d968589d8	182	#define RCC_OSCILLATORTYPE_LSI ((uint32_t)0x00000008)
Kojto	90:cb3d968589d8	183
Kojto	90:cb3d968589d8	184	#define IS_RCC_OSCILLATORTYPE(OSCILLATOR) (((OSCILLATOR) == RCC_OSCILLATORTYPE_NONE) \|\| \
Kojto	90:cb3d968589d8	185	(((OSCILLATOR) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE) \|\| \
Kojto	90:cb3d968589d8	186	(((OSCILLATOR) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI) \|\| \
Kojto	90:cb3d968589d8	187	(((OSCILLATOR) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI) \|\| \
Kojto	90:cb3d968589d8	188	(((OSCILLATOR) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE))
Kojto	90:cb3d968589d8	189	/**
Kojto	90:cb3d968589d8	190	* @}
Kojto	90:cb3d968589d8	191	*/
Kojto	90:cb3d968589d8	192
Kojto	90:cb3d968589d8	193	/** @defgroup RCC_HSE_Config RCC HSE Config
Kojto	90:cb3d968589d8	194	* @{
Kojto	90:cb3d968589d8	195	*/
Kojto	90:cb3d968589d8	196	#define RCC_HSE_OFF ((uint32_t)0x00000000)
Kojto	90:cb3d968589d8	197	#define RCC_HSE_ON ((uint32_t)0x00000001)
Kojto	90:cb3d968589d8	198	#define RCC_HSE_BYPASS ((uint32_t)0x00000005)
Kojto	90:cb3d968589d8	199
Kojto	90:cb3d968589d8	200	#define IS_RCC_HSE(HSE) (((HSE) == RCC_HSE_OFF) \|\| ((HSE) == RCC_HSE_ON) \|\| \
Kojto	90:cb3d968589d8	201	((HSE) == RCC_HSE_BYPASS))
Kojto	90:cb3d968589d8	202	/**
Kojto	90:cb3d968589d8	203	* @}
Kojto	90:cb3d968589d8	204	*/
Kojto	90:cb3d968589d8	205
Kojto	90:cb3d968589d8	206	/** @defgroup RCC_LSE_Config RCC_LSE_Config
Kojto	90:cb3d968589d8	207	* @{
Kojto	90:cb3d968589d8	208	*/
Kojto	90:cb3d968589d8	209	#define RCC_LSE_OFF ((uint32_t)0x00000000)
Kojto	90:cb3d968589d8	210	#define RCC_LSE_ON ((uint32_t)0x00000001)
Kojto	90:cb3d968589d8	211	#define RCC_LSE_BYPASS ((uint32_t)0x00000005)
Kojto	90:cb3d968589d8	212
Kojto	90:cb3d968589d8	213	#define IS_RCC_LSE(LSE) (((LSE) == RCC_LSE_OFF) \|\| ((LSE) == RCC_LSE_ON) \|\| \
Kojto	90:cb3d968589d8	214	((LSE) == RCC_LSE_BYPASS))
Kojto	90:cb3d968589d8	215	/**
Kojto	90:cb3d968589d8	216	* @}
Kojto	90:cb3d968589d8	217	*/
Kojto	90:cb3d968589d8	218
Kojto	90:cb3d968589d8	219	/** @defgroup RCC_HSI_Config RCC HSI Config
Kojto	90:cb3d968589d8	220	* @{
Kojto	90:cb3d968589d8	221	*/
Kojto	90:cb3d968589d8	222	#define RCC_HSI_OFF ((uint32_t)0x00000000)
Kojto	90:cb3d968589d8	223	#define RCC_HSI_ON ((uint32_t)0x00000001)
Kojto	90:cb3d968589d8	224
Kojto	90:cb3d968589d8	225	#define IS_RCC_HSI(HSI) (((HSI) == RCC_HSI_OFF) \|\| ((HSI) == RCC_HSI_ON))
Kojto	90:cb3d968589d8	226
Kojto	90:cb3d968589d8	227	#define RCC_HSICALIBRATION_DEFAULT ((uint32_t)0x10) /* Default HSI calibration trimming value */
Kojto	90:cb3d968589d8	228
Kojto	90:cb3d968589d8	229	#define IS_RCC_CALIBRATION_VALUE(__VALUE__) ((__VALUE__) <= 0x1F)
Kojto	90:cb3d968589d8	230	/**
Kojto	90:cb3d968589d8	231	* @}
Kojto	90:cb3d968589d8	232	*/
Kojto	90:cb3d968589d8	233
Kojto	90:cb3d968589d8	234	/** @defgroup RCC_LSI_Config RCC LSI Config
Kojto	90:cb3d968589d8	235	* @{
Kojto	90:cb3d968589d8	236	*/
Kojto	90:cb3d968589d8	237	#define RCC_LSI_OFF ((uint32_t)0x00000000)
Kojto	90:cb3d968589d8	238	#define RCC_LSI_ON ((uint32_t)0x00000001)
Kojto	90:cb3d968589d8	239
Kojto	90:cb3d968589d8	240	#define IS_RCC_LSI(LSI) (((LSI) == RCC_LSI_OFF) \|\| ((LSI) == RCC_LSI_ON))
Kojto	90:cb3d968589d8	241	/**
Kojto	90:cb3d968589d8	242	* @}
Kojto	90:cb3d968589d8	243	*/
Kojto	90:cb3d968589d8	244
Kojto	90:cb3d968589d8	245	/** @defgroup RCC_PLL_Config RCC PLL Config
Kojto	90:cb3d968589d8	246	* @{
Kojto	90:cb3d968589d8	247	*/
Kojto	90:cb3d968589d8	248	#define RCC_PLL_NONE ((uint32_t)0x00000000)
Kojto	90:cb3d968589d8	249	#define RCC_PLL_OFF ((uint32_t)0x00000001)
Kojto	90:cb3d968589d8	250	#define RCC_PLL_ON ((uint32_t)0x00000002)
Kojto	90:cb3d968589d8	251
Kojto	90:cb3d968589d8	252	#define IS_RCC_PLL(PLL) (((PLL) == RCC_PLL_NONE) \|\|((PLL) == RCC_PLL_OFF) \|\| ((PLL) == RCC_PLL_ON))
Kojto	90:cb3d968589d8	253	/**
Kojto	90:cb3d968589d8	254	* @}
Kojto	90:cb3d968589d8	255	*/
Kojto	90:cb3d968589d8	256
Kojto	90:cb3d968589d8	257	/** @defgroup RCC_PLL_Multiplication_Factor RCC PLL Multiplication Factor
Kojto	90:cb3d968589d8	258	* @{
Kojto	90:cb3d968589d8	259	*/
Kojto	90:cb3d968589d8	260	#define RCC_PLL_MUL2 RCC_CFGR_PLLMUL2
Kojto	90:cb3d968589d8	261	#define RCC_PLL_MUL3 RCC_CFGR_PLLMUL3
Kojto	90:cb3d968589d8	262	#define RCC_PLL_MUL4 RCC_CFGR_PLLMUL4
Kojto	90:cb3d968589d8	263	#define RCC_PLL_MUL5 RCC_CFGR_PLLMUL5
Kojto	90:cb3d968589d8	264	#define RCC_PLL_MUL6 RCC_CFGR_PLLMUL6
Kojto	90:cb3d968589d8	265	#define RCC_PLL_MUL7 RCC_CFGR_PLLMUL7
Kojto	90:cb3d968589d8	266	#define RCC_PLL_MUL8 RCC_CFGR_PLLMUL8
Kojto	90:cb3d968589d8	267	#define RCC_PLL_MUL9 RCC_CFGR_PLLMUL9
Kojto	90:cb3d968589d8	268	#define RCC_PLL_MUL10 RCC_CFGR_PLLMUL10
Kojto	90:cb3d968589d8	269	#define RCC_PLL_MUL11 RCC_CFGR_PLLMUL11
Kojto	90:cb3d968589d8	270	#define RCC_PLL_MUL12 RCC_CFGR_PLLMUL12
Kojto	90:cb3d968589d8	271	#define RCC_PLL_MUL13 RCC_CFGR_PLLMUL13
Kojto	90:cb3d968589d8	272	#define RCC_PLL_MUL14 RCC_CFGR_PLLMUL14
Kojto	90:cb3d968589d8	273	#define RCC_PLL_MUL15 RCC_CFGR_PLLMUL15
Kojto	90:cb3d968589d8	274	#define RCC_PLL_MUL16 RCC_CFGR_PLLMUL16
Kojto	90:cb3d968589d8	275
Kojto	90:cb3d968589d8	276	#define IS_RCC_PLL_MUL(MUL) (((MUL) == RCC_PLL_MUL2) \|\| ((MUL) == RCC_PLL_MUL3) \|\| \
Kojto	90:cb3d968589d8	277	((MUL) == RCC_PLL_MUL4) \|\| ((MUL) == RCC_PLL_MUL5) \|\| \
Kojto	90:cb3d968589d8	278	((MUL) == RCC_PLL_MUL6) \|\| ((MUL) == RCC_PLL_MUL7) \|\| \
Kojto	90:cb3d968589d8	279	((MUL) == RCC_PLL_MUL8) \|\| ((MUL) == RCC_PLL_MUL9) \|\| \
Kojto	90:cb3d968589d8	280	((MUL) == RCC_PLL_MUL10) \|\| ((MUL) == RCC_PLL_MUL11) \|\| \
Kojto	90:cb3d968589d8	281	((MUL) == RCC_PLL_MUL12) \|\| ((MUL) == RCC_PLL_MUL13) \|\| \
Kojto	90:cb3d968589d8	282	((MUL) == RCC_PLL_MUL14) \|\| ((MUL) == RCC_PLL_MUL15) \|\| \
Kojto	90:cb3d968589d8	283	((MUL) == RCC_PLL_MUL16))
Kojto	90:cb3d968589d8	284	/**
Kojto	90:cb3d968589d8	285	* @}
Kojto	90:cb3d968589d8	286	*/
Kojto	90:cb3d968589d8	287
Kojto	90:cb3d968589d8	288	/** @defgroup RCC_System_Clock_Type RCC System Clock Type
Kojto	90:cb3d968589d8	289	* @{
Kojto	90:cb3d968589d8	290	*/
Kojto	90:cb3d968589d8	291	#define RCC_CLOCKTYPE_SYSCLK ((uint32_t)0x00000001)
Kojto	90:cb3d968589d8	292	#define RCC_CLOCKTYPE_HCLK ((uint32_t)0x00000002)
Kojto	90:cb3d968589d8	293	#define RCC_CLOCKTYPE_PCLK1 ((uint32_t)0x00000004)
Kojto	90:cb3d968589d8	294	#define RCC_CLOCKTYPE_PCLK2 ((uint32_t)0x00000008)
Kojto	90:cb3d968589d8	295
Kojto	90:cb3d968589d8	296	#define IS_RCC_CLOCKTYPE(CLK) ((((CLK) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK) \|\| \
Kojto	90:cb3d968589d8	297	(((CLK) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK) \|\| \
Kojto	90:cb3d968589d8	298	(((CLK) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1) \|\| \
Kojto	90:cb3d968589d8	299	(((CLK) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2))
Kojto	90:cb3d968589d8	300	/**
Kojto	90:cb3d968589d8	301	* @}
Kojto	90:cb3d968589d8	302	*/
Kojto	90:cb3d968589d8	303
Kojto	90:cb3d968589d8	304	/** @defgroup RCC_System_Clock_Source RCC System Clock Source
Kojto	90:cb3d968589d8	305	* @{
Kojto	90:cb3d968589d8	306	*/
Kojto	90:cb3d968589d8	307	#define RCC_SYSCLKSOURCE_HSI RCC_CFGR_SW_HSI
Kojto	90:cb3d968589d8	308	#define RCC_SYSCLKSOURCE_HSE RCC_CFGR_SW_HSE
Kojto	90:cb3d968589d8	309	#define RCC_SYSCLKSOURCE_PLLCLK RCC_CFGR_SW_PLL
Kojto	90:cb3d968589d8	310
Kojto	90:cb3d968589d8	311	#define IS_RCC_SYSCLKSOURCE(SOURCE) (((SOURCE) == RCC_SYSCLKSOURCE_HSI) \|\| \
Kojto	90:cb3d968589d8	312	((SOURCE) == RCC_SYSCLKSOURCE_HSE) \|\| \
Kojto	90:cb3d968589d8	313	((SOURCE) == RCC_SYSCLKSOURCE_PLLCLK))
Kojto	90:cb3d968589d8	314	/**
Kojto	90:cb3d968589d8	315	* @}
Kojto	90:cb3d968589d8	316	*/
Kojto	90:cb3d968589d8	317
Kojto	90:cb3d968589d8	318	/** @defgroup RCC_System_Clock_Source_Status RCC System Clock Source Status
Kojto	90:cb3d968589d8	319	* @{
Kojto	90:cb3d968589d8	320	*/
Kojto	90:cb3d968589d8	321	#define RCC_SYSCLKSOURCE_STATUS_HSI RCC_CFGR_SWS_HSI
Kojto	90:cb3d968589d8	322	#define RCC_SYSCLKSOURCE_STATUS_HSE RCC_CFGR_SWS_HSE
Kojto	90:cb3d968589d8	323	#define RCC_SYSCLKSOURCE_STATUS_PLLCLK RCC_CFGR_SWS_PLL
Kojto	90:cb3d968589d8	324
Kojto	90:cb3d968589d8	325	#define IS_RCC_SYSCLKSOURCE_STATUS(SOURCE) (((SOURCE) == RCC_SYSCLKSOURCE_STATUS_HSI) \|\| \
Kojto	90:cb3d968589d8	326	((SOURCE) == RCC_SYSCLKSOURCE_STATUS_HSE) \|\| \
Kojto	90:cb3d968589d8	327	((SOURCE) == RCC_SYSCLKSOURCE_STATUS_PLLCLK)))
Kojto	90:cb3d968589d8	328	/**
Kojto	90:cb3d968589d8	329	* @}
Kojto	90:cb3d968589d8	330	*/
Kojto	90:cb3d968589d8	331
Kojto	90:cb3d968589d8	332	/** @defgroup RCC_AHB_Clock_Source RCC AHB Clock Source
Kojto	90:cb3d968589d8	333	* @{
Kojto	90:cb3d968589d8	334	*/
Kojto	90:cb3d968589d8	335	#define RCC_SYSCLK_DIV1 RCC_CFGR_HPRE_DIV1
Kojto	90:cb3d968589d8	336	#define RCC_SYSCLK_DIV2 RCC_CFGR_HPRE_DIV2
Kojto	90:cb3d968589d8	337	#define RCC_SYSCLK_DIV4 RCC_CFGR_HPRE_DIV4
Kojto	90:cb3d968589d8	338	#define RCC_SYSCLK_DIV8 RCC_CFGR_HPRE_DIV8
Kojto	90:cb3d968589d8	339	#define RCC_SYSCLK_DIV16 RCC_CFGR_HPRE_DIV16
Kojto	90:cb3d968589d8	340	#define RCC_SYSCLK_DIV64 RCC_CFGR_HPRE_DIV64
Kojto	90:cb3d968589d8	341	#define RCC_SYSCLK_DIV128 RCC_CFGR_HPRE_DIV128
Kojto	90:cb3d968589d8	342	#define RCC_SYSCLK_DIV256 RCC_CFGR_HPRE_DIV256
Kojto	90:cb3d968589d8	343	#define RCC_SYSCLK_DIV512 RCC_CFGR_HPRE_DIV512
Kojto	90:cb3d968589d8	344
Kojto	90:cb3d968589d8	345	#define IS_RCC_SYSCLK_DIV(DIV) (((DIV) == RCC_SYSCLK_DIV1) \|\| ((DIV) == RCC_SYSCLK_DIV2) \|\| \
Kojto	90:cb3d968589d8	346	((DIV) == RCC_SYSCLK_DIV4) \|\| ((DIV) == RCC_SYSCLK_DIV8) \|\| \
Kojto	90:cb3d968589d8	347	((DIV) == RCC_SYSCLK_DIV16) \|\| ((DIV) == RCC_SYSCLK_DIV64) \|\| \
Kojto	90:cb3d968589d8	348	((DIV) == RCC_SYSCLK_DIV128) \|\| ((DIV) == RCC_SYSCLK_DIV256) \|\| \
Kojto	90:cb3d968589d8	349	((DIV) == RCC_SYSCLK_DIV512))
Kojto	90:cb3d968589d8	350	/**
Kojto	90:cb3d968589d8	351	* @}
Kojto	90:cb3d968589d8	352	*/
Kojto	90:cb3d968589d8	353
Kojto	90:cb3d968589d8	354	/** @defgroup RCC_APB1_APB2_Clock_Source RCC APB1 APB2 Clock Source
Kojto	90:cb3d968589d8	355	* @{
Kojto	90:cb3d968589d8	356	*/
Kojto	90:cb3d968589d8	357	#define RCC_HCLK_DIV1 RCC_CFGR_PPRE1_DIV1
Kojto	90:cb3d968589d8	358	#define RCC_HCLK_DIV2 RCC_CFGR_PPRE1_DIV2
Kojto	90:cb3d968589d8	359	#define RCC_HCLK_DIV4 RCC_CFGR_PPRE1_DIV4
Kojto	90:cb3d968589d8	360	#define RCC_HCLK_DIV8 RCC_CFGR_PPRE1_DIV8
Kojto	90:cb3d968589d8	361	#define RCC_HCLK_DIV16 RCC_CFGR_PPRE1_DIV16
Kojto	90:cb3d968589d8	362
Kojto	90:cb3d968589d8	363	#define IS_RCC_HCLK_DIV(DIV) (((DIV) == RCC_HCLK_DIV1) \|\| ((DIV) == RCC_HCLK_DIV2) \|\| \
Kojto	90:cb3d968589d8	364	((DIV) == RCC_HCLK_DIV4) \|\| ((DIV) == RCC_HCLK_DIV8) \|\| \
Kojto	90:cb3d968589d8	365	((DIV) == RCC_HCLK_DIV16))
Kojto	90:cb3d968589d8	366	/**
Kojto	90:cb3d968589d8	367	* @}
Kojto	90:cb3d968589d8	368	*/
Kojto	90:cb3d968589d8	369
Kojto	90:cb3d968589d8	370	/** @defgroup RCC_RTC_Clock_Source RCC RTC Clock Source
Kojto	90:cb3d968589d8	371	* @{
Kojto	90:cb3d968589d8	372	*/
Kojto	90:cb3d968589d8	373	#define RCC_RTCCLKSOURCE_NONE RCC_BDCR_RTCSEL_NOCLOCK
Kojto	90:cb3d968589d8	374	#define RCC_RTCCLKSOURCE_LSE RCC_BDCR_RTCSEL_LSE
Kojto	90:cb3d968589d8	375	#define RCC_RTCCLKSOURCE_LSI RCC_BDCR_RTCSEL_LSI
Kojto	90:cb3d968589d8	376	#define RCC_RTCCLKSOURCE_HSE_DIV32 RCC_BDCR_RTCSEL_HSE
Kojto	90:cb3d968589d8	377
Kojto	90:cb3d968589d8	378	#define IS_RCC_RTCCLKSOURCE(SOURCE) (((SOURCE) == RCC_RTCCLKSOURCE_NONE) \|\| \
Kojto	90:cb3d968589d8	379	((SOURCE) == RCC_RTCCLKSOURCE_LSE) \|\| \
Kojto	90:cb3d968589d8	380	((SOURCE) == RCC_RTCCLKSOURCE_LSI) \|\| \
Kojto	90:cb3d968589d8	381	((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV32))
Kojto	90:cb3d968589d8	382	/**
Kojto	90:cb3d968589d8	383	* @}
Kojto	90:cb3d968589d8	384	*/
Kojto	90:cb3d968589d8	385
Kojto	90:cb3d968589d8	386	/** @defgroup RCC_USART2_Clock_Source RCC USART2 Clock Source
Kojto	90:cb3d968589d8	387	* @{
Kojto	90:cb3d968589d8	388	*/
Kojto	90:cb3d968589d8	389	#define RCC_USART2CLKSOURCE_PCLK1 RCC_CFGR3_USART2SW_PCLK
Kojto	90:cb3d968589d8	390	#define RCC_USART2CLKSOURCE_SYSCLK RCC_CFGR3_USART2SW_SYSCLK
Kojto	90:cb3d968589d8	391	#define RCC_USART2CLKSOURCE_LSE RCC_CFGR3_USART2SW_LSE
Kojto	90:cb3d968589d8	392	#define RCC_USART2CLKSOURCE_HSI RCC_CFGR3_USART2SW_HSI
Kojto	90:cb3d968589d8	393
Kojto	90:cb3d968589d8	394	#define IS_RCC_USART2CLKSOURCE(SOURCE) (((SOURCE) == RCC_USART2CLKSOURCE_PCLK1) \|\| \
Kojto	90:cb3d968589d8	395	((SOURCE) == RCC_USART2CLKSOURCE_SYSCLK) \|\| \
Kojto	90:cb3d968589d8	396	((SOURCE) == RCC_USART2CLKSOURCE_LSE) \|\| \
Kojto	90:cb3d968589d8	397	((SOURCE) == RCC_USART2CLKSOURCE_HSI))
Kojto	90:cb3d968589d8	398	/**
Kojto	90:cb3d968589d8	399	* @}
Kojto	90:cb3d968589d8	400	*/
Kojto	90:cb3d968589d8	401
Kojto	90:cb3d968589d8	402	/** @defgroup RCC_USART3_Clock_Source RCC USART3 Clock Source
Kojto	90:cb3d968589d8	403	* @{
Kojto	90:cb3d968589d8	404	*/
Kojto	90:cb3d968589d8	405	#define RCC_USART3CLKSOURCE_PCLK1 RCC_CFGR3_USART3SW_PCLK
Kojto	90:cb3d968589d8	406	#define RCC_USART3CLKSOURCE_SYSCLK RCC_CFGR3_USART3SW_SYSCLK
Kojto	90:cb3d968589d8	407	#define RCC_USART3CLKSOURCE_LSE RCC_CFGR3_USART3SW_LSE
Kojto	90:cb3d968589d8	408	#define RCC_USART3CLKSOURCE_HSI RCC_CFGR3_USART3SW_HSI
Kojto	90:cb3d968589d8	409
Kojto	90:cb3d968589d8	410	#define IS_RCC_USART3CLKSOURCE(SOURCE) (((SOURCE) == RCC_USART3CLKSOURCE_PCLK1) \|\| \
Kojto	90:cb3d968589d8	411	((SOURCE) == RCC_USART3CLKSOURCE_SYSCLK) \|\| \
Kojto	90:cb3d968589d8	412	((SOURCE) == RCC_USART3CLKSOURCE_LSE) \|\| \
Kojto	90:cb3d968589d8	413	((SOURCE) == RCC_USART3CLKSOURCE_HSI))
Kojto	90:cb3d968589d8	414	/**
Kojto	90:cb3d968589d8	415	* @}
Kojto	90:cb3d968589d8	416	*/
Kojto	90:cb3d968589d8	417
Kojto	90:cb3d968589d8	418	/** @defgroup RCC_I2C1_Clock_Source RCC I2C1 Clock Source
Kojto	90:cb3d968589d8	419	* @{
Kojto	90:cb3d968589d8	420	*/
Kojto	90:cb3d968589d8	421	#define RCC_I2C1CLKSOURCE_HSI RCC_CFGR3_I2C1SW_HSI
Kojto	90:cb3d968589d8	422	#define RCC_I2C1CLKSOURCE_SYSCLK RCC_CFGR3_I2C1SW_SYSCLK
Kojto	90:cb3d968589d8	423
Kojto	90:cb3d968589d8	424	#define IS_RCC_I2C1CLKSOURCE(SOURCE) (((SOURCE) == RCC_I2C1CLKSOURCE_HSI) \|\| \
Kojto	90:cb3d968589d8	425	((SOURCE) == RCC_I2C1CLKSOURCE_SYSCLK))
Kojto	90:cb3d968589d8	426	/**
Kojto	90:cb3d968589d8	427	* @}
Kojto	90:cb3d968589d8	428	*/
Kojto	90:cb3d968589d8	429
Kojto	90:cb3d968589d8	430	/** @defgroup RCC_MCOx_Index RCC MCOx Index
Kojto	90:cb3d968589d8	431	* @{
Kojto	90:cb3d968589d8	432	*/
Kojto	90:cb3d968589d8	433	#define RCC_MCO ((uint32_t)0x00000000)
Kojto	90:cb3d968589d8	434
Kojto	90:cb3d968589d8	435	#define IS_RCC_MCO(MCOx) ((MCOx) == RCC_MCO)
Kojto	90:cb3d968589d8	436	/**
Kojto	90:cb3d968589d8	437	* @}
Kojto	90:cb3d968589d8	438	*/
Kojto	90:cb3d968589d8	439
Kojto	90:cb3d968589d8	440	/** @defgroup RCC_Interrupt RCC Interrupt
Kojto	90:cb3d968589d8	441	* @{
Kojto	90:cb3d968589d8	442	*/
Kojto	90:cb3d968589d8	443	#define RCC_IT_LSIRDY ((uint32_t)0x00000001)
Kojto	90:cb3d968589d8	444	#define RCC_IT_LSERDY ((uint32_t)0x00000002)
Kojto	90:cb3d968589d8	445	#define RCC_IT_HSIRDY ((uint32_t)0x00000004)
Kojto	90:cb3d968589d8	446	#define RCC_IT_HSERDY ((uint32_t)0x00000008)
Kojto	90:cb3d968589d8	447	#define RCC_IT_PLLRDY ((uint32_t)0x00000010)
Kojto	90:cb3d968589d8	448	#define RCC_IT_CSS ((uint32_t)0x00000080)
Kojto	90:cb3d968589d8	449	/**
Kojto	90:cb3d968589d8	450	* @}
Kojto	90:cb3d968589d8	451	*/
Kojto	90:cb3d968589d8	452
Kojto	90:cb3d968589d8	453	/** @defgroup RCC_Flag RCC Flag
Kojto	90:cb3d968589d8	454	* Elements values convention: 0XXYYYYYb
Kojto	90:cb3d968589d8	455	* - YYYYY : Flag position in the register
Kojto	90:cb3d968589d8	456	* - XX : Register index
Kojto	90:cb3d968589d8	457	* - 01: CR register
Kojto	90:cb3d968589d8	458	* - 10: BDCR register
Kojto	90:cb3d968589d8	459	* - 11: CSR register
Kojto	90:cb3d968589d8	460	* @{
Kojto	90:cb3d968589d8	461	*/
Kojto	90:cb3d968589d8	462	#define CR_REG_INDEX 1U
Kojto	90:cb3d968589d8	463	#define BDCR_REG_INDEX 2U
Kojto	90:cb3d968589d8	464	#define CSR_REG_INDEX 3U
Kojto	90:cb3d968589d8	465
Kojto	90:cb3d968589d8	466	/* Flags in the CR register */
Kojto	90:cb3d968589d8	467	#define RCC_FLAG_HSIRDY ((uint32_t)((CR_REG_INDEX << 5U) \| (uint32_t)(POSITION_VAL(RCC_CR_HSIRDY))))
Kojto	90:cb3d968589d8	468	#define RCC_FLAG_HSERDY ((uint32_t)((CR_REG_INDEX << 5U) \| (uint32_t)(POSITION_VAL(RCC_CR_HSERDY))))
Kojto	90:cb3d968589d8	469	#define RCC_FLAG_PLLRDY ((uint32_t)((CR_REG_INDEX << 5U) \| (uint32_t)(POSITION_VAL(RCC_CR_PLLRDY))))
Kojto	90:cb3d968589d8	470
Kojto	90:cb3d968589d8	471	/* Flags in the BDCR register */
Kojto	90:cb3d968589d8	472	#define RCC_FLAG_LSERDY ((uint32_t)((BDCR_REG_INDEX << 5U) \| (uint32_t)(POSITION_VAL(RCC_BDCR_LSERDY))))
Kojto	90:cb3d968589d8	473
Kojto	90:cb3d968589d8	474	/* Flags in the CSR register */
Kojto	90:cb3d968589d8	475	#define RCC_FLAG_LSIRDY ((uint32_t)((CSR_REG_INDEX << 5U) \| (uint32_t)(POSITION_VAL(RCC_CSR_LSIRDY))))
Kojto	90:cb3d968589d8	476	#define RCC_FLAG_RMV ((uint32_t)((CSR_REG_INDEX << 5U) \| (uint32_t)(POSITION_VAL(RCC_CSR_RMVF))))
Kojto	90:cb3d968589d8	477	#define RCC_FLAG_OBLRST ((uint32_t)((CSR_REG_INDEX << 5U) \| (uint32_t)(POSITION_VAL(RCC_CSR_OBLRSTF))))
Kojto	90:cb3d968589d8	478	#define RCC_FLAG_PINRST ((uint32_t)((CSR_REG_INDEX << 5U) \| (uint32_t)(POSITION_VAL(RCC_CSR_PINRSTF))))
Kojto	90:cb3d968589d8	479	#define RCC_FLAG_PORRST ((uint32_t)((CSR_REG_INDEX << 5U) \| (uint32_t)(POSITION_VAL(RCC_CSR_PORRSTF))))
Kojto	90:cb3d968589d8	480	#define RCC_FLAG_SFTRST ((uint32_t)((CSR_REG_INDEX << 5U) \| (uint32_t)(POSITION_VAL(RCC_CSR_SFTRSTF))))
Kojto	90:cb3d968589d8	481	#define RCC_FLAG_IWDGRST ((uint32_t)((CSR_REG_INDEX << 5U) \| (uint32_t)(POSITION_VAL(RCC_CSR_IWDGRSTF))))
Kojto	90:cb3d968589d8	482	#define RCC_FLAG_WWDGRST ((uint32_t)((CSR_REG_INDEX << 5U) \| (uint32_t)(POSITION_VAL(RCC_CSR_WWDGRSTF))))
Kojto	90:cb3d968589d8	483	#define RCC_FLAG_LPWRRST ((uint32_t)((CSR_REG_INDEX << 5U) \| (uint32_t)(POSITION_VAL(RCC_CSR_LPWRRSTF))))
Kojto	90:cb3d968589d8	484	/**
Kojto	90:cb3d968589d8	485	* @}
Kojto	90:cb3d968589d8	486	*/
Kojto	90:cb3d968589d8	487
Kojto	90:cb3d968589d8	488	/**
Kojto	90:cb3d968589d8	489	* @}
Kojto	90:cb3d968589d8	490	*/
Kojto	90:cb3d968589d8	491	/* Exported macro ------------------------------------------------------------*/
Kojto	90:cb3d968589d8	492
Kojto	90:cb3d968589d8	493	/** @defgroup RCC_Exported_Macros RCC Exported Macros
Kojto	90:cb3d968589d8	494	* @{
Kojto	90:cb3d968589d8	495	*/
Kojto	90:cb3d968589d8	496
Kojto	90:cb3d968589d8	497	/** @defgroup RCC_AHB_Clock_Enable_Disable RCC AHB Clock Enable Disable
Kojto	90:cb3d968589d8	498	* @brief Enable or disable the AHB peripheral clock.
Kojto	90:cb3d968589d8	499	* @note After reset, the peripheral clock (used for registers read/write access)
Kojto	90:cb3d968589d8	500	* is disabled and the application software has to enable this clock before
Kojto	90:cb3d968589d8	501	* using it.
Kojto	90:cb3d968589d8	502	* @{
Kojto	90:cb3d968589d8	503	*/
Kojto	90:cb3d968589d8	504	#define __GPIOA_CLK_ENABLE() (RCC->AHBENR \|= (RCC_AHBENR_GPIOAEN))
Kojto	90:cb3d968589d8	505	#define __GPIOB_CLK_ENABLE() (RCC->AHBENR \|= (RCC_AHBENR_GPIOBEN))
Kojto	90:cb3d968589d8	506	#define __GPIOC_CLK_ENABLE() (RCC->AHBENR \|= (RCC_AHBENR_GPIOCEN))
Kojto	90:cb3d968589d8	507	#define __GPIOD_CLK_ENABLE() (RCC->AHBENR \|= (RCC_AHBENR_GPIODEN))
Kojto	90:cb3d968589d8	508	#define __GPIOF_CLK_ENABLE() (RCC->AHBENR \|= (RCC_AHBENR_GPIOFEN))
Kojto	90:cb3d968589d8	509	#define __CRC_CLK_ENABLE() (RCC->AHBENR \|= (RCC_AHBENR_CRCEN))
Kojto	90:cb3d968589d8	510	#define __DMA1_CLK_ENABLE() (RCC->AHBENR \|= (RCC_AHBENR_DMA1EN))
Kojto	90:cb3d968589d8	511	#define __SRAM_CLK_ENABLE() (RCC->AHBENR \|= (RCC_AHBENR_SRAMEN))
Kojto	90:cb3d968589d8	512	#define __FLITF_CLK_ENABLE() (RCC->AHBENR \|= (RCC_AHBENR_FLITFEN))
Kojto	90:cb3d968589d8	513	#define __TSC_CLK_ENABLE() (RCC->AHBENR \|= (RCC_AHBENR_TSCEN))
Kojto	90:cb3d968589d8	514
Kojto	90:cb3d968589d8	515	#define __GPIOA_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_GPIOAEN))
Kojto	90:cb3d968589d8	516	#define __GPIOB_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_GPIOBEN))
Kojto	90:cb3d968589d8	517	#define __GPIOC_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_GPIOCEN))
Kojto	90:cb3d968589d8	518	#define __GPIOD_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_GPIODEN))
Kojto	90:cb3d968589d8	519	#define __GPIOF_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_GPIOFEN))
Kojto	90:cb3d968589d8	520	#define __CRC_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_CRCEN))
Kojto	90:cb3d968589d8	521	#define __DMA1_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_DMA1EN))
Kojto	90:cb3d968589d8	522	#define __SRAM_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_SRAMEN))
Kojto	90:cb3d968589d8	523	#define __FLITF_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_FLITFEN))
Kojto	90:cb3d968589d8	524	#define __TSC_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_TSCEN))
Kojto	90:cb3d968589d8	525	/**
Kojto	90:cb3d968589d8	526	* @}
Kojto	90:cb3d968589d8	527	*/
Kojto	90:cb3d968589d8	528
Kojto	90:cb3d968589d8	529	/** @defgroup RCC_APB1_Clock_Enable_Disable RCC APB1 Clock Enable Disable
Kojto	90:cb3d968589d8	530	* @brief Enable or disable the Low Speed APB (APB1) peripheral clock.
Kojto	90:cb3d968589d8	531	* @note After reset, the peripheral clock (used for registers read/write access)
Kojto	90:cb3d968589d8	532	* is disabled and the application software has to enable this clock before
Kojto	90:cb3d968589d8	533	* using it.
Kojto	90:cb3d968589d8	534	* @{
Kojto	90:cb3d968589d8	535	*/
Kojto	90:cb3d968589d8	536	#define __TIM2_CLK_ENABLE() (RCC->APB1ENR \|= (RCC_APB1ENR_TIM2EN))
Kojto	90:cb3d968589d8	537	#define __TIM6_CLK_ENABLE() (RCC->APB1ENR \|= (RCC_APB1ENR_TIM6EN))
Kojto	90:cb3d968589d8	538	#define __WWDG_CLK_ENABLE() (RCC->APB1ENR \|= (RCC_APB1ENR_WWDGEN))
Kojto	90:cb3d968589d8	539	#define __USART2_CLK_ENABLE() (RCC->APB1ENR \|= (RCC_APB1ENR_USART2EN))
Kojto	90:cb3d968589d8	540	#define __USART3_CLK_ENABLE() (RCC->APB1ENR \|= (RCC_APB1ENR_USART3EN))
Kojto	90:cb3d968589d8	541	#define __I2C1_CLK_ENABLE() (RCC->APB1ENR \|= (RCC_APB1ENR_I2C1EN))
Kojto	90:cb3d968589d8	542	#define __PWR_CLK_ENABLE() (RCC->APB1ENR \|= (RCC_APB1ENR_PWREN))
Kojto	90:cb3d968589d8	543	#define __DAC1_CLK_ENABLE() (RCC->APB1ENR \|= (RCC_APB1ENR_DAC1EN))
Kojto	90:cb3d968589d8	544
Kojto	90:cb3d968589d8	545	#define __TIM2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM2EN))
Kojto	90:cb3d968589d8	546	#define __TIM6_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM6EN))
Kojto	90:cb3d968589d8	547	#define __WWDG_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_WWDGEN))
Kojto	90:cb3d968589d8	548	#define __USART2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USART2EN))
Kojto	90:cb3d968589d8	549	#define __USART3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USART3EN))
Kojto	90:cb3d968589d8	550	#define __I2C1_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C1EN))
Kojto	90:cb3d968589d8	551	#define __PWR_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_PWREN))
Kojto	90:cb3d968589d8	552	#define __DAC1_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_DAC1EN))
Kojto	90:cb3d968589d8	553	/**
Kojto	90:cb3d968589d8	554	* @}
Kojto	90:cb3d968589d8	555	*/
Kojto	90:cb3d968589d8	556
Kojto	90:cb3d968589d8	557	/** @defgroup RCC_APB2_Clock_Enable_Disable RCC APB2 Clock Enable Disable
Kojto	90:cb3d968589d8	558	* @brief Enable or disable the High Speed APB (APB2) peripheral clock.
Kojto	90:cb3d968589d8	559	* @note After reset, the peripheral clock (used for registers read/write access)
Kojto	90:cb3d968589d8	560	* is disabled and the application software has to enable this clock before
Kojto	90:cb3d968589d8	561	* using it.
Kojto	90:cb3d968589d8	562	* @{
Kojto	90:cb3d968589d8	563	*/
Kojto	90:cb3d968589d8	564	#define __SYSCFG_CLK_ENABLE() (RCC->APB2ENR \|= (RCC_APB2ENR_SYSCFGEN))
Kojto	90:cb3d968589d8	565	#define __TIM15_CLK_ENABLE() (RCC->APB2ENR \|= (RCC_APB2ENR_TIM15EN))
Kojto	90:cb3d968589d8	566	#define __TIM16_CLK_ENABLE() (RCC->APB2ENR \|= (RCC_APB2ENR_TIM16EN))
Kojto	90:cb3d968589d8	567	#define __TIM17_CLK_ENABLE() (RCC->APB2ENR \|= (RCC_APB2ENR_TIM17EN))
Kojto	90:cb3d968589d8	568	#define __USART1_CLK_ENABLE() (RCC->APB2ENR \|= (RCC_APB2ENR_USART1EN))
Kojto	90:cb3d968589d8	569
Kojto	90:cb3d968589d8	570	#define __SYSCFG_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SYSCFGEN))
Kojto	90:cb3d968589d8	571	#define __TIM15_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM15EN))
Kojto	90:cb3d968589d8	572	#define __TIM16_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM16EN))
Kojto	90:cb3d968589d8	573	#define __TIM17_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM17EN))
Kojto	90:cb3d968589d8	574	#define __USART1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_USART1EN))
Kojto	90:cb3d968589d8	575	/**
Kojto	90:cb3d968589d8	576	* @}
Kojto	90:cb3d968589d8	577	*/
Kojto	90:cb3d968589d8	578
Kojto	90:cb3d968589d8	579	/** @defgroup RCC_AHB_Force_Release_Reset RCC AHB Force Release Reset
Kojto	90:cb3d968589d8	580	* @brief Force or release AHB peripheral reset.
Kojto	90:cb3d968589d8	581	* @{
Kojto	90:cb3d968589d8	582	*/
Kojto	90:cb3d968589d8	583	#define __AHB_FORCE_RESET() (RCC->AHBRSTR = 0xFFFFFFFF)
Kojto	90:cb3d968589d8	584	#define __GPIOA_FORCE_RESET() (RCC->AHBRSTR \|= (RCC_AHBRSTR_GPIOARST))
Kojto	90:cb3d968589d8	585	#define __GPIOB_FORCE_RESET() (RCC->AHBRSTR \|= (RCC_AHBRSTR_GPIOBRST))
Kojto	90:cb3d968589d8	586	#define __GPIOC_FORCE_RESET() (RCC->AHBRSTR \|= (RCC_AHBRSTR_GPIOCRST))
Kojto	90:cb3d968589d8	587	#define __GPIOD_FORCE_RESET() (RCC->AHBRSTR \|= (RCC_AHBRSTR_GPIODRST))
Kojto	90:cb3d968589d8	588	#define __GPIOF_FORCE_RESET() (RCC->AHBRSTR \|= (RCC_AHBRSTR_GPIOFRST))
Kojto	90:cb3d968589d8	589	#define __TSC_FORCE_RESET() (RCC->AHBRSTR \|= (RCC_AHBRSTR_TSCRST))
Kojto	90:cb3d968589d8	590
Kojto	90:cb3d968589d8	591	#define __AHB_RELEASE_RESET() (RCC->AHBRSTR = 0x00)
Kojto	90:cb3d968589d8	592	#define __GPIOA_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_GPIOARST))
Kojto	90:cb3d968589d8	593	#define __GPIOB_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_GPIOBRST))
Kojto	90:cb3d968589d8	594	#define __GPIOC_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_GPIOCRST))
Kojto	90:cb3d968589d8	595	#define __GPIOD_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_GPIODRST))
Kojto	90:cb3d968589d8	596	#define __GPIOF_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_GPIOFRST))
Kojto	90:cb3d968589d8	597	#define __TSC_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_TSCRST))
Kojto	90:cb3d968589d8	598	/**
Kojto	90:cb3d968589d8	599	* @}
Kojto	90:cb3d968589d8	600	*/
Kojto	90:cb3d968589d8	601
Kojto	90:cb3d968589d8	602	/** @defgroup RCC_APB1_Force_Release_Reset RCC APB1 Force Release Reset
Kojto	90:cb3d968589d8	603	* @brief Force or release APB1 peripheral reset.
Kojto	90:cb3d968589d8	604	* @{
Kojto	90:cb3d968589d8	605	*/
Kojto	90:cb3d968589d8	606	#define __APB1_FORCE_RESET() (RCC->APB1RSTR = 0xFFFFFFFF)
Kojto	90:cb3d968589d8	607	#define __TIM2_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM2RST))
Kojto	90:cb3d968589d8	608	#define __TIM6_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM6RST))
Kojto	90:cb3d968589d8	609	#define __WWDG_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_WWDGRST))
Kojto	90:cb3d968589d8	610	#define __USART2_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_USART2RST))
Kojto	90:cb3d968589d8	611	#define __USART3_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_USART3RST))
Kojto	90:cb3d968589d8	612	#define __I2C1_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_I2C1RST))
Kojto	90:cb3d968589d8	613	#define __PWR_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_PWRRST))
Kojto	90:cb3d968589d8	614	#define __DAC1_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_DAC1RST))
Kojto	90:cb3d968589d8	615
Kojto	90:cb3d968589d8	616	#define __APB1_RELEASE_RESET() (RCC->APB1RSTR = 0x00)
Kojto	90:cb3d968589d8	617	#define __TIM2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM2RST))
Kojto	90:cb3d968589d8	618	#define __TIM6_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM6RST))
Kojto	90:cb3d968589d8	619	#define __WWDG_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_WWDGRST))
Kojto	90:cb3d968589d8	620	#define __USART2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USART2RST))
Kojto	90:cb3d968589d8	621	#define __USART3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USART3RST))
Kojto	90:cb3d968589d8	622	#define __I2C1_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C1RST))
Kojto	90:cb3d968589d8	623	#define __PWR_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_PWRRST))
Kojto	90:cb3d968589d8	624	#define __DAC1_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_DAC1RST))
Kojto	90:cb3d968589d8	625	/**
Kojto	90:cb3d968589d8	626	* @}
Kojto	90:cb3d968589d8	627	*/
Kojto	90:cb3d968589d8	628
Kojto	90:cb3d968589d8	629	/** @defgroup RCC_APB2_Force_Release_Reset RCC APB2 Force Release Reset
Kojto	90:cb3d968589d8	630	* @brief Force or release APB2 peripheral reset.
Kojto	90:cb3d968589d8	631	* @{
Kojto	90:cb3d968589d8	632	*/
Kojto	90:cb3d968589d8	633	#define __APB2_FORCE_RESET() (RCC->APB2RSTR = 0xFFFFFFFF)
Kojto	90:cb3d968589d8	634	#define __SYSCFG_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_SYSCFGRST))
Kojto	90:cb3d968589d8	635	#define __TIM15_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_TIM15RST))
Kojto	90:cb3d968589d8	636	#define __TIM16_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_TIM16RST))
Kojto	90:cb3d968589d8	637	#define __TIM17_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_TIM17RST))
Kojto	90:cb3d968589d8	638	#define __USART1_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_USART1RST))
Kojto	90:cb3d968589d8	639
Kojto	90:cb3d968589d8	640	#define __APB2_RELEASE_RESET() (RCC->APB2RSTR = 0x00)
Kojto	90:cb3d968589d8	641	#define __SYSCFG_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SYSCFGRST))
Kojto	90:cb3d968589d8	642	#define __TIM15_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM15RST))
Kojto	90:cb3d968589d8	643	#define __TIM16_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM16RST))
Kojto	90:cb3d968589d8	644	#define __TIM17_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM17RST))
Kojto	90:cb3d968589d8	645	#define __USART1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_USART1RST))
Kojto	90:cb3d968589d8	646	/**
Kojto	90:cb3d968589d8	647	* @}
Kojto	90:cb3d968589d8	648	*/
Kojto	90:cb3d968589d8	649
Kojto	90:cb3d968589d8	650	/** @defgroup RCC_HSI_Configuration RCC HSI Configuration
Kojto	90:cb3d968589d8	651	* @{
Kojto	90:cb3d968589d8	652	*/
Kojto	90:cb3d968589d8	653
Kojto	90:cb3d968589d8	654	/** @brief Macros to enable or disable the Internal High Speed oscillator (HSI).
Kojto	90:cb3d968589d8	655	* @note The HSI is stopped by hardware when entering STOP and STANDBY modes.
Kojto	90:cb3d968589d8	656	* It is used (enabled by hardware) as system clock source after startup
Kojto	90:cb3d968589d8	657	* from Reset, wakeup from STOP and STANDBY mode, or in case of failure
Kojto	90:cb3d968589d8	658	* of the HSE used directly or indirectly as system clock (if the Clock
Kojto	90:cb3d968589d8	659	* Security System CSS is enabled).
Kojto	90:cb3d968589d8	660	* @note HSI can not be stopped if it is used as system clock source. In this case,
Kojto	90:cb3d968589d8	661	* you have to select another source of the system clock then stop the HSI.
Kojto	90:cb3d968589d8	662	* @note After enabling the HSI, the application software should wait on HSIRDY
Kojto	90:cb3d968589d8	663	* flag to be set indicating that HSI clock is stable and can be used as
Kojto	90:cb3d968589d8	664	* system clock source.
Kojto	90:cb3d968589d8	665	* @note When the HSI is stopped, HSIRDY flag goes low after 6 HSI oscillator
Kojto	90:cb3d968589d8	666	* clock cycles.
Kojto	90:cb3d968589d8	667	*/
Kojto	90:cb3d968589d8	668	#define __HAL_RCC_HSI_ENABLE() ((__IO uint32_t )CR_HSION_BB = ENABLE)
Kojto	90:cb3d968589d8	669	#define __HAL_RCC_HSI_DISABLE() ((__IO uint32_t )CR_HSION_BB = DISABLE)
Kojto	90:cb3d968589d8	670
Kojto	90:cb3d968589d8	671
Kojto	90:cb3d968589d8	672	/** @brief Macro to adjust the Internal High Speed oscillator (HSI) calibration value.
Kojto	90:cb3d968589d8	673	* @note The calibration is used to compensate for the variations in voltage
Kojto	90:cb3d968589d8	674	* and temperature that influence the frequency of the internal HSI RC.
Kojto	90:cb3d968589d8	675	* @param __HSICalibrationValue__: specifies the calibration trimming value.
Kojto	90:cb3d968589d8	676	* This parameter must be a number between 0 and 0x1F.
Kojto	90:cb3d968589d8	677	*/
Kojto	90:cb3d968589d8	678	#define __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(__HSICalibrationValue__) \
Kojto	90:cb3d968589d8	679	MODIFY_REG(RCC->CR, RCC_CR_HSITRIM, (uint32_t)(__HSICalibrationValue__) << POSITION_VAL(RCC_CR_HSITRIM))
Kojto	90:cb3d968589d8	680	/**
Kojto	90:cb3d968589d8	681	* @}
Kojto	90:cb3d968589d8	682	*/
Kojto	90:cb3d968589d8	683
Kojto	90:cb3d968589d8	684	/** @defgroup RCC_LSI_Configuration RCC LSI Configuration
Kojto	90:cb3d968589d8	685	* @{
Kojto	90:cb3d968589d8	686	*/
Kojto	90:cb3d968589d8	687
Kojto	90:cb3d968589d8	688	/** @brief Macro to enable or disable the Internal Low Speed oscillator (LSI).
Kojto	90:cb3d968589d8	689	* @note After enabling the LSI, the application software should wait on
Kojto	90:cb3d968589d8	690	* LSIRDY flag to be set indicating that LSI clock is stable and can
Kojto	90:cb3d968589d8	691	* be used to clock the IWDG and/or the RTC.
Kojto	90:cb3d968589d8	692	* @note LSI can not be disabled if the IWDG is running.
Kojto	90:cb3d968589d8	693	* @note When the LSI is stopped, LSIRDY flag goes low after 6 LSI oscillator
Kojto	90:cb3d968589d8	694	* clock cycles.
Kojto	90:cb3d968589d8	695	*/
Kojto	90:cb3d968589d8	696	#define __HAL_RCC_LSI_ENABLE() ((__IO uint32_t )CSR_LSION_BB = ENABLE)
Kojto	90:cb3d968589d8	697	#define __HAL_RCC_LSI_DISABLE() ((__IO uint32_t )CSR_LSION_BB = DISABLE)
Kojto	90:cb3d968589d8	698	/**
Kojto	90:cb3d968589d8	699	* @}
Kojto	90:cb3d968589d8	700	*/
Kojto	90:cb3d968589d8	701
Kojto	90:cb3d968589d8	702	/** @defgroup RCC_HSE_Configuration RCC HSE Configuration
Kojto	90:cb3d968589d8	703	* @{
Kojto	90:cb3d968589d8	704	*/
Kojto	90:cb3d968589d8	705
Kojto	90:cb3d968589d8	706	/**
Kojto	90:cb3d968589d8	707	* @brief Macro to configure the External High Speed oscillator (HSE).
Kojto	90:cb3d968589d8	708	* @note After enabling the HSE (RCC_HSE_ON or RCC_HSE_Bypass), the application
Kojto	90:cb3d968589d8	709	* software should wait on HSERDY flag to be set indicating that HSE clock
Kojto	90:cb3d968589d8	710	* is stable and can be used to clock the PLL and/or system clock.
Kojto	90:cb3d968589d8	711	* @note HSE state can not be changed if it is used directly or through the
Kojto	90:cb3d968589d8	712	* PLL as system clock. In this case, you have to select another source
Kojto	90:cb3d968589d8	713	* of the system clock then change the HSE state (ex. disable it).
Kojto	90:cb3d968589d8	714	* @note The HSE is stopped by hardware when entering STOP and STANDBY modes.
Kojto	90:cb3d968589d8	715	* @note This function reset the CSSON bit, so if the Clock security system(CSS)
Kojto	90:cb3d968589d8	716	* was previously enabled you have to enable it again after calling this
Kojto	90:cb3d968589d8	717	* function.
Kojto	90:cb3d968589d8	718	* @param __STATE__: specifies the new state of the HSE.
Kojto	90:cb3d968589d8	719	* This parameter can be one of the following values:
Kojto	90:cb3d968589d8	720	* @arg RCC_HSE_OFF: turn OFF the HSE oscillator, HSERDY flag goes low after
Kojto	90:cb3d968589d8	721	* 6 HSE oscillator clock cycles.
Kojto	90:cb3d968589d8	722	* @arg RCC_HSE_ON: turn ON the HSE oscillator
Kojto	90:cb3d968589d8	723	* @arg RCC_HSE_BYPASS: HSE oscillator bypassed with external clock
Kojto	90:cb3d968589d8	724	*/
Kojto	90:cb3d968589d8	725	#define __HAL_RCC_HSE_CONFIG(__STATE__) ((__IO uint8_t )CR_BYTE2_ADDRESS = (__STATE__))
Kojto	90:cb3d968589d8	726	/**
Kojto	90:cb3d968589d8	727	* @}
Kojto	90:cb3d968589d8	728	*/
Kojto	90:cb3d968589d8	729
Kojto	90:cb3d968589d8	730	/** @defgroup RCC_LSE_Configuration RCC LSE Configuration
Kojto	90:cb3d968589d8	731	* @{
Kojto	90:cb3d968589d8	732	*/
Kojto	90:cb3d968589d8	733	/**
Kojto	90:cb3d968589d8	734	* @brief Macro to configure the External Low Speed oscillator (LSE).
Kojto	90:cb3d968589d8	735	* @note As the LSE is in the Backup domain and write access is denied to
Kojto	90:cb3d968589d8	736	* this domain after reset, you have to enable write access using
Kojto	90:cb3d968589d8	737	* HAL_PWR_EnableBkUpAccess() function before to configure the LSE
Kojto	90:cb3d968589d8	738	* (to be done once after reset).
Kojto	90:cb3d968589d8	739	* @note After enabling the LSE (RCC_LSE_ON or RCC_LSE_BYPASS), the application
Kojto	90:cb3d968589d8	740	* software should wait on LSERDY flag to be set indicating that LSE clock
Kojto	90:cb3d968589d8	741	* is stable and can be used to clock the RTC.
Kojto	90:cb3d968589d8	742	* @param __STATE__: specifies the new state of the LSE.
Kojto	90:cb3d968589d8	743	* This parameter can be one of the following values:
Kojto	90:cb3d968589d8	744	* @arg RCC_LSE_OFF: turn OFF the LSE oscillator, LSERDY flag goes low after
Kojto	90:cb3d968589d8	745	* 6 LSE oscillator clock cycles.
Kojto	90:cb3d968589d8	746	* @arg RCC_LSE_ON: turn ON the LSE oscillator
Kojto	90:cb3d968589d8	747	* @arg RCC_LSE_BYPASS: LSE oscillator bypassed with external clock
Kojto	90:cb3d968589d8	748	*/
Kojto	90:cb3d968589d8	749	#define __HAL_RCC_LSE_CONFIG(__STATE__) \
Kojto	90:cb3d968589d8	750	MODIFY_REG(RCC->BDCR, RCC_BDCR_LSEON\|RCC_BDCR_LSEBYP, (uint32_t)(__STATE__))
Kojto	90:cb3d968589d8	751	/**
Kojto	90:cb3d968589d8	752	* @}
Kojto	90:cb3d968589d8	753	*/
Kojto	90:cb3d968589d8	754
Kojto	90:cb3d968589d8	755	/** @defgroup RCC_I2Cx_Clock_Config RCC I2Cx Clock Config
Kojto	90:cb3d968589d8	756	* @{
Kojto	90:cb3d968589d8	757	*/
Kojto	90:cb3d968589d8	758	/** @brief Macro to configure the I2C1 clock (I2C1CLK).
Kojto	90:cb3d968589d8	759	* @param __I2C1CLKSource__: specifies the I2C1 clock source.
Kojto	90:cb3d968589d8	760	* This parameter can be one of the following values:
Kojto	90:cb3d968589d8	761	* @arg RCC_I2C1CLKSOURCE_HSI: HSI selected as I2C1 clock
Kojto	90:cb3d968589d8	762	* @arg RCC_I2C1CLKSOURCE_SYSCLK: System Clock selected as I2C1 clock
Kojto	90:cb3d968589d8	763	*/
Kojto	90:cb3d968589d8	764	#define __HAL_RCC_I2C1_CONFIG(__I2C1CLKSource__) \
Kojto	90:cb3d968589d8	765	MODIFY_REG(RCC->CFGR3, RCC_CFGR3_I2C1SW, (uint32_t)(__I2C1CLKSource__))
Kojto	90:cb3d968589d8	766
Kojto	90:cb3d968589d8	767	/** @brief Macro to get the I2C1 clock source.
Kojto	90:cb3d968589d8	768	* @retval The clock source can be one of the following values:
Kojto	90:cb3d968589d8	769	* @arg RCC_I2C1CLKSOURCE_HSI: HSI selected as I2C1 clock
Kojto	90:cb3d968589d8	770	* @arg RCC_I2C1CLKSOURCE_SYSCLK: System Clock selected as I2C1 clock
Kojto	90:cb3d968589d8	771	*/
Kojto	90:cb3d968589d8	772	#define __HAL_RCC_GET_I2C1_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_I2C1SW)))
Kojto	90:cb3d968589d8	773	/**
Kojto	90:cb3d968589d8	774	* @}
Kojto	90:cb3d968589d8	775	*/
Kojto	90:cb3d968589d8	776
Kojto	90:cb3d968589d8	777	/** @defgroup RCC_USARTx_Clock_Config RCC USARTx Clock Config
Kojto	90:cb3d968589d8	778	* @{
Kojto	90:cb3d968589d8	779	*/
Kojto	90:cb3d968589d8	780
Kojto	90:cb3d968589d8	781	/** @brief Macro to configure the USART1 clock (USART1CLK).
Kojto	90:cb3d968589d8	782	* @param __USART1CLKSource__: specifies the USART1 clock source.
Kojto	90:cb3d968589d8	783	* This parameter can be one of the following values:
Kojto	90:cb3d968589d8	784	* @arg RCC_USART1CLKSOURCE_PCLK2 or RCC_USART1CLKSOURCE_PCLK1: PCLK2 or PCLK1 selected as USART1 clock
Kojto	90:cb3d968589d8	785	* @arg RCC_USART1CLKSOURCE_HSI: HSI selected as USART1 clock
Kojto	90:cb3d968589d8	786	* @arg RCC_USART1CLKSOURCE_SYSCLK: System Clock selected as USART1 clock
Kojto	90:cb3d968589d8	787	* @arg RCC_USART1CLKSOURCE_LSE: LSE selected as USART1 clock
Kojto	90:cb3d968589d8	788	*/
Kojto	90:cb3d968589d8	789	#define __HAL_RCC_USART1_CONFIG(__USART1CLKSource__) \
Kojto	90:cb3d968589d8	790	MODIFY_REG(RCC->CFGR3, RCC_CFGR3_USART1SW, (uint32_t)(__USART1CLKSource__))
Kojto	90:cb3d968589d8	791
Kojto	90:cb3d968589d8	792	/** @brief Macro to get the USART1 clock source.
Kojto	90:cb3d968589d8	793	* @retval The clock source can be one of the following values:
Kojto	90:cb3d968589d8	794	* @arg RCC_USART1CLKSOURCE_PCLK2 or RCC_USART1CLKSOURCE_PCLK1: PCLK2 or PCLK1 selected as USART1 clock
Kojto	90:cb3d968589d8	795	* @arg RCC_USART1CLKSOURCE_HSI: HSI selected as USART1 clock
Kojto	90:cb3d968589d8	796	* @arg RCC_USART1CLKSOURCE_SYSCLK: System Clock selected as USART1 clock
Kojto	90:cb3d968589d8	797	* @arg RCC_USART1CLKSOURCE_LSE: LSE selected as USART1 clock
Kojto	90:cb3d968589d8	798	*/
Kojto	90:cb3d968589d8	799	#define __HAL_RCC_GET_USART1_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_USART1SW)))
Kojto	90:cb3d968589d8	800
Kojto	90:cb3d968589d8	801	/** @brief Macro to configure the USART2 clock (USART2CLK).
Kojto	90:cb3d968589d8	802	* @param __USART2CLKSource__: specifies the USART2 clock source.
Kojto	90:cb3d968589d8	803	* This parameter can be one of the following values:
Kojto	90:cb3d968589d8	804	* @arg RCC_USART2CLKSOURCE_PCLK1: PCLK1 selected as USART2 clock
Kojto	90:cb3d968589d8	805	* @arg RCC_USART2CLKSOURCE_HSI: HSI selected as USART2 clock
Kojto	90:cb3d968589d8	806	* @arg RCC_USART2CLKSOURCE_SYSCLK: System Clock selected as USART2 clock
Kojto	90:cb3d968589d8	807	* @arg RCC_USART2CLKSOURCE_LSE: LSE selected as USART2 clock
Kojto	90:cb3d968589d8	808	*/
Kojto	90:cb3d968589d8	809	#define __HAL_RCC_USART2_CONFIG(__USART2CLKSource__) \
Kojto	90:cb3d968589d8	810	MODIFY_REG(RCC->CFGR3, RCC_CFGR3_USART2SW, (uint32_t)(__USART2CLKSource__))
Kojto	90:cb3d968589d8	811
Kojto	90:cb3d968589d8	812	/** @brief Macro to get the USART2 clock source.
Kojto	90:cb3d968589d8	813	* @retval The clock source can be one of the following values:
Kojto	90:cb3d968589d8	814	* @arg RCC_USART2CLKSOURCE_PCLK1: PCLK1 selected as USART2 clock
Kojto	90:cb3d968589d8	815	* @arg RCC_USART2CLKSOURCE_HSI: HSI selected as USART2 clock
Kojto	90:cb3d968589d8	816	* @arg RCC_USART2CLKSOURCE_SYSCLK: System Clock selected as USART2 clock
Kojto	90:cb3d968589d8	817	* @arg RCC_USART2CLKSOURCE_LSE: LSE selected as USART2 clock
Kojto	90:cb3d968589d8	818	*/
Kojto	90:cb3d968589d8	819	#define __HAL_RCC_GET_USART2_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_USART2SW)))
Kojto	90:cb3d968589d8	820
Kojto	90:cb3d968589d8	821	/** @brief Macro to configure the USART3 clock (USART3CLK).
Kojto	90:cb3d968589d8	822	* @param __USART3CLKSource__: specifies the USART3 clock source.
Kojto	90:cb3d968589d8	823	* This parameter can be one of the following values:
Kojto	90:cb3d968589d8	824	* @arg RCC_USART3CLKSOURCE_PCLK1: PCLK1 selected as USART3 clock
Kojto	90:cb3d968589d8	825	* @arg RCC_USART3CLKSOURCE_HSI: HSI selected as USART3 clock
Kojto	90:cb3d968589d8	826	* @arg RCC_USART3CLKSOURCE_SYSCLK: System Clock selected as USART3 clock
Kojto	90:cb3d968589d8	827	* @arg RCC_USART3CLKSOURCE_LSE: LSE selected as USART3 clock
Kojto	90:cb3d968589d8	828	*/
Kojto	90:cb3d968589d8	829	#define __HAL_RCC_USART3_CONFIG(__USART3CLKSource__) \
Kojto	90:cb3d968589d8	830	MODIFY_REG(RCC->CFGR3, RCC_CFGR3_USART3SW, (uint32_t)(__USART3CLKSource__))
Kojto	90:cb3d968589d8	831
Kojto	90:cb3d968589d8	832	/** @brief Macro to get the USART3 clock source.
Kojto	90:cb3d968589d8	833	* @retval The clock source can be one of the following values:
Kojto	90:cb3d968589d8	834	* @arg RCC_USART3CLKSOURCE_PCLK1: PCLK1 selected as USART3 clock
Kojto	90:cb3d968589d8	835	* @arg RCC_USART3CLKSOURCE_HSI: HSI selected as USART3 clock
Kojto	90:cb3d968589d8	836	* @arg RCC_USART3CLKSOURCE_SYSCLK: System Clock selected as USART3 clock
Kojto	90:cb3d968589d8	837	* @arg RCC_USART3CLKSOURCE_LSE: LSE selected as USART3 clock
Kojto	90:cb3d968589d8	838	*/
Kojto	90:cb3d968589d8	839	#define __HAL_RCC_GET_USART3_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_USART3SW)))
Kojto	90:cb3d968589d8	840	/**
Kojto	90:cb3d968589d8	841	* @}
Kojto	90:cb3d968589d8	842	*/
Kojto	90:cb3d968589d8	843
Kojto	90:cb3d968589d8	844	/** @defgroup RCC_RTC_Clock_Configuration RCC RTC Clock Configuration
Kojto	90:cb3d968589d8	845	* @{
Kojto	90:cb3d968589d8	846	*/
Kojto	90:cb3d968589d8	847	/** @brief Macros to enable or disable the the RTC clock.
Kojto	90:cb3d968589d8	848	* @note These macros must be used only after the RTC clock source was selected.
Kojto	90:cb3d968589d8	849	*/
Kojto	90:cb3d968589d8	850	#define __HAL_RCC_RTC_ENABLE() ((__IO uint32_t )BDCR_RTCEN_BB = ENABLE)
Kojto	90:cb3d968589d8	851	#define __HAL_RCC_RTC_DISABLE() ((__IO uint32_t )BDCR_RTCEN_BB = DISABLE)
Kojto	90:cb3d968589d8	852
Kojto	90:cb3d968589d8	853	/** @brief Macro to configure the RTC clock (RTCCLK).
Kojto	90:cb3d968589d8	854	* @note As the RTC clock configuration bits are in the Backup domain and write
Kojto	90:cb3d968589d8	855	* access is denied to this domain after reset, you have to enable write
Kojto	90:cb3d968589d8	856	* access using the Power Backup Access macro before to configure
Kojto	90:cb3d968589d8	857	* the RTC clock source (to be done once after reset).
Kojto	90:cb3d968589d8	858	* @note Once the RTC clock is configured it can't be changed unless the
Kojto	90:cb3d968589d8	859	* Backup domain is reset using __HAL_RCC_BackupReset_RELEASE() macro, or by
Kojto	90:cb3d968589d8	860	* a Power On Reset (POR).
Kojto	90:cb3d968589d8	861	* @param __RTCCLKSource__: specifies the RTC clock source.
Kojto	90:cb3d968589d8	862	* This parameter can be one of the following values:
Kojto	90:cb3d968589d8	863	* @arg RCC_RTCCLKSOURCE_NONE: No clock selected as RTC clock
Kojto	90:cb3d968589d8	864	* @arg RCC_RTCCLKSOURCE_LSE: LSE selected as RTC clock
Kojto	90:cb3d968589d8	865	* @arg RCC_RTCCLKSOURCE_LSI: LSI selected as RTC clock
Kojto	90:cb3d968589d8	866	* @arg RCC_RTCCLKSOURCE_HSE_DIV32: HSE clock divided by 32
Kojto	90:cb3d968589d8	867	*
Kojto	90:cb3d968589d8	868	* @note If the LSE is used as RTC clock source, the RTC continues to
Kojto	90:cb3d968589d8	869	* work in STOP and STANDBY modes, and can be used as wakeup source.
Kojto	90:cb3d968589d8	870	* However, when the LSI clock and HSE clock divided by 32 is used as RTC clock source,
Kojto	90:cb3d968589d8	871	* the RTC cannot be used in STOP and STANDBY modes.
Kojto	90:cb3d968589d8	872	* @note The system must always be configured so as to get a PCLK frequency greater than or
Kojto	90:cb3d968589d8	873	* equal to the RTCCLK frequency for a proper operation of the RTC.
Kojto	90:cb3d968589d8	874	*/
Kojto	90:cb3d968589d8	875	#define __HAL_RCC_RTC_CONFIG(__RTCCLKSource__) \
Kojto	90:cb3d968589d8	876	MODIFY_REG(RCC->BDCR, RCC_BDCR_RTCSEL, (uint32_t)(__RTCCLKSource__))
Kojto	90:cb3d968589d8	877
Kojto	90:cb3d968589d8	878	/** @brief Macro to get the RTC clock source.
Kojto	90:cb3d968589d8	879	* @retval The clock source can be one of the following values:
Kojto	90:cb3d968589d8	880	* @arg RCC_RTCCLKSOURCE_NONE: No clock selected as RTC clock
Kojto	90:cb3d968589d8	881	* @arg RCC_RTCCLKSOURCE_LSE: LSE selected as RTC clock
Kojto	90:cb3d968589d8	882	* @arg RCC_RTCCLKSOURCE_LSI: LSI selected as RTC clock
Kojto	90:cb3d968589d8	883	* @arg RCC_RTCCLKSOURCE_HSE_DIV32: HSE clock divided by 32 selected as RTC clock
Kojto	90:cb3d968589d8	884	*/
Kojto	90:cb3d968589d8	885	#define __HAL_RCC_GET_RTC_SOURCE() ((uint32_t)(READ_BIT(RCC->BDCR, RCC_BDCR_RTCSEL)))
Kojto	90:cb3d968589d8	886	/**
Kojto	90:cb3d968589d8	887	* @}
Kojto	90:cb3d968589d8	888	*/
Kojto	90:cb3d968589d8	889
Kojto	90:cb3d968589d8	890	/** @defgroup RCC_Force_Release_Backup RCC Force Release Backup
Kojto	90:cb3d968589d8	891	* @{
Kojto	90:cb3d968589d8	892	*/
Kojto	90:cb3d968589d8	893
Kojto	90:cb3d968589d8	894	/** @brief Macro to force or release the Backup domain reset.
Kojto	90:cb3d968589d8	895	* @note These macros reset the RTC peripheral (including the backup registers)
Kojto	90:cb3d968589d8	896	* and the RTC clock source selection in RCC_CSR register.
Kojto	90:cb3d968589d8	897	* @note The BKPSRAM is not affected by this reset.
Kojto	90:cb3d968589d8	898	*/
Kojto	90:cb3d968589d8	899	#define __HAL_RCC_BACKUPRESET_FORCE() ((__IO uint32_t )BDCR_BDRST_BB = ENABLE)
Kojto	90:cb3d968589d8	900	#define __HAL_RCC_BACKUPRESET_RELEASE() ((__IO uint32_t )BDCR_BDRST_BB = DISABLE)
Kojto	90:cb3d968589d8	901	/**
Kojto	90:cb3d968589d8	902	* @}
Kojto	90:cb3d968589d8	903	*/
Kojto	90:cb3d968589d8	904
Kojto	90:cb3d968589d8	905	/** @defgroup RCC_PLL_Configuration RCC PLL Configuration
Kojto	90:cb3d968589d8	906	* @{
Kojto	90:cb3d968589d8	907	*/
Kojto	90:cb3d968589d8	908
Kojto	90:cb3d968589d8	909	/** @brief Macro to enable or disable the PLL.
Kojto	90:cb3d968589d8	910	* @note After enabling the PLL, the application software should wait on
Kojto	90:cb3d968589d8	911	* PLLRDY flag to be set indicating that PLL clock is stable and can
Kojto	90:cb3d968589d8	912	* be used as system clock source.
Kojto	90:cb3d968589d8	913	* @note The PLL can not be disabled if it is used as system clock source
Kojto	90:cb3d968589d8	914	* @note The PLL is disabled by hardware when entering STOP and STANDBY modes.
Kojto	90:cb3d968589d8	915	*/
Kojto	90:cb3d968589d8	916	#define __HAL_RCC_PLL_ENABLE() ((__IO uint32_t )CR_PLLON_BB = ENABLE)
Kojto	90:cb3d968589d8	917	#define __HAL_RCC_PLL_DISABLE() ((__IO uint32_t )CR_PLLON_BB = DISABLE)
Kojto	90:cb3d968589d8	918	/**
Kojto	90:cb3d968589d8	919	* @}
Kojto	90:cb3d968589d8	920	*/
Kojto	90:cb3d968589d8	921
Kojto	90:cb3d968589d8	922	/** @defgroup RCC_Get_Clock_source RCC Get Clock source
Kojto	90:cb3d968589d8	923	* @{
Kojto	90:cb3d968589d8	924	*/
Kojto	90:cb3d968589d8	925
Kojto	90:cb3d968589d8	926	/** @brief Macro to get the clock source used as system clock.
Kojto	90:cb3d968589d8	927	* @retval The clock source used as system clock.
Kojto	90:cb3d968589d8	928	* The returned value can be one of the following value:
Kojto	90:cb3d968589d8	929	* @arg RCC_SYSCLKSOURCE_STATUS_HSI: HSI used as system clock
Kojto	90:cb3d968589d8	930	* @arg RCC_SYSCLKSOURCE_STATUS_HSE: HSE used as system clock
Kojto	90:cb3d968589d8	931	* @arg RCC_SYSCLKSOURCE_STATUS_PLLCLK: PLL used as system clock
Kojto	90:cb3d968589d8	932	*/
Kojto	90:cb3d968589d8	933	#define __HAL_RCC_GET_SYSCLK_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_SWS)))
Kojto	90:cb3d968589d8	934
Kojto	90:cb3d968589d8	935	/** @brief Macro to get the oscillator used as PLL clock source.
Kojto	90:cb3d968589d8	936	* @retval The oscillator used as PLL clock source. The returned value can be one
Kojto	90:cb3d968589d8	937	* of the following:
Kojto	90:cb3d968589d8	938	* - RCC_PLLSOURCE_HSI: HSI oscillator is used as PLL clock source.
Kojto	90:cb3d968589d8	939	* - RCC_PLLSOURCE_HSE: HSE oscillator is used as PLL clock source.
Kojto	90:cb3d968589d8	940	*/
Kojto	90:cb3d968589d8	941	#define __HAL_RCC_GET_PLL_OSCSOURCE() ((uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_PLLSRC)))
Kojto	90:cb3d968589d8	942	/**
Kojto	90:cb3d968589d8	943	* @}
Kojto	90:cb3d968589d8	944	*/
Kojto	90:cb3d968589d8	945
Kojto	90:cb3d968589d8	946	/** @defgroup RCC_Flags_Interrupts_Management RCC Flags Interrupts Management
Kojto	90:cb3d968589d8	947	* @brief macros to manage the specified RCC Flags and interrupts.
Kojto	90:cb3d968589d8	948	* @{
Kojto	90:cb3d968589d8	949	*/
Kojto	90:cb3d968589d8	950
Kojto	90:cb3d968589d8	951	/** @brief Enable RCC interrupt (Perform Byte access to RCC_CIR[12:8] bits to enable
Kojto	90:cb3d968589d8	952	* the selected interrupts.).
Kojto	90:cb3d968589d8	953	* @param __INTERRUPT__: specifies the RCC interrupt sources to be enabled.
Kojto	90:cb3d968589d8	954	* This parameter can be any combination of the following values:
Kojto	90:cb3d968589d8	955	* @arg RCC_IT_LSIRDY: LSI ready interrupt enable
Kojto	90:cb3d968589d8	956	* @arg RCC_IT_LSERDY: LSE ready interrupt enable
Kojto	90:cb3d968589d8	957	* @arg RCC_IT_HSIRDY: HSI ready interrupt enable
Kojto	90:cb3d968589d8	958	* @arg RCC_IT_HSERDY: HSE ready interrupt enable
Kojto	90:cb3d968589d8	959	* @arg RCC_IT_PLLRDY: PLL ready interrupt enable
Kojto	90:cb3d968589d8	960	*/
Kojto	90:cb3d968589d8	961	#define __HAL_RCC_ENABLE_IT(__INTERRUPT__) ((__IO uint8_t )CIR_BYTE1_ADDRESS \|= (__INTERRUPT__))
Kojto	90:cb3d968589d8	962
Kojto	90:cb3d968589d8	963	/** @brief Disable RCC interrupt (Perform Byte access to RCC_CIR[12:8] bits to disable
Kojto	90:cb3d968589d8	964	* the selected interrupts.).
Kojto	90:cb3d968589d8	965	* @param __INTERRUPT__: specifies the RCC interrupt sources to be disabled.
Kojto	90:cb3d968589d8	966	* This parameter can be any combination of the following values:
Kojto	90:cb3d968589d8	967	* @arg RCC_IT_LSIRDYIE: LSI ready interrupt enable
Kojto	90:cb3d968589d8	968	* @arg RCC_IT_LSERDYIE: LSE ready interrupt enable
Kojto	90:cb3d968589d8	969	* @arg RCC_IT_HSIRDYIE: HSI ready interrupt enable
Kojto	90:cb3d968589d8	970	* @arg RCC_IT_HSERDYIE: HSE ready interrupt enable
Kojto	90:cb3d968589d8	971	* @arg RCC_IT_PLLRDYIE: PLL ready interrupt enable
Kojto	90:cb3d968589d8	972	*/
Kojto	90:cb3d968589d8	973	#define __HAL_RCC_DISABLE_IT(__INTERRUPT__) ((__IO uint8_t )CIR_BYTE1_ADDRESS &= ~(__INTERRUPT__))
Kojto	90:cb3d968589d8	974
Kojto	90:cb3d968589d8	975	/** @brief Clear the RCC's interrupt pending bits ( Perform Byte access to RCC_CIR[23:16]
Kojto	90:cb3d968589d8	976	* bits to clear the selected interrupt pending bits.
Kojto	90:cb3d968589d8	977	* @param __IT__: specifies the interrupt pending bit to clear.
Kojto	90:cb3d968589d8	978	* This parameter can be any combination of the following values:
Kojto	90:cb3d968589d8	979	* @arg RCC_IT_LSIRDYC: LSI ready interrupt clear
Kojto	90:cb3d968589d8	980	* @arg RCC_IT_LSERDYC: LSE ready interrupt clear
Kojto	90:cb3d968589d8	981	* @arg RCC_IT_HSIRDYC: HSI ready interrupt clear
Kojto	90:cb3d968589d8	982	* @arg RCC_IT_HSERDYC: HSE ready interrupt clear
Kojto	90:cb3d968589d8	983	* @arg RCC_IT_PLLRDYC: PLL ready interrupt clear
Kojto	90:cb3d968589d8	984	* @arg RCC_IT_CSSC: Clock Security System interrupt clear
Kojto	90:cb3d968589d8	985	*/
Kojto	90:cb3d968589d8	986	#define __HAL_RCC_CLEAR_IT(__IT__) ((__IO uint8_t )CIR_BYTE2_ADDRESS = (__IT__))
Kojto	90:cb3d968589d8	987
Kojto	90:cb3d968589d8	988	/** @brief Check the RCC's interrupt has occurred or not.
Kojto	90:cb3d968589d8	989	* @param __IT__: specifies the RCC interrupt source to check.
Kojto	90:cb3d968589d8	990	* This parameter can be one of the following values:
Kojto	90:cb3d968589d8	991	* @arg RCC_IT_LSIRDYF: LSI ready interrupt flag
Kojto	90:cb3d968589d8	992	* @arg RCC_IT_LSERDYF: LSE ready interrupt flag
Kojto	90:cb3d968589d8	993	* @arg RCC_IT_HSIRDYF: HSI ready interrupt flag
Kojto	90:cb3d968589d8	994	* @arg RCC_IT_HSERDYF: HSE ready interrupt flag
Kojto	90:cb3d968589d8	995	* @arg RCC_IT_PLLRDYF: PLL ready interrupt flag
Kojto	90:cb3d968589d8	996	* @arg RCC_IT_CSSF: Clock Security System interrupt flag
Kojto	90:cb3d968589d8	997	* @retval The new state of __IT__ (TRUE or FALSE).
Kojto	90:cb3d968589d8	998	*/
Kojto	90:cb3d968589d8	999	#define __HAL_RCC_GET_IT(__IT__) ((RCC->CIR & (__IT__)) == (__IT__))
Kojto	90:cb3d968589d8	1000
Kojto	90:cb3d968589d8	1001	/** @brief Set RMVF bit to clear the reset flags: RCC_FLAG_OBLRST, RCC_FLAG_PINRST, RCC_FLAG_PORRST, RCC_FLAG_SFTRST,
Kojto	90:cb3d968589d8	1002	* RCC_FLAG_IWDGRST, RCC_FLAG_WWDGRST, RCC_FLAG_LPWRRST
Kojto	90:cb3d968589d8	1003	*/
Kojto	90:cb3d968589d8	1004	#define __HAL_RCC_CLEAR_RESET_FLAGS() ((__IO uint32_t )CSR_RMVF_BB = ENABLE)
Kojto	90:cb3d968589d8	1005
Kojto	90:cb3d968589d8	1006	/** @brief Check RCC flag is set or not.
Kojto	90:cb3d968589d8	1007	* @param __FLAG__: specifies the flag to check.
Kojto	90:cb3d968589d8	1008	* This parameter can be one of the following values:
Kojto	90:cb3d968589d8	1009	* @arg RCC_FLAG_HSIRDY: HSI oscillator clock ready
Kojto	90:cb3d968589d8	1010	* @arg RCC_FLAG_HSERDY: HSE oscillator clock ready
Kojto	90:cb3d968589d8	1011	* @arg RCC_FLAG_PLLRDY: PLL clock ready
Kojto	90:cb3d968589d8	1012	* @arg RCC_FLAG_LSERDY: LSE oscillator clock ready
Kojto	90:cb3d968589d8	1013	* @arg RCC_FLAG_LSIRDY: LSI oscillator clock ready
Kojto	90:cb3d968589d8	1014	* @arg RCC_FLAG_OBLRST: Option Byte Load reset
Kojto	90:cb3d968589d8	1015	* @arg RCC_FLAG_PINRST: Pin reset
Kojto	90:cb3d968589d8	1016	* @arg RCC_FLAG_PORRST: POR/PDR reset
Kojto	90:cb3d968589d8	1017	* @arg RCC_FLAG_SFTRST: Software reset
Kojto	90:cb3d968589d8	1018	* @arg RCC_FLAG_IWDGRST: Independent Watchdog reset
Kojto	90:cb3d968589d8	1019	* @arg RCC_FLAG_WWDGRST: Window Watchdog reset
Kojto	90:cb3d968589d8	1020	* @arg RCC_FLAG_LPWRRST: Low Power reset
Kojto	90:cb3d968589d8	1021	* @retval The new state of __FLAG__ (TRUE or FALSE).
Kojto	90:cb3d968589d8	1022	*/
Kojto	90:cb3d968589d8	1023	#define RCC_FLAG_MASK ((uint32_t)0x0000001F)
Kojto	90:cb3d968589d8	1024	#define __HAL_RCC_GET_FLAG(__FLAG__) (((((__FLAG__) >> 5U) == CR_REG_INDEX)? RCC->CR : \
Kojto	90:cb3d968589d8	1025	((((__FLAG__) >> 5U) == BDCR_REG_INDEX) ? RCC->BDCR : \
Kojto	90:cb3d968589d8	1026	RCC->CSR)) & (1U << ((__FLAG__) & RCC_FLAG_MASK)))
Kojto	90:cb3d968589d8	1027
Kojto	90:cb3d968589d8	1028
Kojto	90:cb3d968589d8	1029	/**
Kojto	90:cb3d968589d8	1030	* @}
Kojto	90:cb3d968589d8	1031	*/
Kojto	90:cb3d968589d8	1032
Kojto	90:cb3d968589d8	1033	/**
Kojto	90:cb3d968589d8	1034	* @}
Kojto	90:cb3d968589d8	1035	*/
Kojto	90:cb3d968589d8	1036
Kojto	90:cb3d968589d8	1037	/* Include RCC HAL Extended module */
Kojto	90:cb3d968589d8	1038	#include "stm32f3xx_hal_rcc_ex.h"
Kojto	90:cb3d968589d8	1039
Kojto	90:cb3d968589d8	1040	/* Exported functions --------------------------------------------------------*/
Kojto	90:cb3d968589d8	1041
Kojto	90:cb3d968589d8	1042	/** @addtogroup RCC_Exported_Functions
Kojto	90:cb3d968589d8	1043	* @{
Kojto	90:cb3d968589d8	1044	*/
Kojto	90:cb3d968589d8	1045
Kojto	90:cb3d968589d8	1046	/** @addtogroup RCC_Exported_Functions_Group1 Initialization and de-initialization functions
Kojto	90:cb3d968589d8	1047	* @{
Kojto	90:cb3d968589d8	1048	*/
Kojto	90:cb3d968589d8	1049
Kojto	90:cb3d968589d8	1050	/* Initialization and de-initialization functions ***************************/
Kojto	90:cb3d968589d8	1051	void HAL_RCC_DeInit(void);
Kojto	90:cb3d968589d8	1052	HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct);
Kojto	90:cb3d968589d8	1053	HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency);
Kojto	90:cb3d968589d8	1054
Kojto	90:cb3d968589d8	1055	/**
Kojto	90:cb3d968589d8	1056	* @}
Kojto	90:cb3d968589d8	1057	*/
Kojto	90:cb3d968589d8	1058
Kojto	90:cb3d968589d8	1059	/** @addtogroup RCC_Exported_Functions_Group2 Peripheral Control functions
Kojto	90:cb3d968589d8	1060	* @{
Kojto	90:cb3d968589d8	1061	*/
Kojto	90:cb3d968589d8	1062
Kojto	90:cb3d968589d8	1063	/* Peripheral Control functions *********************************************/
Kojto	90:cb3d968589d8	1064	void HAL_RCC_MCOConfig(uint32_t RCC_MCOx, uint32_t RCC_MCOSource, uint32_t RCC_MCODiv);
Kojto	90:cb3d968589d8	1065	void HAL_RCC_EnableCSS(void);
Kojto	90:cb3d968589d8	1066	void HAL_RCC_DisableCSS(void);
Kojto	90:cb3d968589d8	1067	uint32_t HAL_RCC_GetSysClockFreq(void);
Kojto	90:cb3d968589d8	1068	uint32_t HAL_RCC_GetHCLKFreq(void);
Kojto	90:cb3d968589d8	1069	uint32_t HAL_RCC_GetPCLK1Freq(void);
Kojto	90:cb3d968589d8	1070	uint32_t HAL_RCC_GetPCLK2Freq(void);
Kojto	90:cb3d968589d8	1071	void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct);
Kojto	90:cb3d968589d8	1072	void HAL_RCC_GetClockConfig(RCC_ClkInitTypeDef RCC_ClkInitStruct, uint32_t pFLatency);
Kojto	90:cb3d968589d8	1073
Kojto	90:cb3d968589d8	1074	/* CSS NMI IRQ handler */
Kojto	90:cb3d968589d8	1075	void HAL_RCC_NMI_IRQHandler(void);
Kojto	90:cb3d968589d8	1076
Kojto	90:cb3d968589d8	1077	/* User Callbacks in non blocking mode (IT mode) */
Kojto	90:cb3d968589d8	1078	void HAL_RCC_CCSCallback(void);
Kojto	90:cb3d968589d8	1079
Kojto	90:cb3d968589d8	1080	/**
Kojto	90:cb3d968589d8	1081	* @}
Kojto	90:cb3d968589d8	1082	*/
Kojto	90:cb3d968589d8	1083
Kojto	90:cb3d968589d8	1084	/**
Kojto	90:cb3d968589d8	1085	* @}
Kojto	90:cb3d968589d8	1086	*/
Kojto	90:cb3d968589d8	1087
Kojto	90:cb3d968589d8	1088	/**
Kojto	90:cb3d968589d8	1089	* @}
Kojto	90:cb3d968589d8	1090	*/
Kojto	90:cb3d968589d8	1091
Kojto	90:cb3d968589d8	1092	/**
Kojto	90:cb3d968589d8	1093	* @}
Kojto	90:cb3d968589d8	1094	*/
Kojto	90:cb3d968589d8	1095
Kojto	90:cb3d968589d8	1096	#ifdef __cplusplus
Kojto	90:cb3d968589d8	1097	}
Kojto	90:cb3d968589d8	1098	#endif
Kojto	90:cb3d968589d8	1099
Kojto	90:cb3d968589d8	1100	#endif /* __STM32F3xx_HAL_RCC_H */
Kojto	90:cb3d968589d8	1101
Kojto	90:cb3d968589d8	1102	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/

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Type:	Library
Created:	31 Mar 2015
Imports:	13
Forks:	0
Commits:	99
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TARGET_NUCLEO_F302R8/stm32f3xx_hal_rcc.h@90:cb3d968589d8, 2014-10-28 (annotated)

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