雄介 太田
mbed(SerialHalfDuplex入り)
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LPC11U24/LPC11Uxx.h@40:976df7c37ad5, 2012-06-12 (annotated)
- Committer:
- emilmont
- Date:
- Tue Jun 12 18:23:44 2012 +0100
- Revision:
- 40:976df7c37ad5
- Child:
- 44:24d45a770a51
First build for the new build system
Who changed what in which revision?
| User | Revision | Line number | New contents of line |
|---|---|---|---|
| emilmont | 40:976df7c37ad5 | 1 | |
| emilmont | 40:976df7c37ad5 | 2 | /****************************************************************************************************//** |
| emilmont | 40:976df7c37ad5 | 3 | * @file LPC11Uxx.h |
| emilmont | 40:976df7c37ad5 | 4 | * |
| emilmont | 40:976df7c37ad5 | 5 | * |
| emilmont | 40:976df7c37ad5 | 6 | * @brief CMSIS Cortex-M0 Core Peripheral Access Layer Header File for |
| emilmont | 40:976df7c37ad5 | 7 | * default LPC11Uxx Device Series |
| emilmont | 40:976df7c37ad5 | 8 | * |
| emilmont | 40:976df7c37ad5 | 9 | * @version V0.1 |
| emilmont | 40:976df7c37ad5 | 10 | * @date 21. March 2011 |
| emilmont | 40:976df7c37ad5 | 11 | * |
| emilmont | 40:976df7c37ad5 | 12 | * @note Generated with SFDGen V2.6 Build 3j (beta) on Thursday, 17.03.2011 13:19:45 |
| emilmont | 40:976df7c37ad5 | 13 | * |
| emilmont | 40:976df7c37ad5 | 14 | * from CMSIS SVD File 'LPC11U1x_svd.xml' Version 0.1, |
| emilmont | 40:976df7c37ad5 | 15 | * created on Wednesday, 16.03.2011 20:30:42, last modified on Thursday, 17.03.2011 20:19:40 |
| emilmont | 40:976df7c37ad5 | 16 | * |
| emilmont | 40:976df7c37ad5 | 17 | *******************************************************************************************************/ |
| emilmont | 40:976df7c37ad5 | 18 | |
| emilmont | 40:976df7c37ad5 | 19 | // ################################################################################ |
| emilmont | 40:976df7c37ad5 | 20 | // Minor fix 8 April 2011 - changed LPC_CT32B1_BASE from 0x40014000 to 0x40018000 |
| emilmont | 40:976df7c37ad5 | 21 | // ################################################################################ |
| emilmont | 40:976df7c37ad5 | 22 | |
| emilmont | 40:976df7c37ad5 | 23 | /** @addtogroup NXP |
| emilmont | 40:976df7c37ad5 | 24 | * @{ |
| emilmont | 40:976df7c37ad5 | 25 | */ |
| emilmont | 40:976df7c37ad5 | 26 | |
| emilmont | 40:976df7c37ad5 | 27 | /** @addtogroup LPC11Uxx |
| emilmont | 40:976df7c37ad5 | 28 | * @{ |
| emilmont | 40:976df7c37ad5 | 29 | */ |
| emilmont | 40:976df7c37ad5 | 30 | |
| emilmont | 40:976df7c37ad5 | 31 | #ifndef __LPC11UXX_H__ |
| emilmont | 40:976df7c37ad5 | 32 | #define __LPC11UXX_H__ |
| emilmont | 40:976df7c37ad5 | 33 | |
| emilmont | 40:976df7c37ad5 | 34 | #ifdef __cplusplus |
| emilmont | 40:976df7c37ad5 | 35 | extern "C" { |
| emilmont | 40:976df7c37ad5 | 36 | #endif |
| emilmont | 40:976df7c37ad5 | 37 | |
| emilmont | 40:976df7c37ad5 | 38 | |
| emilmont | 40:976df7c37ad5 | 39 | #if defined ( __CC_ARM ) |
| emilmont | 40:976df7c37ad5 | 40 | #pragma anon_unions |
| emilmont | 40:976df7c37ad5 | 41 | #endif |
| emilmont | 40:976df7c37ad5 | 42 | |
| emilmont | 40:976df7c37ad5 | 43 | /* Interrupt Number Definition */ |
| emilmont | 40:976df7c37ad5 | 44 | |
| emilmont | 40:976df7c37ad5 | 45 | typedef enum { |
| emilmont | 40:976df7c37ad5 | 46 | // ------------------------- Cortex-M0 Processor Exceptions Numbers ----------------------------- |
| emilmont | 40:976df7c37ad5 | 47 | Reset_IRQn = -15, /*!< 1 Reset Vector, invoked on Power up and warm reset */ |
| emilmont | 40:976df7c37ad5 | 48 | NonMaskableInt_IRQn = -14, /*!< 2 Non maskable Interrupt, cannot be stopped or preempted */ |
| emilmont | 40:976df7c37ad5 | 49 | HardFault_IRQn = -13, /*!< 3 Hard Fault, all classes of Fault */ |
| emilmont | 40:976df7c37ad5 | 50 | SVCall_IRQn = -5, /*!< 11 System Service Call via SVC instruction */ |
| emilmont | 40:976df7c37ad5 | 51 | DebugMonitor_IRQn = -4, /*!< 12 Debug Monitor */ |
| emilmont | 40:976df7c37ad5 | 52 | PendSV_IRQn = -2, /*!< 14 Pendable request for system service */ |
| emilmont | 40:976df7c37ad5 | 53 | SysTick_IRQn = -1, /*!< 15 System Tick Timer */ |
| emilmont | 40:976df7c37ad5 | 54 | // --------------------------- LPC11Uxx Specific Interrupt Numbers ------------------------------ |
| emilmont | 40:976df7c37ad5 | 55 | FLEX_INT0_IRQn = 0, /*!< All I/O pins can be routed to below 8 interrupts. */ |
| emilmont | 40:976df7c37ad5 | 56 | FLEX_INT1_IRQn = 1, |
| emilmont | 40:976df7c37ad5 | 57 | FLEX_INT2_IRQn = 2, |
| emilmont | 40:976df7c37ad5 | 58 | FLEX_INT3_IRQn = 3, |
| emilmont | 40:976df7c37ad5 | 59 | FLEX_INT4_IRQn = 4, |
| emilmont | 40:976df7c37ad5 | 60 | FLEX_INT5_IRQn = 5, |
| emilmont | 40:976df7c37ad5 | 61 | FLEX_INT6_IRQn = 6, |
| emilmont | 40:976df7c37ad5 | 62 | FLEX_INT7_IRQn = 7, |
| emilmont | 40:976df7c37ad5 | 63 | GINT0_IRQn = 8, /*!< Grouped Interrupt 0 */ |
| emilmont | 40:976df7c37ad5 | 64 | GINT1_IRQn = 9, /*!< Grouped Interrupt 1 */ |
| emilmont | 40:976df7c37ad5 | 65 | Reserved0_IRQn = 10, /*!< Reserved Interrupt */ |
| emilmont | 40:976df7c37ad5 | 66 | Reserved1_IRQn = 11, |
| emilmont | 40:976df7c37ad5 | 67 | Reserved2_IRQn = 12, |
| emilmont | 40:976df7c37ad5 | 68 | Reserved3_IRQn = 13, |
| emilmont | 40:976df7c37ad5 | 69 | SSP1_IRQn = 14, /*!< SSP1 Interrupt */ |
| emilmont | 40:976df7c37ad5 | 70 | I2C_IRQn = 15, /*!< I2C Interrupt */ |
| emilmont | 40:976df7c37ad5 | 71 | TIMER_16_0_IRQn = 16, /*!< 16-bit Timer0 Interrupt */ |
| emilmont | 40:976df7c37ad5 | 72 | TIMER_16_1_IRQn = 17, /*!< 16-bit Timer1 Interrupt */ |
| emilmont | 40:976df7c37ad5 | 73 | TIMER_32_0_IRQn = 18, /*!< 32-bit Timer0 Interrupt */ |
| emilmont | 40:976df7c37ad5 | 74 | TIMER_32_1_IRQn = 19, /*!< 32-bit Timer1 Interrupt */ |
| emilmont | 40:976df7c37ad5 | 75 | SSP0_IRQn = 20, /*!< SSP0 Interrupt */ |
| emilmont | 40:976df7c37ad5 | 76 | UART_IRQn = 21, /*!< UART Interrupt */ |
| emilmont | 40:976df7c37ad5 | 77 | USB_IRQn = 22, /*!< USB IRQ Interrupt */ |
| emilmont | 40:976df7c37ad5 | 78 | USB_FIQn = 23, /*!< USB FIQ Interrupt */ |
| emilmont | 40:976df7c37ad5 | 79 | ADC_IRQn = 24, /*!< A/D Converter Interrupt */ |
| emilmont | 40:976df7c37ad5 | 80 | WDT_IRQn = 25, /*!< Watchdog timer Interrupt */ |
| emilmont | 40:976df7c37ad5 | 81 | BOD_IRQn = 26, /*!< Brown Out Detect(BOD) Interrupt */ |
| emilmont | 40:976df7c37ad5 | 82 | FMC_IRQn = 27, /*!< Flash Memory Controller Interrupt */ |
| emilmont | 40:976df7c37ad5 | 83 | Reserved4_IRQn = 28, /*!< Reserved Interrupt */ |
| emilmont | 40:976df7c37ad5 | 84 | Reserved5_IRQn = 29, /*!< Reserved Interrupt */ |
| emilmont | 40:976df7c37ad5 | 85 | USBWakeup_IRQn = 30, /*!< USB wakeup Interrupt */ |
| emilmont | 40:976df7c37ad5 | 86 | Reserved6_IRQn = 31, /*!< Reserved Interrupt */ |
| emilmont | 40:976df7c37ad5 | 87 | } IRQn_Type; |
| emilmont | 40:976df7c37ad5 | 88 | |
| emilmont | 40:976df7c37ad5 | 89 | |
| emilmont | 40:976df7c37ad5 | 90 | /** @addtogroup Configuration_of_CMSIS |
| emilmont | 40:976df7c37ad5 | 91 | * @{ |
| emilmont | 40:976df7c37ad5 | 92 | */ |
| emilmont | 40:976df7c37ad5 | 93 | |
| emilmont | 40:976df7c37ad5 | 94 | /* Processor and Core Peripheral Section */ /* Configuration of the Cortex-M0 Processor and Core Peripherals */ |
| emilmont | 40:976df7c37ad5 | 95 | |
| emilmont | 40:976df7c37ad5 | 96 | #define __MPU_PRESENT 0 /*!< MPU present or not */ |
| emilmont | 40:976df7c37ad5 | 97 | #define __NVIC_PRIO_BITS 3 /*!< Number of Bits used for Priority Levels */ |
| emilmont | 40:976df7c37ad5 | 98 | #define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ |
| emilmont | 40:976df7c37ad5 | 99 | /** @} */ /* End of group Configuration_of_CMSIS */ |
| emilmont | 40:976df7c37ad5 | 100 | |
| emilmont | 40:976df7c37ad5 | 101 | #include "core_cm0.h" /*!< Cortex-M0 processor and core peripherals */ |
| emilmont | 40:976df7c37ad5 | 102 | #include "system_LPC11Uxx.h" /*!< LPC11Uxx System */ |
| emilmont | 40:976df7c37ad5 | 103 | |
| emilmont | 40:976df7c37ad5 | 104 | /** @addtogroup Device_Peripheral_Registers |
| emilmont | 40:976df7c37ad5 | 105 | * @{ |
| emilmont | 40:976df7c37ad5 | 106 | */ |
| emilmont | 40:976df7c37ad5 | 107 | |
| emilmont | 40:976df7c37ad5 | 108 | |
| emilmont | 40:976df7c37ad5 | 109 | // ------------------------------------------------------------------------------------------------ |
| emilmont | 40:976df7c37ad5 | 110 | // ----- I2C ----- |
| emilmont | 40:976df7c37ad5 | 111 | // ------------------------------------------------------------------------------------------------ |
| emilmont | 40:976df7c37ad5 | 112 | |
| emilmont | 40:976df7c37ad5 | 113 | |
| emilmont | 40:976df7c37ad5 | 114 | /** |
| emilmont | 40:976df7c37ad5 | 115 | * @brief Product name title=UM10462 Chapter title=LPC11U1x I2C-bus controller Modification date=3/16/2011 Major revision=0 Minor revision=3 (I2C) |
| emilmont | 40:976df7c37ad5 | 116 | */ |
| emilmont | 40:976df7c37ad5 | 117 | |
| emilmont | 40:976df7c37ad5 | 118 | typedef struct { /*!< (@ 0x40000000) I2C Structure */ |
| emilmont | 40:976df7c37ad5 | 119 | __IO uint32_t CONSET; /*!< (@ 0x40000000) I2C Control Set Register */ |
| emilmont | 40:976df7c37ad5 | 120 | __I uint32_t STAT; /*!< (@ 0x40000004) I2C Status Register */ |
| emilmont | 40:976df7c37ad5 | 121 | __IO uint32_t DAT; /*!< (@ 0x40000008) I2C Data Register. */ |
| emilmont | 40:976df7c37ad5 | 122 | __IO uint32_t ADR0; /*!< (@ 0x4000000C) I2C Slave Address Register 0 */ |
| emilmont | 40:976df7c37ad5 | 123 | __IO uint32_t SCLH; /*!< (@ 0x40000010) SCH Duty Cycle Register High Half Word */ |
| emilmont | 40:976df7c37ad5 | 124 | __IO uint32_t SCLL; /*!< (@ 0x40000014) SCL Duty Cycle Register Low Half Word */ |
| emilmont | 40:976df7c37ad5 | 125 | __IO uint32_t CONCLR; /*!< (@ 0x40000018) I2C Control Clear Register*/ |
| emilmont | 40:976df7c37ad5 | 126 | __IO uint32_t MMCTRL; /*!< (@ 0x4000001C) Monitor mode control register*/ |
| emilmont | 40:976df7c37ad5 | 127 | __IO uint32_t ADR1; /*!< (@ 0x40000020) I2C Slave Address Register 1*/ |
| emilmont | 40:976df7c37ad5 | 128 | __IO uint32_t ADR2; /*!< (@ 0x40000024) I2C Slave Address Register 2*/ |
| emilmont | 40:976df7c37ad5 | 129 | __IO uint32_t ADR3; /*!< (@ 0x40000028) I2C Slave Address Register 3*/ |
| emilmont | 40:976df7c37ad5 | 130 | __I uint32_t DATA_BUFFER; /*!< (@ 0x4000002C) Data buffer register */ |
| emilmont | 40:976df7c37ad5 | 131 | union{ |
| emilmont | 40:976df7c37ad5 | 132 | __IO uint32_t MASK[4]; /*!< (@ 0x40000030) I2C Slave address mask register */ |
| emilmont | 40:976df7c37ad5 | 133 | struct{ |
| emilmont | 40:976df7c37ad5 | 134 | __IO uint32_t MASK0; |
| emilmont | 40:976df7c37ad5 | 135 | __IO uint32_t MASK1; |
| emilmont | 40:976df7c37ad5 | 136 | __IO uint32_t MASK2; |
| emilmont | 40:976df7c37ad5 | 137 | __IO uint32_t MASK3; |
| emilmont | 40:976df7c37ad5 | 138 | }; |
| emilmont | 40:976df7c37ad5 | 139 | }; |
| emilmont | 40:976df7c37ad5 | 140 | } LPC_I2C_Type; |
| emilmont | 40:976df7c37ad5 | 141 | |
| emilmont | 40:976df7c37ad5 | 142 | |
| emilmont | 40:976df7c37ad5 | 143 | // ------------------------------------------------------------------------------------------------ |
| emilmont | 40:976df7c37ad5 | 144 | // ----- WWDT ----- |
| emilmont | 40:976df7c37ad5 | 145 | // ------------------------------------------------------------------------------------------------ |
| emilmont | 40:976df7c37ad5 | 146 | |
| emilmont | 40:976df7c37ad5 | 147 | |
| emilmont | 40:976df7c37ad5 | 148 | /** |
| emilmont | 40:976df7c37ad5 | 149 | * @brief Product name title=UM10462 Chapter title=LPC11U1x Windowed Watchdog Timer (WWDT) Modification date=3/16/2011 Major revision=0 Minor revision=3 (WWDT) |
| emilmont | 40:976df7c37ad5 | 150 | */ |
| emilmont | 40:976df7c37ad5 | 151 | |
| emilmont | 40:976df7c37ad5 | 152 | typedef struct { /*!< (@ 0x40004000) WWDT Structure */ |
| emilmont | 40:976df7c37ad5 | 153 | __IO uint32_t MOD; /*!< (@ 0x40004000) Watchdog mode register*/ |
| emilmont | 40:976df7c37ad5 | 154 | __IO uint32_t TC; /*!< (@ 0x40004004) Watchdog timer constant register */ |
| emilmont | 40:976df7c37ad5 | 155 | __IO uint32_t FEED; /*!< (@ 0x40004008) Watchdog feed sequence register */ |
| emilmont | 40:976df7c37ad5 | 156 | __I uint32_t TV; /*!< (@ 0x4000400C) Watchdog timer value register */ |
| emilmont | 40:976df7c37ad5 | 157 | __IO uint32_t CLKSEL; /*!< (@ 0x40004010) Watchdog clock select register. */ |
| emilmont | 40:976df7c37ad5 | 158 | __IO uint32_t WARNINT; /*!< (@ 0x40004014) Watchdog Warning Interrupt compare value. */ |
| emilmont | 40:976df7c37ad5 | 159 | __IO uint32_t WINDOW; /*!< (@ 0x40004018) Watchdog Window compare value. */ |
| emilmont | 40:976df7c37ad5 | 160 | } LPC_WWDT_Type; |
| emilmont | 40:976df7c37ad5 | 161 | |
| emilmont | 40:976df7c37ad5 | 162 | |
| emilmont | 40:976df7c37ad5 | 163 | // ------------------------------------------------------------------------------------------------ |
| emilmont | 40:976df7c37ad5 | 164 | // ----- USART ----- |
| emilmont | 40:976df7c37ad5 | 165 | // ------------------------------------------------------------------------------------------------ |
| emilmont | 40:976df7c37ad5 | 166 | |
| emilmont | 40:976df7c37ad5 | 167 | |
| emilmont | 40:976df7c37ad5 | 168 | /** |
| emilmont | 40:976df7c37ad5 | 169 | * @brief Product name title=UM10462 Chapter title=LPC11U1x USART Modification date=3/16/2011 Major revision=0 Minor revision=3 (USART) |
| emilmont | 40:976df7c37ad5 | 170 | */ |
| emilmont | 40:976df7c37ad5 | 171 | |
| emilmont | 40:976df7c37ad5 | 172 | typedef struct { /*!< (@ 0x40008000) USART Structure */ |
| emilmont | 40:976df7c37ad5 | 173 | |
| emilmont | 40:976df7c37ad5 | 174 | union { |
| emilmont | 40:976df7c37ad5 | 175 | __IO uint32_t DLL; /*!< (@ 0x40008000) Divisor Latch LSB. Least significant byte of the baud rate divisor value. The full divisor is used to generate a baud rate from the fractional rate divider. (DLAB=1) */ |
| emilmont | 40:976df7c37ad5 | 176 | __O uint32_t THR; /*!< (@ 0x40008000) Transmit Holding Register. The next character to be transmitted is written here. (DLAB=0) */ |
| emilmont | 40:976df7c37ad5 | 177 | __I uint32_t RBR; /*!< (@ 0x40008000) Receiver Buffer Register. Contains the next received character to be read. (DLAB=0) */ |
| emilmont | 40:976df7c37ad5 | 178 | }; |
| emilmont | 40:976df7c37ad5 | 179 | |
| emilmont | 40:976df7c37ad5 | 180 | union { |
| emilmont | 40:976df7c37ad5 | 181 | __IO uint32_t IER; /*!< (@ 0x40008004) Interrupt Enable Register. Contains individual interrupt enable bits for the 7 potential USART interrupts. (DLAB=0) */ |
| emilmont | 40:976df7c37ad5 | 182 | __IO uint32_t DLM; /*!< (@ 0x40008004) Divisor Latch MSB. Most significant byte of the baud rate divisor value. The full divisor is used to generate a baud rate from the fractional rate divider. (DLAB=1) */ |
| emilmont | 40:976df7c37ad5 | 183 | }; |
| emilmont | 40:976df7c37ad5 | 184 | |
| emilmont | 40:976df7c37ad5 | 185 | union { |
| emilmont | 40:976df7c37ad5 | 186 | __O uint32_t FCR; /*!< (@ 0x40008008) FIFO Control Register. Controls USART FIFO usage and modes. */ |
| emilmont | 40:976df7c37ad5 | 187 | __I uint32_t IIR; /*!< (@ 0x40008008) Interrupt ID Register. Identifies which interrupt(s) are pending. */ |
| emilmont | 40:976df7c37ad5 | 188 | }; |
| emilmont | 40:976df7c37ad5 | 189 | __IO uint32_t LCR; /*!< (@ 0x4000800C) Line Control Register. Contains controls for frame formatting and break generation. */ |
| emilmont | 40:976df7c37ad5 | 190 | __IO uint32_t MCR; /*!< (@ 0x40008010) Modem Control Register. */ |
| emilmont | 40:976df7c37ad5 | 191 | __I uint32_t LSR; /*!< (@ 0x40008014) Line Status Register. Contains flags for transmit and receive status, including line errors. */ |
| emilmont | 40:976df7c37ad5 | 192 | __I uint32_t MSR; /*!< (@ 0x40008018) Modem Status Register. */ |
| emilmont | 40:976df7c37ad5 | 193 | __IO uint32_t SCR; /*!< (@ 0x4000801C) Scratch Pad Register. Eight-bit temporary storage for software. */ |
| emilmont | 40:976df7c37ad5 | 194 | __IO uint32_t ACR; /*!< (@ 0x40008020) Auto-baud Control Register. Contains controls for the auto-baud feature. */ |
| emilmont | 40:976df7c37ad5 | 195 | __IO uint32_t ICR; /*!< (@ 0x40008024) IrDA Control Register. Enables and configures the IrDA (remote control) mode. */ |
| emilmont | 40:976df7c37ad5 | 196 | __IO uint32_t FDR; /*!< (@ 0x40008028) Fractional Divider Register. Generates a clock input for the baud rate divider. */ |
| emilmont | 40:976df7c37ad5 | 197 | __IO uint32_t OSR; /*!< (@ 0x4000802C) Oversampling Register. Controls the degree of oversampling during each bit time. */ |
| emilmont | 40:976df7c37ad5 | 198 | __IO uint32_t TER; /*!< (@ 0x40008030) Transmit Enable Register. Turns off USART transmitter for use with software flow control. */ |
| emilmont | 40:976df7c37ad5 | 199 | __I uint32_t RESERVED0[3]; |
| emilmont | 40:976df7c37ad5 | 200 | __IO uint32_t HDEN; /*!< (@ 0x40008040) Half duplex enable register. */ |
| emilmont | 40:976df7c37ad5 | 201 | __I uint32_t RESERVED1; |
| emilmont | 40:976df7c37ad5 | 202 | __IO uint32_t SCICTRL; /*!< (@ 0x40008048) Smart Card Interface Control register. Enables and configures the Smart Card Interface feature. */ |
| emilmont | 40:976df7c37ad5 | 203 | __IO uint32_t RS485CTRL; /*!< (@ 0x4000804C) RS-485/EIA-485 Control. Contains controls to configure various aspects of RS-485/EIA-485 modes. */ |
| emilmont | 40:976df7c37ad5 | 204 | __IO uint32_t RS485ADRMATCH; /*!< (@ 0x40008050) RS-485/EIA-485 address match. Contains the address match value for RS-485/EIA-485 mode. */ |
| emilmont | 40:976df7c37ad5 | 205 | __IO uint32_t RS485DLY; /*!< (@ 0x40008054) RS-485/EIA-485 direction control delay. */ |
| emilmont | 40:976df7c37ad5 | 206 | __IO uint32_t SYNCCTRL; |
| emilmont | 40:976df7c37ad5 | 207 | } LPC_USART_Type; |
| emilmont | 40:976df7c37ad5 | 208 | |
| emilmont | 40:976df7c37ad5 | 209 | |
| emilmont | 40:976df7c37ad5 | 210 | // ------------------------------------------------------------------------------------------------ |
| emilmont | 40:976df7c37ad5 | 211 | // ----- Timer ----- |
| emilmont | 40:976df7c37ad5 | 212 | // ------------------------------------------------------------------------------------------------ |
| emilmont | 40:976df7c37ad5 | 213 | |
| emilmont | 40:976df7c37ad5 | 214 | |
| emilmont | 40:976df7c37ad5 | 215 | /** |
| emilmont | 40:976df7c37ad5 | 216 | * @brief Product name title=UM10462 Chapter title=LPC11U1x 32-bitcounter/timers CT32B0/1 Modification date=3/16/2011 Major revision=0 Minor revision=3 |
| emilmont | 40:976df7c37ad5 | 217 | */ |
| emilmont | 40:976df7c37ad5 | 218 | |
| emilmont | 40:976df7c37ad5 | 219 | typedef struct { /*!< (@ 0x40014000) CT32B0 Structure */ |
| emilmont | 40:976df7c37ad5 | 220 | __IO uint32_t IR; /*!< (@ 0x40014000) Interrupt Register */ |
| emilmont | 40:976df7c37ad5 | 221 | __IO uint32_t TCR; /*!< (@ 0x40014004) Timer Control Register */ |
| emilmont | 40:976df7c37ad5 | 222 | __IO uint32_t TC; /*!< (@ 0x40014008) Timer Counter */ |
| emilmont | 40:976df7c37ad5 | 223 | __IO uint32_t PR; /*!< (@ 0x4001400C) Prescale Register */ |
| emilmont | 40:976df7c37ad5 | 224 | __IO uint32_t PC; /*!< (@ 0x40014010) Prescale Counter */ |
| emilmont | 40:976df7c37ad5 | 225 | __IO uint32_t MCR; /*!< (@ 0x40014014) Match Control Register */ |
| emilmont | 40:976df7c37ad5 | 226 | union { |
| emilmont | 40:976df7c37ad5 | 227 | __IO uint32_t MR[4]; /*!< (@ 0x40014018) Match Register */ |
| emilmont | 40:976df7c37ad5 | 228 | struct{ |
| emilmont | 40:976df7c37ad5 | 229 | __IO uint32_t MR0; /*!< (@ 0x40018018) Match Register. MR0 */ |
| emilmont | 40:976df7c37ad5 | 230 | __IO uint32_t MR1; /*!< (@ 0x4001801C) Match Register. MR1 */ |
| emilmont | 40:976df7c37ad5 | 231 | __IO uint32_t MR2; /*!< (@ 0x40018020) Match Register. MR2 */ |
| emilmont | 40:976df7c37ad5 | 232 | __IO uint32_t MR3; /*!< (@ 0x40018024) Match Register. MR3 */ |
| emilmont | 40:976df7c37ad5 | 233 | }; |
| emilmont | 40:976df7c37ad5 | 234 | }; |
| emilmont | 40:976df7c37ad5 | 235 | __IO uint32_t CCR; /*!< (@ 0x40014028) Capture Control Register */ |
| emilmont | 40:976df7c37ad5 | 236 | union{ |
| emilmont | 40:976df7c37ad5 | 237 | __I uint32_t CR[4]; /*!< (@ 0x4001402C) Capture Register */ |
| emilmont | 40:976df7c37ad5 | 238 | struct{ |
| emilmont | 40:976df7c37ad5 | 239 | __I uint32_t CR0; /*!< (@ 0x4001802C) Capture Register. CR 0 */ |
| emilmont | 40:976df7c37ad5 | 240 | __I uint32_t CR1; /*!< (@ 0x40018030) Capture Register. CR 1 */ |
| emilmont | 40:976df7c37ad5 | 241 | __I uint32_t CR2; /*!< (@ 0x40018034) Capture Register. CR 2 */ |
| emilmont | 40:976df7c37ad5 | 242 | __I uint32_t CR3; /*!< (@ 0x40018038) Capture Register. CR 3 */ |
| emilmont | 40:976df7c37ad5 | 243 | }; |
| emilmont | 40:976df7c37ad5 | 244 | }; |
| emilmont | 40:976df7c37ad5 | 245 | __IO uint32_t EMR; /*!< (@ 0x4001403C) External Match Register */ |
| emilmont | 40:976df7c37ad5 | 246 | __I uint32_t RESERVED0[12]; |
| emilmont | 40:976df7c37ad5 | 247 | __IO uint32_t CTCR; /*!< (@ 0x40014070) Count Control Register */ |
| emilmont | 40:976df7c37ad5 | 248 | __IO uint32_t PWMC; /*!< (@ 0x40014074) PWM Control Register */ |
| emilmont | 40:976df7c37ad5 | 249 | } LPC_CTxxBx_Type; |
| emilmont | 40:976df7c37ad5 | 250 | |
| emilmont | 40:976df7c37ad5 | 251 | |
| emilmont | 40:976df7c37ad5 | 252 | |
| emilmont | 40:976df7c37ad5 | 253 | // ------------------------------------------------------------------------------------------------ |
| emilmont | 40:976df7c37ad5 | 254 | // ----- ADC ----- |
| emilmont | 40:976df7c37ad5 | 255 | // ------------------------------------------------------------------------------------------------ |
| emilmont | 40:976df7c37ad5 | 256 | |
| emilmont | 40:976df7c37ad5 | 257 | |
| emilmont | 40:976df7c37ad5 | 258 | /** |
| emilmont | 40:976df7c37ad5 | 259 | * @brief Product name title=UM10462 Chapter title=LPC11U1x ADC Modification date=3/16/2011 Major revision=0 Minor revision=3 (ADC) |
| emilmont | 40:976df7c37ad5 | 260 | */ |
| emilmont | 40:976df7c37ad5 | 261 | |
| emilmont | 40:976df7c37ad5 | 262 | typedef struct { /*!< (@ 0x4001C000) ADC Structure */ |
| emilmont | 40:976df7c37ad5 | 263 | __IO uint32_t CR; /*!< (@ 0x4001C000) A/D Control Register */ |
| emilmont | 40:976df7c37ad5 | 264 | __IO uint32_t GDR; /*!< (@ 0x4001C004) A/D Global Data Register */ |
| emilmont | 40:976df7c37ad5 | 265 | __I uint32_t RESERVED0[1]; |
| emilmont | 40:976df7c37ad5 | 266 | __IO uint32_t INTEN; /*!< (@ 0x4001C00C) A/D Interrupt Enable Register */ |
| emilmont | 40:976df7c37ad5 | 267 | union{ |
| emilmont | 40:976df7c37ad5 | 268 | __I uint32_t DR[8]; /*!< (@ 0x4001C010) A/D Channel Data Register*/ |
| emilmont | 40:976df7c37ad5 | 269 | struct{ |
| emilmont | 40:976df7c37ad5 | 270 | __IO uint32_t DR0; /*!< (@ 0x40020010) A/D Channel Data Register 0*/ |
| emilmont | 40:976df7c37ad5 | 271 | __IO uint32_t DR1; /*!< (@ 0x40020014) A/D Channel Data Register 1*/ |
| emilmont | 40:976df7c37ad5 | 272 | __IO uint32_t DR2; /*!< (@ 0x40020018) A/D Channel Data Register 2*/ |
| emilmont | 40:976df7c37ad5 | 273 | __IO uint32_t DR3; /*!< (@ 0x4002001C) A/D Channel Data Register 3*/ |
| emilmont | 40:976df7c37ad5 | 274 | __IO uint32_t DR4; /*!< (@ 0x40020020) A/D Channel Data Register 4*/ |
| emilmont | 40:976df7c37ad5 | 275 | __IO uint32_t DR5; /*!< (@ 0x40020024) A/D Channel Data Register 5*/ |
| emilmont | 40:976df7c37ad5 | 276 | __IO uint32_t DR6; /*!< (@ 0x40020028) A/D Channel Data Register 6*/ |
| emilmont | 40:976df7c37ad5 | 277 | __IO uint32_t DR7; /*!< (@ 0x4002002C) A/D Channel Data Register 7*/ |
| emilmont | 40:976df7c37ad5 | 278 | }; |
| emilmont | 40:976df7c37ad5 | 279 | }; |
| emilmont | 40:976df7c37ad5 | 280 | __I uint32_t STAT; /*!< (@ 0x4001C030) A/D Status Register. */ |
| emilmont | 40:976df7c37ad5 | 281 | } LPC_ADC_Type; |
| emilmont | 40:976df7c37ad5 | 282 | |
| emilmont | 40:976df7c37ad5 | 283 | |
| emilmont | 40:976df7c37ad5 | 284 | // ------------------------------------------------------------------------------------------------ |
| emilmont | 40:976df7c37ad5 | 285 | // ----- PMU ----- |
| emilmont | 40:976df7c37ad5 | 286 | // ------------------------------------------------------------------------------------------------ |
| emilmont | 40:976df7c37ad5 | 287 | |
| emilmont | 40:976df7c37ad5 | 288 | |
| emilmont | 40:976df7c37ad5 | 289 | /** |
| emilmont | 40:976df7c37ad5 | 290 | * @brief Product name title=UM10462 Chapter title=LPC11U1x Power Management Unit (PMU) Modification date=3/16/2011 Major revision=0 Minor revision=3 (PMU) |
| emilmont | 40:976df7c37ad5 | 291 | */ |
| emilmont | 40:976df7c37ad5 | 292 | |
| emilmont | 40:976df7c37ad5 | 293 | typedef struct { /*!< (@ 0x40038000) PMU Structure */ |
| emilmont | 40:976df7c37ad5 | 294 | __IO uint32_t PCON; /*!< (@ 0x40038000) Power control register */ |
| emilmont | 40:976df7c37ad5 | 295 | union{ |
| emilmont | 40:976df7c37ad5 | 296 | __IO uint32_t GPREG[4]; /*!< (@ 0x40038004) General purpose register 0 */ |
| emilmont | 40:976df7c37ad5 | 297 | struct{ |
| emilmont | 40:976df7c37ad5 | 298 | __IO uint32_t GPREG0; /*!< (@ 0x40038004) General purpose register 0 */ |
| emilmont | 40:976df7c37ad5 | 299 | __IO uint32_t GPREG1; /*!< (@ 0x40038008) General purpose register 1 */ |
| emilmont | 40:976df7c37ad5 | 300 | __IO uint32_t GPREG2; /*!< (@ 0x4003800C) General purpose register 2 */ |
| emilmont | 40:976df7c37ad5 | 301 | __IO uint32_t GPREG3; /*!< (@ 0x40038010) General purpose register 3 */ |
| emilmont | 40:976df7c37ad5 | 302 | }; |
| emilmont | 40:976df7c37ad5 | 303 | }; |
| emilmont | 40:976df7c37ad5 | 304 | } LPC_PMU_Type; |
| emilmont | 40:976df7c37ad5 | 305 | |
| emilmont | 40:976df7c37ad5 | 306 | |
| emilmont | 40:976df7c37ad5 | 307 | // ------------------------------------------------------------------------------------------------ |
| emilmont | 40:976df7c37ad5 | 308 | // ----- FLASHCTRL ----- |
| emilmont | 40:976df7c37ad5 | 309 | // ------------------------------------------------------------------------------------------------ |
| emilmont | 40:976df7c37ad5 | 310 | |
| emilmont | 40:976df7c37ad5 | 311 | |
| emilmont | 40:976df7c37ad5 | 312 | /** |
| emilmont | 40:976df7c37ad5 | 313 | * @brief Product name title=UM10462 Chapter title=LPC11U1x Flash programming firmware Modification date=3/17/2011 Major revision=0 Minor revision=3 (FLASHCTRL) |
| emilmont | 40:976df7c37ad5 | 314 | */ |
| emilmont | 40:976df7c37ad5 | 315 | |
| emilmont | 40:976df7c37ad5 | 316 | typedef struct { /*!< (@ 0x4003C000) FLASHCTRL Structure */ |
| emilmont | 40:976df7c37ad5 | 317 | __I uint32_t RESERVED0[4]; |
| emilmont | 40:976df7c37ad5 | 318 | __IO uint32_t FLASHCFG; /*!< (@ 0x4003C010) Flash memory access time configuration register */ |
| emilmont | 40:976df7c37ad5 | 319 | __I uint32_t RESERVED1[3]; |
| emilmont | 40:976df7c37ad5 | 320 | __IO uint32_t FMSSTART; /*!< (@ 0x4003C020) Signature start address register */ |
| emilmont | 40:976df7c37ad5 | 321 | __IO uint32_t FMSSTOP; /*!< (@ 0x4003C024) Signature stop-address register */ |
| emilmont | 40:976df7c37ad5 | 322 | __I uint32_t RESERVED2[1]; |
| emilmont | 40:976df7c37ad5 | 323 | __I uint32_t FMSW0; /*!< (@ 0x4003C02C) Word 0 [31:0] */ |
| emilmont | 40:976df7c37ad5 | 324 | __I uint32_t FMSW1; /*!< (@ 0x4003C030) Word 1 [63:32] */ |
| emilmont | 40:976df7c37ad5 | 325 | __I uint32_t FMSW2; /*!< (@ 0x4003C034) Word 2 [95:64] */ |
| emilmont | 40:976df7c37ad5 | 326 | __I uint32_t FMSW3; /*!< (@ 0x4003C038) Word 3 [127:96] */ |
| emilmont | 40:976df7c37ad5 | 327 | __I uint32_t RESERVED3[1001]; |
| emilmont | 40:976df7c37ad5 | 328 | __I uint32_t FMSTAT; /*!< (@ 0x4003CFE0) Signature generation status register */ |
| emilmont | 40:976df7c37ad5 | 329 | __I uint32_t RESERVED4[1]; |
| emilmont | 40:976df7c37ad5 | 330 | __IO uint32_t FMSTATCLR; /*!< (@ 0x4003CFE8) Signature generation status clear register */ |
| emilmont | 40:976df7c37ad5 | 331 | } LPC_FLASHCTRL_Type; |
| emilmont | 40:976df7c37ad5 | 332 | |
| emilmont | 40:976df7c37ad5 | 333 | |
| emilmont | 40:976df7c37ad5 | 334 | // ------------------------------------------------------------------------------------------------ |
| emilmont | 40:976df7c37ad5 | 335 | // ----- SSP0/1 ----- |
| emilmont | 40:976df7c37ad5 | 336 | // ------------------------------------------------------------------------------------------------ |
| emilmont | 40:976df7c37ad5 | 337 | |
| emilmont | 40:976df7c37ad5 | 338 | |
| emilmont | 40:976df7c37ad5 | 339 | /** |
| emilmont | 40:976df7c37ad5 | 340 | * @brief Product name title=UM10462 Chapter title=LPC11U1x SSP/SPI Modification date=3/16/2011 Major revision=0 Minor revision=3 (SSP0) |
| emilmont | 40:976df7c37ad5 | 341 | */ |
| emilmont | 40:976df7c37ad5 | 342 | |
| emilmont | 40:976df7c37ad5 | 343 | typedef struct { /*!< (@ 0x40040000) SSP0 Structure */ |
| emilmont | 40:976df7c37ad5 | 344 | __IO uint32_t CR0; /*!< (@ 0x40040000) Control Register 0. Selects the serial clock rate, bus type, and data size. */ |
| emilmont | 40:976df7c37ad5 | 345 | __IO uint32_t CR1; /*!< (@ 0x40040004) Control Register 1. Selects master/slave and other modes. */ |
| emilmont | 40:976df7c37ad5 | 346 | __IO uint32_t DR; /*!< (@ 0x40040008) Data Register. Writes fill the transmit FIFO, and reads empty the receive FIFO. */ |
| emilmont | 40:976df7c37ad5 | 347 | __I uint32_t SR; /*!< (@ 0x4004000C) Status Register */ |
| emilmont | 40:976df7c37ad5 | 348 | __IO uint32_t CPSR; /*!< (@ 0x40040010) Clock Prescale Register */ |
| emilmont | 40:976df7c37ad5 | 349 | __IO uint32_t IMSC; /*!< (@ 0x40040014) Interrupt Mask Set and Clear Register */ |
| emilmont | 40:976df7c37ad5 | 350 | __I uint32_t RIS; /*!< (@ 0x40040018) Raw Interrupt Status Register */ |
| emilmont | 40:976df7c37ad5 | 351 | __I uint32_t MIS; /*!< (@ 0x4004001C) Masked Interrupt Status Register */ |
| emilmont | 40:976df7c37ad5 | 352 | __IO uint32_t ICR; /*!< (@ 0x40040020) SSPICR Interrupt Clear Register */ |
| emilmont | 40:976df7c37ad5 | 353 | } LPC_SSPx_Type; |
| emilmont | 40:976df7c37ad5 | 354 | |
| emilmont | 40:976df7c37ad5 | 355 | |
| emilmont | 40:976df7c37ad5 | 356 | |
| emilmont | 40:976df7c37ad5 | 357 | // ------------------------------------------------------------------------------------------------ |
| emilmont | 40:976df7c37ad5 | 358 | // ----- IOCONFIG ----- |
| emilmont | 40:976df7c37ad5 | 359 | // ------------------------------------------------------------------------------------------------ |
| emilmont | 40:976df7c37ad5 | 360 | |
| emilmont | 40:976df7c37ad5 | 361 | |
| emilmont | 40:976df7c37ad5 | 362 | /** |
| emilmont | 40:976df7c37ad5 | 363 | * @brief Product name title=UM10462 Chapter title=LPC11U1x I/O configuration Modification date=3/16/2011 Major revision=0 Minor revision=3 (IOCONFIG) |
| emilmont | 40:976df7c37ad5 | 364 | */ |
| emilmont | 40:976df7c37ad5 | 365 | |
| emilmont | 40:976df7c37ad5 | 366 | typedef struct { /*!< (@ 0x40044000) IOCONFIG Structure */ |
| emilmont | 40:976df7c37ad5 | 367 | __IO uint32_t RESET_PIO0_0; /*!< (@ 0x40044000) I/O configuration for pin RESET/PIO0_0 */ |
| emilmont | 40:976df7c37ad5 | 368 | __IO uint32_t PIO0_1; /*!< (@ 0x40044004) I/O configuration for pin PIO0_1/CLKOUT/CT32B0_MAT2/USB_FTOGGLE */ |
| emilmont | 40:976df7c37ad5 | 369 | __IO uint32_t PIO0_2; /*!< (@ 0x40044008) I/O configuration for pin PIO0_2/SSEL0/CT16B0_CAP0 */ |
| emilmont | 40:976df7c37ad5 | 370 | __IO uint32_t PIO0_3; /*!< (@ 0x4004400C) I/O configuration for pin PIO0_3/USB_VBUS */ |
| emilmont | 40:976df7c37ad5 | 371 | __IO uint32_t PIO0_4; /*!< (@ 0x40044010) I/O configuration for pin PIO0_4/SCL */ |
| emilmont | 40:976df7c37ad5 | 372 | __IO uint32_t PIO0_5; /*!< (@ 0x40044014) I/O configuration for pin PIO0_5/SDA */ |
| emilmont | 40:976df7c37ad5 | 373 | __IO uint32_t PIO0_6; /*!< (@ 0x40044018) I/O configuration for pin PIO0_6/USB_CONNECT/SCK0 */ |
| emilmont | 40:976df7c37ad5 | 374 | __IO uint32_t PIO0_7; /*!< (@ 0x4004401C) I/O configuration for pin PIO0_7/CTS */ |
| emilmont | 40:976df7c37ad5 | 375 | __IO uint32_t PIO0_8; /*!< (@ 0x40044020) I/O configuration for pin PIO0_8/MISO0/CT16B0_MAT0 */ |
| emilmont | 40:976df7c37ad5 | 376 | __IO uint32_t PIO0_9; /*!< (@ 0x40044024) I/O configuration for pin PIO0_9/MOSI0/CT16B0_MAT1 */ |
| emilmont | 40:976df7c37ad5 | 377 | __IO uint32_t SWCLK_PIO0_10; /*!< (@ 0x40044028) I/O configuration for pin SWCLK/PIO0_10/ SCK0/CT16B0_MAT2 */ |
| emilmont | 40:976df7c37ad5 | 378 | __IO uint32_t TDI_PIO0_11; /*!< (@ 0x4004402C) I/O configuration for pin TDI/PIO0_11/AD0/CT32B0_MAT3 */ |
| emilmont | 40:976df7c37ad5 | 379 | __IO uint32_t TMS_PIO0_12; /*!< (@ 0x40044030) I/O configuration for pin TMS/PIO0_12/AD1/CT32B1_CAP0 */ |
| emilmont | 40:976df7c37ad5 | 380 | __IO uint32_t TDO_PIO0_13; /*!< (@ 0x40044034) I/O configuration for pin TDO/PIO0_13/AD2/CT32B1_MAT0 */ |
| emilmont | 40:976df7c37ad5 | 381 | __IO uint32_t TRST_PIO0_14; /*!< (@ 0x40044038) I/O configuration for pin TRST/PIO0_14/AD3/CT32B1_MAT1 */ |
| emilmont | 40:976df7c37ad5 | 382 | __IO uint32_t SWDIO_PIO0_15; /*!< (@ 0x4004403C) I/O configuration for pin SWDIO/PIO0_15/AD4/CT32B1_MAT2 */ |
| emilmont | 40:976df7c37ad5 | 383 | __IO uint32_t PIO0_16; /*!< (@ 0x40044040) I/O configuration for pin PIO0_16/AD5/CT32B1_MAT3/ WAKEUP */ |
| emilmont | 40:976df7c37ad5 | 384 | __IO uint32_t PIO0_17; /*!< (@ 0x40044044) I/O configuration for pin PIO0_17/RTS/CT32B0_CAP0/SCLK */ |
| emilmont | 40:976df7c37ad5 | 385 | __IO uint32_t PIO0_18; /*!< (@ 0x40044048) I/O configuration for pin PIO0_18/RXD/CT32B0_MAT0 */ |
| emilmont | 40:976df7c37ad5 | 386 | __IO uint32_t PIO0_19; /*!< (@ 0x4004404C) I/O configuration for pin PIO0_19/TXD/CT32B0_MAT1 */ |
| emilmont | 40:976df7c37ad5 | 387 | __IO uint32_t PIO0_20; /*!< (@ 0x40044050) I/O configuration for pin PIO0_20/CT16B1_CAP0 */ |
| emilmont | 40:976df7c37ad5 | 388 | __IO uint32_t PIO0_21; /*!< (@ 0x40044054) I/O configuration for pin PIO0_21/CT16B1_MAT0/MOSI1 */ |
| emilmont | 40:976df7c37ad5 | 389 | __IO uint32_t PIO0_22; /*!< (@ 0x40044058) I/O configuration for pin PIO0_22/AD6/CT16B1_MAT1/MISO1 */ |
| emilmont | 40:976df7c37ad5 | 390 | __IO uint32_t PIO0_23; /*!< (@ 0x4004405C) I/O configuration for pin PIO0_23/AD7 */ |
| emilmont | 40:976df7c37ad5 | 391 | __IO uint32_t PIO1_0; /*!< Offset: 0x060 */ |
| emilmont | 40:976df7c37ad5 | 392 | __IO uint32_t PIO1_1; |
| emilmont | 40:976df7c37ad5 | 393 | __IO uint32_t PIO1_2; |
| emilmont | 40:976df7c37ad5 | 394 | __IO uint32_t PIO1_3; |
| emilmont | 40:976df7c37ad5 | 395 | __IO uint32_t PIO1_4; /*!< Offset: 0x070 */ |
| emilmont | 40:976df7c37ad5 | 396 | __IO uint32_t PIO1_5; /*!< (@ 0x40044074) I/O configuration for pin PIO1_5/CT32B1_CAP1 */ |
| emilmont | 40:976df7c37ad5 | 397 | __IO uint32_t PIO1_6; |
| emilmont | 40:976df7c37ad5 | 398 | __IO uint32_t PIO1_7; |
| emilmont | 40:976df7c37ad5 | 399 | __IO uint32_t PIO1_8; /*!< Offset: 0x080 */ |
| emilmont | 40:976df7c37ad5 | 400 | __IO uint32_t PIO1_9; |
| emilmont | 40:976df7c37ad5 | 401 | __IO uint32_t PIO1_10; |
| emilmont | 40:976df7c37ad5 | 402 | __IO uint32_t PIO1_11; |
| emilmont | 40:976df7c37ad5 | 403 | __IO uint32_t PIO1_12; /*!< Offset: 0x090 */ |
| emilmont | 40:976df7c37ad5 | 404 | __IO uint32_t PIO1_13; /*!< (@ 0x40044094) I/O configuration for pin PIO1_13/DTR/CT16B0_MAT0/TXD */ |
| emilmont | 40:976df7c37ad5 | 405 | __IO uint32_t PIO1_14; /*!< (@ 0x40044098) I/O configuration for pin PIO1_14/DSR/CT16B0_MAT1/RXD */ |
| emilmont | 40:976df7c37ad5 | 406 | __IO uint32_t PIO1_15; /*!< (@ 0x4004409C) I/O configuration for pin PIO1_15/DCD/ CT16B0_MAT2/SCK1 */ |
| emilmont | 40:976df7c37ad5 | 407 | __IO uint32_t PIO1_16; /*!< (@ 0x400440A0) I/O configuration for pin PIO1_16/RI/CT16B0_CAP0 */ |
| emilmont | 40:976df7c37ad5 | 408 | __IO uint32_t PIO1_17; |
| emilmont | 40:976df7c37ad5 | 409 | __IO uint32_t PIO1_18; |
| emilmont | 40:976df7c37ad5 | 410 | __IO uint32_t PIO1_19; /*!< (@ 0x400440AC) I/O configuration for pin PIO1_19/DTR/SSEL1 */ |
| emilmont | 40:976df7c37ad5 | 411 | __IO uint32_t PIO1_20; /*!< (@ 0x400440B0) I/O configuration for pin PIO1_20/DSR/SCK1 */ |
| emilmont | 40:976df7c37ad5 | 412 | __IO uint32_t PIO1_21; /*!< (@ 0x400440B4) I/O configuration for pin PIO1_21/DCD/MISO1 */ |
| emilmont | 40:976df7c37ad5 | 413 | __IO uint32_t PIO1_22; /*!< (@ 0x400440B8) I/O configuration for pin PIO1_22/RI/MOSI1 */ |
| emilmont | 40:976df7c37ad5 | 414 | __IO uint32_t PIO1_23; /*!< (@ 0x400440BC) I/O configuration for pin PIO1_23/CT16B1_MAT1/SSEL1 */ |
| emilmont | 40:976df7c37ad5 | 415 | __IO uint32_t PIO1_24; /*!< (@ 0x400440C0) I/O configuration for pin PIO1_24/ CT32B0_MAT0 */ |
| emilmont | 40:976df7c37ad5 | 416 | __IO uint32_t PIO1_25; /*!< (@ 0x400440C4) I/O configuration for pin PIO1_25/CT32B0_MAT1 */ |
| emilmont | 40:976df7c37ad5 | 417 | __IO uint32_t PIO1_26; /*!< (@ 0x400440C8) I/O configuration for pin PIO1_26/CT32B0_MAT2/ RXD */ |
| emilmont | 40:976df7c37ad5 | 418 | __IO uint32_t PIO1_27; /*!< (@ 0x400440CC) I/O configuration for pin PIO1_27/CT32B0_MAT3/ TXD */ |
| emilmont | 40:976df7c37ad5 | 419 | __IO uint32_t PIO1_28; /*!< (@ 0x400440D0) I/O configuration for pin PIO1_28/CT32B0_CAP0/ SCLK */ |
| emilmont | 40:976df7c37ad5 | 420 | __IO uint32_t PIO1_29; /*!< (@ 0x400440D4) I/O configuration for pin PIO1_29/SCK0/ CT32B0_CAP1 */ |
| emilmont | 40:976df7c37ad5 | 421 | __IO uint32_t PIO1_30; |
| emilmont | 40:976df7c37ad5 | 422 | __IO uint32_t PIO1_31; /*!< (@ 0x400440DC) I/O configuration for pin PIO1_31 */ |
| emilmont | 40:976df7c37ad5 | 423 | } LPC_IOCON_Type; |
| emilmont | 40:976df7c37ad5 | 424 | |
| emilmont | 40:976df7c37ad5 | 425 | |
| emilmont | 40:976df7c37ad5 | 426 | // ------------------------------------------------------------------------------------------------ |
| emilmont | 40:976df7c37ad5 | 427 | // ----- SYSCON ----- |
| emilmont | 40:976df7c37ad5 | 428 | // ------------------------------------------------------------------------------------------------ |
| emilmont | 40:976df7c37ad5 | 429 | |
| emilmont | 40:976df7c37ad5 | 430 | |
| emilmont | 40:976df7c37ad5 | 431 | /** |
| emilmont | 40:976df7c37ad5 | 432 | * @brief Product name title=UM10462 Chapter title=LPC11U1x System control block Modification date=3/16/2011 Major revision=0 Minor revision=3 (SYSCON) |
| emilmont | 40:976df7c37ad5 | 433 | */ |
| emilmont | 40:976df7c37ad5 | 434 | |
| emilmont | 40:976df7c37ad5 | 435 | typedef struct { /*!< (@ 0x40048000) SYSCON Structure */ |
| emilmont | 40:976df7c37ad5 | 436 | __IO uint32_t SYSMEMREMAP; /*!< (@ 0x40048000) System memory remap */ |
| emilmont | 40:976df7c37ad5 | 437 | __IO uint32_t PRESETCTRL; /*!< (@ 0x40048004) Peripheral reset control */ |
| emilmont | 40:976df7c37ad5 | 438 | __IO uint32_t SYSPLLCTRL; /*!< (@ 0x40048008) System PLL control */ |
| emilmont | 40:976df7c37ad5 | 439 | __I uint32_t SYSPLLSTAT; /*!< (@ 0x4004800C) System PLL status */ |
| emilmont | 40:976df7c37ad5 | 440 | __IO uint32_t USBPLLCTRL; /*!< (@ 0x40048010) USB PLL control */ |
| emilmont | 40:976df7c37ad5 | 441 | __I uint32_t USBPLLSTAT; /*!< (@ 0x40048014) USB PLL status */ |
| emilmont | 40:976df7c37ad5 | 442 | __I uint32_t RESERVED0[2]; |
| emilmont | 40:976df7c37ad5 | 443 | __IO uint32_t SYSOSCCTRL; /*!< (@ 0x40048020) System oscillator control */ |
| emilmont | 40:976df7c37ad5 | 444 | __IO uint32_t WDTOSCCTRL; /*!< (@ 0x40048024) Watchdog oscillator control */ |
| emilmont | 40:976df7c37ad5 | 445 | __I uint32_t RESERVED1[2]; |
| emilmont | 40:976df7c37ad5 | 446 | __IO uint32_t SYSRSTSTAT; /*!< (@ 0x40048030) System reset status register */ |
| emilmont | 40:976df7c37ad5 | 447 | __I uint32_t RESERVED2[3]; |
| emilmont | 40:976df7c37ad5 | 448 | __IO uint32_t SYSPLLCLKSEL; /*!< (@ 0x40048040) System PLL clock source select */ |
| emilmont | 40:976df7c37ad5 | 449 | __IO uint32_t SYSPLLCLKUEN; /*!< (@ 0x40048044) System PLL clock source update enable */ |
| emilmont | 40:976df7c37ad5 | 450 | __IO uint32_t USBPLLCLKSEL; /*!< (@ 0x40048048) USB PLL clock source select */ |
| emilmont | 40:976df7c37ad5 | 451 | __IO uint32_t USBPLLCLKUEN; /*!< (@ 0x4004804C) USB PLL clock source update enable */ |
| emilmont | 40:976df7c37ad5 | 452 | __I uint32_t RESERVED3[8]; |
| emilmont | 40:976df7c37ad5 | 453 | __IO uint32_t MAINCLKSEL; /*!< (@ 0x40048070) Main clock source select */ |
| emilmont | 40:976df7c37ad5 | 454 | __IO uint32_t MAINCLKUEN; /*!< (@ 0x40048074) Main clock source update enable */ |
| emilmont | 40:976df7c37ad5 | 455 | __IO uint32_t SYSAHBCLKDIV; /*!< (@ 0x40048078) System clock divider */ |
| emilmont | 40:976df7c37ad5 | 456 | __I uint32_t RESERVED4[1]; |
| emilmont | 40:976df7c37ad5 | 457 | __IO uint32_t SYSAHBCLKCTRL; /*!< (@ 0x40048080) System clock control */ |
| emilmont | 40:976df7c37ad5 | 458 | __I uint32_t RESERVED5[4]; |
| emilmont | 40:976df7c37ad5 | 459 | __IO uint32_t SSP0CLKDIV; /*!< (@ 0x40048094) SSP0 clock divider */ |
| emilmont | 40:976df7c37ad5 | 460 | __IO uint32_t UARTCLKDIV; /*!< (@ 0x40048098) UART clock divider */ |
| emilmont | 40:976df7c37ad5 | 461 | __IO uint32_t SSP1CLKDIV; /*!< (@ 0x4004809C) SSP1 clock divider */ |
| emilmont | 40:976df7c37ad5 | 462 | __I uint32_t RESERVED6[8]; |
| emilmont | 40:976df7c37ad5 | 463 | __IO uint32_t USBCLKSEL; /*!< (@ 0x400480C0) USB clock source select */ |
| emilmont | 40:976df7c37ad5 | 464 | __IO uint32_t USBCLKUEN; /*!< (@ 0x400480C4) USB clock source update enable */ |
| emilmont | 40:976df7c37ad5 | 465 | __IO uint32_t USBCLKDIV; /*!< (@ 0x400480C8) USB clock source divider */ |
| emilmont | 40:976df7c37ad5 | 466 | __I uint32_t RESERVED7[5]; |
| emilmont | 40:976df7c37ad5 | 467 | __IO uint32_t CLKOUTSEL; /*!< (@ 0x400480E0) CLKOUT clock source select */ |
| emilmont | 40:976df7c37ad5 | 468 | __IO uint32_t CLKOUTUEN; /*!< (@ 0x400480E4) CLKOUT clock source update enable */ |
| emilmont | 40:976df7c37ad5 | 469 | __IO uint32_t CLKOUTDIV; /*!< (@ 0x400480E8) CLKOUT clock divider */ |
| emilmont | 40:976df7c37ad5 | 470 | __I uint32_t RESERVED8[5]; |
| emilmont | 40:976df7c37ad5 | 471 | __I uint32_t PIOPORCAP0; /*!< (@ 0x40048100) POR captured PIO status 0 */ |
| emilmont | 40:976df7c37ad5 | 472 | __I uint32_t PIOPORCAP1; /*!< (@ 0x40048104) POR captured PIO status 1 */ |
| emilmont | 40:976df7c37ad5 | 473 | __I uint32_t RESERVED9[18]; |
| emilmont | 40:976df7c37ad5 | 474 | __IO uint32_t BODCTRL; /*!< (@ 0x40048150) Brown-Out Detect */ |
| emilmont | 40:976df7c37ad5 | 475 | __IO uint32_t SYSTCKCAL; /*!< (@ 0x40048154) System tick counter calibration */ |
| emilmont | 40:976df7c37ad5 | 476 | __I uint32_t RESERVED10[6]; |
| emilmont | 40:976df7c37ad5 | 477 | __IO uint32_t IRQLATENCY; /*!< (@ 0x40048170) IQR delay */ |
| emilmont | 40:976df7c37ad5 | 478 | __IO uint32_t NMISRC; /*!< (@ 0x40048174) NMI Source Control */ |
| emilmont | 40:976df7c37ad5 | 479 | __IO uint32_t PINTSEL[8]; /*!< (@ 0x40048178) GPIO Pin Interrupt Select register 0 */ |
| emilmont | 40:976df7c37ad5 | 480 | __IO uint32_t USBCLKCTRL; /*!< (@ 0x40048198) USB clock control */ |
| emilmont | 40:976df7c37ad5 | 481 | __I uint32_t USBCLKST; /*!< (@ 0x4004819C) USB clock status */ |
| emilmont | 40:976df7c37ad5 | 482 | __I uint32_t RESERVED11[25]; |
| emilmont | 40:976df7c37ad5 | 483 | __IO uint32_t STARTERP0; /*!< (@ 0x40048204) Start logic 0 interrupt wake-up enable register 0 */ |
| emilmont | 40:976df7c37ad5 | 484 | __I uint32_t RESERVED12[3]; |
| emilmont | 40:976df7c37ad5 | 485 | __IO uint32_t STARTERP1; /*!< (@ 0x40048214) Start logic 1 interrupt wake-up enable register 1 */ |
| emilmont | 40:976df7c37ad5 | 486 | __I uint32_t RESERVED13[6]; |
| emilmont | 40:976df7c37ad5 | 487 | __IO uint32_t PDSLEEPCFG; /*!< (@ 0x40048230) Power-down states in deep-sleep mode */ |
| emilmont | 40:976df7c37ad5 | 488 | __IO uint32_t PDAWAKECFG; /*!< (@ 0x40048234) Power-down states for wake-up from deep-sleep */ |
| emilmont | 40:976df7c37ad5 | 489 | __IO uint32_t PDRUNCFG; /*!< (@ 0x40048238) Power configuration register */ |
| emilmont | 40:976df7c37ad5 | 490 | __I uint32_t RESERVED14[110]; |
| emilmont | 40:976df7c37ad5 | 491 | __I uint32_t DEVICE_ID; /*!< (@ 0x400483F4) Device ID */ |
| emilmont | 40:976df7c37ad5 | 492 | } LPC_SYSCON_Type; |
| emilmont | 40:976df7c37ad5 | 493 | |
| emilmont | 40:976df7c37ad5 | 494 | |
| emilmont | 40:976df7c37ad5 | 495 | // ------------------------------------------------------------------------------------------------ |
| emilmont | 40:976df7c37ad5 | 496 | // ----- GPIO_PIN_INT ----- |
| emilmont | 40:976df7c37ad5 | 497 | // ------------------------------------------------------------------------------------------------ |
| emilmont | 40:976df7c37ad5 | 498 | |
| emilmont | 40:976df7c37ad5 | 499 | |
| emilmont | 40:976df7c37ad5 | 500 | /** |
| emilmont | 40:976df7c37ad5 | 501 | * @brief Product name title=UM10462 Chapter title=LPC11U1x GPIO Modification date=3/17/2011 Major revision=0 Minor revision=3 (GPIO_PIN_INT) |
| emilmont | 40:976df7c37ad5 | 502 | */ |
| emilmont | 40:976df7c37ad5 | 503 | |
| emilmont | 40:976df7c37ad5 | 504 | typedef struct { /*!< (@ 0x4004C000) GPIO_PIN_INT Structure */ |
| emilmont | 40:976df7c37ad5 | 505 | __IO uint32_t ISEL; /*!< (@ 0x4004C000) Pin Interrupt Mode register */ |
| emilmont | 40:976df7c37ad5 | 506 | __IO uint32_t IENR; /*!< (@ 0x4004C004) Pin Interrupt Enable (Rising) register */ |
| emilmont | 40:976df7c37ad5 | 507 | __IO uint32_t SIENR; /*!< (@ 0x4004C008) Set Pin Interrupt Enable (Rising) register */ |
| emilmont | 40:976df7c37ad5 | 508 | __IO uint32_t CIENR; /*!< (@ 0x4004C00C) Clear Pin Interrupt Enable (Rising) register */ |
| emilmont | 40:976df7c37ad5 | 509 | __IO uint32_t IENF; /*!< (@ 0x4004C010) Pin Interrupt Enable Falling Edge / Active Level register */ |
| emilmont | 40:976df7c37ad5 | 510 | __IO uint32_t SIENF; /*!< (@ 0x4004C014) Set Pin Interrupt Enable Falling Edge / Active Level register */ |
| emilmont | 40:976df7c37ad5 | 511 | __IO uint32_t CIENF; /*!< (@ 0x4004C018) Clear Pin Interrupt Enable Falling Edge / Active Level address */ |
| emilmont | 40:976df7c37ad5 | 512 | __IO uint32_t RISE; /*!< (@ 0x4004C01C) Pin Interrupt Rising Edge register */ |
| emilmont | 40:976df7c37ad5 | 513 | __IO uint32_t FALL; /*!< (@ 0x4004C020) Pin Interrupt Falling Edge register */ |
| emilmont | 40:976df7c37ad5 | 514 | __IO uint32_t IST; /*!< (@ 0x4004C024) Pin Interrupt Status register */ |
| emilmont | 40:976df7c37ad5 | 515 | } LPC_GPIO_PIN_INT_Type; |
| emilmont | 40:976df7c37ad5 | 516 | |
| emilmont | 40:976df7c37ad5 | 517 | |
| emilmont | 40:976df7c37ad5 | 518 | // ------------------------------------------------------------------------------------------------ |
| emilmont | 40:976df7c37ad5 | 519 | // ----- GPIO_GROUP_INT0/1 ----- |
| emilmont | 40:976df7c37ad5 | 520 | // ------------------------------------------------------------------------------------------------ |
| emilmont | 40:976df7c37ad5 | 521 | |
| emilmont | 40:976df7c37ad5 | 522 | |
| emilmont | 40:976df7c37ad5 | 523 | /** |
| emilmont | 40:976df7c37ad5 | 524 | * @brief Product name title=UM10462 Chapter title=LPC11U1x GPIO Modification date=3/17/2011 Major revision=0 Minor revision=3 (GPIO_GROUP_INT0) |
| emilmont | 40:976df7c37ad5 | 525 | */ |
| emilmont | 40:976df7c37ad5 | 526 | |
| emilmont | 40:976df7c37ad5 | 527 | typedef struct { /*!< (@ 0x4005C000) GPIO_GROUP_INT0 Structure */ |
| emilmont | 40:976df7c37ad5 | 528 | __IO uint32_t CTRL; /*!< (@ 0x4005C000) GPIO grouped interrupt control register */ |
| emilmont | 40:976df7c37ad5 | 529 | __I uint32_t RESERVED0[7]; |
| emilmont | 40:976df7c37ad5 | 530 | __IO uint32_t PORT_POL[2]; /*!< (@ 0x4005C020) GPIO grouped interrupt port 0 polarity register */ |
| emilmont | 40:976df7c37ad5 | 531 | __I uint32_t RESERVED1[6]; |
| emilmont | 40:976df7c37ad5 | 532 | __IO uint32_t PORT_ENA[2]; /*!< (@ 0x4005C040) GPIO grouped interrupt port 0/1 enable register */ |
| emilmont | 40:976df7c37ad5 | 533 | } LPC_GPIO_GROUP_INTx_Type; |
| emilmont | 40:976df7c37ad5 | 534 | |
| emilmont | 40:976df7c37ad5 | 535 | |
| emilmont | 40:976df7c37ad5 | 536 | |
| emilmont | 40:976df7c37ad5 | 537 | // ------------------------------------------------------------------------------------------------ |
| emilmont | 40:976df7c37ad5 | 538 | // ----- USB ----- |
| emilmont | 40:976df7c37ad5 | 539 | // ------------------------------------------------------------------------------------------------ |
| emilmont | 40:976df7c37ad5 | 540 | |
| emilmont | 40:976df7c37ad5 | 541 | |
| emilmont | 40:976df7c37ad5 | 542 | /** |
| emilmont | 40:976df7c37ad5 | 543 | * @brief Product name title=UM10462 Chapter title=LPC11U1x USB2.0device controller Modification date=3/16/2011 Major revision=0 Minor revision=3 (USB) |
| emilmont | 40:976df7c37ad5 | 544 | */ |
| emilmont | 40:976df7c37ad5 | 545 | |
| emilmont | 40:976df7c37ad5 | 546 | typedef struct { /*!< (@ 0x40080000) USB Structure */ |
| emilmont | 40:976df7c37ad5 | 547 | __IO uint32_t DEVCMDSTAT; /*!< (@ 0x40080000) USB Device Command/Status register */ |
| emilmont | 40:976df7c37ad5 | 548 | __IO uint32_t INFO; /*!< (@ 0x40080004) USB Info register */ |
| emilmont | 40:976df7c37ad5 | 549 | __IO uint32_t EPLISTSTART; /*!< (@ 0x40080008) USB EP Command/Status List start address */ |
| emilmont | 40:976df7c37ad5 | 550 | __IO uint32_t DATABUFSTART; /*!< (@ 0x4008000C) USB Data buffer start address */ |
| emilmont | 40:976df7c37ad5 | 551 | __IO uint32_t LPM; /*!< (@ 0x40080010) Link Power Management register */ |
| emilmont | 40:976df7c37ad5 | 552 | __IO uint32_t EPSKIP; /*!< (@ 0x40080014) USB Endpoint skip */ |
| emilmont | 40:976df7c37ad5 | 553 | __IO uint32_t EPINUSE; /*!< (@ 0x40080018) USB Endpoint Buffer in use */ |
| emilmont | 40:976df7c37ad5 | 554 | __IO uint32_t EPBUFCFG; /*!< (@ 0x4008001C) USB Endpoint Buffer Configuration register */ |
| emilmont | 40:976df7c37ad5 | 555 | __IO uint32_t INTSTAT; /*!< (@ 0x40080020) USB interrupt status register */ |
| emilmont | 40:976df7c37ad5 | 556 | __IO uint32_t INTEN; /*!< (@ 0x40080024) USB interrupt enable register */ |
| emilmont | 40:976df7c37ad5 | 557 | __IO uint32_t INTSETSTAT; /*!< (@ 0x40080028) USB set interrupt status register */ |
| emilmont | 40:976df7c37ad5 | 558 | __IO uint32_t INTROUTING; /*!< (@ 0x4008002C) USB interrupt routing register */ |
| emilmont | 40:976df7c37ad5 | 559 | __I uint32_t RESERVED0[1]; |
| emilmont | 40:976df7c37ad5 | 560 | __I uint32_t EPTOGGLE; /*!< (@ 0x40080034) USB Endpoint toggle register */ |
| emilmont | 40:976df7c37ad5 | 561 | } LPC_USB_Type; |
| emilmont | 40:976df7c37ad5 | 562 | |
| emilmont | 40:976df7c37ad5 | 563 | |
| emilmont | 40:976df7c37ad5 | 564 | // ------------------------------------------------------------------------------------------------ |
| emilmont | 40:976df7c37ad5 | 565 | // ----- GPIO_PORT ----- |
| emilmont | 40:976df7c37ad5 | 566 | // ------------------------------------------------------------------------------------------------ |
| emilmont | 40:976df7c37ad5 | 567 | |
| emilmont | 40:976df7c37ad5 | 568 | |
| emilmont | 40:976df7c37ad5 | 569 | /** |
| emilmont | 40:976df7c37ad5 | 570 | * @brief Product name title=UM10462 Chapter title=LPC11U1x GPIO Modification date=3/17/2011 Major revision=0 Minor revision=3 (GPIO_PORT) |
| emilmont | 40:976df7c37ad5 | 571 | */ |
| emilmont | 40:976df7c37ad5 | 572 | |
| emilmont | 40:976df7c37ad5 | 573 | typedef struct { |
| emilmont | 40:976df7c37ad5 | 574 | union { |
| emilmont | 40:976df7c37ad5 | 575 | struct { |
| emilmont | 40:976df7c37ad5 | 576 | __IO uint8_t B0[32]; /*!< (@ 0x50000000) Byte pin registers port 0; pins PIO0_0 to PIO0_31 */ |
| emilmont | 40:976df7c37ad5 | 577 | __IO uint8_t B1[32]; /*!< (@ 0x50000020) Byte pin registers port 1 */ |
| emilmont | 40:976df7c37ad5 | 578 | }; |
| emilmont | 40:976df7c37ad5 | 579 | __IO uint8_t B[64]; /*!< (@ 0x50000000) Byte pin registers port 0/1 */ |
| emilmont | 40:976df7c37ad5 | 580 | }; |
| emilmont | 40:976df7c37ad5 | 581 | __I uint32_t RESERVED0[1008]; |
| emilmont | 40:976df7c37ad5 | 582 | union { |
| emilmont | 40:976df7c37ad5 | 583 | struct { |
| emilmont | 40:976df7c37ad5 | 584 | __IO uint32_t W0[32]; /*!< (@ 0x50001000) Word pin registers port 0 */ |
| emilmont | 40:976df7c37ad5 | 585 | __IO uint32_t W1[32]; /*!< (@ 0x50001080) Word pin registers port 1 */ |
| emilmont | 40:976df7c37ad5 | 586 | }; |
| emilmont | 40:976df7c37ad5 | 587 | __IO uint32_t W[64]; /*!< (@ 0x50001000) Word pin registers port 0/1 */ |
| emilmont | 40:976df7c37ad5 | 588 | }; |
| emilmont | 40:976df7c37ad5 | 589 | uint32_t RESERVED1[960]; |
| emilmont | 40:976df7c37ad5 | 590 | __IO uint32_t DIR[2]; /* 0x2000 */ |
| emilmont | 40:976df7c37ad5 | 591 | uint32_t RESERVED2[30]; |
| emilmont | 40:976df7c37ad5 | 592 | __IO uint32_t MASK[2]; /* 0x2080 */ |
| emilmont | 40:976df7c37ad5 | 593 | uint32_t RESERVED3[30]; |
| emilmont | 40:976df7c37ad5 | 594 | __IO uint32_t PIN[2]; /* 0x2100 */ |
| emilmont | 40:976df7c37ad5 | 595 | uint32_t RESERVED4[30]; |
| emilmont | 40:976df7c37ad5 | 596 | __IO uint32_t MPIN[2]; /* 0x2180 */ |
| emilmont | 40:976df7c37ad5 | 597 | uint32_t RESERVED5[30]; |
| emilmont | 40:976df7c37ad5 | 598 | __IO uint32_t SET[2]; /* 0x2200 */ |
| emilmont | 40:976df7c37ad5 | 599 | uint32_t RESERVED6[30]; |
| emilmont | 40:976df7c37ad5 | 600 | __O uint32_t CLR[2]; /* 0x2280 */ |
| emilmont | 40:976df7c37ad5 | 601 | uint32_t RESERVED7[30]; |
| emilmont | 40:976df7c37ad5 | 602 | __O uint32_t NOT[2]; /* 0x2300 */ |
| emilmont | 40:976df7c37ad5 | 603 | } LPC_GPIO_Type; |
| emilmont | 40:976df7c37ad5 | 604 | |
| emilmont | 40:976df7c37ad5 | 605 | |
| emilmont | 40:976df7c37ad5 | 606 | #if defined ( __CC_ARM ) |
| emilmont | 40:976df7c37ad5 | 607 | #pragma no_anon_unions |
| emilmont | 40:976df7c37ad5 | 608 | #endif |
| emilmont | 40:976df7c37ad5 | 609 | |
| emilmont | 40:976df7c37ad5 | 610 | |
| emilmont | 40:976df7c37ad5 | 611 | // ------------------------------------------------------------------------------------------------ |
| emilmont | 40:976df7c37ad5 | 612 | // ----- Peripheral memory map ----- |
| emilmont | 40:976df7c37ad5 | 613 | // ------------------------------------------------------------------------------------------------ |
| emilmont | 40:976df7c37ad5 | 614 | |
| emilmont | 40:976df7c37ad5 | 615 | #define LPC_I2C_BASE (0x40000000) |
| emilmont | 40:976df7c37ad5 | 616 | #define LPC_WWDT_BASE (0x40004000) |
| emilmont | 40:976df7c37ad5 | 617 | #define LPC_USART_BASE (0x40008000) |
| emilmont | 40:976df7c37ad5 | 618 | #define LPC_CT16B0_BASE (0x4000C000) |
| emilmont | 40:976df7c37ad5 | 619 | #define LPC_CT16B1_BASE (0x40010000) |
| emilmont | 40:976df7c37ad5 | 620 | #define LPC_CT32B0_BASE (0x40014000) |
| emilmont | 40:976df7c37ad5 | 621 | #define LPC_CT32B1_BASE (0x40018000) |
| emilmont | 40:976df7c37ad5 | 622 | #define LPC_ADC_BASE (0x4001C000) |
| emilmont | 40:976df7c37ad5 | 623 | #define LPC_PMU_BASE (0x40038000) |
| emilmont | 40:976df7c37ad5 | 624 | #define LPC_FLASHCTRL_BASE (0x4003C000) |
| emilmont | 40:976df7c37ad5 | 625 | #define LPC_SSP0_BASE (0x40040000) |
| emilmont | 40:976df7c37ad5 | 626 | #define LPC_SSP1_BASE (0x40058000) |
| emilmont | 40:976df7c37ad5 | 627 | #define LPC_IOCON_BASE (0x40044000) |
| emilmont | 40:976df7c37ad5 | 628 | #define LPC_SYSCON_BASE (0x40048000) |
| emilmont | 40:976df7c37ad5 | 629 | #define LPC_GPIO_PIN_INT_BASE (0x4004C000) |
| emilmont | 40:976df7c37ad5 | 630 | #define LPC_GPIO_GROUP_INT0_BASE (0x4005C000) |
| emilmont | 40:976df7c37ad5 | 631 | #define LPC_GPIO_GROUP_INT1_BASE (0x40060000) |
| emilmont | 40:976df7c37ad5 | 632 | #define LPC_USB_BASE (0x40080000) |
| emilmont | 40:976df7c37ad5 | 633 | #define LPC_GPIO_BASE (0x50000000) |
| emilmont | 40:976df7c37ad5 | 634 | |
| emilmont | 40:976df7c37ad5 | 635 | |
| emilmont | 40:976df7c37ad5 | 636 | // ------------------------------------------------------------------------------------------------ |
| emilmont | 40:976df7c37ad5 | 637 | // ----- Peripheral declaration ----- |
| emilmont | 40:976df7c37ad5 | 638 | // ------------------------------------------------------------------------------------------------ |
| emilmont | 40:976df7c37ad5 | 639 | |
| emilmont | 40:976df7c37ad5 | 640 | #define LPC_I2C ((LPC_I2C_Type *) LPC_I2C_BASE) |
| emilmont | 40:976df7c37ad5 | 641 | #define LPC_WWDT ((LPC_WWDT_Type *) LPC_WWDT_BASE) |
| emilmont | 40:976df7c37ad5 | 642 | #define LPC_USART ((LPC_USART_Type *) LPC_USART_BASE) |
| emilmont | 40:976df7c37ad5 | 643 | #define LPC_CT16B0 ((LPC_CTxxBx_Type *) LPC_CT16B0_BASE) |
| emilmont | 40:976df7c37ad5 | 644 | #define LPC_CT16B1 ((LPC_CTxxBx_Type *) LPC_CT16B1_BASE) |
| emilmont | 40:976df7c37ad5 | 645 | #define LPC_CT32B0 ((LPC_CTxxBx_Type *) LPC_CT32B0_BASE) |
| emilmont | 40:976df7c37ad5 | 646 | #define LPC_CT32B1 ((LPC_CTxxBx_Type *) LPC_CT32B1_BASE) |
| emilmont | 40:976df7c37ad5 | 647 | #define LPC_ADC ((LPC_ADC_Type *) LPC_ADC_BASE) |
| emilmont | 40:976df7c37ad5 | 648 | #define LPC_PMU ((LPC_PMU_Type *) LPC_PMU_BASE) |
| emilmont | 40:976df7c37ad5 | 649 | #define LPC_FLASHCTRL ((LPC_FLASHCTRL_Type *) LPC_FLASHCTRL_BASE) |
| emilmont | 40:976df7c37ad5 | 650 | #define LPC_SSP0 ((LPC_SSPx_Type *) LPC_SSP0_BASE) |
| emilmont | 40:976df7c37ad5 | 651 | #define LPC_SSP1 ((LPC_SSPx_Type *) LPC_SSP1_BASE) |
| emilmont | 40:976df7c37ad5 | 652 | #define LPC_IOCON ((LPC_IOCON_Type *) LPC_IOCON_BASE) |
| emilmont | 40:976df7c37ad5 | 653 | #define LPC_SYSCON ((LPC_SYSCON_Type *) LPC_SYSCON_BASE) |
| emilmont | 40:976df7c37ad5 | 654 | #define LPC_GPIO_PIN_INT ((LPC_GPIO_PIN_INT_Type *) LPC_GPIO_PIN_INT_BASE) |
| emilmont | 40:976df7c37ad5 | 655 | #define LPC_GPIO_GROUP_INT0 ((LPC_GPIO_GROUP_INTx_Type*) LPC_GPIO_GROUP_INT0_BASE) |
| emilmont | 40:976df7c37ad5 | 656 | #define LPC_GPIO_GROUP_INT1 ((LPC_GPIO_GROUP_INTx_Type*) LPC_GPIO_GROUP_INT1_BASE) |
| emilmont | 40:976df7c37ad5 | 657 | #define LPC_USB ((LPC_USB_Type *) LPC_USB_BASE) |
| emilmont | 40:976df7c37ad5 | 658 | #define LPC_GPIO ((LPC_GPIO_Type *) LPC_GPIO_BASE) |
| emilmont | 40:976df7c37ad5 | 659 | |
| emilmont | 40:976df7c37ad5 | 660 | |
| emilmont | 40:976df7c37ad5 | 661 | /** @} */ /* End of group Device_Peripheral_Registers */ |
| emilmont | 40:976df7c37ad5 | 662 | /** @} */ /* End of group (null) */ |
| emilmont | 40:976df7c37ad5 | 663 | /** @} */ /* End of group LPC11Uxx */ |
| emilmont | 40:976df7c37ad5 | 664 | |
| emilmont | 40:976df7c37ad5 | 665 | #ifdef __cplusplus |
| emilmont | 40:976df7c37ad5 | 666 | } |
| emilmont | 40:976df7c37ad5 | 667 | #endif |
| emilmont | 40:976df7c37ad5 | 668 | |
| emilmont | 40:976df7c37ad5 | 669 | |
| emilmont | 40:976df7c37ad5 | 670 | #endif // __LPC11UXX_H__ |