雄介 太田
mbed(SerialHalfDuplex入り)
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LPC812/core_cmInstr.h@62:7e6c9f46b3bd, 2013-04-17 (annotated)
- Committer:
- emilmont
- Date:
- Wed Apr 17 15:30:58 2013 +0100
- Revision:
- 62:7e6c9f46b3bd
Add NXP LPC812
[KL25Z] Use channel 0 as a prescaler for channel 1
[CodeSourcery] Fix standard library retargeting removing duplicate "_isatty"
Move parse_pins in RPC module
Who changed what in which revision?
| User | Revision | Line number | New contents of line |
|---|---|---|---|
| emilmont | 62:7e6c9f46b3bd | 1 | /**************************************************************************//** |
| emilmont | 62:7e6c9f46b3bd | 2 | * @file core_cmInstr.h |
| emilmont | 62:7e6c9f46b3bd | 3 | * @brief CMSIS Cortex-M Core Instruction Access Header File |
| emilmont | 62:7e6c9f46b3bd | 4 | * @version V3.03 |
| emilmont | 62:7e6c9f46b3bd | 5 | * @date 29. August 2012 |
| emilmont | 62:7e6c9f46b3bd | 6 | * |
| emilmont | 62:7e6c9f46b3bd | 7 | * @note |
| emilmont | 62:7e6c9f46b3bd | 8 | * Copyright (C) 2009-2012 ARM Limited. All rights reserved. |
| emilmont | 62:7e6c9f46b3bd | 9 | * |
| emilmont | 62:7e6c9f46b3bd | 10 | * @par |
| emilmont | 62:7e6c9f46b3bd | 11 | * ARM Limited (ARM) is supplying this software for use with Cortex-M |
| emilmont | 62:7e6c9f46b3bd | 12 | * processor based microcontrollers. This file can be freely distributed |
| emilmont | 62:7e6c9f46b3bd | 13 | * within development tools that are supporting such ARM based processors. |
| emilmont | 62:7e6c9f46b3bd | 14 | * |
| emilmont | 62:7e6c9f46b3bd | 15 | * @par |
| emilmont | 62:7e6c9f46b3bd | 16 | * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED |
| emilmont | 62:7e6c9f46b3bd | 17 | * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF |
| emilmont | 62:7e6c9f46b3bd | 18 | * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. |
| emilmont | 62:7e6c9f46b3bd | 19 | * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR |
| emilmont | 62:7e6c9f46b3bd | 20 | * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. |
| emilmont | 62:7e6c9f46b3bd | 21 | * |
| emilmont | 62:7e6c9f46b3bd | 22 | ******************************************************************************/ |
| emilmont | 62:7e6c9f46b3bd | 23 | |
| emilmont | 62:7e6c9f46b3bd | 24 | #ifndef __CORE_CMINSTR_H |
| emilmont | 62:7e6c9f46b3bd | 25 | #define __CORE_CMINSTR_H |
| emilmont | 62:7e6c9f46b3bd | 26 | |
| emilmont | 62:7e6c9f46b3bd | 27 | |
| emilmont | 62:7e6c9f46b3bd | 28 | /* ########################## Core Instruction Access ######################### */ |
| emilmont | 62:7e6c9f46b3bd | 29 | /** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface |
| emilmont | 62:7e6c9f46b3bd | 30 | Access to dedicated instructions |
| emilmont | 62:7e6c9f46b3bd | 31 | @{ |
| emilmont | 62:7e6c9f46b3bd | 32 | */ |
| emilmont | 62:7e6c9f46b3bd | 33 | |
| emilmont | 62:7e6c9f46b3bd | 34 | #if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/ |
| emilmont | 62:7e6c9f46b3bd | 35 | /* ARM armcc specific functions */ |
| emilmont | 62:7e6c9f46b3bd | 36 | |
| emilmont | 62:7e6c9f46b3bd | 37 | #if (__ARMCC_VERSION < 400677) |
| emilmont | 62:7e6c9f46b3bd | 38 | #error "Please use ARM Compiler Toolchain V4.0.677 or later!" |
| emilmont | 62:7e6c9f46b3bd | 39 | #endif |
| emilmont | 62:7e6c9f46b3bd | 40 | |
| emilmont | 62:7e6c9f46b3bd | 41 | |
| emilmont | 62:7e6c9f46b3bd | 42 | /** \brief No Operation |
| emilmont | 62:7e6c9f46b3bd | 43 | |
| emilmont | 62:7e6c9f46b3bd | 44 | No Operation does nothing. This instruction can be used for code alignment purposes. |
| emilmont | 62:7e6c9f46b3bd | 45 | */ |
| emilmont | 62:7e6c9f46b3bd | 46 | #define __NOP __nop |
| emilmont | 62:7e6c9f46b3bd | 47 | |
| emilmont | 62:7e6c9f46b3bd | 48 | |
| emilmont | 62:7e6c9f46b3bd | 49 | /** \brief Wait For Interrupt |
| emilmont | 62:7e6c9f46b3bd | 50 | |
| emilmont | 62:7e6c9f46b3bd | 51 | Wait For Interrupt is a hint instruction that suspends execution |
| emilmont | 62:7e6c9f46b3bd | 52 | until one of a number of events occurs. |
| emilmont | 62:7e6c9f46b3bd | 53 | */ |
| emilmont | 62:7e6c9f46b3bd | 54 | #define __WFI __wfi |
| emilmont | 62:7e6c9f46b3bd | 55 | |
| emilmont | 62:7e6c9f46b3bd | 56 | |
| emilmont | 62:7e6c9f46b3bd | 57 | /** \brief Wait For Event |
| emilmont | 62:7e6c9f46b3bd | 58 | |
| emilmont | 62:7e6c9f46b3bd | 59 | Wait For Event is a hint instruction that permits the processor to enter |
| emilmont | 62:7e6c9f46b3bd | 60 | a low-power state until one of a number of events occurs. |
| emilmont | 62:7e6c9f46b3bd | 61 | */ |
| emilmont | 62:7e6c9f46b3bd | 62 | #define __WFE __wfe |
| emilmont | 62:7e6c9f46b3bd | 63 | |
| emilmont | 62:7e6c9f46b3bd | 64 | |
| emilmont | 62:7e6c9f46b3bd | 65 | /** \brief Send Event |
| emilmont | 62:7e6c9f46b3bd | 66 | |
| emilmont | 62:7e6c9f46b3bd | 67 | Send Event is a hint instruction. It causes an event to be signaled to the CPU. |
| emilmont | 62:7e6c9f46b3bd | 68 | */ |
| emilmont | 62:7e6c9f46b3bd | 69 | #define __SEV __sev |
| emilmont | 62:7e6c9f46b3bd | 70 | |
| emilmont | 62:7e6c9f46b3bd | 71 | |
| emilmont | 62:7e6c9f46b3bd | 72 | /** \brief Instruction Synchronization Barrier |
| emilmont | 62:7e6c9f46b3bd | 73 | |
| emilmont | 62:7e6c9f46b3bd | 74 | Instruction Synchronization Barrier flushes the pipeline in the processor, |
| emilmont | 62:7e6c9f46b3bd | 75 | so that all instructions following the ISB are fetched from cache or |
| emilmont | 62:7e6c9f46b3bd | 76 | memory, after the instruction has been completed. |
| emilmont | 62:7e6c9f46b3bd | 77 | */ |
| emilmont | 62:7e6c9f46b3bd | 78 | #define __ISB() __isb(0xF) |
| emilmont | 62:7e6c9f46b3bd | 79 | |
| emilmont | 62:7e6c9f46b3bd | 80 | |
| emilmont | 62:7e6c9f46b3bd | 81 | /** \brief Data Synchronization Barrier |
| emilmont | 62:7e6c9f46b3bd | 82 | |
| emilmont | 62:7e6c9f46b3bd | 83 | This function acts as a special kind of Data Memory Barrier. |
| emilmont | 62:7e6c9f46b3bd | 84 | It completes when all explicit memory accesses before this instruction complete. |
| emilmont | 62:7e6c9f46b3bd | 85 | */ |
| emilmont | 62:7e6c9f46b3bd | 86 | #define __DSB() __dsb(0xF) |
| emilmont | 62:7e6c9f46b3bd | 87 | |
| emilmont | 62:7e6c9f46b3bd | 88 | |
| emilmont | 62:7e6c9f46b3bd | 89 | /** \brief Data Memory Barrier |
| emilmont | 62:7e6c9f46b3bd | 90 | |
| emilmont | 62:7e6c9f46b3bd | 91 | This function ensures the apparent order of the explicit memory operations before |
| emilmont | 62:7e6c9f46b3bd | 92 | and after the instruction, without ensuring their completion. |
| emilmont | 62:7e6c9f46b3bd | 93 | */ |
| emilmont | 62:7e6c9f46b3bd | 94 | #define __DMB() __dmb(0xF) |
| emilmont | 62:7e6c9f46b3bd | 95 | |
| emilmont | 62:7e6c9f46b3bd | 96 | |
| emilmont | 62:7e6c9f46b3bd | 97 | /** \brief Reverse byte order (32 bit) |
| emilmont | 62:7e6c9f46b3bd | 98 | |
| emilmont | 62:7e6c9f46b3bd | 99 | This function reverses the byte order in integer value. |
| emilmont | 62:7e6c9f46b3bd | 100 | |
| emilmont | 62:7e6c9f46b3bd | 101 | \param [in] value Value to reverse |
| emilmont | 62:7e6c9f46b3bd | 102 | \return Reversed value |
| emilmont | 62:7e6c9f46b3bd | 103 | */ |
| emilmont | 62:7e6c9f46b3bd | 104 | #define __REV __rev |
| emilmont | 62:7e6c9f46b3bd | 105 | |
| emilmont | 62:7e6c9f46b3bd | 106 | |
| emilmont | 62:7e6c9f46b3bd | 107 | /** \brief Reverse byte order (16 bit) |
| emilmont | 62:7e6c9f46b3bd | 108 | |
| emilmont | 62:7e6c9f46b3bd | 109 | This function reverses the byte order in two unsigned short values. |
| emilmont | 62:7e6c9f46b3bd | 110 | |
| emilmont | 62:7e6c9f46b3bd | 111 | \param [in] value Value to reverse |
| emilmont | 62:7e6c9f46b3bd | 112 | \return Reversed value |
| emilmont | 62:7e6c9f46b3bd | 113 | */ |
| emilmont | 62:7e6c9f46b3bd | 114 | #ifndef __NO_EMBEDDED_ASM |
| emilmont | 62:7e6c9f46b3bd | 115 | __attribute__((section(".rev16_text"))) __STATIC_INLINE __ASM uint32_t __REV16(uint32_t value) |
| emilmont | 62:7e6c9f46b3bd | 116 | { |
| emilmont | 62:7e6c9f46b3bd | 117 | rev16 r0, r0 |
| emilmont | 62:7e6c9f46b3bd | 118 | bx lr |
| emilmont | 62:7e6c9f46b3bd | 119 | } |
| emilmont | 62:7e6c9f46b3bd | 120 | #endif |
| emilmont | 62:7e6c9f46b3bd | 121 | |
| emilmont | 62:7e6c9f46b3bd | 122 | /** \brief Reverse byte order in signed short value |
| emilmont | 62:7e6c9f46b3bd | 123 | |
| emilmont | 62:7e6c9f46b3bd | 124 | This function reverses the byte order in a signed short value with sign extension to integer. |
| emilmont | 62:7e6c9f46b3bd | 125 | |
| emilmont | 62:7e6c9f46b3bd | 126 | \param [in] value Value to reverse |
| emilmont | 62:7e6c9f46b3bd | 127 | \return Reversed value |
| emilmont | 62:7e6c9f46b3bd | 128 | */ |
| emilmont | 62:7e6c9f46b3bd | 129 | #ifndef __NO_EMBEDDED_ASM |
| emilmont | 62:7e6c9f46b3bd | 130 | __attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int32_t __REVSH(int32_t value) |
| emilmont | 62:7e6c9f46b3bd | 131 | { |
| emilmont | 62:7e6c9f46b3bd | 132 | revsh r0, r0 |
| emilmont | 62:7e6c9f46b3bd | 133 | bx lr |
| emilmont | 62:7e6c9f46b3bd | 134 | } |
| emilmont | 62:7e6c9f46b3bd | 135 | #endif |
| emilmont | 62:7e6c9f46b3bd | 136 | |
| emilmont | 62:7e6c9f46b3bd | 137 | |
| emilmont | 62:7e6c9f46b3bd | 138 | /** \brief Rotate Right in unsigned value (32 bit) |
| emilmont | 62:7e6c9f46b3bd | 139 | |
| emilmont | 62:7e6c9f46b3bd | 140 | This function Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. |
| emilmont | 62:7e6c9f46b3bd | 141 | |
| emilmont | 62:7e6c9f46b3bd | 142 | \param [in] value Value to rotate |
| emilmont | 62:7e6c9f46b3bd | 143 | \param [in] value Number of Bits to rotate |
| emilmont | 62:7e6c9f46b3bd | 144 | \return Rotated value |
| emilmont | 62:7e6c9f46b3bd | 145 | */ |
| emilmont | 62:7e6c9f46b3bd | 146 | #define __ROR __ror |
| emilmont | 62:7e6c9f46b3bd | 147 | |
| emilmont | 62:7e6c9f46b3bd | 148 | |
| emilmont | 62:7e6c9f46b3bd | 149 | /** \brief Breakpoint |
| emilmont | 62:7e6c9f46b3bd | 150 | |
| emilmont | 62:7e6c9f46b3bd | 151 | This function causes the processor to enter Debug state. |
| emilmont | 62:7e6c9f46b3bd | 152 | Debug tools can use this to investigate system state when the instruction at a particular address is reached. |
| emilmont | 62:7e6c9f46b3bd | 153 | |
| emilmont | 62:7e6c9f46b3bd | 154 | \param [in] value is ignored by the processor. |
| emilmont | 62:7e6c9f46b3bd | 155 | If required, a debugger can use it to store additional information about the breakpoint. |
| emilmont | 62:7e6c9f46b3bd | 156 | */ |
| emilmont | 62:7e6c9f46b3bd | 157 | #define __BKPT(value) __breakpoint(value) |
| emilmont | 62:7e6c9f46b3bd | 158 | |
| emilmont | 62:7e6c9f46b3bd | 159 | |
| emilmont | 62:7e6c9f46b3bd | 160 | #if (__CORTEX_M >= 0x03) |
| emilmont | 62:7e6c9f46b3bd | 161 | |
| emilmont | 62:7e6c9f46b3bd | 162 | /** \brief Reverse bit order of value |
| emilmont | 62:7e6c9f46b3bd | 163 | |
| emilmont | 62:7e6c9f46b3bd | 164 | This function reverses the bit order of the given value. |
| emilmont | 62:7e6c9f46b3bd | 165 | |
| emilmont | 62:7e6c9f46b3bd | 166 | \param [in] value Value to reverse |
| emilmont | 62:7e6c9f46b3bd | 167 | \return Reversed value |
| emilmont | 62:7e6c9f46b3bd | 168 | */ |
| emilmont | 62:7e6c9f46b3bd | 169 | #define __RBIT __rbit |
| emilmont | 62:7e6c9f46b3bd | 170 | |
| emilmont | 62:7e6c9f46b3bd | 171 | |
| emilmont | 62:7e6c9f46b3bd | 172 | /** \brief LDR Exclusive (8 bit) |
| emilmont | 62:7e6c9f46b3bd | 173 | |
| emilmont | 62:7e6c9f46b3bd | 174 | This function performs a exclusive LDR command for 8 bit value. |
| emilmont | 62:7e6c9f46b3bd | 175 | |
| emilmont | 62:7e6c9f46b3bd | 176 | \param [in] ptr Pointer to data |
| emilmont | 62:7e6c9f46b3bd | 177 | \return value of type uint8_t at (*ptr) |
| emilmont | 62:7e6c9f46b3bd | 178 | */ |
| emilmont | 62:7e6c9f46b3bd | 179 | #define __LDREXB(ptr) ((uint8_t ) __ldrex(ptr)) |
| emilmont | 62:7e6c9f46b3bd | 180 | |
| emilmont | 62:7e6c9f46b3bd | 181 | |
| emilmont | 62:7e6c9f46b3bd | 182 | /** \brief LDR Exclusive (16 bit) |
| emilmont | 62:7e6c9f46b3bd | 183 | |
| emilmont | 62:7e6c9f46b3bd | 184 | This function performs a exclusive LDR command for 16 bit values. |
| emilmont | 62:7e6c9f46b3bd | 185 | |
| emilmont | 62:7e6c9f46b3bd | 186 | \param [in] ptr Pointer to data |
| emilmont | 62:7e6c9f46b3bd | 187 | \return value of type uint16_t at (*ptr) |
| emilmont | 62:7e6c9f46b3bd | 188 | */ |
| emilmont | 62:7e6c9f46b3bd | 189 | #define __LDREXH(ptr) ((uint16_t) __ldrex(ptr)) |
| emilmont | 62:7e6c9f46b3bd | 190 | |
| emilmont | 62:7e6c9f46b3bd | 191 | |
| emilmont | 62:7e6c9f46b3bd | 192 | /** \brief LDR Exclusive (32 bit) |
| emilmont | 62:7e6c9f46b3bd | 193 | |
| emilmont | 62:7e6c9f46b3bd | 194 | This function performs a exclusive LDR command for 32 bit values. |
| emilmont | 62:7e6c9f46b3bd | 195 | |
| emilmont | 62:7e6c9f46b3bd | 196 | \param [in] ptr Pointer to data |
| emilmont | 62:7e6c9f46b3bd | 197 | \return value of type uint32_t at (*ptr) |
| emilmont | 62:7e6c9f46b3bd | 198 | */ |
| emilmont | 62:7e6c9f46b3bd | 199 | #define __LDREXW(ptr) ((uint32_t ) __ldrex(ptr)) |
| emilmont | 62:7e6c9f46b3bd | 200 | |
| emilmont | 62:7e6c9f46b3bd | 201 | |
| emilmont | 62:7e6c9f46b3bd | 202 | /** \brief STR Exclusive (8 bit) |
| emilmont | 62:7e6c9f46b3bd | 203 | |
| emilmont | 62:7e6c9f46b3bd | 204 | This function performs a exclusive STR command for 8 bit values. |
| emilmont | 62:7e6c9f46b3bd | 205 | |
| emilmont | 62:7e6c9f46b3bd | 206 | \param [in] value Value to store |
| emilmont | 62:7e6c9f46b3bd | 207 | \param [in] ptr Pointer to location |
| emilmont | 62:7e6c9f46b3bd | 208 | \return 0 Function succeeded |
| emilmont | 62:7e6c9f46b3bd | 209 | \return 1 Function failed |
| emilmont | 62:7e6c9f46b3bd | 210 | */ |
| emilmont | 62:7e6c9f46b3bd | 211 | #define __STREXB(value, ptr) __strex(value, ptr) |
| emilmont | 62:7e6c9f46b3bd | 212 | |
| emilmont | 62:7e6c9f46b3bd | 213 | |
| emilmont | 62:7e6c9f46b3bd | 214 | /** \brief STR Exclusive (16 bit) |
| emilmont | 62:7e6c9f46b3bd | 215 | |
| emilmont | 62:7e6c9f46b3bd | 216 | This function performs a exclusive STR command for 16 bit values. |
| emilmont | 62:7e6c9f46b3bd | 217 | |
| emilmont | 62:7e6c9f46b3bd | 218 | \param [in] value Value to store |
| emilmont | 62:7e6c9f46b3bd | 219 | \param [in] ptr Pointer to location |
| emilmont | 62:7e6c9f46b3bd | 220 | \return 0 Function succeeded |
| emilmont | 62:7e6c9f46b3bd | 221 | \return 1 Function failed |
| emilmont | 62:7e6c9f46b3bd | 222 | */ |
| emilmont | 62:7e6c9f46b3bd | 223 | #define __STREXH(value, ptr) __strex(value, ptr) |
| emilmont | 62:7e6c9f46b3bd | 224 | |
| emilmont | 62:7e6c9f46b3bd | 225 | |
| emilmont | 62:7e6c9f46b3bd | 226 | /** \brief STR Exclusive (32 bit) |
| emilmont | 62:7e6c9f46b3bd | 227 | |
| emilmont | 62:7e6c9f46b3bd | 228 | This function performs a exclusive STR command for 32 bit values. |
| emilmont | 62:7e6c9f46b3bd | 229 | |
| emilmont | 62:7e6c9f46b3bd | 230 | \param [in] value Value to store |
| emilmont | 62:7e6c9f46b3bd | 231 | \param [in] ptr Pointer to location |
| emilmont | 62:7e6c9f46b3bd | 232 | \return 0 Function succeeded |
| emilmont | 62:7e6c9f46b3bd | 233 | \return 1 Function failed |
| emilmont | 62:7e6c9f46b3bd | 234 | */ |
| emilmont | 62:7e6c9f46b3bd | 235 | #define __STREXW(value, ptr) __strex(value, ptr) |
| emilmont | 62:7e6c9f46b3bd | 236 | |
| emilmont | 62:7e6c9f46b3bd | 237 | |
| emilmont | 62:7e6c9f46b3bd | 238 | /** \brief Remove the exclusive lock |
| emilmont | 62:7e6c9f46b3bd | 239 | |
| emilmont | 62:7e6c9f46b3bd | 240 | This function removes the exclusive lock which is created by LDREX. |
| emilmont | 62:7e6c9f46b3bd | 241 | |
| emilmont | 62:7e6c9f46b3bd | 242 | */ |
| emilmont | 62:7e6c9f46b3bd | 243 | #define __CLREX __clrex |
| emilmont | 62:7e6c9f46b3bd | 244 | |
| emilmont | 62:7e6c9f46b3bd | 245 | |
| emilmont | 62:7e6c9f46b3bd | 246 | /** \brief Signed Saturate |
| emilmont | 62:7e6c9f46b3bd | 247 | |
| emilmont | 62:7e6c9f46b3bd | 248 | This function saturates a signed value. |
| emilmont | 62:7e6c9f46b3bd | 249 | |
| emilmont | 62:7e6c9f46b3bd | 250 | \param [in] value Value to be saturated |
| emilmont | 62:7e6c9f46b3bd | 251 | \param [in] sat Bit position to saturate to (1..32) |
| emilmont | 62:7e6c9f46b3bd | 252 | \return Saturated value |
| emilmont | 62:7e6c9f46b3bd | 253 | */ |
| emilmont | 62:7e6c9f46b3bd | 254 | #define __SSAT __ssat |
| emilmont | 62:7e6c9f46b3bd | 255 | |
| emilmont | 62:7e6c9f46b3bd | 256 | |
| emilmont | 62:7e6c9f46b3bd | 257 | /** \brief Unsigned Saturate |
| emilmont | 62:7e6c9f46b3bd | 258 | |
| emilmont | 62:7e6c9f46b3bd | 259 | This function saturates an unsigned value. |
| emilmont | 62:7e6c9f46b3bd | 260 | |
| emilmont | 62:7e6c9f46b3bd | 261 | \param [in] value Value to be saturated |
| emilmont | 62:7e6c9f46b3bd | 262 | \param [in] sat Bit position to saturate to (0..31) |
| emilmont | 62:7e6c9f46b3bd | 263 | \return Saturated value |
| emilmont | 62:7e6c9f46b3bd | 264 | */ |
| emilmont | 62:7e6c9f46b3bd | 265 | #define __USAT __usat |
| emilmont | 62:7e6c9f46b3bd | 266 | |
| emilmont | 62:7e6c9f46b3bd | 267 | |
| emilmont | 62:7e6c9f46b3bd | 268 | /** \brief Count leading zeros |
| emilmont | 62:7e6c9f46b3bd | 269 | |
| emilmont | 62:7e6c9f46b3bd | 270 | This function counts the number of leading zeros of a data value. |
| emilmont | 62:7e6c9f46b3bd | 271 | |
| emilmont | 62:7e6c9f46b3bd | 272 | \param [in] value Value to count the leading zeros |
| emilmont | 62:7e6c9f46b3bd | 273 | \return number of leading zeros in value |
| emilmont | 62:7e6c9f46b3bd | 274 | */ |
| emilmont | 62:7e6c9f46b3bd | 275 | #define __CLZ __clz |
| emilmont | 62:7e6c9f46b3bd | 276 | |
| emilmont | 62:7e6c9f46b3bd | 277 | #endif /* (__CORTEX_M >= 0x03) */ |
| emilmont | 62:7e6c9f46b3bd | 278 | |
| emilmont | 62:7e6c9f46b3bd | 279 | |
| emilmont | 62:7e6c9f46b3bd | 280 | |
| emilmont | 62:7e6c9f46b3bd | 281 | #elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/ |
| emilmont | 62:7e6c9f46b3bd | 282 | /* IAR iccarm specific functions */ |
| emilmont | 62:7e6c9f46b3bd | 283 | |
| emilmont | 62:7e6c9f46b3bd | 284 | #include <cmsis_iar.h> |
| emilmont | 62:7e6c9f46b3bd | 285 | |
| emilmont | 62:7e6c9f46b3bd | 286 | |
| emilmont | 62:7e6c9f46b3bd | 287 | #elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/ |
| emilmont | 62:7e6c9f46b3bd | 288 | /* TI CCS specific functions */ |
| emilmont | 62:7e6c9f46b3bd | 289 | |
| emilmont | 62:7e6c9f46b3bd | 290 | #include <cmsis_ccs.h> |
| emilmont | 62:7e6c9f46b3bd | 291 | |
| emilmont | 62:7e6c9f46b3bd | 292 | |
| emilmont | 62:7e6c9f46b3bd | 293 | #elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/ |
| emilmont | 62:7e6c9f46b3bd | 294 | /* GNU gcc specific functions */ |
| emilmont | 62:7e6c9f46b3bd | 295 | |
| emilmont | 62:7e6c9f46b3bd | 296 | /** \brief No Operation |
| emilmont | 62:7e6c9f46b3bd | 297 | |
| emilmont | 62:7e6c9f46b3bd | 298 | No Operation does nothing. This instruction can be used for code alignment purposes. |
| emilmont | 62:7e6c9f46b3bd | 299 | */ |
| emilmont | 62:7e6c9f46b3bd | 300 | __attribute__( ( always_inline ) ) __STATIC_INLINE void __NOP(void) |
| emilmont | 62:7e6c9f46b3bd | 301 | { |
| emilmont | 62:7e6c9f46b3bd | 302 | __ASM volatile ("nop"); |
| emilmont | 62:7e6c9f46b3bd | 303 | } |
| emilmont | 62:7e6c9f46b3bd | 304 | |
| emilmont | 62:7e6c9f46b3bd | 305 | |
| emilmont | 62:7e6c9f46b3bd | 306 | /** \brief Wait For Interrupt |
| emilmont | 62:7e6c9f46b3bd | 307 | |
| emilmont | 62:7e6c9f46b3bd | 308 | Wait For Interrupt is a hint instruction that suspends execution |
| emilmont | 62:7e6c9f46b3bd | 309 | until one of a number of events occurs. |
| emilmont | 62:7e6c9f46b3bd | 310 | */ |
| emilmont | 62:7e6c9f46b3bd | 311 | __attribute__( ( always_inline ) ) __STATIC_INLINE void __WFI(void) |
| emilmont | 62:7e6c9f46b3bd | 312 | { |
| emilmont | 62:7e6c9f46b3bd | 313 | __ASM volatile ("wfi"); |
| emilmont | 62:7e6c9f46b3bd | 314 | } |
| emilmont | 62:7e6c9f46b3bd | 315 | |
| emilmont | 62:7e6c9f46b3bd | 316 | |
| emilmont | 62:7e6c9f46b3bd | 317 | /** \brief Wait For Event |
| emilmont | 62:7e6c9f46b3bd | 318 | |
| emilmont | 62:7e6c9f46b3bd | 319 | Wait For Event is a hint instruction that permits the processor to enter |
| emilmont | 62:7e6c9f46b3bd | 320 | a low-power state until one of a number of events occurs. |
| emilmont | 62:7e6c9f46b3bd | 321 | */ |
| emilmont | 62:7e6c9f46b3bd | 322 | __attribute__( ( always_inline ) ) __STATIC_INLINE void __WFE(void) |
| emilmont | 62:7e6c9f46b3bd | 323 | { |
| emilmont | 62:7e6c9f46b3bd | 324 | __ASM volatile ("wfe"); |
| emilmont | 62:7e6c9f46b3bd | 325 | } |
| emilmont | 62:7e6c9f46b3bd | 326 | |
| emilmont | 62:7e6c9f46b3bd | 327 | |
| emilmont | 62:7e6c9f46b3bd | 328 | /** \brief Send Event |
| emilmont | 62:7e6c9f46b3bd | 329 | |
| emilmont | 62:7e6c9f46b3bd | 330 | Send Event is a hint instruction. It causes an event to be signaled to the CPU. |
| emilmont | 62:7e6c9f46b3bd | 331 | */ |
| emilmont | 62:7e6c9f46b3bd | 332 | __attribute__( ( always_inline ) ) __STATIC_INLINE void __SEV(void) |
| emilmont | 62:7e6c9f46b3bd | 333 | { |
| emilmont | 62:7e6c9f46b3bd | 334 | __ASM volatile ("sev"); |
| emilmont | 62:7e6c9f46b3bd | 335 | } |
| emilmont | 62:7e6c9f46b3bd | 336 | |
| emilmont | 62:7e6c9f46b3bd | 337 | |
| emilmont | 62:7e6c9f46b3bd | 338 | /** \brief Instruction Synchronization Barrier |
| emilmont | 62:7e6c9f46b3bd | 339 | |
| emilmont | 62:7e6c9f46b3bd | 340 | Instruction Synchronization Barrier flushes the pipeline in the processor, |
| emilmont | 62:7e6c9f46b3bd | 341 | so that all instructions following the ISB are fetched from cache or |
| emilmont | 62:7e6c9f46b3bd | 342 | memory, after the instruction has been completed. |
| emilmont | 62:7e6c9f46b3bd | 343 | */ |
| emilmont | 62:7e6c9f46b3bd | 344 | __attribute__( ( always_inline ) ) __STATIC_INLINE void __ISB(void) |
| emilmont | 62:7e6c9f46b3bd | 345 | { |
| emilmont | 62:7e6c9f46b3bd | 346 | __ASM volatile ("isb"); |
| emilmont | 62:7e6c9f46b3bd | 347 | } |
| emilmont | 62:7e6c9f46b3bd | 348 | |
| emilmont | 62:7e6c9f46b3bd | 349 | |
| emilmont | 62:7e6c9f46b3bd | 350 | /** \brief Data Synchronization Barrier |
| emilmont | 62:7e6c9f46b3bd | 351 | |
| emilmont | 62:7e6c9f46b3bd | 352 | This function acts as a special kind of Data Memory Barrier. |
| emilmont | 62:7e6c9f46b3bd | 353 | It completes when all explicit memory accesses before this instruction complete. |
| emilmont | 62:7e6c9f46b3bd | 354 | */ |
| emilmont | 62:7e6c9f46b3bd | 355 | __attribute__( ( always_inline ) ) __STATIC_INLINE void __DSB(void) |
| emilmont | 62:7e6c9f46b3bd | 356 | { |
| emilmont | 62:7e6c9f46b3bd | 357 | __ASM volatile ("dsb"); |
| emilmont | 62:7e6c9f46b3bd | 358 | } |
| emilmont | 62:7e6c9f46b3bd | 359 | |
| emilmont | 62:7e6c9f46b3bd | 360 | |
| emilmont | 62:7e6c9f46b3bd | 361 | /** \brief Data Memory Barrier |
| emilmont | 62:7e6c9f46b3bd | 362 | |
| emilmont | 62:7e6c9f46b3bd | 363 | This function ensures the apparent order of the explicit memory operations before |
| emilmont | 62:7e6c9f46b3bd | 364 | and after the instruction, without ensuring their completion. |
| emilmont | 62:7e6c9f46b3bd | 365 | */ |
| emilmont | 62:7e6c9f46b3bd | 366 | __attribute__( ( always_inline ) ) __STATIC_INLINE void __DMB(void) |
| emilmont | 62:7e6c9f46b3bd | 367 | { |
| emilmont | 62:7e6c9f46b3bd | 368 | __ASM volatile ("dmb"); |
| emilmont | 62:7e6c9f46b3bd | 369 | } |
| emilmont | 62:7e6c9f46b3bd | 370 | |
| emilmont | 62:7e6c9f46b3bd | 371 | |
| emilmont | 62:7e6c9f46b3bd | 372 | /** \brief Reverse byte order (32 bit) |
| emilmont | 62:7e6c9f46b3bd | 373 | |
| emilmont | 62:7e6c9f46b3bd | 374 | This function reverses the byte order in integer value. |
| emilmont | 62:7e6c9f46b3bd | 375 | |
| emilmont | 62:7e6c9f46b3bd | 376 | \param [in] value Value to reverse |
| emilmont | 62:7e6c9f46b3bd | 377 | \return Reversed value |
| emilmont | 62:7e6c9f46b3bd | 378 | */ |
| emilmont | 62:7e6c9f46b3bd | 379 | __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __REV(uint32_t value) |
| emilmont | 62:7e6c9f46b3bd | 380 | { |
| emilmont | 62:7e6c9f46b3bd | 381 | uint32_t result; |
| emilmont | 62:7e6c9f46b3bd | 382 | |
| emilmont | 62:7e6c9f46b3bd | 383 | __ASM volatile ("rev %0, %1" : "=r" (result) : "r" (value) ); |
| emilmont | 62:7e6c9f46b3bd | 384 | return(result); |
| emilmont | 62:7e6c9f46b3bd | 385 | } |
| emilmont | 62:7e6c9f46b3bd | 386 | |
| emilmont | 62:7e6c9f46b3bd | 387 | |
| emilmont | 62:7e6c9f46b3bd | 388 | /** \brief Reverse byte order (16 bit) |
| emilmont | 62:7e6c9f46b3bd | 389 | |
| emilmont | 62:7e6c9f46b3bd | 390 | This function reverses the byte order in two unsigned short values. |
| emilmont | 62:7e6c9f46b3bd | 391 | |
| emilmont | 62:7e6c9f46b3bd | 392 | \param [in] value Value to reverse |
| emilmont | 62:7e6c9f46b3bd | 393 | \return Reversed value |
| emilmont | 62:7e6c9f46b3bd | 394 | */ |
| emilmont | 62:7e6c9f46b3bd | 395 | __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __REV16(uint32_t value) |
| emilmont | 62:7e6c9f46b3bd | 396 | { |
| emilmont | 62:7e6c9f46b3bd | 397 | uint32_t result; |
| emilmont | 62:7e6c9f46b3bd | 398 | |
| emilmont | 62:7e6c9f46b3bd | 399 | __ASM volatile ("rev16 %0, %1" : "=r" (result) : "r" (value) ); |
| emilmont | 62:7e6c9f46b3bd | 400 | return(result); |
| emilmont | 62:7e6c9f46b3bd | 401 | } |
| emilmont | 62:7e6c9f46b3bd | 402 | |
| emilmont | 62:7e6c9f46b3bd | 403 | |
| emilmont | 62:7e6c9f46b3bd | 404 | /** \brief Reverse byte order in signed short value |
| emilmont | 62:7e6c9f46b3bd | 405 | |
| emilmont | 62:7e6c9f46b3bd | 406 | This function reverses the byte order in a signed short value with sign extension to integer. |
| emilmont | 62:7e6c9f46b3bd | 407 | |
| emilmont | 62:7e6c9f46b3bd | 408 | \param [in] value Value to reverse |
| emilmont | 62:7e6c9f46b3bd | 409 | \return Reversed value |
| emilmont | 62:7e6c9f46b3bd | 410 | */ |
| emilmont | 62:7e6c9f46b3bd | 411 | __attribute__( ( always_inline ) ) __STATIC_INLINE int32_t __REVSH(int32_t value) |
| emilmont | 62:7e6c9f46b3bd | 412 | { |
| emilmont | 62:7e6c9f46b3bd | 413 | uint32_t result; |
| emilmont | 62:7e6c9f46b3bd | 414 | |
| emilmont | 62:7e6c9f46b3bd | 415 | __ASM volatile ("revsh %0, %1" : "=r" (result) : "r" (value) ); |
| emilmont | 62:7e6c9f46b3bd | 416 | return(result); |
| emilmont | 62:7e6c9f46b3bd | 417 | } |
| emilmont | 62:7e6c9f46b3bd | 418 | |
| emilmont | 62:7e6c9f46b3bd | 419 | |
| emilmont | 62:7e6c9f46b3bd | 420 | /** \brief Rotate Right in unsigned value (32 bit) |
| emilmont | 62:7e6c9f46b3bd | 421 | |
| emilmont | 62:7e6c9f46b3bd | 422 | This function Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. |
| emilmont | 62:7e6c9f46b3bd | 423 | |
| emilmont | 62:7e6c9f46b3bd | 424 | \param [in] value Value to rotate |
| emilmont | 62:7e6c9f46b3bd | 425 | \param [in] value Number of Bits to rotate |
| emilmont | 62:7e6c9f46b3bd | 426 | \return Rotated value |
| emilmont | 62:7e6c9f46b3bd | 427 | */ |
| emilmont | 62:7e6c9f46b3bd | 428 | __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __ROR(uint32_t op1, uint32_t op2) |
| emilmont | 62:7e6c9f46b3bd | 429 | { |
| emilmont | 62:7e6c9f46b3bd | 430 | |
| emilmont | 62:7e6c9f46b3bd | 431 | __ASM volatile ("ror %0, %0, %1" : "+r" (op1) : "r" (op2) ); |
| emilmont | 62:7e6c9f46b3bd | 432 | return(op1); |
| emilmont | 62:7e6c9f46b3bd | 433 | } |
| emilmont | 62:7e6c9f46b3bd | 434 | |
| emilmont | 62:7e6c9f46b3bd | 435 | |
| emilmont | 62:7e6c9f46b3bd | 436 | /** \brief Breakpoint |
| emilmont | 62:7e6c9f46b3bd | 437 | |
| emilmont | 62:7e6c9f46b3bd | 438 | This function causes the processor to enter Debug state. |
| emilmont | 62:7e6c9f46b3bd | 439 | Debug tools can use this to investigate system state when the instruction at a particular address is reached. |
| emilmont | 62:7e6c9f46b3bd | 440 | |
| emilmont | 62:7e6c9f46b3bd | 441 | \param [in] value is ignored by the processor. |
| emilmont | 62:7e6c9f46b3bd | 442 | If required, a debugger can use it to store additional information about the breakpoint. |
| emilmont | 62:7e6c9f46b3bd | 443 | */ |
| emilmont | 62:7e6c9f46b3bd | 444 | #define __BKPT(value) __ASM volatile ("bkpt "#value) |
| emilmont | 62:7e6c9f46b3bd | 445 | |
| emilmont | 62:7e6c9f46b3bd | 446 | |
| emilmont | 62:7e6c9f46b3bd | 447 | #if (__CORTEX_M >= 0x03) |
| emilmont | 62:7e6c9f46b3bd | 448 | |
| emilmont | 62:7e6c9f46b3bd | 449 | /** \brief Reverse bit order of value |
| emilmont | 62:7e6c9f46b3bd | 450 | |
| emilmont | 62:7e6c9f46b3bd | 451 | This function reverses the bit order of the given value. |
| emilmont | 62:7e6c9f46b3bd | 452 | |
| emilmont | 62:7e6c9f46b3bd | 453 | \param [in] value Value to reverse |
| emilmont | 62:7e6c9f46b3bd | 454 | \return Reversed value |
| emilmont | 62:7e6c9f46b3bd | 455 | */ |
| emilmont | 62:7e6c9f46b3bd | 456 | __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __RBIT(uint32_t value) |
| emilmont | 62:7e6c9f46b3bd | 457 | { |
| emilmont | 62:7e6c9f46b3bd | 458 | uint32_t result; |
| emilmont | 62:7e6c9f46b3bd | 459 | |
| emilmont | 62:7e6c9f46b3bd | 460 | __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); |
| emilmont | 62:7e6c9f46b3bd | 461 | return(result); |
| emilmont | 62:7e6c9f46b3bd | 462 | } |
| emilmont | 62:7e6c9f46b3bd | 463 | |
| emilmont | 62:7e6c9f46b3bd | 464 | |
| emilmont | 62:7e6c9f46b3bd | 465 | /** \brief LDR Exclusive (8 bit) |
| emilmont | 62:7e6c9f46b3bd | 466 | |
| emilmont | 62:7e6c9f46b3bd | 467 | This function performs a exclusive LDR command for 8 bit value. |
| emilmont | 62:7e6c9f46b3bd | 468 | |
| emilmont | 62:7e6c9f46b3bd | 469 | \param [in] ptr Pointer to data |
| emilmont | 62:7e6c9f46b3bd | 470 | \return value of type uint8_t at (*ptr) |
| emilmont | 62:7e6c9f46b3bd | 471 | */ |
| emilmont | 62:7e6c9f46b3bd | 472 | __attribute__( ( always_inline ) ) __STATIC_INLINE uint8_t __LDREXB(volatile uint8_t *addr) |
| emilmont | 62:7e6c9f46b3bd | 473 | { |
| emilmont | 62:7e6c9f46b3bd | 474 | uint8_t result; |
| emilmont | 62:7e6c9f46b3bd | 475 | |
| emilmont | 62:7e6c9f46b3bd | 476 | __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) ); |
| emilmont | 62:7e6c9f46b3bd | 477 | return(result); |
| emilmont | 62:7e6c9f46b3bd | 478 | } |
| emilmont | 62:7e6c9f46b3bd | 479 | |
| emilmont | 62:7e6c9f46b3bd | 480 | |
| emilmont | 62:7e6c9f46b3bd | 481 | /** \brief LDR Exclusive (16 bit) |
| emilmont | 62:7e6c9f46b3bd | 482 | |
| emilmont | 62:7e6c9f46b3bd | 483 | This function performs a exclusive LDR command for 16 bit values. |
| emilmont | 62:7e6c9f46b3bd | 484 | |
| emilmont | 62:7e6c9f46b3bd | 485 | \param [in] ptr Pointer to data |
| emilmont | 62:7e6c9f46b3bd | 486 | \return value of type uint16_t at (*ptr) |
| emilmont | 62:7e6c9f46b3bd | 487 | */ |
| emilmont | 62:7e6c9f46b3bd | 488 | __attribute__( ( always_inline ) ) __STATIC_INLINE uint16_t __LDREXH(volatile uint16_t *addr) |
| emilmont | 62:7e6c9f46b3bd | 489 | { |
| emilmont | 62:7e6c9f46b3bd | 490 | uint16_t result; |
| emilmont | 62:7e6c9f46b3bd | 491 | |
| emilmont | 62:7e6c9f46b3bd | 492 | __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) ); |
| emilmont | 62:7e6c9f46b3bd | 493 | return(result); |
| emilmont | 62:7e6c9f46b3bd | 494 | } |
| emilmont | 62:7e6c9f46b3bd | 495 | |
| emilmont | 62:7e6c9f46b3bd | 496 | |
| emilmont | 62:7e6c9f46b3bd | 497 | /** \brief LDR Exclusive (32 bit) |
| emilmont | 62:7e6c9f46b3bd | 498 | |
| emilmont | 62:7e6c9f46b3bd | 499 | This function performs a exclusive LDR command for 32 bit values. |
| emilmont | 62:7e6c9f46b3bd | 500 | |
| emilmont | 62:7e6c9f46b3bd | 501 | \param [in] ptr Pointer to data |
| emilmont | 62:7e6c9f46b3bd | 502 | \return value of type uint32_t at (*ptr) |
| emilmont | 62:7e6c9f46b3bd | 503 | */ |
| emilmont | 62:7e6c9f46b3bd | 504 | __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __LDREXW(volatile uint32_t *addr) |
| emilmont | 62:7e6c9f46b3bd | 505 | { |
| emilmont | 62:7e6c9f46b3bd | 506 | uint32_t result; |
| emilmont | 62:7e6c9f46b3bd | 507 | |
| emilmont | 62:7e6c9f46b3bd | 508 | __ASM volatile ("ldrex %0, [%1]" : "=r" (result) : "r" (addr) ); |
| emilmont | 62:7e6c9f46b3bd | 509 | return(result); |
| emilmont | 62:7e6c9f46b3bd | 510 | } |
| emilmont | 62:7e6c9f46b3bd | 511 | |
| emilmont | 62:7e6c9f46b3bd | 512 | |
| emilmont | 62:7e6c9f46b3bd | 513 | /** \brief STR Exclusive (8 bit) |
| emilmont | 62:7e6c9f46b3bd | 514 | |
| emilmont | 62:7e6c9f46b3bd | 515 | This function performs a exclusive STR command for 8 bit values. |
| emilmont | 62:7e6c9f46b3bd | 516 | |
| emilmont | 62:7e6c9f46b3bd | 517 | \param [in] value Value to store |
| emilmont | 62:7e6c9f46b3bd | 518 | \param [in] ptr Pointer to location |
| emilmont | 62:7e6c9f46b3bd | 519 | \return 0 Function succeeded |
| emilmont | 62:7e6c9f46b3bd | 520 | \return 1 Function failed |
| emilmont | 62:7e6c9f46b3bd | 521 | */ |
| emilmont | 62:7e6c9f46b3bd | 522 | __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr) |
| emilmont | 62:7e6c9f46b3bd | 523 | { |
| emilmont | 62:7e6c9f46b3bd | 524 | uint32_t result; |
| emilmont | 62:7e6c9f46b3bd | 525 | |
| emilmont | 62:7e6c9f46b3bd | 526 | __ASM volatile ("strexb %0, %2, [%1]" : "=&r" (result) : "r" (addr), "r" (value) ); |
| emilmont | 62:7e6c9f46b3bd | 527 | return(result); |
| emilmont | 62:7e6c9f46b3bd | 528 | } |
| emilmont | 62:7e6c9f46b3bd | 529 | |
| emilmont | 62:7e6c9f46b3bd | 530 | |
| emilmont | 62:7e6c9f46b3bd | 531 | /** \brief STR Exclusive (16 bit) |
| emilmont | 62:7e6c9f46b3bd | 532 | |
| emilmont | 62:7e6c9f46b3bd | 533 | This function performs a exclusive STR command for 16 bit values. |
| emilmont | 62:7e6c9f46b3bd | 534 | |
| emilmont | 62:7e6c9f46b3bd | 535 | \param [in] value Value to store |
| emilmont | 62:7e6c9f46b3bd | 536 | \param [in] ptr Pointer to location |
| emilmont | 62:7e6c9f46b3bd | 537 | \return 0 Function succeeded |
| emilmont | 62:7e6c9f46b3bd | 538 | \return 1 Function failed |
| emilmont | 62:7e6c9f46b3bd | 539 | */ |
| emilmont | 62:7e6c9f46b3bd | 540 | __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr) |
| emilmont | 62:7e6c9f46b3bd | 541 | { |
| emilmont | 62:7e6c9f46b3bd | 542 | uint32_t result; |
| emilmont | 62:7e6c9f46b3bd | 543 | |
| emilmont | 62:7e6c9f46b3bd | 544 | __ASM volatile ("strexh %0, %2, [%1]" : "=&r" (result) : "r" (addr), "r" (value) ); |
| emilmont | 62:7e6c9f46b3bd | 545 | return(result); |
| emilmont | 62:7e6c9f46b3bd | 546 | } |
| emilmont | 62:7e6c9f46b3bd | 547 | |
| emilmont | 62:7e6c9f46b3bd | 548 | |
| emilmont | 62:7e6c9f46b3bd | 549 | /** \brief STR Exclusive (32 bit) |
| emilmont | 62:7e6c9f46b3bd | 550 | |
| emilmont | 62:7e6c9f46b3bd | 551 | This function performs a exclusive STR command for 32 bit values. |
| emilmont | 62:7e6c9f46b3bd | 552 | |
| emilmont | 62:7e6c9f46b3bd | 553 | \param [in] value Value to store |
| emilmont | 62:7e6c9f46b3bd | 554 | \param [in] ptr Pointer to location |
| emilmont | 62:7e6c9f46b3bd | 555 | \return 0 Function succeeded |
| emilmont | 62:7e6c9f46b3bd | 556 | \return 1 Function failed |
| emilmont | 62:7e6c9f46b3bd | 557 | */ |
| emilmont | 62:7e6c9f46b3bd | 558 | __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr) |
| emilmont | 62:7e6c9f46b3bd | 559 | { |
| emilmont | 62:7e6c9f46b3bd | 560 | uint32_t result; |
| emilmont | 62:7e6c9f46b3bd | 561 | |
| emilmont | 62:7e6c9f46b3bd | 562 | __ASM volatile ("strex %0, %2, [%1]" : "=&r" (result) : "r" (addr), "r" (value) ); |
| emilmont | 62:7e6c9f46b3bd | 563 | return(result); |
| emilmont | 62:7e6c9f46b3bd | 564 | } |
| emilmont | 62:7e6c9f46b3bd | 565 | |
| emilmont | 62:7e6c9f46b3bd | 566 | |
| emilmont | 62:7e6c9f46b3bd | 567 | /** \brief Remove the exclusive lock |
| emilmont | 62:7e6c9f46b3bd | 568 | |
| emilmont | 62:7e6c9f46b3bd | 569 | This function removes the exclusive lock which is created by LDREX. |
| emilmont | 62:7e6c9f46b3bd | 570 | |
| emilmont | 62:7e6c9f46b3bd | 571 | */ |
| emilmont | 62:7e6c9f46b3bd | 572 | __attribute__( ( always_inline ) ) __STATIC_INLINE void __CLREX(void) |
| emilmont | 62:7e6c9f46b3bd | 573 | { |
| emilmont | 62:7e6c9f46b3bd | 574 | __ASM volatile ("clrex"); |
| emilmont | 62:7e6c9f46b3bd | 575 | } |
| emilmont | 62:7e6c9f46b3bd | 576 | |
| emilmont | 62:7e6c9f46b3bd | 577 | |
| emilmont | 62:7e6c9f46b3bd | 578 | /** \brief Signed Saturate |
| emilmont | 62:7e6c9f46b3bd | 579 | |
| emilmont | 62:7e6c9f46b3bd | 580 | This function saturates a signed value. |
| emilmont | 62:7e6c9f46b3bd | 581 | |
| emilmont | 62:7e6c9f46b3bd | 582 | \param [in] value Value to be saturated |
| emilmont | 62:7e6c9f46b3bd | 583 | \param [in] sat Bit position to saturate to (1..32) |
| emilmont | 62:7e6c9f46b3bd | 584 | \return Saturated value |
| emilmont | 62:7e6c9f46b3bd | 585 | */ |
| emilmont | 62:7e6c9f46b3bd | 586 | #define __SSAT(ARG1,ARG2) \ |
| emilmont | 62:7e6c9f46b3bd | 587 | ({ \ |
| emilmont | 62:7e6c9f46b3bd | 588 | uint32_t __RES, __ARG1 = (ARG1); \ |
| emilmont | 62:7e6c9f46b3bd | 589 | __ASM ("ssat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ |
| emilmont | 62:7e6c9f46b3bd | 590 | __RES; \ |
| emilmont | 62:7e6c9f46b3bd | 591 | }) |
| emilmont | 62:7e6c9f46b3bd | 592 | |
| emilmont | 62:7e6c9f46b3bd | 593 | |
| emilmont | 62:7e6c9f46b3bd | 594 | /** \brief Unsigned Saturate |
| emilmont | 62:7e6c9f46b3bd | 595 | |
| emilmont | 62:7e6c9f46b3bd | 596 | This function saturates an unsigned value. |
| emilmont | 62:7e6c9f46b3bd | 597 | |
| emilmont | 62:7e6c9f46b3bd | 598 | \param [in] value Value to be saturated |
| emilmont | 62:7e6c9f46b3bd | 599 | \param [in] sat Bit position to saturate to (0..31) |
| emilmont | 62:7e6c9f46b3bd | 600 | \return Saturated value |
| emilmont | 62:7e6c9f46b3bd | 601 | */ |
| emilmont | 62:7e6c9f46b3bd | 602 | #define __USAT(ARG1,ARG2) \ |
| emilmont | 62:7e6c9f46b3bd | 603 | ({ \ |
| emilmont | 62:7e6c9f46b3bd | 604 | uint32_t __RES, __ARG1 = (ARG1); \ |
| emilmont | 62:7e6c9f46b3bd | 605 | __ASM ("usat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ |
| emilmont | 62:7e6c9f46b3bd | 606 | __RES; \ |
| emilmont | 62:7e6c9f46b3bd | 607 | }) |
| emilmont | 62:7e6c9f46b3bd | 608 | |
| emilmont | 62:7e6c9f46b3bd | 609 | |
| emilmont | 62:7e6c9f46b3bd | 610 | /** \brief Count leading zeros |
| emilmont | 62:7e6c9f46b3bd | 611 | |
| emilmont | 62:7e6c9f46b3bd | 612 | This function counts the number of leading zeros of a data value. |
| emilmont | 62:7e6c9f46b3bd | 613 | |
| emilmont | 62:7e6c9f46b3bd | 614 | \param [in] value Value to count the leading zeros |
| emilmont | 62:7e6c9f46b3bd | 615 | \return number of leading zeros in value |
| emilmont | 62:7e6c9f46b3bd | 616 | */ |
| emilmont | 62:7e6c9f46b3bd | 617 | __attribute__( ( always_inline ) ) __STATIC_INLINE uint8_t __CLZ(uint32_t value) |
| emilmont | 62:7e6c9f46b3bd | 618 | { |
| emilmont | 62:7e6c9f46b3bd | 619 | uint8_t result; |
| emilmont | 62:7e6c9f46b3bd | 620 | |
| emilmont | 62:7e6c9f46b3bd | 621 | __ASM volatile ("clz %0, %1" : "=r" (result) : "r" (value) ); |
| emilmont | 62:7e6c9f46b3bd | 622 | return(result); |
| emilmont | 62:7e6c9f46b3bd | 623 | } |
| emilmont | 62:7e6c9f46b3bd | 624 | |
| emilmont | 62:7e6c9f46b3bd | 625 | #endif /* (__CORTEX_M >= 0x03) */ |
| emilmont | 62:7e6c9f46b3bd | 626 | |
| emilmont | 62:7e6c9f46b3bd | 627 | |
| emilmont | 62:7e6c9f46b3bd | 628 | |
| emilmont | 62:7e6c9f46b3bd | 629 | |
| emilmont | 62:7e6c9f46b3bd | 630 | #elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/ |
| emilmont | 62:7e6c9f46b3bd | 631 | /* TASKING carm specific functions */ |
| emilmont | 62:7e6c9f46b3bd | 632 | |
| emilmont | 62:7e6c9f46b3bd | 633 | /* |
| emilmont | 62:7e6c9f46b3bd | 634 | * The CMSIS functions have been implemented as intrinsics in the compiler. |
| emilmont | 62:7e6c9f46b3bd | 635 | * Please use "carm -?i" to get an up to date list of all intrinsics, |
| emilmont | 62:7e6c9f46b3bd | 636 | * Including the CMSIS ones. |
| emilmont | 62:7e6c9f46b3bd | 637 | */ |
| emilmont | 62:7e6c9f46b3bd | 638 | |
| emilmont | 62:7e6c9f46b3bd | 639 | #endif |
| emilmont | 62:7e6c9f46b3bd | 640 | |
| emilmont | 62:7e6c9f46b3bd | 641 | /*@}*/ /* end of group CMSIS_Core_InstructionInterface */ |
| emilmont | 62:7e6c9f46b3bd | 642 | |
| emilmont | 62:7e6c9f46b3bd | 643 | #endif /* __CORE_CMINSTR_H */ |