雄介 太田
mbed(SerialHalfDuplex入り)
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LPC812/core_cm0plus.h@62:7e6c9f46b3bd, 2013-04-17 (annotated)
- Committer:
- emilmont
- Date:
- Wed Apr 17 15:30:58 2013 +0100
- Revision:
- 62:7e6c9f46b3bd
Add NXP LPC812
[KL25Z] Use channel 0 as a prescaler for channel 1
[CodeSourcery] Fix standard library retargeting removing duplicate "_isatty"
Move parse_pins in RPC module
Who changed what in which revision?
| User | Revision | Line number | New contents of line |
|---|---|---|---|
| emilmont | 62:7e6c9f46b3bd | 1 | /**************************************************************************//** |
| emilmont | 62:7e6c9f46b3bd | 2 | * @file core_cm0plus.h |
| emilmont | 62:7e6c9f46b3bd | 3 | * @brief CMSIS Cortex-M0+ Core Peripheral Access Layer Header File |
| emilmont | 62:7e6c9f46b3bd | 4 | * @version V3.02 |
| emilmont | 62:7e6c9f46b3bd | 5 | * @date 05. November 2012 |
| emilmont | 62:7e6c9f46b3bd | 6 | * |
| emilmont | 62:7e6c9f46b3bd | 7 | * @note |
| emilmont | 62:7e6c9f46b3bd | 8 | * Copyright (C) 2009-2012 ARM Limited. All rights reserved. |
| emilmont | 62:7e6c9f46b3bd | 9 | * |
| emilmont | 62:7e6c9f46b3bd | 10 | * @par |
| emilmont | 62:7e6c9f46b3bd | 11 | * ARM Limited (ARM) is supplying this software for use with Cortex-M |
| emilmont | 62:7e6c9f46b3bd | 12 | * processor based microcontrollers. This file can be freely distributed |
| emilmont | 62:7e6c9f46b3bd | 13 | * within development tools that are supporting such ARM based processors. |
| emilmont | 62:7e6c9f46b3bd | 14 | * |
| emilmont | 62:7e6c9f46b3bd | 15 | * @par |
| emilmont | 62:7e6c9f46b3bd | 16 | * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED |
| emilmont | 62:7e6c9f46b3bd | 17 | * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF |
| emilmont | 62:7e6c9f46b3bd | 18 | * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. |
| emilmont | 62:7e6c9f46b3bd | 19 | * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR |
| emilmont | 62:7e6c9f46b3bd | 20 | * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. |
| emilmont | 62:7e6c9f46b3bd | 21 | * |
| emilmont | 62:7e6c9f46b3bd | 22 | ******************************************************************************/ |
| emilmont | 62:7e6c9f46b3bd | 23 | #if defined ( __ICCARM__ ) |
| emilmont | 62:7e6c9f46b3bd | 24 | #pragma system_include /* treat file as system include file for MISRA check */ |
| emilmont | 62:7e6c9f46b3bd | 25 | #endif |
| emilmont | 62:7e6c9f46b3bd | 26 | |
| emilmont | 62:7e6c9f46b3bd | 27 | #ifdef __cplusplus |
| emilmont | 62:7e6c9f46b3bd | 28 | extern "C" { |
| emilmont | 62:7e6c9f46b3bd | 29 | #endif |
| emilmont | 62:7e6c9f46b3bd | 30 | |
| emilmont | 62:7e6c9f46b3bd | 31 | #ifndef __CORE_CM0PLUS_H_GENERIC |
| emilmont | 62:7e6c9f46b3bd | 32 | #define __CORE_CM0PLUS_H_GENERIC |
| emilmont | 62:7e6c9f46b3bd | 33 | |
| emilmont | 62:7e6c9f46b3bd | 34 | /** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions |
| emilmont | 62:7e6c9f46b3bd | 35 | CMSIS violates the following MISRA-C:2004 rules: |
| emilmont | 62:7e6c9f46b3bd | 36 | |
| emilmont | 62:7e6c9f46b3bd | 37 | \li Required Rule 8.5, object/function definition in header file.<br> |
| emilmont | 62:7e6c9f46b3bd | 38 | Function definitions in header files are used to allow 'inlining'. |
| emilmont | 62:7e6c9f46b3bd | 39 | |
| emilmont | 62:7e6c9f46b3bd | 40 | \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br> |
| emilmont | 62:7e6c9f46b3bd | 41 | Unions are used for effective representation of core registers. |
| emilmont | 62:7e6c9f46b3bd | 42 | |
| emilmont | 62:7e6c9f46b3bd | 43 | \li Advisory Rule 19.7, Function-like macro defined.<br> |
| emilmont | 62:7e6c9f46b3bd | 44 | Function-like macros are used to allow more efficient code. |
| emilmont | 62:7e6c9f46b3bd | 45 | */ |
| emilmont | 62:7e6c9f46b3bd | 46 | |
| emilmont | 62:7e6c9f46b3bd | 47 | |
| emilmont | 62:7e6c9f46b3bd | 48 | /******************************************************************************* |
| emilmont | 62:7e6c9f46b3bd | 49 | * CMSIS definitions |
| emilmont | 62:7e6c9f46b3bd | 50 | ******************************************************************************/ |
| emilmont | 62:7e6c9f46b3bd | 51 | /** \ingroup Cortex-M0+ |
| emilmont | 62:7e6c9f46b3bd | 52 | @{ |
| emilmont | 62:7e6c9f46b3bd | 53 | */ |
| emilmont | 62:7e6c9f46b3bd | 54 | |
| emilmont | 62:7e6c9f46b3bd | 55 | /* CMSIS CM0P definitions */ |
| emilmont | 62:7e6c9f46b3bd | 56 | #define __CM0PLUS_CMSIS_VERSION_MAIN (0x03) /*!< [31:16] CMSIS HAL main version */ |
| emilmont | 62:7e6c9f46b3bd | 57 | #define __CM0PLUS_CMSIS_VERSION_SUB (0x01) /*!< [15:0] CMSIS HAL sub version */ |
| emilmont | 62:7e6c9f46b3bd | 58 | #define __CM0PLUS_CMSIS_VERSION ((__CM0PLUS_CMSIS_VERSION_MAIN << 16) | \ |
| emilmont | 62:7e6c9f46b3bd | 59 | __CM0PLUS_CMSIS_VERSION_SUB) /*!< CMSIS HAL version number */ |
| emilmont | 62:7e6c9f46b3bd | 60 | |
| emilmont | 62:7e6c9f46b3bd | 61 | #define __CORTEX_M (0x00) /*!< Cortex-M Core */ |
| emilmont | 62:7e6c9f46b3bd | 62 | |
| emilmont | 62:7e6c9f46b3bd | 63 | |
| emilmont | 62:7e6c9f46b3bd | 64 | #if defined ( __CC_ARM ) |
| emilmont | 62:7e6c9f46b3bd | 65 | #define __ASM __asm /*!< asm keyword for ARM Compiler */ |
| emilmont | 62:7e6c9f46b3bd | 66 | #define __INLINE __inline /*!< inline keyword for ARM Compiler */ |
| emilmont | 62:7e6c9f46b3bd | 67 | #define __STATIC_INLINE static __inline |
| emilmont | 62:7e6c9f46b3bd | 68 | |
| emilmont | 62:7e6c9f46b3bd | 69 | #elif defined ( __ICCARM__ ) |
| emilmont | 62:7e6c9f46b3bd | 70 | #define __ASM __asm /*!< asm keyword for IAR Compiler */ |
| emilmont | 62:7e6c9f46b3bd | 71 | #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */ |
| emilmont | 62:7e6c9f46b3bd | 72 | #define __STATIC_INLINE static inline |
| emilmont | 62:7e6c9f46b3bd | 73 | |
| emilmont | 62:7e6c9f46b3bd | 74 | #elif defined ( __GNUC__ ) |
| emilmont | 62:7e6c9f46b3bd | 75 | #define __ASM __asm /*!< asm keyword for GNU Compiler */ |
| emilmont | 62:7e6c9f46b3bd | 76 | #define __INLINE inline /*!< inline keyword for GNU Compiler */ |
| emilmont | 62:7e6c9f46b3bd | 77 | #define __STATIC_INLINE static inline |
| emilmont | 62:7e6c9f46b3bd | 78 | |
| emilmont | 62:7e6c9f46b3bd | 79 | #elif defined ( __TASKING__ ) |
| emilmont | 62:7e6c9f46b3bd | 80 | #define __ASM __asm /*!< asm keyword for TASKING Compiler */ |
| emilmont | 62:7e6c9f46b3bd | 81 | #define __INLINE inline /*!< inline keyword for TASKING Compiler */ |
| emilmont | 62:7e6c9f46b3bd | 82 | #define __STATIC_INLINE static inline |
| emilmont | 62:7e6c9f46b3bd | 83 | |
| emilmont | 62:7e6c9f46b3bd | 84 | #endif |
| emilmont | 62:7e6c9f46b3bd | 85 | |
| emilmont | 62:7e6c9f46b3bd | 86 | /** __FPU_USED indicates whether an FPU is used or not. This core does not support an FPU at all |
| emilmont | 62:7e6c9f46b3bd | 87 | */ |
| emilmont | 62:7e6c9f46b3bd | 88 | #define __FPU_USED 0 |
| emilmont | 62:7e6c9f46b3bd | 89 | |
| emilmont | 62:7e6c9f46b3bd | 90 | #if defined ( __CC_ARM ) |
| emilmont | 62:7e6c9f46b3bd | 91 | #if defined __TARGET_FPU_VFP |
| emilmont | 62:7e6c9f46b3bd | 92 | #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" |
| emilmont | 62:7e6c9f46b3bd | 93 | #endif |
| emilmont | 62:7e6c9f46b3bd | 94 | |
| emilmont | 62:7e6c9f46b3bd | 95 | #elif defined ( __ICCARM__ ) |
| emilmont | 62:7e6c9f46b3bd | 96 | #if defined __ARMVFP__ |
| emilmont | 62:7e6c9f46b3bd | 97 | #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" |
| emilmont | 62:7e6c9f46b3bd | 98 | #endif |
| emilmont | 62:7e6c9f46b3bd | 99 | |
| emilmont | 62:7e6c9f46b3bd | 100 | #elif defined ( __GNUC__ ) |
| emilmont | 62:7e6c9f46b3bd | 101 | #if defined (__VFP_FP__) && !defined(__SOFTFP__) |
| emilmont | 62:7e6c9f46b3bd | 102 | #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" |
| emilmont | 62:7e6c9f46b3bd | 103 | #endif |
| emilmont | 62:7e6c9f46b3bd | 104 | |
| emilmont | 62:7e6c9f46b3bd | 105 | #elif defined ( __TASKING__ ) |
| emilmont | 62:7e6c9f46b3bd | 106 | #if defined __FPU_VFP__ |
| emilmont | 62:7e6c9f46b3bd | 107 | #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" |
| emilmont | 62:7e6c9f46b3bd | 108 | #endif |
| emilmont | 62:7e6c9f46b3bd | 109 | #endif |
| emilmont | 62:7e6c9f46b3bd | 110 | |
| emilmont | 62:7e6c9f46b3bd | 111 | #include <stdint.h> /* standard types definitions */ |
| emilmont | 62:7e6c9f46b3bd | 112 | #include <core_cmInstr.h> /* Core Instruction Access */ |
| emilmont | 62:7e6c9f46b3bd | 113 | #include <core_cmFunc.h> /* Core Function Access */ |
| emilmont | 62:7e6c9f46b3bd | 114 | |
| emilmont | 62:7e6c9f46b3bd | 115 | #endif /* __CORE_CM0PLUS_H_GENERIC */ |
| emilmont | 62:7e6c9f46b3bd | 116 | |
| emilmont | 62:7e6c9f46b3bd | 117 | #ifndef __CMSIS_GENERIC |
| emilmont | 62:7e6c9f46b3bd | 118 | |
| emilmont | 62:7e6c9f46b3bd | 119 | #ifndef __CORE_CM0PLUS_H_DEPENDANT |
| emilmont | 62:7e6c9f46b3bd | 120 | #define __CORE_CM0PLUS_H_DEPENDANT |
| emilmont | 62:7e6c9f46b3bd | 121 | |
| emilmont | 62:7e6c9f46b3bd | 122 | /* check device defines and use defaults */ |
| emilmont | 62:7e6c9f46b3bd | 123 | #if defined __CHECK_DEVICE_DEFINES |
| emilmont | 62:7e6c9f46b3bd | 124 | #ifndef __CM0PLUS_REV |
| emilmont | 62:7e6c9f46b3bd | 125 | #define __CM0PLUS_REV 0x0000 |
| emilmont | 62:7e6c9f46b3bd | 126 | #warning "__CM0PLUS_REV not defined in device header file; using default!" |
| emilmont | 62:7e6c9f46b3bd | 127 | #endif |
| emilmont | 62:7e6c9f46b3bd | 128 | |
| emilmont | 62:7e6c9f46b3bd | 129 | #ifndef __MPU_PRESENT |
| emilmont | 62:7e6c9f46b3bd | 130 | #define __MPU_PRESENT 0 |
| emilmont | 62:7e6c9f46b3bd | 131 | #warning "__MPU_PRESENT not defined in device header file; using default!" |
| emilmont | 62:7e6c9f46b3bd | 132 | #endif |
| emilmont | 62:7e6c9f46b3bd | 133 | |
| emilmont | 62:7e6c9f46b3bd | 134 | #ifndef __VTOR_PRESENT |
| emilmont | 62:7e6c9f46b3bd | 135 | #define __VTOR_PRESENT 0 |
| emilmont | 62:7e6c9f46b3bd | 136 | #warning "__VTOR_PRESENT not defined in device header file; using default!" |
| emilmont | 62:7e6c9f46b3bd | 137 | #endif |
| emilmont | 62:7e6c9f46b3bd | 138 | |
| emilmont | 62:7e6c9f46b3bd | 139 | #ifndef __NVIC_PRIO_BITS |
| emilmont | 62:7e6c9f46b3bd | 140 | #define __NVIC_PRIO_BITS 2 |
| emilmont | 62:7e6c9f46b3bd | 141 | #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" |
| emilmont | 62:7e6c9f46b3bd | 142 | #endif |
| emilmont | 62:7e6c9f46b3bd | 143 | |
| emilmont | 62:7e6c9f46b3bd | 144 | #ifndef __Vendor_SysTickConfig |
| emilmont | 62:7e6c9f46b3bd | 145 | #define __Vendor_SysTickConfig 0 |
| emilmont | 62:7e6c9f46b3bd | 146 | #warning "__Vendor_SysTickConfig not defined in device header file; using default!" |
| emilmont | 62:7e6c9f46b3bd | 147 | #endif |
| emilmont | 62:7e6c9f46b3bd | 148 | #endif |
| emilmont | 62:7e6c9f46b3bd | 149 | |
| emilmont | 62:7e6c9f46b3bd | 150 | /* IO definitions (access restrictions to peripheral registers) */ |
| emilmont | 62:7e6c9f46b3bd | 151 | /** |
| emilmont | 62:7e6c9f46b3bd | 152 | \defgroup CMSIS_glob_defs CMSIS Global Defines |
| emilmont | 62:7e6c9f46b3bd | 153 | |
| emilmont | 62:7e6c9f46b3bd | 154 | <strong>IO Type Qualifiers</strong> are used |
| emilmont | 62:7e6c9f46b3bd | 155 | \li to specify the access to peripheral variables. |
| emilmont | 62:7e6c9f46b3bd | 156 | \li for automatic generation of peripheral register debug information. |
| emilmont | 62:7e6c9f46b3bd | 157 | */ |
| emilmont | 62:7e6c9f46b3bd | 158 | #ifdef __cplusplus |
| emilmont | 62:7e6c9f46b3bd | 159 | #define __I volatile /*!< Defines 'read only' permissions */ |
| emilmont | 62:7e6c9f46b3bd | 160 | #else |
| emilmont | 62:7e6c9f46b3bd | 161 | #define __I volatile const /*!< Defines 'read only' permissions */ |
| emilmont | 62:7e6c9f46b3bd | 162 | #endif |
| emilmont | 62:7e6c9f46b3bd | 163 | #define __O volatile /*!< Defines 'write only' permissions */ |
| emilmont | 62:7e6c9f46b3bd | 164 | #define __IO volatile /*!< Defines 'read / write' permissions */ |
| emilmont | 62:7e6c9f46b3bd | 165 | |
| emilmont | 62:7e6c9f46b3bd | 166 | /*@} end of group Cortex-M0+ */ |
| emilmont | 62:7e6c9f46b3bd | 167 | |
| emilmont | 62:7e6c9f46b3bd | 168 | |
| emilmont | 62:7e6c9f46b3bd | 169 | |
| emilmont | 62:7e6c9f46b3bd | 170 | /******************************************************************************* |
| emilmont | 62:7e6c9f46b3bd | 171 | * Register Abstraction |
| emilmont | 62:7e6c9f46b3bd | 172 | Core Register contain: |
| emilmont | 62:7e6c9f46b3bd | 173 | - Core Register |
| emilmont | 62:7e6c9f46b3bd | 174 | - Core NVIC Register |
| emilmont | 62:7e6c9f46b3bd | 175 | - Core SCB Register |
| emilmont | 62:7e6c9f46b3bd | 176 | - Core SysTick Register |
| emilmont | 62:7e6c9f46b3bd | 177 | - Core MPU Register |
| emilmont | 62:7e6c9f46b3bd | 178 | ******************************************************************************/ |
| emilmont | 62:7e6c9f46b3bd | 179 | /** \defgroup CMSIS_core_register Defines and Type Definitions |
| emilmont | 62:7e6c9f46b3bd | 180 | \brief Type definitions and defines for Cortex-M processor based devices. |
| emilmont | 62:7e6c9f46b3bd | 181 | */ |
| emilmont | 62:7e6c9f46b3bd | 182 | |
| emilmont | 62:7e6c9f46b3bd | 183 | /** \ingroup CMSIS_core_register |
| emilmont | 62:7e6c9f46b3bd | 184 | \defgroup CMSIS_CORE Status and Control Registers |
| emilmont | 62:7e6c9f46b3bd | 185 | \brief Core Register type definitions. |
| emilmont | 62:7e6c9f46b3bd | 186 | @{ |
| emilmont | 62:7e6c9f46b3bd | 187 | */ |
| emilmont | 62:7e6c9f46b3bd | 188 | |
| emilmont | 62:7e6c9f46b3bd | 189 | /** \brief Union type to access the Application Program Status Register (APSR). |
| emilmont | 62:7e6c9f46b3bd | 190 | */ |
| emilmont | 62:7e6c9f46b3bd | 191 | typedef union |
| emilmont | 62:7e6c9f46b3bd | 192 | { |
| emilmont | 62:7e6c9f46b3bd | 193 | struct |
| emilmont | 62:7e6c9f46b3bd | 194 | { |
| emilmont | 62:7e6c9f46b3bd | 195 | #if (__CORTEX_M != 0x04) |
| emilmont | 62:7e6c9f46b3bd | 196 | uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */ |
| emilmont | 62:7e6c9f46b3bd | 197 | #else |
| emilmont | 62:7e6c9f46b3bd | 198 | uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ |
| emilmont | 62:7e6c9f46b3bd | 199 | uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ |
| emilmont | 62:7e6c9f46b3bd | 200 | uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ |
| emilmont | 62:7e6c9f46b3bd | 201 | #endif |
| emilmont | 62:7e6c9f46b3bd | 202 | uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ |
| emilmont | 62:7e6c9f46b3bd | 203 | uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ |
| emilmont | 62:7e6c9f46b3bd | 204 | uint32_t C:1; /*!< bit: 29 Carry condition code flag */ |
| emilmont | 62:7e6c9f46b3bd | 205 | uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ |
| emilmont | 62:7e6c9f46b3bd | 206 | uint32_t N:1; /*!< bit: 31 Negative condition code flag */ |
| emilmont | 62:7e6c9f46b3bd | 207 | } b; /*!< Structure used for bit access */ |
| emilmont | 62:7e6c9f46b3bd | 208 | uint32_t w; /*!< Type used for word access */ |
| emilmont | 62:7e6c9f46b3bd | 209 | } APSR_Type; |
| emilmont | 62:7e6c9f46b3bd | 210 | |
| emilmont | 62:7e6c9f46b3bd | 211 | |
| emilmont | 62:7e6c9f46b3bd | 212 | /** \brief Union type to access the Interrupt Program Status Register (IPSR). |
| emilmont | 62:7e6c9f46b3bd | 213 | */ |
| emilmont | 62:7e6c9f46b3bd | 214 | typedef union |
| emilmont | 62:7e6c9f46b3bd | 215 | { |
| emilmont | 62:7e6c9f46b3bd | 216 | struct |
| emilmont | 62:7e6c9f46b3bd | 217 | { |
| emilmont | 62:7e6c9f46b3bd | 218 | uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ |
| emilmont | 62:7e6c9f46b3bd | 219 | uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ |
| emilmont | 62:7e6c9f46b3bd | 220 | } b; /*!< Structure used for bit access */ |
| emilmont | 62:7e6c9f46b3bd | 221 | uint32_t w; /*!< Type used for word access */ |
| emilmont | 62:7e6c9f46b3bd | 222 | } IPSR_Type; |
| emilmont | 62:7e6c9f46b3bd | 223 | |
| emilmont | 62:7e6c9f46b3bd | 224 | |
| emilmont | 62:7e6c9f46b3bd | 225 | /** \brief Union type to access the Special-Purpose Program Status Registers (xPSR). |
| emilmont | 62:7e6c9f46b3bd | 226 | */ |
| emilmont | 62:7e6c9f46b3bd | 227 | typedef union |
| emilmont | 62:7e6c9f46b3bd | 228 | { |
| emilmont | 62:7e6c9f46b3bd | 229 | struct |
| emilmont | 62:7e6c9f46b3bd | 230 | { |
| emilmont | 62:7e6c9f46b3bd | 231 | uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ |
| emilmont | 62:7e6c9f46b3bd | 232 | #if (__CORTEX_M != 0x04) |
| emilmont | 62:7e6c9f46b3bd | 233 | uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ |
| emilmont | 62:7e6c9f46b3bd | 234 | #else |
| emilmont | 62:7e6c9f46b3bd | 235 | uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */ |
| emilmont | 62:7e6c9f46b3bd | 236 | uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ |
| emilmont | 62:7e6c9f46b3bd | 237 | uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ |
| emilmont | 62:7e6c9f46b3bd | 238 | #endif |
| emilmont | 62:7e6c9f46b3bd | 239 | uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ |
| emilmont | 62:7e6c9f46b3bd | 240 | uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ |
| emilmont | 62:7e6c9f46b3bd | 241 | uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ |
| emilmont | 62:7e6c9f46b3bd | 242 | uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ |
| emilmont | 62:7e6c9f46b3bd | 243 | uint32_t C:1; /*!< bit: 29 Carry condition code flag */ |
| emilmont | 62:7e6c9f46b3bd | 244 | uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ |
| emilmont | 62:7e6c9f46b3bd | 245 | uint32_t N:1; /*!< bit: 31 Negative condition code flag */ |
| emilmont | 62:7e6c9f46b3bd | 246 | } b; /*!< Structure used for bit access */ |
| emilmont | 62:7e6c9f46b3bd | 247 | uint32_t w; /*!< Type used for word access */ |
| emilmont | 62:7e6c9f46b3bd | 248 | } xPSR_Type; |
| emilmont | 62:7e6c9f46b3bd | 249 | |
| emilmont | 62:7e6c9f46b3bd | 250 | |
| emilmont | 62:7e6c9f46b3bd | 251 | /** \brief Union type to access the Control Registers (CONTROL). |
| emilmont | 62:7e6c9f46b3bd | 252 | */ |
| emilmont | 62:7e6c9f46b3bd | 253 | typedef union |
| emilmont | 62:7e6c9f46b3bd | 254 | { |
| emilmont | 62:7e6c9f46b3bd | 255 | struct |
| emilmont | 62:7e6c9f46b3bd | 256 | { |
| emilmont | 62:7e6c9f46b3bd | 257 | uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ |
| emilmont | 62:7e6c9f46b3bd | 258 | uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ |
| emilmont | 62:7e6c9f46b3bd | 259 | uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */ |
| emilmont | 62:7e6c9f46b3bd | 260 | uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */ |
| emilmont | 62:7e6c9f46b3bd | 261 | } b; /*!< Structure used for bit access */ |
| emilmont | 62:7e6c9f46b3bd | 262 | uint32_t w; /*!< Type used for word access */ |
| emilmont | 62:7e6c9f46b3bd | 263 | } CONTROL_Type; |
| emilmont | 62:7e6c9f46b3bd | 264 | |
| emilmont | 62:7e6c9f46b3bd | 265 | /*@} end of group CMSIS_CORE */ |
| emilmont | 62:7e6c9f46b3bd | 266 | |
| emilmont | 62:7e6c9f46b3bd | 267 | |
| emilmont | 62:7e6c9f46b3bd | 268 | /** \ingroup CMSIS_core_register |
| emilmont | 62:7e6c9f46b3bd | 269 | \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) |
| emilmont | 62:7e6c9f46b3bd | 270 | \brief Type definitions for the NVIC Registers |
| emilmont | 62:7e6c9f46b3bd | 271 | @{ |
| emilmont | 62:7e6c9f46b3bd | 272 | */ |
| emilmont | 62:7e6c9f46b3bd | 273 | |
| emilmont | 62:7e6c9f46b3bd | 274 | /** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). |
| emilmont | 62:7e6c9f46b3bd | 275 | */ |
| emilmont | 62:7e6c9f46b3bd | 276 | typedef struct |
| emilmont | 62:7e6c9f46b3bd | 277 | { |
| emilmont | 62:7e6c9f46b3bd | 278 | __IO uint32_t ISER[1]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ |
| emilmont | 62:7e6c9f46b3bd | 279 | uint32_t RESERVED0[31]; |
| emilmont | 62:7e6c9f46b3bd | 280 | __IO uint32_t ICER[1]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ |
| emilmont | 62:7e6c9f46b3bd | 281 | uint32_t RSERVED1[31]; |
| emilmont | 62:7e6c9f46b3bd | 282 | __IO uint32_t ISPR[1]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ |
| emilmont | 62:7e6c9f46b3bd | 283 | uint32_t RESERVED2[31]; |
| emilmont | 62:7e6c9f46b3bd | 284 | __IO uint32_t ICPR[1]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ |
| emilmont | 62:7e6c9f46b3bd | 285 | uint32_t RESERVED3[31]; |
| emilmont | 62:7e6c9f46b3bd | 286 | uint32_t RESERVED4[64]; |
| emilmont | 62:7e6c9f46b3bd | 287 | __IO uint32_t IP[8]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ |
| emilmont | 62:7e6c9f46b3bd | 288 | } NVIC_Type; |
| emilmont | 62:7e6c9f46b3bd | 289 | |
| emilmont | 62:7e6c9f46b3bd | 290 | /*@} end of group CMSIS_NVIC */ |
| emilmont | 62:7e6c9f46b3bd | 291 | |
| emilmont | 62:7e6c9f46b3bd | 292 | |
| emilmont | 62:7e6c9f46b3bd | 293 | /** \ingroup CMSIS_core_register |
| emilmont | 62:7e6c9f46b3bd | 294 | \defgroup CMSIS_SCB System Control Block (SCB) |
| emilmont | 62:7e6c9f46b3bd | 295 | \brief Type definitions for the System Control Block Registers |
| emilmont | 62:7e6c9f46b3bd | 296 | @{ |
| emilmont | 62:7e6c9f46b3bd | 297 | */ |
| emilmont | 62:7e6c9f46b3bd | 298 | |
| emilmont | 62:7e6c9f46b3bd | 299 | /** \brief Structure type to access the System Control Block (SCB). |
| emilmont | 62:7e6c9f46b3bd | 300 | */ |
| emilmont | 62:7e6c9f46b3bd | 301 | typedef struct |
| emilmont | 62:7e6c9f46b3bd | 302 | { |
| emilmont | 62:7e6c9f46b3bd | 303 | __I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ |
| emilmont | 62:7e6c9f46b3bd | 304 | __IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ |
| emilmont | 62:7e6c9f46b3bd | 305 | #if (__VTOR_PRESENT == 1) |
| emilmont | 62:7e6c9f46b3bd | 306 | __IO uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ |
| emilmont | 62:7e6c9f46b3bd | 307 | #else |
| emilmont | 62:7e6c9f46b3bd | 308 | uint32_t RESERVED0; |
| emilmont | 62:7e6c9f46b3bd | 309 | #endif |
| emilmont | 62:7e6c9f46b3bd | 310 | __IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ |
| emilmont | 62:7e6c9f46b3bd | 311 | __IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ |
| emilmont | 62:7e6c9f46b3bd | 312 | __IO uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ |
| emilmont | 62:7e6c9f46b3bd | 313 | uint32_t RESERVED1; |
| emilmont | 62:7e6c9f46b3bd | 314 | __IO uint32_t SHP[2]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ |
| emilmont | 62:7e6c9f46b3bd | 315 | __IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ |
| emilmont | 62:7e6c9f46b3bd | 316 | } SCB_Type; |
| emilmont | 62:7e6c9f46b3bd | 317 | |
| emilmont | 62:7e6c9f46b3bd | 318 | /* SCB CPUID Register Definitions */ |
| emilmont | 62:7e6c9f46b3bd | 319 | #define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */ |
| emilmont | 62:7e6c9f46b3bd | 320 | #define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ |
| emilmont | 62:7e6c9f46b3bd | 321 | |
| emilmont | 62:7e6c9f46b3bd | 322 | #define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */ |
| emilmont | 62:7e6c9f46b3bd | 323 | #define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ |
| emilmont | 62:7e6c9f46b3bd | 324 | |
| emilmont | 62:7e6c9f46b3bd | 325 | #define SCB_CPUID_ARCHITECTURE_Pos 16 /*!< SCB CPUID: ARCHITECTURE Position */ |
| emilmont | 62:7e6c9f46b3bd | 326 | #define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ |
| emilmont | 62:7e6c9f46b3bd | 327 | |
| emilmont | 62:7e6c9f46b3bd | 328 | #define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */ |
| emilmont | 62:7e6c9f46b3bd | 329 | #define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ |
| emilmont | 62:7e6c9f46b3bd | 330 | |
| emilmont | 62:7e6c9f46b3bd | 331 | #define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */ |
| emilmont | 62:7e6c9f46b3bd | 332 | #define SCB_CPUID_REVISION_Msk (0xFUL << SCB_CPUID_REVISION_Pos) /*!< SCB CPUID: REVISION Mask */ |
| emilmont | 62:7e6c9f46b3bd | 333 | |
| emilmont | 62:7e6c9f46b3bd | 334 | /* SCB Interrupt Control State Register Definitions */ |
| emilmont | 62:7e6c9f46b3bd | 335 | #define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */ |
| emilmont | 62:7e6c9f46b3bd | 336 | #define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ |
| emilmont | 62:7e6c9f46b3bd | 337 | |
| emilmont | 62:7e6c9f46b3bd | 338 | #define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */ |
| emilmont | 62:7e6c9f46b3bd | 339 | #define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ |
| emilmont | 62:7e6c9f46b3bd | 340 | |
| emilmont | 62:7e6c9f46b3bd | 341 | #define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */ |
| emilmont | 62:7e6c9f46b3bd | 342 | #define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ |
| emilmont | 62:7e6c9f46b3bd | 343 | |
| emilmont | 62:7e6c9f46b3bd | 344 | #define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */ |
| emilmont | 62:7e6c9f46b3bd | 345 | #define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ |
| emilmont | 62:7e6c9f46b3bd | 346 | |
| emilmont | 62:7e6c9f46b3bd | 347 | #define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */ |
| emilmont | 62:7e6c9f46b3bd | 348 | #define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ |
| emilmont | 62:7e6c9f46b3bd | 349 | |
| emilmont | 62:7e6c9f46b3bd | 350 | #define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */ |
| emilmont | 62:7e6c9f46b3bd | 351 | #define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ |
| emilmont | 62:7e6c9f46b3bd | 352 | |
| emilmont | 62:7e6c9f46b3bd | 353 | #define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */ |
| emilmont | 62:7e6c9f46b3bd | 354 | #define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ |
| emilmont | 62:7e6c9f46b3bd | 355 | |
| emilmont | 62:7e6c9f46b3bd | 356 | #define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */ |
| emilmont | 62:7e6c9f46b3bd | 357 | #define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ |
| emilmont | 62:7e6c9f46b3bd | 358 | |
| emilmont | 62:7e6c9f46b3bd | 359 | #define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */ |
| emilmont | 62:7e6c9f46b3bd | 360 | #define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos) /*!< SCB ICSR: VECTACTIVE Mask */ |
| emilmont | 62:7e6c9f46b3bd | 361 | |
| emilmont | 62:7e6c9f46b3bd | 362 | #if (__VTOR_PRESENT == 1) |
| emilmont | 62:7e6c9f46b3bd | 363 | /* SCB Interrupt Control State Register Definitions */ |
| emilmont | 62:7e6c9f46b3bd | 364 | #define SCB_VTOR_TBLOFF_Pos 7 /*!< SCB VTOR: TBLOFF Position */ |
| emilmont | 62:7e6c9f46b3bd | 365 | #define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ |
| emilmont | 62:7e6c9f46b3bd | 366 | #endif |
| emilmont | 62:7e6c9f46b3bd | 367 | |
| emilmont | 62:7e6c9f46b3bd | 368 | /* SCB Application Interrupt and Reset Control Register Definitions */ |
| emilmont | 62:7e6c9f46b3bd | 369 | #define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */ |
| emilmont | 62:7e6c9f46b3bd | 370 | #define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ |
| emilmont | 62:7e6c9f46b3bd | 371 | |
| emilmont | 62:7e6c9f46b3bd | 372 | #define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */ |
| emilmont | 62:7e6c9f46b3bd | 373 | #define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ |
| emilmont | 62:7e6c9f46b3bd | 374 | |
| emilmont | 62:7e6c9f46b3bd | 375 | #define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */ |
| emilmont | 62:7e6c9f46b3bd | 376 | #define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ |
| emilmont | 62:7e6c9f46b3bd | 377 | |
| emilmont | 62:7e6c9f46b3bd | 378 | #define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */ |
| emilmont | 62:7e6c9f46b3bd | 379 | #define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ |
| emilmont | 62:7e6c9f46b3bd | 380 | |
| emilmont | 62:7e6c9f46b3bd | 381 | #define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */ |
| emilmont | 62:7e6c9f46b3bd | 382 | #define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ |
| emilmont | 62:7e6c9f46b3bd | 383 | |
| emilmont | 62:7e6c9f46b3bd | 384 | /* SCB System Control Register Definitions */ |
| emilmont | 62:7e6c9f46b3bd | 385 | #define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */ |
| emilmont | 62:7e6c9f46b3bd | 386 | #define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ |
| emilmont | 62:7e6c9f46b3bd | 387 | |
| emilmont | 62:7e6c9f46b3bd | 388 | #define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */ |
| emilmont | 62:7e6c9f46b3bd | 389 | #define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ |
| emilmont | 62:7e6c9f46b3bd | 390 | |
| emilmont | 62:7e6c9f46b3bd | 391 | #define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */ |
| emilmont | 62:7e6c9f46b3bd | 392 | #define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ |
| emilmont | 62:7e6c9f46b3bd | 393 | |
| emilmont | 62:7e6c9f46b3bd | 394 | /* SCB Configuration Control Register Definitions */ |
| emilmont | 62:7e6c9f46b3bd | 395 | #define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */ |
| emilmont | 62:7e6c9f46b3bd | 396 | #define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ |
| emilmont | 62:7e6c9f46b3bd | 397 | |
| emilmont | 62:7e6c9f46b3bd | 398 | #define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */ |
| emilmont | 62:7e6c9f46b3bd | 399 | #define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ |
| emilmont | 62:7e6c9f46b3bd | 400 | |
| emilmont | 62:7e6c9f46b3bd | 401 | /* SCB System Handler Control and State Register Definitions */ |
| emilmont | 62:7e6c9f46b3bd | 402 | #define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */ |
| emilmont | 62:7e6c9f46b3bd | 403 | #define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ |
| emilmont | 62:7e6c9f46b3bd | 404 | |
| emilmont | 62:7e6c9f46b3bd | 405 | /*@} end of group CMSIS_SCB */ |
| emilmont | 62:7e6c9f46b3bd | 406 | |
| emilmont | 62:7e6c9f46b3bd | 407 | |
| emilmont | 62:7e6c9f46b3bd | 408 | /** \ingroup CMSIS_core_register |
| emilmont | 62:7e6c9f46b3bd | 409 | \defgroup CMSIS_SysTick System Tick Timer (SysTick) |
| emilmont | 62:7e6c9f46b3bd | 410 | \brief Type definitions for the System Timer Registers. |
| emilmont | 62:7e6c9f46b3bd | 411 | @{ |
| emilmont | 62:7e6c9f46b3bd | 412 | */ |
| emilmont | 62:7e6c9f46b3bd | 413 | |
| emilmont | 62:7e6c9f46b3bd | 414 | /** \brief Structure type to access the System Timer (SysTick). |
| emilmont | 62:7e6c9f46b3bd | 415 | */ |
| emilmont | 62:7e6c9f46b3bd | 416 | typedef struct |
| emilmont | 62:7e6c9f46b3bd | 417 | { |
| emilmont | 62:7e6c9f46b3bd | 418 | __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ |
| emilmont | 62:7e6c9f46b3bd | 419 | __IO uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ |
| emilmont | 62:7e6c9f46b3bd | 420 | __IO uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ |
| emilmont | 62:7e6c9f46b3bd | 421 | __I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ |
| emilmont | 62:7e6c9f46b3bd | 422 | } SysTick_Type; |
| emilmont | 62:7e6c9f46b3bd | 423 | |
| emilmont | 62:7e6c9f46b3bd | 424 | /* SysTick Control / Status Register Definitions */ |
| emilmont | 62:7e6c9f46b3bd | 425 | #define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */ |
| emilmont | 62:7e6c9f46b3bd | 426 | #define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ |
| emilmont | 62:7e6c9f46b3bd | 427 | |
| emilmont | 62:7e6c9f46b3bd | 428 | #define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */ |
| emilmont | 62:7e6c9f46b3bd | 429 | #define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ |
| emilmont | 62:7e6c9f46b3bd | 430 | |
| emilmont | 62:7e6c9f46b3bd | 431 | #define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */ |
| emilmont | 62:7e6c9f46b3bd | 432 | #define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ |
| emilmont | 62:7e6c9f46b3bd | 433 | |
| emilmont | 62:7e6c9f46b3bd | 434 | #define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */ |
| emilmont | 62:7e6c9f46b3bd | 435 | #define SysTick_CTRL_ENABLE_Msk (1UL << SysTick_CTRL_ENABLE_Pos) /*!< SysTick CTRL: ENABLE Mask */ |
| emilmont | 62:7e6c9f46b3bd | 436 | |
| emilmont | 62:7e6c9f46b3bd | 437 | /* SysTick Reload Register Definitions */ |
| emilmont | 62:7e6c9f46b3bd | 438 | #define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */ |
| emilmont | 62:7e6c9f46b3bd | 439 | #define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos) /*!< SysTick LOAD: RELOAD Mask */ |
| emilmont | 62:7e6c9f46b3bd | 440 | |
| emilmont | 62:7e6c9f46b3bd | 441 | /* SysTick Current Register Definitions */ |
| emilmont | 62:7e6c9f46b3bd | 442 | #define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */ |
| emilmont | 62:7e6c9f46b3bd | 443 | #define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick VAL: CURRENT Mask */ |
| emilmont | 62:7e6c9f46b3bd | 444 | |
| emilmont | 62:7e6c9f46b3bd | 445 | /* SysTick Calibration Register Definitions */ |
| emilmont | 62:7e6c9f46b3bd | 446 | #define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */ |
| emilmont | 62:7e6c9f46b3bd | 447 | #define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ |
| emilmont | 62:7e6c9f46b3bd | 448 | |
| emilmont | 62:7e6c9f46b3bd | 449 | #define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */ |
| emilmont | 62:7e6c9f46b3bd | 450 | #define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ |
| emilmont | 62:7e6c9f46b3bd | 451 | |
| emilmont | 62:7e6c9f46b3bd | 452 | #define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */ |
| emilmont | 62:7e6c9f46b3bd | 453 | #define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick CALIB: TENMS Mask */ |
| emilmont | 62:7e6c9f46b3bd | 454 | |
| emilmont | 62:7e6c9f46b3bd | 455 | /*@} end of group CMSIS_SysTick */ |
| emilmont | 62:7e6c9f46b3bd | 456 | |
| emilmont | 62:7e6c9f46b3bd | 457 | #if (__MPU_PRESENT == 1) |
| emilmont | 62:7e6c9f46b3bd | 458 | /** \ingroup CMSIS_core_register |
| emilmont | 62:7e6c9f46b3bd | 459 | \defgroup CMSIS_MPU Memory Protection Unit (MPU) |
| emilmont | 62:7e6c9f46b3bd | 460 | \brief Type definitions for the Memory Protection Unit (MPU) |
| emilmont | 62:7e6c9f46b3bd | 461 | @{ |
| emilmont | 62:7e6c9f46b3bd | 462 | */ |
| emilmont | 62:7e6c9f46b3bd | 463 | |
| emilmont | 62:7e6c9f46b3bd | 464 | /** \brief Structure type to access the Memory Protection Unit (MPU). |
| emilmont | 62:7e6c9f46b3bd | 465 | */ |
| emilmont | 62:7e6c9f46b3bd | 466 | typedef struct |
| emilmont | 62:7e6c9f46b3bd | 467 | { |
| emilmont | 62:7e6c9f46b3bd | 468 | __I uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ |
| emilmont | 62:7e6c9f46b3bd | 469 | __IO uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ |
| emilmont | 62:7e6c9f46b3bd | 470 | __IO uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ |
| emilmont | 62:7e6c9f46b3bd | 471 | __IO uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ |
| emilmont | 62:7e6c9f46b3bd | 472 | __IO uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ |
| emilmont | 62:7e6c9f46b3bd | 473 | } MPU_Type; |
| emilmont | 62:7e6c9f46b3bd | 474 | |
| emilmont | 62:7e6c9f46b3bd | 475 | /* MPU Type Register */ |
| emilmont | 62:7e6c9f46b3bd | 476 | #define MPU_TYPE_IREGION_Pos 16 /*!< MPU TYPE: IREGION Position */ |
| emilmont | 62:7e6c9f46b3bd | 477 | #define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ |
| emilmont | 62:7e6c9f46b3bd | 478 | |
| emilmont | 62:7e6c9f46b3bd | 479 | #define MPU_TYPE_DREGION_Pos 8 /*!< MPU TYPE: DREGION Position */ |
| emilmont | 62:7e6c9f46b3bd | 480 | #define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ |
| emilmont | 62:7e6c9f46b3bd | 481 | |
| emilmont | 62:7e6c9f46b3bd | 482 | #define MPU_TYPE_SEPARATE_Pos 0 /*!< MPU TYPE: SEPARATE Position */ |
| emilmont | 62:7e6c9f46b3bd | 483 | #define MPU_TYPE_SEPARATE_Msk (1UL << MPU_TYPE_SEPARATE_Pos) /*!< MPU TYPE: SEPARATE Mask */ |
| emilmont | 62:7e6c9f46b3bd | 484 | |
| emilmont | 62:7e6c9f46b3bd | 485 | /* MPU Control Register */ |
| emilmont | 62:7e6c9f46b3bd | 486 | #define MPU_CTRL_PRIVDEFENA_Pos 2 /*!< MPU CTRL: PRIVDEFENA Position */ |
| emilmont | 62:7e6c9f46b3bd | 487 | #define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ |
| emilmont | 62:7e6c9f46b3bd | 488 | |
| emilmont | 62:7e6c9f46b3bd | 489 | #define MPU_CTRL_HFNMIENA_Pos 1 /*!< MPU CTRL: HFNMIENA Position */ |
| emilmont | 62:7e6c9f46b3bd | 490 | #define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ |
| emilmont | 62:7e6c9f46b3bd | 491 | |
| emilmont | 62:7e6c9f46b3bd | 492 | #define MPU_CTRL_ENABLE_Pos 0 /*!< MPU CTRL: ENABLE Position */ |
| emilmont | 62:7e6c9f46b3bd | 493 | #define MPU_CTRL_ENABLE_Msk (1UL << MPU_CTRL_ENABLE_Pos) /*!< MPU CTRL: ENABLE Mask */ |
| emilmont | 62:7e6c9f46b3bd | 494 | |
| emilmont | 62:7e6c9f46b3bd | 495 | /* MPU Region Number Register */ |
| emilmont | 62:7e6c9f46b3bd | 496 | #define MPU_RNR_REGION_Pos 0 /*!< MPU RNR: REGION Position */ |
| emilmont | 62:7e6c9f46b3bd | 497 | #define MPU_RNR_REGION_Msk (0xFFUL << MPU_RNR_REGION_Pos) /*!< MPU RNR: REGION Mask */ |
| emilmont | 62:7e6c9f46b3bd | 498 | |
| emilmont | 62:7e6c9f46b3bd | 499 | /* MPU Region Base Address Register */ |
| emilmont | 62:7e6c9f46b3bd | 500 | #define MPU_RBAR_ADDR_Pos 8 /*!< MPU RBAR: ADDR Position */ |
| emilmont | 62:7e6c9f46b3bd | 501 | #define MPU_RBAR_ADDR_Msk (0xFFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ |
| emilmont | 62:7e6c9f46b3bd | 502 | |
| emilmont | 62:7e6c9f46b3bd | 503 | #define MPU_RBAR_VALID_Pos 4 /*!< MPU RBAR: VALID Position */ |
| emilmont | 62:7e6c9f46b3bd | 504 | #define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ |
| emilmont | 62:7e6c9f46b3bd | 505 | |
| emilmont | 62:7e6c9f46b3bd | 506 | #define MPU_RBAR_REGION_Pos 0 /*!< MPU RBAR: REGION Position */ |
| emilmont | 62:7e6c9f46b3bd | 507 | #define MPU_RBAR_REGION_Msk (0xFUL << MPU_RBAR_REGION_Pos) /*!< MPU RBAR: REGION Mask */ |
| emilmont | 62:7e6c9f46b3bd | 508 | |
| emilmont | 62:7e6c9f46b3bd | 509 | /* MPU Region Attribute and Size Register */ |
| emilmont | 62:7e6c9f46b3bd | 510 | #define MPU_RASR_ATTRS_Pos 16 /*!< MPU RASR: MPU Region Attribute field Position */ |
| emilmont | 62:7e6c9f46b3bd | 511 | #define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ |
| emilmont | 62:7e6c9f46b3bd | 512 | |
| emilmont | 62:7e6c9f46b3bd | 513 | #define MPU_RASR_XN_Pos 28 /*!< MPU RASR: ATTRS.XN Position */ |
| emilmont | 62:7e6c9f46b3bd | 514 | #define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ |
| emilmont | 62:7e6c9f46b3bd | 515 | |
| emilmont | 62:7e6c9f46b3bd | 516 | #define MPU_RASR_AP_Pos 24 /*!< MPU RASR: ATTRS.AP Position */ |
| emilmont | 62:7e6c9f46b3bd | 517 | #define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ |
| emilmont | 62:7e6c9f46b3bd | 518 | |
| emilmont | 62:7e6c9f46b3bd | 519 | #define MPU_RASR_TEX_Pos 19 /*!< MPU RASR: ATTRS.TEX Position */ |
| emilmont | 62:7e6c9f46b3bd | 520 | #define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ |
| emilmont | 62:7e6c9f46b3bd | 521 | |
| emilmont | 62:7e6c9f46b3bd | 522 | #define MPU_RASR_S_Pos 18 /*!< MPU RASR: ATTRS.S Position */ |
| emilmont | 62:7e6c9f46b3bd | 523 | #define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ |
| emilmont | 62:7e6c9f46b3bd | 524 | |
| emilmont | 62:7e6c9f46b3bd | 525 | #define MPU_RASR_C_Pos 17 /*!< MPU RASR: ATTRS.C Position */ |
| emilmont | 62:7e6c9f46b3bd | 526 | #define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ |
| emilmont | 62:7e6c9f46b3bd | 527 | |
| emilmont | 62:7e6c9f46b3bd | 528 | #define MPU_RASR_B_Pos 16 /*!< MPU RASR: ATTRS.B Position */ |
| emilmont | 62:7e6c9f46b3bd | 529 | #define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ |
| emilmont | 62:7e6c9f46b3bd | 530 | |
| emilmont | 62:7e6c9f46b3bd | 531 | #define MPU_RASR_SRD_Pos 8 /*!< MPU RASR: Sub-Region Disable Position */ |
| emilmont | 62:7e6c9f46b3bd | 532 | #define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ |
| emilmont | 62:7e6c9f46b3bd | 533 | |
| emilmont | 62:7e6c9f46b3bd | 534 | #define MPU_RASR_SIZE_Pos 1 /*!< MPU RASR: Region Size Field Position */ |
| emilmont | 62:7e6c9f46b3bd | 535 | #define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ |
| emilmont | 62:7e6c9f46b3bd | 536 | |
| emilmont | 62:7e6c9f46b3bd | 537 | #define MPU_RASR_ENABLE_Pos 0 /*!< MPU RASR: Region enable bit Position */ |
| emilmont | 62:7e6c9f46b3bd | 538 | #define MPU_RASR_ENABLE_Msk (1UL << MPU_RASR_ENABLE_Pos) /*!< MPU RASR: Region enable bit Disable Mask */ |
| emilmont | 62:7e6c9f46b3bd | 539 | |
| emilmont | 62:7e6c9f46b3bd | 540 | /*@} end of group CMSIS_MPU */ |
| emilmont | 62:7e6c9f46b3bd | 541 | #endif |
| emilmont | 62:7e6c9f46b3bd | 542 | |
| emilmont | 62:7e6c9f46b3bd | 543 | |
| emilmont | 62:7e6c9f46b3bd | 544 | /** \ingroup CMSIS_core_register |
| emilmont | 62:7e6c9f46b3bd | 545 | \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) |
| emilmont | 62:7e6c9f46b3bd | 546 | \brief Cortex-M0+ Core Debug Registers (DCB registers, SHCSR, and DFSR) |
| emilmont | 62:7e6c9f46b3bd | 547 | are only accessible over DAP and not via processor. Therefore |
| emilmont | 62:7e6c9f46b3bd | 548 | they are not covered by the Cortex-M0 header file. |
| emilmont | 62:7e6c9f46b3bd | 549 | @{ |
| emilmont | 62:7e6c9f46b3bd | 550 | */ |
| emilmont | 62:7e6c9f46b3bd | 551 | /*@} end of group CMSIS_CoreDebug */ |
| emilmont | 62:7e6c9f46b3bd | 552 | |
| emilmont | 62:7e6c9f46b3bd | 553 | |
| emilmont | 62:7e6c9f46b3bd | 554 | /** \ingroup CMSIS_core_register |
| emilmont | 62:7e6c9f46b3bd | 555 | \defgroup CMSIS_core_base Core Definitions |
| emilmont | 62:7e6c9f46b3bd | 556 | \brief Definitions for base addresses, unions, and structures. |
| emilmont | 62:7e6c9f46b3bd | 557 | @{ |
| emilmont | 62:7e6c9f46b3bd | 558 | */ |
| emilmont | 62:7e6c9f46b3bd | 559 | |
| emilmont | 62:7e6c9f46b3bd | 560 | /* Memory mapping of Cortex-M0+ Hardware */ |
| emilmont | 62:7e6c9f46b3bd | 561 | #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ |
| emilmont | 62:7e6c9f46b3bd | 562 | #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ |
| emilmont | 62:7e6c9f46b3bd | 563 | #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ |
| emilmont | 62:7e6c9f46b3bd | 564 | #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ |
| emilmont | 62:7e6c9f46b3bd | 565 | |
| emilmont | 62:7e6c9f46b3bd | 566 | #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ |
| emilmont | 62:7e6c9f46b3bd | 567 | #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ |
| emilmont | 62:7e6c9f46b3bd | 568 | #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ |
| emilmont | 62:7e6c9f46b3bd | 569 | |
| emilmont | 62:7e6c9f46b3bd | 570 | #if (__MPU_PRESENT == 1) |
| emilmont | 62:7e6c9f46b3bd | 571 | #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ |
| emilmont | 62:7e6c9f46b3bd | 572 | #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ |
| emilmont | 62:7e6c9f46b3bd | 573 | #endif |
| emilmont | 62:7e6c9f46b3bd | 574 | |
| emilmont | 62:7e6c9f46b3bd | 575 | /*@} */ |
| emilmont | 62:7e6c9f46b3bd | 576 | |
| emilmont | 62:7e6c9f46b3bd | 577 | |
| emilmont | 62:7e6c9f46b3bd | 578 | |
| emilmont | 62:7e6c9f46b3bd | 579 | /******************************************************************************* |
| emilmont | 62:7e6c9f46b3bd | 580 | * Hardware Abstraction Layer |
| emilmont | 62:7e6c9f46b3bd | 581 | Core Function Interface contains: |
| emilmont | 62:7e6c9f46b3bd | 582 | - Core NVIC Functions |
| emilmont | 62:7e6c9f46b3bd | 583 | - Core SysTick Functions |
| emilmont | 62:7e6c9f46b3bd | 584 | - Core Register Access Functions |
| emilmont | 62:7e6c9f46b3bd | 585 | ******************************************************************************/ |
| emilmont | 62:7e6c9f46b3bd | 586 | /** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference |
| emilmont | 62:7e6c9f46b3bd | 587 | */ |
| emilmont | 62:7e6c9f46b3bd | 588 | |
| emilmont | 62:7e6c9f46b3bd | 589 | |
| emilmont | 62:7e6c9f46b3bd | 590 | |
| emilmont | 62:7e6c9f46b3bd | 591 | /* ########################## NVIC functions #################################### */ |
| emilmont | 62:7e6c9f46b3bd | 592 | /** \ingroup CMSIS_Core_FunctionInterface |
| emilmont | 62:7e6c9f46b3bd | 593 | \defgroup CMSIS_Core_NVICFunctions NVIC Functions |
| emilmont | 62:7e6c9f46b3bd | 594 | \brief Functions that manage interrupts and exceptions via the NVIC. |
| emilmont | 62:7e6c9f46b3bd | 595 | @{ |
| emilmont | 62:7e6c9f46b3bd | 596 | */ |
| emilmont | 62:7e6c9f46b3bd | 597 | |
| emilmont | 62:7e6c9f46b3bd | 598 | /* Interrupt Priorities are WORD accessible only under ARMv6M */ |
| emilmont | 62:7e6c9f46b3bd | 599 | /* The following MACROS handle generation of the register offset and byte masks */ |
| emilmont | 62:7e6c9f46b3bd | 600 | #define _BIT_SHIFT(IRQn) ( (((uint32_t)(IRQn) ) & 0x03) * 8 ) |
| emilmont | 62:7e6c9f46b3bd | 601 | #define _SHP_IDX(IRQn) ( ((((uint32_t)(IRQn) & 0x0F)-8) >> 2) ) |
| emilmont | 62:7e6c9f46b3bd | 602 | #define _IP_IDX(IRQn) ( ((uint32_t)(IRQn) >> 2) ) |
| emilmont | 62:7e6c9f46b3bd | 603 | |
| emilmont | 62:7e6c9f46b3bd | 604 | |
| emilmont | 62:7e6c9f46b3bd | 605 | /** \brief Enable External Interrupt |
| emilmont | 62:7e6c9f46b3bd | 606 | |
| emilmont | 62:7e6c9f46b3bd | 607 | The function enables a device-specific interrupt in the NVIC interrupt controller. |
| emilmont | 62:7e6c9f46b3bd | 608 | |
| emilmont | 62:7e6c9f46b3bd | 609 | \param [in] IRQn External interrupt number. Value cannot be negative. |
| emilmont | 62:7e6c9f46b3bd | 610 | */ |
| emilmont | 62:7e6c9f46b3bd | 611 | __STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn) |
| emilmont | 62:7e6c9f46b3bd | 612 | { |
| emilmont | 62:7e6c9f46b3bd | 613 | NVIC->ISER[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); |
| emilmont | 62:7e6c9f46b3bd | 614 | } |
| emilmont | 62:7e6c9f46b3bd | 615 | |
| emilmont | 62:7e6c9f46b3bd | 616 | |
| emilmont | 62:7e6c9f46b3bd | 617 | /** \brief Disable External Interrupt |
| emilmont | 62:7e6c9f46b3bd | 618 | |
| emilmont | 62:7e6c9f46b3bd | 619 | The function disables a device-specific interrupt in the NVIC interrupt controller. |
| emilmont | 62:7e6c9f46b3bd | 620 | |
| emilmont | 62:7e6c9f46b3bd | 621 | \param [in] IRQn External interrupt number. Value cannot be negative. |
| emilmont | 62:7e6c9f46b3bd | 622 | */ |
| emilmont | 62:7e6c9f46b3bd | 623 | __STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn) |
| emilmont | 62:7e6c9f46b3bd | 624 | { |
| emilmont | 62:7e6c9f46b3bd | 625 | NVIC->ICER[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); |
| emilmont | 62:7e6c9f46b3bd | 626 | } |
| emilmont | 62:7e6c9f46b3bd | 627 | |
| emilmont | 62:7e6c9f46b3bd | 628 | |
| emilmont | 62:7e6c9f46b3bd | 629 | /** \brief Get Pending Interrupt |
| emilmont | 62:7e6c9f46b3bd | 630 | |
| emilmont | 62:7e6c9f46b3bd | 631 | The function reads the pending register in the NVIC and returns the pending bit |
| emilmont | 62:7e6c9f46b3bd | 632 | for the specified interrupt. |
| emilmont | 62:7e6c9f46b3bd | 633 | |
| emilmont | 62:7e6c9f46b3bd | 634 | \param [in] IRQn Interrupt number. |
| emilmont | 62:7e6c9f46b3bd | 635 | |
| emilmont | 62:7e6c9f46b3bd | 636 | \return 0 Interrupt status is not pending. |
| emilmont | 62:7e6c9f46b3bd | 637 | \return 1 Interrupt status is pending. |
| emilmont | 62:7e6c9f46b3bd | 638 | */ |
| emilmont | 62:7e6c9f46b3bd | 639 | __STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn) |
| emilmont | 62:7e6c9f46b3bd | 640 | { |
| emilmont | 62:7e6c9f46b3bd | 641 | return((uint32_t) ((NVIC->ISPR[0] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); |
| emilmont | 62:7e6c9f46b3bd | 642 | } |
| emilmont | 62:7e6c9f46b3bd | 643 | |
| emilmont | 62:7e6c9f46b3bd | 644 | |
| emilmont | 62:7e6c9f46b3bd | 645 | /** \brief Set Pending Interrupt |
| emilmont | 62:7e6c9f46b3bd | 646 | |
| emilmont | 62:7e6c9f46b3bd | 647 | The function sets the pending bit of an external interrupt. |
| emilmont | 62:7e6c9f46b3bd | 648 | |
| emilmont | 62:7e6c9f46b3bd | 649 | \param [in] IRQn Interrupt number. Value cannot be negative. |
| emilmont | 62:7e6c9f46b3bd | 650 | */ |
| emilmont | 62:7e6c9f46b3bd | 651 | __STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn) |
| emilmont | 62:7e6c9f46b3bd | 652 | { |
| emilmont | 62:7e6c9f46b3bd | 653 | NVIC->ISPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); |
| emilmont | 62:7e6c9f46b3bd | 654 | } |
| emilmont | 62:7e6c9f46b3bd | 655 | |
| emilmont | 62:7e6c9f46b3bd | 656 | |
| emilmont | 62:7e6c9f46b3bd | 657 | /** \brief Clear Pending Interrupt |
| emilmont | 62:7e6c9f46b3bd | 658 | |
| emilmont | 62:7e6c9f46b3bd | 659 | The function clears the pending bit of an external interrupt. |
| emilmont | 62:7e6c9f46b3bd | 660 | |
| emilmont | 62:7e6c9f46b3bd | 661 | \param [in] IRQn External interrupt number. Value cannot be negative. |
| emilmont | 62:7e6c9f46b3bd | 662 | */ |
| emilmont | 62:7e6c9f46b3bd | 663 | __STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn) |
| emilmont | 62:7e6c9f46b3bd | 664 | { |
| emilmont | 62:7e6c9f46b3bd | 665 | NVIC->ICPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */ |
| emilmont | 62:7e6c9f46b3bd | 666 | } |
| emilmont | 62:7e6c9f46b3bd | 667 | |
| emilmont | 62:7e6c9f46b3bd | 668 | |
| emilmont | 62:7e6c9f46b3bd | 669 | /** \brief Set Interrupt Priority |
| emilmont | 62:7e6c9f46b3bd | 670 | |
| emilmont | 62:7e6c9f46b3bd | 671 | The function sets the priority of an interrupt. |
| emilmont | 62:7e6c9f46b3bd | 672 | |
| emilmont | 62:7e6c9f46b3bd | 673 | \note The priority cannot be set for every core interrupt. |
| emilmont | 62:7e6c9f46b3bd | 674 | |
| emilmont | 62:7e6c9f46b3bd | 675 | \param [in] IRQn Interrupt number. |
| emilmont | 62:7e6c9f46b3bd | 676 | \param [in] priority Priority to set. |
| emilmont | 62:7e6c9f46b3bd | 677 | */ |
| emilmont | 62:7e6c9f46b3bd | 678 | __STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) |
| emilmont | 62:7e6c9f46b3bd | 679 | { |
| emilmont | 62:7e6c9f46b3bd | 680 | if(IRQn < 0) { |
| emilmont | 62:7e6c9f46b3bd | 681 | SCB->SHP[_SHP_IDX(IRQn)] = (SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) | |
| emilmont | 62:7e6c9f46b3bd | 682 | (((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); } |
| emilmont | 62:7e6c9f46b3bd | 683 | else { |
| emilmont | 62:7e6c9f46b3bd | 684 | NVIC->IP[_IP_IDX(IRQn)] = (NVIC->IP[_IP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) | |
| emilmont | 62:7e6c9f46b3bd | 685 | (((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); } |
| emilmont | 62:7e6c9f46b3bd | 686 | } |
| emilmont | 62:7e6c9f46b3bd | 687 | |
| emilmont | 62:7e6c9f46b3bd | 688 | |
| emilmont | 62:7e6c9f46b3bd | 689 | /** \brief Get Interrupt Priority |
| emilmont | 62:7e6c9f46b3bd | 690 | |
| emilmont | 62:7e6c9f46b3bd | 691 | The function reads the priority of an interrupt. The interrupt |
| emilmont | 62:7e6c9f46b3bd | 692 | number can be positive to specify an external (device specific) |
| emilmont | 62:7e6c9f46b3bd | 693 | interrupt, or negative to specify an internal (core) interrupt. |
| emilmont | 62:7e6c9f46b3bd | 694 | |
| emilmont | 62:7e6c9f46b3bd | 695 | |
| emilmont | 62:7e6c9f46b3bd | 696 | \param [in] IRQn Interrupt number. |
| emilmont | 62:7e6c9f46b3bd | 697 | \return Interrupt Priority. Value is aligned automatically to the implemented |
| emilmont | 62:7e6c9f46b3bd | 698 | priority bits of the microcontroller. |
| emilmont | 62:7e6c9f46b3bd | 699 | */ |
| emilmont | 62:7e6c9f46b3bd | 700 | __STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn) |
| emilmont | 62:7e6c9f46b3bd | 701 | { |
| emilmont | 62:7e6c9f46b3bd | 702 | |
| emilmont | 62:7e6c9f46b3bd | 703 | if(IRQn < 0) { |
| emilmont | 62:7e6c9f46b3bd | 704 | return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & 0xFF) >> (8 - __NVIC_PRIO_BITS))); } /* get priority for Cortex-M0 system interrupts */ |
| emilmont | 62:7e6c9f46b3bd | 705 | else { |
| emilmont | 62:7e6c9f46b3bd | 706 | return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & 0xFF) >> (8 - __NVIC_PRIO_BITS))); } /* get priority for device specific interrupts */ |
| emilmont | 62:7e6c9f46b3bd | 707 | } |
| emilmont | 62:7e6c9f46b3bd | 708 | |
| emilmont | 62:7e6c9f46b3bd | 709 | |
| emilmont | 62:7e6c9f46b3bd | 710 | /** \brief System Reset |
| emilmont | 62:7e6c9f46b3bd | 711 | |
| emilmont | 62:7e6c9f46b3bd | 712 | The function initiates a system reset request to reset the MCU. |
| emilmont | 62:7e6c9f46b3bd | 713 | */ |
| emilmont | 62:7e6c9f46b3bd | 714 | __STATIC_INLINE void NVIC_SystemReset(void) |
| emilmont | 62:7e6c9f46b3bd | 715 | { |
| emilmont | 62:7e6c9f46b3bd | 716 | __DSB(); /* Ensure all outstanding memory accesses included |
| emilmont | 62:7e6c9f46b3bd | 717 | buffered write are completed before reset */ |
| emilmont | 62:7e6c9f46b3bd | 718 | SCB->AIRCR = ((0x5FA << SCB_AIRCR_VECTKEY_Pos) | |
| emilmont | 62:7e6c9f46b3bd | 719 | SCB_AIRCR_SYSRESETREQ_Msk); |
| emilmont | 62:7e6c9f46b3bd | 720 | __DSB(); /* Ensure completion of memory access */ |
| emilmont | 62:7e6c9f46b3bd | 721 | while(1); /* wait until reset */ |
| emilmont | 62:7e6c9f46b3bd | 722 | } |
| emilmont | 62:7e6c9f46b3bd | 723 | |
| emilmont | 62:7e6c9f46b3bd | 724 | /*@} end of CMSIS_Core_NVICFunctions */ |
| emilmont | 62:7e6c9f46b3bd | 725 | |
| emilmont | 62:7e6c9f46b3bd | 726 | |
| emilmont | 62:7e6c9f46b3bd | 727 | |
| emilmont | 62:7e6c9f46b3bd | 728 | /* ################################## SysTick function ############################################ */ |
| emilmont | 62:7e6c9f46b3bd | 729 | /** \ingroup CMSIS_Core_FunctionInterface |
| emilmont | 62:7e6c9f46b3bd | 730 | \defgroup CMSIS_Core_SysTickFunctions SysTick Functions |
| emilmont | 62:7e6c9f46b3bd | 731 | \brief Functions that configure the System. |
| emilmont | 62:7e6c9f46b3bd | 732 | @{ |
| emilmont | 62:7e6c9f46b3bd | 733 | */ |
| emilmont | 62:7e6c9f46b3bd | 734 | |
| emilmont | 62:7e6c9f46b3bd | 735 | #if (__Vendor_SysTickConfig == 0) |
| emilmont | 62:7e6c9f46b3bd | 736 | |
| emilmont | 62:7e6c9f46b3bd | 737 | /** \brief System Tick Configuration |
| emilmont | 62:7e6c9f46b3bd | 738 | |
| emilmont | 62:7e6c9f46b3bd | 739 | The function initializes the System Timer and its interrupt, and starts the System Tick Timer. |
| emilmont | 62:7e6c9f46b3bd | 740 | Counter is in free running mode to generate periodic interrupts. |
| emilmont | 62:7e6c9f46b3bd | 741 | |
| emilmont | 62:7e6c9f46b3bd | 742 | \param [in] ticks Number of ticks between two interrupts. |
| emilmont | 62:7e6c9f46b3bd | 743 | |
| emilmont | 62:7e6c9f46b3bd | 744 | \return 0 Function succeeded. |
| emilmont | 62:7e6c9f46b3bd | 745 | \return 1 Function failed. |
| emilmont | 62:7e6c9f46b3bd | 746 | |
| emilmont | 62:7e6c9f46b3bd | 747 | \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the |
| emilmont | 62:7e6c9f46b3bd | 748 | function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b> |
| emilmont | 62:7e6c9f46b3bd | 749 | must contain a vendor-specific implementation of this function. |
| emilmont | 62:7e6c9f46b3bd | 750 | |
| emilmont | 62:7e6c9f46b3bd | 751 | */ |
| emilmont | 62:7e6c9f46b3bd | 752 | __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) |
| emilmont | 62:7e6c9f46b3bd | 753 | { |
| emilmont | 62:7e6c9f46b3bd | 754 | if ((ticks - 1) > SysTick_LOAD_RELOAD_Msk) return (1); /* Reload value impossible */ |
| emilmont | 62:7e6c9f46b3bd | 755 | |
| emilmont | 62:7e6c9f46b3bd | 756 | SysTick->LOAD = ticks - 1; /* set reload register */ |
| emilmont | 62:7e6c9f46b3bd | 757 | NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1); /* set Priority for Systick Interrupt */ |
| emilmont | 62:7e6c9f46b3bd | 758 | SysTick->VAL = 0; /* Load the SysTick Counter Value */ |
| emilmont | 62:7e6c9f46b3bd | 759 | SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | |
| emilmont | 62:7e6c9f46b3bd | 760 | SysTick_CTRL_TICKINT_Msk | |
| emilmont | 62:7e6c9f46b3bd | 761 | SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ |
| emilmont | 62:7e6c9f46b3bd | 762 | return (0); /* Function successful */ |
| emilmont | 62:7e6c9f46b3bd | 763 | } |
| emilmont | 62:7e6c9f46b3bd | 764 | |
| emilmont | 62:7e6c9f46b3bd | 765 | #endif |
| emilmont | 62:7e6c9f46b3bd | 766 | |
| emilmont | 62:7e6c9f46b3bd | 767 | /*@} end of CMSIS_Core_SysTickFunctions */ |
| emilmont | 62:7e6c9f46b3bd | 768 | |
| emilmont | 62:7e6c9f46b3bd | 769 | |
| emilmont | 62:7e6c9f46b3bd | 770 | |
| emilmont | 62:7e6c9f46b3bd | 771 | |
| emilmont | 62:7e6c9f46b3bd | 772 | #endif /* __CORE_CM0PLUS_H_DEPENDANT */ |
| emilmont | 62:7e6c9f46b3bd | 773 | |
| emilmont | 62:7e6c9f46b3bd | 774 | #endif /* __CMSIS_GENERIC */ |
| emilmont | 62:7e6c9f46b3bd | 775 | |
| emilmont | 62:7e6c9f46b3bd | 776 | #ifdef __cplusplus |
| emilmont | 62:7e6c9f46b3bd | 777 | } |
| emilmont | 62:7e6c9f46b3bd | 778 | #endif |