雄介 太田 / mbed

mbed(SerialHalfDuplex入り)

Fork of mbed by mbed official

TARGET_ARCH_MAX/stm32f4xx_hal_spi.h@89:552587b429a1, 2014-09-12 (annotated)

Committer:
bogdanm
Date:
Fri Sep 12 16:41:52 2014 +0100
Revision:
89:552587b429a1
Child:
92:4fc01daae5a5
Release 89 of the mbed library



Main changes:



- low power optimizations for Nordic targets

- code structure changes for Freescale K64F targets

- bug fixes in various backends

Who changed what in which revision?

UserRevisionLine numberNew contents of line
bogdanm 89:552587b429a1 1 /**
bogdanm 89:552587b429a1 2 ******************************************************************************
bogdanm 89:552587b429a1 3 * @file stm32f4xx_hal_spi.h
bogdanm 89:552587b429a1 4 * @author MCD Application Team
bogdanm 89:552587b429a1 5 * @version V1.1.0RC2
bogdanm 89:552587b429a1 6 * @date 14-May-2014
bogdanm 89:552587b429a1 7 * @brief Header file of SPI HAL module.
bogdanm 89:552587b429a1 8 ******************************************************************************
bogdanm 89:552587b429a1 9 * @attention
bogdanm 89:552587b429a1 10 *
bogdanm 89:552587b429a1 11 * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
bogdanm 89:552587b429a1 12 *
bogdanm 89:552587b429a1 13 * Redistribution and use in source and binary forms, with or without modification,
bogdanm 89:552587b429a1 14 * are permitted provided that the following conditions are met:
bogdanm 89:552587b429a1 15 * 1. Redistributions of source code must retain the above copyright notice,
bogdanm 89:552587b429a1 16 * this list of conditions and the following disclaimer.
bogdanm 89:552587b429a1 17 * 2. Redistributions in binary form must reproduce the above copyright notice,
bogdanm 89:552587b429a1 18 * this list of conditions and the following disclaimer in the documentation
bogdanm 89:552587b429a1 19 * and/or other materials provided with the distribution.
bogdanm 89:552587b429a1 20 * 3. Neither the name of STMicroelectronics nor the names of its contributors
bogdanm 89:552587b429a1 21 * may be used to endorse or promote products derived from this software
bogdanm 89:552587b429a1 22 * without specific prior written permission.
bogdanm 89:552587b429a1 23 *
bogdanm 89:552587b429a1 24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
bogdanm 89:552587b429a1 25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
bogdanm 89:552587b429a1 26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
bogdanm 89:552587b429a1 27 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
bogdanm 89:552587b429a1 28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
bogdanm 89:552587b429a1 29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
bogdanm 89:552587b429a1 30 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
bogdanm 89:552587b429a1 31 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
bogdanm 89:552587b429a1 32 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
bogdanm 89:552587b429a1 33 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
bogdanm 89:552587b429a1 34 *
bogdanm 89:552587b429a1 35 ******************************************************************************
bogdanm 89:552587b429a1 36 */
bogdanm 89:552587b429a1 37
bogdanm 89:552587b429a1 38 /* Define to prevent recursive inclusion -------------------------------------*/
bogdanm 89:552587b429a1 39 #ifndef __STM32F4xx_HAL_SPI_H
bogdanm 89:552587b429a1 40 #define __STM32F4xx_HAL_SPI_H
bogdanm 89:552587b429a1 41
bogdanm 89:552587b429a1 42 #ifdef __cplusplus
bogdanm 89:552587b429a1 43 extern "C" {
bogdanm 89:552587b429a1 44 #endif
bogdanm 89:552587b429a1 45
bogdanm 89:552587b429a1 46 /* Includes ------------------------------------------------------------------*/
bogdanm 89:552587b429a1 47 #include "stm32f4xx_hal_def.h"
bogdanm 89:552587b429a1 48
bogdanm 89:552587b429a1 49 /** @addtogroup STM32F4xx_HAL_Driver
bogdanm 89:552587b429a1 50 * @{
bogdanm 89:552587b429a1 51 */
bogdanm 89:552587b429a1 52
bogdanm 89:552587b429a1 53 /** @addtogroup SPI
bogdanm 89:552587b429a1 54 * @{
bogdanm 89:552587b429a1 55 */
bogdanm 89:552587b429a1 56
bogdanm 89:552587b429a1 57 /* Exported types ------------------------------------------------------------*/
bogdanm 89:552587b429a1 58
bogdanm 89:552587b429a1 59 /**
bogdanm 89:552587b429a1 60 * @brief SPI Configuration Structure definition
bogdanm 89:552587b429a1 61 */
bogdanm 89:552587b429a1 62 typedef struct
bogdanm 89:552587b429a1 63 {
bogdanm 89:552587b429a1 64 uint32_t Mode; /*!< Specifies the SPI operating mode.
bogdanm 89:552587b429a1 65 This parameter can be a value of @ref SPI_mode */
bogdanm 89:552587b429a1 66
bogdanm 89:552587b429a1 67 uint32_t Direction; /*!< Specifies the SPI Directional mode state.
bogdanm 89:552587b429a1 68 This parameter can be a value of @ref SPI_Direction_mode */
bogdanm 89:552587b429a1 69
bogdanm 89:552587b429a1 70 uint32_t DataSize; /*!< Specifies the SPI data size.
bogdanm 89:552587b429a1 71 This parameter can be a value of @ref SPI_data_size */
bogdanm 89:552587b429a1 72
bogdanm 89:552587b429a1 73 uint32_t CLKPolarity; /*!< Specifies the serial clock steady state.
bogdanm 89:552587b429a1 74 This parameter can be a value of @ref SPI_Clock_Polarity */
bogdanm 89:552587b429a1 75
bogdanm 89:552587b429a1 76 uint32_t CLKPhase; /*!< Specifies the clock active edge for the bit capture.
bogdanm 89:552587b429a1 77 This parameter can be a value of @ref SPI_Clock_Phase */
bogdanm 89:552587b429a1 78
bogdanm 89:552587b429a1 79 uint32_t NSS; /*!< Specifies whether the NSS signal is managed by
bogdanm 89:552587b429a1 80 hardware (NSS pin) or by software using the SSI bit.
bogdanm 89:552587b429a1 81 This parameter can be a value of @ref SPI_Slave_Select_management */
bogdanm 89:552587b429a1 82
bogdanm 89:552587b429a1 83 uint32_t BaudRatePrescaler; /*!< Specifies the Baud Rate prescaler value which will be
bogdanm 89:552587b429a1 84 used to configure the transmit and receive SCK clock.
bogdanm 89:552587b429a1 85 This parameter can be a value of @ref SPI_BaudRate_Prescaler
bogdanm 89:552587b429a1 86 @note The communication clock is derived from the master
bogdanm 89:552587b429a1 87 clock. The slave clock does not need to be set */
bogdanm 89:552587b429a1 88
bogdanm 89:552587b429a1 89 uint32_t FirstBit; /*!< Specifies whether data transfers start from MSB or LSB bit.
bogdanm 89:552587b429a1 90 This parameter can be a value of @ref SPI_MSB_LSB_transmission */
bogdanm 89:552587b429a1 91
bogdanm 89:552587b429a1 92 uint32_t TIMode; /*!< Specifies if the TI mode is enabled or not.
bogdanm 89:552587b429a1 93 This parameter can be a value of @ref SPI_TI_mode */
bogdanm 89:552587b429a1 94
bogdanm 89:552587b429a1 95 uint32_t CRCCalculation; /*!< Specifies if the CRC calculation is enabled or not.
bogdanm 89:552587b429a1 96 This parameter can be a value of @ref SPI_CRC_Calculation */
bogdanm 89:552587b429a1 97
bogdanm 89:552587b429a1 98 uint32_t CRCPolynomial; /*!< Specifies the polynomial used for the CRC calculation.
bogdanm 89:552587b429a1 99 This parameter must be a number between Min_Data = 0 and Max_Data = 65535 */
bogdanm 89:552587b429a1 100
bogdanm 89:552587b429a1 101 }SPI_InitTypeDef;
bogdanm 89:552587b429a1 102
bogdanm 89:552587b429a1 103 /**
bogdanm 89:552587b429a1 104 * @brief HAL SPI State structure definition
bogdanm 89:552587b429a1 105 */
bogdanm 89:552587b429a1 106 typedef enum
bogdanm 89:552587b429a1 107 {
bogdanm 89:552587b429a1 108 HAL_SPI_STATE_RESET = 0x00, /*!< SPI not yet initialized or disabled */
bogdanm 89:552587b429a1 109 HAL_SPI_STATE_READY = 0x01, /*!< SPI initialized and ready for use */
bogdanm 89:552587b429a1 110 HAL_SPI_STATE_BUSY = 0x02, /*!< SPI process is ongoing */
bogdanm 89:552587b429a1 111 HAL_SPI_STATE_BUSY_TX = 0x12, /*!< Data Transmission process is ongoing */
bogdanm 89:552587b429a1 112 HAL_SPI_STATE_BUSY_RX = 0x22, /*!< Data Reception process is ongoing */
bogdanm 89:552587b429a1 113 HAL_SPI_STATE_BUSY_TX_RX = 0x32, /*!< Data Transmission and Reception process is ongoing */
bogdanm 89:552587b429a1 114 HAL_SPI_STATE_ERROR = 0x03 /*!< SPI error state */
bogdanm 89:552587b429a1 115
bogdanm 89:552587b429a1 116 }HAL_SPI_StateTypeDef;
bogdanm 89:552587b429a1 117
bogdanm 89:552587b429a1 118 /**
bogdanm 89:552587b429a1 119 * @brief HAL SPI Error Code structure definition
bogdanm 89:552587b429a1 120 */
bogdanm 89:552587b429a1 121 typedef enum
bogdanm 89:552587b429a1 122 {
bogdanm 89:552587b429a1 123 HAL_SPI_ERROR_NONE = 0x00, /*!< No error */
bogdanm 89:552587b429a1 124 HAL_SPI_ERROR_MODF = 0x01, /*!< MODF error */
bogdanm 89:552587b429a1 125 HAL_SPI_ERROR_CRC = 0x02, /*!< CRC error */
bogdanm 89:552587b429a1 126 HAL_SPI_ERROR_OVR = 0x04, /*!< OVR error */
bogdanm 89:552587b429a1 127 HAL_SPI_ERROR_FRE = 0x08, /*!< FRE error */
bogdanm 89:552587b429a1 128 HAL_SPI_ERROR_DMA = 0x10, /*!< DMA transfer error */
bogdanm 89:552587b429a1 129 HAL_SPI_ERROR_FLAG = 0x20 /*!< Flag: RXNE,TXE, BSY */
bogdanm 89:552587b429a1 130
bogdanm 89:552587b429a1 131 }HAL_SPI_ErrorTypeDef;
bogdanm 89:552587b429a1 132
bogdanm 89:552587b429a1 133 /**
bogdanm 89:552587b429a1 134 * @brief SPI handle Structure definition
bogdanm 89:552587b429a1 135 */
bogdanm 89:552587b429a1 136 typedef struct __SPI_HandleTypeDef
bogdanm 89:552587b429a1 137 {
bogdanm 89:552587b429a1 138 SPI_TypeDef *Instance; /* SPI registers base address */
bogdanm 89:552587b429a1 139
bogdanm 89:552587b429a1 140 SPI_InitTypeDef Init; /* SPI communication parameters */
bogdanm 89:552587b429a1 141
bogdanm 89:552587b429a1 142 uint8_t *pTxBuffPtr; /* Pointer to SPI Tx transfer Buffer */
bogdanm 89:552587b429a1 143
bogdanm 89:552587b429a1 144 uint16_t TxXferSize; /* SPI Tx transfer size */
bogdanm 89:552587b429a1 145
bogdanm 89:552587b429a1 146 uint16_t TxXferCount; /* SPI Tx Transfer Counter */
bogdanm 89:552587b429a1 147
bogdanm 89:552587b429a1 148 uint8_t *pRxBuffPtr; /* Pointer to SPI Rx transfer Buffer */
bogdanm 89:552587b429a1 149
bogdanm 89:552587b429a1 150 uint16_t RxXferSize; /* SPI Rx transfer size */
bogdanm 89:552587b429a1 151
bogdanm 89:552587b429a1 152 uint16_t RxXferCount; /* SPI Rx Transfer Counter */
bogdanm 89:552587b429a1 153
bogdanm 89:552587b429a1 154 DMA_HandleTypeDef *hdmatx; /* SPI Tx DMA handle parameters */
bogdanm 89:552587b429a1 155
bogdanm 89:552587b429a1 156 DMA_HandleTypeDef *hdmarx; /* SPI Rx DMA handle parameters */
bogdanm 89:552587b429a1 157
bogdanm 89:552587b429a1 158 void (*RxISR)(struct __SPI_HandleTypeDef * hspi); /* function pointer on Rx ISR */
bogdanm 89:552587b429a1 159
bogdanm 89:552587b429a1 160 void (*TxISR)(struct __SPI_HandleTypeDef * hspi); /* function pointer on Tx ISR */
bogdanm 89:552587b429a1 161
bogdanm 89:552587b429a1 162 HAL_LockTypeDef Lock; /* SPI locking object */
bogdanm 89:552587b429a1 163
bogdanm 89:552587b429a1 164 __IO HAL_SPI_StateTypeDef State; /* SPI communication state */
bogdanm 89:552587b429a1 165
bogdanm 89:552587b429a1 166 __IO HAL_SPI_ErrorTypeDef ErrorCode; /* SPI Error code */
bogdanm 89:552587b429a1 167
bogdanm 89:552587b429a1 168 }SPI_HandleTypeDef;
bogdanm 89:552587b429a1 169
bogdanm 89:552587b429a1 170 /* Exported constants --------------------------------------------------------*/
bogdanm 89:552587b429a1 171
bogdanm 89:552587b429a1 172 /** @defgroup SPI_Exported_Constants
bogdanm 89:552587b429a1 173 * @{
bogdanm 89:552587b429a1 174 */
bogdanm 89:552587b429a1 175
bogdanm 89:552587b429a1 176 /** @defgroup SPI_mode
bogdanm 89:552587b429a1 177 * @{
bogdanm 89:552587b429a1 178 */
bogdanm 89:552587b429a1 179 #define SPI_MODE_SLAVE ((uint32_t)0x00000000)
bogdanm 89:552587b429a1 180 #define SPI_MODE_MASTER (SPI_CR1_MSTR | SPI_CR1_SSI)
bogdanm 89:552587b429a1 181
bogdanm 89:552587b429a1 182 #define IS_SPI_MODE(MODE) (((MODE) == SPI_MODE_SLAVE) || \
bogdanm 89:552587b429a1 183 ((MODE) == SPI_MODE_MASTER))
bogdanm 89:552587b429a1 184 /**
bogdanm 89:552587b429a1 185 * @}
bogdanm 89:552587b429a1 186 */
bogdanm 89:552587b429a1 187
bogdanm 89:552587b429a1 188 /** @defgroup SPI_Direction_mode
bogdanm 89:552587b429a1 189 * @{
bogdanm 89:552587b429a1 190 */
bogdanm 89:552587b429a1 191 #define SPI_DIRECTION_2LINES ((uint32_t)0x00000000)
bogdanm 89:552587b429a1 192 #define SPI_DIRECTION_2LINES_RXONLY SPI_CR1_RXONLY
bogdanm 89:552587b429a1 193 #define SPI_DIRECTION_1LINE SPI_CR1_BIDIMODE
bogdanm 89:552587b429a1 194
bogdanm 89:552587b429a1 195 #define IS_SPI_DIRECTION_MODE(MODE) (((MODE) == SPI_DIRECTION_2LINES) || \
bogdanm 89:552587b429a1 196 ((MODE) == SPI_DIRECTION_2LINES_RXONLY) || \
bogdanm 89:552587b429a1 197 ((MODE) == SPI_DIRECTION_1LINE))
bogdanm 89:552587b429a1 198
bogdanm 89:552587b429a1 199 #define IS_SPI_DIRECTION_2LINES_OR_1LINE(MODE) (((MODE) == SPI_DIRECTION_2LINES) || \
bogdanm 89:552587b429a1 200 ((MODE) == SPI_DIRECTION_1LINE))
bogdanm 89:552587b429a1 201
bogdanm 89:552587b429a1 202 #define IS_SPI_DIRECTION_2LINES(MODE) ((MODE) == SPI_DIRECTION_2LINES)
bogdanm 89:552587b429a1 203
bogdanm 89:552587b429a1 204 /**
bogdanm 89:552587b429a1 205 * @}
bogdanm 89:552587b429a1 206 */
bogdanm 89:552587b429a1 207
bogdanm 89:552587b429a1 208 /** @defgroup SPI_data_size
bogdanm 89:552587b429a1 209 * @{
bogdanm 89:552587b429a1 210 */
bogdanm 89:552587b429a1 211 #define SPI_DATASIZE_8BIT ((uint32_t)0x00000000)
bogdanm 89:552587b429a1 212 #define SPI_DATASIZE_16BIT SPI_CR1_DFF
bogdanm 89:552587b429a1 213
bogdanm 89:552587b429a1 214 #define IS_SPI_DATASIZE(DATASIZE) (((DATASIZE) == SPI_DATASIZE_16BIT) || \
bogdanm 89:552587b429a1 215 ((DATASIZE) == SPI_DATASIZE_8BIT))
bogdanm 89:552587b429a1 216 /**
bogdanm 89:552587b429a1 217 * @}
bogdanm 89:552587b429a1 218 */
bogdanm 89:552587b429a1 219
bogdanm 89:552587b429a1 220 /** @defgroup SPI_Clock_Polarity
bogdanm 89:552587b429a1 221 * @{
bogdanm 89:552587b429a1 222 */
bogdanm 89:552587b429a1 223 #define SPI_POLARITY_LOW ((uint32_t)0x00000000)
bogdanm 89:552587b429a1 224 #define SPI_POLARITY_HIGH SPI_CR1_CPOL
bogdanm 89:552587b429a1 225
bogdanm 89:552587b429a1 226 #define IS_SPI_CPOL(CPOL) (((CPOL) == SPI_POLARITY_LOW) || \
bogdanm 89:552587b429a1 227 ((CPOL) == SPI_POLARITY_HIGH))
bogdanm 89:552587b429a1 228 /**
bogdanm 89:552587b429a1 229 * @}
bogdanm 89:552587b429a1 230 */
bogdanm 89:552587b429a1 231
bogdanm 89:552587b429a1 232 /** @defgroup SPI_Clock_Phase
bogdanm 89:552587b429a1 233 * @{
bogdanm 89:552587b429a1 234 */
bogdanm 89:552587b429a1 235 #define SPI_PHASE_1EDGE ((uint32_t)0x00000000)
bogdanm 89:552587b429a1 236 #define SPI_PHASE_2EDGE SPI_CR1_CPHA
bogdanm 89:552587b429a1 237
bogdanm 89:552587b429a1 238 #define IS_SPI_CPHA(CPHA) (((CPHA) == SPI_PHASE_1EDGE) || \
bogdanm 89:552587b429a1 239 ((CPHA) == SPI_PHASE_2EDGE))
bogdanm 89:552587b429a1 240 /**
bogdanm 89:552587b429a1 241 * @}
bogdanm 89:552587b429a1 242 */
bogdanm 89:552587b429a1 243
bogdanm 89:552587b429a1 244 /** @defgroup SPI_Slave_Select_management
bogdanm 89:552587b429a1 245 * @{
bogdanm 89:552587b429a1 246 */
bogdanm 89:552587b429a1 247 #define SPI_NSS_SOFT SPI_CR1_SSM
bogdanm 89:552587b429a1 248 #define SPI_NSS_HARD_INPUT ((uint32_t)0x00000000)
bogdanm 89:552587b429a1 249 #define SPI_NSS_HARD_OUTPUT ((uint32_t)0x00040000)
bogdanm 89:552587b429a1 250
bogdanm 89:552587b429a1 251 #define IS_SPI_NSS(NSS) (((NSS) == SPI_NSS_SOFT) || \
bogdanm 89:552587b429a1 252 ((NSS) == SPI_NSS_HARD_INPUT) || \
bogdanm 89:552587b429a1 253 ((NSS) == SPI_NSS_HARD_OUTPUT))
bogdanm 89:552587b429a1 254 /**
bogdanm 89:552587b429a1 255 * @}
bogdanm 89:552587b429a1 256 */
bogdanm 89:552587b429a1 257
bogdanm 89:552587b429a1 258 /** @defgroup SPI_BaudRate_Prescaler
bogdanm 89:552587b429a1 259 * @{
bogdanm 89:552587b429a1 260 */
bogdanm 89:552587b429a1 261 #define SPI_BAUDRATEPRESCALER_2 ((uint32_t)0x00000000)
bogdanm 89:552587b429a1 262 #define SPI_BAUDRATEPRESCALER_4 ((uint32_t)0x00000008)
bogdanm 89:552587b429a1 263 #define SPI_BAUDRATEPRESCALER_8 ((uint32_t)0x00000010)
bogdanm 89:552587b429a1 264 #define SPI_BAUDRATEPRESCALER_16 ((uint32_t)0x00000018)
bogdanm 89:552587b429a1 265 #define SPI_BAUDRATEPRESCALER_32 ((uint32_t)0x00000020)
bogdanm 89:552587b429a1 266 #define SPI_BAUDRATEPRESCALER_64 ((uint32_t)0x00000028)
bogdanm 89:552587b429a1 267 #define SPI_BAUDRATEPRESCALER_128 ((uint32_t)0x00000030)
bogdanm 89:552587b429a1 268 #define SPI_BAUDRATEPRESCALER_256 ((uint32_t)0x00000038)
bogdanm 89:552587b429a1 269
bogdanm 89:552587b429a1 270 #define IS_SPI_BAUDRATE_PRESCALER(PRESCALER) (((PRESCALER) == SPI_BAUDRATEPRESCALER_2) || \
bogdanm 89:552587b429a1 271 ((PRESCALER) == SPI_BAUDRATEPRESCALER_4) || \
bogdanm 89:552587b429a1 272 ((PRESCALER) == SPI_BAUDRATEPRESCALER_8) || \
bogdanm 89:552587b429a1 273 ((PRESCALER) == SPI_BAUDRATEPRESCALER_16) || \
bogdanm 89:552587b429a1 274 ((PRESCALER) == SPI_BAUDRATEPRESCALER_32) || \
bogdanm 89:552587b429a1 275 ((PRESCALER) == SPI_BAUDRATEPRESCALER_64) || \
bogdanm 89:552587b429a1 276 ((PRESCALER) == SPI_BAUDRATEPRESCALER_128) || \
bogdanm 89:552587b429a1 277 ((PRESCALER) == SPI_BAUDRATEPRESCALER_256))
bogdanm 89:552587b429a1 278 /**
bogdanm 89:552587b429a1 279 * @}
bogdanm 89:552587b429a1 280 */
bogdanm 89:552587b429a1 281
bogdanm 89:552587b429a1 282 /** @defgroup SPI_MSB_LSB_transmission
bogdanm 89:552587b429a1 283 * @{
bogdanm 89:552587b429a1 284 */
bogdanm 89:552587b429a1 285 #define SPI_FIRSTBIT_MSB ((uint32_t)0x00000000)
bogdanm 89:552587b429a1 286 #define SPI_FIRSTBIT_LSB SPI_CR1_LSBFIRST
bogdanm 89:552587b429a1 287
bogdanm 89:552587b429a1 288 #define IS_SPI_FIRST_BIT(BIT) (((BIT) == SPI_FIRSTBIT_MSB) || \
bogdanm 89:552587b429a1 289 ((BIT) == SPI_FIRSTBIT_LSB))
bogdanm 89:552587b429a1 290 /**
bogdanm 89:552587b429a1 291 * @}
bogdanm 89:552587b429a1 292 */
bogdanm 89:552587b429a1 293
bogdanm 89:552587b429a1 294 /** @defgroup SPI_TI_mode
bogdanm 89:552587b429a1 295 * @{
bogdanm 89:552587b429a1 296 */
bogdanm 89:552587b429a1 297 #define SPI_TIMODE_DISABLED ((uint32_t)0x00000000)
bogdanm 89:552587b429a1 298 #define SPI_TIMODE_ENABLED SPI_CR2_FRF
bogdanm 89:552587b429a1 299
bogdanm 89:552587b429a1 300 #define IS_SPI_TIMODE(MODE) (((MODE) == SPI_TIMODE_DISABLED) || \
bogdanm 89:552587b429a1 301 ((MODE) == SPI_TIMODE_ENABLED))
bogdanm 89:552587b429a1 302 /**
bogdanm 89:552587b429a1 303 * @}
bogdanm 89:552587b429a1 304 */
bogdanm 89:552587b429a1 305
bogdanm 89:552587b429a1 306 /** @defgroup SPI_CRC_Calculation
bogdanm 89:552587b429a1 307 * @{
bogdanm 89:552587b429a1 308 */
bogdanm 89:552587b429a1 309 #define SPI_CRCCALCULATION_DISABLED ((uint32_t)0x00000000)
bogdanm 89:552587b429a1 310 #define SPI_CRCCALCULATION_ENABLED SPI_CR1_CRCEN
bogdanm 89:552587b429a1 311
bogdanm 89:552587b429a1 312 #define IS_SPI_CRC_CALCULATION(CALCULATION) (((CALCULATION) == SPI_CRCCALCULATION_DISABLED) || \
bogdanm 89:552587b429a1 313 ((CALCULATION) == SPI_CRCCALCULATION_ENABLED))
bogdanm 89:552587b429a1 314 /**
bogdanm 89:552587b429a1 315 * @}
bogdanm 89:552587b429a1 316 */
bogdanm 89:552587b429a1 317
bogdanm 89:552587b429a1 318 /** @defgroup SPI_Interrupt_configuration_definition
bogdanm 89:552587b429a1 319 * @{
bogdanm 89:552587b429a1 320 */
bogdanm 89:552587b429a1 321 #define SPI_IT_TXE SPI_CR2_TXEIE
bogdanm 89:552587b429a1 322 #define SPI_IT_RXNE SPI_CR2_RXNEIE
bogdanm 89:552587b429a1 323 #define SPI_IT_ERR SPI_CR2_ERRIE
bogdanm 89:552587b429a1 324 /**
bogdanm 89:552587b429a1 325 * @}
bogdanm 89:552587b429a1 326 */
bogdanm 89:552587b429a1 327
bogdanm 89:552587b429a1 328 /** @defgroup SPI_Flag_definition
bogdanm 89:552587b429a1 329 * @{
bogdanm 89:552587b429a1 330 */
bogdanm 89:552587b429a1 331 #define SPI_FLAG_RXNE SPI_SR_RXNE
bogdanm 89:552587b429a1 332 #define SPI_FLAG_TXE SPI_SR_TXE
bogdanm 89:552587b429a1 333 #define SPI_FLAG_CRCERR SPI_SR_CRCERR
bogdanm 89:552587b429a1 334 #define SPI_FLAG_MODF SPI_SR_MODF
bogdanm 89:552587b429a1 335 #define SPI_FLAG_OVR SPI_SR_OVR
bogdanm 89:552587b429a1 336 #define SPI_FLAG_BSY SPI_SR_BSY
bogdanm 89:552587b429a1 337 #define SPI_FLAG_FRE SPI_SR_FRE
bogdanm 89:552587b429a1 338
bogdanm 89:552587b429a1 339 /**
bogdanm 89:552587b429a1 340 * @}
bogdanm 89:552587b429a1 341 */
bogdanm 89:552587b429a1 342
bogdanm 89:552587b429a1 343 /**
bogdanm 89:552587b429a1 344 * @}
bogdanm 89:552587b429a1 345 */
bogdanm 89:552587b429a1 346
bogdanm 89:552587b429a1 347 /* Exported macro ------------------------------------------------------------*/
bogdanm 89:552587b429a1 348
bogdanm 89:552587b429a1 349 /** @brief Reset SPI handle state
bogdanm 89:552587b429a1 350 * @param __HANDLE__: specifies the SPI handle.
bogdanm 89:552587b429a1 351 * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
bogdanm 89:552587b429a1 352 * @retval None
bogdanm 89:552587b429a1 353 */
bogdanm 89:552587b429a1 354 #define __HAL_SPI_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_SPI_STATE_RESET)
bogdanm 89:552587b429a1 355
bogdanm 89:552587b429a1 356 /** @brief Enable or disable the specified SPI interrupts.
bogdanm 89:552587b429a1 357 * @param __HANDLE__: specifies the SPI handle.
bogdanm 89:552587b429a1 358 * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
bogdanm 89:552587b429a1 359 * @param __INTERRUPT__: specifies the interrupt source to enable or disable.
bogdanm 89:552587b429a1 360 * This parameter can be one of the following values:
bogdanm 89:552587b429a1 361 * @arg SPI_IT_TXE: Tx buffer empty interrupt enable
bogdanm 89:552587b429a1 362 * @arg SPI_IT_RXNE: RX buffer not empty interrupt enable
bogdanm 89:552587b429a1 363 * @arg SPI_IT_ERR: Error interrupt enable
bogdanm 89:552587b429a1 364 * @retval None
bogdanm 89:552587b429a1 365 */
bogdanm 89:552587b429a1 366 #define __HAL_SPI_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR2 |= (__INTERRUPT__))
bogdanm 89:552587b429a1 367 #define __HAL_SPI_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR2 &= (~(__INTERRUPT__)))
bogdanm 89:552587b429a1 368
bogdanm 89:552587b429a1 369 /** @brief Check if the specified SPI interrupt source is enabled or disabled.
bogdanm 89:552587b429a1 370 * @param __HANDLE__: specifies the SPI handle.
bogdanm 89:552587b429a1 371 * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
bogdanm 89:552587b429a1 372 * @param __INTERRUPT__: specifies the SPI interrupt source to check.
bogdanm 89:552587b429a1 373 * This parameter can be one of the following values:
bogdanm 89:552587b429a1 374 * @arg SPI_IT_TXE: Tx buffer empty interrupt enable
bogdanm 89:552587b429a1 375 * @arg SPI_IT_RXNE: RX buffer not empty interrupt enable
bogdanm 89:552587b429a1 376 * @arg SPI_IT_ERR: Error interrupt enable
bogdanm 89:552587b429a1 377 * @retval The new state of __IT__ (TRUE or FALSE).
bogdanm 89:552587b429a1 378 */
bogdanm 89:552587b429a1 379 #define __HAL_SPI_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->CR2 & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
bogdanm 89:552587b429a1 380
bogdanm 89:552587b429a1 381 /** @brief Check whether the specified SPI flag is set or not.
bogdanm 89:552587b429a1 382 * @param __HANDLE__: specifies the SPI handle.
bogdanm 89:552587b429a1 383 * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
bogdanm 89:552587b429a1 384 * @param __FLAG__: specifies the flag to check.
bogdanm 89:552587b429a1 385 * This parameter can be one of the following values:
bogdanm 89:552587b429a1 386 * @arg SPI_FLAG_RXNE: Receive buffer not empty flag
bogdanm 89:552587b429a1 387 * @arg SPI_FLAG_TXE: Transmit buffer empty flag
bogdanm 89:552587b429a1 388 * @arg SPI_FLAG_CRCERR: CRC error flag
bogdanm 89:552587b429a1 389 * @arg SPI_FLAG_MODF: Mode fault flag
bogdanm 89:552587b429a1 390 * @arg SPI_FLAG_OVR: Overrun flag
bogdanm 89:552587b429a1 391 * @arg SPI_FLAG_BSY: Busy flag
bogdanm 89:552587b429a1 392 * @arg SPI_FLAG_FRE: Frame format error flag
bogdanm 89:552587b429a1 393 * @retval The new state of __FLAG__ (TRUE or FALSE).
bogdanm 89:552587b429a1 394 */
bogdanm 89:552587b429a1 395 #define __HAL_SPI_GET_FLAG(__HANDLE__, __FLAG__) ((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__))
bogdanm 89:552587b429a1 396
bogdanm 89:552587b429a1 397 /** @brief Clear the SPI CRCERR pending flag.
bogdanm 89:552587b429a1 398 * @param __HANDLE__: specifies the SPI handle.
bogdanm 89:552587b429a1 399 * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
bogdanm 89:552587b429a1 400 * @retval None
bogdanm 89:552587b429a1 401 */
bogdanm 89:552587b429a1 402 #define __HAL_SPI_CLEAR_CRCERRFLAG(__HANDLE__) ((__HANDLE__)->Instance->SR &= ~(SPI_FLAG_CRCERR))
bogdanm 89:552587b429a1 403
bogdanm 89:552587b429a1 404 /** @brief Clear the SPI MODF pending flag.
bogdanm 89:552587b429a1 405 * @param __HANDLE__: specifies the SPI handle.
bogdanm 89:552587b429a1 406 * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
bogdanm 89:552587b429a1 407 * @retval None
bogdanm 89:552587b429a1 408 */
bogdanm 89:552587b429a1 409 #define __HAL_SPI_CLEAR_MODFFLAG(__HANDLE__) do{(__HANDLE__)->Instance->SR;\
bogdanm 89:552587b429a1 410 (__HANDLE__)->Instance->CR1 &= (~SPI_CR1_SPE);}while(0)
bogdanm 89:552587b429a1 411
bogdanm 89:552587b429a1 412 /** @brief Clear the SPI OVR pending flag.
bogdanm 89:552587b429a1 413 * @param __HANDLE__: specifies the SPI handle.
bogdanm 89:552587b429a1 414 * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
bogdanm 89:552587b429a1 415 * @retval None
bogdanm 89:552587b429a1 416 */
bogdanm 89:552587b429a1 417 #define __HAL_SPI_CLEAR_OVRFLAG(__HANDLE__) do{(__HANDLE__)->Instance->DR;\
bogdanm 89:552587b429a1 418 (__HANDLE__)->Instance->SR;}while(0)
bogdanm 89:552587b429a1 419
bogdanm 89:552587b429a1 420 /** @brief Clear the SPI FRE pending flag.
bogdanm 89:552587b429a1 421 * @param __HANDLE__: specifies the SPI handle.
bogdanm 89:552587b429a1 422 * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
bogdanm 89:552587b429a1 423 * @retval None
bogdanm 89:552587b429a1 424 */
bogdanm 89:552587b429a1 425 #define __HAL_SPI_CLEAR_FREFLAG(__HANDLE__) ((__HANDLE__)->Instance->SR)
bogdanm 89:552587b429a1 426
bogdanm 89:552587b429a1 427 #define __HAL_SPI_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 |= SPI_CR1_SPE)
bogdanm 89:552587b429a1 428 #define __HAL_SPI_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 &= ~SPI_CR1_SPE)
bogdanm 89:552587b429a1 429
bogdanm 89:552587b429a1 430 #define IS_SPI_CRC_POLYNOMIAL(POLYNOMIAL) (((POLYNOMIAL) >= 0x1) && ((POLYNOMIAL) <= 0xFFFF))
bogdanm 89:552587b429a1 431
bogdanm 89:552587b429a1 432 #define __HAL_SPI_1LINE_TX(__HANDLE__) ((__HANDLE__)->Instance->CR1 |= SPI_CR1_BIDIOE)
bogdanm 89:552587b429a1 433
bogdanm 89:552587b429a1 434 #define __HAL_SPI_1LINE_RX(__HANDLE__) ((__HANDLE__)->Instance->CR1 &= ~SPI_CR1_BIDIOE)
bogdanm 89:552587b429a1 435
bogdanm 89:552587b429a1 436 #define __HAL_SPI_RESET_CRC(__HANDLE__) do{(__HANDLE__)->Instance->CR1 &= (~SPI_CR1_CRCEN);\
bogdanm 89:552587b429a1 437 (__HANDLE__)->Instance->CR1 |= SPI_CR1_CRCEN;}while(0)
bogdanm 89:552587b429a1 438
bogdanm 89:552587b429a1 439 /* Exported functions --------------------------------------------------------*/
bogdanm 89:552587b429a1 440
bogdanm 89:552587b429a1 441 /* Initialization/de-initialization functions **********************************/
bogdanm 89:552587b429a1 442 HAL_StatusTypeDef HAL_SPI_Init(SPI_HandleTypeDef *hspi);
bogdanm 89:552587b429a1 443 HAL_StatusTypeDef HAL_SPI_DeInit (SPI_HandleTypeDef *hspi);
bogdanm 89:552587b429a1 444 void HAL_SPI_MspInit(SPI_HandleTypeDef *hspi);
bogdanm 89:552587b429a1 445 void HAL_SPI_MspDeInit(SPI_HandleTypeDef *hspi);
bogdanm 89:552587b429a1 446
bogdanm 89:552587b429a1 447 /* I/O operation functions *****************************************************/
bogdanm 89:552587b429a1 448 HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout);
bogdanm 89:552587b429a1 449 HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout);
bogdanm 89:552587b429a1 450 HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size, uint32_t Timeout);
bogdanm 89:552587b429a1 451 HAL_StatusTypeDef HAL_SPI_Transmit_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size);
bogdanm 89:552587b429a1 452 HAL_StatusTypeDef HAL_SPI_Receive_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size);
bogdanm 89:552587b429a1 453 HAL_StatusTypeDef HAL_SPI_TransmitReceive_IT(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size);
bogdanm 89:552587b429a1 454 HAL_StatusTypeDef HAL_SPI_Transmit_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size);
bogdanm 89:552587b429a1 455 HAL_StatusTypeDef HAL_SPI_Receive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size);
bogdanm 89:552587b429a1 456 HAL_StatusTypeDef HAL_SPI_TransmitReceive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size);
bogdanm 89:552587b429a1 457 void HAL_SPI_IRQHandler(SPI_HandleTypeDef *hspi);
bogdanm 89:552587b429a1 458 void HAL_SPI_TxCpltCallback(SPI_HandleTypeDef *hspi);
bogdanm 89:552587b429a1 459 void HAL_SPI_RxCpltCallback(SPI_HandleTypeDef *hspi);
bogdanm 89:552587b429a1 460 void HAL_SPI_TxRxCpltCallback(SPI_HandleTypeDef *hspi);
bogdanm 89:552587b429a1 461 void HAL_SPI_ErrorCallback(SPI_HandleTypeDef *hspi);
bogdanm 89:552587b429a1 462
bogdanm 89:552587b429a1 463 /* Peripheral State and Control functions **************************************/
bogdanm 89:552587b429a1 464 HAL_SPI_StateTypeDef HAL_SPI_GetState(SPI_HandleTypeDef *hspi);
bogdanm 89:552587b429a1 465 HAL_SPI_ErrorTypeDef HAL_SPI_GetError(SPI_HandleTypeDef *hspi);
bogdanm 89:552587b429a1 466
bogdanm 89:552587b429a1 467 /**
bogdanm 89:552587b429a1 468 * @}
bogdanm 89:552587b429a1 469 */
bogdanm 89:552587b429a1 470
bogdanm 89:552587b429a1 471 /**
bogdanm 89:552587b429a1 472 * @}
bogdanm 89:552587b429a1 473 */
bogdanm 89:552587b429a1 474
bogdanm 89:552587b429a1 475 #ifdef __cplusplus
bogdanm 89:552587b429a1 476 }
bogdanm 89:552587b429a1 477 #endif
bogdanm 89:552587b429a1 478
bogdanm 89:552587b429a1 479 #endif /* __STM32F4xx_HAL_SPI_H */
bogdanm 89:552587b429a1 480
bogdanm 89:552587b429a1 481 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/