雄介 太田 / mbed

mbed(SerialHalfDuplex入り)

Fork of mbed by mbed official

TARGET_ARCH_MAX/stm32f4xx_hal_i2s.h@89:552587b429a1, 2014-09-12 (annotated)

Committer:
bogdanm
Date:
Fri Sep 12 16:41:52 2014 +0100
Revision:
89:552587b429a1
Child:
92:4fc01daae5a5
Release 89 of the mbed library



Main changes:



- low power optimizations for Nordic targets

- code structure changes for Freescale K64F targets

- bug fixes in various backends

Who changed what in which revision?

UserRevisionLine numberNew contents of line
bogdanm 89:552587b429a1 1 /**
bogdanm 89:552587b429a1 2 ******************************************************************************
bogdanm 89:552587b429a1 3 * @file stm32f4xx_hal_i2s.h
bogdanm 89:552587b429a1 4 * @author MCD Application Team
bogdanm 89:552587b429a1 5 * @version V1.1.0RC2
bogdanm 89:552587b429a1 6 * @date 14-May-2014
bogdanm 89:552587b429a1 7 * @brief Header file of I2S HAL module.
bogdanm 89:552587b429a1 8 ******************************************************************************
bogdanm 89:552587b429a1 9 * @attention
bogdanm 89:552587b429a1 10 *
bogdanm 89:552587b429a1 11 * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
bogdanm 89:552587b429a1 12 *
bogdanm 89:552587b429a1 13 * Redistribution and use in source and binary forms, with or without modification,
bogdanm 89:552587b429a1 14 * are permitted provided that the following conditions are met:
bogdanm 89:552587b429a1 15 * 1. Redistributions of source code must retain the above copyright notice,
bogdanm 89:552587b429a1 16 * this list of conditions and the following disclaimer.
bogdanm 89:552587b429a1 17 * 2. Redistributions in binary form must reproduce the above copyright notice,
bogdanm 89:552587b429a1 18 * this list of conditions and the following disclaimer in the documentation
bogdanm 89:552587b429a1 19 * and/or other materials provided with the distribution.
bogdanm 89:552587b429a1 20 * 3. Neither the name of STMicroelectronics nor the names of its contributors
bogdanm 89:552587b429a1 21 * may be used to endorse or promote products derived from this software
bogdanm 89:552587b429a1 22 * without specific prior written permission.
bogdanm 89:552587b429a1 23 *
bogdanm 89:552587b429a1 24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
bogdanm 89:552587b429a1 25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
bogdanm 89:552587b429a1 26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
bogdanm 89:552587b429a1 27 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
bogdanm 89:552587b429a1 28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
bogdanm 89:552587b429a1 29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
bogdanm 89:552587b429a1 30 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
bogdanm 89:552587b429a1 31 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
bogdanm 89:552587b429a1 32 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
bogdanm 89:552587b429a1 33 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
bogdanm 89:552587b429a1 34 *
bogdanm 89:552587b429a1 35 ******************************************************************************
bogdanm 89:552587b429a1 36 */
bogdanm 89:552587b429a1 37
bogdanm 89:552587b429a1 38 /* Define to prevent recursive inclusion -------------------------------------*/
bogdanm 89:552587b429a1 39 #ifndef __STM32F4xx_HAL_I2S_H
bogdanm 89:552587b429a1 40 #define __STM32F4xx_HAL_I2S_H
bogdanm 89:552587b429a1 41
bogdanm 89:552587b429a1 42 #ifdef __cplusplus
bogdanm 89:552587b429a1 43 extern "C" {
bogdanm 89:552587b429a1 44 #endif
bogdanm 89:552587b429a1 45
bogdanm 89:552587b429a1 46 /* Includes ------------------------------------------------------------------*/
bogdanm 89:552587b429a1 47 #include "stm32f4xx_hal_def.h"
bogdanm 89:552587b429a1 48
bogdanm 89:552587b429a1 49 /** @addtogroup STM32F4xx_HAL_Driver
bogdanm 89:552587b429a1 50 * @{
bogdanm 89:552587b429a1 51 */
bogdanm 89:552587b429a1 52
bogdanm 89:552587b429a1 53 /** @addtogroup I2S
bogdanm 89:552587b429a1 54 * @{
bogdanm 89:552587b429a1 55 */
bogdanm 89:552587b429a1 56
bogdanm 89:552587b429a1 57 /* Exported types ------------------------------------------------------------*/
bogdanm 89:552587b429a1 58 /**
bogdanm 89:552587b429a1 59 * @brief I2S Init structure definition
bogdanm 89:552587b429a1 60 */
bogdanm 89:552587b429a1 61 typedef struct
bogdanm 89:552587b429a1 62 {
bogdanm 89:552587b429a1 63 uint32_t Mode; /*!< Specifies the I2S operating mode.
bogdanm 89:552587b429a1 64 This parameter can be a value of @ref I2S_Mode */
bogdanm 89:552587b429a1 65
bogdanm 89:552587b429a1 66 uint32_t Standard; /*!< Specifies the standard used for the I2S communication.
bogdanm 89:552587b429a1 67 This parameter can be a value of @ref I2S_Standard */
bogdanm 89:552587b429a1 68
bogdanm 89:552587b429a1 69 uint32_t DataFormat; /*!< Specifies the data format for the I2S communication.
bogdanm 89:552587b429a1 70 This parameter can be a value of @ref I2S_Data_Format */
bogdanm 89:552587b429a1 71
bogdanm 89:552587b429a1 72 uint32_t MCLKOutput; /*!< Specifies whether the I2S MCLK output is enabled or not.
bogdanm 89:552587b429a1 73 This parameter can be a value of @ref I2S_MCLK_Output */
bogdanm 89:552587b429a1 74
bogdanm 89:552587b429a1 75 uint32_t AudioFreq; /*!< Specifies the frequency selected for the I2S communication.
bogdanm 89:552587b429a1 76 This parameter can be a value of @ref I2S_Audio_Frequency */
bogdanm 89:552587b429a1 77
bogdanm 89:552587b429a1 78 uint32_t CPOL; /*!< Specifies the idle state of the I2S clock.
bogdanm 89:552587b429a1 79 This parameter can be a value of @ref I2S_Clock_Polarity */
bogdanm 89:552587b429a1 80
bogdanm 89:552587b429a1 81 uint32_t ClockSource; /*!< Specifies the I2S Clock Source.
bogdanm 89:552587b429a1 82 This parameter can be a value of @ref I2S_Clock_Source */
bogdanm 89:552587b429a1 83
bogdanm 89:552587b429a1 84 uint32_t FullDuplexMode; /*!< Specifies the I2S FullDuplex mode.
bogdanm 89:552587b429a1 85 This parameter can be a value of @ref I2S_FullDuplex_Mode */
bogdanm 89:552587b429a1 86
bogdanm 89:552587b429a1 87 }I2S_InitTypeDef;
bogdanm 89:552587b429a1 88
bogdanm 89:552587b429a1 89 /**
bogdanm 89:552587b429a1 90 * @brief HAL State structures definition
bogdanm 89:552587b429a1 91 */
bogdanm 89:552587b429a1 92 typedef enum
bogdanm 89:552587b429a1 93 {
bogdanm 89:552587b429a1 94 HAL_I2S_STATE_RESET = 0x00, /*!< I2S not yet initialized or disabled */
bogdanm 89:552587b429a1 95 HAL_I2S_STATE_READY = 0x01, /*!< I2S initialized and ready for use */
bogdanm 89:552587b429a1 96 HAL_I2S_STATE_BUSY = 0x02, /*!< I2S internal process is ongoing */
bogdanm 89:552587b429a1 97 HAL_I2S_STATE_BUSY_TX = 0x12, /*!< Data Transmission process is ongoing */
bogdanm 89:552587b429a1 98 HAL_I2S_STATE_BUSY_RX = 0x22, /*!< Data Reception process is ongoing */
bogdanm 89:552587b429a1 99 HAL_I2S_STATE_BUSY_TX_RX = 0x32, /*!< Data Transmission and Reception process is ongoing */
bogdanm 89:552587b429a1 100 HAL_I2S_STATE_TIMEOUT = 0x03, /*!< I2S timeout state */
bogdanm 89:552587b429a1 101 HAL_I2S_STATE_ERROR = 0x04 /*!< I2S error state */
bogdanm 89:552587b429a1 102
bogdanm 89:552587b429a1 103 }HAL_I2S_StateTypeDef;
bogdanm 89:552587b429a1 104
bogdanm 89:552587b429a1 105 /**
bogdanm 89:552587b429a1 106 * @brief HAL I2S Error Code structure definition
bogdanm 89:552587b429a1 107 */
bogdanm 89:552587b429a1 108 typedef enum
bogdanm 89:552587b429a1 109 {
bogdanm 89:552587b429a1 110 HAL_I2S_ERROR_NONE = 0x00, /*!< No error */
bogdanm 89:552587b429a1 111 HAL_I2S_ERROR_UDR = 0x01, /*!< I2S Underrun error */
bogdanm 89:552587b429a1 112 HAL_I2S_ERROR_OVR = 0x02, /*!< I2S Overrun error */
bogdanm 89:552587b429a1 113 HAL_I2SEX_ERROR_UDR = 0x04, /*!< I2S extended Underrun error */
bogdanm 89:552587b429a1 114 HAL_I2SEX_ERROR_OVR = 0x08, /*!< I2S extended Overrun error */
bogdanm 89:552587b429a1 115 HAL_I2S_ERROR_FRE = 0x10, /*!< I2S Frame format error */
bogdanm 89:552587b429a1 116 HAL_I2S_ERROR_DMA = 0x20 /*!< DMA transfer error */
bogdanm 89:552587b429a1 117 }HAL_I2S_ErrorTypeDef;
bogdanm 89:552587b429a1 118
bogdanm 89:552587b429a1 119 /**
bogdanm 89:552587b429a1 120 * @brief I2S handle Structure definition
bogdanm 89:552587b429a1 121 */
bogdanm 89:552587b429a1 122 typedef struct
bogdanm 89:552587b429a1 123 {
bogdanm 89:552587b429a1 124 SPI_TypeDef *Instance; /* I2S registers base address */
bogdanm 89:552587b429a1 125
bogdanm 89:552587b429a1 126 I2S_InitTypeDef Init; /* I2S communication parameters */
bogdanm 89:552587b429a1 127
bogdanm 89:552587b429a1 128 uint16_t *pTxBuffPtr; /* Pointer to I2S Tx transfer buffer */
bogdanm 89:552587b429a1 129
bogdanm 89:552587b429a1 130 __IO uint16_t TxXferSize; /* I2S Tx transfer size */
bogdanm 89:552587b429a1 131
bogdanm 89:552587b429a1 132 __IO uint16_t TxXferCount; /* I2S Tx transfer Counter */
bogdanm 89:552587b429a1 133
bogdanm 89:552587b429a1 134 uint16_t *pRxBuffPtr; /* Pointer to I2S Rx transfer buffer */
bogdanm 89:552587b429a1 135
bogdanm 89:552587b429a1 136 __IO uint16_t RxXferSize; /* I2S Rx transfer size */
bogdanm 89:552587b429a1 137
bogdanm 89:552587b429a1 138 __IO uint16_t RxXferCount; /* I2S Rx transfer counter */
bogdanm 89:552587b429a1 139
bogdanm 89:552587b429a1 140 DMA_HandleTypeDef *hdmatx; /* I2S Tx DMA handle parameters */
bogdanm 89:552587b429a1 141
bogdanm 89:552587b429a1 142 DMA_HandleTypeDef *hdmarx; /* I2S Rx DMA handle parameters */
bogdanm 89:552587b429a1 143
bogdanm 89:552587b429a1 144 __IO HAL_LockTypeDef Lock; /* I2S locking object */
bogdanm 89:552587b429a1 145
bogdanm 89:552587b429a1 146 __IO HAL_I2S_StateTypeDef State; /* I2S communication state */
bogdanm 89:552587b429a1 147
bogdanm 89:552587b429a1 148 __IO HAL_I2S_ErrorTypeDef ErrorCode; /* I2S Error code */
bogdanm 89:552587b429a1 149
bogdanm 89:552587b429a1 150 }I2S_HandleTypeDef;
bogdanm 89:552587b429a1 151
bogdanm 89:552587b429a1 152 /* Exported constants --------------------------------------------------------*/
bogdanm 89:552587b429a1 153
bogdanm 89:552587b429a1 154 /** @defgroup I2S_Exported_Constants
bogdanm 89:552587b429a1 155 * @{
bogdanm 89:552587b429a1 156 */
bogdanm 89:552587b429a1 157 #define I2SxEXT(__INSTANCE__) ((__INSTANCE__) == (SPI2)? (SPI_TypeDef *)(I2S2ext_BASE): (SPI_TypeDef *)(I2S3ext_BASE))
bogdanm 89:552587b429a1 158
bogdanm 89:552587b429a1 159 /** @defgroup I2S_Clock_Source
bogdanm 89:552587b429a1 160 * @{
bogdanm 89:552587b429a1 161 */
bogdanm 89:552587b429a1 162 #define I2S_CLOCK_PLL ((uint32_t)0x00000000)
bogdanm 89:552587b429a1 163 #define I2S_CLOCK_EXTERNAL ((uint32_t)0x00000001)
bogdanm 89:552587b429a1 164
bogdanm 89:552587b429a1 165 #define IS_I2S_CLOCKSOURCE(CLOCK) (((CLOCK) == I2S_CLOCK_EXTERNAL) || \
bogdanm 89:552587b429a1 166 ((CLOCK) == I2S_CLOCK_PLL))
bogdanm 89:552587b429a1 167 /**
bogdanm 89:552587b429a1 168 * @}
bogdanm 89:552587b429a1 169 */
bogdanm 89:552587b429a1 170
bogdanm 89:552587b429a1 171 /** @defgroup I2S_Mode
bogdanm 89:552587b429a1 172 * @{
bogdanm 89:552587b429a1 173 */
bogdanm 89:552587b429a1 174 #define I2S_MODE_SLAVE_TX ((uint32_t)0x00000000)
bogdanm 89:552587b429a1 175 #define I2S_MODE_SLAVE_RX ((uint32_t)0x00000100)
bogdanm 89:552587b429a1 176 #define I2S_MODE_MASTER_TX ((uint32_t)0x00000200)
bogdanm 89:552587b429a1 177 #define I2S_MODE_MASTER_RX ((uint32_t)0x00000300)
bogdanm 89:552587b429a1 178
bogdanm 89:552587b429a1 179 #define IS_I2S_MODE(MODE) (((MODE) == I2S_MODE_SLAVE_TX) || \
bogdanm 89:552587b429a1 180 ((MODE) == I2S_MODE_SLAVE_RX) || \
bogdanm 89:552587b429a1 181 ((MODE) == I2S_MODE_MASTER_TX) || \
bogdanm 89:552587b429a1 182 ((MODE) == I2S_MODE_MASTER_RX))
bogdanm 89:552587b429a1 183 /**
bogdanm 89:552587b429a1 184 * @}
bogdanm 89:552587b429a1 185 */
bogdanm 89:552587b429a1 186
bogdanm 89:552587b429a1 187 /** @defgroup I2S_Standard
bogdanm 89:552587b429a1 188 * @{
bogdanm 89:552587b429a1 189 */
bogdanm 89:552587b429a1 190 #define I2S_STANDARD_PHILIPS ((uint32_t)0x00000000)
bogdanm 89:552587b429a1 191 #define I2S_STANDARD_MSB ((uint32_t)0x00000010)
bogdanm 89:552587b429a1 192 #define I2S_STANDARD_LSB ((uint32_t)0x00000020)
bogdanm 89:552587b429a1 193 #define I2S_STANDARD_PCM_SHORT ((uint32_t)0x00000030)
bogdanm 89:552587b429a1 194 #define I2S_STANDARD_PCM_LONG ((uint32_t)0x000000B0)
bogdanm 89:552587b429a1 195
bogdanm 89:552587b429a1 196 #define IS_I2S_STANDARD(STANDARD) (((STANDARD) == I2S_STANDARD_PHILIPS) || \
bogdanm 89:552587b429a1 197 ((STANDARD) == I2S_STANDARD_MSB) || \
bogdanm 89:552587b429a1 198 ((STANDARD) == I2S_STANDARD_LSB) || \
bogdanm 89:552587b429a1 199 ((STANDARD) == I2S_STANDARD_PCM_SHORT) || \
bogdanm 89:552587b429a1 200 ((STANDARD) == I2S_STANDARD_PCM_LONG))
bogdanm 89:552587b429a1 201 /** @defgroup I2S_Legacy
bogdanm 89:552587b429a1 202 * @{
bogdanm 89:552587b429a1 203 */
bogdanm 89:552587b429a1 204 #define I2S_STANDARD_PHILLIPS I2S_STANDARD_PHILIPS
bogdanm 89:552587b429a1 205 /**
bogdanm 89:552587b429a1 206 * @}
bogdanm 89:552587b429a1 207 */
bogdanm 89:552587b429a1 208
bogdanm 89:552587b429a1 209 /**
bogdanm 89:552587b429a1 210 * @}
bogdanm 89:552587b429a1 211 */
bogdanm 89:552587b429a1 212
bogdanm 89:552587b429a1 213 /** @defgroup I2S_Data_Format
bogdanm 89:552587b429a1 214 * @{
bogdanm 89:552587b429a1 215 */
bogdanm 89:552587b429a1 216 #define I2S_DATAFORMAT_16B ((uint32_t)0x00000000)
bogdanm 89:552587b429a1 217 #define I2S_DATAFORMAT_16B_EXTENDED ((uint32_t)0x00000001)
bogdanm 89:552587b429a1 218 #define I2S_DATAFORMAT_24B ((uint32_t)0x00000003)
bogdanm 89:552587b429a1 219 #define I2S_DATAFORMAT_32B ((uint32_t)0x00000005)
bogdanm 89:552587b429a1 220
bogdanm 89:552587b429a1 221 #define IS_I2S_DATA_FORMAT(FORMAT) (((FORMAT) == I2S_DATAFORMAT_16B) || \
bogdanm 89:552587b429a1 222 ((FORMAT) == I2S_DATAFORMAT_16B_EXTENDED) || \
bogdanm 89:552587b429a1 223 ((FORMAT) == I2S_DATAFORMAT_24B) || \
bogdanm 89:552587b429a1 224 ((FORMAT) == I2S_DATAFORMAT_32B))
bogdanm 89:552587b429a1 225 /**
bogdanm 89:552587b429a1 226 * @}
bogdanm 89:552587b429a1 227 */
bogdanm 89:552587b429a1 228
bogdanm 89:552587b429a1 229 /** @defgroup I2S_MCLK_Output
bogdanm 89:552587b429a1 230 * @{
bogdanm 89:552587b429a1 231 */
bogdanm 89:552587b429a1 232 #define I2S_MCLKOUTPUT_ENABLE ((uint32_t)SPI_I2SPR_MCKOE)
bogdanm 89:552587b429a1 233 #define I2S_MCLKOUTPUT_DISABLE ((uint32_t)0x00000000)
bogdanm 89:552587b429a1 234
bogdanm 89:552587b429a1 235 #define IS_I2S_MCLK_OUTPUT(OUTPUT) (((OUTPUT) == I2S_MCLKOUTPUT_ENABLE) || \
bogdanm 89:552587b429a1 236 ((OUTPUT) == I2S_MCLKOUTPUT_DISABLE))
bogdanm 89:552587b429a1 237 /**
bogdanm 89:552587b429a1 238 * @}
bogdanm 89:552587b429a1 239 */
bogdanm 89:552587b429a1 240
bogdanm 89:552587b429a1 241 /** @defgroup I2S_Audio_Frequency
bogdanm 89:552587b429a1 242 * @{
bogdanm 89:552587b429a1 243 */
bogdanm 89:552587b429a1 244 #define I2S_AUDIOFREQ_192K ((uint32_t)192000)
bogdanm 89:552587b429a1 245 #define I2S_AUDIOFREQ_96K ((uint32_t)96000)
bogdanm 89:552587b429a1 246 #define I2S_AUDIOFREQ_48K ((uint32_t)48000)
bogdanm 89:552587b429a1 247 #define I2S_AUDIOFREQ_44K ((uint32_t)44100)
bogdanm 89:552587b429a1 248 #define I2S_AUDIOFREQ_32K ((uint32_t)32000)
bogdanm 89:552587b429a1 249 #define I2S_AUDIOFREQ_22K ((uint32_t)22050)
bogdanm 89:552587b429a1 250 #define I2S_AUDIOFREQ_16K ((uint32_t)16000)
bogdanm 89:552587b429a1 251 #define I2S_AUDIOFREQ_11K ((uint32_t)11025)
bogdanm 89:552587b429a1 252 #define I2S_AUDIOFREQ_8K ((uint32_t)8000)
bogdanm 89:552587b429a1 253 #define I2S_AUDIOFREQ_DEFAULT ((uint32_t)2)
bogdanm 89:552587b429a1 254
bogdanm 89:552587b429a1 255 #define IS_I2S_AUDIO_FREQ(FREQ) ((((FREQ) >= I2S_AUDIOFREQ_8K) && \
bogdanm 89:552587b429a1 256 ((FREQ) <= I2S_AUDIOFREQ_192K)) || \
bogdanm 89:552587b429a1 257 ((FREQ) == I2S_AUDIOFREQ_DEFAULT))
bogdanm 89:552587b429a1 258 /**
bogdanm 89:552587b429a1 259 * @}
bogdanm 89:552587b429a1 260 */
bogdanm 89:552587b429a1 261
bogdanm 89:552587b429a1 262 /** @defgroup I2S_FullDuplex_Mode
bogdanm 89:552587b429a1 263 * @{
bogdanm 89:552587b429a1 264 */
bogdanm 89:552587b429a1 265 #define I2S_FULLDUPLEXMODE_DISABLE ((uint32_t)0x00000000)
bogdanm 89:552587b429a1 266 #define I2S_FULLDUPLEXMODE_ENABLE ((uint32_t)0x00000001)
bogdanm 89:552587b429a1 267
bogdanm 89:552587b429a1 268 #define IS_I2S_FULLDUPLEX_MODE(MODE) (((MODE) == I2S_FULLDUPLEXMODE_DISABLE) || \
bogdanm 89:552587b429a1 269 ((MODE) == I2S_FULLDUPLEXMODE_ENABLE))
bogdanm 89:552587b429a1 270 /**
bogdanm 89:552587b429a1 271 * @}
bogdanm 89:552587b429a1 272 */
bogdanm 89:552587b429a1 273
bogdanm 89:552587b429a1 274 /** @defgroup I2S_Clock_Polarity
bogdanm 89:552587b429a1 275 * @{
bogdanm 89:552587b429a1 276 */
bogdanm 89:552587b429a1 277 #define I2S_CPOL_LOW ((uint32_t)0x00000000)
bogdanm 89:552587b429a1 278 #define I2S_CPOL_HIGH ((uint32_t)SPI_I2SCFGR_CKPOL)
bogdanm 89:552587b429a1 279
bogdanm 89:552587b429a1 280 #define IS_I2S_CPOL(CPOL) (((CPOL) == I2S_CPOL_LOW) || \
bogdanm 89:552587b429a1 281 ((CPOL) == I2S_CPOL_HIGH))
bogdanm 89:552587b429a1 282 /**
bogdanm 89:552587b429a1 283 * @}
bogdanm 89:552587b429a1 284 */
bogdanm 89:552587b429a1 285
bogdanm 89:552587b429a1 286 /** @defgroup I2S_Interrupt_configuration_definition
bogdanm 89:552587b429a1 287 * @{
bogdanm 89:552587b429a1 288 */
bogdanm 89:552587b429a1 289 #define I2S_IT_TXE SPI_CR2_TXEIE
bogdanm 89:552587b429a1 290 #define I2S_IT_RXNE SPI_CR2_RXNEIE
bogdanm 89:552587b429a1 291 #define I2S_IT_ERR SPI_CR2_ERRIE
bogdanm 89:552587b429a1 292 /**
bogdanm 89:552587b429a1 293 * @}
bogdanm 89:552587b429a1 294 */
bogdanm 89:552587b429a1 295
bogdanm 89:552587b429a1 296 /** @defgroup I2S_Flag_definition
bogdanm 89:552587b429a1 297 * @{
bogdanm 89:552587b429a1 298 */
bogdanm 89:552587b429a1 299 #define I2S_FLAG_TXE SPI_SR_TXE
bogdanm 89:552587b429a1 300 #define I2S_FLAG_RXNE SPI_SR_RXNE
bogdanm 89:552587b429a1 301
bogdanm 89:552587b429a1 302 #define I2S_FLAG_UDR SPI_SR_UDR
bogdanm 89:552587b429a1 303 #define I2S_FLAG_OVR SPI_SR_OVR
bogdanm 89:552587b429a1 304 #define I2S_FLAG_FRE SPI_SR_FRE
bogdanm 89:552587b429a1 305
bogdanm 89:552587b429a1 306 #define I2S_FLAG_CHSIDE SPI_SR_CHSIDE
bogdanm 89:552587b429a1 307 #define I2S_FLAG_BSY SPI_SR_BSY
bogdanm 89:552587b429a1 308 /**
bogdanm 89:552587b429a1 309 * @}
bogdanm 89:552587b429a1 310 */
bogdanm 89:552587b429a1 311
bogdanm 89:552587b429a1 312 /**
bogdanm 89:552587b429a1 313 * @}
bogdanm 89:552587b429a1 314 */
bogdanm 89:552587b429a1 315
bogdanm 89:552587b429a1 316 /* Exported macro ------------------------------------------------------------*/
bogdanm 89:552587b429a1 317
bogdanm 89:552587b429a1 318
bogdanm 89:552587b429a1 319 /** @brief Reset I2S handle state
bogdanm 89:552587b429a1 320 * @param __HANDLE__: specifies the I2S Handle.
bogdanm 89:552587b429a1 321 * @retval None
bogdanm 89:552587b429a1 322 */
bogdanm 89:552587b429a1 323 #define __HAL_I2S_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_I2S_STATE_RESET)
bogdanm 89:552587b429a1 324
bogdanm 89:552587b429a1 325 /** @brief Enable or disable the specified SPI peripheral (in I2S mode).
bogdanm 89:552587b429a1 326 * @param __HANDLE__: specifies the I2S Handle.
bogdanm 89:552587b429a1 327 * @retval None
bogdanm 89:552587b429a1 328 */
bogdanm 89:552587b429a1 329 #define __HAL_I2S_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->I2SCFGR |= SPI_I2SCFGR_I2SE)
bogdanm 89:552587b429a1 330 #define __HAL_I2S_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->I2SCFGR &= ~SPI_I2SCFGR_I2SE)
bogdanm 89:552587b429a1 331
bogdanm 89:552587b429a1 332 /** @brief Enable or disable the specified I2S interrupts.
bogdanm 89:552587b429a1 333 * @param __HANDLE__: specifies the I2S Handle.
bogdanm 89:552587b429a1 334 * @param __INTERRUPT__: specifies the interrupt source to enable or disable.
bogdanm 89:552587b429a1 335 * This parameter can be one of the following values:
bogdanm 89:552587b429a1 336 * @arg I2S_IT_TXE: Tx buffer empty interrupt enable
bogdanm 89:552587b429a1 337 * @arg I2S_IT_RXNE: RX buffer not empty interrupt enable
bogdanm 89:552587b429a1 338 * @arg I2S_IT_ERR: Error interrupt enable
bogdanm 89:552587b429a1 339 * @retval None
bogdanm 89:552587b429a1 340 */
bogdanm 89:552587b429a1 341 #define __HAL_I2S_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR2 |= (__INTERRUPT__))
bogdanm 89:552587b429a1 342 #define __HAL_I2S_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR2 &= ~(__INTERRUPT__))
bogdanm 89:552587b429a1 343
bogdanm 89:552587b429a1 344 /** @brief Checks if the specified I2S interrupt source is enabled or disabled.
bogdanm 89:552587b429a1 345 * @param __HANDLE__: specifies the I2S Handle.
bogdanm 89:552587b429a1 346 * This parameter can be I2S where x: 1, 2, or 3 to select the I2S peripheral.
bogdanm 89:552587b429a1 347 * @param __INTERRUPT__: specifies the I2S interrupt source to check.
bogdanm 89:552587b429a1 348 * This parameter can be one of the following values:
bogdanm 89:552587b429a1 349 * @arg I2S_IT_TXE: Tx buffer empty interrupt enable
bogdanm 89:552587b429a1 350 * @arg I2S_IT_RXNE: RX buffer not empty interrupt enable
bogdanm 89:552587b429a1 351 * @arg I2S_IT_ERR: Error interrupt enable
bogdanm 89:552587b429a1 352 * @retval The new state of __IT__ (TRUE or FALSE).
bogdanm 89:552587b429a1 353 */
bogdanm 89:552587b429a1 354 #define __HAL_I2S_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->CR2 & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
bogdanm 89:552587b429a1 355
bogdanm 89:552587b429a1 356 /** @brief Checks whether the specified I2S flag is set or not.
bogdanm 89:552587b429a1 357 * @param __HANDLE__: specifies the I2S Handle.
bogdanm 89:552587b429a1 358 * @param __FLAG__: specifies the flag to check.
bogdanm 89:552587b429a1 359 * This parameter can be one of the following values:
bogdanm 89:552587b429a1 360 * @arg I2S_FLAG_RXNE: Receive buffer not empty flag
bogdanm 89:552587b429a1 361 * @arg I2S_FLAG_TXE: Transmit buffer empty flag
bogdanm 89:552587b429a1 362 * @arg I2S_FLAG_UDR: Underrun flag
bogdanm 89:552587b429a1 363 * @arg I2S_FLAG_OVR: Overrun flag
bogdanm 89:552587b429a1 364 * @arg I2S_FLAG_FRE: Frame error flag
bogdanm 89:552587b429a1 365 * @arg I2S_FLAG_CHSIDE: Channel Side flag
bogdanm 89:552587b429a1 366 * @arg I2S_FLAG_BSY: Busy flag
bogdanm 89:552587b429a1 367 * @retval The new state of __FLAG__ (TRUE or FALSE).
bogdanm 89:552587b429a1 368 */
bogdanm 89:552587b429a1 369 #define __HAL_I2S_GET_FLAG(__HANDLE__, __FLAG__) ((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__))
bogdanm 89:552587b429a1 370
bogdanm 89:552587b429a1 371 /** @brief Clears the I2S OVR pending flag.
bogdanm 89:552587b429a1 372 * @param __HANDLE__: specifies the I2S Handle.
bogdanm 89:552587b429a1 373 * @retval None
bogdanm 89:552587b429a1 374 */
bogdanm 89:552587b429a1 375 #define __HAL_I2S_CLEAR_OVRFLAG(__HANDLE__) do{(__HANDLE__)->Instance->DR;\
bogdanm 89:552587b429a1 376 (__HANDLE__)->Instance->SR;}while(0)
bogdanm 89:552587b429a1 377 /** @brief Clears the I2S UDR pending flag.
bogdanm 89:552587b429a1 378 * @param __HANDLE__: specifies the I2S Handle.
bogdanm 89:552587b429a1 379 * @retval None
bogdanm 89:552587b429a1 380 */
bogdanm 89:552587b429a1 381 #define __HAL_I2S_CLEAR_UDRFLAG(__HANDLE__)((__HANDLE__)->Instance->SR)
bogdanm 89:552587b429a1 382
bogdanm 89:552587b429a1 383 /* Include I2S Extension module */
bogdanm 89:552587b429a1 384 #include "stm32f4xx_hal_i2s_ex.h"
bogdanm 89:552587b429a1 385
bogdanm 89:552587b429a1 386 /* Exported functions --------------------------------------------------------*/
bogdanm 89:552587b429a1 387
bogdanm 89:552587b429a1 388 /* Initialization/de-initialization functions **********************************/
bogdanm 89:552587b429a1 389 HAL_StatusTypeDef HAL_I2S_Init(I2S_HandleTypeDef *hi2s);
bogdanm 89:552587b429a1 390 HAL_StatusTypeDef HAL_I2S_DeInit (I2S_HandleTypeDef *hi2s);
bogdanm 89:552587b429a1 391 void HAL_I2S_MspInit(I2S_HandleTypeDef *hi2s);
bogdanm 89:552587b429a1 392 void HAL_I2S_MspDeInit(I2S_HandleTypeDef *hi2s);
bogdanm 89:552587b429a1 393
bogdanm 89:552587b429a1 394 /* I/O operation functions *****************************************************/
bogdanm 89:552587b429a1 395 /* Blocking mode: Polling */
bogdanm 89:552587b429a1 396 HAL_StatusTypeDef HAL_I2S_Transmit(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size, uint32_t Timeout);
bogdanm 89:552587b429a1 397 HAL_StatusTypeDef HAL_I2S_Receive(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size, uint32_t Timeout);
bogdanm 89:552587b429a1 398
bogdanm 89:552587b429a1 399 /* Non-Blocking mode: Interrupt */
bogdanm 89:552587b429a1 400 HAL_StatusTypeDef HAL_I2S_Transmit_IT(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size);
bogdanm 89:552587b429a1 401 HAL_StatusTypeDef HAL_I2S_Receive_IT(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size);
bogdanm 89:552587b429a1 402 void HAL_I2S_IRQHandler(I2S_HandleTypeDef *hi2s);
bogdanm 89:552587b429a1 403
bogdanm 89:552587b429a1 404 /* Non-Blocking mode: DMA */
bogdanm 89:552587b429a1 405 HAL_StatusTypeDef HAL_I2S_Transmit_DMA(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size);
bogdanm 89:552587b429a1 406 HAL_StatusTypeDef HAL_I2S_Receive_DMA(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size);
bogdanm 89:552587b429a1 407
bogdanm 89:552587b429a1 408 HAL_StatusTypeDef HAL_I2S_DMAPause(I2S_HandleTypeDef *hi2s);
bogdanm 89:552587b429a1 409 HAL_StatusTypeDef HAL_I2S_DMAResume(I2S_HandleTypeDef *hi2s);
bogdanm 89:552587b429a1 410 HAL_StatusTypeDef HAL_I2S_DMAStop(I2S_HandleTypeDef *hi2s);
bogdanm 89:552587b429a1 411
bogdanm 89:552587b429a1 412 /* Peripheral Control and State functions **************************************/
bogdanm 89:552587b429a1 413 HAL_I2S_StateTypeDef HAL_I2S_GetState(I2S_HandleTypeDef *hi2s);
bogdanm 89:552587b429a1 414 HAL_I2S_ErrorTypeDef HAL_I2S_GetError(I2S_HandleTypeDef *hi2s);
bogdanm 89:552587b429a1 415
bogdanm 89:552587b429a1 416 /* Callbacks used in non blocking modes (Interrupt and DMA) *******************/
bogdanm 89:552587b429a1 417 void HAL_I2S_TxHalfCpltCallback(I2S_HandleTypeDef *hi2s);
bogdanm 89:552587b429a1 418 void HAL_I2S_TxCpltCallback(I2S_HandleTypeDef *hi2s);
bogdanm 89:552587b429a1 419 void HAL_I2S_RxHalfCpltCallback(I2S_HandleTypeDef *hi2s);
bogdanm 89:552587b429a1 420 void HAL_I2S_RxCpltCallback(I2S_HandleTypeDef *hi2s);
bogdanm 89:552587b429a1 421 void HAL_I2S_ErrorCallback(I2S_HandleTypeDef *hi2s);
bogdanm 89:552587b429a1 422
bogdanm 89:552587b429a1 423 void I2S_DMATxCplt(DMA_HandleTypeDef *hdma);
bogdanm 89:552587b429a1 424 void I2S_DMATxHalfCplt(DMA_HandleTypeDef *hdma);
bogdanm 89:552587b429a1 425 void I2S_DMARxCplt(DMA_HandleTypeDef *hdma);
bogdanm 89:552587b429a1 426 void I2S_DMARxHalfCplt(DMA_HandleTypeDef *hdma);
bogdanm 89:552587b429a1 427 void I2S_DMAError(DMA_HandleTypeDef *hdma);
bogdanm 89:552587b429a1 428 HAL_StatusTypeDef I2S_WaitFlagStateUntilTimeout(I2S_HandleTypeDef *hi2s, uint32_t Flag, uint32_t Status, uint32_t Timeout);
bogdanm 89:552587b429a1 429
bogdanm 89:552587b429a1 430 /**
bogdanm 89:552587b429a1 431 * @}
bogdanm 89:552587b429a1 432 */
bogdanm 89:552587b429a1 433
bogdanm 89:552587b429a1 434 /**
bogdanm 89:552587b429a1 435 * @}
bogdanm 89:552587b429a1 436 */
bogdanm 89:552587b429a1 437
bogdanm 89:552587b429a1 438 #ifdef __cplusplus
bogdanm 89:552587b429a1 439 }
bogdanm 89:552587b429a1 440 #endif
bogdanm 89:552587b429a1 441
bogdanm 89:552587b429a1 442
bogdanm 89:552587b429a1 443 #endif /* __STM32F4xx_HAL_I2S_H */
bogdanm 89:552587b429a1 444
bogdanm 89:552587b429a1 445 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/