雄介 太田 / mbed

mbed(SerialHalfDuplex入り)

Fork of mbed by mbed official

TARGET_ARCH_MAX/stm32f4xx_ll_sdmmc.h@92:4fc01daae5a5, 2014-11-27 (annotated)

Committer:
bogdanm
Date:
Thu Nov 27 13:33:22 2014 +0000
Revision:
92:4fc01daae5a5
Parent:
89:552587b429a1 
Release 92 of the mbed libray



Main changes:



- nRF51822: fixed pin assignment issues

- ST targets moving to the STM32Cube driver

- LPC1439: fixed serial interrupt issue

- first Cortex-A platform supported in mbed (RZ_A1H)

Who changed what in which revision?

UserRevisionLine numberNew contents of line
bogdanm 89:552587b429a1 1 /**
bogdanm 89:552587b429a1 2 ******************************************************************************
bogdanm 89:552587b429a1 3 * @file stm32f4xx_ll_sdmmc.h
bogdanm 89:552587b429a1 4 * @author MCD Application Team
bogdanm 92:4fc01daae5a5 5 * @version V1.1.0
bogdanm 92:4fc01daae5a5 6 * @date 19-June-2014
bogdanm 89:552587b429a1 7 * @brief Header file of SDMMC HAL module.
bogdanm 89:552587b429a1 8 ******************************************************************************
bogdanm 89:552587b429a1 9 * @attention
bogdanm 89:552587b429a1 10 *
bogdanm 89:552587b429a1 11 * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
bogdanm 89:552587b429a1 12 *
bogdanm 89:552587b429a1 13 * Redistribution and use in source and binary forms, with or without modification,
bogdanm 89:552587b429a1 14 * are permitted provided that the following conditions are met:
bogdanm 89:552587b429a1 15 * 1. Redistributions of source code must retain the above copyright notice,
bogdanm 89:552587b429a1 16 * this list of conditions and the following disclaimer.
bogdanm 89:552587b429a1 17 * 2. Redistributions in binary form must reproduce the above copyright notice,
bogdanm 89:552587b429a1 18 * this list of conditions and the following disclaimer in the documentation
bogdanm 89:552587b429a1 19 * and/or other materials provided with the distribution.
bogdanm 89:552587b429a1 20 * 3. Neither the name of STMicroelectronics nor the names of its contributors
bogdanm 89:552587b429a1 21 * may be used to endorse or promote products derived from this software
bogdanm 89:552587b429a1 22 * without specific prior written permission.
bogdanm 89:552587b429a1 23 *
bogdanm 89:552587b429a1 24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
bogdanm 89:552587b429a1 25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
bogdanm 89:552587b429a1 26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
bogdanm 89:552587b429a1 27 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
bogdanm 89:552587b429a1 28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
bogdanm 89:552587b429a1 29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
bogdanm 89:552587b429a1 30 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
bogdanm 89:552587b429a1 31 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
bogdanm 89:552587b429a1 32 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
bogdanm 89:552587b429a1 33 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
bogdanm 89:552587b429a1 34 *
bogdanm 89:552587b429a1 35 ******************************************************************************
bogdanm 89:552587b429a1 36 */
bogdanm 89:552587b429a1 37
bogdanm 89:552587b429a1 38 /* Define to prevent recursive inclusion -------------------------------------*/
bogdanm 89:552587b429a1 39 #ifndef __STM32F4xx_LL_SDMMC_H
bogdanm 89:552587b429a1 40 #define __STM32F4xx_LL_SDMMC_H
bogdanm 89:552587b429a1 41
bogdanm 89:552587b429a1 42 #ifdef __cplusplus
bogdanm 89:552587b429a1 43 extern "C" {
bogdanm 89:552587b429a1 44 #endif
bogdanm 89:552587b429a1 45
bogdanm 89:552587b429a1 46 /* Includes ------------------------------------------------------------------*/
bogdanm 89:552587b429a1 47 #include "stm32f4xx_hal_def.h"
bogdanm 89:552587b429a1 48
bogdanm 89:552587b429a1 49 /** @addtogroup STM32F4xx_Driver
bogdanm 89:552587b429a1 50 * @{
bogdanm 89:552587b429a1 51 */
bogdanm 89:552587b429a1 52
bogdanm 89:552587b429a1 53 /** @addtogroup SDMMC
bogdanm 89:552587b429a1 54 * @{
bogdanm 89:552587b429a1 55 */
bogdanm 89:552587b429a1 56
bogdanm 89:552587b429a1 57 /* Exported types ------------------------------------------------------------*/
bogdanm 89:552587b429a1 58
bogdanm 92:4fc01daae5a5 59 /** @defgroup SDIO_Exported_Types SDIO Exported Types
bogdanm 92:4fc01daae5a5 60 * @{
bogdanm 92:4fc01daae5a5 61 */
bogdanm 92:4fc01daae5a5 62
bogdanm 89:552587b429a1 63 /**
bogdanm 89:552587b429a1 64 * @brief SDMMC Configuration Structure definition
bogdanm 89:552587b429a1 65 */
bogdanm 89:552587b429a1 66 typedef struct
bogdanm 89:552587b429a1 67 {
bogdanm 89:552587b429a1 68 uint32_t ClockEdge; /*!< Specifies the clock transition on which the bit capture is made.
bogdanm 89:552587b429a1 69 This parameter can be a value of @ref SDIO_Clock_Edge */
bogdanm 89:552587b429a1 70
bogdanm 89:552587b429a1 71 uint32_t ClockBypass; /*!< Specifies whether the SDIO Clock divider bypass is
bogdanm 89:552587b429a1 72 enabled or disabled.
bogdanm 89:552587b429a1 73 This parameter can be a value of @ref SDIO_Clock_Bypass */
bogdanm 89:552587b429a1 74
bogdanm 89:552587b429a1 75 uint32_t ClockPowerSave; /*!< Specifies whether SDIO Clock output is enabled or
bogdanm 89:552587b429a1 76 disabled when the bus is idle.
bogdanm 89:552587b429a1 77 This parameter can be a value of @ref SDIO_Clock_Power_Save */
bogdanm 89:552587b429a1 78
bogdanm 89:552587b429a1 79 uint32_t BusWide; /*!< Specifies the SDIO bus width.
bogdanm 89:552587b429a1 80 This parameter can be a value of @ref SDIO_Bus_Wide */
bogdanm 89:552587b429a1 81
bogdanm 89:552587b429a1 82 uint32_t HardwareFlowControl; /*!< Specifies whether the SDIO hardware flow control is enabled or disabled.
bogdanm 89:552587b429a1 83 This parameter can be a value of @ref SDIO_Hardware_Flow_Control */
bogdanm 89:552587b429a1 84
bogdanm 89:552587b429a1 85 uint32_t ClockDiv; /*!< Specifies the clock frequency of the SDIO controller.
bogdanm 89:552587b429a1 86 This parameter can be a value between Min_Data = 0 and Max_Data = 255 */
bogdanm 89:552587b429a1 87
bogdanm 89:552587b429a1 88 }SDIO_InitTypeDef;
bogdanm 89:552587b429a1 89
bogdanm 89:552587b429a1 90
bogdanm 89:552587b429a1 91 /**
bogdanm 89:552587b429a1 92 * @brief SDIO Command Control structure
bogdanm 89:552587b429a1 93 */
bogdanm 89:552587b429a1 94 typedef struct
bogdanm 89:552587b429a1 95 {
bogdanm 89:552587b429a1 96 uint32_t Argument; /*!< Specifies the SDIO command argument which is sent
bogdanm 89:552587b429a1 97 to a card as part of a command message. If a command
bogdanm 89:552587b429a1 98 contains an argument, it must be loaded into this register
bogdanm 89:552587b429a1 99 before writing the command to the command register. */
bogdanm 89:552587b429a1 100
bogdanm 89:552587b429a1 101 uint32_t CmdIndex; /*!< Specifies the SDIO command index. It must be Min_Data = 0 and
bogdanm 89:552587b429a1 102 Max_Data = 64 */
bogdanm 89:552587b429a1 103
bogdanm 89:552587b429a1 104 uint32_t Response; /*!< Specifies the SDIO response type.
bogdanm 89:552587b429a1 105 This parameter can be a value of @ref SDIO_Response_Type */
bogdanm 89:552587b429a1 106
bogdanm 89:552587b429a1 107 uint32_t WaitForInterrupt; /*!< Specifies whether SDIO wait for interrupt request is
bogdanm 89:552587b429a1 108 enabled or disabled.
bogdanm 89:552587b429a1 109 This parameter can be a value of @ref SDIO_Wait_Interrupt_State */
bogdanm 89:552587b429a1 110
bogdanm 89:552587b429a1 111 uint32_t CPSM; /*!< Specifies whether SDIO Command path state machine (CPSM)
bogdanm 89:552587b429a1 112 is enabled or disabled.
bogdanm 89:552587b429a1 113 This parameter can be a value of @ref SDIO_CPSM_State */
bogdanm 89:552587b429a1 114 }SDIO_CmdInitTypeDef;
bogdanm 89:552587b429a1 115
bogdanm 89:552587b429a1 116
bogdanm 89:552587b429a1 117 /**
bogdanm 89:552587b429a1 118 * @brief SDIO Data Control structure
bogdanm 89:552587b429a1 119 */
bogdanm 89:552587b429a1 120 typedef struct
bogdanm 89:552587b429a1 121 {
bogdanm 89:552587b429a1 122 uint32_t DataTimeOut; /*!< Specifies the data timeout period in card bus clock periods. */
bogdanm 89:552587b429a1 123
bogdanm 89:552587b429a1 124 uint32_t DataLength; /*!< Specifies the number of data bytes to be transferred. */
bogdanm 89:552587b429a1 125
bogdanm 89:552587b429a1 126 uint32_t DataBlockSize; /*!< Specifies the data block size for block transfer.
bogdanm 89:552587b429a1 127 This parameter can be a value of @ref SDIO_Data_Block_Size */
bogdanm 89:552587b429a1 128
bogdanm 89:552587b429a1 129 uint32_t TransferDir; /*!< Specifies the data transfer direction, whether the transfer
bogdanm 89:552587b429a1 130 is a read or write.
bogdanm 89:552587b429a1 131 This parameter can be a value of @ref SDIO_Transfer_Direction */
bogdanm 89:552587b429a1 132
bogdanm 89:552587b429a1 133 uint32_t TransferMode; /*!< Specifies whether data transfer is in stream or block mode.
bogdanm 89:552587b429a1 134 This parameter can be a value of @ref SDIO_Transfer_Type */
bogdanm 89:552587b429a1 135
bogdanm 89:552587b429a1 136 uint32_t DPSM; /*!< Specifies whether SDIO Data path state machine (DPSM)
bogdanm 89:552587b429a1 137 is enabled or disabled.
bogdanm 89:552587b429a1 138 This parameter can be a value of @ref SDIO_DPSM_State */
bogdanm 89:552587b429a1 139 }SDIO_DataInitTypeDef;
bogdanm 89:552587b429a1 140
bogdanm 92:4fc01daae5a5 141 /**
bogdanm 92:4fc01daae5a5 142 * @}
bogdanm 92:4fc01daae5a5 143 */
bogdanm 92:4fc01daae5a5 144
bogdanm 89:552587b429a1 145 /* Exported constants --------------------------------------------------------*/
bogdanm 89:552587b429a1 146
bogdanm 89:552587b429a1 147 /** @defgroup SDIO_Exported_Constants
bogdanm 89:552587b429a1 148 * @{
bogdanm 89:552587b429a1 149 */
bogdanm 89:552587b429a1 150
bogdanm 89:552587b429a1 151 /** @defgroup SDIO_Clock_Edge
bogdanm 89:552587b429a1 152 * @{
bogdanm 89:552587b429a1 153 */
bogdanm 89:552587b429a1 154 #define SDIO_CLOCK_EDGE_RISING ((uint32_t)0x00000000)
bogdanm 92:4fc01daae5a5 155 #define SDIO_CLOCK_EDGE_FALLING SDIO_CLKCR_NEGEDGE
bogdanm 89:552587b429a1 156
bogdanm 89:552587b429a1 157 #define IS_SDIO_CLOCK_EDGE(EDGE) (((EDGE) == SDIO_CLOCK_EDGE_RISING) || \
bogdanm 89:552587b429a1 158 ((EDGE) == SDIO_CLOCK_EDGE_FALLING))
bogdanm 89:552587b429a1 159 /**
bogdanm 89:552587b429a1 160 * @}
bogdanm 89:552587b429a1 161 */
bogdanm 89:552587b429a1 162
bogdanm 89:552587b429a1 163 /** @defgroup SDIO_Clock_Bypass
bogdanm 89:552587b429a1 164 * @{
bogdanm 89:552587b429a1 165 */
bogdanm 89:552587b429a1 166 #define SDIO_CLOCK_BYPASS_DISABLE ((uint32_t)0x00000000)
bogdanm 92:4fc01daae5a5 167 #define SDIO_CLOCK_BYPASS_ENABLE SDIO_CLKCR_BYPASS
bogdanm 89:552587b429a1 168
bogdanm 89:552587b429a1 169 #define IS_SDIO_CLOCK_BYPASS(BYPASS) (((BYPASS) == SDIO_CLOCK_BYPASS_DISABLE) || \
bogdanm 89:552587b429a1 170 ((BYPASS) == SDIO_CLOCK_BYPASS_ENABLE))
bogdanm 89:552587b429a1 171 /**
bogdanm 89:552587b429a1 172 * @}
bogdanm 89:552587b429a1 173 */
bogdanm 89:552587b429a1 174
bogdanm 89:552587b429a1 175 /** @defgroup SDIO_Clock_Power_Save
bogdanm 89:552587b429a1 176 * @{
bogdanm 89:552587b429a1 177 */
bogdanm 89:552587b429a1 178 #define SDIO_CLOCK_POWER_SAVE_DISABLE ((uint32_t)0x00000000)
bogdanm 92:4fc01daae5a5 179 #define SDIO_CLOCK_POWER_SAVE_ENABLE SDIO_CLKCR_PWRSAV
bogdanm 89:552587b429a1 180
bogdanm 89:552587b429a1 181 #define IS_SDIO_CLOCK_POWER_SAVE(SAVE) (((SAVE) == SDIO_CLOCK_POWER_SAVE_DISABLE) || \
bogdanm 89:552587b429a1 182 ((SAVE) == SDIO_CLOCK_POWER_SAVE_ENABLE))
bogdanm 89:552587b429a1 183 /**
bogdanm 89:552587b429a1 184 * @}
bogdanm 89:552587b429a1 185 */
bogdanm 89:552587b429a1 186
bogdanm 89:552587b429a1 187 /** @defgroup SDIO_Bus_Wide
bogdanm 89:552587b429a1 188 * @{
bogdanm 89:552587b429a1 189 */
bogdanm 89:552587b429a1 190 #define SDIO_BUS_WIDE_1B ((uint32_t)0x00000000)
bogdanm 92:4fc01daae5a5 191 #define SDIO_BUS_WIDE_4B SDIO_CLKCR_WIDBUS_0
bogdanm 92:4fc01daae5a5 192 #define SDIO_BUS_WIDE_8B SDIO_CLKCR_WIDBUS_1
bogdanm 89:552587b429a1 193
bogdanm 89:552587b429a1 194 #define IS_SDIO_BUS_WIDE(WIDE) (((WIDE) == SDIO_BUS_WIDE_1B) || \
bogdanm 89:552587b429a1 195 ((WIDE) == SDIO_BUS_WIDE_4B) || \
bogdanm 89:552587b429a1 196 ((WIDE) == SDIO_BUS_WIDE_8B))
bogdanm 89:552587b429a1 197 /**
bogdanm 89:552587b429a1 198 * @}
bogdanm 89:552587b429a1 199 */
bogdanm 89:552587b429a1 200
bogdanm 89:552587b429a1 201 /** @defgroup SDIO_Hardware_Flow_Control
bogdanm 89:552587b429a1 202 * @{
bogdanm 89:552587b429a1 203 */
bogdanm 89:552587b429a1 204 #define SDIO_HARDWARE_FLOW_CONTROL_DISABLE ((uint32_t)0x00000000)
bogdanm 92:4fc01daae5a5 205 #define SDIO_HARDWARE_FLOW_CONTROL_ENABLE SDIO_CLKCR_HWFC_EN
bogdanm 89:552587b429a1 206
bogdanm 89:552587b429a1 207 #define IS_SDIO_HARDWARE_FLOW_CONTROL(CONTROL) (((CONTROL) == SDIO_HARDWARE_FLOW_CONTROL_DISABLE) || \
bogdanm 89:552587b429a1 208 ((CONTROL) == SDIO_HARDWARE_FLOW_CONTROL_ENABLE))
bogdanm 89:552587b429a1 209 /**
bogdanm 89:552587b429a1 210 * @}
bogdanm 89:552587b429a1 211 */
bogdanm 89:552587b429a1 212
bogdanm 89:552587b429a1 213 /** @defgroup SDIO_Clock_Division
bogdanm 89:552587b429a1 214 * @{
bogdanm 89:552587b429a1 215 */
bogdanm 89:552587b429a1 216 #define IS_SDIO_CLKDIV(DIV) ((DIV) <= 0xFF)
bogdanm 89:552587b429a1 217 /**
bogdanm 89:552587b429a1 218 * @}
bogdanm 89:552587b429a1 219 */
bogdanm 89:552587b429a1 220
bogdanm 89:552587b429a1 221 /** @defgroup SDIO_Command_Index
bogdanm 89:552587b429a1 222 * @{
bogdanm 89:552587b429a1 223 */
bogdanm 89:552587b429a1 224 #define IS_SDIO_CMD_INDEX(INDEX) ((INDEX) < 0x40)
bogdanm 89:552587b429a1 225 /**
bogdanm 89:552587b429a1 226 * @}
bogdanm 89:552587b429a1 227 */
bogdanm 89:552587b429a1 228
bogdanm 89:552587b429a1 229 /** @defgroup SDIO_Response_Type
bogdanm 89:552587b429a1 230 * @{
bogdanm 89:552587b429a1 231 */
bogdanm 89:552587b429a1 232 #define SDIO_RESPONSE_NO ((uint32_t)0x00000000)
bogdanm 92:4fc01daae5a5 233 #define SDIO_RESPONSE_SHORT SDIO_CMD_WAITRESP_0
bogdanm 92:4fc01daae5a5 234 #define SDIO_RESPONSE_LONG SDIO_CMD_WAITRESP
bogdanm 89:552587b429a1 235
bogdanm 89:552587b429a1 236 #define IS_SDIO_RESPONSE(RESPONSE) (((RESPONSE) == SDIO_RESPONSE_NO) || \
bogdanm 89:552587b429a1 237 ((RESPONSE) == SDIO_RESPONSE_SHORT) || \
bogdanm 89:552587b429a1 238 ((RESPONSE) == SDIO_RESPONSE_LONG))
bogdanm 89:552587b429a1 239 /**
bogdanm 89:552587b429a1 240 * @}
bogdanm 89:552587b429a1 241 */
bogdanm 89:552587b429a1 242
bogdanm 89:552587b429a1 243 /** @defgroup SDIO_Wait_Interrupt_State
bogdanm 89:552587b429a1 244 * @{
bogdanm 89:552587b429a1 245 */
bogdanm 89:552587b429a1 246 #define SDIO_WAIT_NO ((uint32_t)0x00000000)
bogdanm 92:4fc01daae5a5 247 #define SDIO_WAIT_IT SDIO_CMD_WAITINT
bogdanm 92:4fc01daae5a5 248 #define SDIO_WAIT_PEND SDIO_CMD_WAITPEND
bogdanm 89:552587b429a1 249
bogdanm 89:552587b429a1 250 #define IS_SDIO_WAIT(WAIT) (((WAIT) == SDIO_WAIT_NO) || \
bogdanm 89:552587b429a1 251 ((WAIT) == SDIO_WAIT_IT) || \
bogdanm 89:552587b429a1 252 ((WAIT) == SDIO_WAIT_PEND))
bogdanm 89:552587b429a1 253 /**
bogdanm 89:552587b429a1 254 * @}
bogdanm 89:552587b429a1 255 */
bogdanm 89:552587b429a1 256
bogdanm 89:552587b429a1 257 /** @defgroup SDIO_CPSM_State
bogdanm 89:552587b429a1 258 * @{
bogdanm 89:552587b429a1 259 */
bogdanm 89:552587b429a1 260 #define SDIO_CPSM_DISABLE ((uint32_t)0x00000000)
bogdanm 92:4fc01daae5a5 261 #define SDIO_CPSM_ENABLE SDIO_CMD_CPSMEN
bogdanm 89:552587b429a1 262
bogdanm 89:552587b429a1 263 #define IS_SDIO_CPSM(CPSM) (((CPSM) == SDIO_CPSM_DISABLE) || \
bogdanm 89:552587b429a1 264 ((CPSM) == SDIO_CPSM_ENABLE))
bogdanm 89:552587b429a1 265 /**
bogdanm 89:552587b429a1 266 * @}
bogdanm 89:552587b429a1 267 */
bogdanm 89:552587b429a1 268
bogdanm 89:552587b429a1 269 /** @defgroup SDIO_Response_Registers
bogdanm 89:552587b429a1 270 * @{
bogdanm 89:552587b429a1 271 */
bogdanm 89:552587b429a1 272 #define SDIO_RESP1 ((uint32_t)0x00000000)
bogdanm 89:552587b429a1 273 #define SDIO_RESP2 ((uint32_t)0x00000004)
bogdanm 89:552587b429a1 274 #define SDIO_RESP3 ((uint32_t)0x00000008)
bogdanm 89:552587b429a1 275 #define SDIO_RESP4 ((uint32_t)0x0000000C)
bogdanm 89:552587b429a1 276
bogdanm 89:552587b429a1 277 #define IS_SDIO_RESP(RESP) (((RESP) == SDIO_RESP1) || \
bogdanm 89:552587b429a1 278 ((RESP) == SDIO_RESP2) || \
bogdanm 89:552587b429a1 279 ((RESP) == SDIO_RESP3) || \
bogdanm 89:552587b429a1 280 ((RESP) == SDIO_RESP4))
bogdanm 89:552587b429a1 281 /**
bogdanm 89:552587b429a1 282 * @}
bogdanm 89:552587b429a1 283 */
bogdanm 89:552587b429a1 284
bogdanm 89:552587b429a1 285 /** @defgroup SDIO_Data_Length
bogdanm 89:552587b429a1 286 * @{
bogdanm 89:552587b429a1 287 */
bogdanm 89:552587b429a1 288 #define IS_SDIO_DATA_LENGTH(LENGTH) ((LENGTH) <= 0x01FFFFFF)
bogdanm 89:552587b429a1 289 /**
bogdanm 89:552587b429a1 290 * @}
bogdanm 89:552587b429a1 291 */
bogdanm 89:552587b429a1 292
bogdanm 89:552587b429a1 293 /** @defgroup SDIO_Data_Block_Size
bogdanm 89:552587b429a1 294 * @{
bogdanm 89:552587b429a1 295 */
bogdanm 89:552587b429a1 296 #define SDIO_DATABLOCK_SIZE_1B ((uint32_t)0x00000000)
bogdanm 92:4fc01daae5a5 297 #define SDIO_DATABLOCK_SIZE_2B SDIO_DCTRL_DBLOCKSIZE_0
bogdanm 92:4fc01daae5a5 298 #define SDIO_DATABLOCK_SIZE_4B SDIO_DCTRL_DBLOCKSIZE_1
bogdanm 89:552587b429a1 299 #define SDIO_DATABLOCK_SIZE_8B ((uint32_t)0x00000030)
bogdanm 92:4fc01daae5a5 300 #define SDIO_DATABLOCK_SIZE_16B SDIO_DCTRL_DBLOCKSIZE_2
bogdanm 89:552587b429a1 301 #define SDIO_DATABLOCK_SIZE_32B ((uint32_t)0x00000050)
bogdanm 89:552587b429a1 302 #define SDIO_DATABLOCK_SIZE_64B ((uint32_t)0x00000060)
bogdanm 89:552587b429a1 303 #define SDIO_DATABLOCK_SIZE_128B ((uint32_t)0x00000070)
bogdanm 92:4fc01daae5a5 304 #define SDIO_DATABLOCK_SIZE_256B SDIO_DCTRL_DBLOCKSIZE_3
bogdanm 89:552587b429a1 305 #define SDIO_DATABLOCK_SIZE_512B ((uint32_t)0x00000090)
bogdanm 89:552587b429a1 306 #define SDIO_DATABLOCK_SIZE_1024B ((uint32_t)0x000000A0)
bogdanm 89:552587b429a1 307 #define SDIO_DATABLOCK_SIZE_2048B ((uint32_t)0x000000B0)
bogdanm 89:552587b429a1 308 #define SDIO_DATABLOCK_SIZE_4096B ((uint32_t)0x000000C0)
bogdanm 89:552587b429a1 309 #define SDIO_DATABLOCK_SIZE_8192B ((uint32_t)0x000000D0)
bogdanm 89:552587b429a1 310 #define SDIO_DATABLOCK_SIZE_16384B ((uint32_t)0x000000E0)
bogdanm 89:552587b429a1 311
bogdanm 89:552587b429a1 312 #define IS_SDIO_BLOCK_SIZE(SIZE) (((SIZE) == SDIO_DATABLOCK_SIZE_1B) || \
bogdanm 89:552587b429a1 313 ((SIZE) == SDIO_DATABLOCK_SIZE_2B) || \
bogdanm 89:552587b429a1 314 ((SIZE) == SDIO_DATABLOCK_SIZE_4B) || \
bogdanm 89:552587b429a1 315 ((SIZE) == SDIO_DATABLOCK_SIZE_8B) || \
bogdanm 89:552587b429a1 316 ((SIZE) == SDIO_DATABLOCK_SIZE_16B) || \
bogdanm 89:552587b429a1 317 ((SIZE) == SDIO_DATABLOCK_SIZE_32B) || \
bogdanm 89:552587b429a1 318 ((SIZE) == SDIO_DATABLOCK_SIZE_64B) || \
bogdanm 89:552587b429a1 319 ((SIZE) == SDIO_DATABLOCK_SIZE_128B) || \
bogdanm 89:552587b429a1 320 ((SIZE) == SDIO_DATABLOCK_SIZE_256B) || \
bogdanm 89:552587b429a1 321 ((SIZE) == SDIO_DATABLOCK_SIZE_512B) || \
bogdanm 89:552587b429a1 322 ((SIZE) == SDIO_DATABLOCK_SIZE_1024B) || \
bogdanm 89:552587b429a1 323 ((SIZE) == SDIO_DATABLOCK_SIZE_2048B) || \
bogdanm 89:552587b429a1 324 ((SIZE) == SDIO_DATABLOCK_SIZE_4096B) || \
bogdanm 89:552587b429a1 325 ((SIZE) == SDIO_DATABLOCK_SIZE_8192B) || \
bogdanm 89:552587b429a1 326 ((SIZE) == SDIO_DATABLOCK_SIZE_16384B))
bogdanm 89:552587b429a1 327 /**
bogdanm 89:552587b429a1 328 * @}
bogdanm 89:552587b429a1 329 */
bogdanm 89:552587b429a1 330
bogdanm 89:552587b429a1 331 /** @defgroup SDIO_Transfer_Direction
bogdanm 89:552587b429a1 332 * @{
bogdanm 89:552587b429a1 333 */
bogdanm 89:552587b429a1 334 #define SDIO_TRANSFER_DIR_TO_CARD ((uint32_t)0x00000000)
bogdanm 92:4fc01daae5a5 335 #define SDIO_TRANSFER_DIR_TO_SDIO SDIO_DCTRL_DTDIR
bogdanm 89:552587b429a1 336
bogdanm 89:552587b429a1 337 #define IS_SDIO_TRANSFER_DIR(DIR) (((DIR) == SDIO_TRANSFER_DIR_TO_CARD) || \
bogdanm 89:552587b429a1 338 ((DIR) == SDIO_TRANSFER_DIR_TO_SDIO))
bogdanm 89:552587b429a1 339 /**
bogdanm 89:552587b429a1 340 * @}
bogdanm 89:552587b429a1 341 */
bogdanm 89:552587b429a1 342
bogdanm 89:552587b429a1 343 /** @defgroup SDIO_Transfer_Type
bogdanm 89:552587b429a1 344 * @{
bogdanm 89:552587b429a1 345 */
bogdanm 89:552587b429a1 346 #define SDIO_TRANSFER_MODE_BLOCK ((uint32_t)0x00000000)
bogdanm 92:4fc01daae5a5 347 #define SDIO_TRANSFER_MODE_STREAM SDIO_DCTRL_DTMODE
bogdanm 89:552587b429a1 348
bogdanm 89:552587b429a1 349 #define IS_SDIO_TRANSFER_MODE(MODE) (((MODE) == SDIO_TRANSFER_MODE_BLOCK) || \
bogdanm 89:552587b429a1 350 ((MODE) == SDIO_TRANSFER_MODE_STREAM))
bogdanm 89:552587b429a1 351 /**
bogdanm 89:552587b429a1 352 * @}
bogdanm 89:552587b429a1 353 */
bogdanm 89:552587b429a1 354
bogdanm 89:552587b429a1 355 /** @defgroup SDIO_DPSM_State
bogdanm 89:552587b429a1 356 * @{
bogdanm 89:552587b429a1 357 */
bogdanm 89:552587b429a1 358 #define SDIO_DPSM_DISABLE ((uint32_t)0x00000000)
bogdanm 92:4fc01daae5a5 359 #define SDIO_DPSM_ENABLE SDIO_DCTRL_DTEN
bogdanm 89:552587b429a1 360
bogdanm 89:552587b429a1 361 #define IS_SDIO_DPSM(DPSM) (((DPSM) == SDIO_DPSM_DISABLE) ||\
bogdanm 89:552587b429a1 362 ((DPSM) == SDIO_DPSM_ENABLE))
bogdanm 89:552587b429a1 363 /**
bogdanm 89:552587b429a1 364 * @}
bogdanm 89:552587b429a1 365 */
bogdanm 89:552587b429a1 366
bogdanm 89:552587b429a1 367 /** @defgroup SDIO_Read_Wait_Mode
bogdanm 89:552587b429a1 368 * @{
bogdanm 89:552587b429a1 369 */
bogdanm 89:552587b429a1 370 #define SDIO_READ_WAIT_MODE_CLK ((uint32_t)0x00000000)
bogdanm 89:552587b429a1 371 #define SDIO_READ_WAIT_MODE_DATA2 ((uint32_t)0x00000001)
bogdanm 89:552587b429a1 372
bogdanm 89:552587b429a1 373 #define IS_SDIO_READWAIT_MODE(MODE) (((MODE) == SDIO_READ_WAIT_MODE_CLK) || \
bogdanm 89:552587b429a1 374 ((MODE) == SDIO_READ_WAIT_MODE_DATA2))
bogdanm 89:552587b429a1 375 /**
bogdanm 89:552587b429a1 376 * @}
bogdanm 89:552587b429a1 377 */
bogdanm 89:552587b429a1 378
bogdanm 89:552587b429a1 379 /** @defgroup SDIO_Interrupt_sources
bogdanm 89:552587b429a1 380 * @{
bogdanm 89:552587b429a1 381 */
bogdanm 92:4fc01daae5a5 382 #define SDIO_IT_CCRCFAIL SDIO_STA_CCRCFAIL
bogdanm 92:4fc01daae5a5 383 #define SDIO_IT_DCRCFAIL SDIO_STA_DCRCFAIL
bogdanm 92:4fc01daae5a5 384 #define SDIO_IT_CTIMEOUT SDIO_STA_CTIMEOUT
bogdanm 92:4fc01daae5a5 385 #define SDIO_IT_DTIMEOUT SDIO_STA_DTIMEOUT
bogdanm 92:4fc01daae5a5 386 #define SDIO_IT_TXUNDERR SDIO_STA_TXUNDERR
bogdanm 92:4fc01daae5a5 387 #define SDIO_IT_RXOVERR SDIO_STA_RXOVERR
bogdanm 92:4fc01daae5a5 388 #define SDIO_IT_CMDREND SDIO_STA_CMDREND
bogdanm 92:4fc01daae5a5 389 #define SDIO_IT_CMDSENT SDIO_STA_CMDSENT
bogdanm 92:4fc01daae5a5 390 #define SDIO_IT_DATAEND SDIO_STA_DATAEND
bogdanm 92:4fc01daae5a5 391 #define SDIO_IT_STBITERR SDIO_STA_STBITERR
bogdanm 92:4fc01daae5a5 392 #define SDIO_IT_DBCKEND SDIO_STA_DBCKEND
bogdanm 92:4fc01daae5a5 393 #define SDIO_IT_CMDACT SDIO_STA_CMDACT
bogdanm 92:4fc01daae5a5 394 #define SDIO_IT_TXACT SDIO_STA_TXACT
bogdanm 92:4fc01daae5a5 395 #define SDIO_IT_RXACT SDIO_STA_RXACT
bogdanm 92:4fc01daae5a5 396 #define SDIO_IT_TXFIFOHE SDIO_STA_TXFIFOHE
bogdanm 92:4fc01daae5a5 397 #define SDIO_IT_RXFIFOHF SDIO_STA_RXFIFOHF
bogdanm 92:4fc01daae5a5 398 #define SDIO_IT_TXFIFOF SDIO_STA_TXFIFOF
bogdanm 92:4fc01daae5a5 399 #define SDIO_IT_RXFIFOF SDIO_STA_RXFIFOF
bogdanm 92:4fc01daae5a5 400 #define SDIO_IT_TXFIFOE SDIO_STA_TXFIFOE
bogdanm 92:4fc01daae5a5 401 #define SDIO_IT_RXFIFOE SDIO_STA_RXFIFOE
bogdanm 92:4fc01daae5a5 402 #define SDIO_IT_TXDAVL SDIO_STA_TXDAVL
bogdanm 92:4fc01daae5a5 403 #define SDIO_IT_RXDAVL SDIO_STA_RXDAVL
bogdanm 92:4fc01daae5a5 404 #define SDIO_IT_SDIOIT SDIO_STA_SDIOIT
bogdanm 92:4fc01daae5a5 405 #define SDIO_IT_CEATAEND SDIO_STA_CEATAEND
bogdanm 89:552587b429a1 406
bogdanm 89:552587b429a1 407 #define IS_SDIO_IT(IT) ((((IT) & (uint32_t)0xFF000000) == 0x00) && ((IT) != (uint32_t)0x00))
bogdanm 89:552587b429a1 408 /**
bogdanm 89:552587b429a1 409 * @}
bogdanm 89:552587b429a1 410 */
bogdanm 89:552587b429a1 411
bogdanm 89:552587b429a1 412 /** @defgroup SDIO_Flags
bogdanm 89:552587b429a1 413 * @{
bogdanm 89:552587b429a1 414 */
bogdanm 92:4fc01daae5a5 415 #define SDIO_FLAG_CCRCFAIL SDIO_STA_CCRCFAIL
bogdanm 92:4fc01daae5a5 416 #define SDIO_FLAG_DCRCFAIL SDIO_STA_DCRCFAIL
bogdanm 92:4fc01daae5a5 417 #define SDIO_FLAG_CTIMEOUT SDIO_STA_CTIMEOUT
bogdanm 92:4fc01daae5a5 418 #define SDIO_FLAG_DTIMEOUT SDIO_STA_DTIMEOUT
bogdanm 92:4fc01daae5a5 419 #define SDIO_FLAG_TXUNDERR SDIO_STA_TXUNDERR
bogdanm 92:4fc01daae5a5 420 #define SDIO_FLAG_RXOVERR SDIO_STA_RXOVERR
bogdanm 92:4fc01daae5a5 421 #define SDIO_FLAG_CMDREND SDIO_STA_CMDREND
bogdanm 92:4fc01daae5a5 422 #define SDIO_FLAG_CMDSENT SDIO_STA_CMDSENT
bogdanm 92:4fc01daae5a5 423 #define SDIO_FLAG_DATAEND SDIO_STA_DATAEND
bogdanm 92:4fc01daae5a5 424 #define SDIO_FLAG_STBITERR SDIO_STA_STBITERR
bogdanm 92:4fc01daae5a5 425 #define SDIO_FLAG_DBCKEND SDIO_STA_DBCKEND
bogdanm 92:4fc01daae5a5 426 #define SDIO_FLAG_CMDACT SDIO_STA_CMDACT
bogdanm 92:4fc01daae5a5 427 #define SDIO_FLAG_TXACT SDIO_STA_TXACT
bogdanm 92:4fc01daae5a5 428 #define SDIO_FLAG_RXACT SDIO_STA_RXACT
bogdanm 92:4fc01daae5a5 429 #define SDIO_FLAG_TXFIFOHE SDIO_STA_TXFIFOHE
bogdanm 92:4fc01daae5a5 430 #define SDIO_FLAG_RXFIFOHF SDIO_STA_RXFIFOHF
bogdanm 92:4fc01daae5a5 431 #define SDIO_FLAG_TXFIFOF SDIO_STA_TXFIFOF
bogdanm 92:4fc01daae5a5 432 #define SDIO_FLAG_RXFIFOF SDIO_STA_RXFIFOF
bogdanm 92:4fc01daae5a5 433 #define SDIO_FLAG_TXFIFOE SDIO_STA_TXFIFOE
bogdanm 92:4fc01daae5a5 434 #define SDIO_FLAG_RXFIFOE SDIO_STA_RXFIFOE
bogdanm 92:4fc01daae5a5 435 #define SDIO_FLAG_TXDAVL SDIO_STA_TXDAVL
bogdanm 92:4fc01daae5a5 436 #define SDIO_FLAG_RXDAVL SDIO_STA_RXDAVL
bogdanm 92:4fc01daae5a5 437 #define SDIO_FLAG_SDIOIT SDIO_STA_SDIOIT
bogdanm 92:4fc01daae5a5 438 #define SDIO_FLAG_CEATAEND SDIO_STA_CEATAEND
bogdanm 89:552587b429a1 439
bogdanm 89:552587b429a1 440 #define IS_SDIO_FLAG(FLAG) (((FLAG) == SDIO_FLAG_CCRCFAIL) || \
bogdanm 89:552587b429a1 441 ((FLAG) == SDIO_FLAG_DCRCFAIL) || \
bogdanm 89:552587b429a1 442 ((FLAG) == SDIO_FLAG_CTIMEOUT) || \
bogdanm 89:552587b429a1 443 ((FLAG) == SDIO_FLAG_DTIMEOUT) || \
bogdanm 89:552587b429a1 444 ((FLAG) == SDIO_FLAG_TXUNDERR) || \
bogdanm 89:552587b429a1 445 ((FLAG) == SDIO_FLAG_RXOVERR) || \
bogdanm 89:552587b429a1 446 ((FLAG) == SDIO_FLAG_CMDREND) || \
bogdanm 89:552587b429a1 447 ((FLAG) == SDIO_FLAG_CMDSENT) || \
bogdanm 89:552587b429a1 448 ((FLAG) == SDIO_FLAG_DATAEND) || \
bogdanm 89:552587b429a1 449 ((FLAG) == SDIO_FLAG_STBITERR) || \
bogdanm 89:552587b429a1 450 ((FLAG) == SDIO_FLAG_DBCKEND) || \
bogdanm 89:552587b429a1 451 ((FLAG) == SDIO_FLAG_CMDACT) || \
bogdanm 89:552587b429a1 452 ((FLAG) == SDIO_FLAG_TXACT) || \
bogdanm 89:552587b429a1 453 ((FLAG) == SDIO_FLAG_RXACT) || \
bogdanm 89:552587b429a1 454 ((FLAG) == SDIO_FLAG_TXFIFOHE) || \
bogdanm 89:552587b429a1 455 ((FLAG) == SDIO_FLAG_RXFIFOHF) || \
bogdanm 89:552587b429a1 456 ((FLAG) == SDIO_FLAG_TXFIFOF) || \
bogdanm 89:552587b429a1 457 ((FLAG) == SDIO_FLAG_RXFIFOF) || \
bogdanm 89:552587b429a1 458 ((FLAG) == SDIO_FLAG_TXFIFOE) || \
bogdanm 89:552587b429a1 459 ((FLAG) == SDIO_FLAG_RXFIFOE) || \
bogdanm 89:552587b429a1 460 ((FLAG) == SDIO_FLAG_TXDAVL) || \
bogdanm 89:552587b429a1 461 ((FLAG) == SDIO_FLAG_RXDAVL) || \
bogdanm 89:552587b429a1 462 ((FLAG) == SDIO_FLAG_SDIOIT) || \
bogdanm 89:552587b429a1 463 ((FLAG) == SDIO_FLAG_CEATAEND))
bogdanm 89:552587b429a1 464
bogdanm 89:552587b429a1 465 #define IS_SDIO_CLEAR_FLAG(FLAG) ((((FLAG) & (uint32_t)0xFF3FF800) == 0x00) && ((FLAG) != (uint32_t)0x00))
bogdanm 89:552587b429a1 466
bogdanm 89:552587b429a1 467 #define IS_SDIO_GET_IT(IT) (((IT) == SDIO_IT_CCRCFAIL) || \
bogdanm 89:552587b429a1 468 ((IT) == SDIO_IT_DCRCFAIL) || \
bogdanm 89:552587b429a1 469 ((IT) == SDIO_IT_CTIMEOUT) || \
bogdanm 89:552587b429a1 470 ((IT) == SDIO_IT_DTIMEOUT) || \
bogdanm 89:552587b429a1 471 ((IT) == SDIO_IT_TXUNDERR) || \
bogdanm 89:552587b429a1 472 ((IT) == SDIO_IT_RXOVERR) || \
bogdanm 89:552587b429a1 473 ((IT) == SDIO_IT_CMDREND) || \
bogdanm 89:552587b429a1 474 ((IT) == SDIO_IT_CMDSENT) || \
bogdanm 89:552587b429a1 475 ((IT) == SDIO_IT_DATAEND) || \
bogdanm 89:552587b429a1 476 ((IT) == SDIO_IT_STBITERR) || \
bogdanm 89:552587b429a1 477 ((IT) == SDIO_IT_DBCKEND) || \
bogdanm 89:552587b429a1 478 ((IT) == SDIO_IT_CMDACT) || \
bogdanm 89:552587b429a1 479 ((IT) == SDIO_IT_TXACT) || \
bogdanm 89:552587b429a1 480 ((IT) == SDIO_IT_RXACT) || \
bogdanm 89:552587b429a1 481 ((IT) == SDIO_IT_TXFIFOHE) || \
bogdanm 89:552587b429a1 482 ((IT) == SDIO_IT_RXFIFOHF) || \
bogdanm 89:552587b429a1 483 ((IT) == SDIO_IT_TXFIFOF) || \
bogdanm 89:552587b429a1 484 ((IT) == SDIO_IT_RXFIFOF) || \
bogdanm 89:552587b429a1 485 ((IT) == SDIO_IT_TXFIFOE) || \
bogdanm 89:552587b429a1 486 ((IT) == SDIO_IT_RXFIFOE) || \
bogdanm 89:552587b429a1 487 ((IT) == SDIO_IT_TXDAVL) || \
bogdanm 89:552587b429a1 488 ((IT) == SDIO_IT_RXDAVL) || \
bogdanm 89:552587b429a1 489 ((IT) == SDIO_IT_SDIOIT) || \
bogdanm 89:552587b429a1 490 ((IT) == SDIO_IT_CEATAEND))
bogdanm 89:552587b429a1 491
bogdanm 89:552587b429a1 492 #define IS_SDIO_CLEAR_IT(IT) ((((IT) & (uint32_t)0xFF3FF800) == 0x00) && ((IT) != (uint32_t)0x00))
bogdanm 89:552587b429a1 493
bogdanm 89:552587b429a1 494 /**
bogdanm 89:552587b429a1 495 * @}
bogdanm 89:552587b429a1 496 */
bogdanm 89:552587b429a1 497
bogdanm 89:552587b429a1 498
bogdanm 89:552587b429a1 499 /** @defgroup SDIO_Instance_definition
bogdanm 89:552587b429a1 500 * @{
bogdanm 89:552587b429a1 501 */
bogdanm 89:552587b429a1 502 #define IS_SDIO_ALL_INSTANCE(INSTANCE) ((INSTANCE) == SDIO)
bogdanm 89:552587b429a1 503
bogdanm 89:552587b429a1 504 /**
bogdanm 89:552587b429a1 505 * @}
bogdanm 89:552587b429a1 506 */
bogdanm 89:552587b429a1 507
bogdanm 89:552587b429a1 508 /* Exported macro ------------------------------------------------------------*/
bogdanm 89:552587b429a1 509 /* ------------ SDIO registers bit address in the alias region -------------- */
bogdanm 89:552587b429a1 510 #define SDIO_OFFSET (SDIO_BASE - PERIPH_BASE)
bogdanm 89:552587b429a1 511
bogdanm 89:552587b429a1 512 /* --- CLKCR Register ---*/
bogdanm 89:552587b429a1 513 /* Alias word address of CLKEN bit */
bogdanm 89:552587b429a1 514 #define CLKCR_OFFSET (SDIO_OFFSET + 0x04)
bogdanm 89:552587b429a1 515 #define CLKEN_BitNumber 0x08
bogdanm 89:552587b429a1 516 #define CLKCR_CLKEN_BB (PERIPH_BB_BASE + (CLKCR_OFFSET * 32) + (CLKEN_BitNumber * 4))
bogdanm 89:552587b429a1 517
bogdanm 89:552587b429a1 518 /* --- CMD Register ---*/
bogdanm 89:552587b429a1 519 /* Alias word address of SDIOSUSPEND bit */
bogdanm 89:552587b429a1 520 #define CMD_OFFSET (SDIO_OFFSET + 0x0C)
bogdanm 89:552587b429a1 521 #define SDIOSUSPEND_BitNumber 0x0B
bogdanm 89:552587b429a1 522 #define CMD_SDIOSUSPEND_BB (PERIPH_BB_BASE + (CMD_OFFSET * 32) + (SDIOSUSPEND_BitNumber * 4))
bogdanm 89:552587b429a1 523
bogdanm 89:552587b429a1 524 /* Alias word address of ENCMDCOMPL bit */
bogdanm 89:552587b429a1 525 #define ENCMDCOMPL_BitNumber 0x0C
bogdanm 89:552587b429a1 526 #define CMD_ENCMDCOMPL_BB (PERIPH_BB_BASE + (CMD_OFFSET * 32) + (ENCMDCOMPL_BitNumber * 4))
bogdanm 89:552587b429a1 527
bogdanm 89:552587b429a1 528 /* Alias word address of NIEN bit */
bogdanm 89:552587b429a1 529 #define NIEN_BitNumber 0x0D
bogdanm 89:552587b429a1 530 #define CMD_NIEN_BB (PERIPH_BB_BASE + (CMD_OFFSET * 32) + (NIEN_BitNumber * 4))
bogdanm 89:552587b429a1 531
bogdanm 89:552587b429a1 532 /* Alias word address of ATACMD bit */
bogdanm 89:552587b429a1 533 #define ATACMD_BitNumber 0x0E
bogdanm 89:552587b429a1 534 #define CMD_ATACMD_BB (PERIPH_BB_BASE + (CMD_OFFSET * 32) + (ATACMD_BitNumber * 4))
bogdanm 89:552587b429a1 535
bogdanm 89:552587b429a1 536 /* --- DCTRL Register ---*/
bogdanm 89:552587b429a1 537 /* Alias word address of DMAEN bit */
bogdanm 89:552587b429a1 538 #define DCTRL_OFFSET (SDIO_OFFSET + 0x2C)
bogdanm 89:552587b429a1 539 #define DMAEN_BitNumber 0x03
bogdanm 89:552587b429a1 540 #define DCTRL_DMAEN_BB (PERIPH_BB_BASE + (DCTRL_OFFSET * 32) + (DMAEN_BitNumber * 4))
bogdanm 89:552587b429a1 541
bogdanm 89:552587b429a1 542 /* Alias word address of RWSTART bit */
bogdanm 89:552587b429a1 543 #define RWSTART_BitNumber 0x08
bogdanm 89:552587b429a1 544 #define DCTRL_RWSTART_BB (PERIPH_BB_BASE + (DCTRL_OFFSET * 32) + (RWSTART_BitNumber * 4))
bogdanm 89:552587b429a1 545
bogdanm 89:552587b429a1 546 /* Alias word address of RWSTOP bit */
bogdanm 89:552587b429a1 547 #define RWSTOP_BitNumber 0x09
bogdanm 89:552587b429a1 548 #define DCTRL_RWSTOP_BB (PERIPH_BB_BASE + (DCTRL_OFFSET * 32) + (RWSTOP_BitNumber * 4))
bogdanm 89:552587b429a1 549
bogdanm 89:552587b429a1 550 /* Alias word address of RWMOD bit */
bogdanm 89:552587b429a1 551 #define RWMOD_BitNumber 0x0A
bogdanm 89:552587b429a1 552 #define DCTRL_RWMOD_BB (PERIPH_BB_BASE + (DCTRL_OFFSET * 32) + (RWMOD_BitNumber * 4))
bogdanm 89:552587b429a1 553
bogdanm 89:552587b429a1 554 /* Alias word address of SDIOEN bit */
bogdanm 89:552587b429a1 555 #define SDIOEN_BitNumber 0x0B
bogdanm 89:552587b429a1 556 #define DCTRL_SDIOEN_BB (PERIPH_BB_BASE + (DCTRL_OFFSET * 32) + (SDIOEN_BitNumber * 4))
bogdanm 89:552587b429a1 557
bogdanm 89:552587b429a1 558 /* ---------------------- SDIO registers bit mask --------------------------- */
bogdanm 89:552587b429a1 559 /* --- CLKCR Register ---*/
bogdanm 92:4fc01daae5a5 560 /* CLKCR register clear mask */
bogdanm 92:4fc01daae5a5 561 #define CLKCR_CLEAR_MASK ((uint32_t)(SDIO_CLKCR_CLKDIV | SDIO_CLKCR_PWRSAV |\
bogdanm 92:4fc01daae5a5 562 SDIO_CLKCR_BYPASS | SDIO_CLKCR_WIDBUS |\
bogdanm 92:4fc01daae5a5 563 SDIO_CLKCR_NEGEDGE | SDIO_CLKCR_HWFC_EN))
bogdanm 89:552587b429a1 564
bogdanm 89:552587b429a1 565 /* --- PWRCTRL Register ---*/
bogdanm 89:552587b429a1 566 /* --- DCTRL Register ---*/
bogdanm 89:552587b429a1 567 /* SDIO DCTRL Clear Mask */
bogdanm 92:4fc01daae5a5 568 #define DCTRL_CLEAR_MASK ((uint32_t)(SDIO_DCTRL_DTEN | SDIO_DCTRL_DTDIR |\
bogdanm 92:4fc01daae5a5 569 SDIO_DCTRL_DTMODE | SDIO_DCTRL_DBLOCKSIZE))
bogdanm 89:552587b429a1 570
bogdanm 89:552587b429a1 571 /* --- CMD Register ---*/
bogdanm 89:552587b429a1 572 /* CMD Register clear mask */
bogdanm 92:4fc01daae5a5 573 #define CMD_CLEAR_MASK ((uint32_t)(SDIO_CMD_CMDINDEX | SDIO_CMD_WAITRESP |\
bogdanm 92:4fc01daae5a5 574 SDIO_CMD_WAITINT | SDIO_CMD_WAITPEND |\
bogdanm 92:4fc01daae5a5 575 SDIO_CMD_CPSMEN | SDIO_CMD_SDIOSUSPEND))
bogdanm 89:552587b429a1 576
bogdanm 89:552587b429a1 577 /* SDIO RESP Registers Address */
bogdanm 89:552587b429a1 578 #define SDIO_RESP_ADDR ((uint32_t)(SDIO_BASE + 0x14))
bogdanm 89:552587b429a1 579
bogdanm 89:552587b429a1 580 /* SDIO Intialization Frequency (400KHz max) */
bogdanm 89:552587b429a1 581 #define SDIO_INIT_CLK_DIV ((uint8_t)0x76)
bogdanm 89:552587b429a1 582
bogdanm 89:552587b429a1 583 /* SDIO Data Transfer Frequency (25MHz max) */
bogdanm 89:552587b429a1 584 #define SDIO_TRANSFER_CLK_DIV ((uint8_t)0x0)
bogdanm 89:552587b429a1 585
bogdanm 89:552587b429a1 586 /** @defgroup SDIO_Interrupt_Clock
bogdanm 89:552587b429a1 587 * @brief macros to handle interrupts and specific clock configurations
bogdanm 89:552587b429a1 588 * @{
bogdanm 89:552587b429a1 589 */
bogdanm 89:552587b429a1 590
bogdanm 89:552587b429a1 591 /**
bogdanm 89:552587b429a1 592 * @brief Enable the SDIO device.
bogdanm 89:552587b429a1 593 * @param None
bogdanm 89:552587b429a1 594 * @retval None
bogdanm 89:552587b429a1 595 */
bogdanm 89:552587b429a1 596 #define __SDIO_ENABLE() (*(__IO uint32_t *)CLKCR_CLKEN_BB = ENABLE)
bogdanm 89:552587b429a1 597
bogdanm 89:552587b429a1 598 /**
bogdanm 89:552587b429a1 599 * @brief Disable the SDIO device.
bogdanm 89:552587b429a1 600 * @param None
bogdanm 89:552587b429a1 601 * @retval None
bogdanm 89:552587b429a1 602 */
bogdanm 89:552587b429a1 603 #define __SDIO_DISABLE() (*(__IO uint32_t *)CLKCR_CLKEN_BB = DISABLE)
bogdanm 89:552587b429a1 604
bogdanm 89:552587b429a1 605 /**
bogdanm 89:552587b429a1 606 * @brief Enable the SDIO DMA transfer.
bogdanm 89:552587b429a1 607 * @param None
bogdanm 89:552587b429a1 608 * @retval None
bogdanm 89:552587b429a1 609 */
bogdanm 89:552587b429a1 610 #define __SDIO_DMA_ENABLE() (*(__IO uint32_t *)DCTRL_DMAEN_BB = ENABLE)
bogdanm 89:552587b429a1 611
bogdanm 89:552587b429a1 612 /**
bogdanm 89:552587b429a1 613 * @brief Disable the SDIO DMA transfer.
bogdanm 89:552587b429a1 614 * @param None
bogdanm 89:552587b429a1 615 * @retval None
bogdanm 89:552587b429a1 616 */
bogdanm 89:552587b429a1 617 #define __SDIO_DMA_DISABLE() (*(__IO uint32_t *)DCTRL_DMAEN_BB = DISABLE)
bogdanm 89:552587b429a1 618
bogdanm 89:552587b429a1 619 /**
bogdanm 89:552587b429a1 620 * @brief Enable the SDIO device interrupt.
bogdanm 89:552587b429a1 621 * @param __INSTANCE__ : Pointer to SDIO register base
bogdanm 89:552587b429a1 622 * @param __INTERRUPT__ : specifies the SDIO interrupt sources to be enabled.
bogdanm 89:552587b429a1 623 * This parameter can be one or a combination of the following values:
bogdanm 89:552587b429a1 624 * @arg SDIO_IT_CCRCFAIL: Command response received (CRC check failed) interrupt
bogdanm 89:552587b429a1 625 * @arg SDIO_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt
bogdanm 89:552587b429a1 626 * @arg SDIO_IT_CTIMEOUT: Command response timeout interrupt
bogdanm 89:552587b429a1 627 * @arg SDIO_IT_DTIMEOUT: Data timeout interrupt
bogdanm 89:552587b429a1 628 * @arg SDIO_IT_TXUNDERR: Transmit FIFO underrun error interrupt
bogdanm 89:552587b429a1 629 * @arg SDIO_IT_RXOVERR: Received FIFO overrun error interrupt
bogdanm 89:552587b429a1 630 * @arg SDIO_IT_CMDREND: Command response received (CRC check passed) interrupt
bogdanm 89:552587b429a1 631 * @arg SDIO_IT_CMDSENT: Command sent (no response required) interrupt
bogdanm 89:552587b429a1 632 * @arg SDIO_IT_DATAEND: Data end (data counter, SDIDCOUNT, is zero) interrupt
bogdanm 89:552587b429a1 633 * @arg SDIO_IT_STBITERR: Start bit not detected on all data signals in wide
bogdanm 89:552587b429a1 634 * bus mode interrupt
bogdanm 89:552587b429a1 635 * @arg SDIO_IT_DBCKEND: Data block sent/received (CRC check passed) interrupt
bogdanm 89:552587b429a1 636 * @arg SDIO_IT_CMDACT: Command transfer in progress interrupt
bogdanm 89:552587b429a1 637 * @arg SDIO_IT_TXACT: Data transmit in progress interrupt
bogdanm 89:552587b429a1 638 * @arg SDIO_IT_RXACT: Data receive in progress interrupt
bogdanm 89:552587b429a1 639 * @arg SDIO_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt
bogdanm 89:552587b429a1 640 * @arg SDIO_IT_RXFIFOHF: Receive FIFO Half Full interrupt
bogdanm 89:552587b429a1 641 * @arg SDIO_IT_TXFIFOF: Transmit FIFO full interrupt
bogdanm 89:552587b429a1 642 * @arg SDIO_IT_RXFIFOF: Receive FIFO full interrupt
bogdanm 89:552587b429a1 643 * @arg SDIO_IT_TXFIFOE: Transmit FIFO empty interrupt
bogdanm 89:552587b429a1 644 * @arg SDIO_IT_RXFIFOE: Receive FIFO empty interrupt
bogdanm 89:552587b429a1 645 * @arg SDIO_IT_TXDAVL: Data available in transmit FIFO interrupt
bogdanm 89:552587b429a1 646 * @arg SDIO_IT_RXDAVL: Data available in receive FIFO interrupt
bogdanm 89:552587b429a1 647 * @arg SDIO_IT_SDIOIT: SD I/O interrupt received interrupt
bogdanm 89:552587b429a1 648 * @arg SDIO_IT_CEATAEND: CE-ATA command completion signal received for CMD61 interrupt
bogdanm 89:552587b429a1 649 * @retval None
bogdanm 89:552587b429a1 650 */
bogdanm 89:552587b429a1 651 #define __SDIO_ENABLE_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->MASK |= (__INTERRUPT__))
bogdanm 89:552587b429a1 652
bogdanm 89:552587b429a1 653 /**
bogdanm 89:552587b429a1 654 * @brief Disable the SDIO device interrupt.
bogdanm 89:552587b429a1 655 * @param __INSTANCE__ : Pointer to SDIO register base
bogdanm 89:552587b429a1 656 * @param __INTERRUPT__ : specifies the SDIO interrupt sources to be disabled.
bogdanm 89:552587b429a1 657 * This parameter can be one or a combination of the following values:
bogdanm 89:552587b429a1 658 * @arg SDIO_IT_CCRCFAIL: Command response received (CRC check failed) interrupt
bogdanm 89:552587b429a1 659 * @arg SDIO_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt
bogdanm 89:552587b429a1 660 * @arg SDIO_IT_CTIMEOUT: Command response timeout interrupt
bogdanm 89:552587b429a1 661 * @arg SDIO_IT_DTIMEOUT: Data timeout interrupt
bogdanm 89:552587b429a1 662 * @arg SDIO_IT_TXUNDERR: Transmit FIFO underrun error interrupt
bogdanm 89:552587b429a1 663 * @arg SDIO_IT_RXOVERR: Received FIFO overrun error interrupt
bogdanm 89:552587b429a1 664 * @arg SDIO_IT_CMDREND: Command response received (CRC check passed) interrupt
bogdanm 89:552587b429a1 665 * @arg SDIO_IT_CMDSENT: Command sent (no response required) interrupt
bogdanm 89:552587b429a1 666 * @arg SDIO_IT_DATAEND: Data end (data counter, SDIDCOUNT, is zero) interrupt
bogdanm 89:552587b429a1 667 * @arg SDIO_IT_STBITERR: Start bit not detected on all data signals in wide
bogdanm 89:552587b429a1 668 * bus mode interrupt
bogdanm 89:552587b429a1 669 * @arg SDIO_IT_DBCKEND: Data block sent/received (CRC check passed) interrupt
bogdanm 89:552587b429a1 670 * @arg SDIO_IT_CMDACT: Command transfer in progress interrupt
bogdanm 89:552587b429a1 671 * @arg SDIO_IT_TXACT: Data transmit in progress interrupt
bogdanm 89:552587b429a1 672 * @arg SDIO_IT_RXACT: Data receive in progress interrupt
bogdanm 89:552587b429a1 673 * @arg SDIO_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt
bogdanm 89:552587b429a1 674 * @arg SDIO_IT_RXFIFOHF: Receive FIFO Half Full interrupt
bogdanm 89:552587b429a1 675 * @arg SDIO_IT_TXFIFOF: Transmit FIFO full interrupt
bogdanm 89:552587b429a1 676 * @arg SDIO_IT_RXFIFOF: Receive FIFO full interrupt
bogdanm 89:552587b429a1 677 * @arg SDIO_IT_TXFIFOE: Transmit FIFO empty interrupt
bogdanm 89:552587b429a1 678 * @arg SDIO_IT_RXFIFOE: Receive FIFO empty interrupt
bogdanm 89:552587b429a1 679 * @arg SDIO_IT_TXDAVL: Data available in transmit FIFO interrupt
bogdanm 89:552587b429a1 680 * @arg SDIO_IT_RXDAVL: Data available in receive FIFO interrupt
bogdanm 89:552587b429a1 681 * @arg SDIO_IT_SDIOIT: SD I/O interrupt received interrupt
bogdanm 89:552587b429a1 682 * @arg SDIO_IT_CEATAEND: CE-ATA command completion signal received for CMD61 interrupt
bogdanm 89:552587b429a1 683 * @retval None
bogdanm 89:552587b429a1 684 */
bogdanm 89:552587b429a1 685 #define __SDIO_DISABLE_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->MASK &= ~(__INTERRUPT__))
bogdanm 89:552587b429a1 686
bogdanm 89:552587b429a1 687 /**
bogdanm 89:552587b429a1 688 * @brief Checks whether the specified SDIO flag is set or not.
bogdanm 89:552587b429a1 689 * @param __INSTANCE__ : Pointer to SDIO register base
bogdanm 89:552587b429a1 690 * @param __FLAG__: specifies the flag to check.
bogdanm 89:552587b429a1 691 * This parameter can be one of the following values:
bogdanm 89:552587b429a1 692 * @arg SDIO_FLAG_CCRCFAIL: Command response received (CRC check failed)
bogdanm 89:552587b429a1 693 * @arg SDIO_FLAG_DCRCFAIL: Data block sent/received (CRC check failed)
bogdanm 89:552587b429a1 694 * @arg SDIO_FLAG_CTIMEOUT: Command response timeout
bogdanm 89:552587b429a1 695 * @arg SDIO_FLAG_DTIMEOUT: Data timeout
bogdanm 89:552587b429a1 696 * @arg SDIO_FLAG_TXUNDERR: Transmit FIFO underrun error
bogdanm 89:552587b429a1 697 * @arg SDIO_FLAG_RXOVERR: Received FIFO overrun error
bogdanm 89:552587b429a1 698 * @arg SDIO_FLAG_CMDREND: Command response received (CRC check passed)
bogdanm 89:552587b429a1 699 * @arg SDIO_FLAG_CMDSENT: Command sent (no response required)
bogdanm 89:552587b429a1 700 * @arg SDIO_FLAG_DATAEND: Data end (data counter, SDIDCOUNT, is zero)
bogdanm 89:552587b429a1 701 * @arg SDIO_FLAG_STBITERR: Start bit not detected on all data signals in wide bus mode.
bogdanm 89:552587b429a1 702 * @arg SDIO_FLAG_DBCKEND: Data block sent/received (CRC check passed)
bogdanm 89:552587b429a1 703 * @arg SDIO_FLAG_CMDACT: Command transfer in progress
bogdanm 89:552587b429a1 704 * @arg SDIO_FLAG_TXACT: Data transmit in progress
bogdanm 89:552587b429a1 705 * @arg SDIO_FLAG_RXACT: Data receive in progress
bogdanm 89:552587b429a1 706 * @arg SDIO_FLAG_TXFIFOHE: Transmit FIFO Half Empty
bogdanm 89:552587b429a1 707 * @arg SDIO_FLAG_RXFIFOHF: Receive FIFO Half Full
bogdanm 89:552587b429a1 708 * @arg SDIO_FLAG_TXFIFOF: Transmit FIFO full
bogdanm 89:552587b429a1 709 * @arg SDIO_FLAG_RXFIFOF: Receive FIFO full
bogdanm 89:552587b429a1 710 * @arg SDIO_FLAG_TXFIFOE: Transmit FIFO empty
bogdanm 89:552587b429a1 711 * @arg SDIO_FLAG_RXFIFOE: Receive FIFO empty
bogdanm 89:552587b429a1 712 * @arg SDIO_FLAG_TXDAVL: Data available in transmit FIFO
bogdanm 89:552587b429a1 713 * @arg SDIO_FLAG_RXDAVL: Data available in receive FIFO
bogdanm 89:552587b429a1 714 * @arg SDIO_FLAG_SDIOIT: SD I/O interrupt received
bogdanm 89:552587b429a1 715 * @arg SDIO_FLAG_CEATAEND: CE-ATA command completion signal received for CMD61
bogdanm 89:552587b429a1 716 * @retval The new state of SDIO_FLAG (SET or RESET).
bogdanm 89:552587b429a1 717 */
bogdanm 89:552587b429a1 718 #define __SDIO_GET_FLAG(__INSTANCE__, __FLAG__) (((__INSTANCE__)->STA &(__FLAG__)) != RESET)
bogdanm 89:552587b429a1 719
bogdanm 89:552587b429a1 720
bogdanm 89:552587b429a1 721 /**
bogdanm 92:4fc01daae5a5 722 * @brief Clears the SDIO pending flags.
bogdanm 89:552587b429a1 723 * @param __INSTANCE__ : Pointer to SDIO register base
bogdanm 89:552587b429a1 724 * @param __FLAG__: specifies the flag to clear.
bogdanm 89:552587b429a1 725 * This parameter can be one or a combination of the following values:
bogdanm 89:552587b429a1 726 * @arg SDIO_FLAG_CCRCFAIL: Command response received (CRC check failed)
bogdanm 89:552587b429a1 727 * @arg SDIO_FLAG_DCRCFAIL: Data block sent/received (CRC check failed)
bogdanm 89:552587b429a1 728 * @arg SDIO_FLAG_CTIMEOUT: Command response timeout
bogdanm 89:552587b429a1 729 * @arg SDIO_FLAG_DTIMEOUT: Data timeout
bogdanm 89:552587b429a1 730 * @arg SDIO_FLAG_TXUNDERR: Transmit FIFO underrun error
bogdanm 89:552587b429a1 731 * @arg SDIO_FLAG_RXOVERR: Received FIFO overrun error
bogdanm 89:552587b429a1 732 * @arg SDIO_FLAG_CMDREND: Command response received (CRC check passed)
bogdanm 89:552587b429a1 733 * @arg SDIO_FLAG_CMDSENT: Command sent (no response required)
bogdanm 89:552587b429a1 734 * @arg SDIO_FLAG_DATAEND: Data end (data counter, SDIDCOUNT, is zero)
bogdanm 89:552587b429a1 735 * @arg SDIO_FLAG_STBITERR: Start bit not detected on all data signals in wide bus mode
bogdanm 89:552587b429a1 736 * @arg SDIO_FLAG_DBCKEND: Data block sent/received (CRC check passed)
bogdanm 89:552587b429a1 737 * @arg SDIO_FLAG_SDIOIT: SD I/O interrupt received
bogdanm 89:552587b429a1 738 * @arg SDIO_FLAG_CEATAEND: CE-ATA command completion signal received for CMD61
bogdanm 89:552587b429a1 739 * @retval None
bogdanm 89:552587b429a1 740 */
bogdanm 89:552587b429a1 741 #define __SDIO_CLEAR_FLAG(__INSTANCE__, __FLAG__) ((__INSTANCE__)->ICR = (__FLAG__))
bogdanm 89:552587b429a1 742
bogdanm 89:552587b429a1 743 /**
bogdanm 89:552587b429a1 744 * @brief Checks whether the specified SDIO interrupt has occurred or not.
bogdanm 89:552587b429a1 745 * @param __INSTANCE__ : Pointer to SDIO register base
bogdanm 89:552587b429a1 746 * @param __INTERRUPT__: specifies the SDIO interrupt source to check.
bogdanm 89:552587b429a1 747 * This parameter can be one of the following values:
bogdanm 89:552587b429a1 748 * @arg SDIO_IT_CCRCFAIL: Command response received (CRC check failed) interrupt
bogdanm 89:552587b429a1 749 * @arg SDIO_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt
bogdanm 89:552587b429a1 750 * @arg SDIO_IT_CTIMEOUT: Command response timeout interrupt
bogdanm 89:552587b429a1 751 * @arg SDIO_IT_DTIMEOUT: Data timeout interrupt
bogdanm 89:552587b429a1 752 * @arg SDIO_IT_TXUNDERR: Transmit FIFO underrun error interrupt
bogdanm 89:552587b429a1 753 * @arg SDIO_IT_RXOVERR: Received FIFO overrun error interrupt
bogdanm 89:552587b429a1 754 * @arg SDIO_IT_CMDREND: Command response received (CRC check passed) interrupt
bogdanm 89:552587b429a1 755 * @arg SDIO_IT_CMDSENT: Command sent (no response required) interrupt
bogdanm 89:552587b429a1 756 * @arg SDIO_IT_DATAEND: Data end (data counter, SDIDCOUNT, is zero) interrupt
bogdanm 89:552587b429a1 757 * @arg SDIO_IT_STBITERR: Start bit not detected on all data signals in wide
bogdanm 89:552587b429a1 758 * bus mode interrupt
bogdanm 89:552587b429a1 759 * @arg SDIO_IT_DBCKEND: Data block sent/received (CRC check passed) interrupt
bogdanm 89:552587b429a1 760 * @arg SDIO_IT_CMDACT: Command transfer in progress interrupt
bogdanm 89:552587b429a1 761 * @arg SDIO_IT_TXACT: Data transmit in progress interrupt
bogdanm 89:552587b429a1 762 * @arg SDIO_IT_RXACT: Data receive in progress interrupt
bogdanm 89:552587b429a1 763 * @arg SDIO_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt
bogdanm 89:552587b429a1 764 * @arg SDIO_IT_RXFIFOHF: Receive FIFO Half Full interrupt
bogdanm 89:552587b429a1 765 * @arg SDIO_IT_TXFIFOF: Transmit FIFO full interrupt
bogdanm 89:552587b429a1 766 * @arg SDIO_IT_RXFIFOF: Receive FIFO full interrupt
bogdanm 89:552587b429a1 767 * @arg SDIO_IT_TXFIFOE: Transmit FIFO empty interrupt
bogdanm 89:552587b429a1 768 * @arg SDIO_IT_RXFIFOE: Receive FIFO empty interrupt
bogdanm 89:552587b429a1 769 * @arg SDIO_IT_TXDAVL: Data available in transmit FIFO interrupt
bogdanm 89:552587b429a1 770 * @arg SDIO_IT_RXDAVL: Data available in receive FIFO interrupt
bogdanm 89:552587b429a1 771 * @arg SDIO_IT_SDIOIT: SD I/O interrupt received interrupt
bogdanm 89:552587b429a1 772 * @arg SDIO_IT_CEATAEND: CE-ATA command completion signal received for CMD61 interrupt
bogdanm 89:552587b429a1 773 * @retval The new state of SDIO_IT (SET or RESET).
bogdanm 89:552587b429a1 774 */
bogdanm 89:552587b429a1 775 #define __SDIO_GET_IT (__INSTANCE__, __INTERRUPT__) (((__INSTANCE__)->STA &(__INTERRUPT__)) == (__INTERRUPT__))
bogdanm 89:552587b429a1 776
bogdanm 89:552587b429a1 777 /**
bogdanm 89:552587b429a1 778 * @brief Clears the SDIO's interrupt pending bits.
bogdanm 89:552587b429a1 779 * @param __INSTANCE__ : Pointer to SDIO register base
bogdanm 89:552587b429a1 780 * @param __INTERRUPT__: specifies the interrupt pending bit to clear.
bogdanm 89:552587b429a1 781 * This parameter can be one or a combination of the following values:
bogdanm 89:552587b429a1 782 * @arg SDIO_IT_CCRCFAIL: Command response received (CRC check failed) interrupt
bogdanm 89:552587b429a1 783 * @arg SDIO_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt
bogdanm 89:552587b429a1 784 * @arg SDIO_IT_CTIMEOUT: Command response timeout interrupt
bogdanm 89:552587b429a1 785 * @arg SDIO_IT_DTIMEOUT: Data timeout interrupt
bogdanm 89:552587b429a1 786 * @arg SDIO_IT_TXUNDERR: Transmit FIFO underrun error interrupt
bogdanm 89:552587b429a1 787 * @arg SDIO_IT_RXOVERR: Received FIFO overrun error interrupt
bogdanm 89:552587b429a1 788 * @arg SDIO_IT_CMDREND: Command response received (CRC check passed) interrupt
bogdanm 89:552587b429a1 789 * @arg SDIO_IT_CMDSENT: Command sent (no response required) interrupt
bogdanm 89:552587b429a1 790 * @arg SDIO_IT_DATAEND: Data end (data counter, SDIO_DCOUNT, is zero) interrupt
bogdanm 89:552587b429a1 791 * @arg SDIO_IT_STBITERR: Start bit not detected on all data signals in wide
bogdanm 89:552587b429a1 792 * bus mode interrupt
bogdanm 89:552587b429a1 793 * @arg SDIO_IT_SDIOIT: SD I/O interrupt received interrupt
bogdanm 89:552587b429a1 794 * @arg SDIO_IT_CEATAEND: CE-ATA command completion signal received for CMD61
bogdanm 89:552587b429a1 795 * @retval None
bogdanm 89:552587b429a1 796 */
bogdanm 89:552587b429a1 797 #define __SDIO_CLEAR_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->ICR = (__INTERRUPT__))
bogdanm 89:552587b429a1 798
bogdanm 89:552587b429a1 799 /**
bogdanm 89:552587b429a1 800 * @brief Enable Start the SD I/O Read Wait operation.
bogdanm 89:552587b429a1 801 * @param None
bogdanm 89:552587b429a1 802 * @retval None
bogdanm 89:552587b429a1 803 */
bogdanm 89:552587b429a1 804 #define __SDIO_START_READWAIT_ENABLE() (*(__IO uint32_t *) DCTRL_RWSTART_BB = ENABLE)
bogdanm 89:552587b429a1 805
bogdanm 89:552587b429a1 806 /**
bogdanm 89:552587b429a1 807 * @brief Disable Start the SD I/O Read Wait operations.
bogdanm 89:552587b429a1 808 * @param None
bogdanm 89:552587b429a1 809 * @retval None
bogdanm 89:552587b429a1 810 */
bogdanm 89:552587b429a1 811 #define __SDIO_START_READWAIT_DISABLE() (*(__IO uint32_t *) DCTRL_RWSTART_BB = DISABLE)
bogdanm 89:552587b429a1 812
bogdanm 89:552587b429a1 813 /**
bogdanm 89:552587b429a1 814 * @brief Enable Start the SD I/O Read Wait operation.
bogdanm 89:552587b429a1 815 * @param None
bogdanm 89:552587b429a1 816 * @retval None
bogdanm 89:552587b429a1 817 */
bogdanm 89:552587b429a1 818 #define __SDIO_STOP_READWAIT_ENABLE() (*(__IO uint32_t *) DCTRL_RWSTOP_BB = ENABLE)
bogdanm 89:552587b429a1 819
bogdanm 89:552587b429a1 820 /**
bogdanm 89:552587b429a1 821 * @brief Disable Stop the SD I/O Read Wait operations.
bogdanm 89:552587b429a1 822 * @param None
bogdanm 89:552587b429a1 823 * @retval None
bogdanm 89:552587b429a1 824 */
bogdanm 89:552587b429a1 825 #define __SDIO_STOP_READWAIT_DISABLE() (*(__IO uint32_t *) DCTRL_RWSTOP_BB = DISABLE)
bogdanm 89:552587b429a1 826
bogdanm 89:552587b429a1 827 /**
bogdanm 89:552587b429a1 828 * @brief Enable the SD I/O Mode Operation.
bogdanm 89:552587b429a1 829 * @param None
bogdanm 89:552587b429a1 830 * @retval None
bogdanm 89:552587b429a1 831 */
bogdanm 89:552587b429a1 832 #define __SDIO_OPERATION_ENABLE() (*(__IO uint32_t *) DCTRL_SDIOEN_BB = ENABLE)
bogdanm 89:552587b429a1 833
bogdanm 89:552587b429a1 834 /**
bogdanm 89:552587b429a1 835 * @brief Disable the SD I/O Mode Operation.
bogdanm 89:552587b429a1 836 * @param None
bogdanm 89:552587b429a1 837 * @retval None
bogdanm 89:552587b429a1 838 */
bogdanm 89:552587b429a1 839 #define __SDIO_OPERATION_DISABLE() (*(__IO uint32_t *) DCTRL_SDIOEN_BB = DISABLE)
bogdanm 89:552587b429a1 840
bogdanm 89:552587b429a1 841 /**
bogdanm 89:552587b429a1 842 * @brief Enable the SD I/O Suspend command sending.
bogdanm 89:552587b429a1 843 * @param None
bogdanm 89:552587b429a1 844 * @retval None
bogdanm 89:552587b429a1 845 */
bogdanm 89:552587b429a1 846 #define __SDIO_SUSPEND_CMD_ENABLE() (*(__IO uint32_t *) CMD_SDIOSUSPEND_BB = ENABLE)
bogdanm 89:552587b429a1 847
bogdanm 89:552587b429a1 848 /**
bogdanm 89:552587b429a1 849 * @brief Disable the SD I/O Suspend command sending.
bogdanm 89:552587b429a1 850 * @param None
bogdanm 89:552587b429a1 851 * @retval None
bogdanm 89:552587b429a1 852 */
bogdanm 89:552587b429a1 853 #define __SDIO_SUSPEND_CMD_DISABLE() (*(__IO uint32_t *) CMD_SDIOSUSPEND_BB = DISABLE)
bogdanm 89:552587b429a1 854
bogdanm 89:552587b429a1 855 /**
bogdanm 89:552587b429a1 856 * @brief Enable the command completion signal.
bogdanm 89:552587b429a1 857 * @param None
bogdanm 89:552587b429a1 858 * @retval None
bogdanm 89:552587b429a1 859 */
bogdanm 89:552587b429a1 860 #define __SDIO_CEATA_CMD_COMPLETION_ENABLE() (*(__IO uint32_t *) CMD_ENCMDCOMPL_BB = ENABLE)
bogdanm 89:552587b429a1 861
bogdanm 89:552587b429a1 862 /**
bogdanm 89:552587b429a1 863 * @brief Disable the command completion signal.
bogdanm 89:552587b429a1 864 * @param None
bogdanm 89:552587b429a1 865 * @retval None
bogdanm 89:552587b429a1 866 */
bogdanm 89:552587b429a1 867 #define __SDIO_CEATA_CMD_COMPLETION_DISABLE() (*(__IO uint32_t *) CMD_ENCMDCOMPL_BB = DISABLE)
bogdanm 89:552587b429a1 868
bogdanm 89:552587b429a1 869 /**
bogdanm 89:552587b429a1 870 * @brief Enable the CE-ATA interrupt.
bogdanm 89:552587b429a1 871 * @param None
bogdanm 89:552587b429a1 872 * @retval None
bogdanm 89:552587b429a1 873 */
bogdanm 89:552587b429a1 874 #define __SDIO_CEATA_ENABLE_IT() (*(__IO uint32_t *) CMD_NIEN_BB = (uint32_t)0)
bogdanm 89:552587b429a1 875
bogdanm 89:552587b429a1 876 /**
bogdanm 89:552587b429a1 877 * @brief Disable the CE-ATA interrupt.
bogdanm 89:552587b429a1 878 * @param None
bogdanm 89:552587b429a1 879 * @retval None
bogdanm 89:552587b429a1 880 */
bogdanm 89:552587b429a1 881 #define __SDIO_CEATA_DISABLE_IT() (*(__IO uint32_t *) CMD_NIEN_BB = (uint32_t)1)
bogdanm 89:552587b429a1 882
bogdanm 89:552587b429a1 883 /**
bogdanm 89:552587b429a1 884 * @brief Enable send CE-ATA command (CMD61).
bogdanm 89:552587b429a1 885 * @param None
bogdanm 89:552587b429a1 886 * @retval None
bogdanm 89:552587b429a1 887 */
bogdanm 89:552587b429a1 888 #define __SDIO_CEATA_SENDCMD_ENABLE() (*(__IO uint32_t *) CMD_ATACMD_BB = ENABLE)
bogdanm 89:552587b429a1 889
bogdanm 89:552587b429a1 890 /**
bogdanm 89:552587b429a1 891 * @brief Disable send CE-ATA command (CMD61).
bogdanm 89:552587b429a1 892 * @param None
bogdanm 89:552587b429a1 893 * @retval None
bogdanm 89:552587b429a1 894 */
bogdanm 89:552587b429a1 895 #define __SDIO_CEATA_SENDCMD_DISABLE() (*(__IO uint32_t *) CMD_ATACMD_BB = DISABLE)
bogdanm 89:552587b429a1 896
bogdanm 89:552587b429a1 897 /**
bogdanm 89:552587b429a1 898 * @}
bogdanm 89:552587b429a1 899 */
bogdanm 89:552587b429a1 900
bogdanm 92:4fc01daae5a5 901 /**
bogdanm 92:4fc01daae5a5 902 * @}
bogdanm 92:4fc01daae5a5 903 */
bogdanm 92:4fc01daae5a5 904
bogdanm 89:552587b429a1 905 /* Exported functions --------------------------------------------------------*/
bogdanm 92:4fc01daae5a5 906 /** @addtogroup SDIO_Exported_Functions
bogdanm 92:4fc01daae5a5 907 * @{
bogdanm 92:4fc01daae5a5 908 */
bogdanm 92:4fc01daae5a5 909
bogdanm 89:552587b429a1 910 /* Initialization/de-initialization functions **********************************/
bogdanm 92:4fc01daae5a5 911 /** @addtogroup HAL_SDIO_Group1
bogdanm 92:4fc01daae5a5 912 * @{
bogdanm 92:4fc01daae5a5 913 */
bogdanm 89:552587b429a1 914 HAL_StatusTypeDef SDIO_Init(SDIO_TypeDef *SDIOx, SDIO_InitTypeDef Init);
bogdanm 92:4fc01daae5a5 915 /**
bogdanm 92:4fc01daae5a5 916 * @}
bogdanm 92:4fc01daae5a5 917 */
bogdanm 92:4fc01daae5a5 918
bogdanm 89:552587b429a1 919 /* I/O operation functions *****************************************************/
bogdanm 92:4fc01daae5a5 920 /** @addtogroup HAL_SDIO_Group2
bogdanm 92:4fc01daae5a5 921 * @{
bogdanm 92:4fc01daae5a5 922 */
bogdanm 89:552587b429a1 923 /* Blocking mode: Polling */
bogdanm 89:552587b429a1 924 uint32_t SDIO_ReadFIFO(SDIO_TypeDef *SDIOx);
bogdanm 89:552587b429a1 925 HAL_StatusTypeDef SDIO_WriteFIFO(SDIO_TypeDef *SDIOx, uint32_t *pWriteData);
bogdanm 92:4fc01daae5a5 926 /**
bogdanm 92:4fc01daae5a5 927 * @}
bogdanm 92:4fc01daae5a5 928 */
bogdanm 92:4fc01daae5a5 929
bogdanm 89:552587b429a1 930 /* Peripheral Control functions ************************************************/
bogdanm 92:4fc01daae5a5 931 /** @addtogroup HAL_SDIO_Group3
bogdanm 92:4fc01daae5a5 932 * @{
bogdanm 92:4fc01daae5a5 933 */
bogdanm 89:552587b429a1 934 HAL_StatusTypeDef SDIO_PowerState_ON(SDIO_TypeDef *SDIOx);
bogdanm 89:552587b429a1 935 HAL_StatusTypeDef SDIO_PowerState_OFF(SDIO_TypeDef *SDIOx);
bogdanm 89:552587b429a1 936 uint32_t SDIO_GetPowerState(SDIO_TypeDef *SDIOx);
bogdanm 89:552587b429a1 937
bogdanm 89:552587b429a1 938 /* Command path state machine (CPSM) management functions */
bogdanm 89:552587b429a1 939 HAL_StatusTypeDef SDIO_SendCommand(SDIO_TypeDef *SDIOx, SDIO_CmdInitTypeDef *SDIO_CmdInitStruct);
bogdanm 89:552587b429a1 940 uint8_t SDIO_GetCommandResponse(SDIO_TypeDef *SDIOx);
bogdanm 89:552587b429a1 941 uint32_t SDIO_GetResponse(uint32_t SDIO_RESP);
bogdanm 89:552587b429a1 942
bogdanm 89:552587b429a1 943 /* Data path state machine (DPSM) management functions */
bogdanm 89:552587b429a1 944 HAL_StatusTypeDef SDIO_DataConfig(SDIO_TypeDef *SDIOx, SDIO_DataInitTypeDef* SDIO_DataInitStruct);
bogdanm 89:552587b429a1 945 uint32_t SDIO_GetDataCounter(SDIO_TypeDef *SDIOx);
bogdanm 89:552587b429a1 946 uint32_t SDIO_GetFIFOCount(SDIO_TypeDef *SDIOx);
bogdanm 89:552587b429a1 947
bogdanm 89:552587b429a1 948 /* SDIO IO Cards mode management functions */
bogdanm 89:552587b429a1 949 HAL_StatusTypeDef SDIO_SetSDIOReadWaitMode(uint32_t SDIO_ReadWaitMode);
bogdanm 89:552587b429a1 950
bogdanm 92:4fc01daae5a5 951 /**
bogdanm 92:4fc01daae5a5 952 * @}
bogdanm 92:4fc01daae5a5 953 */
bogdanm 92:4fc01daae5a5 954
bogdanm 92:4fc01daae5a5 955 /**
bogdanm 92:4fc01daae5a5 956 * @}
bogdanm 92:4fc01daae5a5 957 */
bogdanm 92:4fc01daae5a5 958
bogdanm 92:4fc01daae5a5 959 /**
bogdanm 92:4fc01daae5a5 960 * @}
bogdanm 92:4fc01daae5a5 961 */
bogdanm 92:4fc01daae5a5 962
bogdanm 92:4fc01daae5a5 963 /**
bogdanm 92:4fc01daae5a5 964 * @}
bogdanm 92:4fc01daae5a5 965 */
bogdanm 92:4fc01daae5a5 966
bogdanm 89:552587b429a1 967 #ifdef __cplusplus
bogdanm 89:552587b429a1 968 }
bogdanm 89:552587b429a1 969 #endif
bogdanm 89:552587b429a1 970
bogdanm 89:552587b429a1 971 #endif /* __STM32F4xx_LL_SDMMC_H */
bogdanm 89:552587b429a1 972
bogdanm 89:552587b429a1 973 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/