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TARGET_NUCLEO_F334R8/stm32f3xx_hal_tim.h@98:01a414ca7d6d, 2015-04-08 (annotated)

Committer:
yusuke_kyo
Date:
Wed Apr 08 08:04:18 2015 +0000
Revision:
98:01a414ca7d6d
Parent:
92:4fc01daae5a5 
remove SerialHalfDuplex.h

Who changed what in which revision?

UserRevisionLine numberNew contents of line
bogdanm 86:04dd9b1680ae 1 /**
bogdanm 86:04dd9b1680ae 2 ******************************************************************************
bogdanm 86:04dd9b1680ae 3 * @file stm32f3xx_hal_tim.h
bogdanm 86:04dd9b1680ae 4 * @author MCD Application Team
bogdanm 92:4fc01daae5a5 5 * @version V1.1.0
bogdanm 92:4fc01daae5a5 6 * @date 12-Sept-2014
bogdanm 86:04dd9b1680ae 7 * @brief Header file of TIM HAL module.
bogdanm 86:04dd9b1680ae 8 ******************************************************************************
bogdanm 86:04dd9b1680ae 9 * @attention
bogdanm 86:04dd9b1680ae 10 *
bogdanm 86:04dd9b1680ae 11 * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
bogdanm 86:04dd9b1680ae 12 *
bogdanm 86:04dd9b1680ae 13 * Redistribution and use in source and binary forms, with or without modification,
bogdanm 86:04dd9b1680ae 14 * are permitted provided that the following conditions are met:
bogdanm 86:04dd9b1680ae 15 * 1. Redistributions of source code must retain the above copyright notice,
bogdanm 86:04dd9b1680ae 16 * this list of conditions and the following disclaimer.
bogdanm 86:04dd9b1680ae 17 * 2. Redistributions in binary form must reproduce the above copyright notice,
bogdanm 86:04dd9b1680ae 18 * this list of conditions and the following disclaimer in the documentation
bogdanm 86:04dd9b1680ae 19 * and/or other materials provided with the distribution.
bogdanm 86:04dd9b1680ae 20 * 3. Neither the name of STMicroelectronics nor the names of its contributors
bogdanm 86:04dd9b1680ae 21 * may be used to endorse or promote products derived from this software
bogdanm 86:04dd9b1680ae 22 * without specific prior written permission.
bogdanm 86:04dd9b1680ae 23 *
bogdanm 86:04dd9b1680ae 24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
bogdanm 86:04dd9b1680ae 25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
bogdanm 86:04dd9b1680ae 26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
bogdanm 86:04dd9b1680ae 27 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
bogdanm 86:04dd9b1680ae 28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
bogdanm 86:04dd9b1680ae 29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
bogdanm 86:04dd9b1680ae 30 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
bogdanm 86:04dd9b1680ae 31 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
bogdanm 86:04dd9b1680ae 32 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
bogdanm 86:04dd9b1680ae 33 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
bogdanm 86:04dd9b1680ae 34 *
bogdanm 86:04dd9b1680ae 35 ******************************************************************************
bogdanm 86:04dd9b1680ae 36 */
bogdanm 86:04dd9b1680ae 37
bogdanm 86:04dd9b1680ae 38 /* Define to prevent recursive inclusion -------------------------------------*/
bogdanm 86:04dd9b1680ae 39 #ifndef __STM32F3xx_HAL_TIM_H
bogdanm 86:04dd9b1680ae 40 #define __STM32F3xx_HAL_TIM_H
bogdanm 86:04dd9b1680ae 41
bogdanm 86:04dd9b1680ae 42 #ifdef __cplusplus
bogdanm 86:04dd9b1680ae 43 extern "C" {
bogdanm 86:04dd9b1680ae 44 #endif
bogdanm 86:04dd9b1680ae 45
bogdanm 86:04dd9b1680ae 46 /* Includes ------------------------------------------------------------------*/
bogdanm 86:04dd9b1680ae 47 #include "stm32f3xx_hal_def.h"
bogdanm 86:04dd9b1680ae 48
bogdanm 86:04dd9b1680ae 49 /** @addtogroup STM32F3xx_HAL_Driver
bogdanm 86:04dd9b1680ae 50 * @{
bogdanm 86:04dd9b1680ae 51 */
bogdanm 86:04dd9b1680ae 52
bogdanm 86:04dd9b1680ae 53 /** @addtogroup TIM
bogdanm 86:04dd9b1680ae 54 * @{
bogdanm 86:04dd9b1680ae 55 */
bogdanm 86:04dd9b1680ae 56
bogdanm 86:04dd9b1680ae 57 /* Exported types ------------------------------------------------------------*/
bogdanm 92:4fc01daae5a5 58 /** @defgroup TIM_Exported_Types TIM Exported Types
bogdanm 92:4fc01daae5a5 59 * @{
bogdanm 92:4fc01daae5a5 60 */
bogdanm 86:04dd9b1680ae 61
bogdanm 86:04dd9b1680ae 62 /**
bogdanm 86:04dd9b1680ae 63 * @brief TIM Time base Configuration Structure definition
bogdanm 86:04dd9b1680ae 64 */
bogdanm 86:04dd9b1680ae 65 typedef struct
bogdanm 86:04dd9b1680ae 66 {
bogdanm 86:04dd9b1680ae 67 uint32_t Prescaler; /*!< Specifies the prescaler value used to divide the TIM clock.
bogdanm 86:04dd9b1680ae 68 This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */
bogdanm 86:04dd9b1680ae 69
bogdanm 86:04dd9b1680ae 70 uint32_t CounterMode; /*!< Specifies the counter mode.
bogdanm 86:04dd9b1680ae 71 This parameter can be a value of @ref TIM_Counter_Mode */
bogdanm 86:04dd9b1680ae 72
bogdanm 86:04dd9b1680ae 73 uint32_t Period; /*!< Specifies the period value to be loaded into the active
bogdanm 86:04dd9b1680ae 74 Auto-Reload Register at the next update event.
bogdanm 86:04dd9b1680ae 75 This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF. */
bogdanm 86:04dd9b1680ae 76
bogdanm 86:04dd9b1680ae 77 uint32_t ClockDivision; /*!< Specifies the clock division.
bogdanm 86:04dd9b1680ae 78 This parameter can be a value of @ref TIM_ClockDivision */
bogdanm 86:04dd9b1680ae 79
bogdanm 86:04dd9b1680ae 80 uint32_t RepetitionCounter; /*!< Specifies the repetition counter value. Each time the RCR downcounter
bogdanm 86:04dd9b1680ae 81 reaches zero, an update event is generated and counting restarts
bogdanm 86:04dd9b1680ae 82 from the RCR value (N).
bogdanm 86:04dd9b1680ae 83 This means in PWM mode that (N+1) corresponds to:
bogdanm 86:04dd9b1680ae 84 - the number of PWM periods in edge-aligned mode
bogdanm 86:04dd9b1680ae 85 - the number of half PWM period in center-aligned mode
bogdanm 86:04dd9b1680ae 86 This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF.
bogdanm 86:04dd9b1680ae 87 @note This parameter is valid only for TIM1 and TIM8. */
bogdanm 86:04dd9b1680ae 88 } TIM_Base_InitTypeDef;
bogdanm 86:04dd9b1680ae 89
bogdanm 86:04dd9b1680ae 90 /**
bogdanm 86:04dd9b1680ae 91 * @brief TIM Output Compare Configuration Structure definition
bogdanm 86:04dd9b1680ae 92 */
bogdanm 86:04dd9b1680ae 93 typedef struct
bogdanm 86:04dd9b1680ae 94 {
bogdanm 86:04dd9b1680ae 95 uint32_t OCMode; /*!< Specifies the TIM mode.
bogdanm 86:04dd9b1680ae 96 This parameter can be a value of @ref TIMEx_Output_Compare_and_PWM_modes */
bogdanm 86:04dd9b1680ae 97
bogdanm 86:04dd9b1680ae 98 uint32_t Pulse; /*!< Specifies the pulse value to be loaded into the Capture Compare Register.
bogdanm 86:04dd9b1680ae 99 This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */
bogdanm 86:04dd9b1680ae 100
bogdanm 86:04dd9b1680ae 101 uint32_t OCPolarity; /*!< Specifies the output polarity.
bogdanm 86:04dd9b1680ae 102 This parameter can be a value of @ref TIM_Output_Compare_Polarity */
bogdanm 86:04dd9b1680ae 103
bogdanm 86:04dd9b1680ae 104 uint32_t OCNPolarity; /*!< Specifies the complementary output polarity.
bogdanm 86:04dd9b1680ae 105 This parameter can be a value of @ref TIM_Output_Compare_N_Polarity
bogdanm 86:04dd9b1680ae 106 @note This parameter is valid only for TIM1 and TIM8. */
bogdanm 86:04dd9b1680ae 107
bogdanm 86:04dd9b1680ae 108 uint32_t OCFastMode; /*!< Specifies the Fast mode state.
bogdanm 86:04dd9b1680ae 109 This parameter can be a value of @ref TIM_Output_Fast_State
bogdanm 86:04dd9b1680ae 110 @note This parameter is valid only in PWM1 and PWM2 mode. */
bogdanm 86:04dd9b1680ae 111
bogdanm 86:04dd9b1680ae 112
bogdanm 86:04dd9b1680ae 113 uint32_t OCIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state.
bogdanm 86:04dd9b1680ae 114 This parameter can be a value of @ref TIM_Output_Compare_Idle_State
bogdanm 86:04dd9b1680ae 115 @note This parameter is valid only for TIM1 and TIM8. */
bogdanm 86:04dd9b1680ae 116
bogdanm 86:04dd9b1680ae 117 uint32_t OCNIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state.
bogdanm 86:04dd9b1680ae 118 This parameter can be a value of @ref TIM_Output_Compare_N_Idle_State
bogdanm 86:04dd9b1680ae 119 @note This parameter is valid only for TIM1 and TIM8. */
bogdanm 86:04dd9b1680ae 120 } TIM_OC_InitTypeDef;
bogdanm 86:04dd9b1680ae 121
bogdanm 86:04dd9b1680ae 122 /**
bogdanm 86:04dd9b1680ae 123 * @brief TIM One Pulse Mode Configuration Structure definition
bogdanm 86:04dd9b1680ae 124 */
bogdanm 86:04dd9b1680ae 125 typedef struct
bogdanm 86:04dd9b1680ae 126 {
bogdanm 86:04dd9b1680ae 127 uint32_t OCMode; /*!< Specifies the TIM mode.
bogdanm 86:04dd9b1680ae 128 This parameter can be a value of @ref TIMEx_Output_Compare_and_PWM_modes */
bogdanm 86:04dd9b1680ae 129
bogdanm 86:04dd9b1680ae 130 uint32_t Pulse; /*!< Specifies the pulse value to be loaded into the Capture Compare Register.
bogdanm 86:04dd9b1680ae 131 This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */
bogdanm 86:04dd9b1680ae 132
bogdanm 86:04dd9b1680ae 133 uint32_t OCPolarity; /*!< Specifies the output polarity.
bogdanm 86:04dd9b1680ae 134 This parameter can be a value of @ref TIM_Output_Compare_Polarity */
bogdanm 86:04dd9b1680ae 135
bogdanm 86:04dd9b1680ae 136 uint32_t OCNPolarity; /*!< Specifies the complementary output polarity.
bogdanm 86:04dd9b1680ae 137 This parameter can be a value of @ref TIM_Output_Compare_N_Polarity
bogdanm 86:04dd9b1680ae 138 @note This parameter is valid only for TIM1 and TIM8. */
bogdanm 86:04dd9b1680ae 139
bogdanm 86:04dd9b1680ae 140 uint32_t OCIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state.
bogdanm 86:04dd9b1680ae 141 This parameter can be a value of @ref TIM_Output_Compare_Idle_State
bogdanm 86:04dd9b1680ae 142 @note This parameter is valid only for TIM1 and TIM8. */
bogdanm 86:04dd9b1680ae 143
bogdanm 86:04dd9b1680ae 144 uint32_t OCNIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state.
bogdanm 86:04dd9b1680ae 145 This parameter can be a value of @ref TIM_Output_Compare_N_Idle_State
bogdanm 86:04dd9b1680ae 146 @note This parameter is valid only for TIM1 and TIM8. */
bogdanm 86:04dd9b1680ae 147
bogdanm 86:04dd9b1680ae 148 uint32_t ICPolarity; /*!< Specifies the active edge of the input signal.
bogdanm 86:04dd9b1680ae 149 This parameter can be a value of @ref TIM_Input_Capture_Polarity */
bogdanm 86:04dd9b1680ae 150
bogdanm 86:04dd9b1680ae 151 uint32_t ICSelection; /*!< Specifies the input.
bogdanm 86:04dd9b1680ae 152 This parameter can be a value of @ref TIM_Input_Capture_Selection */
bogdanm 86:04dd9b1680ae 153
bogdanm 86:04dd9b1680ae 154 uint32_t ICFilter; /*!< Specifies the input capture filter.
bogdanm 86:04dd9b1680ae 155 This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
bogdanm 86:04dd9b1680ae 156 } TIM_OnePulse_InitTypeDef;
bogdanm 86:04dd9b1680ae 157
bogdanm 86:04dd9b1680ae 158
bogdanm 86:04dd9b1680ae 159 /**
bogdanm 86:04dd9b1680ae 160 * @brief TIM Input Capture Configuration Structure definition
bogdanm 86:04dd9b1680ae 161 */
bogdanm 86:04dd9b1680ae 162 typedef struct
bogdanm 86:04dd9b1680ae 163 {
bogdanm 86:04dd9b1680ae 164 uint32_t ICPolarity; /*!< Specifies the active edge of the input signal.
bogdanm 86:04dd9b1680ae 165 This parameter can be a value of @ref TIM_Input_Capture_Polarity */
bogdanm 86:04dd9b1680ae 166
bogdanm 86:04dd9b1680ae 167 uint32_t ICSelection; /*!< Specifies the input.
bogdanm 86:04dd9b1680ae 168 This parameter can be a value of @ref TIM_Input_Capture_Selection */
bogdanm 86:04dd9b1680ae 169
bogdanm 86:04dd9b1680ae 170 uint32_t ICPrescaler; /*!< Specifies the Input Capture Prescaler.
bogdanm 86:04dd9b1680ae 171 This parameter can be a value of @ref TIM_Input_Capture_Prescaler */
bogdanm 86:04dd9b1680ae 172
bogdanm 86:04dd9b1680ae 173 uint32_t ICFilter; /*!< Specifies the input capture filter.
bogdanm 86:04dd9b1680ae 174 This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
bogdanm 86:04dd9b1680ae 175 } TIM_IC_InitTypeDef;
bogdanm 86:04dd9b1680ae 176
bogdanm 86:04dd9b1680ae 177 /**
bogdanm 86:04dd9b1680ae 178 * @brief TIM Encoder Configuration Structure definition
bogdanm 86:04dd9b1680ae 179 */
bogdanm 86:04dd9b1680ae 180 typedef struct
bogdanm 86:04dd9b1680ae 181 {
bogdanm 86:04dd9b1680ae 182 uint32_t EncoderMode; /*!< Specifies the active edge of the input signal.
bogdanm 86:04dd9b1680ae 183 This parameter can be a value of @ref TIM_Encoder_Mode */
bogdanm 86:04dd9b1680ae 184
bogdanm 86:04dd9b1680ae 185 uint32_t IC1Polarity; /*!< Specifies the active edge of the input signal.
bogdanm 86:04dd9b1680ae 186 This parameter can be a value of @ref TIM_Input_Capture_Polarity */
bogdanm 86:04dd9b1680ae 187
bogdanm 86:04dd9b1680ae 188 uint32_t IC1Selection; /*!< Specifies the input.
bogdanm 86:04dd9b1680ae 189 This parameter can be a value of @ref TIM_Input_Capture_Selection */
bogdanm 86:04dd9b1680ae 190
bogdanm 86:04dd9b1680ae 191 uint32_t IC1Prescaler; /*!< Specifies the Input Capture Prescaler.
bogdanm 86:04dd9b1680ae 192 This parameter can be a value of @ref TIM_Input_Capture_Prescaler */
bogdanm 86:04dd9b1680ae 193
bogdanm 86:04dd9b1680ae 194 uint32_t IC1Filter; /*!< Specifies the input capture filter.
bogdanm 86:04dd9b1680ae 195 This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
bogdanm 86:04dd9b1680ae 196
bogdanm 86:04dd9b1680ae 197 uint32_t IC2Polarity; /*!< Specifies the active edge of the input signal.
bogdanm 86:04dd9b1680ae 198 This parameter can be a value of @ref TIM_Input_Capture_Polarity */
bogdanm 86:04dd9b1680ae 199
bogdanm 86:04dd9b1680ae 200 uint32_t IC2Selection; /*!< Specifies the input.
bogdanm 86:04dd9b1680ae 201 This parameter can be a value of @ref TIM_Input_Capture_Selection */
bogdanm 86:04dd9b1680ae 202
bogdanm 86:04dd9b1680ae 203 uint32_t IC2Prescaler; /*!< Specifies the Input Capture Prescaler.
bogdanm 86:04dd9b1680ae 204 This parameter can be a value of @ref TIM_Input_Capture_Prescaler */
bogdanm 86:04dd9b1680ae 205
bogdanm 86:04dd9b1680ae 206 uint32_t IC2Filter; /*!< Specifies the input capture filter.
bogdanm 86:04dd9b1680ae 207 This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
bogdanm 86:04dd9b1680ae 208 } TIM_Encoder_InitTypeDef;
bogdanm 86:04dd9b1680ae 209
bogdanm 86:04dd9b1680ae 210
bogdanm 86:04dd9b1680ae 211 /**
bogdanm 86:04dd9b1680ae 212 * @brief Clock Configuration Handle Structure definition
bogdanm 86:04dd9b1680ae 213 */
bogdanm 86:04dd9b1680ae 214 typedef struct
bogdanm 86:04dd9b1680ae 215 {
bogdanm 86:04dd9b1680ae 216 uint32_t ClockSource; /*!< TIM clock sources
bogdanm 86:04dd9b1680ae 217 This parameter can be a value of @ref TIM_Clock_Source */
bogdanm 86:04dd9b1680ae 218 uint32_t ClockPolarity; /*!< TIM clock polarity
bogdanm 86:04dd9b1680ae 219 This parameter can be a value of @ref TIM_Clock_Polarity */
bogdanm 86:04dd9b1680ae 220 uint32_t ClockPrescaler; /*!< TIM clock prescaler
bogdanm 86:04dd9b1680ae 221 This parameter can be a value of @ref TIM_Clock_Prescaler */
bogdanm 86:04dd9b1680ae 222 uint32_t ClockFilter; /*!< TIM clock filter
bogdanm 86:04dd9b1680ae 223 This parameter can be a value of @ref TIM_Clock_Filter */
bogdanm 86:04dd9b1680ae 224 }TIM_ClockConfigTypeDef;
bogdanm 86:04dd9b1680ae 225
bogdanm 86:04dd9b1680ae 226 /**
bogdanm 86:04dd9b1680ae 227 * @brief Clear Input Configuration Handle Structure definition
bogdanm 86:04dd9b1680ae 228 */
bogdanm 86:04dd9b1680ae 229 typedef struct
bogdanm 86:04dd9b1680ae 230 {
bogdanm 86:04dd9b1680ae 231 uint32_t ClearInputState; /*!< TIM clear Input state
bogdanm 86:04dd9b1680ae 232 This parameter can be ENABLE or DISABLE */
bogdanm 86:04dd9b1680ae 233 uint32_t ClearInputSource; /*!< TIM clear Input sources
bogdanm 86:04dd9b1680ae 234 This parameter can be a value of @ref TIMEx_ClearInput_Source */
bogdanm 86:04dd9b1680ae 235 uint32_t ClearInputPolarity; /*!< TIM Clear Input polarity
bogdanm 86:04dd9b1680ae 236 This parameter can be a value of @ref TIM_ClearInput_Polarity */
bogdanm 86:04dd9b1680ae 237 uint32_t ClearInputPrescaler; /*!< TIM Clear Input prescaler
bogdanm 86:04dd9b1680ae 238 This parameter can be a value of @ref TIM_ClearInput_Prescaler */
bogdanm 86:04dd9b1680ae 239 uint32_t ClearInputFilter; /*!< TIM Clear Input filter
bogdanm 86:04dd9b1680ae 240 This parameter can be a value of @ref TIM_ClearInput_Filter */
bogdanm 86:04dd9b1680ae 241 }TIM_ClearInputConfigTypeDef;
bogdanm 86:04dd9b1680ae 242
bogdanm 86:04dd9b1680ae 243 /**
bogdanm 86:04dd9b1680ae 244 * @brief TIM Slave configuration Structure definition
bogdanm 86:04dd9b1680ae 245 */
bogdanm 86:04dd9b1680ae 246 typedef struct {
bogdanm 86:04dd9b1680ae 247 uint32_t SlaveMode; /*!< Slave mode selection
bogdanm 86:04dd9b1680ae 248 This parameter can be a value of @ref TIMEx_Slave_Mode */
bogdanm 86:04dd9b1680ae 249 uint32_t InputTrigger; /*!< Input Trigger source
bogdanm 86:04dd9b1680ae 250 This parameter can be a value of @ref TIM_Trigger_Selection */
bogdanm 86:04dd9b1680ae 251 uint32_t TriggerPolarity; /*!< Input Trigger polarity
bogdanm 86:04dd9b1680ae 252 This parameter can be a value of @ref TIM_Trigger_Polarity */
bogdanm 86:04dd9b1680ae 253 uint32_t TriggerPrescaler; /*!< Input trigger prescaler
bogdanm 86:04dd9b1680ae 254 This parameter can be a value of @ref TIM_Trigger_Prescaler */
bogdanm 86:04dd9b1680ae 255 uint32_t TriggerFilter; /*!< Input trigger filter
bogdanm 86:04dd9b1680ae 256 This parameter can be a value of @ref TIM_Trigger_Filter */
bogdanm 86:04dd9b1680ae 257
bogdanm 86:04dd9b1680ae 258 }TIM_SlaveConfigTypeDef;
bogdanm 86:04dd9b1680ae 259
bogdanm 86:04dd9b1680ae 260 /**
bogdanm 86:04dd9b1680ae 261 * @brief HAL State structures definition
bogdanm 86:04dd9b1680ae 262 */
bogdanm 86:04dd9b1680ae 263 typedef enum
bogdanm 86:04dd9b1680ae 264 {
bogdanm 86:04dd9b1680ae 265 HAL_TIM_STATE_RESET = 0x00, /*!< Peripheral not yet initialized or disabled */
bogdanm 86:04dd9b1680ae 266 HAL_TIM_STATE_READY = 0x01, /*!< Peripheral Initialized and ready for use */
bogdanm 86:04dd9b1680ae 267 HAL_TIM_STATE_BUSY = 0x02, /*!< An internal process is ongoing */
bogdanm 86:04dd9b1680ae 268 HAL_TIM_STATE_TIMEOUT = 0x03, /*!< Timeout state */
bogdanm 86:04dd9b1680ae 269 HAL_TIM_STATE_ERROR = 0x04 /*!< Reception process is ongoing */
bogdanm 86:04dd9b1680ae 270 }HAL_TIM_StateTypeDef;
bogdanm 86:04dd9b1680ae 271
bogdanm 86:04dd9b1680ae 272 /**
bogdanm 86:04dd9b1680ae 273 * @brief HAL Active channel structures definition
bogdanm 86:04dd9b1680ae 274 */
bogdanm 86:04dd9b1680ae 275 typedef enum
bogdanm 86:04dd9b1680ae 276 {
bogdanm 86:04dd9b1680ae 277 HAL_TIM_ACTIVE_CHANNEL_1 = 0x01, /*!< The active channel is 1 */
bogdanm 86:04dd9b1680ae 278 HAL_TIM_ACTIVE_CHANNEL_2 = 0x02, /*!< The active channel is 2 */
bogdanm 86:04dd9b1680ae 279 HAL_TIM_ACTIVE_CHANNEL_3 = 0x04, /*!< The active channel is 3 */
bogdanm 86:04dd9b1680ae 280 HAL_TIM_ACTIVE_CHANNEL_4 = 0x08, /*!< The active channel is 4 */
bogdanm 86:04dd9b1680ae 281 HAL_TIM_ACTIVE_CHANNEL_CLEARED = 0x00 /*!< All active channels cleared */
bogdanm 86:04dd9b1680ae 282 }HAL_TIM_ActiveChannel;
bogdanm 86:04dd9b1680ae 283
bogdanm 86:04dd9b1680ae 284 /**
bogdanm 86:04dd9b1680ae 285 * @brief TIM Time Base Handle Structure definition
bogdanm 86:04dd9b1680ae 286 */
bogdanm 86:04dd9b1680ae 287 typedef struct
bogdanm 86:04dd9b1680ae 288 {
bogdanm 86:04dd9b1680ae 289 TIM_TypeDef *Instance; /*!< Register base address */
bogdanm 86:04dd9b1680ae 290 TIM_Base_InitTypeDef Init; /*!< TIM Time Base required parameters */
bogdanm 86:04dd9b1680ae 291 HAL_TIM_ActiveChannel Channel; /*!< Active channel */
bogdanm 86:04dd9b1680ae 292 DMA_HandleTypeDef *hdma[7]; /*!< DMA Handlers array
bogdanm 86:04dd9b1680ae 293 This array is accessed by a @ref DMA_Handle_index */
bogdanm 86:04dd9b1680ae 294 HAL_LockTypeDef Lock; /*!< Locking object */
bogdanm 86:04dd9b1680ae 295 __IO HAL_TIM_StateTypeDef State; /*!< TIM operation state */
bogdanm 86:04dd9b1680ae 296 }TIM_HandleTypeDef;
bogdanm 86:04dd9b1680ae 297
bogdanm 92:4fc01daae5a5 298 /**
bogdanm 92:4fc01daae5a5 299 * @}
bogdanm 92:4fc01daae5a5 300 */
bogdanm 92:4fc01daae5a5 301
bogdanm 86:04dd9b1680ae 302 /* Exported constants --------------------------------------------------------*/
bogdanm 92:4fc01daae5a5 303 /** @defgroup TIM_Exported_Constants TIM Exported Constants
bogdanm 86:04dd9b1680ae 304 * @{
bogdanm 86:04dd9b1680ae 305 */
bogdanm 86:04dd9b1680ae 306
bogdanm 92:4fc01daae5a5 307 /** @defgroup TIM_Input_Channel_Polarity TIM Input Channel polarity
bogdanm 86:04dd9b1680ae 308 * @{
bogdanm 86:04dd9b1680ae 309 */
bogdanm 86:04dd9b1680ae 310 #define TIM_INPUTCHANNELPOLARITY_RISING ((uint32_t)0x00000000) /*!< Polarity for TIx source */
bogdanm 86:04dd9b1680ae 311 #define TIM_INPUTCHANNELPOLARITY_FALLING (TIM_CCER_CC1P) /*!< Polarity for TIx source */
bogdanm 86:04dd9b1680ae 312 #define TIM_INPUTCHANNELPOLARITY_BOTHEDGE (TIM_CCER_CC1P | TIM_CCER_CC1NP) /*!< Polarity for TIx source */
bogdanm 86:04dd9b1680ae 313 /**
bogdanm 86:04dd9b1680ae 314 * @}
bogdanm 86:04dd9b1680ae 315 */
bogdanm 86:04dd9b1680ae 316
bogdanm 92:4fc01daae5a5 317 /** @defgroup TIM_ETR_Polarity TIM ETR Polarity
bogdanm 86:04dd9b1680ae 318 * @{
bogdanm 86:04dd9b1680ae 319 */
bogdanm 86:04dd9b1680ae 320 #define TIM_ETRPOLARITY_INVERTED (TIM_SMCR_ETP) /*!< Polarity for ETR source */
bogdanm 86:04dd9b1680ae 321 #define TIM_ETRPOLARITY_NONINVERTED ((uint32_t)0x0000) /*!< Polarity for ETR source */
bogdanm 86:04dd9b1680ae 322 /**
bogdanm 86:04dd9b1680ae 323 * @}
bogdanm 86:04dd9b1680ae 324 */
bogdanm 86:04dd9b1680ae 325
bogdanm 92:4fc01daae5a5 326 /** @defgroup TIM_ETR_Prescaler TIM ETR Prescaler
bogdanm 86:04dd9b1680ae 327 * @{
bogdanm 86:04dd9b1680ae 328 */
bogdanm 86:04dd9b1680ae 329 #define TIM_ETRPRESCALER_DIV1 ((uint32_t)0x0000) /*!< No prescaler is used */
bogdanm 86:04dd9b1680ae 330 #define TIM_ETRPRESCALER_DIV2 (TIM_SMCR_ETPS_0) /*!< ETR input source is divided by 2 */
bogdanm 86:04dd9b1680ae 331 #define TIM_ETRPRESCALER_DIV4 (TIM_SMCR_ETPS_1) /*!< ETR input source is divided by 4 */
bogdanm 86:04dd9b1680ae 332 #define TIM_ETRPRESCALER_DIV8 (TIM_SMCR_ETPS) /*!< ETR input source is divided by 8 */
bogdanm 86:04dd9b1680ae 333 /**
bogdanm 86:04dd9b1680ae 334 * @}
bogdanm 86:04dd9b1680ae 335 */
bogdanm 86:04dd9b1680ae 336
bogdanm 92:4fc01daae5a5 337 /** @defgroup TIM_Counter_Mode TIM Counter Mode
bogdanm 86:04dd9b1680ae 338 * @{
bogdanm 86:04dd9b1680ae 339 */
bogdanm 86:04dd9b1680ae 340
bogdanm 86:04dd9b1680ae 341 #define TIM_COUNTERMODE_UP ((uint32_t)0x0000)
bogdanm 86:04dd9b1680ae 342 #define TIM_COUNTERMODE_DOWN TIM_CR1_DIR
bogdanm 86:04dd9b1680ae 343 #define TIM_COUNTERMODE_CENTERALIGNED1 TIM_CR1_CMS_0
bogdanm 86:04dd9b1680ae 344 #define TIM_COUNTERMODE_CENTERALIGNED2 TIM_CR1_CMS_1
bogdanm 86:04dd9b1680ae 345 #define TIM_COUNTERMODE_CENTERALIGNED3 TIM_CR1_CMS
bogdanm 86:04dd9b1680ae 346
bogdanm 86:04dd9b1680ae 347 #define IS_TIM_COUNTER_MODE(MODE) (((MODE) == TIM_COUNTERMODE_UP) || \
bogdanm 86:04dd9b1680ae 348 ((MODE) == TIM_COUNTERMODE_DOWN) || \
bogdanm 86:04dd9b1680ae 349 ((MODE) == TIM_COUNTERMODE_CENTERALIGNED1) || \
bogdanm 86:04dd9b1680ae 350 ((MODE) == TIM_COUNTERMODE_CENTERALIGNED2) || \
bogdanm 86:04dd9b1680ae 351 ((MODE) == TIM_COUNTERMODE_CENTERALIGNED3))
bogdanm 86:04dd9b1680ae 352 /**
bogdanm 86:04dd9b1680ae 353 * @}
bogdanm 86:04dd9b1680ae 354 */
bogdanm 86:04dd9b1680ae 355
bogdanm 92:4fc01daae5a5 356 /** @defgroup TIM_ClockDivision TIM Clock Division
bogdanm 86:04dd9b1680ae 357 * @{
bogdanm 86:04dd9b1680ae 358 */
bogdanm 86:04dd9b1680ae 359
bogdanm 86:04dd9b1680ae 360 #define TIM_CLOCKDIVISION_DIV1 ((uint32_t)0x0000)
bogdanm 86:04dd9b1680ae 361 #define TIM_CLOCKDIVISION_DIV2 (TIM_CR1_CKD_0)
bogdanm 86:04dd9b1680ae 362 #define TIM_CLOCKDIVISION_DIV4 (TIM_CR1_CKD_1)
bogdanm 86:04dd9b1680ae 363
bogdanm 86:04dd9b1680ae 364 #define IS_TIM_CLOCKDIVISION_DIV(DIV) (((DIV) == TIM_CLOCKDIVISION_DIV1) || \
bogdanm 86:04dd9b1680ae 365 ((DIV) == TIM_CLOCKDIVISION_DIV2) || \
bogdanm 86:04dd9b1680ae 366 ((DIV) == TIM_CLOCKDIVISION_DIV4))
bogdanm 86:04dd9b1680ae 367 /**
bogdanm 86:04dd9b1680ae 368 * @}
bogdanm 86:04dd9b1680ae 369 */
bogdanm 86:04dd9b1680ae 370
bogdanm 92:4fc01daae5a5 371 /** @defgroup TIM_Output_Compare_State TIM Output Compare State
bogdanm 86:04dd9b1680ae 372 * @{
bogdanm 86:04dd9b1680ae 373 */
bogdanm 86:04dd9b1680ae 374
bogdanm 86:04dd9b1680ae 375 #define TIM_OUTPUTSTATE_DISABLE ((uint32_t)0x0000)
bogdanm 86:04dd9b1680ae 376 #define TIM_OUTPUTSTATE_ENABLE (TIM_CCER_CC1E)
bogdanm 86:04dd9b1680ae 377
bogdanm 86:04dd9b1680ae 378 #define IS_TIM_OUTPUT_STATE(STATE) (((STATE) == TIM_OUTPUTSTATE_DISABLE) || \
bogdanm 86:04dd9b1680ae 379 ((STATE) == TIM_OUTPUTSTATE_ENABLE))
bogdanm 86:04dd9b1680ae 380 /**
bogdanm 86:04dd9b1680ae 381 * @}
bogdanm 86:04dd9b1680ae 382 */
bogdanm 92:4fc01daae5a5 383 /** @defgroup TIM_Output_Fast_State TIM Output Fast State
bogdanm 86:04dd9b1680ae 384 * @{
bogdanm 86:04dd9b1680ae 385 */
bogdanm 86:04dd9b1680ae 386 #define TIM_OCFAST_DISABLE ((uint32_t)0x0000)
bogdanm 86:04dd9b1680ae 387 #define TIM_OCFAST_ENABLE (TIM_CCMR1_OC1FE)
bogdanm 86:04dd9b1680ae 388
bogdanm 86:04dd9b1680ae 389 #define IS_TIM_FAST_STATE(STATE) (((STATE) == TIM_OCFAST_DISABLE) || \
bogdanm 86:04dd9b1680ae 390 ((STATE) == TIM_OCFAST_ENABLE))
bogdanm 86:04dd9b1680ae 391 /**
bogdanm 86:04dd9b1680ae 392 * @}
bogdanm 86:04dd9b1680ae 393 */
bogdanm 92:4fc01daae5a5 394 /** @defgroup TIM_Output_Compare_N_State TIM Complementary Output Compare State
bogdanm 86:04dd9b1680ae 395 * @{
bogdanm 86:04dd9b1680ae 396 */
bogdanm 86:04dd9b1680ae 397
bogdanm 86:04dd9b1680ae 398 #define TIM_OUTPUTNSTATE_DISABLE ((uint32_t)0x0000)
bogdanm 86:04dd9b1680ae 399 #define TIM_OUTPUTNSTATE_ENABLE (TIM_CCER_CC1NE)
bogdanm 86:04dd9b1680ae 400
bogdanm 86:04dd9b1680ae 401 #define IS_TIM_OUTPUTN_STATE(STATE) (((STATE) == TIM_OUTPUTNSTATE_DISABLE) || \
bogdanm 86:04dd9b1680ae 402 ((STATE) == TIM_OUTPUTNSTATE_ENABLE))
bogdanm 86:04dd9b1680ae 403 /**
bogdanm 86:04dd9b1680ae 404 * @}
bogdanm 86:04dd9b1680ae 405 */
bogdanm 86:04dd9b1680ae 406
bogdanm 92:4fc01daae5a5 407 /** @defgroup TIM_Output_Compare_Polarity TIM Output Compare Polarity
bogdanm 86:04dd9b1680ae 408 * @{
bogdanm 86:04dd9b1680ae 409 */
bogdanm 86:04dd9b1680ae 410
bogdanm 86:04dd9b1680ae 411 #define TIM_OCPOLARITY_HIGH ((uint32_t)0x0000)
bogdanm 86:04dd9b1680ae 412 #define TIM_OCPOLARITY_LOW (TIM_CCER_CC1P)
bogdanm 86:04dd9b1680ae 413
bogdanm 86:04dd9b1680ae 414 #define IS_TIM_OC_POLARITY(POLARITY) (((POLARITY) == TIM_OCPOLARITY_HIGH) || \
bogdanm 86:04dd9b1680ae 415 ((POLARITY) == TIM_OCPOLARITY_LOW))
bogdanm 86:04dd9b1680ae 416 /**
bogdanm 86:04dd9b1680ae 417 * @}
bogdanm 86:04dd9b1680ae 418 */
bogdanm 86:04dd9b1680ae 419
bogdanm 92:4fc01daae5a5 420 /** @defgroup TIM_Output_Compare_N_Polarity TIM Complementary Output Compare Polarity
bogdanm 86:04dd9b1680ae 421 * @{
bogdanm 86:04dd9b1680ae 422 */
bogdanm 86:04dd9b1680ae 423
bogdanm 86:04dd9b1680ae 424 #define TIM_OCNPOLARITY_HIGH ((uint32_t)0x0000)
bogdanm 86:04dd9b1680ae 425 #define TIM_OCNPOLARITY_LOW (TIM_CCER_CC1NP)
bogdanm 86:04dd9b1680ae 426
bogdanm 86:04dd9b1680ae 427 #define IS_TIM_OCN_POLARITY(POLARITY) (((POLARITY) == TIM_OCNPOLARITY_HIGH) || \
bogdanm 86:04dd9b1680ae 428 ((POLARITY) == TIM_OCNPOLARITY_LOW))
bogdanm 86:04dd9b1680ae 429 /**
bogdanm 86:04dd9b1680ae 430 * @}
bogdanm 86:04dd9b1680ae 431 */
bogdanm 86:04dd9b1680ae 432
bogdanm 92:4fc01daae5a5 433 /** @defgroup TIM_Output_Compare_Idle_State TIM Output Compare Idle State
bogdanm 86:04dd9b1680ae 434 * @{
bogdanm 86:04dd9b1680ae 435 */
bogdanm 86:04dd9b1680ae 436
bogdanm 86:04dd9b1680ae 437 #define TIM_OCIDLESTATE_SET (TIM_CR2_OIS1)
bogdanm 86:04dd9b1680ae 438 #define TIM_OCIDLESTATE_RESET ((uint32_t)0x0000)
bogdanm 86:04dd9b1680ae 439 #define IS_TIM_OCIDLE_STATE(STATE) (((STATE) == TIM_OCIDLESTATE_SET) || \
bogdanm 86:04dd9b1680ae 440 ((STATE) == TIM_OCIDLESTATE_RESET))
bogdanm 86:04dd9b1680ae 441 /**
bogdanm 86:04dd9b1680ae 442 * @}
bogdanm 86:04dd9b1680ae 443 */
bogdanm 86:04dd9b1680ae 444
bogdanm 92:4fc01daae5a5 445 /** @defgroup TIM_Output_Compare_N_Idle_State TIM Complementary Output Compare Idle State
bogdanm 86:04dd9b1680ae 446 * @{
bogdanm 86:04dd9b1680ae 447 */
bogdanm 86:04dd9b1680ae 448
bogdanm 86:04dd9b1680ae 449 #define TIM_OCNIDLESTATE_SET (TIM_CR2_OIS1N)
bogdanm 86:04dd9b1680ae 450 #define TIM_OCNIDLESTATE_RESET ((uint32_t)0x0000)
bogdanm 86:04dd9b1680ae 451 #define IS_TIM_OCNIDLE_STATE(STATE) (((STATE) == TIM_OCNIDLESTATE_SET) || \
bogdanm 86:04dd9b1680ae 452 ((STATE) == TIM_OCNIDLESTATE_RESET))
bogdanm 86:04dd9b1680ae 453 /**
bogdanm 86:04dd9b1680ae 454 * @}
bogdanm 86:04dd9b1680ae 455 */
bogdanm 86:04dd9b1680ae 456
bogdanm 86:04dd9b1680ae 457
bogdanm 86:04dd9b1680ae 458
bogdanm 92:4fc01daae5a5 459 /** @defgroup TIM_Input_Capture_Polarity TIM Input Capture Polarity
bogdanm 86:04dd9b1680ae 460 * @{
bogdanm 86:04dd9b1680ae 461 */
bogdanm 86:04dd9b1680ae 462
bogdanm 86:04dd9b1680ae 463 #define TIM_ICPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING
bogdanm 86:04dd9b1680ae 464 #define TIM_ICPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING
bogdanm 86:04dd9b1680ae 465 #define TIM_ICPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE
bogdanm 86:04dd9b1680ae 466
bogdanm 86:04dd9b1680ae 467 #define IS_TIM_IC_POLARITY(POLARITY) (((POLARITY) == TIM_ICPOLARITY_RISING) || \
bogdanm 86:04dd9b1680ae 468 ((POLARITY) == TIM_ICPOLARITY_FALLING) || \
bogdanm 86:04dd9b1680ae 469 ((POLARITY) == TIM_ICPOLARITY_BOTHEDGE))
bogdanm 86:04dd9b1680ae 470 /**
bogdanm 86:04dd9b1680ae 471 * @}
bogdanm 86:04dd9b1680ae 472 */
bogdanm 86:04dd9b1680ae 473
bogdanm 92:4fc01daae5a5 474 /** @defgroup TIM_Input_Capture_Selection TIM Input Capture Selection
bogdanm 86:04dd9b1680ae 475 * @{
bogdanm 86:04dd9b1680ae 476 */
bogdanm 86:04dd9b1680ae 477
bogdanm 86:04dd9b1680ae 478 #define TIM_ICSELECTION_DIRECTTI (TIM_CCMR1_CC1S_0) /*!< TIM Input 1, 2, 3 or 4 is selected to be
bogdanm 86:04dd9b1680ae 479 connected to IC1, IC2, IC3 or IC4, respectively */
bogdanm 86:04dd9b1680ae 480 #define TIM_ICSELECTION_INDIRECTTI (TIM_CCMR1_CC1S_1) /*!< TIM Input 1, 2, 3 or 4 is selected to be
bogdanm 86:04dd9b1680ae 481 connected to IC2, IC1, IC4 or IC3, respectively */
bogdanm 86:04dd9b1680ae 482 #define TIM_ICSELECTION_TRC (TIM_CCMR1_CC1S) /*!< TIM Input 1, 2, 3 or 4 is selected to be connected to TRC */
bogdanm 86:04dd9b1680ae 483
bogdanm 86:04dd9b1680ae 484 #define IS_TIM_IC_SELECTION(SELECTION) (((SELECTION) == TIM_ICSELECTION_DIRECTTI) || \
bogdanm 86:04dd9b1680ae 485 ((SELECTION) == TIM_ICSELECTION_INDIRECTTI) || \
bogdanm 86:04dd9b1680ae 486 ((SELECTION) == TIM_ICSELECTION_TRC))
bogdanm 86:04dd9b1680ae 487 /**
bogdanm 86:04dd9b1680ae 488 * @}
bogdanm 86:04dd9b1680ae 489 */
bogdanm 86:04dd9b1680ae 490
bogdanm 92:4fc01daae5a5 491 /** @defgroup TIM_Input_Capture_Prescaler TIM Input Capture Prescaler
bogdanm 86:04dd9b1680ae 492 * @{
bogdanm 86:04dd9b1680ae 493 */
bogdanm 86:04dd9b1680ae 494
bogdanm 86:04dd9b1680ae 495 #define TIM_ICPSC_DIV1 ((uint32_t)0x0000) /*!< Capture performed each time an edge is detected on the capture input */
bogdanm 86:04dd9b1680ae 496 #define TIM_ICPSC_DIV2 (TIM_CCMR1_IC1PSC_0) /*!< Capture performed once every 2 events */
bogdanm 86:04dd9b1680ae 497 #define TIM_ICPSC_DIV4 (TIM_CCMR1_IC1PSC_1) /*!< Capture performed once every 4 events */
bogdanm 86:04dd9b1680ae 498 #define TIM_ICPSC_DIV8 (TIM_CCMR1_IC1PSC) /*!< Capture performed once every 8 events */
bogdanm 86:04dd9b1680ae 499
bogdanm 86:04dd9b1680ae 500 #define IS_TIM_IC_PRESCALER(PRESCALER) (((PRESCALER) == TIM_ICPSC_DIV1) || \
bogdanm 86:04dd9b1680ae 501 ((PRESCALER) == TIM_ICPSC_DIV2) || \
bogdanm 86:04dd9b1680ae 502 ((PRESCALER) == TIM_ICPSC_DIV4) || \
bogdanm 86:04dd9b1680ae 503 ((PRESCALER) == TIM_ICPSC_DIV8))
bogdanm 86:04dd9b1680ae 504 /**
bogdanm 86:04dd9b1680ae 505 * @}
bogdanm 86:04dd9b1680ae 506 */
bogdanm 86:04dd9b1680ae 507
bogdanm 92:4fc01daae5a5 508 /** @defgroup TIM_One_Pulse_Mode TIM One Pulse Mode
bogdanm 86:04dd9b1680ae 509 * @{
bogdanm 86:04dd9b1680ae 510 */
bogdanm 86:04dd9b1680ae 511
bogdanm 86:04dd9b1680ae 512 #define TIM_OPMODE_SINGLE (TIM_CR1_OPM)
bogdanm 86:04dd9b1680ae 513 #define TIM_OPMODE_REPETITIVE ((uint32_t)0x0000)
bogdanm 86:04dd9b1680ae 514 #define IS_TIM_OPM_MODE(MODE) (((MODE) == TIM_OPMODE_SINGLE) || \
bogdanm 86:04dd9b1680ae 515 ((MODE) == TIM_OPMODE_REPETITIVE))
bogdanm 86:04dd9b1680ae 516 /**
bogdanm 86:04dd9b1680ae 517 * @}
bogdanm 86:04dd9b1680ae 518 */
bogdanm 92:4fc01daae5a5 519 /** @defgroup TIM_Encoder_Mode TIM Encoder Mode
bogdanm 86:04dd9b1680ae 520 * @{
bogdanm 86:04dd9b1680ae 521 */
bogdanm 86:04dd9b1680ae 522 #define TIM_ENCODERMODE_TI1 (TIM_SMCR_SMS_0)
bogdanm 86:04dd9b1680ae 523 #define TIM_ENCODERMODE_TI2 (TIM_SMCR_SMS_1)
bogdanm 86:04dd9b1680ae 524 #define TIM_ENCODERMODE_TI12 (TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0)
bogdanm 86:04dd9b1680ae 525 #define IS_TIM_ENCODER_MODE(MODE) (((MODE) == TIM_ENCODERMODE_TI1) || \
bogdanm 86:04dd9b1680ae 526 ((MODE) == TIM_ENCODERMODE_TI2) || \
bogdanm 86:04dd9b1680ae 527 ((MODE) == TIM_ENCODERMODE_TI12))
bogdanm 86:04dd9b1680ae 528 /**
bogdanm 86:04dd9b1680ae 529 * @}
bogdanm 86:04dd9b1680ae 530 */
bogdanm 92:4fc01daae5a5 531 /** @defgroup TIM_Interrupt_definition TIM interrupt Definition
bogdanm 86:04dd9b1680ae 532 * @{
bogdanm 86:04dd9b1680ae 533 */
bogdanm 86:04dd9b1680ae 534 #define TIM_IT_UPDATE (TIM_DIER_UIE)
bogdanm 86:04dd9b1680ae 535 #define TIM_IT_CC1 (TIM_DIER_CC1IE)
bogdanm 86:04dd9b1680ae 536 #define TIM_IT_CC2 (TIM_DIER_CC2IE)
bogdanm 86:04dd9b1680ae 537 #define TIM_IT_CC3 (TIM_DIER_CC3IE)
bogdanm 86:04dd9b1680ae 538 #define TIM_IT_CC4 (TIM_DIER_CC4IE)
bogdanm 86:04dd9b1680ae 539 #define TIM_IT_COM (TIM_DIER_COMIE)
bogdanm 86:04dd9b1680ae 540 #define TIM_IT_TRIGGER (TIM_DIER_TIE)
bogdanm 86:04dd9b1680ae 541 #define TIM_IT_BREAK (TIM_DIER_BIE)
bogdanm 86:04dd9b1680ae 542
bogdanm 86:04dd9b1680ae 543 #define IS_TIM_IT(IT) ((((IT) & 0xFFFFFF00) == 0x00000000) && ((IT) != 0x00000000))
bogdanm 86:04dd9b1680ae 544
bogdanm 86:04dd9b1680ae 545 #define IS_TIM_GET_IT(IT) (((IT) == TIM_IT_UPDATE) || \
bogdanm 86:04dd9b1680ae 546 ((IT) == TIM_IT_CC1) || \
bogdanm 86:04dd9b1680ae 547 ((IT) == TIM_IT_CC2) || \
bogdanm 86:04dd9b1680ae 548 ((IT) == TIM_IT_CC3) || \
bogdanm 86:04dd9b1680ae 549 ((IT) == TIM_IT_CC4) || \
bogdanm 86:04dd9b1680ae 550 ((IT) == TIM_IT_COM) || \
bogdanm 86:04dd9b1680ae 551 ((IT) == TIM_IT_TRIGGER) || \
bogdanm 86:04dd9b1680ae 552 ((IT) == TIM_IT_BREAK))
bogdanm 86:04dd9b1680ae 553 /**
bogdanm 86:04dd9b1680ae 554 * @}
bogdanm 86:04dd9b1680ae 555 */
bogdanm 86:04dd9b1680ae 556 #define TIM_COMMUTATION_TRGI (TIM_CR2_CCUS)
bogdanm 86:04dd9b1680ae 557 #define TIM_COMMUTATION_SOFTWARE ((uint32_t)0x0000)
bogdanm 86:04dd9b1680ae 558
bogdanm 92:4fc01daae5a5 559 /** @defgroup TIM_DMA_sources TIM DMA Sources
bogdanm 86:04dd9b1680ae 560 * @{
bogdanm 86:04dd9b1680ae 561 */
bogdanm 86:04dd9b1680ae 562
bogdanm 86:04dd9b1680ae 563 #define TIM_DMA_UPDATE (TIM_DIER_UDE)
bogdanm 86:04dd9b1680ae 564 #define TIM_DMA_CC1 (TIM_DIER_CC1DE)
bogdanm 86:04dd9b1680ae 565 #define TIM_DMA_CC2 (TIM_DIER_CC2DE)
bogdanm 86:04dd9b1680ae 566 #define TIM_DMA_CC3 (TIM_DIER_CC3DE)
bogdanm 86:04dd9b1680ae 567 #define TIM_DMA_CC4 (TIM_DIER_CC4DE)
bogdanm 86:04dd9b1680ae 568 #define TIM_DMA_COM (TIM_DIER_COMDE)
bogdanm 86:04dd9b1680ae 569 #define TIM_DMA_TRIGGER (TIM_DIER_TDE)
bogdanm 86:04dd9b1680ae 570 #define IS_TIM_DMA_SOURCE(SOURCE) ((((SOURCE) & 0xFFFF80FF) == 0x00000000) && ((SOURCE) != 0x00000000))
bogdanm 86:04dd9b1680ae 571
bogdanm 86:04dd9b1680ae 572 /**
bogdanm 86:04dd9b1680ae 573 * @}
bogdanm 86:04dd9b1680ae 574 */
bogdanm 86:04dd9b1680ae 575
bogdanm 92:4fc01daae5a5 576 /** @defgroup TIM_Flag_definition TIM Flag Definition
bogdanm 86:04dd9b1680ae 577 * @{
bogdanm 86:04dd9b1680ae 578 */
bogdanm 86:04dd9b1680ae 579
bogdanm 86:04dd9b1680ae 580 #define TIM_FLAG_UPDATE (TIM_SR_UIF)
bogdanm 86:04dd9b1680ae 581 #define TIM_FLAG_CC1 (TIM_SR_CC1IF)
bogdanm 86:04dd9b1680ae 582 #define TIM_FLAG_CC2 (TIM_SR_CC2IF)
bogdanm 86:04dd9b1680ae 583 #define TIM_FLAG_CC3 (TIM_SR_CC3IF)
bogdanm 86:04dd9b1680ae 584 #define TIM_FLAG_CC4 (TIM_SR_CC4IF)
bogdanm 86:04dd9b1680ae 585 #define TIM_FLAG_COM (TIM_SR_COMIF)
bogdanm 86:04dd9b1680ae 586 #define TIM_FLAG_TRIGGER (TIM_SR_TIF)
bogdanm 86:04dd9b1680ae 587 #define TIM_FLAG_BREAK (TIM_SR_BIF)
bogdanm 86:04dd9b1680ae 588 #define TIM_FLAG_CC1OF (TIM_SR_CC1OF)
bogdanm 86:04dd9b1680ae 589 #define TIM_FLAG_CC2OF (TIM_SR_CC2OF)
bogdanm 86:04dd9b1680ae 590 #define TIM_FLAG_CC3OF (TIM_SR_CC3OF)
bogdanm 86:04dd9b1680ae 591 #define TIM_FLAG_CC4OF (TIM_SR_CC4OF)
bogdanm 86:04dd9b1680ae 592
bogdanm 86:04dd9b1680ae 593 #define IS_TIM_FLAG(FLAG) (((FLAG) == TIM_FLAG_UPDATE) || \
bogdanm 86:04dd9b1680ae 594 ((FLAG) == TIM_FLAG_CC1) || \
bogdanm 86:04dd9b1680ae 595 ((FLAG) == TIM_FLAG_CC2) || \
bogdanm 86:04dd9b1680ae 596 ((FLAG) == TIM_FLAG_CC3) || \
bogdanm 86:04dd9b1680ae 597 ((FLAG) == TIM_FLAG_CC4) || \
bogdanm 86:04dd9b1680ae 598 ((FLAG) == TIM_FLAG_COM) || \
bogdanm 86:04dd9b1680ae 599 ((FLAG) == TIM_FLAG_TRIGGER) || \
bogdanm 86:04dd9b1680ae 600 ((FLAG) == TIM_FLAG_BREAK) || \
bogdanm 86:04dd9b1680ae 601 ((FLAG) == TIM_FLAG_CC1OF) || \
bogdanm 86:04dd9b1680ae 602 ((FLAG) == TIM_FLAG_CC2OF) || \
bogdanm 86:04dd9b1680ae 603 ((FLAG) == TIM_FLAG_CC3OF) || \
bogdanm 86:04dd9b1680ae 604 ((FLAG) == TIM_FLAG_CC4OF))
bogdanm 86:04dd9b1680ae 605 /**
bogdanm 86:04dd9b1680ae 606 * @}
bogdanm 86:04dd9b1680ae 607 */
bogdanm 86:04dd9b1680ae 608
bogdanm 92:4fc01daae5a5 609 /** @defgroup TIM_Clock_Source TIM Clock Source
bogdanm 86:04dd9b1680ae 610 * @{
bogdanm 86:04dd9b1680ae 611 */
bogdanm 86:04dd9b1680ae 612 #define TIM_CLOCKSOURCE_ETRMODE2 (TIM_SMCR_ETPS_1)
bogdanm 86:04dd9b1680ae 613 #define TIM_CLOCKSOURCE_INTERNAL (TIM_SMCR_ETPS_0)
bogdanm 86:04dd9b1680ae 614 #define TIM_CLOCKSOURCE_ITR0 ((uint32_t)0x0000)
bogdanm 86:04dd9b1680ae 615 #define TIM_CLOCKSOURCE_ITR1 (TIM_SMCR_TS_0)
bogdanm 86:04dd9b1680ae 616 #define TIM_CLOCKSOURCE_ITR2 (TIM_SMCR_TS_1)
bogdanm 86:04dd9b1680ae 617 #define TIM_CLOCKSOURCE_ITR3 (TIM_SMCR_TS_0 | TIM_SMCR_TS_1)
bogdanm 86:04dd9b1680ae 618 #define TIM_CLOCKSOURCE_TI1ED (TIM_SMCR_TS_2)
bogdanm 86:04dd9b1680ae 619 #define TIM_CLOCKSOURCE_TI1 (TIM_SMCR_TS_0 | TIM_SMCR_TS_2)
bogdanm 86:04dd9b1680ae 620 #define TIM_CLOCKSOURCE_TI2 (TIM_SMCR_TS_1 | TIM_SMCR_TS_2)
bogdanm 86:04dd9b1680ae 621 #define TIM_CLOCKSOURCE_ETRMODE1 (TIM_SMCR_TS)
bogdanm 86:04dd9b1680ae 622
bogdanm 86:04dd9b1680ae 623 #define IS_TIM_CLOCKSOURCE(CLOCK) (((CLOCK) == TIM_CLOCKSOURCE_INTERNAL) || \
bogdanm 86:04dd9b1680ae 624 ((CLOCK) == TIM_CLOCKSOURCE_ETRMODE2) || \
bogdanm 86:04dd9b1680ae 625 ((CLOCK) == TIM_CLOCKSOURCE_ITR0) || \
bogdanm 86:04dd9b1680ae 626 ((CLOCK) == TIM_CLOCKSOURCE_ITR1) || \
bogdanm 86:04dd9b1680ae 627 ((CLOCK) == TIM_CLOCKSOURCE_ITR2) || \
bogdanm 86:04dd9b1680ae 628 ((CLOCK) == TIM_CLOCKSOURCE_ITR3) || \
bogdanm 86:04dd9b1680ae 629 ((CLOCK) == TIM_CLOCKSOURCE_TI1ED) || \
bogdanm 86:04dd9b1680ae 630 ((CLOCK) == TIM_CLOCKSOURCE_TI1) || \
bogdanm 86:04dd9b1680ae 631 ((CLOCK) == TIM_CLOCKSOURCE_TI2) || \
bogdanm 86:04dd9b1680ae 632 ((CLOCK) == TIM_CLOCKSOURCE_ETRMODE1))
bogdanm 86:04dd9b1680ae 633 /**
bogdanm 86:04dd9b1680ae 634 * @}
bogdanm 86:04dd9b1680ae 635 */
bogdanm 86:04dd9b1680ae 636
bogdanm 92:4fc01daae5a5 637 /** @defgroup TIM_Clock_Polarity TIM Clock Polarity
bogdanm 86:04dd9b1680ae 638 * @{
bogdanm 86:04dd9b1680ae 639 */
bogdanm 86:04dd9b1680ae 640 #define TIM_CLOCKPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED /*!< Polarity for ETRx clock sources */
bogdanm 86:04dd9b1680ae 641 #define TIM_CLOCKPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED /*!< Polarity for ETRx clock sources */
bogdanm 86:04dd9b1680ae 642 #define TIM_CLOCKPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING /*!< Polarity for TIx clock sources */
bogdanm 86:04dd9b1680ae 643 #define TIM_CLOCKPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING /*!< Polarity for TIx clock sources */
bogdanm 86:04dd9b1680ae 644 #define TIM_CLOCKPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE /*!< Polarity for TIx clock sources */
bogdanm 86:04dd9b1680ae 645
bogdanm 86:04dd9b1680ae 646 #define IS_TIM_CLOCKPOLARITY(POLARITY) (((POLARITY) == TIM_CLOCKPOLARITY_INVERTED) || \
bogdanm 86:04dd9b1680ae 647 ((POLARITY) == TIM_CLOCKPOLARITY_NONINVERTED) || \
bogdanm 86:04dd9b1680ae 648 ((POLARITY) == TIM_CLOCKPOLARITY_RISING) || \
bogdanm 86:04dd9b1680ae 649 ((POLARITY) == TIM_CLOCKPOLARITY_FALLING) || \
bogdanm 86:04dd9b1680ae 650 ((POLARITY) == TIM_CLOCKPOLARITY_BOTHEDGE))
bogdanm 86:04dd9b1680ae 651 /**
bogdanm 86:04dd9b1680ae 652 * @}
bogdanm 86:04dd9b1680ae 653 */
bogdanm 92:4fc01daae5a5 654 /** @defgroup TIM_Clock_Prescaler TIM Clock Prescaler
bogdanm 86:04dd9b1680ae 655 * @{
bogdanm 86:04dd9b1680ae 656 */
bogdanm 86:04dd9b1680ae 657 #define TIM_CLOCKPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1 /*!< No prescaler is used */
bogdanm 86:04dd9b1680ae 658 #define TIM_CLOCKPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2 /*!< Prescaler for External ETR Clock: Capture performed once every 2 events. */
bogdanm 86:04dd9b1680ae 659 #define TIM_CLOCKPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4 /*!< Prescaler for External ETR Clock: Capture performed once every 4 events. */
bogdanm 86:04dd9b1680ae 660 #define TIM_CLOCKPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8 /*!< Prescaler for External ETR Clock: Capture performed once every 8 events. */
bogdanm 86:04dd9b1680ae 661
bogdanm 86:04dd9b1680ae 662 #define IS_TIM_CLOCKPRESCALER(PRESCALER) (((PRESCALER) == TIM_CLOCKPRESCALER_DIV1) || \
bogdanm 86:04dd9b1680ae 663 ((PRESCALER) == TIM_CLOCKPRESCALER_DIV2) || \
bogdanm 86:04dd9b1680ae 664 ((PRESCALER) == TIM_CLOCKPRESCALER_DIV4) || \
bogdanm 86:04dd9b1680ae 665 ((PRESCALER) == TIM_CLOCKPRESCALER_DIV8))
bogdanm 86:04dd9b1680ae 666 /**
bogdanm 86:04dd9b1680ae 667 * @}
bogdanm 86:04dd9b1680ae 668 */
bogdanm 92:4fc01daae5a5 669 /** @defgroup TIM_Clock_Filter TIM Clock Filter
bogdanm 86:04dd9b1680ae 670 * @{
bogdanm 86:04dd9b1680ae 671 */
bogdanm 86:04dd9b1680ae 672
bogdanm 86:04dd9b1680ae 673 #define IS_TIM_CLOCKFILTER(ICFILTER) ((ICFILTER) <= 0xF)
bogdanm 86:04dd9b1680ae 674 /**
bogdanm 86:04dd9b1680ae 675 * @}
bogdanm 86:04dd9b1680ae 676 */
bogdanm 86:04dd9b1680ae 677
bogdanm 92:4fc01daae5a5 678 /** @defgroup TIM_ClearInput_Polarity TIM Clear Input Polarity
bogdanm 86:04dd9b1680ae 679 * @{
bogdanm 86:04dd9b1680ae 680 */
bogdanm 86:04dd9b1680ae 681 #define TIM_CLEARINPUTPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED /*!< Polarity for ETRx pin */
bogdanm 86:04dd9b1680ae 682 #define TIM_CLEARINPUTPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED /*!< Polarity for ETRx pin */
bogdanm 86:04dd9b1680ae 683
bogdanm 86:04dd9b1680ae 684
bogdanm 86:04dd9b1680ae 685 #define IS_TIM_CLEARINPUT_POLARITY(POLARITY) (((POLARITY) == TIM_CLEARINPUTPOLARITY_INVERTED) || \
bogdanm 86:04dd9b1680ae 686 ((POLARITY) == TIM_CLEARINPUTPOLARITY_NONINVERTED))
bogdanm 86:04dd9b1680ae 687 /**
bogdanm 86:04dd9b1680ae 688 * @}
bogdanm 86:04dd9b1680ae 689 */
bogdanm 86:04dd9b1680ae 690
bogdanm 92:4fc01daae5a5 691 /** @defgroup TIM_ClearInput_Prescaler TIM Clear Input Prescaler
bogdanm 86:04dd9b1680ae 692 * @{
bogdanm 86:04dd9b1680ae 693 */
bogdanm 86:04dd9b1680ae 694 #define TIM_CLEARINPUTPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1 /*!< No prescaler is used */
bogdanm 86:04dd9b1680ae 695 #define TIM_CLEARINPUTPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2 /*!< Prescaler for External ETR pin: Capture performed once every 2 events. */
bogdanm 86:04dd9b1680ae 696 #define TIM_CLEARINPUTPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4 /*!< Prescaler for External ETR pin: Capture performed once every 4 events. */
bogdanm 86:04dd9b1680ae 697 #define TIM_CLEARINPUTPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8 /*!< Prescaler for External ETR pin: Capture performed once every 8 events. */
bogdanm 86:04dd9b1680ae 698 #define IS_TIM_CLEARINPUT_PRESCALER(PRESCALER) (((PRESCALER) == TIM_CLEARINPUTPRESCALER_DIV1) || \
bogdanm 86:04dd9b1680ae 699 ((PRESCALER) == TIM_CLEARINPUTPRESCALER_DIV2) || \
bogdanm 86:04dd9b1680ae 700 ((PRESCALER) == TIM_CLEARINPUTPRESCALER_DIV4) || \
bogdanm 86:04dd9b1680ae 701 ((PRESCALER) == TIM_CLEARINPUTPRESCALER_DIV8))
bogdanm 86:04dd9b1680ae 702 /**
bogdanm 86:04dd9b1680ae 703 * @}
bogdanm 86:04dd9b1680ae 704 */
bogdanm 86:04dd9b1680ae 705
bogdanm 92:4fc01daae5a5 706 /** @defgroup TIM_ClearInput_Filter TIM Clear Input Filter
bogdanm 86:04dd9b1680ae 707 * @{
bogdanm 86:04dd9b1680ae 708 */
bogdanm 86:04dd9b1680ae 709
bogdanm 86:04dd9b1680ae 710 #define IS_TIM_CLEARINPUT_FILTER(ICFILTER) ((ICFILTER) <= 0xF)
bogdanm 86:04dd9b1680ae 711 /**
bogdanm 86:04dd9b1680ae 712 * @}
bogdanm 86:04dd9b1680ae 713 */
bogdanm 86:04dd9b1680ae 714
bogdanm 92:4fc01daae5a5 715 /** @defgroup TIM_OSSR_Off_State_Selection_for_Run_mode_state TIM Off-state Selection for Run Mode
bogdanm 86:04dd9b1680ae 716 * @{
bogdanm 86:04dd9b1680ae 717 */
bogdanm 86:04dd9b1680ae 718 #define TIM_OSSR_ENABLE (TIM_BDTR_OSSR)
bogdanm 86:04dd9b1680ae 719 #define TIM_OSSR_DISABLE ((uint32_t)0x0000)
bogdanm 86:04dd9b1680ae 720
bogdanm 86:04dd9b1680ae 721 #define IS_TIM_OSSR_STATE(STATE) (((STATE) == TIM_OSSR_ENABLE) || \
bogdanm 86:04dd9b1680ae 722 ((STATE) == TIM_OSSR_DISABLE))
bogdanm 86:04dd9b1680ae 723 /**
bogdanm 86:04dd9b1680ae 724 * @}
bogdanm 86:04dd9b1680ae 725 */
bogdanm 86:04dd9b1680ae 726
bogdanm 92:4fc01daae5a5 727 /** @defgroup TIM_OSSI_Off_State_Selection_for_Idle_mode_state TIM Off-state Selection for Idle Mode
bogdanm 86:04dd9b1680ae 728 * @{
bogdanm 86:04dd9b1680ae 729 */
bogdanm 86:04dd9b1680ae 730 #define TIM_OSSI_ENABLE (TIM_BDTR_OSSI)
bogdanm 86:04dd9b1680ae 731 #define TIM_OSSI_DISABLE ((uint32_t)0x0000)
bogdanm 86:04dd9b1680ae 732
bogdanm 86:04dd9b1680ae 733 #define IS_TIM_OSSI_STATE(STATE) (((STATE) == TIM_OSSI_ENABLE) || \
bogdanm 86:04dd9b1680ae 734 ((STATE) == TIM_OSSI_DISABLE))
bogdanm 86:04dd9b1680ae 735 /**
bogdanm 86:04dd9b1680ae 736 * @}
bogdanm 86:04dd9b1680ae 737 */
bogdanm 92:4fc01daae5a5 738 /** @defgroup TIM_Lock_level TIM Lock Configuration
bogdanm 86:04dd9b1680ae 739 * @{
bogdanm 86:04dd9b1680ae 740 */
bogdanm 86:04dd9b1680ae 741 #define TIM_LOCKLEVEL_OFF ((uint32_t)0x0000)
bogdanm 86:04dd9b1680ae 742 #define TIM_LOCKLEVEL_1 (TIM_BDTR_LOCK_0)
bogdanm 86:04dd9b1680ae 743 #define TIM_LOCKLEVEL_2 (TIM_BDTR_LOCK_1)
bogdanm 86:04dd9b1680ae 744 #define TIM_LOCKLEVEL_3 (TIM_BDTR_LOCK)
bogdanm 86:04dd9b1680ae 745
bogdanm 86:04dd9b1680ae 746 #define IS_TIM_LOCK_LEVEL(LEVEL) (((LEVEL) == TIM_LOCKLEVEL_OFF) || \
bogdanm 86:04dd9b1680ae 747 ((LEVEL) == TIM_LOCKLEVEL_1) || \
bogdanm 86:04dd9b1680ae 748 ((LEVEL) == TIM_LOCKLEVEL_2) || \
bogdanm 86:04dd9b1680ae 749 ((LEVEL) == TIM_LOCKLEVEL_3))
bogdanm 86:04dd9b1680ae 750 /**
bogdanm 86:04dd9b1680ae 751 * @}
bogdanm 86:04dd9b1680ae 752 */
bogdanm 92:4fc01daae5a5 753 /** @defgroup TIM_Break_Input_enable_disable TIM Break Input Enable
bogdanm 86:04dd9b1680ae 754 * @{
bogdanm 86:04dd9b1680ae 755 */
bogdanm 86:04dd9b1680ae 756 #define TIM_BREAK_ENABLE (TIM_BDTR_BKE)
bogdanm 86:04dd9b1680ae 757 #define TIM_BREAK_DISABLE ((uint32_t)0x0000)
bogdanm 86:04dd9b1680ae 758
bogdanm 86:04dd9b1680ae 759 #define IS_TIM_BREAK_STATE(STATE) (((STATE) == TIM_BREAK_ENABLE) || \
bogdanm 86:04dd9b1680ae 760 ((STATE) == TIM_BREAK_DISABLE))
bogdanm 86:04dd9b1680ae 761 /**
bogdanm 86:04dd9b1680ae 762 * @}
bogdanm 86:04dd9b1680ae 763 */
bogdanm 92:4fc01daae5a5 764 /** @defgroup TIM_Break_Polarity TIM Break Input Polarity
bogdanm 86:04dd9b1680ae 765 * @{
bogdanm 86:04dd9b1680ae 766 */
bogdanm 86:04dd9b1680ae 767 #define TIM_BREAKPOLARITY_LOW ((uint32_t)0x0000)
bogdanm 86:04dd9b1680ae 768 #define TIM_BREAKPOLARITY_HIGH (TIM_BDTR_BKP)
bogdanm 86:04dd9b1680ae 769
bogdanm 86:04dd9b1680ae 770 #define IS_TIM_BREAK_POLARITY(POLARITY) (((POLARITY) == TIM_BREAKPOLARITY_LOW) || \
bogdanm 86:04dd9b1680ae 771 ((POLARITY) == TIM_BREAKPOLARITY_HIGH))
bogdanm 86:04dd9b1680ae 772 /**
bogdanm 86:04dd9b1680ae 773 * @}
bogdanm 86:04dd9b1680ae 774 */
bogdanm 92:4fc01daae5a5 775 /** @defgroup TIM_AOE_Bit_Set_Reset TIM Automatic Output Enable
bogdanm 86:04dd9b1680ae 776 * @{
bogdanm 86:04dd9b1680ae 777 */
bogdanm 86:04dd9b1680ae 778 #define TIM_AUTOMATICOUTPUT_ENABLE (TIM_BDTR_AOE)
bogdanm 86:04dd9b1680ae 779 #define TIM_AUTOMATICOUTPUT_DISABLE ((uint32_t)0x0000)
bogdanm 86:04dd9b1680ae 780
bogdanm 86:04dd9b1680ae 781 #define IS_TIM_AUTOMATIC_OUTPUT_STATE(STATE) (((STATE) == TIM_AUTOMATICOUTPUT_ENABLE) || \
bogdanm 86:04dd9b1680ae 782 ((STATE) == TIM_AUTOMATICOUTPUT_DISABLE))
bogdanm 86:04dd9b1680ae 783 /**
bogdanm 86:04dd9b1680ae 784 * @}
bogdanm 86:04dd9b1680ae 785 */
bogdanm 86:04dd9b1680ae 786
bogdanm 92:4fc01daae5a5 787 /** @defgroup TIM_Master_Mode_Selection TIM Master Mode Selection
bogdanm 86:04dd9b1680ae 788 * @{
bogdanm 86:04dd9b1680ae 789 */
bogdanm 86:04dd9b1680ae 790 #define TIM_TRGO_RESET ((uint32_t)0x0000)
bogdanm 86:04dd9b1680ae 791 #define TIM_TRGO_ENABLE (TIM_CR2_MMS_0)
bogdanm 86:04dd9b1680ae 792 #define TIM_TRGO_UPDATE (TIM_CR2_MMS_1)
bogdanm 86:04dd9b1680ae 793 #define TIM_TRGO_OC1 ((TIM_CR2_MMS_1 | TIM_CR2_MMS_0))
bogdanm 86:04dd9b1680ae 794 #define TIM_TRGO_OC1REF (TIM_CR2_MMS_2)
bogdanm 86:04dd9b1680ae 795 #define TIM_TRGO_OC2REF ((TIM_CR2_MMS_2 | TIM_CR2_MMS_0))
bogdanm 86:04dd9b1680ae 796 #define TIM_TRGO_OC3REF ((TIM_CR2_MMS_2 | TIM_CR2_MMS_1))
bogdanm 86:04dd9b1680ae 797 #define TIM_TRGO_OC4REF ((TIM_CR2_MMS_2 | TIM_CR2_MMS_1 | TIM_CR2_MMS_0))
bogdanm 86:04dd9b1680ae 798
bogdanm 86:04dd9b1680ae 799 #define IS_TIM_TRGO_SOURCE(SOURCE) (((SOURCE) == TIM_TRGO_RESET) || \
bogdanm 86:04dd9b1680ae 800 ((SOURCE) == TIM_TRGO_ENABLE) || \
bogdanm 86:04dd9b1680ae 801 ((SOURCE) == TIM_TRGO_UPDATE) || \
bogdanm 86:04dd9b1680ae 802 ((SOURCE) == TIM_TRGO_OC1) || \
bogdanm 86:04dd9b1680ae 803 ((SOURCE) == TIM_TRGO_OC1REF) || \
bogdanm 86:04dd9b1680ae 804 ((SOURCE) == TIM_TRGO_OC2REF) || \
bogdanm 86:04dd9b1680ae 805 ((SOURCE) == TIM_TRGO_OC3REF) || \
bogdanm 86:04dd9b1680ae 806 ((SOURCE) == TIM_TRGO_OC4REF))
bogdanm 86:04dd9b1680ae 807
bogdanm 86:04dd9b1680ae 808
bogdanm 86:04dd9b1680ae 809 /**
bogdanm 86:04dd9b1680ae 810 * @}
bogdanm 86:04dd9b1680ae 811 */
bogdanm 92:4fc01daae5a5 812 /** @defgroup TIM_Master_Slave_Mode TIM Master/Slave Mode
bogdanm 86:04dd9b1680ae 813 * @{
bogdanm 86:04dd9b1680ae 814 */
bogdanm 86:04dd9b1680ae 815
bogdanm 86:04dd9b1680ae 816 #define TIM_MASTERSLAVEMODE_ENABLE ((uint32_t)0x0080)
bogdanm 86:04dd9b1680ae 817 #define TIM_MASTERSLAVEMODE_DISABLE ((uint32_t)0x0000)
bogdanm 86:04dd9b1680ae 818 #define IS_TIM_MSM_STATE(STATE) (((STATE) == TIM_MASTERSLAVEMODE_ENABLE) || \
bogdanm 86:04dd9b1680ae 819 ((STATE) == TIM_MASTERSLAVEMODE_DISABLE))
bogdanm 86:04dd9b1680ae 820 /**
bogdanm 86:04dd9b1680ae 821 * @}
bogdanm 86:04dd9b1680ae 822 */
bogdanm 92:4fc01daae5a5 823 /** @defgroup TIM_Trigger_Selection TIM Trigger Selection
bogdanm 86:04dd9b1680ae 824 * @{
bogdanm 86:04dd9b1680ae 825 */
bogdanm 86:04dd9b1680ae 826
bogdanm 86:04dd9b1680ae 827 #define TIM_TS_ITR0 ((uint32_t)0x0000)
bogdanm 86:04dd9b1680ae 828 #define TIM_TS_ITR1 ((uint32_t)0x0010)
bogdanm 86:04dd9b1680ae 829 #define TIM_TS_ITR2 ((uint32_t)0x0020)
bogdanm 86:04dd9b1680ae 830 #define TIM_TS_ITR3 ((uint32_t)0x0030)
bogdanm 86:04dd9b1680ae 831 #define TIM_TS_TI1F_ED ((uint32_t)0x0040)
bogdanm 86:04dd9b1680ae 832 #define TIM_TS_TI1FP1 ((uint32_t)0x0050)
bogdanm 86:04dd9b1680ae 833 #define TIM_TS_TI2FP2 ((uint32_t)0x0060)
bogdanm 86:04dd9b1680ae 834 #define TIM_TS_ETRF ((uint32_t)0x0070)
bogdanm 86:04dd9b1680ae 835 #define TIM_TS_NONE ((uint32_t)0xFFFF)
bogdanm 86:04dd9b1680ae 836 #define IS_TIM_TRIGGER_SELECTION(SELECTION) (((SELECTION) == TIM_TS_ITR0) || \
bogdanm 86:04dd9b1680ae 837 ((SELECTION) == TIM_TS_ITR1) || \
bogdanm 86:04dd9b1680ae 838 ((SELECTION) == TIM_TS_ITR2) || \
bogdanm 86:04dd9b1680ae 839 ((SELECTION) == TIM_TS_ITR3) || \
bogdanm 86:04dd9b1680ae 840 ((SELECTION) == TIM_TS_TI1F_ED) || \
bogdanm 86:04dd9b1680ae 841 ((SELECTION) == TIM_TS_TI1FP1) || \
bogdanm 86:04dd9b1680ae 842 ((SELECTION) == TIM_TS_TI2FP2) || \
bogdanm 86:04dd9b1680ae 843 ((SELECTION) == TIM_TS_ETRF))
bogdanm 86:04dd9b1680ae 844 #define IS_TIM_INTERNAL_TRIGGER_SELECTION(SELECTION) (((SELECTION) == TIM_TS_ITR0) || \
bogdanm 86:04dd9b1680ae 845 ((SELECTION) == TIM_TS_ITR1) || \
bogdanm 86:04dd9b1680ae 846 ((SELECTION) == TIM_TS_ITR2) || \
bogdanm 86:04dd9b1680ae 847 ((SELECTION) == TIM_TS_ITR3))
bogdanm 86:04dd9b1680ae 848 #define IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION(SELECTION) (((SELECTION) == TIM_TS_ITR0) || \
bogdanm 86:04dd9b1680ae 849 ((SELECTION) == TIM_TS_ITR1) || \
bogdanm 86:04dd9b1680ae 850 ((SELECTION) == TIM_TS_ITR2) || \
bogdanm 86:04dd9b1680ae 851 ((SELECTION) == TIM_TS_ITR3) || \
bogdanm 86:04dd9b1680ae 852 ((SELECTION) == TIM_TS_NONE))
bogdanm 86:04dd9b1680ae 853 /**
bogdanm 86:04dd9b1680ae 854 * @}
bogdanm 86:04dd9b1680ae 855 */
bogdanm 86:04dd9b1680ae 856
bogdanm 92:4fc01daae5a5 857 /** @defgroup TIM_Trigger_Polarity TIM Trigger Polarity
bogdanm 86:04dd9b1680ae 858 * @{
bogdanm 86:04dd9b1680ae 859 */
bogdanm 86:04dd9b1680ae 860 #define TIM_TRIGGERPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED /*!< Polarity for ETRx trigger sources */
bogdanm 86:04dd9b1680ae 861 #define TIM_TRIGGERPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED /*!< Polarity for ETRx trigger sources */
bogdanm 86:04dd9b1680ae 862 #define TIM_TRIGGERPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING /*!< Polarity for TIxFPx or TI1_ED trigger sources */
bogdanm 86:04dd9b1680ae 863 #define TIM_TRIGGERPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING /*!< Polarity for TIxFPx or TI1_ED trigger sources */
bogdanm 86:04dd9b1680ae 864 #define TIM_TRIGGERPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE /*!< Polarity for TIxFPx or TI1_ED trigger sources */
bogdanm 86:04dd9b1680ae 865
bogdanm 86:04dd9b1680ae 866 #define IS_TIM_TRIGGERPOLARITY(POLARITY) (((POLARITY) == TIM_TRIGGERPOLARITY_INVERTED ) || \
bogdanm 86:04dd9b1680ae 867 ((POLARITY) == TIM_TRIGGERPOLARITY_NONINVERTED) || \
bogdanm 86:04dd9b1680ae 868 ((POLARITY) == TIM_TRIGGERPOLARITY_RISING ) || \
bogdanm 86:04dd9b1680ae 869 ((POLARITY) == TIM_TRIGGERPOLARITY_FALLING ) || \
bogdanm 86:04dd9b1680ae 870 ((POLARITY) == TIM_TRIGGERPOLARITY_BOTHEDGE ))
bogdanm 86:04dd9b1680ae 871 /**
bogdanm 86:04dd9b1680ae 872 * @}
bogdanm 86:04dd9b1680ae 873 */
bogdanm 86:04dd9b1680ae 874
bogdanm 92:4fc01daae5a5 875 /** @defgroup TIM_Trigger_Prescaler TIM Trigger Prescaler
bogdanm 86:04dd9b1680ae 876 * @{
bogdanm 86:04dd9b1680ae 877 */
bogdanm 86:04dd9b1680ae 878 #define TIM_TRIGGERPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1 /*!< No prescaler is used */
bogdanm 86:04dd9b1680ae 879 #define TIM_TRIGGERPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2 /*!< Prescaler for External ETR Trigger: Capture performed once every 2 events. */
bogdanm 86:04dd9b1680ae 880 #define TIM_TRIGGERPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4 /*!< Prescaler for External ETR Trigger: Capture performed once every 4 events. */
bogdanm 86:04dd9b1680ae 881 #define TIM_TRIGGERPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8 /*!< Prescaler for External ETR Trigger: Capture performed once every 8 events. */
bogdanm 86:04dd9b1680ae 882
bogdanm 86:04dd9b1680ae 883 #define IS_TIM_TRIGGERPRESCALER(PRESCALER) (((PRESCALER) == TIM_TRIGGERPRESCALER_DIV1) || \
bogdanm 86:04dd9b1680ae 884 ((PRESCALER) == TIM_TRIGGERPRESCALER_DIV2) || \
bogdanm 86:04dd9b1680ae 885 ((PRESCALER) == TIM_TRIGGERPRESCALER_DIV4) || \
bogdanm 86:04dd9b1680ae 886 ((PRESCALER) == TIM_TRIGGERPRESCALER_DIV8))
bogdanm 86:04dd9b1680ae 887 /**
bogdanm 86:04dd9b1680ae 888 * @}
bogdanm 86:04dd9b1680ae 889 */
bogdanm 86:04dd9b1680ae 890
bogdanm 92:4fc01daae5a5 891 /** @defgroup TIM_Trigger_Filter TIM Trigger Filter
bogdanm 86:04dd9b1680ae 892 * @{
bogdanm 86:04dd9b1680ae 893 */
bogdanm 86:04dd9b1680ae 894
bogdanm 86:04dd9b1680ae 895 #define IS_TIM_TRIGGERFILTER(ICFILTER) ((ICFILTER) <= 0xF)
bogdanm 86:04dd9b1680ae 896 /**
bogdanm 86:04dd9b1680ae 897 * @}
bogdanm 86:04dd9b1680ae 898 */
bogdanm 86:04dd9b1680ae 899
bogdanm 92:4fc01daae5a5 900 /** @defgroup TIM_TI1_Selection TIM TI1 Input Selection
bogdanm 86:04dd9b1680ae 901 * @{
bogdanm 86:04dd9b1680ae 902 */
bogdanm 86:04dd9b1680ae 903
bogdanm 86:04dd9b1680ae 904 #define TIM_TI1SELECTION_CH1 ((uint32_t)0x0000)
bogdanm 86:04dd9b1680ae 905 #define TIM_TI1SELECTION_XORCOMBINATION (TIM_CR2_TI1S)
bogdanm 86:04dd9b1680ae 906
bogdanm 86:04dd9b1680ae 907 #define IS_TIM_TI1SELECTION(TI1SELECTION) (((TI1SELECTION) == TIM_TI1SELECTION_CH1) || \
bogdanm 86:04dd9b1680ae 908 ((TI1SELECTION) == TIM_TI1SELECTION_XORCOMBINATION))
bogdanm 86:04dd9b1680ae 909
bogdanm 86:04dd9b1680ae 910 /**
bogdanm 86:04dd9b1680ae 911 * @}
bogdanm 86:04dd9b1680ae 912 */
bogdanm 86:04dd9b1680ae 913
bogdanm 92:4fc01daae5a5 914 /** @defgroup TIM_DMA_Burst_Length TIM DMA Burst Length
bogdanm 86:04dd9b1680ae 915 * @{
bogdanm 86:04dd9b1680ae 916 */
bogdanm 86:04dd9b1680ae 917
bogdanm 86:04dd9b1680ae 918 #define TIM_DMABurstLength_1Transfer (0x00000000)
bogdanm 86:04dd9b1680ae 919 #define TIM_DMABurstLength_2Transfers (0x00000100)
bogdanm 86:04dd9b1680ae 920 #define TIM_DMABurstLength_3Transfers (0x00000200)
bogdanm 86:04dd9b1680ae 921 #define TIM_DMABurstLength_4Transfers (0x00000300)
bogdanm 86:04dd9b1680ae 922 #define TIM_DMABurstLength_5Transfers (0x00000400)
bogdanm 86:04dd9b1680ae 923 #define TIM_DMABurstLength_6Transfers (0x00000500)
bogdanm 86:04dd9b1680ae 924 #define TIM_DMABurstLength_7Transfers (0x00000600)
bogdanm 86:04dd9b1680ae 925 #define TIM_DMABurstLength_8Transfers (0x00000700)
bogdanm 86:04dd9b1680ae 926 #define TIM_DMABurstLength_9Transfers (0x00000800)
bogdanm 86:04dd9b1680ae 927 #define TIM_DMABurstLength_10Transfers (0x00000900)
bogdanm 86:04dd9b1680ae 928 #define TIM_DMABurstLength_11Transfers (0x00000A00)
bogdanm 86:04dd9b1680ae 929 #define TIM_DMABurstLength_12Transfers (0x00000B00)
bogdanm 86:04dd9b1680ae 930 #define TIM_DMABurstLength_13Transfers (0x00000C00)
bogdanm 86:04dd9b1680ae 931 #define TIM_DMABurstLength_14Transfers (0x00000D00)
bogdanm 86:04dd9b1680ae 932 #define TIM_DMABurstLength_15Transfers (0x00000E00)
bogdanm 86:04dd9b1680ae 933 #define TIM_DMABurstLength_16Transfers (0x00000F00)
bogdanm 86:04dd9b1680ae 934 #define TIM_DMABurstLength_17Transfers (0x00001000)
bogdanm 86:04dd9b1680ae 935 #define TIM_DMABurstLength_18Transfers (0x00001100)
bogdanm 86:04dd9b1680ae 936 #define IS_TIM_DMA_LENGTH(LENGTH) (((LENGTH) == TIM_DMABurstLength_1Transfer) || \
bogdanm 86:04dd9b1680ae 937 ((LENGTH) == TIM_DMABurstLength_2Transfers) || \
bogdanm 86:04dd9b1680ae 938 ((LENGTH) == TIM_DMABurstLength_3Transfers) || \
bogdanm 86:04dd9b1680ae 939 ((LENGTH) == TIM_DMABurstLength_4Transfers) || \
bogdanm 86:04dd9b1680ae 940 ((LENGTH) == TIM_DMABurstLength_5Transfers) || \
bogdanm 86:04dd9b1680ae 941 ((LENGTH) == TIM_DMABurstLength_6Transfers) || \
bogdanm 86:04dd9b1680ae 942 ((LENGTH) == TIM_DMABurstLength_7Transfers) || \
bogdanm 86:04dd9b1680ae 943 ((LENGTH) == TIM_DMABurstLength_8Transfers) || \
bogdanm 86:04dd9b1680ae 944 ((LENGTH) == TIM_DMABurstLength_9Transfers) || \
bogdanm 86:04dd9b1680ae 945 ((LENGTH) == TIM_DMABurstLength_10Transfers) || \
bogdanm 86:04dd9b1680ae 946 ((LENGTH) == TIM_DMABurstLength_11Transfers) || \
bogdanm 86:04dd9b1680ae 947 ((LENGTH) == TIM_DMABurstLength_12Transfers) || \
bogdanm 86:04dd9b1680ae 948 ((LENGTH) == TIM_DMABurstLength_13Transfers) || \
bogdanm 86:04dd9b1680ae 949 ((LENGTH) == TIM_DMABurstLength_14Transfers) || \
bogdanm 86:04dd9b1680ae 950 ((LENGTH) == TIM_DMABurstLength_15Transfers) || \
bogdanm 86:04dd9b1680ae 951 ((LENGTH) == TIM_DMABurstLength_16Transfers) || \
bogdanm 86:04dd9b1680ae 952 ((LENGTH) == TIM_DMABurstLength_17Transfers) || \
bogdanm 86:04dd9b1680ae 953 ((LENGTH) == TIM_DMABurstLength_18Transfers))
bogdanm 86:04dd9b1680ae 954 /**
bogdanm 86:04dd9b1680ae 955 * @}
bogdanm 86:04dd9b1680ae 956 */
bogdanm 86:04dd9b1680ae 957
bogdanm 92:4fc01daae5a5 958 /** @defgroup TIM_Input_Capture_Filer_Value TIM Input Capture Value
bogdanm 86:04dd9b1680ae 959 * @{
bogdanm 86:04dd9b1680ae 960 */
bogdanm 86:04dd9b1680ae 961
bogdanm 86:04dd9b1680ae 962 #define IS_TIM_IC_FILTER(ICFILTER) ((ICFILTER) <= 0xF)
bogdanm 86:04dd9b1680ae 963 /**
bogdanm 86:04dd9b1680ae 964 * @}
bogdanm 86:04dd9b1680ae 965 */
bogdanm 86:04dd9b1680ae 966
bogdanm 92:4fc01daae5a5 967 /** @defgroup DMA_Handle_index TIM DMA Handle Index
bogdanm 86:04dd9b1680ae 968 * @{
bogdanm 86:04dd9b1680ae 969 */
bogdanm 86:04dd9b1680ae 970 #define TIM_DMA_ID_UPDATE ((uint16_t) 0x0) /*!< Index of the DMA handle used for Update DMA requests */
bogdanm 86:04dd9b1680ae 971 #define TIM_DMA_ID_CC1 ((uint16_t) 0x1) /*!< Index of the DMA handle used for Capture/Compare 1 DMA requests */
bogdanm 86:04dd9b1680ae 972 #define TIM_DMA_ID_CC2 ((uint16_t) 0x2) /*!< Index of the DMA handle used for Capture/Compare 2 DMA requests */
bogdanm 86:04dd9b1680ae 973 #define TIM_DMA_ID_CC3 ((uint16_t) 0x3) /*!< Index of the DMA handle used for Capture/Compare 3 DMA requests */
bogdanm 86:04dd9b1680ae 974 #define TIM_DMA_ID_CC4 ((uint16_t) 0x4) /*!< Index of the DMA handle used for Capture/Compare 4 DMA requests */
bogdanm 86:04dd9b1680ae 975 #define TIM_DMA_ID_COMMUTATION ((uint16_t) 0x5) /*!< Index of the DMA handle used for Commutation DMA requests */
bogdanm 86:04dd9b1680ae 976 #define TIM_DMA_ID_TRIGGER ((uint16_t) 0x6) /*!< Index of the DMA handle used for Trigger DMA requests */
bogdanm 86:04dd9b1680ae 977 /**
bogdanm 86:04dd9b1680ae 978 * @}
bogdanm 86:04dd9b1680ae 979 */
bogdanm 86:04dd9b1680ae 980
bogdanm 92:4fc01daae5a5 981 /** @defgroup Channel_CC_State TIM Capture/Compare Channel State
bogdanm 86:04dd9b1680ae 982 * @{
bogdanm 86:04dd9b1680ae 983 */
bogdanm 86:04dd9b1680ae 984 #define TIM_CCx_ENABLE ((uint32_t)0x0001)
bogdanm 86:04dd9b1680ae 985 #define TIM_CCx_DISABLE ((uint32_t)0x0000)
bogdanm 86:04dd9b1680ae 986 #define TIM_CCxN_ENABLE ((uint32_t)0x0004)
bogdanm 86:04dd9b1680ae 987 #define TIM_CCxN_DISABLE ((uint32_t)0x0000)
bogdanm 86:04dd9b1680ae 988 /**
bogdanm 86:04dd9b1680ae 989 * @}
bogdanm 86:04dd9b1680ae 990 */
bogdanm 86:04dd9b1680ae 991
bogdanm 86:04dd9b1680ae 992 /**
bogdanm 86:04dd9b1680ae 993 * @}
bogdanm 86:04dd9b1680ae 994 */
bogdanm 86:04dd9b1680ae 995
bogdanm 86:04dd9b1680ae 996 /* Exported macros -----------------------------------------------------------*/
bogdanm 92:4fc01daae5a5 997 /** @defgroup TIM_Exported_Macros TIM Exported Macros
bogdanm 86:04dd9b1680ae 998 * @{
bogdanm 86:04dd9b1680ae 999 */
bogdanm 86:04dd9b1680ae 1000
bogdanm 86:04dd9b1680ae 1001 /** @brief Reset TIM handle state
bogdanm 86:04dd9b1680ae 1002 * @param __HANDLE__: TIM handle.
bogdanm 86:04dd9b1680ae 1003 * @retval None
bogdanm 86:04dd9b1680ae 1004 */
bogdanm 86:04dd9b1680ae 1005 #define __HAL_TIM_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_TIM_STATE_RESET)
bogdanm 86:04dd9b1680ae 1006
bogdanm 86:04dd9b1680ae 1007 /**
bogdanm 86:04dd9b1680ae 1008 * @brief Enable the TIM peripheral.
bogdanm 86:04dd9b1680ae 1009 * @param __HANDLE__: TIM handle
bogdanm 86:04dd9b1680ae 1010 * @retval None
bogdanm 86:04dd9b1680ae 1011 */
bogdanm 86:04dd9b1680ae 1012 #define __HAL_TIM_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1|=(TIM_CR1_CEN))
bogdanm 86:04dd9b1680ae 1013
bogdanm 86:04dd9b1680ae 1014 /**
bogdanm 86:04dd9b1680ae 1015 * @brief Enable the TIM main Output.
bogdanm 86:04dd9b1680ae 1016 * @param __HANDLE__: TIM handle
bogdanm 86:04dd9b1680ae 1017 * @retval None
bogdanm 86:04dd9b1680ae 1018 */
bogdanm 86:04dd9b1680ae 1019 #define __HAL_TIM_MOE_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->BDTR|=(TIM_BDTR_MOE))
bogdanm 86:04dd9b1680ae 1020
bogdanm 86:04dd9b1680ae 1021 /* The counter of a timer instance is disabled only if all the CCx and CCxN
bogdanm 86:04dd9b1680ae 1022 channels have been disabled */
bogdanm 86:04dd9b1680ae 1023 #define CCER_CCxE_MASK ((uint32_t)(TIM_CCER_CC1E | TIM_CCER_CC2E | TIM_CCER_CC3E | TIM_CCER_CC4E))
bogdanm 86:04dd9b1680ae 1024 #define CCER_CCxNE_MASK ((uint32_t)(TIM_CCER_CC1NE | TIM_CCER_CC2NE | TIM_CCER_CC3NE))
bogdanm 86:04dd9b1680ae 1025
bogdanm 86:04dd9b1680ae 1026 /**
bogdanm 86:04dd9b1680ae 1027 * @brief Disable the TIM peripheral.
bogdanm 86:04dd9b1680ae 1028 * @param __HANDLE__: TIM handle
bogdanm 86:04dd9b1680ae 1029 * @retval None
bogdanm 86:04dd9b1680ae 1030 */
bogdanm 86:04dd9b1680ae 1031 #define __HAL_TIM_DISABLE(__HANDLE__) \
bogdanm 86:04dd9b1680ae 1032 do { \
bogdanm 86:04dd9b1680ae 1033 if (((__HANDLE__)->Instance->CCER & CCER_CCxE_MASK) == 0) \
bogdanm 86:04dd9b1680ae 1034 { \
bogdanm 86:04dd9b1680ae 1035 if(((__HANDLE__)->Instance->CCER & CCER_CCxNE_MASK) == 0) \
bogdanm 86:04dd9b1680ae 1036 { \
bogdanm 86:04dd9b1680ae 1037 (__HANDLE__)->Instance->CR1 &= ~(TIM_CR1_CEN); \
bogdanm 86:04dd9b1680ae 1038 } \
bogdanm 86:04dd9b1680ae 1039 } \
bogdanm 86:04dd9b1680ae 1040 } while(0)
bogdanm 86:04dd9b1680ae 1041 /* The Main Output Enable of a timer instance is disabled only if all the CCx and CCxN
bogdanm 86:04dd9b1680ae 1042 channels have been disabled */
bogdanm 86:04dd9b1680ae 1043 /**
bogdanm 86:04dd9b1680ae 1044 * @brief Disable the TIM main Output.
bogdanm 86:04dd9b1680ae 1045 * @param __HANDLE__: TIM handle
bogdanm 86:04dd9b1680ae 1046 * @retval None
bogdanm 86:04dd9b1680ae 1047 */
bogdanm 86:04dd9b1680ae 1048 #define __HAL_TIM_MOE_DISABLE(__HANDLE__) \
bogdanm 86:04dd9b1680ae 1049 do { \
bogdanm 86:04dd9b1680ae 1050 if (((__HANDLE__)->Instance->CCER & CCER_CCxE_MASK) == 0) \
bogdanm 86:04dd9b1680ae 1051 { \
bogdanm 86:04dd9b1680ae 1052 if(((__HANDLE__)->Instance->CCER & CCER_CCxNE_MASK) == 0) \
bogdanm 86:04dd9b1680ae 1053 { \
bogdanm 86:04dd9b1680ae 1054 (__HANDLE__)->Instance->BDTR &= ~(TIM_BDTR_MOE); \
bogdanm 86:04dd9b1680ae 1055 } \
bogdanm 86:04dd9b1680ae 1056 } \
bogdanm 86:04dd9b1680ae 1057 } while(0)
bogdanm 86:04dd9b1680ae 1058
bogdanm 86:04dd9b1680ae 1059 #define __HAL_TIM_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DIER |= (__INTERRUPT__))
bogdanm 86:04dd9b1680ae 1060 #define __HAL_TIM_ENABLE_DMA(__HANDLE__, __DMA__) ((__HANDLE__)->Instance->DIER |= (__DMA__))
bogdanm 86:04dd9b1680ae 1061 #define __HAL_TIM_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DIER &= ~(__INTERRUPT__))
bogdanm 86:04dd9b1680ae 1062 #define __HAL_TIM_DISABLE_DMA(__HANDLE__, __DMA__) ((__HANDLE__)->Instance->DIER &= ~(__DMA__))
bogdanm 86:04dd9b1680ae 1063 #define __HAL_TIM_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR &(__FLAG__)) == (__FLAG__))
bogdanm 86:04dd9b1680ae 1064 #define __HAL_TIM_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->SR = ~(__FLAG__))
bogdanm 86:04dd9b1680ae 1065
bogdanm 86:04dd9b1680ae 1066 #define __HAL_TIM_GET_ITSTATUS(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->DIER & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
bogdanm 86:04dd9b1680ae 1067 #define __HAL_TIM_CLEAR_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->SR = ~(__INTERRUPT__))
bogdanm 86:04dd9b1680ae 1068
bogdanm 86:04dd9b1680ae 1069 #define __HAL_TIM_DIRECTION_STATUS(__HANDLE__) (((__HANDLE__)->Instance->CR1 &(TIM_CR1_DIR)) == (TIM_CR1_DIR))
bogdanm 86:04dd9b1680ae 1070 #define __HAL_TIM_PRESCALER (__HANDLE__, __PRESC__) ((__HANDLE__)->Instance->PSC = (__PRESC__))
bogdanm 86:04dd9b1680ae 1071
bogdanm 86:04dd9b1680ae 1072 #define __HAL_TIM_SetICPrescalerValue(__HANDLE__, __CHANNEL__, __ICPSC__) \
bogdanm 86:04dd9b1680ae 1073 (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 |= (__ICPSC__)) :\
bogdanm 86:04dd9b1680ae 1074 ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 |= ((__ICPSC__) << 8)) :\
bogdanm 86:04dd9b1680ae 1075 ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 |= (__ICPSC__)) :\
bogdanm 86:04dd9b1680ae 1076 ((__HANDLE__)->Instance->CCMR2 |= ((__ICPSC__) << 8)))
bogdanm 86:04dd9b1680ae 1077
bogdanm 86:04dd9b1680ae 1078 #define __HAL_TIM_ResetICPrescalerValue(__HANDLE__, __CHANNEL__) \
bogdanm 86:04dd9b1680ae 1079 (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 &= (uint16_t)~TIM_CCMR1_IC1PSC) :\
bogdanm 86:04dd9b1680ae 1080 ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 &= (uint16_t)~TIM_CCMR1_IC2PSC) :\
bogdanm 86:04dd9b1680ae 1081 ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 &= (uint16_t)~TIM_CCMR2_IC3PSC) :\
bogdanm 86:04dd9b1680ae 1082 ((__HANDLE__)->Instance->CCMR2 &= (uint16_t)~TIM_CCMR2_IC4PSC))
bogdanm 86:04dd9b1680ae 1083
bogdanm 86:04dd9b1680ae 1084 /**
bogdanm 86:04dd9b1680ae 1085 * @brief Sets the TIM Counter Register value on runtime.
bogdanm 86:04dd9b1680ae 1086 * @param __HANDLE__: TIM handle.
bogdanm 86:04dd9b1680ae 1087 * @param __COUNTER__: specifies the Counter register new value.
bogdanm 86:04dd9b1680ae 1088 * @retval None
bogdanm 86:04dd9b1680ae 1089 */
bogdanm 86:04dd9b1680ae 1090 #define __HAL_TIM_SetCounter(__HANDLE__, __COUNTER__) ((__HANDLE__)->Instance->CNT = (__COUNTER__))
bogdanm 86:04dd9b1680ae 1091
bogdanm 86:04dd9b1680ae 1092 /**
bogdanm 86:04dd9b1680ae 1093 * @brief Gets the TIM Counter Register value on runtime.
bogdanm 86:04dd9b1680ae 1094 * @param __HANDLE__: TIM handle.
bogdanm 86:04dd9b1680ae 1095 * @retval None
bogdanm 86:04dd9b1680ae 1096 */
bogdanm 86:04dd9b1680ae 1097 #define __HAL_TIM_GetCounter(__HANDLE__) \
bogdanm 86:04dd9b1680ae 1098 ((__HANDLE__)->Instance->CNT)
bogdanm 86:04dd9b1680ae 1099
bogdanm 86:04dd9b1680ae 1100 /**
bogdanm 86:04dd9b1680ae 1101 * @brief Sets the TIM Autoreload Register value on runtime without calling
bogdanm 86:04dd9b1680ae 1102 * another time any Init function.
bogdanm 86:04dd9b1680ae 1103 * @param __HANDLE__: TIM handle.
bogdanm 86:04dd9b1680ae 1104 * @param __AUTORELOAD__: specifies the Counter register new value.
bogdanm 86:04dd9b1680ae 1105 * @retval None
bogdanm 86:04dd9b1680ae 1106 */
bogdanm 86:04dd9b1680ae 1107 #define __HAL_TIM_SetAutoreload(__HANDLE__, __AUTORELOAD__) \
bogdanm 86:04dd9b1680ae 1108 do{ \
bogdanm 86:04dd9b1680ae 1109 (__HANDLE__)->Instance->ARR = (__AUTORELOAD__); \
bogdanm 86:04dd9b1680ae 1110 (__HANDLE__)->Init.Period = (__AUTORELOAD__); \
bogdanm 86:04dd9b1680ae 1111 } while(0)
bogdanm 86:04dd9b1680ae 1112
bogdanm 86:04dd9b1680ae 1113 /**
bogdanm 86:04dd9b1680ae 1114 * @brief Gets the TIM Autoreload Register value on runtime
bogdanm 86:04dd9b1680ae 1115 * @param __HANDLE__: TIM handle.
bogdanm 86:04dd9b1680ae 1116 * @retval None
bogdanm 86:04dd9b1680ae 1117 */
bogdanm 86:04dd9b1680ae 1118 #define __HAL_TIM_GetAutoreload(__HANDLE__) \
bogdanm 86:04dd9b1680ae 1119 ((__HANDLE__)->Instance->ARR)
bogdanm 86:04dd9b1680ae 1120
bogdanm 86:04dd9b1680ae 1121 /**
bogdanm 86:04dd9b1680ae 1122 * @brief Sets the TIM Clock Division value on runtime without calling
bogdanm 86:04dd9b1680ae 1123 * another time any Init function.
bogdanm 86:04dd9b1680ae 1124 * @param __HANDLE__: TIM handle.
bogdanm 86:04dd9b1680ae 1125 * @param __CKD__: specifies the clock division value.
bogdanm 86:04dd9b1680ae 1126 * This parameter can be one of the following value:
bogdanm 86:04dd9b1680ae 1127 * @arg TIM_CLOCKDIVISION_DIV1
bogdanm 86:04dd9b1680ae 1128 * @arg TIM_CLOCKDIVISION_DIV2
bogdanm 86:04dd9b1680ae 1129 * @arg TIM_CLOCKDIVISION_DIV4
bogdanm 86:04dd9b1680ae 1130 * @retval None
bogdanm 86:04dd9b1680ae 1131 */
bogdanm 86:04dd9b1680ae 1132 #define __HAL_TIM_SetClockDivision(__HANDLE__, __CKD__) \
bogdanm 86:04dd9b1680ae 1133 do{ \
bogdanm 86:04dd9b1680ae 1134 (__HANDLE__)->Instance->CR1 &= (uint16_t)(~TIM_CR1_CKD); \
bogdanm 86:04dd9b1680ae 1135 (__HANDLE__)->Instance->CR1 |= (__CKD__); \
bogdanm 86:04dd9b1680ae 1136 (__HANDLE__)->Init.ClockDivision = (__CKD__); \
bogdanm 86:04dd9b1680ae 1137 } while(0)
bogdanm 86:04dd9b1680ae 1138
bogdanm 86:04dd9b1680ae 1139 /**
bogdanm 86:04dd9b1680ae 1140 * @brief Gets the TIM Clock Division value on runtime
bogdanm 86:04dd9b1680ae 1141 * @param __HANDLE__: TIM handle.
bogdanm 86:04dd9b1680ae 1142 * @retval None
bogdanm 86:04dd9b1680ae 1143 */
bogdanm 86:04dd9b1680ae 1144 #define __HAL_TIM_GetClockDivision(__HANDLE__) \
bogdanm 86:04dd9b1680ae 1145 ((__HANDLE__)->Instance->CR1 & TIM_CR1_CKD)
bogdanm 86:04dd9b1680ae 1146
bogdanm 86:04dd9b1680ae 1147 /**
bogdanm 86:04dd9b1680ae 1148 * @brief Sets the TIM Input Capture prescaler on runtime without calling
bogdanm 86:04dd9b1680ae 1149 * another time HAL_TIM_IC_ConfigChannel() function.
bogdanm 86:04dd9b1680ae 1150 * @param __HANDLE__: TIM handle.
bogdanm 86:04dd9b1680ae 1151 * @param __CHANNEL__ : TIM Channels to be configured.
bogdanm 86:04dd9b1680ae 1152 * This parameter can be one of the following values:
bogdanm 86:04dd9b1680ae 1153 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
bogdanm 86:04dd9b1680ae 1154 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
bogdanm 86:04dd9b1680ae 1155 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
bogdanm 86:04dd9b1680ae 1156 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
bogdanm 86:04dd9b1680ae 1157 * @param __ICPSC__: specifies the Input Capture4 prescaler new value.
bogdanm 86:04dd9b1680ae 1158 * This parameter can be one of the following values:
bogdanm 86:04dd9b1680ae 1159 * @arg TIM_ICPSC_DIV1: no prescaler
bogdanm 86:04dd9b1680ae 1160 * @arg TIM_ICPSC_DIV2: capture is done once every 2 events
bogdanm 86:04dd9b1680ae 1161 * @arg TIM_ICPSC_DIV4: capture is done once every 4 events
bogdanm 86:04dd9b1680ae 1162 * @arg TIM_ICPSC_DIV8: capture is done once every 8 events
bogdanm 86:04dd9b1680ae 1163 * @retval None
bogdanm 86:04dd9b1680ae 1164 */
bogdanm 86:04dd9b1680ae 1165 #define __HAL_TIM_SetICPrescaler(__HANDLE__, __CHANNEL__, __ICPSC__) \
bogdanm 86:04dd9b1680ae 1166 do{ \
bogdanm 86:04dd9b1680ae 1167 __HAL_TIM_ResetICPrescalerValue((__HANDLE__), (__CHANNEL__)); \
bogdanm 86:04dd9b1680ae 1168 __HAL_TIM_SetICPrescalerValue((__HANDLE__), (__CHANNEL__), (__ICPSC__)); \
bogdanm 86:04dd9b1680ae 1169 } while(0)
bogdanm 86:04dd9b1680ae 1170
bogdanm 86:04dd9b1680ae 1171 /**
bogdanm 86:04dd9b1680ae 1172 * @brief Gets the TIM Input Capture prescaler on runtime
bogdanm 86:04dd9b1680ae 1173 * @param __HANDLE__: TIM handle.
bogdanm 86:04dd9b1680ae 1174 * @param __CHANNEL__ : TIM Channels to be configured.
bogdanm 86:04dd9b1680ae 1175 * This parameter can be one of the following values:
bogdanm 86:04dd9b1680ae 1176 * @arg TIM_CHANNEL_1: get input capture 1 prescaler value
bogdanm 86:04dd9b1680ae 1177 * @arg TIM_CHANNEL_2: get input capture 2 prescaler value
bogdanm 86:04dd9b1680ae 1178 * @arg TIM_CHANNEL_3: get input capture 3 prescaler value
bogdanm 86:04dd9b1680ae 1179 * @arg TIM_CHANNEL_4: get input capture 4 prescaler value
bogdanm 86:04dd9b1680ae 1180 * @retval None
bogdanm 86:04dd9b1680ae 1181 */
bogdanm 86:04dd9b1680ae 1182 #define __HAL_TIM_GetICPrescaler(__HANDLE__, __CHANNEL__) \
bogdanm 86:04dd9b1680ae 1183 (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 & TIM_CCMR1_IC1PSC) :\
bogdanm 86:04dd9b1680ae 1184 ((__CHANNEL__) == TIM_CHANNEL_2) ? (((__HANDLE__)->Instance->CCMR1 & TIM_CCMR1_IC2PSC) >> 8) :\
bogdanm 86:04dd9b1680ae 1185 ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 & TIM_CCMR2_IC3PSC) :\
bogdanm 86:04dd9b1680ae 1186 (((__HANDLE__)->Instance->CCMR2 & TIM_CCMR2_IC4PSC)) >> 8)
bogdanm 86:04dd9b1680ae 1187
bogdanm 86:04dd9b1680ae 1188 /**
bogdanm 92:4fc01daae5a5 1189 * @brief Set the Update Request Source (URS) bit of the TIMx_CR1 register
bogdanm 92:4fc01daae5a5 1190 * @param __HANDLE__: TIM handle.
bogdanm 92:4fc01daae5a5 1191 * @note When the USR bit of the TIMx_CR1 register is set, only counter
bogdanm 92:4fc01daae5a5 1192 * overflow/underflow generates an update interrupt or DMA request (if
bogdanm 92:4fc01daae5a5 1193 * enabled)
bogdanm 92:4fc01daae5a5 1194 * @retval None
bogdanm 92:4fc01daae5a5 1195 */
bogdanm 92:4fc01daae5a5 1196 #define __HAL_TIM_URS_ENABLE(__HANDLE__) \
bogdanm 92:4fc01daae5a5 1197 ((__HANDLE__)->Instance->CR1|= (TIM_CR1_URS))
bogdanm 92:4fc01daae5a5 1198
bogdanm 92:4fc01daae5a5 1199 /**
bogdanm 92:4fc01daae5a5 1200 * @brief Reset the Update Request Source (URS) bit of the TIMx_CR1 register
bogdanm 92:4fc01daae5a5 1201 * @param __HANDLE__: TIM handle.
bogdanm 92:4fc01daae5a5 1202 * @note When the USR bit of the TIMx_CR1 register is reset, any of the
bogdanm 92:4fc01daae5a5 1203 * following events generate an update interrupt or DMA request (if
bogdanm 92:4fc01daae5a5 1204 * enabled):
bogdanm 92:4fc01daae5a5 1205 * – Counter overflow/underflow
bogdanm 92:4fc01daae5a5 1206 * – Setting the UG bit
bogdanm 92:4fc01daae5a5 1207 * – Update generation through the slave mode controller
bogdanm 92:4fc01daae5a5 1208 * @retval None
bogdanm 92:4fc01daae5a5 1209 */
bogdanm 92:4fc01daae5a5 1210 #define __HAL_TIM_URS_DISABLE(__HANDLE__) \
bogdanm 92:4fc01daae5a5 1211 ((__HANDLE__)->Instance->CR1&=~(TIM_CR1_URS))
bogdanm 92:4fc01daae5a5 1212
bogdanm 92:4fc01daae5a5 1213 /**
bogdanm 86:04dd9b1680ae 1214 * @}
bogdanm 86:04dd9b1680ae 1215 */
bogdanm 86:04dd9b1680ae 1216
bogdanm 92:4fc01daae5a5 1217 /* Include TIM HAL Extended module */
bogdanm 86:04dd9b1680ae 1218 #include "stm32f3xx_hal_tim_ex.h"
bogdanm 86:04dd9b1680ae 1219
bogdanm 86:04dd9b1680ae 1220 /* Exported functions --------------------------------------------------------*/
bogdanm 92:4fc01daae5a5 1221 /** @addtogroup TIM_Exported_Functions TIM Exported Functions
bogdanm 92:4fc01daae5a5 1222 * @{
bogdanm 92:4fc01daae5a5 1223 */
bogdanm 86:04dd9b1680ae 1224
bogdanm 92:4fc01daae5a5 1225 /** @addtogroup TIM_Exported_Functions_Group1 Time Base functions
bogdanm 92:4fc01daae5a5 1226 * @brief Time Base functions
bogdanm 92:4fc01daae5a5 1227 * @{
bogdanm 92:4fc01daae5a5 1228 */
bogdanm 86:04dd9b1680ae 1229 /* Time Base functions ********************************************************/
bogdanm 86:04dd9b1680ae 1230 HAL_StatusTypeDef HAL_TIM_Base_Init(TIM_HandleTypeDef *htim);
bogdanm 86:04dd9b1680ae 1231 HAL_StatusTypeDef HAL_TIM_Base_DeInit(TIM_HandleTypeDef *htim);
bogdanm 86:04dd9b1680ae 1232 void HAL_TIM_Base_MspInit(TIM_HandleTypeDef *htim);
bogdanm 86:04dd9b1680ae 1233 void HAL_TIM_Base_MspDeInit(TIM_HandleTypeDef *htim);
bogdanm 86:04dd9b1680ae 1234 /* Blocking mode: Polling */
bogdanm 86:04dd9b1680ae 1235 HAL_StatusTypeDef HAL_TIM_Base_Start(TIM_HandleTypeDef *htim);
bogdanm 86:04dd9b1680ae 1236 HAL_StatusTypeDef HAL_TIM_Base_Stop(TIM_HandleTypeDef *htim);
bogdanm 86:04dd9b1680ae 1237 /* Non-Blocking mode: Interrupt */
bogdanm 86:04dd9b1680ae 1238 HAL_StatusTypeDef HAL_TIM_Base_Start_IT(TIM_HandleTypeDef *htim);
bogdanm 86:04dd9b1680ae 1239 HAL_StatusTypeDef HAL_TIM_Base_Stop_IT(TIM_HandleTypeDef *htim);
bogdanm 86:04dd9b1680ae 1240 /* Non-Blocking mode: DMA */
bogdanm 86:04dd9b1680ae 1241 HAL_StatusTypeDef HAL_TIM_Base_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pData, uint16_t Length);
bogdanm 86:04dd9b1680ae 1242 HAL_StatusTypeDef HAL_TIM_Base_Stop_DMA(TIM_HandleTypeDef *htim);
bogdanm 92:4fc01daae5a5 1243 /**
bogdanm 92:4fc01daae5a5 1244 * @}
bogdanm 92:4fc01daae5a5 1245 */
bogdanm 86:04dd9b1680ae 1246
bogdanm 92:4fc01daae5a5 1247 /** @addtogroup TIM_Exported_Functions_Group2 Time Output Compare functions
bogdanm 92:4fc01daae5a5 1248 * @brief Time Output Compare functions
bogdanm 92:4fc01daae5a5 1249 * @{
bogdanm 92:4fc01daae5a5 1250 */
bogdanm 86:04dd9b1680ae 1251 /* Timer Output Compare functions **********************************************/
bogdanm 86:04dd9b1680ae 1252 HAL_StatusTypeDef HAL_TIM_OC_Init(TIM_HandleTypeDef *htim);
bogdanm 86:04dd9b1680ae 1253 HAL_StatusTypeDef HAL_TIM_OC_DeInit(TIM_HandleTypeDef *htim);
bogdanm 86:04dd9b1680ae 1254 void HAL_TIM_OC_MspInit(TIM_HandleTypeDef *htim);
bogdanm 86:04dd9b1680ae 1255 void HAL_TIM_OC_MspDeInit(TIM_HandleTypeDef *htim);
bogdanm 86:04dd9b1680ae 1256 /* Blocking mode: Polling */
bogdanm 86:04dd9b1680ae 1257 HAL_StatusTypeDef HAL_TIM_OC_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
bogdanm 86:04dd9b1680ae 1258 HAL_StatusTypeDef HAL_TIM_OC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
bogdanm 86:04dd9b1680ae 1259 /* Non-Blocking mode: Interrupt */
bogdanm 86:04dd9b1680ae 1260 HAL_StatusTypeDef HAL_TIM_OC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
bogdanm 86:04dd9b1680ae 1261 HAL_StatusTypeDef HAL_TIM_OC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
bogdanm 86:04dd9b1680ae 1262 /* Non-Blocking mode: DMA */
bogdanm 86:04dd9b1680ae 1263 HAL_StatusTypeDef HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length);
bogdanm 86:04dd9b1680ae 1264 HAL_StatusTypeDef HAL_TIM_OC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
bogdanm 92:4fc01daae5a5 1265 /**
bogdanm 92:4fc01daae5a5 1266 * @}
bogdanm 92:4fc01daae5a5 1267 */
bogdanm 92:4fc01daae5a5 1268
bogdanm 92:4fc01daae5a5 1269 /** @addtogroup TIM_Exported_Functions_Group3 Time PWM functions
bogdanm 92:4fc01daae5a5 1270 * @brief Time PWM functions
bogdanm 92:4fc01daae5a5 1271 * @{
bogdanm 92:4fc01daae5a5 1272 */
bogdanm 86:04dd9b1680ae 1273 /* Timer PWM functions *********************************************************/
bogdanm 86:04dd9b1680ae 1274 HAL_StatusTypeDef HAL_TIM_PWM_Init(TIM_HandleTypeDef *htim);
bogdanm 86:04dd9b1680ae 1275 HAL_StatusTypeDef HAL_TIM_PWM_DeInit(TIM_HandleTypeDef *htim);
bogdanm 86:04dd9b1680ae 1276 void HAL_TIM_PWM_MspInit(TIM_HandleTypeDef *htim);
bogdanm 86:04dd9b1680ae 1277 void HAL_TIM_PWM_MspDeInit(TIM_HandleTypeDef *htim);
bogdanm 86:04dd9b1680ae 1278 /* Blocking mode: Polling */
bogdanm 86:04dd9b1680ae 1279 HAL_StatusTypeDef HAL_TIM_PWM_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
bogdanm 86:04dd9b1680ae 1280 HAL_StatusTypeDef HAL_TIM_PWM_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
bogdanm 86:04dd9b1680ae 1281 /* Non-Blocking mode: Interrupt */
bogdanm 86:04dd9b1680ae 1282 HAL_StatusTypeDef HAL_TIM_PWM_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
bogdanm 86:04dd9b1680ae 1283 HAL_StatusTypeDef HAL_TIM_PWM_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
bogdanm 86:04dd9b1680ae 1284 /* Non-Blocking mode: DMA */
bogdanm 86:04dd9b1680ae 1285 HAL_StatusTypeDef HAL_TIM_PWM_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length);
bogdanm 86:04dd9b1680ae 1286 HAL_StatusTypeDef HAL_TIM_PWM_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
bogdanm 92:4fc01daae5a5 1287 /**
bogdanm 92:4fc01daae5a5 1288 * @}
bogdanm 92:4fc01daae5a5 1289 */
bogdanm 92:4fc01daae5a5 1290
bogdanm 92:4fc01daae5a5 1291 /** @addtogroup TIM_Exported_Functions_Group4 Time Input Capture functions
bogdanm 92:4fc01daae5a5 1292 * @brief Time Input Capture functions
bogdanm 92:4fc01daae5a5 1293 * @{
bogdanm 92:4fc01daae5a5 1294 */
bogdanm 86:04dd9b1680ae 1295 /* Timer Input Capture functions ***********************************************/
bogdanm 86:04dd9b1680ae 1296 HAL_StatusTypeDef HAL_TIM_IC_Init(TIM_HandleTypeDef *htim);
bogdanm 86:04dd9b1680ae 1297 HAL_StatusTypeDef HAL_TIM_IC_DeInit(TIM_HandleTypeDef *htim);
bogdanm 86:04dd9b1680ae 1298 void HAL_TIM_IC_MspInit(TIM_HandleTypeDef *htim);
bogdanm 86:04dd9b1680ae 1299 void HAL_TIM_IC_MspDeInit(TIM_HandleTypeDef *htim);
bogdanm 86:04dd9b1680ae 1300 /* Blocking mode: Polling */
bogdanm 86:04dd9b1680ae 1301 HAL_StatusTypeDef HAL_TIM_IC_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
bogdanm 86:04dd9b1680ae 1302 HAL_StatusTypeDef HAL_TIM_IC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
bogdanm 86:04dd9b1680ae 1303 /* Non-Blocking mode: Interrupt */
bogdanm 86:04dd9b1680ae 1304 HAL_StatusTypeDef HAL_TIM_IC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
bogdanm 86:04dd9b1680ae 1305 HAL_StatusTypeDef HAL_TIM_IC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
bogdanm 86:04dd9b1680ae 1306 /* Non-Blocking mode: DMA */
bogdanm 86:04dd9b1680ae 1307 HAL_StatusTypeDef HAL_TIM_IC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length);
bogdanm 86:04dd9b1680ae 1308 HAL_StatusTypeDef HAL_TIM_IC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
bogdanm 92:4fc01daae5a5 1309 /**
bogdanm 92:4fc01daae5a5 1310 * @}
bogdanm 92:4fc01daae5a5 1311 */
bogdanm 92:4fc01daae5a5 1312
bogdanm 92:4fc01daae5a5 1313 /** @addtogroup TIM_Exported_Functions_Group5 Time One Pulse functions
bogdanm 92:4fc01daae5a5 1314 * @brief Time One Pulse functions
bogdanm 92:4fc01daae5a5 1315 * @{
bogdanm 92:4fc01daae5a5 1316 */
bogdanm 86:04dd9b1680ae 1317 /* Timer One Pulse functions ***************************************************/
bogdanm 86:04dd9b1680ae 1318 HAL_StatusTypeDef HAL_TIM_OnePulse_Init(TIM_HandleTypeDef *htim, uint32_t OnePulseMode);
bogdanm 86:04dd9b1680ae 1319 HAL_StatusTypeDef HAL_TIM_OnePulse_DeInit(TIM_HandleTypeDef *htim);
bogdanm 86:04dd9b1680ae 1320 void HAL_TIM_OnePulse_MspInit(TIM_HandleTypeDef *htim);
bogdanm 86:04dd9b1680ae 1321 void HAL_TIM_OnePulse_MspDeInit(TIM_HandleTypeDef *htim);
bogdanm 86:04dd9b1680ae 1322 /* Blocking mode: Polling */
bogdanm 86:04dd9b1680ae 1323 HAL_StatusTypeDef HAL_TIM_OnePulse_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
bogdanm 86:04dd9b1680ae 1324 HAL_StatusTypeDef HAL_TIM_OnePulse_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
bogdanm 86:04dd9b1680ae 1325 /* Non-Blocking mode: Interrupt */
bogdanm 86:04dd9b1680ae 1326 HAL_StatusTypeDef HAL_TIM_OnePulse_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
bogdanm 86:04dd9b1680ae 1327 HAL_StatusTypeDef HAL_TIM_OnePulse_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
bogdanm 92:4fc01daae5a5 1328 /**
bogdanm 92:4fc01daae5a5 1329 * @}
bogdanm 92:4fc01daae5a5 1330 */
bogdanm 86:04dd9b1680ae 1331
bogdanm 92:4fc01daae5a5 1332 /** @addtogroup TIM_Exported_Functions_Group6 Time Encoder functions
bogdanm 92:4fc01daae5a5 1333 * @brief Time Encoder functions
bogdanm 92:4fc01daae5a5 1334 * @{
bogdanm 92:4fc01daae5a5 1335 */
bogdanm 86:04dd9b1680ae 1336 /* Timer Encoder functions *****************************************************/
bogdanm 86:04dd9b1680ae 1337 HAL_StatusTypeDef HAL_TIM_Encoder_Init(TIM_HandleTypeDef *htim, TIM_Encoder_InitTypeDef* sConfig);
bogdanm 86:04dd9b1680ae 1338 HAL_StatusTypeDef HAL_TIM_Encoder_DeInit(TIM_HandleTypeDef *htim);
bogdanm 86:04dd9b1680ae 1339 void HAL_TIM_Encoder_MspInit(TIM_HandleTypeDef *htim);
bogdanm 86:04dd9b1680ae 1340 void HAL_TIM_Encoder_MspDeInit(TIM_HandleTypeDef *htim);
bogdanm 86:04dd9b1680ae 1341 /* Blocking mode: Polling */
bogdanm 86:04dd9b1680ae 1342 HAL_StatusTypeDef HAL_TIM_Encoder_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
bogdanm 86:04dd9b1680ae 1343 HAL_StatusTypeDef HAL_TIM_Encoder_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
bogdanm 86:04dd9b1680ae 1344 /* Non-Blocking mode: Interrupt */
bogdanm 86:04dd9b1680ae 1345 HAL_StatusTypeDef HAL_TIM_Encoder_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
bogdanm 86:04dd9b1680ae 1346 HAL_StatusTypeDef HAL_TIM_Encoder_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
bogdanm 86:04dd9b1680ae 1347 /* Non-Blocking mode: DMA */
bogdanm 86:04dd9b1680ae 1348 HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData1, uint32_t *pData2, uint16_t Length);
bogdanm 86:04dd9b1680ae 1349 HAL_StatusTypeDef HAL_TIM_Encoder_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
bogdanm 92:4fc01daae5a5 1350 /**
bogdanm 92:4fc01daae5a5 1351 * @}
bogdanm 92:4fc01daae5a5 1352 */
bogdanm 86:04dd9b1680ae 1353
bogdanm 92:4fc01daae5a5 1354 /** @addtogroup TIM_Exported_Functions_Group7 TIM IRQ handler management
bogdanm 92:4fc01daae5a5 1355 * @brief IRQ handler management
bogdanm 92:4fc01daae5a5 1356 * @{
bogdanm 92:4fc01daae5a5 1357 */
bogdanm 86:04dd9b1680ae 1358 /* Interrupt Handler functions **********************************************/
bogdanm 86:04dd9b1680ae 1359 void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim);
bogdanm 92:4fc01daae5a5 1360 /**
bogdanm 92:4fc01daae5a5 1361 * @}
bogdanm 92:4fc01daae5a5 1362 */
bogdanm 86:04dd9b1680ae 1363
bogdanm 92:4fc01daae5a5 1364 /** @defgroup TIM_Exported_Functions_Group8 Peripheral Control functions
bogdanm 92:4fc01daae5a5 1365 * @brief Peripheral Control functions
bogdanm 92:4fc01daae5a5 1366 * @{
bogdanm 92:4fc01daae5a5 1367 */
bogdanm 86:04dd9b1680ae 1368 /* Control functions *********************************************************/
bogdanm 86:04dd9b1680ae 1369 HAL_StatusTypeDef HAL_TIM_OC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OC_InitTypeDef* sConfig, uint32_t Channel);
bogdanm 86:04dd9b1680ae 1370 HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OC_InitTypeDef* sConfig, uint32_t Channel);
bogdanm 86:04dd9b1680ae 1371 HAL_StatusTypeDef HAL_TIM_IC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_IC_InitTypeDef* sConfig, uint32_t Channel);
bogdanm 86:04dd9b1680ae 1372 HAL_StatusTypeDef HAL_TIM_OnePulse_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OnePulse_InitTypeDef* sConfig, uint32_t OutputChannel, uint32_t InputChannel);
bogdanm 86:04dd9b1680ae 1373 HAL_StatusTypeDef HAL_TIM_ConfigOCrefClear(TIM_HandleTypeDef *htim, TIM_ClearInputConfigTypeDef * sClearInputConfig, uint32_t Channel);
bogdanm 86:04dd9b1680ae 1374 HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef *htim, TIM_ClockConfigTypeDef * sClockSourceConfig);
bogdanm 86:04dd9b1680ae 1375 HAL_StatusTypeDef HAL_TIM_ConfigTI1Input(TIM_HandleTypeDef *htim, uint32_t TI1_Selection);
bogdanm 86:04dd9b1680ae 1376 HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchronization(TIM_HandleTypeDef *htim, TIM_SlaveConfigTypeDef * sSlaveConfig);
bogdanm 86:04dd9b1680ae 1377 HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc, \
bogdanm 86:04dd9b1680ae 1378 uint32_t *BurstBuffer, uint32_t BurstLength);
bogdanm 86:04dd9b1680ae 1379 HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc);
bogdanm 86:04dd9b1680ae 1380 HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc, \
bogdanm 86:04dd9b1680ae 1381 uint32_t *BurstBuffer, uint32_t BurstLength);
bogdanm 86:04dd9b1680ae 1382 HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc);
bogdanm 86:04dd9b1680ae 1383 HAL_StatusTypeDef HAL_TIM_GenerateEvent(TIM_HandleTypeDef *htim, uint32_t EventSource);
bogdanm 86:04dd9b1680ae 1384 uint32_t HAL_TIM_ReadCapturedValue(TIM_HandleTypeDef *htim, uint32_t Channel);
bogdanm 92:4fc01daae5a5 1385 /**
bogdanm 92:4fc01daae5a5 1386 * @}
bogdanm 92:4fc01daae5a5 1387 */
bogdanm 86:04dd9b1680ae 1388
bogdanm 92:4fc01daae5a5 1389 /** @defgroup TIM_Exported_Functions_Group9 TIM Callbacks functions
bogdanm 92:4fc01daae5a5 1390 * @brief TIM Callbacks functions
bogdanm 92:4fc01daae5a5 1391 * @{
bogdanm 92:4fc01daae5a5 1392 */
bogdanm 86:04dd9b1680ae 1393 /* Callback in non blocking modes (Interrupt and DMA) *************************/
bogdanm 86:04dd9b1680ae 1394 void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim);
bogdanm 86:04dd9b1680ae 1395 void HAL_TIM_OC_DelayElapsedCallback(TIM_HandleTypeDef *htim);
bogdanm 86:04dd9b1680ae 1396 void HAL_TIM_IC_CaptureCallback(TIM_HandleTypeDef *htim);
bogdanm 86:04dd9b1680ae 1397 void HAL_TIM_PWM_PulseFinishedCallback(TIM_HandleTypeDef *htim);
bogdanm 86:04dd9b1680ae 1398 void HAL_TIM_TriggerCallback(TIM_HandleTypeDef *htim);
bogdanm 86:04dd9b1680ae 1399 void HAL_TIM_ErrorCallback(TIM_HandleTypeDef *htim);
bogdanm 92:4fc01daae5a5 1400 /**
bogdanm 92:4fc01daae5a5 1401 * @}
bogdanm 92:4fc01daae5a5 1402 */
bogdanm 86:04dd9b1680ae 1403
bogdanm 92:4fc01daae5a5 1404 /** @defgroup TIM_Exported_Functions_Group10 Peripheral State functions
bogdanm 92:4fc01daae5a5 1405 * @brief Peripheral State functions
bogdanm 92:4fc01daae5a5 1406 * @{
bogdanm 92:4fc01daae5a5 1407 */
bogdanm 86:04dd9b1680ae 1408 /* Peripheral State functions **************************************************/
bogdanm 86:04dd9b1680ae 1409 HAL_TIM_StateTypeDef HAL_TIM_Base_GetState(TIM_HandleTypeDef *htim);
bogdanm 86:04dd9b1680ae 1410 HAL_TIM_StateTypeDef HAL_TIM_OC_GetState(TIM_HandleTypeDef *htim);
bogdanm 86:04dd9b1680ae 1411 HAL_TIM_StateTypeDef HAL_TIM_PWM_GetState(TIM_HandleTypeDef *htim);
bogdanm 86:04dd9b1680ae 1412 HAL_TIM_StateTypeDef HAL_TIM_IC_GetState(TIM_HandleTypeDef *htim);
bogdanm 86:04dd9b1680ae 1413 HAL_TIM_StateTypeDef HAL_TIM_OnePulse_GetState(TIM_HandleTypeDef *htim);
bogdanm 86:04dd9b1680ae 1414 HAL_TIM_StateTypeDef HAL_TIM_Encoder_GetState(TIM_HandleTypeDef *htim);
bogdanm 92:4fc01daae5a5 1415 /**
bogdanm 92:4fc01daae5a5 1416 * @}
bogdanm 92:4fc01daae5a5 1417 */
bogdanm 92:4fc01daae5a5 1418
bogdanm 92:4fc01daae5a5 1419 /**
bogdanm 92:4fc01daae5a5 1420 * @}
bogdanm 92:4fc01daae5a5 1421 */
bogdanm 86:04dd9b1680ae 1422
bogdanm 86:04dd9b1680ae 1423 void TIM_Base_SetConfig(TIM_TypeDef *TIMx, TIM_Base_InitTypeDef *Structure);
bogdanm 86:04dd9b1680ae 1424 void TIM_TI1_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, uint32_t TIM_ICFilter);
bogdanm 86:04dd9b1680ae 1425 void TIM_OC1_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config);
bogdanm 86:04dd9b1680ae 1426 void TIM_OC2_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config);
bogdanm 86:04dd9b1680ae 1427 void TIM_OC3_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config);
bogdanm 86:04dd9b1680ae 1428 void TIM_OC4_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config);
bogdanm 86:04dd9b1680ae 1429 void TIM_ETR_SetConfig(TIM_TypeDef* TIMx, uint32_t TIM_ExtTRGPrescaler,
bogdanm 86:04dd9b1680ae 1430 uint32_t TIM_ExtTRGPolarity, uint32_t ExtTRGFilter);
bogdanm 86:04dd9b1680ae 1431
bogdanm 86:04dd9b1680ae 1432 void HAL_TIM_DMADelayPulseCplt(DMA_HandleTypeDef *hdma);
bogdanm 86:04dd9b1680ae 1433 void HAL_TIM_DMAError(DMA_HandleTypeDef *hdma);
bogdanm 86:04dd9b1680ae 1434 void HAL_TIM_DMACaptureCplt(DMA_HandleTypeDef *hdma);
bogdanm 86:04dd9b1680ae 1435 void TIM_CCxChannelCmd(TIM_TypeDef* TIMx, uint32_t Channel, uint32_t ChannelState);
bogdanm 86:04dd9b1680ae 1436
bogdanm 86:04dd9b1680ae 1437 /**
bogdanm 86:04dd9b1680ae 1438 * @}
bogdanm 92:4fc01daae5a5 1439 */
bogdanm 86:04dd9b1680ae 1440
bogdanm 86:04dd9b1680ae 1441 /**
bogdanm 86:04dd9b1680ae 1442 * @}
bogdanm 86:04dd9b1680ae 1443 */
bogdanm 86:04dd9b1680ae 1444
bogdanm 86:04dd9b1680ae 1445 #ifdef __cplusplus
bogdanm 86:04dd9b1680ae 1446 }
bogdanm 86:04dd9b1680ae 1447 #endif
bogdanm 86:04dd9b1680ae 1448
bogdanm 86:04dd9b1680ae 1449 #endif /* __STM32F3xx_HAL_TIM_H */
bogdanm 86:04dd9b1680ae 1450
bogdanm 86:04dd9b1680ae 1451 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/