mbed-rtos
Fork of mbed-rtos by
rtx/rt_HAL_CM.h@70:923739f38354, 2015-04-16 (annotated)
- Committer:
- yusuke_kyo
- Date:
- Thu Apr 16 02:36:31 2015 +0000
- Revision:
- 70:923739f38354
- Parent:
- 10:fcb1f103f7a1
- Child:
- 31:015df9e602b6
error.h -> mbed_error.h
Who changed what in which revision?
User | Revision | Line number | New contents of line |
---|---|---|---|
emilmont | 6:350b53afb889 | 1 | /*---------------------------------------------------------------------------- |
emilmont | 6:350b53afb889 | 2 | * RL-ARM - RTX |
emilmont | 6:350b53afb889 | 3 | *---------------------------------------------------------------------------- |
emilmont | 6:350b53afb889 | 4 | * Name: RT_HAL_CM.H |
emilmont | 6:350b53afb889 | 5 | * Purpose: Hardware Abstraction Layer for Cortex-M definitions |
emilmont | 6:350b53afb889 | 6 | * Rev.: V4.60 |
emilmont | 6:350b53afb889 | 7 | *---------------------------------------------------------------------------- |
emilmont | 6:350b53afb889 | 8 | * |
emilmont | 6:350b53afb889 | 9 | * Copyright (c) 1999-2009 KEIL, 2009-2012 ARM Germany GmbH |
emilmont | 6:350b53afb889 | 10 | * All rights reserved. |
emilmont | 6:350b53afb889 | 11 | * Redistribution and use in source and binary forms, with or without |
emilmont | 6:350b53afb889 | 12 | * modification, are permitted provided that the following conditions are met: |
emilmont | 6:350b53afb889 | 13 | * - Redistributions of source code must retain the above copyright |
emilmont | 6:350b53afb889 | 14 | * notice, this list of conditions and the following disclaimer. |
emilmont | 6:350b53afb889 | 15 | * - Redistributions in binary form must reproduce the above copyright |
emilmont | 6:350b53afb889 | 16 | * notice, this list of conditions and the following disclaimer in the |
emilmont | 6:350b53afb889 | 17 | * documentation and/or other materials provided with the distribution. |
emilmont | 6:350b53afb889 | 18 | * - Neither the name of ARM nor the names of its contributors may be used |
emilmont | 6:350b53afb889 | 19 | * to endorse or promote products derived from this software without |
emilmont | 6:350b53afb889 | 20 | * specific prior written permission. |
emilmont | 6:350b53afb889 | 21 | * |
emilmont | 6:350b53afb889 | 22 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
emilmont | 6:350b53afb889 | 23 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
emilmont | 6:350b53afb889 | 24 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE |
emilmont | 6:350b53afb889 | 25 | * ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE |
emilmont | 6:350b53afb889 | 26 | * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR |
emilmont | 6:350b53afb889 | 27 | * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF |
emilmont | 6:350b53afb889 | 28 | * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS |
emilmont | 6:350b53afb889 | 29 | * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN |
emilmont | 6:350b53afb889 | 30 | * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) |
emilmont | 6:350b53afb889 | 31 | * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE |
emilmont | 6:350b53afb889 | 32 | * POSSIBILITY OF SUCH DAMAGE. |
emilmont | 6:350b53afb889 | 33 | *---------------------------------------------------------------------------*/ |
emilmont | 6:350b53afb889 | 34 | |
emilmont | 6:350b53afb889 | 35 | /* Definitions */ |
emilmont | 6:350b53afb889 | 36 | #define INITIAL_xPSR 0x01000000 |
emilmont | 6:350b53afb889 | 37 | #define DEMCR_TRCENA 0x01000000 |
emilmont | 6:350b53afb889 | 38 | #define ITM_ITMENA 0x00000001 |
emilmont | 6:350b53afb889 | 39 | #define MAGIC_WORD 0xE25A2EA5 |
emilmont | 6:350b53afb889 | 40 | |
emilmont | 6:350b53afb889 | 41 | #if defined (__CC_ARM) /* ARM Compiler */ |
emilmont | 6:350b53afb889 | 42 | |
emilmont | 6:350b53afb889 | 43 | #if ((__TARGET_ARCH_7_M || __TARGET_ARCH_7E_M) && !NO_EXCLUSIVE_ACCESS) |
emilmont | 6:350b53afb889 | 44 | #define __USE_EXCLUSIVE_ACCESS |
emilmont | 6:350b53afb889 | 45 | #else |
emilmont | 6:350b53afb889 | 46 | #undef __USE_EXCLUSIVE_ACCESS |
emilmont | 6:350b53afb889 | 47 | #endif |
emilmont | 6:350b53afb889 | 48 | |
emilmont | 6:350b53afb889 | 49 | #elif defined (__GNUC__) /* GNU Compiler */ |
emilmont | 6:350b53afb889 | 50 | |
emilmont | 6:350b53afb889 | 51 | #undef __USE_EXCLUSIVE_ACCESS |
emilmont | 6:350b53afb889 | 52 | |
emilmont | 10:fcb1f103f7a1 | 53 | #if defined (__CORTEX_M0) || defined (__CORTEX_M0PLUS) |
emilmont | 6:350b53afb889 | 54 | #define __TARGET_ARCH_6S_M 1 |
emilmont | 6:350b53afb889 | 55 | #else |
emilmont | 6:350b53afb889 | 56 | #define __TARGET_ARCH_6S_M 0 |
emilmont | 6:350b53afb889 | 57 | #endif |
emilmont | 6:350b53afb889 | 58 | |
emilmont | 6:350b53afb889 | 59 | #if defined (__VFP_FP__) && !defined(__SOFTFP__) |
emilmont | 6:350b53afb889 | 60 | #define __TARGET_FPU_VFP 1 |
emilmont | 6:350b53afb889 | 61 | #else |
emilmont | 6:350b53afb889 | 62 | #define __TARGET_FPU_VFP 0 |
emilmont | 6:350b53afb889 | 63 | #endif |
emilmont | 6:350b53afb889 | 64 | |
emilmont | 6:350b53afb889 | 65 | #define __inline inline |
emilmont | 6:350b53afb889 | 66 | #define __weak __attribute__((weak)) |
emilmont | 6:350b53afb889 | 67 | |
emilmont | 6:350b53afb889 | 68 | #ifndef __CMSIS_GENERIC |
emilmont | 6:350b53afb889 | 69 | |
emilmont | 6:350b53afb889 | 70 | __attribute__((always_inline)) static inline void __enable_irq(void) |
emilmont | 6:350b53afb889 | 71 | { |
emilmont | 6:350b53afb889 | 72 | __asm volatile ("cpsie i"); |
emilmont | 6:350b53afb889 | 73 | } |
emilmont | 6:350b53afb889 | 74 | |
emilmont | 6:350b53afb889 | 75 | __attribute__((always_inline)) static inline U32 __disable_irq(void) |
emilmont | 6:350b53afb889 | 76 | { |
emilmont | 6:350b53afb889 | 77 | U32 result; |
emilmont | 6:350b53afb889 | 78 | |
emilmont | 6:350b53afb889 | 79 | __asm volatile ("mrs %0, primask" : "=r" (result)); |
emilmont | 6:350b53afb889 | 80 | __asm volatile ("cpsid i"); |
emilmont | 6:350b53afb889 | 81 | return(result & 1); |
emilmont | 6:350b53afb889 | 82 | } |
emilmont | 6:350b53afb889 | 83 | |
emilmont | 6:350b53afb889 | 84 | #endif |
emilmont | 6:350b53afb889 | 85 | |
emilmont | 6:350b53afb889 | 86 | __attribute__(( always_inline)) static inline U8 __clz(U32 value) |
emilmont | 6:350b53afb889 | 87 | { |
emilmont | 6:350b53afb889 | 88 | U8 result; |
emilmont | 6:350b53afb889 | 89 | |
emilmont | 6:350b53afb889 | 90 | __asm volatile ("clz %0, %1" : "=r" (result) : "r" (value)); |
emilmont | 6:350b53afb889 | 91 | return(result); |
emilmont | 6:350b53afb889 | 92 | } |
emilmont | 6:350b53afb889 | 93 | |
emilmont | 6:350b53afb889 | 94 | #elif defined (__ICCARM__) /* IAR Compiler */ |
emilmont | 6:350b53afb889 | 95 | |
emilmont | 6:350b53afb889 | 96 | #undef __USE_EXCLUSIVE_ACCESS |
emilmont | 6:350b53afb889 | 97 | |
emilmont | 6:350b53afb889 | 98 | #if (__CORE__ == __ARM6M__) |
emilmont | 6:350b53afb889 | 99 | #define __TARGET_ARCH_6S_M 1 |
emilmont | 6:350b53afb889 | 100 | #else |
emilmont | 6:350b53afb889 | 101 | #define __TARGET_ARCH_6S_M 0 |
emilmont | 6:350b53afb889 | 102 | #endif |
emilmont | 6:350b53afb889 | 103 | |
emilmont | 6:350b53afb889 | 104 | #if defined __ARMVFP__ |
emilmont | 6:350b53afb889 | 105 | #define __TARGET_FPU_VFP 1 |
emilmont | 6:350b53afb889 | 106 | #else |
emilmont | 6:350b53afb889 | 107 | #define __TARGET_FPU_VFP 0 |
emilmont | 6:350b53afb889 | 108 | #endif |
emilmont | 6:350b53afb889 | 109 | |
emilmont | 6:350b53afb889 | 110 | #define __inline inline |
emilmont | 6:350b53afb889 | 111 | |
emilmont | 6:350b53afb889 | 112 | #ifndef __CMSIS_GENERIC |
emilmont | 6:350b53afb889 | 113 | |
emilmont | 6:350b53afb889 | 114 | static inline void __enable_irq(void) |
emilmont | 6:350b53afb889 | 115 | { |
emilmont | 6:350b53afb889 | 116 | __asm volatile ("cpsie i"); |
emilmont | 6:350b53afb889 | 117 | } |
emilmont | 6:350b53afb889 | 118 | |
emilmont | 6:350b53afb889 | 119 | static inline U32 __disable_irq(void) |
emilmont | 6:350b53afb889 | 120 | { |
emilmont | 6:350b53afb889 | 121 | U32 result; |
emilmont | 6:350b53afb889 | 122 | |
emilmont | 6:350b53afb889 | 123 | __asm volatile ("mrs %0, primask" : "=r" (result)); |
emilmont | 6:350b53afb889 | 124 | __asm volatile ("cpsid i"); |
emilmont | 6:350b53afb889 | 125 | return(result & 1); |
emilmont | 6:350b53afb889 | 126 | } |
emilmont | 6:350b53afb889 | 127 | |
emilmont | 6:350b53afb889 | 128 | #endif |
emilmont | 6:350b53afb889 | 129 | |
emilmont | 6:350b53afb889 | 130 | static inline U8 __clz(U32 value) |
emilmont | 6:350b53afb889 | 131 | { |
emilmont | 6:350b53afb889 | 132 | U8 result; |
emilmont | 6:350b53afb889 | 133 | |
emilmont | 6:350b53afb889 | 134 | __asm volatile ("clz %0, %1" : "=r" (result) : "r" (value)); |
emilmont | 6:350b53afb889 | 135 | return(result); |
emilmont | 6:350b53afb889 | 136 | } |
emilmont | 6:350b53afb889 | 137 | |
emilmont | 6:350b53afb889 | 138 | #endif |
emilmont | 6:350b53afb889 | 139 | |
emilmont | 6:350b53afb889 | 140 | /* NVIC registers */ |
emilmont | 6:350b53afb889 | 141 | #define NVIC_ST_CTRL (*((volatile U32 *)0xE000E010)) |
emilmont | 6:350b53afb889 | 142 | #define NVIC_ST_RELOAD (*((volatile U32 *)0xE000E014)) |
emilmont | 6:350b53afb889 | 143 | #define NVIC_ST_CURRENT (*((volatile U32 *)0xE000E018)) |
emilmont | 6:350b53afb889 | 144 | #define NVIC_ISER ((volatile U32 *)0xE000E100) |
emilmont | 6:350b53afb889 | 145 | #define NVIC_ICER ((volatile U32 *)0xE000E180) |
emilmont | 6:350b53afb889 | 146 | #if (__TARGET_ARCH_6S_M) |
emilmont | 6:350b53afb889 | 147 | #define NVIC_IP ((volatile U32 *)0xE000E400) |
emilmont | 6:350b53afb889 | 148 | #else |
emilmont | 6:350b53afb889 | 149 | #define NVIC_IP ((volatile U8 *)0xE000E400) |
emilmont | 6:350b53afb889 | 150 | #endif |
emilmont | 6:350b53afb889 | 151 | #define NVIC_INT_CTRL (*((volatile U32 *)0xE000ED04)) |
emilmont | 6:350b53afb889 | 152 | #define NVIC_AIR_CTRL (*((volatile U32 *)0xE000ED0C)) |
emilmont | 6:350b53afb889 | 153 | #define NVIC_SYS_PRI2 (*((volatile U32 *)0xE000ED1C)) |
emilmont | 6:350b53afb889 | 154 | #define NVIC_SYS_PRI3 (*((volatile U32 *)0xE000ED20)) |
emilmont | 6:350b53afb889 | 155 | |
emilmont | 6:350b53afb889 | 156 | #define OS_PEND_IRQ() NVIC_INT_CTRL = (1<<28) |
emilmont | 6:350b53afb889 | 157 | #define OS_PENDING ((NVIC_INT_CTRL >> 26) & (1<<2 | 1)) |
emilmont | 6:350b53afb889 | 158 | #define OS_UNPEND(fl) NVIC_INT_CTRL = (*fl = OS_PENDING) << 25 |
emilmont | 6:350b53afb889 | 159 | #define OS_PEND(fl,p) NVIC_INT_CTRL = (fl | p<<2) << 26 |
emilmont | 6:350b53afb889 | 160 | #define OS_LOCK() NVIC_ST_CTRL = 0x0005 |
emilmont | 6:350b53afb889 | 161 | #define OS_UNLOCK() NVIC_ST_CTRL = 0x0007 |
emilmont | 6:350b53afb889 | 162 | |
emilmont | 6:350b53afb889 | 163 | #define OS_X_PENDING ((NVIC_INT_CTRL >> 28) & 1) |
emilmont | 6:350b53afb889 | 164 | #define OS_X_UNPEND(fl) NVIC_INT_CTRL = (*fl = OS_X_PENDING) << 27 |
emilmont | 6:350b53afb889 | 165 | #define OS_X_PEND(fl,p) NVIC_INT_CTRL = (fl | p) << 28 |
emilmont | 6:350b53afb889 | 166 | #if (__TARGET_ARCH_6S_M) |
emilmont | 6:350b53afb889 | 167 | #define OS_X_INIT(n) NVIC_IP[n>>2] |= 0xFF << (8*(n & 0x03)); \ |
emilmont | 6:350b53afb889 | 168 | NVIC_ISER[n>>5] = 1 << (n & 0x1F) |
emilmont | 6:350b53afb889 | 169 | #else |
emilmont | 6:350b53afb889 | 170 | #define OS_X_INIT(n) NVIC_IP[n] = 0xFF; \ |
emilmont | 6:350b53afb889 | 171 | NVIC_ISER[n>>5] = 1 << (n & 0x1F) |
emilmont | 6:350b53afb889 | 172 | #endif |
emilmont | 6:350b53afb889 | 173 | #define OS_X_LOCK(n) NVIC_ICER[n>>5] = 1 << (n & 0x1F) |
emilmont | 6:350b53afb889 | 174 | #define OS_X_UNLOCK(n) NVIC_ISER[n>>5] = 1 << (n & 0x1F) |
emilmont | 6:350b53afb889 | 175 | |
emilmont | 6:350b53afb889 | 176 | /* Core Debug registers */ |
emilmont | 6:350b53afb889 | 177 | #define DEMCR (*((volatile U32 *)0xE000EDFC)) |
emilmont | 6:350b53afb889 | 178 | |
emilmont | 6:350b53afb889 | 179 | /* ITM registers */ |
emilmont | 6:350b53afb889 | 180 | #define ITM_CONTROL (*((volatile U32 *)0xE0000E80)) |
emilmont | 6:350b53afb889 | 181 | #define ITM_ENABLE (*((volatile U32 *)0xE0000E00)) |
emilmont | 6:350b53afb889 | 182 | #define ITM_PORT30_U32 (*((volatile U32 *)0xE0000078)) |
emilmont | 6:350b53afb889 | 183 | #define ITM_PORT31_U32 (*((volatile U32 *)0xE000007C)) |
emilmont | 6:350b53afb889 | 184 | #define ITM_PORT31_U16 (*((volatile U16 *)0xE000007C)) |
emilmont | 6:350b53afb889 | 185 | #define ITM_PORT31_U8 (*((volatile U8 *)0xE000007C)) |
emilmont | 6:350b53afb889 | 186 | |
emilmont | 6:350b53afb889 | 187 | /* Variables */ |
emilmont | 6:350b53afb889 | 188 | extern BIT dbg_msg; |
emilmont | 6:350b53afb889 | 189 | |
emilmont | 6:350b53afb889 | 190 | /* Functions */ |
emilmont | 6:350b53afb889 | 191 | #ifdef __USE_EXCLUSIVE_ACCESS |
emilmont | 6:350b53afb889 | 192 | #define rt_inc(p) while(__strex((__ldrex(p)+1),p)) |
emilmont | 6:350b53afb889 | 193 | #define rt_dec(p) while(__strex((__ldrex(p)-1),p)) |
emilmont | 6:350b53afb889 | 194 | #else |
emilmont | 6:350b53afb889 | 195 | #define rt_inc(p) __disable_irq();(*p)++;__enable_irq(); |
emilmont | 6:350b53afb889 | 196 | #define rt_dec(p) __disable_irq();(*p)--;__enable_irq(); |
emilmont | 6:350b53afb889 | 197 | #endif |
emilmont | 6:350b53afb889 | 198 | |
emilmont | 6:350b53afb889 | 199 | __inline static U32 rt_inc_qi (U32 size, U8 *count, U8 *first) { |
emilmont | 6:350b53afb889 | 200 | U32 cnt,c2; |
emilmont | 6:350b53afb889 | 201 | #ifdef __USE_EXCLUSIVE_ACCESS |
emilmont | 6:350b53afb889 | 202 | do { |
emilmont | 6:350b53afb889 | 203 | if ((cnt = __ldrex(count)) == size) { |
emilmont | 6:350b53afb889 | 204 | __clrex(); |
emilmont | 6:350b53afb889 | 205 | return (cnt); } |
emilmont | 6:350b53afb889 | 206 | } while (__strex(cnt+1, count)); |
emilmont | 6:350b53afb889 | 207 | do { |
emilmont | 6:350b53afb889 | 208 | c2 = (cnt = __ldrex(first)) + 1; |
emilmont | 6:350b53afb889 | 209 | if (c2 == size) c2 = 0; |
emilmont | 6:350b53afb889 | 210 | } while (__strex(c2, first)); |
emilmont | 6:350b53afb889 | 211 | #else |
emilmont | 6:350b53afb889 | 212 | __disable_irq(); |
emilmont | 6:350b53afb889 | 213 | if ((cnt = *count) < size) { |
emilmont | 6:350b53afb889 | 214 | *count = cnt+1; |
emilmont | 6:350b53afb889 | 215 | c2 = (cnt = *first) + 1; |
emilmont | 6:350b53afb889 | 216 | if (c2 == size) c2 = 0; |
emilmont | 6:350b53afb889 | 217 | *first = c2; |
emilmont | 6:350b53afb889 | 218 | } |
emilmont | 6:350b53afb889 | 219 | __enable_irq (); |
emilmont | 6:350b53afb889 | 220 | #endif |
emilmont | 6:350b53afb889 | 221 | return (cnt); |
emilmont | 6:350b53afb889 | 222 | } |
emilmont | 6:350b53afb889 | 223 | |
emilmont | 6:350b53afb889 | 224 | __inline static void rt_systick_init (void) { |
emilmont | 6:350b53afb889 | 225 | NVIC_ST_RELOAD = os_trv; |
emilmont | 6:350b53afb889 | 226 | NVIC_ST_CURRENT = 0; |
emilmont | 6:350b53afb889 | 227 | NVIC_ST_CTRL = 0x0007; |
emilmont | 6:350b53afb889 | 228 | NVIC_SYS_PRI3 |= 0xFF000000; |
emilmont | 6:350b53afb889 | 229 | } |
emilmont | 6:350b53afb889 | 230 | |
emilmont | 6:350b53afb889 | 231 | __inline static void rt_svc_init (void) { |
emilmont | 6:350b53afb889 | 232 | #if !(__TARGET_ARCH_6S_M) |
emilmont | 6:350b53afb889 | 233 | int sh,prigroup; |
emilmont | 6:350b53afb889 | 234 | #endif |
emilmont | 6:350b53afb889 | 235 | NVIC_SYS_PRI3 |= 0x00FF0000; |
emilmont | 6:350b53afb889 | 236 | #if (__TARGET_ARCH_6S_M) |
emilmont | 6:350b53afb889 | 237 | NVIC_SYS_PRI2 |= (NVIC_SYS_PRI3<<(8+1)) & 0xFC000000; |
emilmont | 6:350b53afb889 | 238 | #else |
emilmont | 6:350b53afb889 | 239 | sh = 8 - __clz (~((NVIC_SYS_PRI3 << 8) & 0xFF000000)); |
emilmont | 6:350b53afb889 | 240 | prigroup = ((NVIC_AIR_CTRL >> 8) & 0x07); |
emilmont | 6:350b53afb889 | 241 | if (prigroup >= sh) { |
emilmont | 6:350b53afb889 | 242 | sh = prigroup + 1; |
emilmont | 6:350b53afb889 | 243 | } |
emilmont | 6:350b53afb889 | 244 | NVIC_SYS_PRI2 = ((0xFEFFFFFF << sh) & 0xFF000000) | (NVIC_SYS_PRI2 & 0x00FFFFFF); |
emilmont | 6:350b53afb889 | 245 | #endif |
emilmont | 6:350b53afb889 | 246 | } |
emilmont | 6:350b53afb889 | 247 | |
emilmont | 6:350b53afb889 | 248 | extern void rt_set_PSP (U32 stack); |
emilmont | 6:350b53afb889 | 249 | extern U32 rt_get_PSP (void); |
emilmont | 6:350b53afb889 | 250 | extern void os_set_env (void); |
emilmont | 6:350b53afb889 | 251 | extern void *_alloc_box (void *box_mem); |
emilmont | 6:350b53afb889 | 252 | extern int _free_box (void *box_mem, void *box); |
emilmont | 6:350b53afb889 | 253 | |
emilmont | 6:350b53afb889 | 254 | extern void rt_init_stack (P_TCB p_TCB, FUNCP task_body); |
emilmont | 6:350b53afb889 | 255 | extern void rt_ret_val (P_TCB p_TCB, U32 v0); |
emilmont | 6:350b53afb889 | 256 | extern void rt_ret_val2 (P_TCB p_TCB, U32 v0, U32 v1); |
emilmont | 6:350b53afb889 | 257 | |
emilmont | 6:350b53afb889 | 258 | extern void dbg_init (void); |
emilmont | 6:350b53afb889 | 259 | extern void dbg_task_notify (P_TCB p_tcb, BOOL create); |
emilmont | 6:350b53afb889 | 260 | extern void dbg_task_switch (U32 task_id); |
emilmont | 6:350b53afb889 | 261 | |
emilmont | 6:350b53afb889 | 262 | #ifdef DBG_MSG |
emilmont | 6:350b53afb889 | 263 | #define DBG_INIT() dbg_init() |
emilmont | 6:350b53afb889 | 264 | #define DBG_TASK_NOTIFY(p_tcb,create) if (dbg_msg) dbg_task_notify(p_tcb,create) |
emilmont | 7:80173c64d05d | 265 | #define DBG_TASK_SWITCH(task_id) if (dbg_msg && (os_tsk.new_tsk != os_tsk.run)) \ |
emilmont | 6:350b53afb889 | 266 | dbg_task_switch(task_id) |
emilmont | 6:350b53afb889 | 267 | #else |
emilmont | 6:350b53afb889 | 268 | #define DBG_INIT() |
emilmont | 6:350b53afb889 | 269 | #define DBG_TASK_NOTIFY(p_tcb,create) |
emilmont | 6:350b53afb889 | 270 | #define DBG_TASK_SWITCH(task_id) |
emilmont | 6:350b53afb889 | 271 | #endif |
emilmont | 6:350b53afb889 | 272 | |
emilmont | 6:350b53afb889 | 273 | /*---------------------------------------------------------------------------- |
emilmont | 6:350b53afb889 | 274 | * end of file |
emilmont | 6:350b53afb889 | 275 | *---------------------------------------------------------------------------*/ |
emilmont | 6:350b53afb889 | 276 |