CHENGQI YANG / SmartLabXBeeAPI2 Featured

SmartLabXBeeCore/Device/XBeePins.h@9:6e4ef3c302b4, 2016-03-30 (annotated)

Committer:
yangcq88517
Date:
Wed Mar 30 20:44:56 2016 +0000
Revision:
9:6e4ef3c302b4
Parent:
8:4da2ac03e35e 
Address.cpp static broadcast variable fix

Who changed what in which revision?

UserRevisionLine numberNew contents of line
yangcq88517 8:4da2ac03e35e 1 #ifndef UK_AC_HERTS_SMARTLAB_XBEE_XBeePins
yangcq88517 8:4da2ac03e35e 2 #define UK_AC_HERTS_SMARTLAB_XBEE_XBeePins
yangcq88517 8:4da2ac03e35e 3
yangcq88517 8:4da2ac03e35e 4 #include "Pin.h"
yangcq88517 8:4da2ac03e35e 5
yangcq88517 8:4da2ac03e35e 6 /**
yangcq88517 8:4da2ac03e35e 7 * Pin configuration information for XBee S1 modules.
yangcq88517 8:4da2ac03e35e 8 */
yangcq88517 8:4da2ac03e35e 9 class XBeePins
yangcq88517 8:4da2ac03e35e 10 {
yangcq88517 8:4da2ac03e35e 11 public:
yangcq88517 8:4da2ac03e35e 12 /** Power supply.
yangcq88517 8:4da2ac03e35e 13 * Poor power supply can lead to poor radio performance, especially if the supply voltage is not kept within tolerance or is excessively noisy. To help reduce noise, we recommend placing a 1.0 μF and 8.2 pF capacitor as near as possible to pin 1 on the XBee. If using a switching regulator for the power supply, switching frequencies above 500 kHz are preferred. Power supply ripple should be limited to a maximum 100 mV peak to peak.
yangcq88517 8:4da2ac03e35e 14 */
yangcq88517 8:4da2ac03e35e 15 static Pin * P1_VCC;
yangcq88517 8:4da2ac03e35e 16
yangcq88517 8:4da2ac03e35e 17 /// DOUT, Output, UART data out.
yangcq88517 8:4da2ac03e35e 18 static Pin * P2_DOUT;
yangcq88517 8:4da2ac03e35e 19
yangcq88517 8:4da2ac03e35e 20 /// DIN / CONFIG(active low), Input, UART data In.
yangcq88517 8:4da2ac03e35e 21 static Pin * P3_DIN_CONFIG;
yangcq88517 8:4da2ac03e35e 22
yangcq88517 8:4da2ac03e35e 23 /// DO8, Either, Digital output 8, Function is not supported at the time of this release(18/05/2015).
yangcq88517 8:4da2ac03e35e 24 static Pin * P4_DO8;
yangcq88517 8:4da2ac03e35e 25
yangcq88517 8:4da2ac03e35e 26 /// RESET(active low), Input, Module reset (reset pulse must be at least 200 ns).
yangcq88517 8:4da2ac03e35e 27 static Pin * P5_RESET;
yangcq88517 8:4da2ac03e35e 28
yangcq88517 8:4da2ac03e35e 29 /// PWM0 / RSSI, Either, PWM output 0 / RX signal strength indicator.
yangcq88517 8:4da2ac03e35e 30 static Pin * P6_RSSI_PWM0;
yangcq88517 8:4da2ac03e35e 31
yangcq88517 8:4da2ac03e35e 32 /// PWM1, Either, PWM output 1.
yangcq88517 8:4da2ac03e35e 33 static Pin * P7_PWM1;
yangcq88517 8:4da2ac03e35e 34
yangcq88517 8:4da2ac03e35e 35 /// Reserved, Do not connect.
yangcq88517 8:4da2ac03e35e 36 static Pin * P8_RESERVED;
yangcq88517 8:4da2ac03e35e 37
yangcq88517 8:4da2ac03e35e 38 /// DTR(active low) / SLEEP_RQ/ DI8, Either, Pin sleep control line or digital input 8.
yangcq88517 8:4da2ac03e35e 39 static Pin * P9_DTR_SLEEP_DIO8;
yangcq88517 8:4da2ac03e35e 40
yangcq88517 8:4da2ac03e35e 41 /// Ground.
yangcq88517 8:4da2ac03e35e 42 static Pin * P10_GND;
yangcq88517 8:4da2ac03e35e 43
yangcq88517 8:4da2ac03e35e 44 /// AD4 / DIO4, Either, Analog input 4 or digital I/O 4.
yangcq88517 8:4da2ac03e35e 45 static Pin * P11_AD4_DIO4;
yangcq88517 8:4da2ac03e35e 46
yangcq88517 8:4da2ac03e35e 47 /// CTS(active low) / DIO7 Either Clear-to-send flow control or digital I/O 7.
yangcq88517 8:4da2ac03e35e 48 static Pin * P12_CTS_DIO7;
yangcq88517 8:4da2ac03e35e 49
yangcq88517 8:4da2ac03e35e 50 /// ON / SLEEP(active low), Output, Module status indicator
yangcq88517 8:4da2ac03e35e 51 static Pin * P13_ON_SLEEP;
yangcq88517 8:4da2ac03e35e 52
yangcq88517 8:4da2ac03e35e 53 /// VREF, Input, Voltage reference for A/D inputs.
yangcq88517 8:4da2ac03e35e 54 static Pin * P14_VREF;
yangcq88517 8:4da2ac03e35e 55
yangcq88517 8:4da2ac03e35e 56 /// Associate / AD5 / DIO5, Either, Associated indicator, analog input 5 or digital I/O 5.
yangcq88517 8:4da2ac03e35e 57 static Pin * P15_ASSOCIATE_AD5_DIO5;
yangcq88517 8:4da2ac03e35e 58
yangcq88517 8:4da2ac03e35e 59 /// RTS(active low) / DIO6, Either, Request-to-send flow control, or digital I/O 6.
yangcq88517 8:4da2ac03e35e 60 static Pin * P16_RTS_AD6_DIO6;
yangcq88517 8:4da2ac03e35e 61
yangcq88517 8:4da2ac03e35e 62 /// AD3 / DIO3 Either Analog input 3 or digital I/O 3.
yangcq88517 8:4da2ac03e35e 63 static Pin * P17_AD3_DIO3;
yangcq88517 8:4da2ac03e35e 64
yangcq88517 8:4da2ac03e35e 65 /// AD2 / DIO2 Either Analog input 2 or digital I/O 2.
yangcq88517 8:4da2ac03e35e 66 static Pin * P18_AD2_DIO2;
yangcq88517 8:4da2ac03e35e 67
yangcq88517 8:4da2ac03e35e 68 /// AD1 / DIO1 Either Analog input 1 or digital I/O 1.
yangcq88517 8:4da2ac03e35e 69 static Pin * P19_AD1_DIO1;
yangcq88517 8:4da2ac03e35e 70
yangcq88517 8:4da2ac03e35e 71 /// AD0 / DIO0 Either Analog input 0, digital I/O 0.
yangcq88517 8:4da2ac03e35e 72 static Pin * P20_AD0_DIO0;
yangcq88517 8:4da2ac03e35e 73 };
yangcq88517 8:4da2ac03e35e 74
yangcq88517 8:4da2ac03e35e 75 #endif