Yuji Notsu / Mbed 2 deprecated MARMEX_Oled_GPS_6

test

Dependencies:   FatFileSystem TextLCD mbed

PowerControl/EthernetPowerControl.cpp@0:2c37ad282618, 2012-09-18 (annotated)

Committer:
y_notsu
Date:
Tue Sep 18 07:24:22 2012 +0000
Revision:
0:2c37ad282618
test

Who changed what in which revision?

UserRevisionLine numberNew contents of line
y_notsu 0:2c37ad282618 1 #include "EthernetPowerControl.h"
y_notsu 0:2c37ad282618 2
y_notsu 0:2c37ad282618 3 static void write_PHY (unsigned int PhyReg, unsigned short Value) {
y_notsu 0:2c37ad282618 4 /* Write a data 'Value' to PHY register 'PhyReg'. */
y_notsu 0:2c37ad282618 5 unsigned int tout;
y_notsu 0:2c37ad282618 6 /* Hardware MII Management for LPC176x devices. */
y_notsu 0:2c37ad282618 7 LPC_EMAC->MADR = DP83848C_DEF_ADR | PhyReg;
y_notsu 0:2c37ad282618 8 LPC_EMAC->MWTD = Value;
y_notsu 0:2c37ad282618 9
y_notsu 0:2c37ad282618 10 /* Wait utill operation completed */
y_notsu 0:2c37ad282618 11 for (tout = 0; tout < MII_WR_TOUT; tout++) {
y_notsu 0:2c37ad282618 12 if ((LPC_EMAC->MIND & MIND_BUSY) == 0) {
y_notsu 0:2c37ad282618 13 break;
y_notsu 0:2c37ad282618 14 }
y_notsu 0:2c37ad282618 15 }
y_notsu 0:2c37ad282618 16 }
y_notsu 0:2c37ad282618 17
y_notsu 0:2c37ad282618 18 static unsigned short read_PHY (unsigned int PhyReg) {
y_notsu 0:2c37ad282618 19 /* Read a PHY register 'PhyReg'. */
y_notsu 0:2c37ad282618 20 unsigned int tout, val;
y_notsu 0:2c37ad282618 21
y_notsu 0:2c37ad282618 22 LPC_EMAC->MADR = DP83848C_DEF_ADR | PhyReg;
y_notsu 0:2c37ad282618 23 LPC_EMAC->MCMD = MCMD_READ;
y_notsu 0:2c37ad282618 24
y_notsu 0:2c37ad282618 25 /* Wait until operation completed */
y_notsu 0:2c37ad282618 26 for (tout = 0; tout < MII_RD_TOUT; tout++) {
y_notsu 0:2c37ad282618 27 if ((LPC_EMAC->MIND & MIND_BUSY) == 0) {
y_notsu 0:2c37ad282618 28 break;
y_notsu 0:2c37ad282618 29 }
y_notsu 0:2c37ad282618 30 }
y_notsu 0:2c37ad282618 31 LPC_EMAC->MCMD = 0;
y_notsu 0:2c37ad282618 32 val = LPC_EMAC->MRDD;
y_notsu 0:2c37ad282618 33
y_notsu 0:2c37ad282618 34 return (val);
y_notsu 0:2c37ad282618 35 }
y_notsu 0:2c37ad282618 36
y_notsu 0:2c37ad282618 37 void EMAC_Init()
y_notsu 0:2c37ad282618 38 {
y_notsu 0:2c37ad282618 39 unsigned int tout,regv;
y_notsu 0:2c37ad282618 40 /* Power Up the EMAC controller. */
y_notsu 0:2c37ad282618 41 Peripheral_PowerUp(LPC1768_PCONP_PCENET);
y_notsu 0:2c37ad282618 42
y_notsu 0:2c37ad282618 43 LPC_PINCON->PINSEL2 = 0x50150105;
y_notsu 0:2c37ad282618 44 LPC_PINCON->PINSEL3 &= ~0x0000000F;
y_notsu 0:2c37ad282618 45 LPC_PINCON->PINSEL3 |= 0x00000005;
y_notsu 0:2c37ad282618 46
y_notsu 0:2c37ad282618 47 /* Reset all EMAC internal modules. */
y_notsu 0:2c37ad282618 48 LPC_EMAC->MAC1 = MAC1_RES_TX | MAC1_RES_MCS_TX | MAC1_RES_RX | MAC1_RES_MCS_RX |
y_notsu 0:2c37ad282618 49 MAC1_SIM_RES | MAC1_SOFT_RES;
y_notsu 0:2c37ad282618 50 LPC_EMAC->Command = CR_REG_RES | CR_TX_RES | CR_RX_RES;
y_notsu 0:2c37ad282618 51
y_notsu 0:2c37ad282618 52 /* A short delay after reset. */
y_notsu 0:2c37ad282618 53 for (tout = 100; tout; tout--);
y_notsu 0:2c37ad282618 54
y_notsu 0:2c37ad282618 55 /* Initialize MAC control registers. */
y_notsu 0:2c37ad282618 56 LPC_EMAC->MAC1 = MAC1_PASS_ALL;
y_notsu 0:2c37ad282618 57 LPC_EMAC->MAC2 = MAC2_CRC_EN | MAC2_PAD_EN;
y_notsu 0:2c37ad282618 58 LPC_EMAC->MAXF = ETH_MAX_FLEN;
y_notsu 0:2c37ad282618 59 LPC_EMAC->CLRT = CLRT_DEF;
y_notsu 0:2c37ad282618 60 LPC_EMAC->IPGR = IPGR_DEF;
y_notsu 0:2c37ad282618 61
y_notsu 0:2c37ad282618 62 /* Enable Reduced MII interface. */
y_notsu 0:2c37ad282618 63 LPC_EMAC->Command = CR_RMII | CR_PASS_RUNT_FRM;
y_notsu 0:2c37ad282618 64
y_notsu 0:2c37ad282618 65 /* Reset Reduced MII Logic. */
y_notsu 0:2c37ad282618 66 LPC_EMAC->SUPP = SUPP_RES_RMII;
y_notsu 0:2c37ad282618 67 for (tout = 100; tout; tout--);
y_notsu 0:2c37ad282618 68 LPC_EMAC->SUPP = 0;
y_notsu 0:2c37ad282618 69
y_notsu 0:2c37ad282618 70 /* Put the DP83848C in reset mode */
y_notsu 0:2c37ad282618 71 write_PHY (PHY_REG_BMCR, 0x8000);
y_notsu 0:2c37ad282618 72
y_notsu 0:2c37ad282618 73 /* Wait for hardware reset to end. */
y_notsu 0:2c37ad282618 74 for (tout = 0; tout < 0x100000; tout++) {
y_notsu 0:2c37ad282618 75 regv = read_PHY (PHY_REG_BMCR);
y_notsu 0:2c37ad282618 76 if (!(regv & 0x8000)) {
y_notsu 0:2c37ad282618 77 /* Reset complete */
y_notsu 0:2c37ad282618 78 break;
y_notsu 0:2c37ad282618 79 }
y_notsu 0:2c37ad282618 80 }
y_notsu 0:2c37ad282618 81 }
y_notsu 0:2c37ad282618 82
y_notsu 0:2c37ad282618 83
y_notsu 0:2c37ad282618 84 void PHY_PowerDown()
y_notsu 0:2c37ad282618 85 {
y_notsu 0:2c37ad282618 86 if (!Peripheral_GetStatus(LPC1768_PCONP_PCENET))
y_notsu 0:2c37ad282618 87 EMAC_Init(); //init EMAC if it is not already init'd
y_notsu 0:2c37ad282618 88
y_notsu 0:2c37ad282618 89 unsigned int regv;
y_notsu 0:2c37ad282618 90 regv = read_PHY(PHY_REG_BMCR);
y_notsu 0:2c37ad282618 91 write_PHY(PHY_REG_BMCR, regv | (1 << PHY_REG_BMCR_POWERDOWN));
y_notsu 0:2c37ad282618 92 regv = read_PHY(PHY_REG_BMCR);
y_notsu 0:2c37ad282618 93
y_notsu 0:2c37ad282618 94 //shouldn't need the EMAC now.
y_notsu 0:2c37ad282618 95 Peripheral_PowerDown(LPC1768_PCONP_PCENET);
y_notsu 0:2c37ad282618 96
y_notsu 0:2c37ad282618 97 //and turn off the PHY OSC
y_notsu 0:2c37ad282618 98 LPC_GPIO1->FIODIR |= 0x8000000;
y_notsu 0:2c37ad282618 99 LPC_GPIO1->FIOCLR = 0x8000000;
y_notsu 0:2c37ad282618 100 }
y_notsu 0:2c37ad282618 101
y_notsu 0:2c37ad282618 102 void PHY_PowerUp()
y_notsu 0:2c37ad282618 103 {
y_notsu 0:2c37ad282618 104 if (!Peripheral_GetStatus(LPC1768_PCONP_PCENET))
y_notsu 0:2c37ad282618 105 EMAC_Init(); //init EMAC if it is not already init'd
y_notsu 0:2c37ad282618 106
y_notsu 0:2c37ad282618 107 LPC_GPIO1->FIODIR |= 0x8000000;
y_notsu 0:2c37ad282618 108 LPC_GPIO1->FIOSET = 0x8000000;
y_notsu 0:2c37ad282618 109
y_notsu 0:2c37ad282618 110 //wait for osc to be stable
y_notsu 0:2c37ad282618 111 wait_ms(200);
y_notsu 0:2c37ad282618 112
y_notsu 0:2c37ad282618 113 unsigned int regv;
y_notsu 0:2c37ad282618 114 regv = read_PHY(PHY_REG_BMCR);
y_notsu 0:2c37ad282618 115 write_PHY(PHY_REG_BMCR, regv & ~(1 << PHY_REG_BMCR_POWERDOWN));
y_notsu 0:2c37ad282618 116 regv = read_PHY(PHY_REG_BMCR);
y_notsu 0:2c37ad282618 117 }
y_notsu 0:2c37ad282618 118
y_notsu 0:2c37ad282618 119 void PHY_EnergyDetect_Enable()
y_notsu 0:2c37ad282618 120 {
y_notsu 0:2c37ad282618 121 if (!Peripheral_GetStatus(LPC1768_PCONP_PCENET))
y_notsu 0:2c37ad282618 122 EMAC_Init(); //init EMAC if it is not already init'd
y_notsu 0:2c37ad282618 123
y_notsu 0:2c37ad282618 124 unsigned int regv;
y_notsu 0:2c37ad282618 125 regv = read_PHY(PHY_REG_EDCR);
y_notsu 0:2c37ad282618 126 write_PHY(PHY_REG_BMCR, regv | (1 << PHY_REG_EDCR_ENABLE));
y_notsu 0:2c37ad282618 127 regv = read_PHY(PHY_REG_EDCR);
y_notsu 0:2c37ad282618 128 }
y_notsu 0:2c37ad282618 129
y_notsu 0:2c37ad282618 130 void PHY_EnergyDetect_Disable()
y_notsu 0:2c37ad282618 131 {
y_notsu 0:2c37ad282618 132 if (!Peripheral_GetStatus(LPC1768_PCONP_PCENET))
y_notsu 0:2c37ad282618 133 EMAC_Init(); //init EMAC if it is not already init'd
y_notsu 0:2c37ad282618 134 unsigned int regv;
y_notsu 0:2c37ad282618 135 regv = read_PHY(PHY_REG_EDCR);
y_notsu 0:2c37ad282618 136 write_PHY(PHY_REG_BMCR, regv & ~(1 << PHY_REG_EDCR_ENABLE));
y_notsu 0:2c37ad282618 137 regv = read_PHY(PHY_REG_EDCR);
y_notsu 0:2c37ad282618 138 }