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EthernetPowerControl.cpp
00001 #include "EthernetPowerControl.h" 00002 00003 static void write_PHY (unsigned int PhyReg, unsigned short Value) { 00004 /* Write a data 'Value' to PHY register 'PhyReg'. */ 00005 unsigned int tout; 00006 /* Hardware MII Management for LPC176x devices. */ 00007 LPC_EMAC->MADR = DP83848C_DEF_ADR | PhyReg; 00008 LPC_EMAC->MWTD = Value; 00009 00010 /* Wait utill operation completed */ 00011 for (tout = 0; tout < MII_WR_TOUT; tout++) { 00012 if ((LPC_EMAC->MIND & MIND_BUSY) == 0) { 00013 break; 00014 } 00015 } 00016 } 00017 00018 static unsigned short read_PHY (unsigned int PhyReg) { 00019 /* Read a PHY register 'PhyReg'. */ 00020 unsigned int tout, val; 00021 00022 LPC_EMAC->MADR = DP83848C_DEF_ADR | PhyReg; 00023 LPC_EMAC->MCMD = MCMD_READ; 00024 00025 /* Wait until operation completed */ 00026 for (tout = 0; tout < MII_RD_TOUT; tout++) { 00027 if ((LPC_EMAC->MIND & MIND_BUSY) == 0) { 00028 break; 00029 } 00030 } 00031 LPC_EMAC->MCMD = 0; 00032 val = LPC_EMAC->MRDD; 00033 00034 return (val); 00035 } 00036 00037 void EMAC_Init() 00038 { 00039 unsigned int tout,regv; 00040 /* Power Up the EMAC controller. */ 00041 Peripheral_PowerUp(LPC1768_PCONP_PCENET); 00042 00043 LPC_PINCON->PINSEL2 = 0x50150105; 00044 LPC_PINCON->PINSEL3 &= ~0x0000000F; 00045 LPC_PINCON->PINSEL3 |= 0x00000005; 00046 00047 /* Reset all EMAC internal modules. */ 00048 LPC_EMAC->MAC1 = MAC1_RES_TX | MAC1_RES_MCS_TX | MAC1_RES_RX | MAC1_RES_MCS_RX | 00049 MAC1_SIM_RES | MAC1_SOFT_RES; 00050 LPC_EMAC->Command = CR_REG_RES | CR_TX_RES | CR_RX_RES; 00051 00052 /* A short delay after reset. */ 00053 for (tout = 100; tout; tout--); 00054 00055 /* Initialize MAC control registers. */ 00056 LPC_EMAC->MAC1 = MAC1_PASS_ALL; 00057 LPC_EMAC->MAC2 = MAC2_CRC_EN | MAC2_PAD_EN; 00058 LPC_EMAC->MAXF = ETH_MAX_FLEN; 00059 LPC_EMAC->CLRT = CLRT_DEF; 00060 LPC_EMAC->IPGR = IPGR_DEF; 00061 00062 /* Enable Reduced MII interface. */ 00063 LPC_EMAC->Command = CR_RMII | CR_PASS_RUNT_FRM; 00064 00065 /* Reset Reduced MII Logic. */ 00066 LPC_EMAC->SUPP = SUPP_RES_RMII; 00067 for (tout = 100; tout; tout--); 00068 LPC_EMAC->SUPP = 0; 00069 00070 /* Put the DP83848C in reset mode */ 00071 write_PHY (PHY_REG_BMCR, 0x8000); 00072 00073 /* Wait for hardware reset to end. */ 00074 for (tout = 0; tout < 0x100000; tout++) { 00075 regv = read_PHY (PHY_REG_BMCR); 00076 if (!(regv & 0x8000)) { 00077 /* Reset complete */ 00078 break; 00079 } 00080 } 00081 } 00082 00083 00084 void PHY_PowerDown() 00085 { 00086 if (!Peripheral_GetStatus(LPC1768_PCONP_PCENET)) 00087 EMAC_Init(); //init EMAC if it is not already init'd 00088 00089 unsigned int regv; 00090 regv = read_PHY(PHY_REG_BMCR); 00091 write_PHY(PHY_REG_BMCR, regv | (1 << PHY_REG_BMCR_POWERDOWN)); 00092 regv = read_PHY(PHY_REG_BMCR); 00093 00094 //shouldn't need the EMAC now. 00095 Peripheral_PowerDown(LPC1768_PCONP_PCENET); 00096 00097 //and turn off the PHY OSC 00098 LPC_GPIO1->FIODIR |= 0x8000000; 00099 LPC_GPIO1->FIOCLR = 0x8000000; 00100 } 00101 00102 void PHY_PowerUp() 00103 { 00104 if (!Peripheral_GetStatus(LPC1768_PCONP_PCENET)) 00105 EMAC_Init(); //init EMAC if it is not already init'd 00106 00107 LPC_GPIO1->FIODIR |= 0x8000000; 00108 LPC_GPIO1->FIOSET = 0x8000000; 00109 00110 //wait for osc to be stable 00111 wait_ms(200); 00112 00113 unsigned int regv; 00114 regv = read_PHY(PHY_REG_BMCR); 00115 write_PHY(PHY_REG_BMCR, regv & ~(1 << PHY_REG_BMCR_POWERDOWN)); 00116 regv = read_PHY(PHY_REG_BMCR); 00117 } 00118 00119 void PHY_EnergyDetect_Enable() 00120 { 00121 if (!Peripheral_GetStatus(LPC1768_PCONP_PCENET)) 00122 EMAC_Init(); //init EMAC if it is not already init'd 00123 00124 unsigned int regv; 00125 regv = read_PHY(PHY_REG_EDCR); 00126 write_PHY(PHY_REG_BMCR, regv | (1 << PHY_REG_EDCR_ENABLE)); 00127 regv = read_PHY(PHY_REG_EDCR); 00128 } 00129 00130 void PHY_EnergyDetect_Disable() 00131 { 00132 if (!Peripheral_GetStatus(LPC1768_PCONP_PCENET)) 00133 EMAC_Init(); //init EMAC if it is not already init'd 00134 unsigned int regv; 00135 regv = read_PHY(PHY_REG_EDCR); 00136 write_PHY(PHY_REG_BMCR, regv & ~(1 << PHY_REG_EDCR_ENABLE)); 00137 regv = read_PHY(PHY_REG_EDCR); 00138 }
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