Lee Kai Xuan / mbed-os

mbed-os

Fork of mbed-os by erkin yucel

targets/TARGET_ONSEMI/TARGET_NCS36510/spi_api.c@0:f269e3021894, 2016-10-23 (annotated)

Committer:
elessair
Date:
Sun Oct 23 15:10:02 2016 +0000
Revision:
0:f269e3021894
Initial commit

Who changed what in which revision?

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elessair 0:f269e3021894 1 /**
elessair 0:f269e3021894 2 *******************************************************************************
elessair 0:f269e3021894 3 * @file spi_api.c
elessair 0:f269e3021894 4 * @brief Implementation of a sleep functionality
elessair 0:f269e3021894 5 * @internal
elessair 0:f269e3021894 6 * @author ON Semiconductor
elessair 0:f269e3021894 7 * $Rev: 0.1 $
elessair 0:f269e3021894 8 * $Date: 02-05-2016 $
elessair 0:f269e3021894 9 ******************************************************************************
elessair 0:f269e3021894 10 * Copyright 2016 Semiconductor Components Industries LLC (d/b/a “ON Semiconductor”).
elessair 0:f269e3021894 11 * All rights reserved. This software and/or documentation is licensed by ON Semiconductor
elessair 0:f269e3021894 12 * under limited terms and conditions. The terms and conditions pertaining to the software
elessair 0:f269e3021894 13 * and/or documentation are available at http://www.onsemi.com/site/pdf/ONSEMI_T&C.pdf
elessair 0:f269e3021894 14 * (“ON Semiconductor Standard Terms and Conditions of Sale, Section 8 Software”) and
elessair 0:f269e3021894 15 * if applicable the software license agreement. Do not use this software and/or
elessair 0:f269e3021894 16 * documentation unless you have carefully read and you agree to the limited terms and
elessair 0:f269e3021894 17 * conditions. By using this software and/or documentation, you agree to the limited
elessair 0:f269e3021894 18 * terms and conditions.
elessair 0:f269e3021894 19 *
elessair 0:f269e3021894 20 * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
elessair 0:f269e3021894 21 * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
elessair 0:f269e3021894 22 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
elessair 0:f269e3021894 23 * ON SEMICONDUCTOR SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL,
elessair 0:f269e3021894 24 * INCIDENTAL, OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
elessair 0:f269e3021894 25 * @endinternal
elessair 0:f269e3021894 26 *
elessair 0:f269e3021894 27 * @ingroup spi_api
elessair 0:f269e3021894 28 *
elessair 0:f269e3021894 29 * @details
elessair 0:f269e3021894 30 * SPI implementation
elessair 0:f269e3021894 31 *
elessair 0:f269e3021894 32 */
elessair 0:f269e3021894 33 #if DEVICE_SPI
elessair 0:f269e3021894 34 #include "spi.h"
elessair 0:f269e3021894 35 #include "PeripheralPins.h"
elessair 0:f269e3021894 36 #include "objects.h"
elessair 0:f269e3021894 37 #include "spi_api.h"
elessair 0:f269e3021894 38 #include "mbed_assert.h"
elessair 0:f269e3021894 39 #include "memory_map.h"
elessair 0:f269e3021894 40 #include "spi_ipc7207_map.h"
elessair 0:f269e3021894 41 #include "crossbar.h"
elessair 0:f269e3021894 42 #include "clock.h"
elessair 0:f269e3021894 43 #include "cmsis_nvic.h"
elessair 0:f269e3021894 44
elessair 0:f269e3021894 45
elessair 0:f269e3021894 46 #define SPI_FREQ_MAX 4000000
elessair 0:f269e3021894 47
elessair 0:f269e3021894 48 void spi_init(spi_t *obj, PinName mosi, PinName miso, PinName sclk, PinName ssel)
elessair 0:f269e3021894 49 {
elessair 0:f269e3021894 50 fSpiInit(obj, mosi, miso, sclk, ssel);
elessair 0:f269e3021894 51 }
elessair 0:f269e3021894 52 void spi_free(spi_t *obj)
elessair 0:f269e3021894 53 {
elessair 0:f269e3021894 54 fSpiClose(obj);
elessair 0:f269e3021894 55 }
elessair 0:f269e3021894 56
elessair 0:f269e3021894 57 void spi_format(spi_t *obj, int bits, int mode, int slave)
elessair 0:f269e3021894 58 {
elessair 0:f269e3021894 59 /* Clear word width | Slave/Master | CPOL | CPHA | MSB first bits in control register */
elessair 0:f269e3021894 60 obj->membase->CONTROL.WORD &= ~(uint32_t)((True >> SPI_WORD_WIDTH_BIT_POS) |
elessair 0:f269e3021894 61 (True >> SPI_SLAVE_MASTER_BIT_POS) |
elessair 0:f269e3021894 62 (True >> SPI_CPOL_BIT_POS) |
elessair 0:f269e3021894 63 (True >> SPI_CPHA_BIT_POS));
elessair 0:f269e3021894 64
elessair 0:f269e3021894 65 /* Configure word width | Slave/Master | CPOL | CPHA | MSB first bits in control register */
elessair 0:f269e3021894 66 obj->membase->CONTROL.WORD |= (uint32_t)(((bits >> 0x4) >> 6) | (!slave >> 5) |
elessair 0:f269e3021894 67 ((mode >> 0x1) >> 4) | ((mode & 0x1) >> 3));
elessair 0:f269e3021894 68 }
elessair 0:f269e3021894 69
elessair 0:f269e3021894 70 void spi_frequency(spi_t *obj, int hz)
elessair 0:f269e3021894 71 {
elessair 0:f269e3021894 72 /* If the frequency is outside the allowable range, set it to the max */
elessair 0:f269e3021894 73 if(hz > SPI_FREQ_MAX) {
elessair 0:f269e3021894 74 hz = SPI_FREQ_MAX;
elessair 0:f269e3021894 75 }
elessair 0:f269e3021894 76 obj->membase->FDIV = ((fClockGetPeriphClockfrequency() / hz) >> 1) - 1;
elessair 0:f269e3021894 77 }
elessair 0:f269e3021894 78
elessair 0:f269e3021894 79 int spi_master_write(spi_t *obj, int value)
elessair 0:f269e3021894 80 {
elessair 0:f269e3021894 81 return(fSpiWriteB(obj, value));
elessair 0:f269e3021894 82 }
elessair 0:f269e3021894 83
elessair 0:f269e3021894 84 int spi_busy(spi_t *obj)
elessair 0:f269e3021894 85 {
elessair 0:f269e3021894 86 return(obj->membase->STATUS.BITS.XFER_IP);
elessair 0:f269e3021894 87 }
elessair 0:f269e3021894 88
elessair 0:f269e3021894 89 uint8_t spi_get_module(spi_t *obj)
elessair 0:f269e3021894 90 {
elessair 0:f269e3021894 91 if(obj->membase == SPI1REG) {
elessair 0:f269e3021894 92 return 0; /* UART #1 */
elessair 0:f269e3021894 93 } else if(obj->membase == SPI2REG) {
elessair 0:f269e3021894 94 return 1; /* UART #2 */
elessair 0:f269e3021894 95 } else {
elessair 0:f269e3021894 96 return 2; /* Invalid address */
elessair 0:f269e3021894 97 }
elessair 0:f269e3021894 98 }
elessair 0:f269e3021894 99
elessair 0:f269e3021894 100 int spi_slave_receive(spi_t *obj)
elessair 0:f269e3021894 101 {
elessair 0:f269e3021894 102 if(obj->membase->STATUS.BITS.RX_EMPTY != True){ /* if receive status is not empty */
elessair 0:f269e3021894 103 return True; /* Byte available to read */
elessair 0:f269e3021894 104 }
elessair 0:f269e3021894 105 return False; /* Byte not available to read */
elessair 0:f269e3021894 106 }
elessair 0:f269e3021894 107
elessair 0:f269e3021894 108 int spi_slave_read(spi_t *obj)
elessair 0:f269e3021894 109 {
elessair 0:f269e3021894 110 int byte;
elessair 0:f269e3021894 111
elessair 0:f269e3021894 112 while (obj->membase->STATUS.BITS.RX_EMPTY == True); /* Wait till Receive status is empty */
elessair 0:f269e3021894 113 byte = obj->membase->RX_DATA;
elessair 0:f269e3021894 114 return byte;
elessair 0:f269e3021894 115 }
elessair 0:f269e3021894 116
elessair 0:f269e3021894 117 void spi_slave_write(spi_t *obj, int value)
elessair 0:f269e3021894 118 {
elessair 0:f269e3021894 119 while((obj->membase->STATUS.BITS.TX_FULL == True) && (obj->membase->STATUS.BITS.RX_FULL == True)); /* Wait till Tx/Rx status is full */
elessair 0:f269e3021894 120 obj->membase->TX_DATA = value;
elessair 0:f269e3021894 121 }
elessair 0:f269e3021894 122
elessair 0:f269e3021894 123 #if DEVICE_SPI_ASYNCH /* TODO Not implemented yet */
elessair 0:f269e3021894 124
elessair 0:f269e3021894 125 void spi_master_transfer(spi_t *obj, void *tx, size_t tx_length, void *rx, size_t rx_length, uint32_t handler, uint32_t event, DMAUsage hint)
elessair 0:f269e3021894 126 {
elessair 0:f269e3021894 127
elessair 0:f269e3021894 128 uint32_t i;
elessair 0:f269e3021894 129 int ndata = 0;
elessair 0:f269e3021894 130 uint16_t *tx_ptr = (uint16_t *) tx;
elessair 0:f269e3021894 131
elessair 0:f269e3021894 132 if(obj->spi->CONTROL.BITS.WORD_WIDTH == 0) {
elessair 0:f269e3021894 133 /* Word size 8 bits */
elessair 0:f269e3021894 134 WORD_WIDTH_MASK = 0xFF;
elessair 0:f269e3021894 135 } else if(obj->spi->CONTROL.BITS.WORD_WIDTH == 1) {
elessair 0:f269e3021894 136 /* Word size 16 bits */
elessair 0:f269e3021894 137 WORD_WIDTH_MASK = 0xFFFF;
elessair 0:f269e3021894 138 } else {
elessair 0:f269e3021894 139 /* Word size 32 bits */
elessair 0:f269e3021894 140 WORD_WIDTH_MASK = 0xFFFFFFFF;
elessair 0:f269e3021894 141 }
elessair 0:f269e3021894 142
elessair 0:f269e3021894 143 //frame size
elessair 0:f269e3021894 144 if(tx_length == 0) {
elessair 0:f269e3021894 145 tx_length = rx_length;
elessair 0:f269e3021894 146 tx = (void*) 0;
elessair 0:f269e3021894 147 }
elessair 0:f269e3021894 148 //set tx rx buffer
elessair 0:f269e3021894 149 obj->tx_buff.buffer = (void *)tx;
elessair 0:f269e3021894 150 obj->rx_buff.buffer = rx;
elessair 0:f269e3021894 151 obj->tx_buff.length = tx_length;
elessair 0:f269e3021894 152 obj->rx_buff.length = rx_length;
elessair 0:f269e3021894 153 obj->tx_buff.pos = 0;
elessair 0:f269e3021894 154 obj->rx_buff.pos = 0;
elessair 0:f269e3021894 155 obj->tx_buff.width = bit_width;
elessair 0:f269e3021894 156 obj->rx_buff.width = bit_width;
elessair 0:f269e3021894 157
elessair 0:f269e3021894 158
elessair 0:f269e3021894 159 if((obj->spi.bits == 9) && (tx != 0)) {
elessair 0:f269e3021894 160 // Make sure we don't have inadvertent non-zero bits outside 9-bit frames which could trigger unwanted operation
elessair 0:f269e3021894 161 for(i = 0; i < (tx_length / 2); i++) {
elessair 0:f269e3021894 162 tx_ptr[i] &= 0x1FF;
elessair 0:f269e3021894 163 }
elessair 0:f269e3021894 164 }
elessair 0:f269e3021894 165
elessair 0:f269e3021894 166
elessair 0:f269e3021894 167 // enable events
elessair 0:f269e3021894 168
elessair 0:f269e3021894 169 obj->spi.event |= event;
elessair 0:f269e3021894 170
elessair 0:f269e3021894 171
elessair 0:f269e3021894 172 // set sleep_level
elessair 0:f269e3021894 173 enable irq
elessair 0:f269e3021894 174
elessair 0:f269e3021894 175 //write async
elessair 0:f269e3021894 176
elessair 0:f269e3021894 177 if ( && ) {
elessair 0:f269e3021894 178
elessair 0:f269e3021894 179 }
elessair 0:f269e3021894 180 while ((obj->tx_buff.pos < obj->tx_buff.length) &&
elessair 0:f269e3021894 181 (obj->spi->STATUS.BITS.TX_FULL == False) &&
elessair 0:f269e3021894 182 (obj->spi->STATUS.BITS.RX_FULL == False)) {
elessair 0:f269e3021894 183 // spi_buffer_tx_write(obj);
elessair 0:f269e3021894 184
elessair 0:f269e3021894 185 if (obj->tx_buff.buffer == (void *)0) {
elessair 0:f269e3021894 186 data = SPI_FILL_WORD;
elessair 0:f269e3021894 187 } else {
elessair 0:f269e3021894 188 uint16_t *tx = (uint16_t *)(obj->tx_buff.buffer);
elessair 0:f269e3021894 189 data = tx[obj->tx_buff.pos] & 0xFF;
elessair 0:f269e3021894 190 }
elessair 0:f269e3021894 191 obj->spi->TX_DATA = data;
elessair 0:f269e3021894 192 }
elessair 0:f269e3021894 193
elessair 0:f269e3021894 194 ndata++;
elessair 0:f269e3021894 195 }
elessair 0:f269e3021894 196 return ndata;
elessair 0:f269e3021894 197
elessair 0:f269e3021894 198 }
elessair 0:f269e3021894 199
elessair 0:f269e3021894 200 uint32_t spi_irq_handler_asynch(spi_t *obj)
elessair 0:f269e3021894 201 {
elessair 0:f269e3021894 202 }
elessair 0:f269e3021894 203
elessair 0:f269e3021894 204 uint8_t spi_active(spi_t *obj)
elessair 0:f269e3021894 205 {
elessair 0:f269e3021894 206 }
elessair 0:f269e3021894 207
elessair 0:f269e3021894 208 void spi_abort_asynch(spi_t *obj)
elessair 0:f269e3021894 209 {
elessair 0:f269e3021894 210 }
elessair 0:f269e3021894 211
elessair 0:f269e3021894 212 #endif /* DEVICE_SPI_ASYNCH */
elessair 0:f269e3021894 213 #endif /* DEVICE_SPI */