Lee Kai Xuan / mbed-os

mbed-os

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targets/TARGET_ONSEMI/TARGET_NCS36510/sleep.c@0:f269e3021894, 2016-10-23 (annotated)

Committer:
elessair
Date:
Sun Oct 23 15:10:02 2016 +0000
Revision:
0:f269e3021894
Initial commit

Who changed what in which revision?

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elessair 0:f269e3021894 1 /**
elessair 0:f269e3021894 2 *******************************************************************************
elessair 0:f269e3021894 3 * @file sleep.c
elessair 0:f269e3021894 4 * @brief Implementation of an sleep functionality
elessair 0:f269e3021894 5 * @internal
elessair 0:f269e3021894 6 * @author ON Semiconductor
elessair 0:f269e3021894 7 * $Rev: 0.1 $
elessair 0:f269e3021894 8 * $Date: 01-21-2016 $
elessair 0:f269e3021894 9 ******************************************************************************
elessair 0:f269e3021894 10 * Copyright 2016 Semiconductor Components Industries LLC (d/b/a “ON Semiconductor”).
elessair 0:f269e3021894 11 * All rights reserved. This software and/or documentation is licensed by ON Semiconductor
elessair 0:f269e3021894 12 * under limited terms and conditions. The terms and conditions pertaining to the software
elessair 0:f269e3021894 13 * and/or documentation are available at http://www.onsemi.com/site/pdf/ONSEMI_T&C.pdf
elessair 0:f269e3021894 14 * (“ON Semiconductor Standard Terms and Conditions of Sale, Section 8 Software”) and
elessair 0:f269e3021894 15 * if applicable the software license agreement. Do not use this software and/or
elessair 0:f269e3021894 16 * documentation unless you have carefully read and you agree to the limited terms and
elessair 0:f269e3021894 17 * conditions. By using this software and/or documentation, you agree to the limited
elessair 0:f269e3021894 18 * terms and conditions.
elessair 0:f269e3021894 19 *
elessair 0:f269e3021894 20 * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
elessair 0:f269e3021894 21 * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
elessair 0:f269e3021894 22 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
elessair 0:f269e3021894 23 * ON SEMICONDUCTOR SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL,
elessair 0:f269e3021894 24 * INCIDENTAL, OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
elessair 0:f269e3021894 25 * @endinternal
elessair 0:f269e3021894 26 *
elessair 0:f269e3021894 27 * @ingroup sleep
elessair 0:f269e3021894 28 *
elessair 0:f269e3021894 29 * @details
elessair 0:f269e3021894 30 * Sleep implementation
elessair 0:f269e3021894 31 *
elessair 0:f269e3021894 32 */
elessair 0:f269e3021894 33 #if DEVICE_SLEEP
elessair 0:f269e3021894 34 #include "sleep.h"
elessair 0:f269e3021894 35 #include "sleep_api.h"
elessair 0:f269e3021894 36 #include "cmsis_nvic.h"
elessair 0:f269e3021894 37
elessair 0:f269e3021894 38 #define ENABLE (uint8_t)0x01
elessair 0:f269e3021894 39 #define DISABLE (uint8_t)0x00
elessair 0:f269e3021894 40 #define MAC_LUT_SIZE (uint8_t)96
elessair 0:f269e3021894 41
elessair 0:f269e3021894 42 #define portNVIC_SYSTICK_CTRL_REG ( * ( ( volatile unsigned long * ) 0xe000e010 ) )
elessair 0:f269e3021894 43 #define portNVIC_SYSTICK_CLK_BIT ( 1UL << 2UL )
elessair 0:f269e3021894 44 #define portNVIC_SYSTICK_INT_BIT ( 1UL << 1UL )
elessair 0:f269e3021894 45 #define portNVIC_SYSTICK_ENABLE_BIT ( 1UL << 0UL )
elessair 0:f269e3021894 46
elessair 0:f269e3021894 47 void sleep(void)
elessair 0:f269e3021894 48 {
elessair 0:f269e3021894 49 /** Unset SLEEPDEEP (SCR) and COMA to select sleep mode */
elessair 0:f269e3021894 50 SCB->SCR &= ~SCB_SCR_SLEEPDEEP_Msk;
elessair 0:f269e3021894 51 PMUREG->CONTROL.BITS.ENCOMA = DISABLE;
elessair 0:f269e3021894 52
elessair 0:f269e3021894 53 /* Enter into sleep mode */
elessair 0:f269e3021894 54 __ISB();
elessair 0:f269e3021894 55 __WFI();
elessair 0:f269e3021894 56 }
elessair 0:f269e3021894 57
elessair 0:f269e3021894 58 void deepsleep(void)
elessair 0:f269e3021894 59 {
elessair 0:f269e3021894 60 /** Set SLEEPDEEP (SCR) and unset COMA to select deep sleep mode */
elessair 0:f269e3021894 61 SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk;
elessair 0:f269e3021894 62 PMUREG->CONTROL.BITS.ENCOMA = DISABLE;
elessair 0:f269e3021894 63
elessair 0:f269e3021894 64 /** Enter into deep sleep mode */
elessair 0:f269e3021894 65 __ISB();
elessair 0:f269e3021894 66 __WFI();
elessair 0:f269e3021894 67
elessair 0:f269e3021894 68 /** Wait for the external 32MHz to be power-ed up & running
elessair 0:f269e3021894 69 * Re-power down the 32MHz internal osc
elessair 0:f269e3021894 70 */
elessair 0:f269e3021894 71 while (!CLOCKREG->CSR.BITS.XTAL32M);
elessair 0:f269e3021894 72 PMUREG->CONTROL.BITS.INT32M = 1;
elessair 0:f269e3021894 73 }
elessair 0:f269e3021894 74
elessair 0:f269e3021894 75 void coma(void)
elessair 0:f269e3021894 76 {
elessair 0:f269e3021894 77 /** Set SLEEPDEEP (SCR) and set COMA to select coma mode */
elessair 0:f269e3021894 78 SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk;
elessair 0:f269e3021894 79 PMUREG->CONTROL.BITS.ENCOMA = ENABLE;
elessair 0:f269e3021894 80
elessair 0:f269e3021894 81 /* TODO Wait till MAC is idle */
elessair 0:f269e3021894 82 // while((MACHWREG->SEQUENCER == MACHW_SEQ_TX) || (MACHWREG->SEQUENCER == MACHW_SEQ_ED) || (MACHWREG->SEQUENCER == MACHW_SEQ_CCA));
elessair 0:f269e3021894 83
elessair 0:f269e3021894 84 /* TODO Back up MAC_LUT *
elessair 0:f269e3021894 85 uint8_t MAC_LUT_BackUp[MAC_LUT_SIZE];
elessair 0:f269e3021894 86 fMacBackupFrameStoreLUT(MAC_LUT_BackUp); */
elessair 0:f269e3021894 87
elessair 0:f269e3021894 88 /* Disable UART 1 & 2 FIFO during coma*/
elessair 0:f269e3021894 89 UART1REG->FCR.WORD &= ~(FCR_FIFO_ENABLE);
elessair 0:f269e3021894 90 UART2REG->FCR.WORD &= ~(FCR_FIFO_ENABLE);
elessair 0:f269e3021894 91
elessair 0:f269e3021894 92 /** Enter into coma mode */
elessair 0:f269e3021894 93 __ISB();
elessair 0:f269e3021894 94 __WFI();
elessair 0:f269e3021894 95
elessair 0:f269e3021894 96 /** Wait for the external 32MHz to be power-ed up & running
elessair 0:f269e3021894 97 * Re-power down the 32MHz internal osc
elessair 0:f269e3021894 98 */
elessair 0:f269e3021894 99 while (!CLOCKREG->CSR.BITS.XTAL32M);
elessair 0:f269e3021894 100 PMUREG->CONTROL.BITS.INT32M = 1;
elessair 0:f269e3021894 101
elessair 0:f269e3021894 102 /** Trim the oscillators */
elessair 0:f269e3021894 103 if ((TRIMREG->TRIM_32K_EXT & 0xFFFF0000) != 0xFFFF0000) {
elessair 0:f269e3021894 104 CLOCKREG->TRIM_32K_EXT = TRIMREG->TRIM_32K_EXT;
elessair 0:f269e3021894 105 }
elessair 0:f269e3021894 106 if ((TRIMREG->TRIM_32M_EXT & 0xFFFF0000) != 0xFFFF0000) {
elessair 0:f269e3021894 107 CLOCKREG->TRIM_32M_EXT = TRIMREG->TRIM_32M_EXT;
elessair 0:f269e3021894 108 }
elessair 0:f269e3021894 109
elessair 0:f269e3021894 110 /* Enable UART 1 & 2 FIFO */
elessair 0:f269e3021894 111 UART1REG->FCR.WORD |= FCR_FIFO_ENABLE;
elessair 0:f269e3021894 112 UART2REG->FCR.WORD |= FCR_FIFO_ENABLE;
elessair 0:f269e3021894 113
elessair 0:f269e3021894 114 /* TODO Restore MAC_LUT *
elessair 0:f269e3021894 115 fMacRestoreFrameStoreLUT(MAC_LUT_BackUp); */
elessair 0:f269e3021894 116 }
elessair 0:f269e3021894 117
elessair 0:f269e3021894 118 #endif /* DEVICE_SLEEP */