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mbed-os

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targets/TARGET_ONSEMI/TARGET_NCS36510/clock_map.h@0:f269e3021894, 2016-10-23 (annotated)

Committer:
elessair
Date:
Sun Oct 23 15:10:02 2016 +0000
Revision:
0:f269e3021894
Initial commit

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elessair 0:f269e3021894 1 /**
elessair 0:f269e3021894 2 ******************************************************************************
elessair 0:f269e3021894 3 * @file clock_map.h
elessair 0:f269e3021894 4 * @brief CLOCK hw module register map
elessair 0:f269e3021894 5 * @internal
elessair 0:f269e3021894 6 * @author ON Semiconductor
elessair 0:f269e3021894 7 * $Rev: 2848 $
elessair 0:f269e3021894 8 * $Date: 2014-04-01 22:48:18 +0530 (Tue, 01 Apr 2014) $
elessair 0:f269e3021894 9 ******************************************************************************
elessair 0:f269e3021894 10 * Copyright 2016 Semiconductor Components Industries LLC (d/b/a “ON Semiconductor”).
elessair 0:f269e3021894 11 * All rights reserved. This software and/or documentation is licensed by ON Semiconductor
elessair 0:f269e3021894 12 * under limited terms and conditions. The terms and conditions pertaining to the software
elessair 0:f269e3021894 13 * and/or documentation are available at http://www.onsemi.com/site/pdf/ONSEMI_T&C.pdf
elessair 0:f269e3021894 14 * (“ON Semiconductor Standard Terms and Conditions of Sale, Section 8 Software”) and
elessair 0:f269e3021894 15 * if applicable the software license agreement. Do not use this software and/or
elessair 0:f269e3021894 16 * documentation unless you have carefully read and you agree to the limited terms and
elessair 0:f269e3021894 17 * conditions. By using this software and/or documentation, you agree to the limited
elessair 0:f269e3021894 18 * terms and conditions.
elessair 0:f269e3021894 19 *
elessair 0:f269e3021894 20 * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
elessair 0:f269e3021894 21 * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
elessair 0:f269e3021894 22 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
elessair 0:f269e3021894 23 * ON SEMICONDUCTOR SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL,
elessair 0:f269e3021894 24 * INCIDENTAL, OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
elessair 0:f269e3021894 25 * @endinternal
elessair 0:f269e3021894 26 *
elessair 0:f269e3021894 27 * @ingroup clock
elessair 0:f269e3021894 28 *
elessair 0:f269e3021894 29 * @details
elessair 0:f269e3021894 30 */
elessair 0:f269e3021894 31
elessair 0:f269e3021894 32 #ifndef CLOCK_MAP_H_
elessair 0:f269e3021894 33 #define CLOCK_MAP_H_
elessair 0:f269e3021894 34
elessair 0:f269e3021894 35 /*************************************************************************************************
elessair 0:f269e3021894 36 * *
elessair 0:f269e3021894 37 * Header files *
elessair 0:f269e3021894 38 * *
elessair 0:f269e3021894 39 *************************************************************************************************/
elessair 0:f269e3021894 40
elessair 0:f269e3021894 41 #include "architecture.h"
elessair 0:f269e3021894 42
elessair 0:f269e3021894 43 /**************************************************************************************************
elessair 0:f269e3021894 44 * *
elessair 0:f269e3021894 45 * Type definitions *
elessair 0:f269e3021894 46 * *
elessair 0:f269e3021894 47 **************************************************************************************************/
elessair 0:f269e3021894 48
elessair 0:f269e3021894 49 /** Clock control HW structure overlay */
elessair 0:f269e3021894 50 typedef struct {
elessair 0:f269e3021894 51 union {
elessair 0:f269e3021894 52 struct {
elessair 0:f269e3021894 53 __IO uint32_t OSC_SEL:1;
elessair 0:f269e3021894 54 __IO uint32_t PAD0:1;
elessair 0:f269e3021894 55 __IO uint32_t CAL32K:1;
elessair 0:f269e3021894 56 __IO uint32_t CAL32M:1;
elessair 0:f269e3021894 57 __IO uint32_t RTCEN:1;
elessair 0:f269e3021894 58 } BITS;
elessair 0:f269e3021894 59 __IO uint32_t WORD;
elessair 0:f269e3021894 60 } CCR; /**< 0x4001B000 Clock control register */
elessair 0:f269e3021894 61 union {
elessair 0:f269e3021894 62 struct {
elessair 0:f269e3021894 63 __I uint32_t XTAL32M:1;
elessair 0:f269e3021894 64 __I uint32_t XTAL32K:1;
elessair 0:f269e3021894 65 __I uint32_t CAL32K:1;
elessair 0:f269e3021894 66 __I uint32_t DONE32K:1;
elessair 0:f269e3021894 67 __I uint32_t CAL32MFAIL:1;
elessair 0:f269e3021894 68 __I uint32_t CAL32MDONE:1;
elessair 0:f269e3021894 69 } BITS;
elessair 0:f269e3021894 70 __I uint32_t WORD;
elessair 0:f269e3021894 71 } CSR; /**< 0x4001B004 Clock status register */
elessair 0:f269e3021894 72 union {
elessair 0:f269e3021894 73 struct {
elessair 0:f269e3021894 74 __IO uint32_t IE32K:1;
elessair 0:f269e3021894 75 __IO uint32_t IE32M:1;
elessair 0:f269e3021894 76 } BITS;
elessair 0:f269e3021894 77 __IO uint32_t WORD;
elessair 0:f269e3021894 78 } IER; /**< 0x4001B008 Interrup enable register */
elessair 0:f269e3021894 79 __IO uint32_t ICR; /**< 0x4001B00C Interrupt clear register */
elessair 0:f269e3021894 80 union {
elessair 0:f269e3021894 81 struct {
elessair 0:f269e3021894 82 __IO uint32_t TIMER0:1;
elessair 0:f269e3021894 83 __IO uint32_t TIMER1:1;
elessair 0:f269e3021894 84 __IO uint32_t TIMER2:1;
elessair 0:f269e3021894 85 __IO uint32_t PAD0:2;
elessair 0:f269e3021894 86 __IO uint32_t UART1:1;
elessair 0:f269e3021894 87 __IO uint32_t SPI:1;
elessair 0:f269e3021894 88 __IO uint32_t I2C:1;
elessair 0:f269e3021894 89 __IO uint32_t UART2:1;
elessair 0:f269e3021894 90 __IO uint32_t PAD1:1;
elessair 0:f269e3021894 91 __IO uint32_t WDOG:1;
elessair 0:f269e3021894 92 __IO uint32_t PWM:1;
elessair 0:f269e3021894 93 __IO uint32_t GPIO:1;
elessair 0:f269e3021894 94 __IO uint32_t PAD2:2;
elessair 0:f269e3021894 95 __IO uint32_t RTC:1;
elessair 0:f269e3021894 96 __IO uint32_t XBAR:1;
elessair 0:f269e3021894 97 __IO uint32_t RAND:1;
elessair 0:f269e3021894 98 __IO uint32_t PAD3:2;
elessair 0:f269e3021894 99 __IO uint32_t MACHW:1;
elessair 0:f269e3021894 100 __IO uint32_t ADC:1;
elessair 0:f269e3021894 101 __IO uint32_t AES:1;
elessair 0:f269e3021894 102 __IO uint32_t FLASH:1;
elessair 0:f269e3021894 103 __IO uint32_t PAD4:1;
elessair 0:f269e3021894 104 __IO uint32_t RFANA:1;
elessair 0:f269e3021894 105 __IO uint32_t IO:1;
elessair 0:f269e3021894 106 __IO uint32_t PAD5:1;
elessair 0:f269e3021894 107 __IO uint32_t PAD:1;
elessair 0:f269e3021894 108 __IO uint32_t PMU:1;
elessair 0:f269e3021894 109 __IO uint32_t PAD6:1;
elessair 0:f269e3021894 110 __IO uint32_t TEST:1;
elessair 0:f269e3021894 111 } BITS;
elessair 0:f269e3021894 112 __IO uint32_t WORD;
elessair 0:f269e3021894 113 } PDIS; /**< 0x4001B010 Periphery disable */
elessair 0:f269e3021894 114 __IO uint32_t FDIV; /**< 0x4001B014 FCLK divider */
elessair 0:f269e3021894 115 __IO uint32_t TDIV; /**< 0x4001B01C Traceclk divider */
elessair 0:f269e3021894 116 __IO uint32_t WDIV; /**< 0x4001B020 Watchdog clock divider */
elessair 0:f269e3021894 117 __IO uint32_t TRIM_32M_INT; /**< 0x4001B024 32Mhz internal trim */
elessair 0:f269e3021894 118 __IO uint32_t TRIM_32K_INT; /**< 0x4001B02C 32kHz internal trim */
elessair 0:f269e3021894 119 __IO uint32_t TRIM_32M_EXT; /**< 0x4001B030 32Mhz external trim */
elessair 0:f269e3021894 120 __IO uint32_t TRIM_32K_EXT; /**< 0x4001B034 32Khz external trim */
elessair 0:f269e3021894 121 union {
elessair 0:f269e3021894 122 struct {
elessair 0:f269e3021894 123 __IO uint32_t OV32M;
elessair 0:f269e3021894 124 __IO uint32_t EN32M;
elessair 0:f269e3021894 125 __IO uint32_t OV32K;
elessair 0:f269e3021894 126 __IO uint32_t EN32K;
elessair 0:f269e3021894 127 } BITS;
elessair 0:f269e3021894 128 __IO uint32_t WORD;
elessair 0:f269e3021894 129 } CER; /**< 0x4001B038 clock enable register*/
elessair 0:f269e3021894 130 } ClockReg_t, *ClockReg_pt;
elessair 0:f269e3021894 131
elessair 0:f269e3021894 132 #endif /* CLOCK_MAP_H_ */