Lee Kai Xuan / mbed-os

mbed-os

Fork of mbed-os by erkin yucel

targets/TARGET_Freescale/TARGET_K20XX/clk_freqs.h@0:f269e3021894, 2016-10-23 (annotated)

Committer:
elessair
Date:
Sun Oct 23 15:10:02 2016 +0000
Revision:
0:f269e3021894
Initial commit

Who changed what in which revision?

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elessair 0:f269e3021894 1 /* mbed Microcontroller Library
elessair 0:f269e3021894 2 * Copyright (c) 2006-2015 ARM Limited
elessair 0:f269e3021894 3 *
elessair 0:f269e3021894 4 * Licensed under the Apache License, Version 2.0 (the "License");
elessair 0:f269e3021894 5 * you may not use this file except in compliance with the License.
elessair 0:f269e3021894 6 * You may obtain a copy of the License at
elessair 0:f269e3021894 7 *
elessair 0:f269e3021894 8 * http://www.apache.org/licenses/LICENSE-2.0
elessair 0:f269e3021894 9 *
elessair 0:f269e3021894 10 * Unless required by applicable law or agreed to in writing, software
elessair 0:f269e3021894 11 * distributed under the License is distributed on an "AS IS" BASIS,
elessair 0:f269e3021894 12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
elessair 0:f269e3021894 13 * See the License for the specific language governing permissions and
elessair 0:f269e3021894 14 * limitations under the License.
elessair 0:f269e3021894 15 */
elessair 0:f269e3021894 16 #ifndef CLK_FREQS_H
elessair 0:f269e3021894 17 #define CLK_FREQS_H
elessair 0:f269e3021894 18
elessair 0:f269e3021894 19 #ifdef __cplusplus
elessair 0:f269e3021894 20 extern "C" {
elessair 0:f269e3021894 21 #endif
elessair 0:f269e3021894 22
elessair 0:f269e3021894 23 /*!
elessair 0:f269e3021894 24 * \brief Get the peripheral bus clock frequency
elessair 0:f269e3021894 25 * \return Bus frequency
elessair 0:f269e3021894 26 */
elessair 0:f269e3021894 27 static inline uint32_t bus_frequency(void) {
elessair 0:f269e3021894 28 return SystemCoreClock / (((SIM->CLKDIV1 & SIM_CLKDIV1_OUTDIV2_MASK) >> SIM_CLKDIV1_OUTDIV2_SHIFT) + 1);
elessair 0:f269e3021894 29 }
elessair 0:f269e3021894 30
elessair 0:f269e3021894 31 /*!
elessair 0:f269e3021894 32 * \brief Get external oscillator (crystal) frequency
elessair 0:f269e3021894 33 * \return External osc frequency
elessair 0:f269e3021894 34 */
elessair 0:f269e3021894 35 static uint32_t extosc_frequency(void) {
elessair 0:f269e3021894 36 uint32_t MCGClock = SystemCoreClock * (1u + ((SIM->CLKDIV1 & SIM_CLKDIV1_OUTDIV1_MASK) >> SIM_CLKDIV1_OUTDIV1_SHIFT));
elessair 0:f269e3021894 37
elessair 0:f269e3021894 38 if ((MCG->C1 & MCG_C1_CLKS_MASK) == MCG_C1_CLKS(2)) //MCG clock = external reference clock
elessair 0:f269e3021894 39 return MCGClock;
elessair 0:f269e3021894 40
elessair 0:f269e3021894 41 if ((MCG->C1 & MCG_C1_CLKS_MASK) == MCG_C1_CLKS(0)) { //PLL/FLL is selected
elessair 0:f269e3021894 42 uint32_t divider, multiplier;
elessair 0:f269e3021894 43 if ((MCG->C6 & MCG_C6_PLLS_MASK) == 0x0u) { //FLL is selected
elessair 0:f269e3021894 44 if ((MCG->S & MCG_S_IREFST_MASK) == 0x0u) { //FLL uses external reference
elessair 0:f269e3021894 45 divider = (uint8_t)(1u << ((MCG->C1 & MCG_C1_FRDIV_MASK) >> MCG_C1_FRDIV_SHIFT));
elessair 0:f269e3021894 46 if ((MCG->C2 & MCG_C2_RANGE0_MASK) != 0x0u)
elessair 0:f269e3021894 47 divider <<= 5u;
elessair 0:f269e3021894 48 /* Select correct multiplier to calculate the MCG output clock */
elessair 0:f269e3021894 49 switch (MCG->C4 & (MCG_C4_DMX32_MASK | MCG_C4_DRST_DRS_MASK)) {
elessair 0:f269e3021894 50 case 0x0u:
elessair 0:f269e3021894 51 multiplier = 640u;
elessair 0:f269e3021894 52 break;
elessair 0:f269e3021894 53 case 0x20u:
elessair 0:f269e3021894 54 multiplier = 1280u;
elessair 0:f269e3021894 55 break;
elessair 0:f269e3021894 56 case 0x40u:
elessair 0:f269e3021894 57 multiplier = 1920u;
elessair 0:f269e3021894 58 break;
elessair 0:f269e3021894 59 case 0x60u:
elessair 0:f269e3021894 60 multiplier = 2560u;
elessair 0:f269e3021894 61 break;
elessair 0:f269e3021894 62 case 0x80u:
elessair 0:f269e3021894 63 multiplier = 732u;
elessair 0:f269e3021894 64 break;
elessair 0:f269e3021894 65 case 0xA0u:
elessair 0:f269e3021894 66 multiplier = 1464u;
elessair 0:f269e3021894 67 break;
elessair 0:f269e3021894 68 case 0xC0u:
elessair 0:f269e3021894 69 multiplier = 2197u;
elessair 0:f269e3021894 70 break;
elessair 0:f269e3021894 71 case 0xE0u:
elessair 0:f269e3021894 72 default:
elessair 0:f269e3021894 73 multiplier = 2929u;
elessair 0:f269e3021894 74 break;
elessair 0:f269e3021894 75 }
elessair 0:f269e3021894 76
elessair 0:f269e3021894 77 return MCGClock * divider / multiplier;
elessair 0:f269e3021894 78 }
elessair 0:f269e3021894 79 } else { //PLL is selected
elessair 0:f269e3021894 80 divider = (1u + (MCG->C5 & MCG_C5_PRDIV0_MASK));
elessair 0:f269e3021894 81 multiplier = ((MCG->C6 & MCG_C6_VDIV0_MASK) + 24u);
elessair 0:f269e3021894 82 return MCGClock * divider / multiplier;
elessair 0:f269e3021894 83 }
elessair 0:f269e3021894 84 }
elessair 0:f269e3021894 85
elessair 0:f269e3021894 86 //In all other cases either there is no crystal or we cannot determine it
elessair 0:f269e3021894 87 //For example when the FLL is running on the internal reference, and there is also an
elessair 0:f269e3021894 88 //external crystal. However these are unlikely situations
elessair 0:f269e3021894 89 return 0;
elessair 0:f269e3021894 90 }
elessair 0:f269e3021894 91
elessair 0:f269e3021894 92 //Get MCG PLL/2 or FLL frequency, depending on which one is active, sets PLLFLLSEL bit
elessair 0:f269e3021894 93 static uint32_t mcgpllfll_frequency(void) {
elessair 0:f269e3021894 94 if ((MCG->C1 & MCG_C1_CLKS_MASK) != MCG_C1_CLKS(0)) //PLL/FLL is not selected
elessair 0:f269e3021894 95 return 0;
elessair 0:f269e3021894 96
elessair 0:f269e3021894 97 uint32_t MCGClock = SystemCoreClock * (1u + ((SIM->CLKDIV1 & SIM_CLKDIV1_OUTDIV1_MASK) >> SIM_CLKDIV1_OUTDIV1_SHIFT));
elessair 0:f269e3021894 98 if ((MCG->C6 & MCG_C6_PLLS_MASK) == 0x0u) { //FLL is selected
elessair 0:f269e3021894 99 SIM->SOPT2 &= ~SIM_SOPT2_PLLFLLSEL_MASK; //MCG peripheral clock is FLL output
elessair 0:f269e3021894 100 return MCGClock;
elessair 0:f269e3021894 101 } else { //PLL is selected
elessair 0:f269e3021894 102 SIM->SOPT2 |= SIM_SOPT2_PLLFLLSEL_MASK; //MCG peripheral clock is PLL output
elessair 0:f269e3021894 103 return MCGClock;
elessair 0:f269e3021894 104 }
elessair 0:f269e3021894 105
elessair 0:f269e3021894 106 //It is possible the SystemCoreClock isn't running on the PLL, and the PLL is still active
elessair 0:f269e3021894 107 //for the peripherals, this is however an unlikely setup
elessair 0:f269e3021894 108 }
elessair 0:f269e3021894 109
elessair 0:f269e3021894 110
elessair 0:f269e3021894 111 #ifdef __cplusplus
elessair 0:f269e3021894 112 }
elessair 0:f269e3021894 113 #endif
elessair 0:f269e3021894 114
elessair 0:f269e3021894 115 #endif