Lee Kai Xuan / mbed-os

mbed-os

Fork of mbed-os by erkin yucel

targets/TARGET_ONSEMI/TARGET_NCS36510/serial_api.c@1:3deb71413561, 2017-07-20 (annotated)

Committer:
xuaner
Date:
Thu Jul 20 14:26:57 2017 +0000
Revision:
1:3deb71413561
Parent:
0:f269e3021894 
mbed_os

Who changed what in which revision?

UserRevisionLine numberNew contents of line
elessair 0:f269e3021894 1 /**
elessair 0:f269e3021894 2 ******************************************************************************
elessair 0:f269e3021894 3 * @file Serial.c
elessair 0:f269e3021894 4 * @brief Implementation of a 16C550 UART driver
elessair 0:f269e3021894 5 * @internal
elessair 0:f269e3021894 6 * @author ON Semiconductor
elessair 0:f269e3021894 7 * $Rev: 0.1 $
elessair 0:f269e3021894 8 * $Date: 2015-11-04 05:30:00 +0530 (Wed, 04 Nov 2015) $
elessair 0:f269e3021894 9 ******************************************************************************
elessair 0:f269e3021894 10 * Copyright 2016 Semiconductor Components Industries LLC (d/b/a “ON Semiconductor”).
elessair 0:f269e3021894 11 * All rights reserved. This software and/or documentation is licensed by ON Semiconductor
elessair 0:f269e3021894 12 * under limited terms and conditions. The terms and conditions pertaining to the software
elessair 0:f269e3021894 13 * and/or documentation are available at http://www.onsemi.com/site/pdf/ONSEMI_T&C.pdf
elessair 0:f269e3021894 14 * (“ON Semiconductor Standard Terms and Conditions of Sale, Section 8 Software”) and
elessair 0:f269e3021894 15 * if applicable the software license agreement. Do not use this software and/or
elessair 0:f269e3021894 16 * documentation unless you have carefully read and you agree to the limited terms and
elessair 0:f269e3021894 17 * conditions. By using this software and/or documentation, you agree to the limited
elessair 0:f269e3021894 18 * terms and conditions.
elessair 0:f269e3021894 19 *
elessair 0:f269e3021894 20 * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
elessair 0:f269e3021894 21 * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
elessair 0:f269e3021894 22 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
elessair 0:f269e3021894 23 * ON SEMICONDUCTOR SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL,
elessair 0:f269e3021894 24 * INCIDENTAL, OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
elessair 0:f269e3021894 25 * @endinternal
elessair 0:f269e3021894 26 *
elessair 0:f269e3021894 27 * @ingroup uart_16c550
elessair 0:f269e3021894 28 *
elessair 0:f269e3021894 29 */
elessair 0:f269e3021894 30 #if DEVICE_SERIAL
elessair 0:f269e3021894 31
elessair 0:f269e3021894 32 #include "serial_api.h"
elessair 0:f269e3021894 33
elessair 0:f269e3021894 34 #include "cmsis.h"
elessair 0:f269e3021894 35 #include "pinmap.h"
elessair 0:f269e3021894 36 #include "PeripheralPins.h"
elessair 0:f269e3021894 37
elessair 0:f269e3021894 38 #include "mbed_assert.h"
elessair 0:f269e3021894 39 #include <string.h>
elessair 0:f269e3021894 40 #include "uart_16c550.h"
elessair 0:f269e3021894 41 #include "cmsis_nvic.h"
elessair 0:f269e3021894 42
elessair 0:f269e3021894 43 static IRQn_Type Irq;
elessair 0:f269e3021894 44
elessair 0:f269e3021894 45 uint32_t stdio_uart_inited = 0;
elessair 0:f269e3021894 46 serial_t stdio_uart;
elessair 0:f269e3021894 47
elessair 0:f269e3021894 48 static uint32_t serial_irq_ids[UART_NUM] = {0};
elessair 0:f269e3021894 49 static uart_irq_handler irq_handler;
elessair 0:f269e3021894 50 static inline void uart_irq(uint8_t status, uint32_t index);
elessair 0:f269e3021894 51
elessair 0:f269e3021894 52
elessair 0:f269e3021894 53 /** Opens UART device.
elessair 0:f269e3021894 54 * @details
elessair 0:f269e3021894 55 * Sets the necessary registers. Set to default Baud rate 115200, 8 bit, parity None and stop bit 1.
elessair 0:f269e3021894 56 * The UART interrupt is enabled.
elessair 0:f269e3021894 57 *
elessair 0:f269e3021894 58 * @note The UART transmit interrupt is not enabled, because sending is controlled
elessair 0:f269e3021894 59 * by the task.
elessair 0:f269e3021894 60 *
elessair 0:f269e3021894 61 * @param UartNum A UART device instance.
elessair 0:f269e3021894 62 * @param options The options parameter containing the baud rate.
elessair 0:f269e3021894 63 * @return True if opening was successful.
elessair 0:f269e3021894 64 */
elessair 0:f269e3021894 65
elessair 0:f269e3021894 66 void serial_init(serial_t *obj, PinName tx, PinName rx)
elessair 0:f269e3021894 67 {
elessair 0:f269e3021894 68 uint16_t clockDivisor;
elessair 0:f269e3021894 69
elessair 0:f269e3021894 70 CrossbReg_t *CbRegOffSet;
elessair 0:f269e3021894 71 PadReg_t *PadRegOffset;
elessair 0:f269e3021894 72
elessair 0:f269e3021894 73 //find which peripheral is associated with the rx and tx pins
elessair 0:f269e3021894 74 uint32_t uart_tx = pinmap_peripheral(tx, PinMap_UART_TX);
elessair 0:f269e3021894 75 uint32_t uart_rx = pinmap_peripheral(rx, PinMap_UART_RX);
elessair 0:f269e3021894 76 //check if the peripherals for each pin are the same or not
elessair 0:f269e3021894 77 //returns the enum associated with the peripheral
elessair 0:f269e3021894 78 //in the case of this target, the enum is the base address of the peripheral
elessair 0:f269e3021894 79 obj->UARTREG = (Uart16C550Reg_pt) pinmap_merge(uart_tx, uart_rx);
elessair 0:f269e3021894 80 MBED_ASSERT(obj->UARTREG != (Uart16C550Reg_pt) NC);
elessair 0:f269e3021894 81
elessair 0:f269e3021894 82 pinmap_pinout(tx, PinMap_UART_TX);
elessair 0:f269e3021894 83 pinmap_pinout(rx, PinMap_UART_RX);
elessair 0:f269e3021894 84
elessair 0:f269e3021894 85 /*TODO: Mac Lobdell - we should recommend using the instance method and not using base addresses as index */
elessair 0:f269e3021894 86
elessair 0:f269e3021894 87 if (obj->UARTREG == (Uart16C550Reg_pt)STDIO_UART) {
elessair 0:f269e3021894 88 stdio_uart_inited = 1;
elessair 0:f269e3021894 89 memcpy(&stdio_uart, obj, sizeof(serial_t));
elessair 0:f269e3021894 90 }
elessair 0:f269e3021894 91 /*TODO: determine if pullups are needed/recommended */
elessair 0:f269e3021894 92 /* if (tx != NC) {
elessair 0:f269e3021894 93 pin_mode(tx, PullUp);
elessair 0:f269e3021894 94 }
elessair 0:f269e3021894 95 if (rx != NC) {
elessair 0:f269e3021894 96 pin_mode(rx, PullUp);
elessair 0:f269e3021894 97 }
elessair 0:f269e3021894 98 */
elessair 0:f269e3021894 99 /* Configure IOs to UART using cross bar, pad and GPIO settings */
elessair 0:f269e3021894 100
elessair 0:f269e3021894 101 if(obj->UARTREG == UART2REG) {
elessair 0:f269e3021894 102 /* UART 2 */
elessair 0:f269e3021894 103 CLOCK_ENABLE(CLOCK_UART2);
elessair 0:f269e3021894 104 Irq = Uart2_IRQn;
elessair 0:f269e3021894 105 } else if(obj->UARTREG == UART1REG) {
elessair 0:f269e3021894 106 /* UART 1 */
elessair 0:f269e3021894 107 CLOCK_ENABLE(CLOCK_UART1);
elessair 0:f269e3021894 108
elessair 0:f269e3021894 109 Irq = Uart1_IRQn;
elessair 0:f269e3021894 110 } else {
elessair 0:f269e3021894 111 MBED_ASSERT(False);
elessair 0:f269e3021894 112 }
elessair 0:f269e3021894 113
elessair 0:f269e3021894 114 CLOCK_ENABLE(CLOCK_GPIO);
elessair 0:f269e3021894 115 CLOCK_ENABLE(CLOCK_CROSSB);
elessair 0:f269e3021894 116 CLOCK_ENABLE(CLOCK_PAD);
elessair 0:f269e3021894 117
elessair 0:f269e3021894 118 /*TODO: determine if tx and rx are used correctly in this case - this depends on the pin enum matching the position in the crossbar*/
elessair 0:f269e3021894 119
elessair 0:f269e3021894 120 /* Configure tx pin as UART */
elessair 0:f269e3021894 121 CbRegOffSet = (CrossbReg_t*)(CROSSBREG_BASE + (tx * CROSS_REG_ADRS_BYTE_SIZE));
elessair 0:f269e3021894 122 CbRegOffSet->DIOCTRL0 = CONFIGURE_AS_UART; /* tx pin as UART */
elessair 0:f269e3021894 123
elessair 0:f269e3021894 124 /* Configure rx pin as UART */
elessair 0:f269e3021894 125 CbRegOffSet = (CrossbReg_t*)(CROSSBREG_BASE + (rx * CROSS_REG_ADRS_BYTE_SIZE));
elessair 0:f269e3021894 126 CbRegOffSet->DIOCTRL0 = CONFIGURE_AS_UART; /* rx pin as UART */
elessair 0:f269e3021894 127
elessair 0:f269e3021894 128 /** - Set pad parameters, output drive strength, pull piece control, output drive type */
elessair 0:f269e3021894 129 PadRegOffset = (PadReg_t*)(PADREG_BASE + (tx * PAD_REG_ADRS_BYTE_SIZE));
elessair 0:f269e3021894 130 PadRegOffset->PADIO0.WORD = PAD_UART_TX; /* Pad setting for UART Tx */
elessair 0:f269e3021894 131
elessair 0:f269e3021894 132 PadRegOffset = (PadReg_t*)(PADREG_BASE + (rx * PAD_REG_ADRS_BYTE_SIZE));
elessair 0:f269e3021894 133 PadRegOffset->PADIO0.WORD = PAD_UART_RX; /* Pad settings for UART Rx */
elessair 0:f269e3021894 134
elessair 0:f269e3021894 135 GPIOREG->W_OUT |= (True << tx); /* tx as OUT direction */
elessair 0:f269e3021894 136 GPIOREG->W_IN |= (True << rx); /* rx as IN directon */
elessair 0:f269e3021894 137
elessair 0:f269e3021894 138 CLOCK_DISABLE(CLOCK_PAD);
elessair 0:f269e3021894 139 CLOCK_DISABLE(CLOCK_CROSSB);
elessair 0:f269e3021894 140 CLOCK_DISABLE(CLOCK_GPIO);
elessair 0:f269e3021894 141
elessair 0:f269e3021894 142 /* Set the divisor value. To do so, LCR[7] needs to be set to 1 in order to access the divisor registers.
elessair 0:f269e3021894 143 * The right-shift of 4 is a division of 16, representing the oversampling rate. */
elessair 0:f269e3021894 144 clockDivisor = (fClockGetPeriphClockfrequency() / UART_DEFAULT_BAUD) >> 4;
elessair 0:f269e3021894 145 obj->UARTREG->LCR.WORD = 0x80;
elessair 0:f269e3021894 146 obj->UARTREG->DLL = clockDivisor & 0xFF;
elessair 0:f269e3021894 147 obj->UARTREG->DLM = clockDivisor >> 8;
elessair 0:f269e3021894 148
elessair 0:f269e3021894 149 /* Set the character width to 8 data bits, no parity, 1 stop bit. Write the entire line control register,
elessair 0:f269e3021894 150 * effectively disabling the divisor latch. */
elessair 0:f269e3021894 151 obj->UARTREG->LCR.WORD = 0x03;
elessair 0:f269e3021894 152
elessair 0:f269e3021894 153 /* Enable the FIFOs, reset the Tx and Rx FIFOs, set the Rx FIFO trigger level to 8 bytes, and set DMA Mode
elessair 0:f269e3021894 154 to 1. */
elessair 0:f269e3021894 155 obj->UARTREG->FCR.WORD = (FCR_RXFIFOTRIGGERLEVEL_8 | FCR_DMA_MODE_1 |
elessair 0:f269e3021894 156 FCR_TXFIFO_RESET | FCR_RXFIFO_RESET | FCR_FIFO_ENABLE);
elessair 0:f269e3021894 157
elessair 0:f269e3021894 158 /* Make a copy of the current MSR to the SCR register. This is used from task space to determine the
elessair 0:f269e3021894 159 * flow control state. */
elessair 0:f269e3021894 160 obj->UARTREG->SCR = obj->UARTREG->MSR.WORD;
elessair 0:f269e3021894 161
elessair 0:f269e3021894 162 if((int)obj->UARTREG == STDIO_UART) {
elessair 0:f269e3021894 163 stdio_uart_inited = 1;
elessair 0:f269e3021894 164 memcpy(&stdio_uart, obj, sizeof(serial_t));
elessair 0:f269e3021894 165 }
elessair 0:f269e3021894 166
elessair 0:f269e3021894 167 NVIC_ClearPendingIRQ(Irq);
elessair 0:f269e3021894 168
elessair 0:f269e3021894 169 return;
elessair 0:f269e3021894 170 }
elessair 0:f269e3021894 171
elessair 0:f269e3021894 172 /** Closes a UART device.
elessair 0:f269e3021894 173 * @details
elessair 0:f269e3021894 174 * Disables the UART interrupt.
elessair 0:f269e3021894 175 *
elessair 0:f269e3021894 176 * @param device The UART device to close.
elessair 0:f269e3021894 177 */
elessair 0:f269e3021894 178 void serial_free(serial_t *obj)
elessair 0:f269e3021894 179 {
elessair 0:f269e3021894 180 NVIC_DisableIRQ(obj->IRQType);
elessair 0:f269e3021894 181 }
elessair 0:f269e3021894 182
elessair 0:f269e3021894 183 void serial_baud(serial_t *obj, int baudrate)
elessair 0:f269e3021894 184 {
elessair 0:f269e3021894 185 /* Set the divisor value. To do so, LCR[7] needs to be set to 1 in order to access the divisor registers.
elessair 0:f269e3021894 186 * The right-shift of 4 is a division of 16, representing the oversampling rate. */
elessair 0:f269e3021894 187 uint16_t clockDivisor = (fClockGetPeriphClockfrequency() / baudrate) >> 4;
elessair 0:f269e3021894 188
elessair 0:f269e3021894 189 obj->UARTREG->LCR.BITS.DLAB = True;
elessair 0:f269e3021894 190 obj->UARTREG->DLL = clockDivisor & 0xFF;
elessair 0:f269e3021894 191 obj->UARTREG->DLM = clockDivisor >> 8;
elessair 0:f269e3021894 192 obj->UARTREG->LCR.BITS.DLAB = False;
elessair 0:f269e3021894 193 }
elessair 0:f269e3021894 194
elessair 0:f269e3021894 195 /*
elessair 0:f269e3021894 196 Parity XX0 – Parity disabled; 001 – Odd Parity; 011 – Even Parity; 101 – Stick Parity, checked as 1; 111 – Stick Parity, checked as 0.
elessair 0:f269e3021894 197 StopBit 0 – 1 stop bit; 1 – 2 stop bits.
elessair 0:f269e3021894 198 DataLen 00 – 5 bits; 01 – 6 bits; 10 – 7 bits; 11 – 8 bits
elessair 0:f269e3021894 199 */
elessair 0:f269e3021894 200 void serial_format(serial_t *obj, int data_bits, SerialParity parity, int stop_bits)
elessair 0:f269e3021894 201 {
elessair 0:f269e3021894 202 if(data_bits >= 5 && data_bits <= 8 && parity <= 7 && stop_bits >= 1 && stop_bits <= 2) {
elessair 0:f269e3021894 203 if(parity == (SerialParity)0) {
elessair 0:f269e3021894 204 parity = (SerialParity)0;
elessair 0:f269e3021894 205 } else {
elessair 0:f269e3021894 206 parity = (SerialParity)(parity + parity - 1) ;
elessair 0:f269e3021894 207 }
elessair 0:f269e3021894 208
elessair 0:f269e3021894 209 obj->UARTREG->LCR.WORD |= ((((data_bits - 5) << UART_LCR_DATALEN_BIT_POS) |
elessair 0:f269e3021894 210 (parity << UART_LCR_PARITY_BIT_POS) |
elessair 0:f269e3021894 211 ((stop_bits - 1) << UART_LCR_STPBIT_BIT_POS)) & 0x3F);
elessair 0:f269e3021894 212 } else {
elessair 0:f269e3021894 213 MBED_ASSERT(False);
elessair 0:f269e3021894 214 }
elessair 0:f269e3021894 215 }
elessair 0:f269e3021894 216
elessair 0:f269e3021894 217 void serial_irq_handler(serial_t *obj, uart_irq_handler handler, uint32_t id)
elessair 0:f269e3021894 218 {
elessair 0:f269e3021894 219 irq_handler = handler;
elessair 0:f269e3021894 220 serial_irq_ids[obj->index] = id;
elessair 0:f269e3021894 221 }
elessair 0:f269e3021894 222
elessair 0:f269e3021894 223 /******************************************************
elessair 0:f269e3021894 224 ************* Internal IRQ functions ******************
elessair 0:f269e3021894 225 *******************************************************/
elessair 0:f269e3021894 226 void Uart1_Irq()
elessair 0:f269e3021894 227 {
elessair 0:f269e3021894 228 uint8_t active_irq = (uint8_t)(UART1REG->LSR.WORD) & 0xFF;
elessair 0:f269e3021894 229 uint8_t irq_mask = 0;
elessair 0:f269e3021894 230
elessair 0:f269e3021894 231 if(UART1REG->IER.WORD & UART_IER_TX_EMPTY_MASK) { /*check if TX interrupt is enabled*/
elessair 0:f269e3021894 232 irq_mask |= active_irq & UART_LSR_TX_EMPTY_MASK;
elessair 0:f269e3021894 233 }
elessair 0:f269e3021894 234
elessair 0:f269e3021894 235 if(UART1REG->IER.WORD & UART_IER_RX_DATA_READY_MASK) { /*check if RX interrupt is enabled*/
elessair 0:f269e3021894 236 irq_mask |= active_irq & UART_LSR_RX_DATA_READY_MASK;
elessair 0:f269e3021894 237 }
elessair 0:f269e3021894 238
elessair 0:f269e3021894 239 //uart_irq((uint8_t)(UART1REG->LSR.WORD & 0xFF), 0);
elessair 0:f269e3021894 240 uart_irq(active_irq & irq_mask, 0);
elessair 0:f269e3021894 241 }
elessair 0:f269e3021894 242
elessair 0:f269e3021894 243 void Uart2_Irq()
elessair 0:f269e3021894 244 {
elessair 0:f269e3021894 245 uint8_t active_irq = (uint8_t)(UART2REG->LSR.WORD) & 0xFF;
elessair 0:f269e3021894 246 uint8_t irq_mask = 0;
elessair 0:f269e3021894 247
elessair 0:f269e3021894 248 if(UART2REG->IER.WORD & UART_IER_TX_EMPTY_MASK) { /*check if TX interrupt is enabled*/
elessair 0:f269e3021894 249 irq_mask |= active_irq & UART_LSR_TX_EMPTY_MASK;
elessair 0:f269e3021894 250 }
elessair 0:f269e3021894 251
elessair 0:f269e3021894 252 if(UART2REG->IER.WORD & UART_IER_RX_DATA_READY_MASK) { /*check if RX interrupt is enabled*/
elessair 0:f269e3021894 253 irq_mask |= active_irq & UART_LSR_RX_DATA_READY_MASK;
elessair 0:f269e3021894 254 }
elessair 0:f269e3021894 255
elessair 0:f269e3021894 256 //uart_irq((uint8_t)(UART2REG->LSR.WORD & 0xFF), 1);
elessair 0:f269e3021894 257 uart_irq(active_irq & irq_mask, 1);
elessair 0:f269e3021894 258
elessair 0:f269e3021894 259 }
elessair 0:f269e3021894 260
elessair 0:f269e3021894 261 static inline void uart_irq(uint8_t status, uint32_t index)
elessair 0:f269e3021894 262 {
elessair 0:f269e3021894 263 if (serial_irq_ids[index] != 0) {
elessair 0:f269e3021894 264 if (status & UART_LSR_TX_EMPTY_MASK) {
elessair 0:f269e3021894 265 irq_handler(serial_irq_ids[index], TxIrq);
elessair 0:f269e3021894 266 }
elessair 0:f269e3021894 267 if (status & UART_LSR_RX_DATA_READY_MASK) {
elessair 0:f269e3021894 268 irq_handler(serial_irq_ids[index], RxIrq);
elessair 0:f269e3021894 269 }
elessair 0:f269e3021894 270 }
elessair 0:f269e3021894 271 }
elessair 0:f269e3021894 272 /******************************************************/
elessair 0:f269e3021894 273
elessair 0:f269e3021894 274 void serial_irq_set(serial_t *obj, SerialIrq irq, uint32_t enable)
elessair 0:f269e3021894 275 {
elessair 0:f269e3021894 276 IRQn_Type irq_n = (IRQn_Type)0;
elessair 0:f269e3021894 277 uint32_t Vector = 0;
elessair 0:f269e3021894 278
elessair 0:f269e3021894 279 /* Check UART number & assign irq handler */
elessair 0:f269e3021894 280 if(obj->UARTREG == UART1REG) {
elessair 0:f269e3021894 281 /* UART 2 */
elessair 0:f269e3021894 282 Vector = (uint32_t)&Uart1_Irq;
elessair 0:f269e3021894 283 irq_n = Uart1_IRQn;
elessair 0:f269e3021894 284 } else if(obj->UARTREG == UART2REG) {
elessair 0:f269e3021894 285 /* UART 1 */
elessair 0:f269e3021894 286 Vector = (uint32_t)&Uart2_Irq;
elessair 0:f269e3021894 287 irq_n = Uart2_IRQn;
elessair 0:f269e3021894 288 } else {
elessair 0:f269e3021894 289 MBED_ASSERT(False);
elessair 0:f269e3021894 290 }
elessair 0:f269e3021894 291
elessair 0:f269e3021894 292 /* Check IRQ type & enable/disable accordingly */
elessair 0:f269e3021894 293 if(enable) {
elessair 0:f269e3021894 294 /* Enable */
elessair 0:f269e3021894 295 if(irq == RxIrq) {
elessair 0:f269e3021894 296 /* Rx IRQ */
elessair 0:f269e3021894 297 obj->UARTREG->FCR.BITS.RX_FIFO_TRIG = 0x0;
elessair 0:f269e3021894 298 obj->UARTREG->IER.BITS.RX_DATA_INT = True;
elessair 0:f269e3021894 299 } else if(irq == TxIrq) {
elessair 0:f269e3021894 300 /* Tx IRQ */
elessair 0:f269e3021894 301 obj->UARTREG->IER.BITS.TX_HOLD_INT = True;
elessair 0:f269e3021894 302 } else {
elessair 0:f269e3021894 303 MBED_ASSERT(False);
elessair 0:f269e3021894 304 }
elessair 0:f269e3021894 305 NVIC_SetVector(irq_n, Vector);
elessair 0:f269e3021894 306 NVIC_EnableIRQ(irq_n);
elessair 0:f269e3021894 307 } else {
elessair 0:f269e3021894 308 /* Disable */
elessair 0:f269e3021894 309 NVIC_DisableIRQ(irq_n);
elessair 0:f269e3021894 310 if(irq == RxIrq) {
elessair 0:f269e3021894 311 /* Rx IRQ */
elessair 0:f269e3021894 312 obj->UARTREG->IER.BITS.RX_DATA_INT = False;
elessair 0:f269e3021894 313 } else if(irq == TxIrq) {
elessair 0:f269e3021894 314 /* Tx IRQ */
elessair 0:f269e3021894 315
elessair 0:f269e3021894 316 obj->UARTREG->IER.BITS.TX_HOLD_INT = False;
elessair 0:f269e3021894 317 } else {
elessair 0:f269e3021894 318 MBED_ASSERT(False);
elessair 0:f269e3021894 319 }
elessair 0:f269e3021894 320 }
elessair 0:f269e3021894 321 }
elessair 0:f269e3021894 322
elessair 0:f269e3021894 323 int serial_getc(serial_t *obj)
elessair 0:f269e3021894 324 {
elessair 0:f269e3021894 325 uint8_t c;
elessair 0:f269e3021894 326
elessair 0:f269e3021894 327 while(!obj->UARTREG->LSR.BITS.READY); /* Wait for received data is ready */
elessair 0:f269e3021894 328 c = obj->UARTREG->RBR & 0xFF; /* Get received character */
elessair 0:f269e3021894 329 return c;
elessair 0:f269e3021894 330 }
elessair 0:f269e3021894 331
elessair 0:f269e3021894 332 void serial_putc(serial_t *obj, int c)
elessair 0:f269e3021894 333 {
elessair 0:f269e3021894 334
elessair 0:f269e3021894 335 while(!obj->UARTREG->LSR.BITS.TX_HOLD_EMPTY);/* Wait till THR is empty */
elessair 0:f269e3021894 336 obj->UARTREG->THR = c; /* Transmit byte */
elessair 0:f269e3021894 337
elessair 0:f269e3021894 338 }
elessair 0:f269e3021894 339
elessair 0:f269e3021894 340 int serial_readable(serial_t *obj)
elessair 0:f269e3021894 341 {
elessair 0:f269e3021894 342 return obj->UARTREG->LSR.BITS.READY;
elessair 0:f269e3021894 343 }
elessair 0:f269e3021894 344
elessair 0:f269e3021894 345 int serial_writable(serial_t *obj)
elessair 0:f269e3021894 346 {
elessair 0:f269e3021894 347 return obj->UARTREG->LSR.BITS.TX_HOLD_EMPTY;
elessair 0:f269e3021894 348 }
elessair 0:f269e3021894 349
elessair 0:f269e3021894 350 void serial_clear(serial_t *obj)
elessair 0:f269e3021894 351 {
elessair 0:f269e3021894 352 /* Reset TX & RX FIFO */
elessair 0:f269e3021894 353 obj->UARTREG->FCR.WORD |= ((True << UART_FCS_TX_FIFO_RST_BIT_POS) |
elessair 0:f269e3021894 354 (True << UART_FCS_RX_FIFO_RST_BIT_POS));
elessair 0:f269e3021894 355 }
elessair 0:f269e3021894 356
elessair 0:f269e3021894 357 void serial_break_set(serial_t *obj)
elessair 0:f269e3021894 358 {
elessair 0:f269e3021894 359 obj->UARTREG->LCR.BITS.BREAK = True;
elessair 0:f269e3021894 360 }
elessair 0:f269e3021894 361
elessair 0:f269e3021894 362 void serial_break_clear(serial_t *obj)
elessair 0:f269e3021894 363 {
elessair 0:f269e3021894 364 obj->UARTREG->LCR.BITS.BREAK = False;
elessair 0:f269e3021894 365 }
elessair 0:f269e3021894 366
elessair 0:f269e3021894 367 void serial_pinout_tx(PinName tx)
elessair 0:f269e3021894 368 {
elessair 0:f269e3021894 369 /* COnfigure PinNo to drive strength of 1, Push pull and pull none */
elessair 0:f269e3021894 370 fPadIOCtrl(tx, 1, 0, 1);
elessair 0:f269e3021894 371 }
elessair 0:f269e3021894 372
elessair 0:f269e3021894 373 /** Configure the serial for the flow control. It sets flow control in the hardware
elessair 0:f269e3021894 374 * if a serial peripheral supports it, otherwise software emulation is used.
elessair 0:f269e3021894 375 *
elessair 0:f269e3021894 376 * @param obj The serial object
elessair 0:f269e3021894 377 * @param type The type of the flow control. Look at the available FlowControl types.
elessair 0:f269e3021894 378 * @param rxflow The TX pin name
elessair 0:f269e3021894 379 * @param txflow The RX pin name
elessair 0:f269e3021894 380 */
elessair 0:f269e3021894 381 void serial_set_flow_control(serial_t *obj, FlowControl type, PinName rxflow, PinName txflow)
elessair 0:f269e3021894 382 {
elessair 0:f269e3021894 383 /* TODO: This is an empty implementation for now.*/
elessair 0:f269e3021894 384 }
elessair 0:f269e3021894 385
elessair 0:f269e3021894 386 #endif /* DEVICE_SERIAL */