Lee Kai Xuan / mbed-os

mbed-os

Fork of mbed-os by erkin yucel

targets/TARGET_ONSEMI/TARGET_NCS36510/rtc_map.h@1:3deb71413561, 2017-07-20 (annotated)

Committer:
xuaner
Date:
Thu Jul 20 14:26:57 2017 +0000
Revision:
1:3deb71413561
Parent:
0:f269e3021894 
mbed_os

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elessair 0:f269e3021894 1 /**
elessair 0:f269e3021894 2 ******************************************************************************
elessair 0:f269e3021894 3 * @file rtc_map.h
elessair 0:f269e3021894 4 * @brief Real Time Clock HW register map
elessair 0:f269e3021894 5 * @internal
elessair 0:f269e3021894 6 * @author ON Semiconductor.
elessair 0:f269e3021894 7 * $Rev: 3008 $
elessair 0:f269e3021894 8 * $Date: 2014-10-16 18:42:48 +0530 (Thu, 16 Oct 2014) $
elessair 0:f269e3021894 9 ******************************************************************************
elessair 0:f269e3021894 10 * Copyright 2016 Semiconductor Components Industries LLC (d/b/a “ON Semiconductor”).
elessair 0:f269e3021894 11 * All rights reserved. This software and/or documentation is licensed by ON Semiconductor
elessair 0:f269e3021894 12 * under limited terms and conditions. The terms and conditions pertaining to the software
elessair 0:f269e3021894 13 * and/or documentation are available at http://www.onsemi.com/site/pdf/ONSEMI_T&C.pdf
elessair 0:f269e3021894 14 * (“ON Semiconductor Standard Terms and Conditions of Sale, Section 8 Software”) and
elessair 0:f269e3021894 15 * if applicable the software license agreement. Do not use this software and/or
elessair 0:f269e3021894 16 * documentation unless you have carefully read and you agree to the limited terms and
elessair 0:f269e3021894 17 * conditions. By using this software and/or documentation, you agree to the limited
elessair 0:f269e3021894 18 * terms and conditions.
elessair 0:f269e3021894 19 *
elessair 0:f269e3021894 20 * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
elessair 0:f269e3021894 21 * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
elessair 0:f269e3021894 22 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
elessair 0:f269e3021894 23 * ON SEMICONDUCTOR SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL,
elessair 0:f269e3021894 24 * INCIDENTAL, OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
elessair 0:f269e3021894 25 * @endinternal
elessair 0:f269e3021894 26 *
elessair 0:f269e3021894 27 * @ingroup rtc
elessair 0:f269e3021894 28 *
elessair 0:f269e3021894 29 * @details
elessair 0:f269e3021894 30 * <p>
elessair 0:f269e3021894 31 * Teal Time Clock HW register map description
elessair 0:f269e3021894 32 * </p>
elessair 0:f269e3021894 33 *
elessair 0:f269e3021894 34 * <h1> Reference document(s) </h1>
elessair 0:f269e3021894 35 * <p>
elessair 0:f269e3021894 36 * <a HOURef="../pdf/IPC7206_RTC_APB_DS_v1P0.pdf" target="_blank">
elessair 0:f269e3021894 37 * IPC7206 APB RTC Design Specification v1.0 </a>
elessair 0:f269e3021894 38 * </p>
elessair 0:f269e3021894 39 */
elessair 0:f269e3021894 40
elessair 0:f269e3021894 41 #ifndef RTC_MAP_H_
elessair 0:f269e3021894 42 #define RTC_MAP_H_
elessair 0:f269e3021894 43
elessair 0:f269e3021894 44 #include "architecture.h"
elessair 0:f269e3021894 45
elessair 0:f269e3021894 46 /** Real Time Clock Control HW Structure Overlay */
elessair 0:f269e3021894 47 typedef struct {
elessair 0:f269e3021894 48 #ifdef REVB
elessair 0:f269e3021894 49 /*REVD REPLACE COMPLETE MAP WITH DATA FROM DIG DESIGN SPEC */
elessair 0:f269e3021894 50 __IO uint32_t SECOND;/**<SECOND Counter */
elessair 0:f269e3021894 51 __IO uint32_t MINUTE;/**<DAY Counter */
elessair 0:f269e3021894 52 __IO uint32_t HOUR;/**< HOUR Counter */
elessair 0:f269e3021894 53 __IO uint32_t DAY;/**< DAY Counter */
elessair 0:f269e3021894 54 __IO uint32_t MONTH;/**< MONTH Counter */
elessair 0:f269e3021894 55 __IO uint32_t YEAR;/**< YEAR Counter */
elessair 0:f269e3021894 56 union {
elessair 0:f269e3021894 57 struct {
elessair 0:f269e3021894 58 __IO uint32_t PAD1 :1;/**<Reserved; Writes have no effect. Read as 0 */
elessair 0:f269e3021894 59 __IO uint32_t TEST_MINUTE :1;/**<0 = normal operation , 1 = Test Mode */
elessair 0:f269e3021894 60 __IO uint32_t TEST_HOUR :1;/**<0 = normal operation , 1 = Test Mode */
elessair 0:f269e3021894 61 __IO uint32_t TEST_DAY :1;/**<0 = normal operation , 1 = Test Mode */
elessair 0:f269e3021894 62 __IO uint32_t TEST_MONTH :1;/**<0 = normal operation , 1 = Test Mode */
elessair 0:f269e3021894 63 __IO uint32_t TEST_YEAR :1;/**<0 = normal operation , 1 = Test Mode */
elessair 0:f269e3021894 64 __IO uint32_t PAD2 :1;/**<Reserved; Writes have no effect. Read as 0 */
elessair 0:f269e3021894 65 __IO uint32_t RESET :1;/**< 0 = counters are incrementing , 1 = counters are in reset */
elessair 0:f269e3021894 66 } BITS;
elessair 0:f269e3021894 67 __IO uint32_t WORD;
elessair 0:f269e3021894 68 } CONTROL;
elessair 0:f269e3021894 69 __IO uint32_t DIVISOR;/**<Clock Divisor value */
elessair 0:f269e3021894 70 __IO uint32_t ALARM_SECOND;/**<SECOND Alarm's BCD value */
elessair 0:f269e3021894 71 __IO uint32_t ALARM_MINUTE;/**<MINUTE Alarm's BCD value */
elessair 0:f269e3021894 72 __IO uint32_t ALARM_HOUR;/**<HOUR Alarm's BCD value*/
elessair 0:f269e3021894 73 __IO uint32_t ALARM_DAY;/**<DAY Alarm's BCD value */
elessair 0:f269e3021894 74 __IO uint32_t ALARM_MONTH;/**<MONTH Alarm's BCD value */
elessair 0:f269e3021894 75 __IO uint32_t ALARM_YEAR;/**<YEAR Alarm's BCD value */
elessair 0:f269e3021894 76 union {
elessair 0:f269e3021894 77 struct {
elessair 0:f269e3021894 78 __IO uint32_t SECOND :1;/**<SECOND Alarm interrupt : 0 = disabled, 1 = enabled */
elessair 0:f269e3021894 79 __IO uint32_t MINUTE :1;/**<MINUTE Alarm interrupt : 0 = disabled, 1 = enabled */
elessair 0:f269e3021894 80 __IO uint32_t HOUR :1;/**<HOUR Alarm interrupt : 0 = disabled, 1 = enabled */
elessair 0:f269e3021894 81 __IO uint32_t DAY :1;/**<DAY Alarm interrupt : 0 = disabled, 1 = enabled */
elessair 0:f269e3021894 82 __IO uint32_t MONTH :1;/**<MONTH Alarm interrupt : 0 = disabled, 1 = enabled */
elessair 0:f269e3021894 83 __IO uint32_t YEAR :1;/**<YEAR Alarm interrupt : 0 = disabled, 1 = enabled */
elessair 0:f269e3021894 84 __IO uint32_t PAD :2 ;/**<Writes have no effect; Read as 2’b00 */
elessair 0:f269e3021894 85 } BITS;
elessair 0:f269e3021894 86 __IO uint32_t WORD;
elessair 0:f269e3021894 87 } INT_EN_CONTROL;
elessair 0:f269e3021894 88 union {
elessair 0:f269e3021894 89 struct {
elessair 0:f269e3021894 90 __I uint32_t SECOND :1;/**<SECOND Alarm interrupt : 0= inactive , 1 = active */
elessair 0:f269e3021894 91 __I uint32_t MINUTE :1;/**<MINUTE Alarm interrupt : 0= inactive , 1 = active */
elessair 0:f269e3021894 92 __I uint32_t HOUR :1;/**<HOUR Alarm interrupt : 0= inactive , 1 = active */
elessair 0:f269e3021894 93 __I uint32_t DAY :1;/**<DAY Alarm interrupt : 0= inactive , 1 = active */
elessair 0:f269e3021894 94 __I uint32_t MONTH :1;/**<MONTH Alarm interrupt : 0= inactive , 1 = active */
elessair 0:f269e3021894 95 __I uint32_t YEAR :1;/**<YEAR Alarm interrupt : 0= inactive , 1 = active */
elessair 0:f269e3021894 96 __I uint32_t PAD :2; /**<Read as 00 */
elessair 0:f269e3021894 97 } BITS;
elessair 0:f269e3021894 98 __I uint32_t WORD;
elessair 0:f269e3021894 99 } INT_STATUS;
elessair 0:f269e3021894 100 union {
elessair 0:f269e3021894 101 struct {
elessair 0:f269e3021894 102 __O uint32_t SECOND :1;/**<Write 1 to clear the SECOND Alarm interrupt.*/
elessair 0:f269e3021894 103 __O uint32_t MINUTE :1;/**<Write 1 to clear the MINUTE Alarm interrupt*/
elessair 0:f269e3021894 104 __O uint32_t HOUR :1;/**<Write 1 to clear the HOUR Alarm interrupt*/
elessair 0:f269e3021894 105 __O uint32_t DAY :1;/**< Write 1 to clear the DAY Alarm interrupt*/
elessair 0:f269e3021894 106 __O uint32_t MONTH :1;/**<Write 1 to clear the MONTH Alarm interrupt */
elessair 0:f269e3021894 107 __O uint32_t YEAR :1;/**< Write 1 to clear the YEAR Alarm interrupt*/
elessair 0:f269e3021894 108 __O uint32_t PAD :2 ;/**< Writes have no effect. */
elessair 0:f269e3021894 109 } BITS;
elessair 0:f269e3021894 110 __O uint32_t WORD;
elessair 0:f269e3021894 111 } INT_CLEAR;
elessair 0:f269e3021894 112 #endif /* REVB */
elessair 0:f269e3021894 113 #ifdef REVD
elessair 0:f269e3021894 114 __IO uint32_t SUB_SECOND_COUNTER; /**<SUB SECOND Counter */ /* 0x4000F000 */
elessair 0:f269e3021894 115 __IO uint32_t SECOND_COUNTER; /**<SECOND Counter */ /* 0x4000F004 */
elessair 0:f269e3021894 116 __IO uint32_t SUB_SECOND_ALARM; /**< SUB SECOND alarm */ /* 0x4000F008 */
elessair 0:f269e3021894 117 __IO uint32_t SECOND_ALARM; /**< SECOND alarm */ /* 0x4000F00c */
elessair 0:f269e3021894 118 union {
elessair 0:f269e3021894 119 struct {
elessair 0:f269e3021894 120 __IO uint32_t SUB_SEC_COUNTER_EN :1; /**<Sub-second counter enable. (1=count is enabled, 0=retain count value) */
elessair 0:f269e3021894 121 __IO uint32_t SEC_COUNTER_EN :1; /**<Second counter enable. (1=count is enabled, 0=retain count value) */
elessair 0:f269e3021894 122 __IO uint32_t SUB_SECOND_INT_EN :1; /**<Sub-second interrupt enable (1=interrupt enabled, 0=interrupt disabled) */
elessair 0:f269e3021894 123 __IO uint32_t SECOND_INT_EN :1; /**<Second interrupt enable (1=interrupt enabled, 0=interrupt disabled) */
elessair 0:f269e3021894 124 } BITS;
elessair 0:f269e3021894 125 __IO uint32_t WORD;
elessair 0:f269e3021894 126 } CONTROL; /* 0x4000F010 */
elessair 0:f269e3021894 127 union {
elessair 0:f269e3021894 128 struct {
elessair 0:f269e3021894 129 /**<Any write to the status register will clear the error bit. */
elessair 0:f269e3021894 130 __IO uint32_t SUB_SECOND_INT:1; /**<Sub-second interrupt status. (1=interrupt active, 0=no interrupt)*/
elessair 0:f269e3021894 131 __IO uint32_t SECOND_INT :1; /**<Second interrupt status. (1=interrupt active, 0=no interrupt)*/
elessair 0:f269e3021894 132 __IO uint32_t WRITE_ERROR :1; /**<Reads error bit which is set when a write occurs before a previous write to the same register has completed. */
elessair 0:f269e3021894 133 __IO uint32_t BSY_ANY_WRT :1; /**<Busy with any write.*/
elessair 0:f269e3021894 134 __IO uint32_t BSY_SUB_SEC_CNTR_REG_WRT :1; /**<Busy with a sub-second counter register write.*/
elessair 0:f269e3021894 135 __IO uint32_t BSY_SEC_CNTR_REG_WRT :1; /**<Busy with a second counter register write.*/
elessair 0:f269e3021894 136 __IO uint32_t BSY_SUB_SEC_ALRM_REG_WRT :1; /**<Busy with a sub-second alarm register write.*/
elessair 0:f269e3021894 137 __IO uint32_t BSY_SEC_ALRM_REG_WRT:1; /**<Busy with a second alarm register write.*/
elessair 0:f269e3021894 138 __IO uint32_t BSY_CTRL_REG_WRT :1; /**<Busy with a control register write.*/
elessair 0:f269e3021894 139 __IO uint32_t BSY_SUB_SEC_INT_CLR_WRT :1; /**<Busy with a sub-second interrupt clear write.*/
elessair 0:f269e3021894 140 __IO uint32_t BSY_SEC_INT_CLR_WRT :1; /**<Busy with a second interrupt clear write.*/
elessair 0:f269e3021894 141 } BITS;
elessair 0:f269e3021894 142 __IO uint32_t WORD;
elessair 0:f269e3021894 143 } STATUS; /* 0x4000F014 */
elessair 0:f269e3021894 144 union {
elessair 0:f269e3021894 145 struct {
elessair 0:f269e3021894 146 __O uint32_t SUB_SECOND :1; /**<Write 1 to this register to clear the sub-second interrupt.*/
elessair 0:f269e3021894 147 __O uint32_t SECOND :1; /**<Write 1 to this register to clear the second interrupt.*/
elessair 0:f269e3021894 148 } BITS;
elessair 0:f269e3021894 149 __O uint32_t WORD;
elessair 0:f269e3021894 150 } INT_CLEAR; /* 0x4000F018 */
elessair 0:f269e3021894 151 #endif /* REVD */
elessair 0:f269e3021894 152 } RtcReg_t, *RtcReg_pt;
elessair 0:f269e3021894 153
elessair 0:f269e3021894 154 #endif /* RTC_MAP_H_ */